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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: deprecated.h 1724 2008-07-30 21:31:33Z arcanum $ */ #ifndef _COMPAT_DEPRECATED_H_ #define _COMPAT_DEPRECATED_H_ /** \defgroup deprecated_items : Deprecated items This header file contains several items that used to be available in previous versions of this library, but have eventually been deprecated over time. \code #include \endcode These items are supplied within that header file for backward compatibility reasons only, so old source code that has been written for previous library versions could easily be maintained until its end-of-life. Use of any of these items in new code is strongly discouraged. */ /** \name Allowing specific system-wide interrupts In addition to globally enabling interrupts, each device's particular interrupt needs to be enabled separately if interrupts for this device are desired. While some devices maintain their interrupt enable bit inside the device's register set, external and timer interrupts have system-wide configuration registers. Example: \code // Enable timer 1 overflow interrupts. timer_enable_int(_BV(TOIE1)); // Do some work... // Disable all timer interrupts. timer_enable_int(0); \endcode \note Be careful when you use these functions. If you already have a different interrupt enabled, you could inadvertantly disable it by enabling another intterupt. */ /*@{*/ /** \ingroup deprecated_items \def enable_external_int(mask) \deprecated This macro gives access to the \c GIMSK register (or \c EIMSK register if using an AVR Mega device or \c GICR register for others). Although this macro is essentially the same as assigning to the register, it does adapt slightly to the type of device being used. This macro is unavailable if none of the registers listed above are defined. */ /* Define common register definition if available. */ #if defined(EIMSK) # define __EICR EIMSK #elif defined(GIMSK) # define __EICR GIMSK #elif defined(GICR) # define __EICR GICR #endif /* If common register defined, define macro. */ #if defined(__EICR) || defined(__DOXYGEN__) #define enable_external_int(mask) (__EICR = mask) #endif /** \ingroup deprecated_items \deprecated This function modifies the \c timsk register. The value you pass via \c ints is device specific. */ static __inline__ void timer_enable_int (unsigned char ints) { #ifdef TIMSK TIMSK = ints; #endif } /** \def INTERRUPT(signame) \ingroup deprecated_items \deprecated Introduces an interrupt handler function that runs with global interrupts initially enabled. This allows interrupt handlers to be interrupted. As this macro has been used by too many unsuspecting people in the past, it has been deprecated, and will be removed in a future version of the library. Users who want to legitimately re-enable interrupts in their interrupt handlers as quickly as possible are encouraged to explicitly declare their handlers as described \ref attr_interrupt "above". */ #if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4) # define __INTR_ATTRS used, externally_visible #else /* GCC < 4.1 */ # define __INTR_ATTRS used #endif #ifdef __cplusplus #define INTERRUPT(signame) \ extern "C" void signame(void); \ void signame (void) __attribute__ ((interrupt,__INTR_ATTRS)); \ void signame (void) #else #define INTERRUPT(signame) \ void signame (void) __attribute__ ((interrupt,__INTR_ATTRS)); \ void signame (void) #endif /*@}*/ /** \name Obsolete IO macros Back in a time when AVR-GCC and avr-libc could not handle IO port access in the direct assignment form as they are handled now, all IO port access had to be done through specific macros that eventually resulted in inline assembly instructions performing the desired action. These macros became obsolete, as reading and writing IO ports can be done by simply using the IO port name in an expression, and all bit manipulation (including those on IO ports) can be done using generic C bit manipulation operators. The macros in this group simulate the historical behaviour. While they are supposed to be applied to IO ports, the emulation actually uses standard C methods, so they could be applied to arbitrary memory locations as well. */ /*@{*/ /** \ingroup deprecated_items \def inp(port) \deprecated Read a value from an IO port \c port. */ #define inp(port) (port) /** \ingroup deprecated_items \def outp(val, port) \deprecated Write \c val to IO port \c port. */ #define outp(val, port) (port) = (val) /** \ingroup deprecated_items \def inb(port) \deprecated Read a value from an IO port \c port. */ #define inb(port) (port) /** \ingroup deprecated_items \def outb(port, val) \deprecated Write \c val to IO port \c port. */ #define outb(port, val) (port) = (val) /** \ingroup deprecated_items \def sbi(port, bit) \deprecated Set \c bit in IO port \c port. */ #define sbi(port, bit) (port) |= (1 << (bit)) /** \ingroup deprecated_items \def cbi(port, bit) \deprecated Clear \c bit in IO port \c port. */ #define cbi(port, bit) (port) &= ~(1 << (bit)) /*@}*/ #endif /* _COMPAT_DEPRECATED_H_ */ avr-libc-1.8.0.orig/include/compat/twi.h0000644000000000000000000000325411732702554014740 0ustar /* Copyright (c) 2005 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: twi.h 933 2005-11-05 22:23:16Z joerg_wunsch $ */ #ifndef _COMPAT_TWI_H_ #define _COMPAT_TWI_H_ #include #endif /* _COMPAT_TWI_H_ */ avr-libc-1.8.0.orig/include/compat/ina90.h0000644000000000000000000000702211732702554015052 0ustar /* Copyright (c) 2002,2004 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ina90.h 932 2005-11-05 21:22:33Z joerg_wunsch $ */ /* copied from: Id: avr/ina90.h,v 1.8 2004/11/09 19:16:09 arcanum Exp */ /* ina90.h Contributors: Created by Marek Michalkiewicz */ /** \defgroup compat_ina90 : Compatibility with IAR EWB 3.x \code #include \endcode This is an attempt to provide some compatibility with header files that come with IAR C, to make porting applications between different compilers easier. No 100% compatibility though. \note For actual documentation, please see the IAR manual. */ #ifndef _INA90_H_ #define _INA90_H_ 1 #define _CLI() do { __asm__ __volatile__ ("cli"); } while (0) #define _SEI() do { __asm__ __volatile__ ("sei"); } while (0) #define _NOP() do { __asm__ __volatile__ ("nop"); } while (0) #define _WDR() do { __asm__ __volatile__ ("wdr"); } while (0) #define _SLEEP() do { __asm__ __volatile__ ("sleep"); } while (0) #define _OPC(op) do { __asm__ __volatile__ (".word %0" : : "n" (op)); } while (0) /* _LPM, _ELPM */ #include #define _LPM(x) do { __LPM(x); } while (0) #define _ELPM(x) do { __ELPM(x); } while (0) /* _EEGET, _EEPUT */ #include #define input(port) (port) #define output(port, val) do { (port) = (val); } while (0) #define __inp_blk__(port, addr, cnt, op) do { \ unsigned char __i = (cnt); \ unsigned char *__addr = (addr); \ while (__i) { \ *(__addr op) = input(port); \ __i--; \ } \ } while (0) #define input_block_inc(port, addr, cnt) __inp_blk__(port, addr, cnt, ++) #define input_block_dec(port, addr, cnt) __inp_blk__(port, addr, cnt, --) #define __out_blk__(port, addr, cnt, op) do { \ unsigned char __i = (cnt); \ const unsigned char *__addr = (addr); \ while (__i) { \ output(port, *(__addr op)); \ __i--; \ } \ } while (0) #define output_block_inc(port, addr, cnt) __out_blk__(port, addr, cnt, ++) #define output_block_dec(port, addr, cnt) __out_blk__(port, addr, cnt, --) #endif avr-libc-1.8.0.orig/include/compat/Makefile.am0000644000000000000000000000324311732702554016016 0ustar # Copyright (c) 2005, Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 930 2005-11-04 23:04:32Z joerg_wunsch $ # avrdir = $(prefix)/avr/include/compat avr_HEADERS = \ deprecated.h \ ina90.h \ twi.h avr-libc-1.8.0.orig/include/errno.h0000644000000000000000000000476411732702554014006 0ustar /* Copyright (c) 2002,2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: errno.h 1196 2007-01-23 15:34:58Z joerg_wunsch $ */ #ifndef __ERRNO_H_ #define __ERRNO_H_ 1 /** \file */ /** \defgroup avr_errno : System Errors \code #include \endcode Some functions in the library set the global variable \c errno when an error occurs. The file, \c , provides symbolic names for various error codes. \warning The \c errno global variable is not safe to use in a threaded or multi-task system. A race condition can occur if a task is interrupted between the call which sets \c error and when the task examines \c errno. If another task changes \c errno during this time, the result will be incorrect for the interrupted task. */ #ifdef __cplusplus extern "C" { #endif extern int errno; #ifdef __cplusplus } #endif /** \ingroup avr_errno \def EDOM Domain error. */ #define EDOM 33 /** \ingroup avr_errno \def ERANGE Range error. */ #define ERANGE 34 #endif avr-libc-1.8.0.orig/include/stdlib.h0000644000000000000000000005404411732702554014136 0ustar /* Copyright (c) 2002, Marek Michalkiewicz Copyright (c) 2004,2007 Joerg Wunsch Portions of documentation Copyright (c) 1990, 1991, 1993, 1994 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. $Id: stdlib.h 1623 2008-03-16 13:44:45Z dmix $ */ #ifndef _STDLIB_H_ #define _STDLIB_H_ 1 #ifndef __ASSEMBLER__ #define __need_NULL #define __need_size_t #define __need_wchar_t #include #ifndef __ptr_t #define __ptr_t void * #endif #ifdef __cplusplus extern "C" { #endif /** \file */ /** \defgroup avr_stdlib : General utilities \code #include \endcode This file declares some basic C macros and functions as defined by the ISO standard, plus some AVR-specific extensions. */ /*@{*/ /** Result type for function div(). */ typedef struct { int quot; /**< The Quotient. */ int rem; /**< The Remainder. */ } div_t; /** Result type for function ldiv(). */ typedef struct { long quot; /**< The Quotient. */ long rem; /**< The Remainder. */ } ldiv_t; /** Comparision function type for qsort(), just for convenience. */ typedef int (*__compar_fn_t)(const void *, const void *); #ifndef __DOXYGEN__ #ifndef __ATTR_CONST__ #define __ATTR_CONST__ __attribute__((__const__)) #endif #ifndef __ATTR_MALLOC__ #define __ATTR_MALLOC__ __attribute__((__malloc__)) #endif #ifndef __ATTR_NORETURN__ #define __ATTR_NORETURN__ __attribute__((__noreturn__)) #endif #ifndef __ATTR_PURE__ #define __ATTR_PURE__ __attribute__((__pure__)) #endif #endif /** The abort() function causes abnormal program termination to occur. This realization disables interrupts and jumps to _exit() function with argument equal to 1. In the limited AVR environment, execution is effectively halted by entering an infinite loop. */ extern void abort(void) __ATTR_NORETURN__; /** The abs() function computes the absolute value of the integer \c i. \note The abs() and labs() functions are builtins of gcc. */ extern int abs(int __i) __ATTR_CONST__; #ifndef __DOXYGEN__ #define abs(__i) __builtin_abs(__i) #endif /** The labs() function computes the absolute value of the long integer \c i. \note The abs() and labs() functions are builtins of gcc. */ extern long labs(long __i) __ATTR_CONST__; #ifndef __DOXYGEN__ #define labs(__i) __builtin_labs(__i) #endif /** The bsearch() function searches an array of \c nmemb objects, the initial member of which is pointed to by \c base, for a member that matches the object pointed to by \c key. The size of each member of the array is specified by \c size. The contents of the array should be in ascending sorted order according to the comparison function referenced by \c compar. The \c compar routine is expected to have two arguments which point to the key object and to an array member, in that order, and should return an integer less than, equal to, or greater than zero if the key object is found, respectively, to be less than, to match, or be greater than the array member. The bsearch() function returns a pointer to a matching member of the array, or a null pointer if no match is found. If two members compare as equal, which member is matched is unspecified. */ extern void *bsearch(const void *__key, const void *__base, size_t __nmemb, size_t __size, int (*__compar)(const void *, const void *)); /* __divmodhi4 and __divmodsi4 from libgcc.a */ /** The div() function computes the value \c num/denom and returns the quotient and remainder in a structure named \c div_t that contains two int members named \c quot and \c rem. */ extern div_t div(int __num, int __denom) __asm__("__divmodhi4") __ATTR_CONST__; /** The ldiv() function computes the value \c num/denom and returns the quotient and remainder in a structure named \c ldiv_t that contains two long integer members named \c quot and \c rem. */ extern ldiv_t ldiv(long __num, long __denom) __asm__("__divmodsi4") __ATTR_CONST__; /** The qsort() function is a modified partition-exchange sort, or quicksort. The qsort() function sorts an array of \c nmemb objects, the initial member of which is pointed to by \c base. The size of each object is specified by \c size. The contents of the array base are sorted in ascending order according to a comparison function pointed to by \c compar, which requires two arguments pointing to the objects being compared. The comparison function must return an integer less than, equal to, or greater than zero if the first argument is considered to be respectively less than, equal to, or greater than the second. */ extern void qsort(void *__base, size_t __nmemb, size_t __size, __compar_fn_t __compar); /** The strtol() function converts the string in \c nptr to a long value. The conversion is done according to the given base, which must be between 2 and 36 inclusive, or be the special value 0. The string may begin with an arbitrary amount of white space (as determined by isspace()) followed by a single optional \c '+' or \c '-' sign. If \c base is zero or 16, the string may then include a \c "0x" prefix, and the number will be read in base 16; otherwise, a zero base is taken as 10 (decimal) unless the next character is \c '0', in which case it is taken as 8 (octal). The remainder of the string is converted to a long value in the obvious manner, stopping at the first character which is not a valid digit in the given base. (In bases above 10, the letter \c 'A' in either upper or lower case represents 10, \c 'B' represents 11, and so forth, with \c 'Z' representing 35.) If \c endptr is not NULL, strtol() stores the address of the first invalid character in \c *endptr. If there were no digits at all, however, strtol() stores the original value of \c nptr in \c *endptr. (Thus, if \c *nptr is not \c '\\0' but \c **endptr is \c '\\0' on return, the entire string was valid.) The strtol() function returns the result of the conversion, unless the value would underflow or overflow. If no conversion could be performed, 0 is returned. If an overflow or underflow occurs, \c errno is set to \ref avr_errno "ERANGE" and the function return value is clamped to \c LONG_MIN or \c LONG_MAX, respectively. */ extern long strtol(const char *__nptr, char **__endptr, int __base); /** The strtoul() function converts the string in \c nptr to an unsigned long value. The conversion is done according to the given base, which must be between 2 and 36 inclusive, or be the special value 0. The string may begin with an arbitrary amount of white space (as determined by isspace()) followed by a single optional \c '+' or \c '-' sign. If \c base is zero or 16, the string may then include a \c "0x" prefix, and the number will be read in base 16; otherwise, a zero base is taken as 10 (decimal) unless the next character is \c '0', in which case it is taken as 8 (octal). The remainder of the string is converted to an unsigned long value in the obvious manner, stopping at the first character which is not a valid digit in the given base. (In bases above 10, the letter \c 'A' in either upper or lower case represents 10, \c 'B' represents 11, and so forth, with \c 'Z' representing 35.) If \c endptr is not NULL, strtoul() stores the address of the first invalid character in \c *endptr. If there were no digits at all, however, strtoul() stores the original value of \c nptr in \c *endptr. (Thus, if \c *nptr is not \c '\\0' but \c **endptr is \c '\\0' on return, the entire string was valid.) The strtoul() function return either the result of the conversion or, if there was a leading minus sign, the negation of the result of the conversion, unless the original (non-negated) value would overflow; in the latter case, strtoul() returns ULONG_MAX, and \c errno is set to \ref avr_errno "ERANGE". If no conversion could be performed, 0 is returned. */ extern unsigned long strtoul(const char *__nptr, char **__endptr, int __base); /** The atol() function converts the initial portion of the string pointed to by \p s to long integer representation. In contrast to \code strtol(s, (char **)NULL, 10); \endcode this function does not detect overflow (\c errno is not changed and the result value is not predictable), uses smaller memory (flash and stack) and works more quickly. */ extern long atol(const char *__s) __ATTR_PURE__; /** The atoi() function converts the initial portion of the string pointed to by \p s to integer representation. In contrast to \code (int)strtol(s, (char **)NULL, 10); \endcode this function does not detect overflow (\c errno is not changed and the result value is not predictable), uses smaller memory (flash and stack) and works more quickly. */ extern int atoi(const char *__s) __ATTR_PURE__; /** The exit() function terminates the application. Since there is no environment to return to, \c status is ignored, and code execution will eventually reach an infinite loop, thereby effectively halting all code processing. Before entering the infinite loop, interrupts are globally disabled. In a C++ context, global destructors will be called before halting execution. */ extern void exit(int __status) __ATTR_NORETURN__; /** The malloc() function allocates \c size bytes of memory. If malloc() fails, a NULL pointer is returned. Note that malloc() does \e not initialize the returned memory to zero bytes. See the chapter about \ref malloc "malloc() usage" for implementation details. */ extern void *malloc(size_t __size) __ATTR_MALLOC__; /** The free() function causes the allocated memory referenced by \c ptr to be made available for future allocations. If \c ptr is NULL, no action occurs. */ extern void free(void *__ptr); /** \c malloc() \ref malloc_tunables "tunable". */ extern size_t __malloc_margin; /** \c malloc() \ref malloc_tunables "tunable". */ extern char *__malloc_heap_start; /** \c malloc() \ref malloc_tunables "tunable". */ extern char *__malloc_heap_end; /** Allocate \c nele elements of \c size each. Identical to calling \c malloc() using nele * size as argument, except the allocated memory will be cleared to zero. */ extern void *calloc(size_t __nele, size_t __size) __ATTR_MALLOC__; /** The realloc() function tries to change the size of the region allocated at \c ptr to the new \c size value. It returns a pointer to the new region. The returned pointer might be the same as the old pointer, or a pointer to a completely different region. The contents of the returned region up to either the old or the new size value (whatever is less) will be identical to the contents of the old region, even in case a new region had to be allocated. It is acceptable to pass \c ptr as NULL, in which case realloc() will behave identical to malloc(). If the new memory cannot be allocated, realloc() returns NULL, and the region at \c ptr will not be changed. */ extern void *realloc(void *__ptr, size_t __size) __ATTR_MALLOC__; extern double strtod(const char *__nptr, char **__endptr); extern double atof(const char *__nptr); /** Highest number that can be generated by rand(). */ #define RAND_MAX 0x7FFF /** The rand() function computes a sequence of pseudo-random integers in the range of 0 to \c RAND_MAX (as defined by the header file ). The srand() function sets its argument \c seed as the seed for a new sequence of pseudo-random numbers to be returned by rand(). These sequences are repeatable by calling srand() with the same seed value. If no seed value is provided, the functions are automatically seeded with a value of 1. In compliance with the C standard, these functions operate on \c int arguments. Since the underlying algorithm already uses 32-bit calculations, this causes a loss of precision. See \c random() for an alternate set of functions that retains full 32-bit precision. */ extern int rand(void); /** Pseudo-random number generator seeding; see rand(). */ extern void srand(unsigned int __seed); /** Variant of rand() that stores the context in the user-supplied variable located at \c ctx instead of a static library variable so the function becomes re-entrant. */ extern int rand_r(unsigned long *__ctx); /*@}*/ /*@{*/ /** \name Non-standard (i.e. non-ISO C) functions. \ingroup avr_stdlib */ /** \brief Convert an integer to a string. The function itoa() converts the integer value from \c val into an ASCII representation that will be stored under \c s. The caller is responsible for providing sufficient storage in \c s. \note The minimal size of the buffer \c s depends on the choice of radix. For example, if the radix is 2 (binary), you need to supply a buffer with a minimal length of 8 * sizeof (int) + 1 characters, i.e. one character for each bit plus one for the string terminator. Using a larger radix will require a smaller minimal buffer size. \warning If the buffer is too small, you risk a buffer overflow. Conversion is done using the \c radix as base, which may be a number between 2 (binary conversion) and up to 36. If \c radix is greater than 10, the next digit after \c '9' will be the letter \c 'a'. If radix is 10 and val is negative, a minus sign will be prepended. The itoa() function returns the pointer passed as \c s. */ extern char *itoa(int __val, char *__s, int __radix); /** \ingroup avr_stdlib \brief Convert a long integer to a string. The function ltoa() converts the long integer value from \c val into an ASCII representation that will be stored under \c s. The caller is responsible for providing sufficient storage in \c s. \note The minimal size of the buffer \c s depends on the choice of radix. For example, if the radix is 2 (binary), you need to supply a buffer with a minimal length of 8 * sizeof (long int) + 1 characters, i.e. one character for each bit plus one for the string terminator. Using a larger radix will require a smaller minimal buffer size. \warning If the buffer is too small, you risk a buffer overflow. Conversion is done using the \c radix as base, which may be a number between 2 (binary conversion) and up to 36. If \c radix is greater than 10, the next digit after \c '9' will be the letter \c 'a'. If radix is 10 and val is negative, a minus sign will be prepended. The ltoa() function returns the pointer passed as \c s. */ extern char *ltoa(long int __val, char *__s, int __radix); /** \ingroup avr_stdlib \brief Convert an unsigned integer to a string. The function utoa() converts the unsigned integer value from \c val into an ASCII representation that will be stored under \c s. The caller is responsible for providing sufficient storage in \c s. \note The minimal size of the buffer \c s depends on the choice of radix. For example, if the radix is 2 (binary), you need to supply a buffer with a minimal length of 8 * sizeof (unsigned int) + 1 characters, i.e. one character for each bit plus one for the string terminator. Using a larger radix will require a smaller minimal buffer size. \warning If the buffer is too small, you risk a buffer overflow. Conversion is done using the \c radix as base, which may be a number between 2 (binary conversion) and up to 36. If \c radix is greater than 10, the next digit after \c '9' will be the letter \c 'a'. The utoa() function returns the pointer passed as \c s. */ extern char *utoa(unsigned int __val, char *__s, int __radix); /** \ingroup avr_stdlib \brief Convert an unsigned long integer to a string. The function ultoa() converts the unsigned long integer value from \c val into an ASCII representation that will be stored under \c s. The caller is responsible for providing sufficient storage in \c s. \note The minimal size of the buffer \c s depends on the choice of radix. For example, if the radix is 2 (binary), you need to supply a buffer with a minimal length of 8 * sizeof (unsigned long int) + 1 characters, i.e. one character for each bit plus one for the string terminator. Using a larger radix will require a smaller minimal buffer size. \warning If the buffer is too small, you risk a buffer overflow. Conversion is done using the \c radix as base, which may be a number between 2 (binary conversion) and up to 36. If \c radix is greater than 10, the next digit after \c '9' will be the letter \c 'a'. The ultoa() function returns the pointer passed as \c s. */ extern char *ultoa(unsigned long int __val, char *__s, int __radix); /** \ingroup avr_stdlib Highest number that can be generated by random(). */ #define RANDOM_MAX 0x7FFFFFFF /** \ingroup avr_stdlib The random() function computes a sequence of pseudo-random integers in the range of 0 to \c RANDOM_MAX (as defined by the header file ). The srandom() function sets its argument \c seed as the seed for a new sequence of pseudo-random numbers to be returned by rand(). These sequences are repeatable by calling srandom() with the same seed value. If no seed value is provided, the functions are automatically seeded with a value of 1. */ extern long random(void); /** \ingroup avr_stdlib Pseudo-random number generator seeding; see random(). */ extern void srandom(unsigned long __seed); /** \ingroup avr_stdlib Variant of random() that stores the context in the user-supplied variable located at \c ctx instead of a static library variable so the function becomes re-entrant. */ extern long random_r(unsigned long *__ctx); #endif /* __ASSEMBLER */ /*@}*/ /*@{*/ /** \name Conversion functions for double arguments. \ingroup avr_stdlib Note that these functions are not located in the default library, libc.a, but in the mathematical library, libm.a. So when linking the application, the \c -lm option needs to be specified. */ /** \ingroup avr_stdlib Bit value that can be passed in \c flags to dtostre(). */ #define DTOSTR_ALWAYS_SIGN 0x01 /* put '+' or ' ' for positives */ /** \ingroup avr_stdlib Bit value that can be passed in \c flags to dtostre(). */ #define DTOSTR_PLUS_SIGN 0x02 /* put '+' rather than ' ' */ /** \ingroup avr_stdlib Bit value that can be passed in \c flags to dtostre(). */ #define DTOSTR_UPPERCASE 0x04 /* put 'E' rather 'e' */ #ifndef __ASSEMBLER__ /** \ingroup avr_stdlib The dtostre() function converts the double value passed in \c val into an ASCII representation that will be stored under \c s. The caller is responsible for providing sufficient storage in \c s. Conversion is done in the format \c "[-]d.dddeħdd" where there is one digit before the decimal-point character and the number of digits after it is equal to the precision \c prec; if the precision is zero, no decimal-point character appears. If \c flags has the DTOSTRE_UPPERCASE bit set, the letter \c 'E' (rather than \c 'e' ) will be used to introduce the exponent. The exponent always contains two digits; if the value is zero, the exponent is \c "00". If \c flags has the DTOSTRE_ALWAYS_SIGN bit set, a space character will be placed into the leading position for positive numbers. If \c flags has the DTOSTRE_PLUS_SIGN bit set, a plus sign will be used instead of a space character in this case. The dtostre() function returns the pointer to the converted string \c s. */ extern char *dtostre(double __val, char *__s, unsigned char __prec, unsigned char __flags); /** \ingroup avr_stdlib The dtostrf() function converts the double value passed in \c val into an ASCII representationthat will be stored under \c s. The caller is responsible for providing sufficient storage in \c s. Conversion is done in the format \c "[-]d.ddd". The minimum field width of the output string (including the \c '.' and the possible sign for negative values) is given in \c width, and \c prec determines the number of digits after the decimal sign. \c width is signed value, negative for left adjustment. The dtostrf() function returns the pointer to the converted string \c s. */ extern char *dtostrf(double __val, signed char __width, unsigned char __prec, char *__s); /*@}*/ #if 0 /* not yet implemented */ extern int atexit(void (*)(void)); #endif #ifdef __cplusplus } #endif #endif /* __ASSEMBLER */ #endif /* _STDLIB_H_ */ avr-libc-1.8.0.orig/include/assert.h0000644000000000000000000000707211732702554014155 0ustar /* Copyright (c) 2005,2007 Joerg Wunsch All rights reserved. Portions of documentation Copyright (c) 1991, 1993 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. $Id: assert.h 1196 2007-01-23 15:34:58Z joerg_wunsch $ */ /** \file */ /** \defgroup avr_assert : Diagnostics \code #include \endcode This header file defines a debugging aid. As there is no standard error output stream available for many applications using this library, the generation of a printable error message is not enabled by default. These messages will only be generated if the application defines the macro \code __ASSERT_USE_STDERR \endcode before including the \c header file. By default, only abort() will be called to halt the application. */ /*@{*/ /* * The ability to include this file (with or without NDEBUG) is a * feature. */ #undef assert #if defined(__DOXYGEN__) /** * \def assert * \param expression Expression to test for. * * The assert() macro tests the given expression and if it is false, * the calling process is terminated. A diagnostic message is written * to stderr and the function abort() is called, effectively * terminating the program. * * If expression is true, the assert() macro does nothing. * * The assert() macro may be removed at compile time by defining * NDEBUG as a macro (e.g., by using the compiler option -DNDEBUG). */ # define assert(expression) #else /* !DOXYGEN */ # if defined(NDEBUG) # define assert(e) ((void)0) # else /* !NDEBUG */ # if defined(__ASSERT_USE_STDERR) # define assert(e) ((e) ? (void)0 : \ __assert(__func__, __FILE__, __LINE__, #e)) # else /* !__ASSERT_USE_STDERR */ # define assert(e) ((e) ? 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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: stdint.h 2261 2011-12-09 07:05:46Z joerg_wunsch $ */ /* * ISO/IEC 9899:1999 7.18 Integer types */ #ifndef __STDINT_H_ #define __STDINT_H_ /** \file */ /** \defgroup avr_stdint : Standard Integer Types \code #include \endcode Use [u]intN_t if you need exactly N bits. Since these typedefs are mandated by the C99 standard, they are preferred over rolling your own typedefs. */ /* * __USING_MINT8 is defined to 1 if the -mint8 option is in effect. */ #if __INT_MAX__ == 127 # define __USING_MINT8 1 #else # define __USING_MINT8 0 #endif /* Integer types */ #if defined(__DOXYGEN__) /* doxygen gets confused by the __attribute__ stuff */ /** \name Exact-width integer types Integer types having exactly the specified width */ /*@{*/ /** \ingroup avr_stdint 8-bit signed type. */ typedef signed char int8_t; /** \ingroup avr_stdint 8-bit unsigned type. */ typedef unsigned char uint8_t; /** \ingroup avr_stdint 16-bit signed type. */ typedef signed int int16_t; /** \ingroup avr_stdint 16-bit unsigned type. */ typedef unsigned int uint16_t; /** \ingroup avr_stdint 32-bit signed type. */ typedef signed long int int32_t; /** \ingroup avr_stdint 32-bit unsigned type. */ typedef unsigned long int uint32_t; /** \ingroup avr_stdint 64-bit signed type. \note This type is not available when the compiler option -mint8 is in effect. */ typedef signed long long int int64_t; /** \ingroup avr_stdint 64-bit unsigned type. \note This type is not available when the compiler option -mint8 is in effect. */ typedef unsigned long long int uint64_t; /*@}*/ #else /* !defined(__DOXYGEN__) */ /* actual implementation goes here */ typedef signed int int8_t __attribute__((__mode__(__QI__))); typedef unsigned int uint8_t __attribute__((__mode__(__QI__))); typedef signed int int16_t __attribute__ ((__mode__ (__HI__))); typedef unsigned int uint16_t __attribute__ ((__mode__ (__HI__))); typedef signed int int32_t __attribute__ ((__mode__ (__SI__))); typedef unsigned int uint32_t __attribute__ ((__mode__ (__SI__))); #if !__USING_MINT8 typedef signed int int64_t __attribute__((__mode__(__DI__))); typedef unsigned int uint64_t __attribute__((__mode__(__DI__))); #endif #endif /* defined(__DOXYGEN__) */ /** \name Integer types capable of holding object pointers These allow you to declare variables of the same size as a pointer. */ /*@{*/ /** \ingroup avr_stdint Signed pointer compatible type. */ typedef int16_t intptr_t; /** \ingroup avr_stdint Unsigned pointer compatible type. */ typedef uint16_t uintptr_t; /*@}*/ /** \name Minimum-width integer types Integer types having at least the specified width */ /*@{*/ /** \ingroup avr_stdint signed int with at least 8 bits. */ typedef int8_t int_least8_t; /** \ingroup avr_stdint unsigned int with at least 8 bits. */ typedef uint8_t uint_least8_t; /** \ingroup avr_stdint signed int with at least 16 bits. */ typedef int16_t int_least16_t; /** \ingroup avr_stdint unsigned int with at least 16 bits. */ typedef uint16_t uint_least16_t; /** \ingroup avr_stdint signed int with at least 32 bits. */ typedef int32_t int_least32_t; /** \ingroup avr_stdint unsigned int with at least 32 bits. */ typedef uint32_t uint_least32_t; #if !__USING_MINT8 || defined(__DOXYGEN__) /** \ingroup avr_stdint signed int with at least 64 bits. \note This type is not available when the compiler option -mint8 is in effect. */ typedef int64_t int_least64_t; /** \ingroup avr_stdint unsigned int with at least 64 bits. \note This type is not available when the compiler option -mint8 is in effect. */ typedef uint64_t uint_least64_t; #endif /*@}*/ /** \name Fastest minimum-width integer types Integer types being usually fastest having at least the specified width */ /*@{*/ /** \ingroup avr_stdint fastest signed int with at least 8 bits. */ typedef int8_t int_fast8_t; /** \ingroup avr_stdint fastest unsigned int with at least 8 bits. */ typedef uint8_t uint_fast8_t; /** \ingroup avr_stdint fastest signed int with at least 16 bits. */ typedef int16_t int_fast16_t; /** \ingroup avr_stdint fastest unsigned int with at least 16 bits. */ typedef uint16_t uint_fast16_t; /** \ingroup avr_stdint fastest signed int with at least 32 bits. */ typedef int32_t int_fast32_t; /** \ingroup avr_stdint fastest unsigned int with at least 32 bits. */ typedef uint32_t uint_fast32_t; #if !__USING_MINT8 || defined(__DOXYGEN__) /** \ingroup avr_stdint fastest signed int with at least 64 bits. \note This type is not available when the compiler option -mint8 is in effect. */ typedef int64_t int_fast64_t; /** \ingroup avr_stdint fastest unsigned int with at least 64 bits. \note This type is not available when the compiler option -mint8 is in effect. */ typedef uint64_t uint_fast64_t; #endif /*@}*/ /** \name Greatest-width integer types Types designating integer data capable of representing any value of any integer type in the corresponding signed or unsigned category */ /*@{*/ #if __USING_MINT8 typedef int32_t intmax_t; typedef uint32_t uintmax_t; #else /* !__USING_MINT8 */ /** \ingroup avr_stdint largest signed int available. */ typedef int64_t intmax_t; /** \ingroup avr_stdint largest unsigned int available. */ typedef uint64_t uintmax_t; #endif /* __USING_MINT8 */ /*@}*/ /* Helping macro */ #ifndef __CONCAT #define __CONCATenate(left, right) left ## right #define __CONCAT(left, right) __CONCATenate(left, right) #endif #if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) /** \name Limits of specified-width integer types C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included */ /*@{*/ /** \ingroup avr_stdint largest positive value an int8_t can hold. */ #define INT8_MAX 0x7f /** \ingroup avr_stdint smallest negative value an int8_t can hold. */ #define INT8_MIN (-INT8_MAX - 1) /** \ingroup avr_stdint largest value an uint8_t can hold. */ #define UINT8_MAX (__CONCAT(INT8_MAX, U) * 2U + 1U) #if __USING_MINT8 #define INT16_MAX 0x7fffL #define INT16_MIN (-INT16_MAX - 1L) #define UINT16_MAX (__CONCAT(INT16_MAX, U) * 2UL + 1UL) #define INT32_MAX 0x7fffffffLL #define INT32_MIN (-INT32_MAX - 1LL) #define UINT32_MAX (__CONCAT(INT32_MAX, U) * 2ULL + 1ULL) #else /* !__USING_MINT8 */ /** \ingroup avr_stdint largest positive value an int16_t can hold. */ #define INT16_MAX 0x7fff /** \ingroup avr_stdint smallest negative value an int16_t can hold. */ #define INT16_MIN (-INT16_MAX - 1) /** \ingroup avr_stdint largest value an uint16_t can hold. */ #define UINT16_MAX (__CONCAT(INT16_MAX, U) * 2U + 1U) /** \ingroup avr_stdint largest positive value an int32_t can hold. */ #define INT32_MAX 0x7fffffffL /** \ingroup avr_stdint smallest negative value an int32_t can hold. */ #define INT32_MIN (-INT32_MAX - 1L) /** \ingroup avr_stdint largest value an uint32_t can hold. */ #define UINT32_MAX (__CONCAT(INT32_MAX, U) * 2UL + 1UL) #endif /* __USING_MINT8 */ /** \ingroup avr_stdint largest positive value an int64_t can hold. */ #define INT64_MAX 0x7fffffffffffffffLL /** \ingroup avr_stdint smallest negative value an int64_t can hold. */ #define INT64_MIN (-INT64_MAX - 1LL) /** \ingroup avr_stdint largest value an uint64_t can hold. */ #define UINT64_MAX (__CONCAT(INT64_MAX, U) * 2ULL + 1ULL) /*@}*/ /** \name Limits of minimum-width integer types */ /*@{*/ /** \ingroup avr_stdint largest positive value an int_least8_t can hold. */ #define INT_LEAST8_MAX INT8_MAX /** \ingroup avr_stdint smallest negative value an int_least8_t can hold. */ #define INT_LEAST8_MIN INT8_MIN /** \ingroup avr_stdint largest value an uint_least8_t can hold. */ #define UINT_LEAST8_MAX UINT8_MAX /** \ingroup avr_stdint largest positive value an int_least16_t can hold. */ #define INT_LEAST16_MAX INT16_MAX /** \ingroup avr_stdint smallest negative value an int_least16_t can hold. */ #define INT_LEAST16_MIN INT16_MIN /** \ingroup avr_stdint largest value an uint_least16_t can hold. */ #define UINT_LEAST16_MAX UINT16_MAX /** \ingroup avr_stdint largest positive value an int_least32_t can hold. */ #define INT_LEAST32_MAX INT32_MAX /** \ingroup avr_stdint smallest negative value an int_least32_t can hold. */ #define INT_LEAST32_MIN INT32_MIN /** \ingroup avr_stdint largest value an uint_least32_t can hold. */ #define UINT_LEAST32_MAX UINT32_MAX /** \ingroup avr_stdint largest positive value an int_least64_t can hold. */ #define INT_LEAST64_MAX INT64_MAX /** \ingroup avr_stdint smallest negative value an int_least64_t can hold. */ #define INT_LEAST64_MIN INT64_MIN /** \ingroup avr_stdint largest value an uint_least64_t can hold. */ #define UINT_LEAST64_MAX UINT64_MAX /*@}*/ /** \name Limits of fastest minimum-width integer types */ /*@{*/ /** \ingroup avr_stdint largest positive value an int_fast8_t can hold. */ #define INT_FAST8_MAX INT8_MAX /** \ingroup avr_stdint smallest negative value an int_fast8_t can hold. */ #define INT_FAST8_MIN INT8_MIN /** \ingroup avr_stdint largest value an uint_fast8_t can hold. */ #define UINT_FAST8_MAX UINT8_MAX /** \ingroup avr_stdint largest positive value an int_fast16_t can hold. */ #define INT_FAST16_MAX INT16_MAX /** \ingroup avr_stdint smallest negative value an int_fast16_t can hold. */ #define INT_FAST16_MIN INT16_MIN /** \ingroup avr_stdint largest value an uint_fast16_t can hold. */ #define UINT_FAST16_MAX UINT16_MAX /** \ingroup avr_stdint largest positive value an int_fast32_t can hold. */ #define INT_FAST32_MAX INT32_MAX /** \ingroup avr_stdint smallest negative value an int_fast32_t can hold. */ #define INT_FAST32_MIN INT32_MIN /** \ingroup avr_stdint largest value an uint_fast32_t can hold. */ #define UINT_FAST32_MAX UINT32_MAX /** \ingroup avr_stdint largest positive value an int_fast64_t can hold. */ #define INT_FAST64_MAX INT64_MAX /** \ingroup avr_stdint smallest negative value an int_fast64_t can hold. */ #define INT_FAST64_MIN INT64_MIN /** \ingroup avr_stdint largest value an uint_fast64_t can hold. */ #define UINT_FAST64_MAX UINT64_MAX /*@}*/ /** \name Limits of integer types capable of holding object pointers */ /*@{*/ /** \ingroup avr_stdint largest positive value an intptr_t can hold. */ #define INTPTR_MAX INT16_MAX /** \ingroup avr_stdint smallest negative value an intptr_t can hold. */ #define INTPTR_MIN INT16_MIN /** \ingroup avr_stdint largest value an uintptr_t can hold. */ #define UINTPTR_MAX UINT16_MAX /*@}*/ /** \name Limits of greatest-width integer types */ /*@{*/ /** \ingroup avr_stdint largest positive value an intmax_t can hold. */ #define INTMAX_MAX INT64_MAX /** \ingroup avr_stdint smallest negative value an intmax_t can hold. */ #define INTMAX_MIN INT64_MIN /** \ingroup avr_stdint largest value an uintmax_t can hold. */ #define UINTMAX_MAX UINT64_MAX /*@}*/ /** \name Limits of other integer types C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included */ /*@{*/ /** \ingroup avr_stdint largest positive value a ptrdiff_t can hold. */ #define PTRDIFF_MAX INT16_MAX /** \ingroup avr_stdint smallest negative value a ptrdiff_t can hold. */ #define PTRDIFF_MIN INT16_MIN /* Limits of sig_atomic_t */ /* signal.h is currently not implemented (not avr/signal.h) */ /** \ingroup avr_stdint largest positive value a sig_atomic_t can hold. */ #define SIG_ATOMIC_MAX INT8_MAX /** \ingroup avr_stdint smallest negative value a sig_atomic_t can hold. */ #define SIG_ATOMIC_MIN INT8_MIN /** \ingroup avr_stdint largest value a size_t can hold. */ #define SIZE_MAX (__CONCAT(INT16_MAX, U)) /* Limits of wchar_t */ /* wchar.h is currently not implemented */ /* #define WCHAR_MAX */ /* #define WCHAR_MIN */ /* Limits of wint_t */ /* wchar.h is currently not implemented */ /* #define WINT_MAX */ /* #define WINT_MIN */ #endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ #if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) /** \name Macros for integer constants C++ implementations should define these macros only when __STDC_CONSTANT_MACROS is defined before is included. These definitions are valid for integer constants without suffix and for macros defined as integer constant without suffix */ /** \ingroup avr_stdint define a constant of type int8_t */ #define INT8_C(value) ((int8_t) value) /** \ingroup avr_stdint define a constant of type uint8_t */ #define UINT8_C(value) ((uint8_t) __CONCAT(value, U)) #if __USING_MINT8 #define INT16_C(value) __CONCAT(value, L) #define UINT16_C(value) __CONCAT(value, UL) #define INT32_C(value) ((int32_t) __CONCAT(value, LL)) #define UINT32_C(value) ((uint32_t) __CONCAT(value, ULL)) #else /* !__USING_MINT8 */ /** \ingroup avr_stdint define a constant of type int16_t */ #define INT16_C(value) value /** \ingroup avr_stdint define a constant of type uint16_t */ #define UINT16_C(value) __CONCAT(value, U) /** \ingroup avr_stdint define a constant of type int32_t */ #define INT32_C(value) __CONCAT(value, L) /** \ingroup avr_stdint define a constant of type uint32_t */ #define UINT32_C(value) __CONCAT(value, UL) #endif /* __USING_MINT8 */ /** \ingroup avr_stdint define a constant of type int64_t */ #define INT64_C(value) __CONCAT(value, LL) /** \ingroup avr_stdint define a constant of type uint64_t */ #define UINT64_C(value) __CONCAT(value, ULL) /** \ingroup avr_stdint define a constant of type intmax_t */ #define INTMAX_C(value) __CONCAT(value, LL) /** \ingroup avr_stdint define a constant of type uintmax_t */ #define UINTMAX_C(value) __CONCAT(value, ULL) /*@}*/ #endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ #endif /* _STDINT_H_ */ avr-libc-1.8.0.orig/include/stdio.h0000644000000000000000000010516411732702554013777 0ustar /* Copyright (c) 2002, 2005, 2007 Joerg Wunsch All rights reserved. Portions of documentation Copyright (c) 1990, 1991, 1993 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. $Id: stdio.h 2135 2010-06-08 11:28:03Z joerg_wunsch $ */ #ifndef _STDIO_H_ #define _STDIO_H_ 1 #ifndef __ASSEMBLER__ #include #include #define __need_NULL #define __need_size_t #include /** \file */ /** \defgroup avr_stdio : Standard IO facilities \code #include \endcode

Introduction to the Standard IO facilities

This file declares the standard IO facilities that are implemented in \c avr-libc. Due to the nature of the underlying hardware, only a limited subset of standard IO is implemented. There is no actual file implementation available, so only device IO can be performed. Since there's no operating system, the application needs to provide enough details about their devices in order to make them usable by the standard IO facilities. Due to space constraints, some functionality has not been implemented at all (like some of the \c printf conversions that have been left out). Nevertheless, potential users of this implementation should be warned: the \c printf and \c scanf families of functions, although usually associated with presumably simple things like the famous "Hello, world!" program, are actually fairly complex which causes their inclusion to eat up a fair amount of code space. Also, they are not fast due to the nature of interpreting the format string at run-time. Whenever possible, resorting to the (sometimes non-standard) predetermined conversion facilities that are offered by avr-libc will usually cost much less in terms of speed and code size.

Tunable options for code size vs. feature set

In order to allow programmers a code size vs. functionality tradeoff, the function vfprintf() which is the heart of the printf family can be selected in different flavours using linker options. See the documentation of vfprintf() for a detailed description. The same applies to vfscanf() and the \c scanf family of functions.

Outline of the chosen API

The standard streams \c stdin, \c stdout, and \c stderr are provided, but contrary to the C standard, since avr-libc has no knowledge about applicable devices, these streams are not already pre-initialized at application startup. Also, since there is no notion of "file" whatsoever to avr-libc, there is no function \c fopen() that could be used to associate a stream to some device. (See \ref stdio_note1 "note 1".) Instead, the function \c fdevopen() is provided to associate a stream to a device, where the device needs to provide a function to send a character, to receive a character, or both. There is no differentiation between "text" and "binary" streams inside avr-libc. Character \c \\n is sent literally down to the device's \c put() function. If the device requires a carriage return (\c \\r) character to be sent before the linefeed, its \c put() routine must implement this (see \ref stdio_note2 "note 2"). As an alternative method to fdevopen(), the macro fdev_setup_stream() might be used to setup a user-supplied FILE structure. It should be noted that the automatic conversion of a newline character into a carriage return - newline sequence breaks binary transfers. If binary transfers are desired, no automatic conversion should be performed, but instead any string that aims to issue a CR-LF sequence must use "\r\n" explicitly. For convenience, the first call to \c fdevopen() that opens a stream for reading will cause the resulting stream to be aliased to \c stdin. Likewise, the first call to \c fdevopen() that opens a stream for writing will cause the resulting stream to be aliased to both, \c stdout, and \c stderr. Thus, if the open was done with both, read and write intent, all three standard streams will be identical. Note that these aliases are indistinguishable from each other, thus calling \c fclose() on such a stream will also effectively close all of its aliases (\ref stdio_note3 "note 3"). It is possible to tie additional user data to a stream, using fdev_set_udata(). The backend put and get functions can then extract this user data using fdev_get_udata(), and act appropriately. For example, a single put function could be used to talk to two different UARTs that way, or the put and get functions could keep internal state between calls there.

Format strings in flash ROM

All the \c printf and \c scanf family functions come in two flavours: the standard name, where the format string is expected to be in SRAM, as well as a version with the suffix "_P" where the format string is expected to reside in the flash ROM. The macro \c PSTR (explained in \ref avr_pgmspace) becomes very handy for declaring these format strings. \anchor stdio_without_malloc

Running stdio without malloc()

By default, fdevopen() requires malloc(). As this is often not desired in the limited environment of a microcontroller, an alternative option is provided to run completely without malloc(). The macro fdev_setup_stream() is provided to prepare a user-supplied FILE buffer for operation with stdio.

Example

\code #include static int uart_putchar(char c, FILE *stream); static FILE mystdout = FDEV_SETUP_STREAM(uart_putchar, NULL, _FDEV_SETUP_WRITE); static int uart_putchar(char c, FILE *stream) { if (c == '\n') uart_putchar('\r', stream); loop_until_bit_is_set(UCSRA, UDRE); UDR = c; return 0; } int main(void) { init_uart(); stdout = &mystdout; printf("Hello, world!\n"); return 0; } \endcode This example uses the initializer form FDEV_SETUP_STREAM() rather than the function-like fdev_setup_stream(), so all data initialization happens during C start-up. If streams initialized that way are no longer needed, they can be destroyed by first calling the macro fdev_close(), and then destroying the object itself. No call to fclose() should be issued for these streams. While calling fclose() itself is harmless, it will cause an undefined reference to free() and thus cause the linker to link the malloc module into the application.

Notes

\anchor stdio_note1 \par Note 1: It might have been possible to implement a device abstraction that is compatible with \c fopen() but since this would have required to parse a string, and to take all the information needed either out of this string, or out of an additional table that would need to be provided by the application, this approach was not taken. \anchor stdio_note2 \par Note 2: This basically follows the Unix approach: if a device such as a terminal needs special handling, it is in the domain of the terminal device driver to provide this functionality. Thus, a simple function suitable as \c put() for \c fdevopen() that talks to a UART interface might look like this: \code int uart_putchar(char c, FILE *stream) { if (c == '\n') uart_putchar('\r'); loop_until_bit_is_set(UCSRA, UDRE); UDR = c; return 0; } \endcode \anchor stdio_note3 \par Note 3: This implementation has been chosen because the cost of maintaining an alias is considerably smaller than the cost of maintaining full copies of each stream. Yet, providing an implementation that offers the complete set of standard streams was deemed to be useful. Not only that writing \c printf() instead of fprintf(mystream, ...) saves typing work, but since avr-gcc needs to resort to pass all arguments of variadic functions on the stack (as opposed to passing them in registers for functions that take a fixed number of parameters), the ability to pass one parameter less by implying \c stdin or stdout will also save some execution time. */ #if !defined(__DOXYGEN__) /* * This is an internal structure of the library that is subject to be * changed without warnings at any time. Please do *never* reference * elements of it beyond by using the official interfaces provided. */ struct __file { char *buf; /* buffer pointer */ unsigned char unget; /* ungetc() buffer */ uint8_t flags; /* flags, see below */ #define __SRD 0x0001 /* OK to read */ #define __SWR 0x0002 /* OK to write */ #define __SSTR 0x0004 /* this is an sprintf/snprintf string */ #define __SPGM 0x0008 /* fmt string is in progmem */ #define __SERR 0x0010 /* found error */ #define __SEOF 0x0020 /* found EOF */ #define __SUNGET 0x040 /* ungetc() happened */ #define __SMALLOC 0x80 /* handle is malloc()ed */ #if 0 /* possible future extensions, will require uint16_t flags */ #define __SRW 0x0100 /* open for reading & writing */ #define __SLBF 0x0200 /* line buffered */ #define __SNBF 0x0400 /* unbuffered */ #define __SMBF 0x0800 /* buf is from malloc */ #endif int size; /* size of buffer */ int len; /* characters read or written so far */ int (*put)(char, struct __file *); /* function to write one char to device */ int (*get)(struct __file *); /* function to read one char from device */ void *udata; /* User defined and accessible data. */ }; #endif /* not __DOXYGEN__ */ /*@{*/ /** \c FILE is the opaque structure that is passed around between the various standard IO functions. */ #define FILE struct __file /** Stream that will be used as an input stream by the simplified functions that don't take a \c stream argument. The first stream opened with read intent using \c fdevopen() will be assigned to \c stdin. */ #define stdin (__iob[0]) /** Stream that will be used as an output stream by the simplified functions that don't take a \c stream argument. The first stream opened with write intent using \c fdevopen() will be assigned to both, \c stdin, and \c stderr. */ #define stdout (__iob[1]) /** Stream destined for error output. Unless specifically assigned, identical to \c stdout. If \c stderr should point to another stream, the result of another \c fdevopen() must be explicitly assigned to it without closing the previous \c stderr (since this would also close \c stdout). */ #define stderr (__iob[2]) /** \c EOF declares the value that is returned by various standard IO functions in case of an error. Since the AVR platform (currently) doesn't contain an abstraction for actual files, its origin as "end of file" is somewhat meaningless here. */ #define EOF (-1) /** This macro inserts a pointer to user defined data into a FILE stream object. The user data can be useful for tracking state in the put and get functions supplied to the fdevopen() function. */ #define fdev_set_udata(stream, u) do { (stream)->udata = u; } while(0) /** This macro retrieves a pointer to user defined data from a FILE stream object. */ #define fdev_get_udata(stream) ((stream)->udata) #if defined(__DOXYGEN__) /** \brief Setup a user-supplied buffer as an stdio stream This macro takes a user-supplied buffer \c stream, and sets it up as a stream that is valid for stdio operations, similar to one that has been obtained dynamically from fdevopen(). The buffer to setup must be of type FILE. The arguments \c put and \c get are identical to those that need to be passed to fdevopen(). The \c rwflag argument can take one of the values _FDEV_SETUP_READ, _FDEV_SETUP_WRITE, or _FDEV_SETUP_RW, for read, write, or read/write intent, respectively. \note No assignments to the standard streams will be performed by fdev_setup_stream(). If standard streams are to be used, these need to be assigned by the user. See also under \ref stdio_without_malloc "Running stdio without malloc()". */ #define fdev_setup_stream(stream, put, get, rwflag) #else /* !DOXYGEN */ #define fdev_setup_stream(stream, p, g, f) \ do { \ (stream)->put = p; \ (stream)->get = g; \ (stream)->flags = f; \ (stream)->udata = 0; \ } while(0) #endif /* DOXYGEN */ #define _FDEV_SETUP_READ __SRD /**< fdev_setup_stream() with read intent */ #define _FDEV_SETUP_WRITE __SWR /**< fdev_setup_stream() with write intent */ #define _FDEV_SETUP_RW (__SRD|__SWR) /**< fdev_setup_stream() with read/write intent */ /** * Return code for an error condition during device read. * * To be used in the get function of fdevopen(). */ #define _FDEV_ERR (-1) /** * Return code for an end-of-file condition during device read. * * To be used in the get function of fdevopen(). */ #define _FDEV_EOF (-2) #if defined(__DOXYGEN__) /** \brief Initializer for a user-supplied stdio stream This macro acts similar to fdev_setup_stream(), but it is to be used as the initializer of a variable of type FILE. The remaining arguments are to be used as explained in fdev_setup_stream(). */ #define FDEV_SETUP_STREAM(put, get, rwflag) #else /* !DOXYGEN */ #define FDEV_SETUP_STREAM(p, g, f) \ { \ .put = p, \ .get = g, \ .flags = f, \ .udata = 0, \ } #endif /* DOXYGEN */ #ifdef __cplusplus extern "C" { #endif #if !defined(__DOXYGEN__) /* * Doxygen documentation can be found in fdevopen.c. */ extern struct __file *__iob[]; #if defined(__STDIO_FDEVOPEN_COMPAT_12) /* * Declare prototype for the discontinued version of fdevopen() that * has been in use up to avr-libc 1.2.x. The new implementation has * some backwards compatibility with the old version. */ extern FILE *fdevopen(int (*__put)(char), int (*__get)(void), int __opts __attribute__((unused))); #else /* !defined(__STDIO_FDEVOPEN_COMPAT_12) */ /* New prototype for avr-libc 1.4 and above. */ extern FILE *fdevopen(int (*__put)(char, FILE*), int (*__get)(FILE*)); #endif /* defined(__STDIO_FDEVOPEN_COMPAT_12) */ #endif /* not __DOXYGEN__ */ /** This function closes \c stream, and disallows and further IO to and from it. When using fdevopen() to setup the stream, a call to fclose() is needed in order to free the internal resources allocated. If the stream has been set up using fdev_setup_stream() or FDEV_SETUP_STREAM(), use fdev_close() instead. It currently always returns 0 (for success). */ extern int fclose(FILE *__stream); /** This macro frees up any library resources that might be associated with \c stream. It should be called if \c stream is no longer needed, right before the application is going to destroy the \c stream object itself. (Currently, this macro evaluates to nothing, but this might change in future versions of the library.) */ #if defined(__DOXYGEN__) # define fdev_close() #else # define fdev_close() ((void)0) #endif /** \c vfprintf is the central facility of the \c printf family of functions. It outputs values to \c stream under control of a format string passed in \c fmt. The actual values to print are passed as a variable argument list \c ap. \c vfprintf returns the number of characters written to \c stream, or \c EOF in case of an error. Currently, this will only happen if \c stream has not been opened with write intent. The format string is composed of zero or more directives: ordinary characters (not \c %), which are copied unchanged to the output stream; and conversion specifications, each of which results in fetching zero or more subsequent arguments. Each conversion specification is introduced by the \c % character. The arguments must properly correspond (after type promotion) with the conversion specifier. After the \c %, the following appear in sequence: - Zero or more of the following flags:
  • \c # The value should be converted to an "alternate form". For c, d, i, s, and u conversions, this option has no effect. For o conversions, the precision of the number is increased to force the first character of the output string to a zero (except if a zero value is printed with an explicit precision of zero). For x and X conversions, a non-zero result has the string `0x' (or `0X' for X conversions) prepended to it.
  • \c 0 (zero) Zero padding. For all conversions, the converted value is padded on the left with zeros rather than blanks. If a precision is given with a numeric conversion (d, i, o, u, i, x, and X), the 0 flag is ignored.
  • \c - A negative field width flag; the converted value is to be left adjusted on the field boundary. The converted value is padded on the right with blanks, rather than on the left with blanks or zeros. A - overrides a 0 if both are given.
  • ' ' (space) A blank should be left before a positive number produced by a signed conversion (d, or i).
  • \c + A sign must always be placed before a number produced by a signed conversion. A + overrides a space if both are used.
- An optional decimal digit string specifying a minimum field width. If the converted value has fewer characters than the field width, it will be padded with spaces on the left (or right, if the left-adjustment flag has been given) to fill out the field width. - An optional precision, in the form of a period . followed by an optional digit string. If the digit string is omitted, the precision is taken as zero. This gives the minimum number of digits to appear for d, i, o, u, x, and X conversions, or the maximum number of characters to be printed from a string for \c s conversions. - An optional \c l or \c h length modifier, that specifies that the argument for the d, i, o, u, x, or X conversion is a \c "long int" rather than \c int. The \c h is ignored, as \c "short int" is equivalent to \c int. - A character that specifies the type of conversion to be applied. The conversion specifiers and their meanings are: - \c diouxX The int (or appropriate variant) argument is converted to signed decimal (d and i), unsigned octal (o), unsigned decimal (u), or unsigned hexadecimal (x and X) notation. The letters "abcdef" are used for x conversions; the letters "ABCDEF" are used for X conversions. The precision, if any, gives the minimum number of digits that must appear; if the converted value requires fewer digits, it is padded on the left with zeros. - \c p The void * argument is taken as an unsigned integer, and converted similarly as a %\#x command would do. - \c c The \c int argument is converted to an \c "unsigned char", and the resulting character is written. - \c s The \c "char *" argument is expected to be a pointer to an array of character type (pointer to a string). Characters from the array are written up to (but not including) a terminating NUL character; if a precision is specified, no more than the number specified are written. If a precision is given, no null character need be present; if the precision is not specified, or is greater than the size of the array, the array must contain a terminating NUL character. - \c % A \c % is written. No argument is converted. The complete conversion specification is "%%". - \c eE The double argument is rounded and converted in the format \c "[-]d.dddeħdd" where there is one digit before the decimal-point character and the number of digits after it is equal to the precision; if the precision is missing, it is taken as 6; if the precision is zero, no decimal-point character appears. An \e E conversion uses the letter \c 'E' (rather than \c 'e') to introduce the exponent. The exponent always contains two digits; if the value is zero, the exponent is 00. - \c fF The double argument is rounded and converted to decimal notation in the format \c "[-]ddd.ddd", where the number of digits after the decimal-point character is equal to the precision specification. If the precision is missing, it is taken as 6; if the precision is explicitly zero, no decimal-point character appears. If a decimal point appears, at least one digit appears before it. - \c gG The double argument is converted in style \c f or \c e (or \c F or \c E for \c G conversions). The precision specifies the number of significant digits. If the precision is missing, 6 digits are given; if the precision is zero, it is treated as 1. Style \c e is used if the exponent from its conversion is less than -4 or greater than or equal to the precision. Trailing zeros are removed from the fractional part of the result; a decimal point appears only if it is followed by at least one digit. - \c S Similar to the \c s format, except the pointer is expected to point to a program-memory (ROM) string instead of a RAM string. In no case does a non-existent or small field width cause truncation of a numeric field; if the result of a conversion is wider than the field width, the field is expanded to contain the conversion result. Since the full implementation of all the mentioned features becomes fairly large, three different flavours of vfprintf() can be selected using linker options. The default vfprintf() implements all the mentioned functionality except floating point conversions. A minimized version of vfprintf() is available that only implements the very basic integer and string conversion facilities, but only the \c # additional option can be specified using conversion flags (these flags are parsed correctly from the format specification, but then simply ignored). This version can be requested using the following \ref gcc_minusW "compiler options": \code -Wl,-u,vfprintf -lprintf_min \endcode If the full functionality including the floating point conversions is required, the following options should be used: \code -Wl,-u,vfprintf -lprintf_flt -lm \endcode \par Limitations: - The specified width and precision can be at most 255. \par Notes: - For floating-point conversions, if you link default or minimized version of vfprintf(), the symbol \c ? will be output and double argument will be skiped. So you output below will not be crashed. For default version the width field and the "pad to left" ( symbol minus ) option will work in this case. - The \c hh length modifier is ignored (\c char argument is promouted to \c int). More exactly, this realization does not check the number of \c h symbols. - But the \c ll length modifier will to abort the output, as this realization does not operate \c long \c long arguments. - The variable width or precision field (an asterisk \c * symbol) is not realized and will to abort the output. */ extern int vfprintf(FILE *__stream, const char *__fmt, va_list __ap); /** Variant of \c vfprintf() that uses a \c fmt string that resides in program memory. */ extern int vfprintf_P(FILE *__stream, const char *__fmt, va_list __ap); /** The function \c fputc sends the character \c c (though given as type \c int) to \c stream. It returns the character, or \c EOF in case an error occurred. */ extern int fputc(int __c, FILE *__stream); #if !defined(__DOXYGEN__) /* putc() function implementation, required by standard */ extern int putc(int __c, FILE *__stream); /* putchar() function implementation, required by standard */ extern int putchar(int __c); #endif /* not __DOXYGEN__ */ /** The macro \c putc used to be a "fast" macro implementation with a functionality identical to fputc(). For space constraints, in \c avr-libc, it is just an alias for \c fputc. */ #define putc(__c, __stream) fputc(__c, __stream) /** The macro \c putchar sends character \c c to \c stdout. */ #define putchar(__c) fputc(__c, stdout) /** The function \c printf performs formatted output to stream \c stdout. See \c vfprintf() for details. */ extern int printf(const char *__fmt, ...); /** Variant of \c printf() that uses a \c fmt string that resides in program memory. */ extern int printf_P(const char *__fmt, ...); /** The function \c vprintf performs formatted output to stream \c stdout, taking a variable argument list as in vfprintf(). See vfprintf() for details. */ extern int vprintf(const char *__fmt, va_list __ap); /** Variant of \c printf() that sends the formatted characters to string \c s. */ extern int sprintf(char *__s, const char *__fmt, ...); /** Variant of \c sprintf() that uses a \c fmt string that resides in program memory. */ extern int sprintf_P(char *__s, const char *__fmt, ...); /** Like \c sprintf(), but instead of assuming \c s to be of infinite size, no more than \c n characters (including the trailing NUL character) will be converted to \c s. Returns the number of characters that would have been written to \c s if there were enough space. */ extern int snprintf(char *__s, size_t __n, const char *__fmt, ...); /** Variant of \c snprintf() that uses a \c fmt string that resides in program memory. */ extern int snprintf_P(char *__s, size_t __n, const char *__fmt, ...); /** Like \c sprintf() but takes a variable argument list for the arguments. */ extern int vsprintf(char *__s, const char *__fmt, va_list ap); /** Variant of \c vsprintf() that uses a \c fmt string that resides in program memory. */ extern int vsprintf_P(char *__s, const char *__fmt, va_list ap); /** Like \c vsprintf(), but instead of assuming \c s to be of infinite size, no more than \c n characters (including the trailing NUL character) will be converted to \c s. Returns the number of characters that would have been written to \c s if there were enough space. */ extern int vsnprintf(char *__s, size_t __n, const char *__fmt, va_list ap); /** Variant of \c vsnprintf() that uses a \c fmt string that resides in program memory. */ extern int vsnprintf_P(char *__s, size_t __n, const char *__fmt, va_list ap); /** The function \c fprintf performs formatted output to \c stream. See \c vfprintf() for details. */ extern int fprintf(FILE *__stream, const char *__fmt, ...); /** Variant of \c fprintf() that uses a \c fmt string that resides in program memory. */ extern int fprintf_P(FILE *__stream, const char *__fmt, ...); /** Write the string pointed to by \c str to stream \c stream. Returns 0 on success and EOF on error. */ extern int fputs(const char *__str, FILE *__stream); /** Variant of fputs() where \c str resides in program memory. */ extern int fputs_P(const char *__str, FILE *__stream); /** Write the string pointed to by \c str, and a trailing newline character, to \c stdout. */ extern int puts(const char *__str); /** Variant of puts() where \c str resides in program memory. */ extern int puts_P(const char *__str); /** Write \c nmemb objects, \c size bytes each, to \c stream. The first byte of the first object is referenced by \c ptr. Returns the number of objects successfully written, i. e. \c nmemb unless an output error occured. */ extern size_t fwrite(const void *__ptr, size_t __size, size_t __nmemb, FILE *__stream); /** The function \c fgetc reads a character from \c stream. It returns the character, or \c EOF in case end-of-file was encountered or an error occurred. The routines feof() or ferror() must be used to distinguish between both situations. */ extern int fgetc(FILE *__stream); #if !defined(__DOXYGEN__) /* getc() function implementation, required by standard */ extern int getc(FILE *__stream); /* getchar() function implementation, required by standard */ extern int getchar(void); #endif /* not __DOXYGEN__ */ /** The macro \c getc used to be a "fast" macro implementation with a functionality identical to fgetc(). For space constraints, in \c avr-libc, it is just an alias for \c fgetc. */ #define getc(__stream) fgetc(__stream) /** The macro \c getchar reads a character from \c stdin. Return values and error handling is identical to fgetc(). */ #define getchar() fgetc(stdin) /** The ungetc() function pushes the character \c c (converted to an unsigned char) back onto the input stream pointed to by \c stream. The pushed-back character will be returned by a subsequent read on the stream. Currently, only a single character can be pushed back onto the stream. The ungetc() function returns the character pushed back after the conversion, or \c EOF if the operation fails. If the value of the argument \c c character equals \c EOF, the operation will fail and the stream will remain unchanged. */ extern int ungetc(int __c, FILE *__stream); /** Read at most size - 1 bytes from \c stream, until a newline character was encountered, and store the characters in the buffer pointed to by \c str. Unless an error was encountered while reading, the string will then be terminated with a \c NUL character. If an error was encountered, the function returns NULL and sets the error flag of \c stream, which can be tested using ferror(). Otherwise, a pointer to the string will be returned. */ extern char *fgets(char *__str, int __size, FILE *__stream); /** Similar to fgets() except that it will operate on stream \c stdin, and the trailing newline (if any) will not be stored in the string. It is the caller's responsibility to provide enough storage to hold the characters read. */ extern char *gets(char *__str); /** Read \c nmemb objects, \c size bytes each, from \c stream, to the buffer pointed to by \c ptr. Returns the number of objects successfully read, i. e. \c nmemb unless an input error occured or end-of-file was encountered. feof() and ferror() must be used to distinguish between these two conditions. */ extern size_t fread(void *__ptr, size_t __size, size_t __nmemb, FILE *__stream); /** Clear the error and end-of-file flags of \c stream. */ extern void clearerr(FILE *__stream); #if !defined(__DOXYGEN__) /* fast inlined version of clearerr() */ #define clearerror(s) do { (s)->flags &= ~(__SERR | __SEOF); } while(0) #endif /* !defined(__DOXYGEN__) */ /** Test the end-of-file flag of \c stream. This flag can only be cleared by a call to clearerr(). */ extern int feof(FILE *__stream); #if !defined(__DOXYGEN__) /* fast inlined version of feof() */ #define feof(s) ((s)->flags & __SEOF) #endif /* !defined(__DOXYGEN__) */ /** Test the error flag of \c stream. This flag can only be cleared by a call to clearerr(). */ extern int ferror(FILE *__stream); #if !defined(__DOXYGEN__) /* fast inlined version of ferror() */ #define ferror(s) ((s)->flags & __SERR) #endif /* !defined(__DOXYGEN__) */ extern int vfscanf(FILE *__stream, const char *__fmt, va_list __ap); /** Variant of vfscanf() using a \c fmt string in program memory. */ extern int vfscanf_P(FILE *__stream, const char *__fmt, va_list __ap); /** The function \c fscanf performs formatted input, reading the input data from \c stream. See vfscanf() for details. */ extern int fscanf(FILE *__stream, const char *__fmt, ...); /** Variant of fscanf() using a \c fmt string in program memory. */ extern int fscanf_P(FILE *__stream, const char *__fmt, ...); /** The function \c scanf performs formatted input from stream \c stdin. See vfscanf() for details. */ extern int scanf(const char *__fmt, ...); /** Variant of scanf() where \c fmt resides in program memory. */ extern int scanf_P(const char *__fmt, ...); /** The function \c vscanf performs formatted input from stream \c stdin, taking a variable argument list as in vfscanf(). See vfscanf() for details. */ extern int vscanf(const char *__fmt, va_list __ap); /** The function \c sscanf performs formatted input, reading the input data from the buffer pointed to by \c buf. See vfscanf() for details. */ extern int sscanf(const char *__buf, const char *__fmt, ...); /** Variant of sscanf() using a \c fmt string in program memory. */ extern int sscanf_P(const char *__buf, const char *__fmt, ...); #if defined(__DOXYGEN__) /** Flush \c stream. This is a null operation provided for source-code compatibility only, as the standard IO implementation currently does not perform any buffering. */ extern int fflush(FILE *stream); #else static __inline__ int fflush(FILE *stream __attribute__((unused))) { return 0; } #endif #ifdef __cplusplus } #endif /*@}*/ /* * The following constants are currently not used by avr-libc's * stdio subsystem. They are defined here since the gcc build * environment expects them to be here. */ #define SEEK_SET 0 #define SEEK_CUR 1 #define SEEK_END 2 #endif /* __ASSEMBLER */ #endif /* _STDLIB_H_ */ avr-libc-1.8.0.orig/include/inttypes.h0000644000000000000000000003503511732702554014533 0ustar /* Copyright (c) 2004,2005,2007 Joerg Wunsch Copyright (c) 2005, Carlos Lamas All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: inttypes.h 1766 2008-10-17 21:33:57Z arcanum $ */ #ifndef __INTTYPES_H_ #define __INTTYPES_H_ #include /** \file */ /** \defgroup avr_inttypes : Integer Type conversions \code #include \endcode This header file includes the exact-width integer definitions from , and extends them with additional facilities provided by the implementation. Currently, the extensions include two additional integer types that could hold a "far" pointer (i.e. a code pointer that can address more than 64 KB), as well as standard names for all printf and scanf formatting options that are supported by the \ref avr_stdio. As the library does not support the full range of conversion specifiers from ISO 9899:1999, only those conversions that are actually implemented will be listed here. The idea behind these conversion macros is that, for each of the types defined by , a macro will be supplied that portably allows formatting an object of that type in printf() or scanf() operations. Example: \code #include uint8_t smallval; int32_t longval; ... printf("The hexadecimal value of smallval is %" PRIx8 ", the decimal value of longval is %" PRId32 ".\n", smallval, longval); \endcode */ /** \name Far pointers for memory access >64K */ /*@{*/ /** \ingroup avr_inttypes signed integer type that can hold a pointer > 64 KB */ typedef int32_t int_farptr_t; /** \ingroup avr_inttypes unsigned integer type that can hold a pointer > 64 KB */ typedef uint32_t uint_farptr_t; /*@}*/ #if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) /** \name macros for printf and scanf format specifiers For C++, these are only included if __STDC_LIMIT_MACROS is defined before including . */ /*@{*/ /** \ingroup avr_inttypes decimal printf format for int8_t */ #define PRId8 "d" /** \ingroup avr_inttypes decimal printf format for int_least8_t */ #define PRIdLEAST8 "d" /** \ingroup avr_inttypes decimal printf format for int_fast8_t */ #define PRIdFAST8 "d" /** \ingroup avr_inttypes integer printf format for int8_t */ #define PRIi8 "i" /** \ingroup avr_inttypes integer printf format for int_least8_t */ #define PRIiLEAST8 "i" /** \ingroup avr_inttypes integer printf format for int_fast8_t */ #define PRIiFAST8 "i" /** \ingroup avr_inttypes decimal printf format for int16_t */ #define PRId16 "d" /** \ingroup avr_inttypes decimal printf format for int_least16_t */ #define PRIdLEAST16 "d" /** \ingroup avr_inttypes decimal printf format for int_fast16_t */ #define PRIdFAST16 "d" /** \ingroup avr_inttypes integer printf format for int16_t */ #define PRIi16 "i" /** \ingroup avr_inttypes integer printf format for int_least16_t */ #define PRIiLEAST16 "i" /** \ingroup avr_inttypes integer printf format for int_fast16_t */ #define PRIiFAST16 "i" /** \ingroup avr_inttypes decimal printf format for int32_t */ #define PRId32 "ld" /** \ingroup avr_inttypes decimal printf format for int_least32_t */ #define PRIdLEAST32 "ld" /** \ingroup avr_inttypes decimal printf format for int_fast32_t */ #define PRIdFAST32 "ld" /** \ingroup avr_inttypes integer printf format for int32_t */ #define PRIi32 "li" /** \ingroup avr_inttypes integer printf format for int_least32_t */ #define PRIiLEAST32 "li" /** \ingroup avr_inttypes integer printf format for int_fast32_t */ #define PRIiFAST32 "li" #ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf #define PRId64 "lld" #define PRIdLEAST64 "lld" #define PRIdFAST64 "lld" #define PRIi64 "lli" #define PRIiLEAST64 "lli" #define PRIiFAST64 "lli" #define PRIdMAX "lld" #define PRIiMAX "lli" #endif /** \ingroup avr_inttypes decimal printf format for intptr_t */ #define PRIdPTR PRId16 /** \ingroup avr_inttypes integer printf format for intptr_t */ #define PRIiPTR PRIi16 /** \ingroup avr_inttypes octal printf format for uint8_t */ #define PRIo8 "o" /** \ingroup avr_inttypes octal printf format for uint_least8_t */ #define PRIoLEAST8 "o" /** \ingroup avr_inttypes octal printf format for uint_fast8_t */ #define PRIoFAST8 "o" /** \ingroup avr_inttypes decimal printf format for uint8_t */ #define PRIu8 "u" /** \ingroup avr_inttypes decimal printf format for uint_least8_t */ #define PRIuLEAST8 "u" /** \ingroup avr_inttypes decimal printf format for uint_fast8_t */ #define PRIuFAST8 "u" /** \ingroup avr_inttypes hexadecimal printf format for uint8_t */ #define PRIx8 "x" /** \ingroup avr_inttypes hexadecimal printf format for uint_least8_t */ #define PRIxLEAST8 "x" /** \ingroup avr_inttypes hexadecimal printf format for uint_fast8_t */ #define PRIxFAST8 "x" /** \ingroup avr_inttypes uppercase hexadecimal printf format for uint8_t */ #define PRIX8 "X" /** \ingroup avr_inttypes uppercase hexadecimal printf format for uint_least8_t */ #define PRIXLEAST8 "X" /** \ingroup avr_inttypes uppercase hexadecimal printf format for uint_fast8_t */ #define PRIXFAST8 "X" /** \ingroup avr_inttypes octal printf format for uint16_t */ #define PRIo16 "o" /** \ingroup avr_inttypes octal printf format for uint_least16_t */ #define PRIoLEAST16 "o" /** \ingroup avr_inttypes octal printf format for uint_fast16_t */ #define PRIoFAST16 "o" /** \ingroup avr_inttypes decimal printf format for uint16_t */ #define PRIu16 "u" /** \ingroup avr_inttypes decimal printf format for uint_least16_t */ #define PRIuLEAST16 "u" /** \ingroup avr_inttypes decimal printf format for uint_fast16_t */ #define PRIuFAST16 "u" /** \ingroup avr_inttypes hexadecimal printf format for uint16_t */ #define PRIx16 "x" /** \ingroup avr_inttypes hexadecimal printf format for uint_least16_t */ #define PRIxLEAST16 "x" /** \ingroup avr_inttypes hexadecimal printf format for uint_fast16_t */ #define PRIxFAST16 "x" /** \ingroup avr_inttypes uppercase hexadecimal printf format for uint16_t */ #define PRIX16 "X" /** \ingroup avr_inttypes uppercase hexadecimal printf format for uint_least16_t */ #define PRIXLEAST16 "X" /** \ingroup avr_inttypes uppercase hexadecimal printf format for uint_fast16_t */ #define PRIXFAST16 "X" /** \ingroup avr_inttypes octal printf format for uint32_t */ #define PRIo32 "lo" /** \ingroup avr_inttypes octal printf format for uint_least32_t */ #define PRIoLEAST32 "lo" /** \ingroup avr_inttypes octal printf format for uint_fast32_t */ #define PRIoFAST32 "lo" /** \ingroup avr_inttypes decimal printf format for uint32_t */ #define PRIu32 "lu" /** \ingroup avr_inttypes decimal printf format for uint_least32_t */ #define PRIuLEAST32 "lu" /** \ingroup avr_inttypes decimal printf format for uint_fast32_t */ #define PRIuFAST32 "lu" /** \ingroup avr_inttypes hexadecimal printf format for uint32_t */ #define PRIx32 "lx" /** \ingroup avr_inttypes hexadecimal printf format for uint_least32_t */ #define PRIxLEAST32 "lx" /** \ingroup avr_inttypes hexadecimal printf format for uint_fast32_t */ #define PRIxFAST32 "lx" /** \ingroup avr_inttypes uppercase hexadecimal printf format for uint32_t */ #define PRIX32 "lX" /** \ingroup avr_inttypes uppercase hexadecimal printf format for uint_least32_t */ #define PRIXLEAST32 "lX" /** \ingroup avr_inttypes uppercase hexadecimal printf format for uint_fast32_t */ #define PRIXFAST32 "lX" #ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf #define PRIo64 "llo" #define PRIoLEAST64 "llo" #define PRIoFAST64 "llo" #define PRIu64 "llu" #define PRIuLEAST64 "llu" #define PRIuFAST64 "llu" #define PRIx64 "llx" #define PRIxLEAST64 "llx" #define PRIxFAST64 "llx" #define PRIX64 "llX" #define PRIXLEAST64 "llX" #define PRIXFAST64 "llX" #define PRIoMAX "llo" #define PRIuMAX "llu" #define PRIxMAX "llx" #define PRIXMAX "llX" #endif /** \ingroup avr_inttypes octal printf format for uintptr_t */ #define PRIoPTR PRIo16 /** \ingroup avr_inttypes decimal printf format for uintptr_t */ #define PRIuPTR PRIu16 /** \ingroup avr_inttypes hexadecimal printf format for uintptr_t */ #define PRIxPTR PRIx16 /** \ingroup avr_inttypes uppercase hexadecimal printf format for uintptr_t */ #define PRIXPTR PRIX16 #ifdef __avr_libc_does_not_implement_hh_in_scanf #define SCNd8 "hhd" #define SCNdLEAST8 "hhd" #define SCNdFAST8 "hhd" #define SCNi8 "hhi" #define SCNiLEAST8 "hhi" #define SCNiFAST8 "hhi" #endif /** \ingroup avr_inttypes decimal scanf format for int16_t */ #define SCNd16 "d" /** \ingroup avr_inttypes decimal scanf format for int_least16_t */ #define SCNdLEAST16 "d" /** \ingroup avr_inttypes decimal scanf format for int_fast16_t */ #define SCNdFAST16 "d" /** \ingroup avr_inttypes generic-integer scanf format for int16_t */ #define SCNi16 "i" /** \ingroup avr_inttypes generic-integer scanf format for int_least16_t */ #define SCNiLEAST16 "i" /** \ingroup avr_inttypes generic-integer scanf format for int_fast16_t */ #define SCNiFAST16 "i" /** \ingroup avr_inttypes decimal scanf format for int32_t */ #define SCNd32 "ld" /** \ingroup avr_inttypes decimal scanf format for int_least32_t */ #define SCNdLEAST32 "ld" /** \ingroup avr_inttypes decimal scanf format for int_fast32_t */ #define SCNdFAST32 "ld" /** \ingroup avr_inttypes generic-integer scanf format for int32_t */ #define SCNi32 "li" /** \ingroup avr_inttypes generic-integer scanf format for int_least32_t */ #define SCNiLEAST32 "li" /** \ingroup avr_inttypes generic-integer scanf format for int_fast32_t */ #define SCNiFAST32 "li" #ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf #define SCNd64 "lld" #define SCNdLEAST64 "lld" #define SCNdFAST64 "lld" #define SCNi64 "lli" #define SCNiLEAST64 "lli" #define SCNiFAST64 "lli" #define SCNdMAX "lld" #define SCNiMAX "lli" #endif /** \ingroup avr_inttypes decimal scanf format for intptr_t */ #define SCNdPTR SCNd16 /** \ingroup avr_inttypes generic-integer scanf format for intptr_t */ #define SCNiPTR SCNi16 #ifdef __avr_libc_does_not_implement_hh_in_scanf #define SCNo8 "hho" #define SCNoLEAST8 "hho" #define SCNoFAST8 "hho" #define SCNu8 "hhu" #define SCNuLEAST8 "hhu" #define SCNuFAST8 "hhu" #define SCNx8 "hhx" #define SCNxLEAST8 "hhx" #define SCNxFAST8 "hhx" #endif /** \ingroup avr_inttypes octal scanf format for uint16_t */ #define SCNo16 "o" /** \ingroup avr_inttypes octal scanf format for uint_least16_t */ #define SCNoLEAST16 "o" /** \ingroup avr_inttypes octal scanf format for uint_fast16_t */ #define SCNoFAST16 "o" /** \ingroup avr_inttypes decimal scanf format for uint16_t */ #define SCNu16 "u" /** \ingroup avr_inttypes decimal scanf format for uint_least16_t */ #define SCNuLEAST16 "u" /** \ingroup avr_inttypes decimal scanf format for uint_fast16_t */ #define SCNuFAST16 "u" /** \ingroup avr_inttypes hexadecimal scanf format for uint16_t */ #define SCNx16 "x" /** \ingroup avr_inttypes hexadecimal scanf format for uint_least16_t */ #define SCNxLEAST16 "x" /** \ingroup avr_inttypes hexadecimal scanf format for uint_fast16_t */ #define SCNxFAST16 "x" /** \ingroup avr_inttypes octal scanf format for uint32_t */ #define SCNo32 "lo" /** \ingroup avr_inttypes octal scanf format for uint_least32_t */ #define SCNoLEAST32 "lo" /** \ingroup avr_inttypes octal scanf format for uint_fast32_t */ #define SCNoFAST32 "lo" /** \ingroup avr_inttypes decimal scanf format for uint32_t */ #define SCNu32 "lu" /** \ingroup avr_inttypes decimal scanf format for uint_least32_t */ #define SCNuLEAST32 "lu" /** \ingroup avr_inttypes decimal scanf format for uint_fast32_t */ #define SCNuFAST32 "lu" /** \ingroup avr_inttypes hexadecimal scanf format for uint32_t */ #define SCNx32 "lx" /** \ingroup avr_inttypes hexadecimal scanf format for uint_least32_t */ #define SCNxLEAST32 "lx" /** \ingroup avr_inttypes hexadecimal scanf format for uint_fast32_t */ #define SCNxFAST32 "lx" #ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf #define SCNo64 "llo" #define SCNoLEAST64 "llo" #define SCNoFAST64 "llo" #define SCNu64 "llu" #define SCNuLEAST64 "llu" #define SCNuFAST64 "llu" #define SCNx64 "llx" #define SCNxLEAST64 "llx" #define SCNxFAST64 "llx" #define SCNoMAX "llo" #define SCNuMAX "llu" #define SCNxMAX "llx" #endif /** \ingroup avr_inttypes octal scanf format for uintptr_t */ #define SCNoPTR SCNo16 /** \ingroup avr_inttypes decimal scanf format for uintptr_t */ #define SCNuPTR SCNu16 /** \ingroup avr_inttypes hexadecimal scanf format for uintptr_t */ #define SCNxPTR SCNx16 /*@}*/ #endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ #endif /* __INTTYPES_H_ */ avr-libc-1.8.0.orig/include/alloca.h0000644000000000000000000000505111732702554014102 0ustar /* Copyright (c) 2007, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: alloca.h 1508 2007-12-18 13:36:50Z dmix $ */ #ifndef _ALLOCA_H #define _ALLOCA_H 1 #include /** \defgroup alloca : Allocate space in the stack */ /** \ingroup alloca \brief Allocate \a __size bytes of space in the stack frame of the caller. This temporary space is automatically freed when the function that called alloca() returns to its caller. Avr-libc defines the alloca() as a macro, which is translated into the inlined \c __builtin_alloca() function. The fact that the code is inlined, means that it is impossible to take the address of this function, or to change its behaviour by linking with a different library. \return alloca() returns a pointer to the beginning of the allocated space. If the allocation causes stack overflow, program behaviour is undefined. \warning Avoid use alloca() inside the list of arguments of a function call. */ extern void *alloca (size_t __size); #define alloca(size) __builtin_alloca (size) #endif /* alloca.h */ avr-libc-1.8.0.orig/include/util/0000755000000000000000000000000011732702554013452 5ustar avr-libc-1.8.0.orig/include/util/delay_basic.h0000644000000000000000000000777111732702554016076 0ustar /* Copyright (c) 2002, Marek Michalkiewicz Copyright (c) 2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: delay_basic.h 2143 2010-06-08 21:19:51Z joerg_wunsch $ */ #ifndef _UTIL_DELAY_BASIC_H_ #define _UTIL_DELAY_BASIC_H_ 1 #include #if !defined(__DOXYGEN__) static inline void _delay_loop_1(uint8_t __count) __attribute__((always_inline)); static inline void _delay_loop_2(uint16_t __count) __attribute__((always_inline)); #endif /** \file */ /** \defgroup util_delay_basic : Basic busy-wait delay loops \code #include \endcode The functions in this header file implement simple delay loops that perform a busy-waiting. They are typically used to facilitate short delays in the program execution. They are implemented as count-down loops with a well-known CPU cycle count per loop iteration. As such, no other processing can occur simultaneously. It should be kept in mind that the functions described here do not disable interrupts. In general, for long delays, the use of hardware timers is much preferrable, as they free the CPU, and allow for concurrent processing of other events while the timer is running. However, in particular for very short delays, the overhead of setting up a hardware timer is too much compared to the overall delay time. Two inline functions are provided for the actual delay algorithms. */ /** \ingroup util_delay_basic Delay loop using an 8-bit counter \c __count, so up to 256 iterations are possible. (The value 256 would have to be passed as 0.) The loop executes three CPU cycles per iteration, not including the overhead the compiler needs to setup the counter register. Thus, at a CPU speed of 1 MHz, delays of up to 768 microseconds can be achieved. */ void _delay_loop_1(uint8_t __count) { __asm__ volatile ( "1: dec %0" "\n\t" "brne 1b" : "=r" (__count) : "0" (__count) ); } /** \ingroup util_delay_basic Delay loop using a 16-bit counter \c __count, so up to 65536 iterations are possible. (The value 65536 would have to be passed as 0.) The loop executes four CPU cycles per iteration, not including the overhead the compiler requires to setup the counter register pair. Thus, at a CPU speed of 1 MHz, delays of up to about 262.1 milliseconds can be achieved. */ void _delay_loop_2(uint16_t __count) { __asm__ volatile ( "1: sbiw %0,1" "\n\t" "brne 1b" : "=w" (__count) : "0" (__count) ); } #endif /* _UTIL_DELAY_BASIC_H_ */ avr-libc-1.8.0.orig/include/util/crc16.h0000644000000000000000000002171111732702554014543 0ustar /* Copyright (c) 2002, 2003, 2004 Marek Michalkiewicz Copyright (c) 2005, 2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: crc16.h 2136 2010-06-08 12:03:38Z joerg_wunsch $ */ #ifndef _UTIL_CRC16_H_ #define _UTIL_CRC16_H_ #include /** \file */ /** \defgroup util_crc : CRC Computations \code#include \endcode This header file provides a optimized inline functions for calculating cyclic redundancy checks (CRC) using common polynomials. \par References: \par See the Dallas Semiconductor app note 27 for 8051 assembler example and general CRC optimization suggestions. The table on the last page of the app note is the key to understanding these implementations. \par Jack Crenshaw's "Implementing CRCs" article in the January 1992 isue of \e Embedded \e Systems \e Programming. This may be difficult to find, but it explains CRC's in very clear and concise terms. Well worth the effort to obtain a copy. A typical application would look like: \code // Dallas iButton test vector. uint8_t serno[] = { 0x02, 0x1c, 0xb8, 0x01, 0, 0, 0, 0xa2 }; int checkcrc(void) { uint8_t crc = 0, i; for (i = 0; i < sizeof serno / sizeof serno[0]; i++) crc = _crc_ibutton_update(crc, serno[i]); return crc; // must be 0 } \endcode */ /** \ingroup util_crc Optimized CRC-16 calculation. Polynomial: x^16 + x^15 + x^2 + 1 (0xa001)
Initial value: 0xffff This CRC is normally used in disk-drive controllers. The following is the equivalent functionality written in C. \code uint16_t crc16_update(uint16_t crc, uint8_t a) { int i; crc ^= a; for (i = 0; i < 8; ++i) { if (crc & 1) crc = (crc >> 1) ^ 0xA001; else crc = (crc >> 1); } return crc; } \endcode */ static __inline__ uint16_t _crc16_update(uint16_t __crc, uint8_t __data) { uint8_t __tmp; uint16_t __ret; __asm__ __volatile__ ( "eor %A0,%2" "\n\t" "mov %1,%A0" "\n\t" "swap %1" "\n\t" "eor %1,%A0" "\n\t" "mov __tmp_reg__,%1" "\n\t" "lsr %1" "\n\t" "lsr %1" "\n\t" "eor %1,__tmp_reg__" "\n\t" "mov __tmp_reg__,%1" "\n\t" "lsr %1" "\n\t" "eor %1,__tmp_reg__" "\n\t" "andi %1,0x07" "\n\t" "mov __tmp_reg__,%A0" "\n\t" "mov %A0,%B0" "\n\t" "lsr %1" "\n\t" "ror __tmp_reg__" "\n\t" "ror %1" "\n\t" "mov %B0,__tmp_reg__" "\n\t" "eor %A0,%1" "\n\t" "lsr __tmp_reg__" "\n\t" "ror %1" "\n\t" "eor %B0,__tmp_reg__" "\n\t" "eor %A0,%1" : "=r" (__ret), "=d" (__tmp) : "r" (__data), "0" (__crc) : "r0" ); return __ret; } /** \ingroup util_crc Optimized CRC-XMODEM calculation. Polynomial: x^16 + x^12 + x^5 + 1 (0x1021)
Initial value: 0x0 This is the CRC used by the Xmodem-CRC protocol. The following is the equivalent functionality written in C. \code uint16_t crc_xmodem_update (uint16_t crc, uint8_t data) { int i; crc = crc ^ ((uint16_t)data << 8); for (i=0; i<8; i++) { if (crc & 0x8000) crc = (crc << 1) ^ 0x1021; else crc <<= 1; } return crc; } \endcode */ static __inline__ uint16_t _crc_xmodem_update(uint16_t __crc, uint8_t __data) { uint16_t __ret; /* %B0:%A0 (alias for __crc) */ uint8_t __tmp1; /* %1 */ uint8_t __tmp2; /* %2 */ /* %3 __data */ __asm__ __volatile__ ( "eor %B0,%3" "\n\t" /* crc.hi ^ data */ "mov __tmp_reg__,%B0" "\n\t" "swap __tmp_reg__" "\n\t" /* swap(crc.hi ^ data) */ /* Calculate the ret.lo of the CRC. */ "mov %1,__tmp_reg__" "\n\t" "andi %1,0x0f" "\n\t" "eor %1,%B0" "\n\t" "mov %2,%B0" "\n\t" "eor %2,__tmp_reg__" "\n\t" "lsl %2" "\n\t" "andi %2,0xe0" "\n\t" "eor %1,%2" "\n\t" /* __tmp1 is now ret.lo. */ /* Calculate the ret.hi of the CRC. */ "mov %2,__tmp_reg__" "\n\t" "eor %2,%B0" "\n\t" "andi %2,0xf0" "\n\t" "lsr %2" "\n\t" "mov __tmp_reg__,%B0" "\n\t" "lsl __tmp_reg__" "\n\t" "rol %2" "\n\t" "lsr %B0" "\n\t" "lsr %B0" "\n\t" "lsr %B0" "\n\t" "andi %B0,0x1f" "\n\t" "eor %B0,%2" "\n\t" "eor %B0,%A0" "\n\t" /* ret.hi is now ready. */ "mov %A0,%1" "\n\t" /* ret.lo is now ready. */ : "=d" (__ret), "=d" (__tmp1), "=d" (__tmp2) : "r" (__data), "0" (__crc) : "r0" ); return __ret; } /** \ingroup util_crc Optimized CRC-CCITT calculation. Polynomial: x^16 + x^12 + x^5 + 1 (0x8408)
Initial value: 0xffff This is the CRC used by PPP and IrDA. See RFC1171 (PPP protocol) and IrDA IrLAP 1.1 \note Although the CCITT polynomial is the same as that used by the Xmodem protocol, they are quite different. The difference is in how the bits are shifted through the alorgithm. Xmodem shifts the MSB of the CRC and the input first, while CCITT shifts the LSB of the CRC and the input first. The following is the equivalent functionality written in C. \code uint16_t crc_ccitt_update (uint16_t crc, uint8_t data) { data ^= lo8 (crc); data ^= data << 4; return ((((uint16_t)data << 8) | hi8 (crc)) ^ (uint8_t)(data >> 4) ^ ((uint16_t)data << 3)); } \endcode */ static __inline__ uint16_t _crc_ccitt_update (uint16_t __crc, uint8_t __data) { uint16_t __ret; __asm__ __volatile__ ( "eor %A0,%1" "\n\t" "mov __tmp_reg__,%A0" "\n\t" "swap %A0" "\n\t" "andi %A0,0xf0" "\n\t" "eor %A0,__tmp_reg__" "\n\t" "mov __tmp_reg__,%B0" "\n\t" "mov %B0,%A0" "\n\t" "swap %A0" "\n\t" "andi %A0,0x0f" "\n\t" "eor __tmp_reg__,%A0" "\n\t" "lsr %A0" "\n\t" "eor %B0,%A0" "\n\t" "eor %A0,%B0" "\n\t" "lsl %A0" "\n\t" "lsl %A0" "\n\t" "lsl %A0" "\n\t" "eor %A0,__tmp_reg__" : "=d" (__ret) : "r" (__data), "0" (__crc) : "r0" ); return __ret; } /** \ingroup util_crc Optimized Dallas (now Maxim) iButton 8-bit CRC calculation. Polynomial: x^8 + x^5 + x^4 + 1 (0x8C)
Initial value: 0x0 See http://www.maxim-ic.com/appnotes.cfm/appnote_number/27 The following is the equivalent functionality written in C. \code uint8_t _crc_ibutton_update(uint8_t crc, uint8_t data) { uint8_t i; crc = crc ^ data; for (i = 0; i < 8; i++) { if (crc & 0x01) crc = (crc >> 1) ^ 0x8C; else crc >>= 1; } return crc; } \endcode */ static __inline__ uint8_t _crc_ibutton_update(uint8_t __crc, uint8_t __data) { uint8_t __i, __pattern; __asm__ __volatile__ ( " eor %0, %4" "\n\t" " ldi %1, 8" "\n\t" " ldi %2, 0x8C" "\n\t" "1: lsr %0" "\n\t" " brcc 2f" "\n\t" " eor %0, %2" "\n\t" "2: dec %1" "\n\t" " brne 1b" "\n\t" : "=r" (__crc), "=d" (__i), "=d" (__pattern) : "0" (__crc), "r" (__data)); return __crc; } #endif /* _UTIL_CRC16_H_ */ avr-libc-1.8.0.orig/include/util/Makefile.in0000644000000000000000000003757311732702554015536 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2005,2007 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 2103 2010-03-17 05:16:10Z joerg_wunsch $ # VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ subdir = include/util DIST_COMMON = $(avr_HEADERS) $(srcdir)/Makefile.am \ $(srcdir)/Makefile.in $(srcdir)/delay.h.in ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = delay.h CONFIG_CLEAN_VPATH_FILES = SOURCES = DIST_SOURCES = am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; 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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: twi.h 1196 2007-01-23 15:34:58Z joerg_wunsch $ */ /* copied from: Id: avr/twi.h,v 1.4 2004/11/01 21:19:54 arcanum Exp */ #ifndef _UTIL_TWI_H_ #define _UTIL_TWI_H_ 1 #include /** \file */ /** \defgroup util_twi : TWI bit mask definitions \code #include \endcode This header file contains bit mask definitions for use with the AVR TWI interface. */ /** \name TWSR values Mnemonics:
TW_MT_xxx - master transmitter
TW_MR_xxx - master receiver
TW_ST_xxx - slave transmitter
TW_SR_xxx - slave receiver */ /*@{*/ /* Master */ /** \ingroup util_twi \def TW_START start condition transmitted */ #define TW_START 0x08 /** \ingroup util_twi \def TW_REP_START repeated start condition transmitted */ #define TW_REP_START 0x10 /* Master Transmitter */ /** \ingroup util_twi \def TW_MT_SLA_ACK SLA+W transmitted, ACK received */ #define TW_MT_SLA_ACK 0x18 /** \ingroup util_twi \def TW_MT_SLA_NACK SLA+W transmitted, NACK received */ #define TW_MT_SLA_NACK 0x20 /** \ingroup util_twi \def TW_MT_DATA_ACK data transmitted, ACK received */ #define TW_MT_DATA_ACK 0x28 /** \ingroup util_twi \def TW_MT_DATA_NACK data transmitted, NACK received */ #define TW_MT_DATA_NACK 0x30 /** \ingroup util_twi \def TW_MT_ARB_LOST arbitration lost in SLA+W or data */ #define TW_MT_ARB_LOST 0x38 /* Master Receiver */ /** \ingroup util_twi \def TW_MR_ARB_LOST arbitration lost in SLA+R or NACK */ #define TW_MR_ARB_LOST 0x38 /** \ingroup util_twi \def TW_MR_SLA_ACK SLA+R transmitted, ACK received */ #define TW_MR_SLA_ACK 0x40 /** \ingroup util_twi \def TW_MR_SLA_NACK SLA+R transmitted, NACK received */ #define TW_MR_SLA_NACK 0x48 /** \ingroup util_twi \def TW_MR_DATA_ACK data received, ACK returned */ #define TW_MR_DATA_ACK 0x50 /** \ingroup util_twi \def TW_MR_DATA_NACK data received, NACK returned */ #define TW_MR_DATA_NACK 0x58 /* Slave Transmitter */ /** \ingroup util_twi \def TW_ST_SLA_ACK SLA+R received, ACK returned */ #define TW_ST_SLA_ACK 0xA8 /** \ingroup util_twi \def TW_ST_ARB_LOST_SLA_ACK arbitration lost in SLA+RW, SLA+R received, ACK returned */ #define TW_ST_ARB_LOST_SLA_ACK 0xB0 /** \ingroup util_twi \def TW_ST_DATA_ACK data transmitted, ACK received */ #define TW_ST_DATA_ACK 0xB8 /** \ingroup util_twi \def TW_ST_DATA_NACK data transmitted, NACK received */ #define TW_ST_DATA_NACK 0xC0 /** \ingroup util_twi \def TW_ST_LAST_DATA last data byte transmitted, ACK received */ #define TW_ST_LAST_DATA 0xC8 /* Slave Receiver */ /** \ingroup util_twi \def TW_SR_SLA_ACK SLA+W received, ACK returned */ #define TW_SR_SLA_ACK 0x60 /** \ingroup util_twi \def TW_SR_ARB_LOST_SLA_ACK arbitration lost in SLA+RW, SLA+W received, ACK returned */ #define TW_SR_ARB_LOST_SLA_ACK 0x68 /** \ingroup util_twi \def TW_SR_GCALL_ACK general call received, ACK returned */ #define TW_SR_GCALL_ACK 0x70 /** \ingroup util_twi \def TW_SR_ARB_LOST_GCALL_ACK arbitration lost in SLA+RW, general call received, ACK returned */ #define TW_SR_ARB_LOST_GCALL_ACK 0x78 /** \ingroup util_twi \def TW_SR_DATA_ACK data received, ACK returned */ #define TW_SR_DATA_ACK 0x80 /** \ingroup util_twi \def TW_SR_DATA_NACK data received, NACK returned */ #define TW_SR_DATA_NACK 0x88 /** \ingroup util_twi \def TW_SR_GCALL_DATA_ACK general call data received, ACK returned */ #define TW_SR_GCALL_DATA_ACK 0x90 /** \ingroup util_twi \def TW_SR_GCALL_DATA_NACK general call data received, NACK returned */ #define TW_SR_GCALL_DATA_NACK 0x98 /** \ingroup util_twi \def TW_SR_STOP stop or repeated start condition received while selected */ #define TW_SR_STOP 0xA0 /* Misc */ /** \ingroup util_twi \def TW_NO_INFO no state information available */ #define TW_NO_INFO 0xF8 /** \ingroup util_twi \def TW_BUS_ERROR illegal start or stop condition */ #define TW_BUS_ERROR 0x00 /** * \ingroup util_twi * \def TW_STATUS_MASK * The lower 3 bits of TWSR are reserved on the ATmega163. * The 2 LSB carry the prescaler bits on the newer ATmegas. */ #define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|\ _BV(TWS3)) /** * \ingroup util_twi * \def TW_STATUS * * TWSR, masked by TW_STATUS_MASK */ #define TW_STATUS (TWSR & TW_STATUS_MASK) /*@}*/ /** * \name R/~W bit in SLA+R/W address field. */ /*@{*/ /** \ingroup util_twi \def TW_READ SLA+R address */ #define TW_READ 1 /** \ingroup util_twi \def TW_WRITE SLA+W address */ #define TW_WRITE 0 /*@}*/ #endif /* _UTIL_TWI_H_ */ avr-libc-1.8.0.orig/include/util/parity.h0000644000000000000000000000467211732702554015144 0ustar /* Copyright (c) 2002, Marek Michalkiewicz Copyright (c) 2004,2005,2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: parity.h 1196 2007-01-23 15:34:58Z joerg_wunsch $ */ #ifndef _UTIL_PARITY_H_ #define _UTIL_PARITY_H_ /** \file */ /** \defgroup util_parity : Parity bit generation \code #include \endcode This header file contains optimized assembler code to calculate the parity bit for a byte. */ /** \def parity_even_bit \ingroup util_parity \returns 1 if \c val has an odd number of bits set. */ #define parity_even_bit(val) \ (__extension__({ \ unsigned char __t; \ __asm__ ( \ "mov __tmp_reg__,%0" "\n\t" \ "swap %0" "\n\t" \ "eor %0,__tmp_reg__" "\n\t" \ "mov __tmp_reg__,%0" "\n\t" \ "lsr %0" "\n\t" \ "lsr %0" "\n\t" \ "eor %0,__tmp_reg__" \ : "=r" (__t) \ : "0" ((unsigned char)(val)) \ : "r0" \ ); \ (((__t + 1) >> 1) & 1); \ })) #endif /* _UTIL_PARITY_H_ */ avr-libc-1.8.0.orig/include/util/atomic.h0000644000000000000000000002333011732702554015100 0ustar /* Copyright (c) 2007 Dean Camera All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: atomic.h 2158 2010-06-10 15:48:28Z joerg_wunsch $ */ #ifndef _UTIL_ATOMIC_H_ #define _UTIL_ATOMIC_H_ 1 #include #include #if !defined(__DOXYGEN__) /* Internal helper functions. */ static __inline__ uint8_t __iSeiRetVal(void) { sei(); return 1; } static __inline__ uint8_t __iCliRetVal(void) { cli(); return 1; } static __inline__ void __iSeiParam(const uint8_t *__s) { sei(); __asm__ volatile ("" ::: "memory"); (void)__s; } static __inline__ void __iCliParam(const uint8_t *__s) { cli(); __asm__ volatile ("" ::: "memory"); (void)__s; } static __inline__ void __iRestore(const uint8_t *__s) { SREG = *__s; __asm__ volatile ("" ::: "memory"); } #endif /* !__DOXYGEN__ */ /** \file */ /** \defgroup util_atomic Atomically and Non-Atomically Executed Code Blocks \code #include \endcode \note The macros in this header file require the ISO/IEC 9899:1999 ("ISO C99") feature of for loop variables that are declared inside the for loop itself. For that reason, this header file can only be used if the standard level of the compiler (option --std=) is set to either \c c99 or \c gnu99. The macros in this header file deal with code blocks that are guaranteed to be excuted Atomically or Non-Atmomically. The term "Atomic" in this context refers to the unability of the respective code to be interrupted. These macros operate via automatic manipulation of the Global Interrupt Status (I) bit of the SREG register. Exit paths from both block types are all managed automatically without the need for special considerations, i. e. the interrupt status will be restored to the same value it has been when entering the respective block. A typical example that requires atomic access is a 16 (or more) bit variable that is shared between the main execution path and an ISR. While declaring such a variable as volatile ensures that the compiler will not optimize accesses to it away, it does not guarantee atomic access to it. Assuming the following example: \code #include #include #include volatile uint16_t ctr; ISR(TIMER1_OVF_vect) { ctr--; } ... int main(void) { ... ctr = 0x200; start_timer(); while (ctr != 0) // wait ; ... } \endcode There is a chance where the main context will exit its wait loop when the variable \c ctr just reached the value 0xFF. This happens because the compiler cannot natively access a 16-bit variable atomically in an 8-bit CPU. So the variable is for example at 0x100, the compiler then tests the low byte for 0, which succeeds. It then proceeds to test the high byte, but that moment the ISR triggers, and the main context is interrupted. The ISR will decrement the variable from 0x100 to 0xFF, and the main context proceeds. It now tests the high byte of the variable which is (now) also 0, so it concludes the variable has reached 0, and terminates the loop. Using the macros from this header file, the above code can be rewritten like: \code #include #include #include #include volatile uint16_t ctr; ISR(TIMER1_OVF_vect) { ctr--; } ... int main(void) { ... ctr = 0x200; start_timer(); sei(); uint16_t ctr_copy; do { ATOMIC_BLOCK(ATOMIC_FORCEON) { ctr_copy = ctr; } } while (ctr_copy != 0); ... } \endcode This will install the appropriate interrupt protection before accessing variable \c ctr, so it is guaranteed to be consistently tested. If the global interrupt state were uncertain before entering the ATOMIC_BLOCK, it should be executed with the parameter ATOMIC_RESTORESTATE rather than ATOMIC_FORCEON. See \ref optim_code_reorder for things to be taken into account with respect to compiler optimizations. */ /** \def ATOMIC_BLOCK(type) \ingroup util_atomic Creates a block of code that is guaranteed to be executed atomically. Upon entering the block the Global Interrupt Status flag in SREG is disabled, and re-enabled upon exiting the block from any exit path. Two possible macro parameters are permitted, ATOMIC_RESTORESTATE and ATOMIC_FORCEON. */ #if defined(__DOXYGEN__) #define ATOMIC_BLOCK(type) #else #define ATOMIC_BLOCK(type) for ( type, __ToDo = __iCliRetVal(); \ __ToDo ; __ToDo = 0 ) #endif /* __DOXYGEN__ */ /** \def NONATOMIC_BLOCK(type) \ingroup util_atomic Creates a block of code that is executed non-atomically. Upon entering the block the Global Interrupt Status flag in SREG is enabled, and disabled upon exiting the block from any exit path. This is useful when nested inside ATOMIC_BLOCK sections, allowing for non-atomic execution of small blocks of code while maintaining the atomic access of the other sections of the parent ATOMIC_BLOCK. Two possible macro parameters are permitted, NONATOMIC_RESTORESTATE and NONATOMIC_FORCEOFF. */ #if defined(__DOXYGEN__) #define NONATOMIC_BLOCK(type) #else #define NONATOMIC_BLOCK(type) for ( type, __ToDo = __iSeiRetVal(); \ __ToDo ; __ToDo = 0 ) #endif /* __DOXYGEN__ */ /** \def ATOMIC_RESTORESTATE \ingroup util_atomic This is a possible parameter for ATOMIC_BLOCK. When used, it will cause the ATOMIC_BLOCK to restore the previous state of the SREG register, saved before the Global Interrupt Status flag bit was disabled. The net effect of this is to make the ATOMIC_BLOCK's contents guaranteed atomic, without changing the state of the Global Interrupt Status flag when execution of the block completes. */ #if defined(__DOXYGEN__) #define ATOMIC_RESTORESTATE #else #define ATOMIC_RESTORESTATE uint8_t sreg_save \ __attribute__((__cleanup__(__iRestore))) = SREG #endif /* __DOXYGEN__ */ /** \def ATOMIC_FORCEON \ingroup util_atomic This is a possible parameter for ATOMIC_BLOCK. When used, it will cause the ATOMIC_BLOCK to force the state of the SREG register on exit, enabling the Global Interrupt Status flag bit. This saves on flash space as the previous value of the SREG register does not need to be saved at the start of the block. Care should be taken that ATOMIC_FORCEON is only used when it is known that interrupts are enabled before the block's execution or when the side effects of enabling global interrupts at the block's completion are known and understood. */ #if defined(__DOXYGEN__) #define ATOMIC_FORCEON #else #define ATOMIC_FORCEON uint8_t sreg_save \ __attribute__((__cleanup__(__iSeiParam))) = 0 #endif /* __DOXYGEN__ */ /** \def NONATOMIC_RESTORESTATE \ingroup util_atomic This is a possible parameter for NONATOMIC_BLOCK. When used, it will cause the NONATOMIC_BLOCK to restore the previous state of the SREG register, saved before the Global Interrupt Status flag bit was enabled. The net effect of this is to make the NONATOMIC_BLOCK's contents guaranteed non-atomic, without changing the state of the Global Interrupt Status flag when execution of the block completes. */ #if defined(__DOXYGEN__) #define NONATOMIC_RESTORESTATE #else #define NONATOMIC_RESTORESTATE uint8_t sreg_save \ __attribute__((__cleanup__(__iRestore))) = SREG #endif /* __DOXYGEN__ */ /** \def NONATOMIC_FORCEOFF \ingroup util_atomic This is a possible parameter for NONATOMIC_BLOCK. When used, it will cause the NONATOMIC_BLOCK to force the state of the SREG register on exit, disabling the Global Interrupt Status flag bit. This saves on flash space as the previous value of the SREG register does not need to be saved at the start of the block. Care should be taken that NONATOMIC_FORCEOFF is only used when it is known that interrupts are disabled before the block's execution or when the side effects of disabling global interrupts at the block's completion are known and understood. */ #if defined(__DOXYGEN__) #define NONATOMIC_FORCEOFF #else #define NONATOMIC_FORCEOFF uint8_t sreg_save \ __attribute__((__cleanup__(__iCliParam))) = 0 #endif /* __DOXYGEN__ */ #endif avr-libc-1.8.0.orig/include/util/setbaud.h0000644000000000000000000001474111732702554015261 0ustar /* Copyright (c) 2007 Cliff Lawson Copyright (c) 2007 Carlos Lamas All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: setbaud.h 2134 2010-06-08 11:19:48Z joerg_wunsch $ */ /** \file */ /** \defgroup util_setbaud : Helper macros for baud rate calculations \code #define F_CPU 11059200 #define BAUD 38400 #include \endcode This header file requires that on entry values are already defined for F_CPU and BAUD. In addition, the macro BAUD_TOL will define the baud rate tolerance (in percent) that is acceptable during the calculations. The value of BAUD_TOL will default to 2 %. This header file defines macros suitable to setup the UART baud rate prescaler registers of an AVR. All calculations are done using the C preprocessor. Including this header file causes no other side effects so it is possible to include this file more than once (supposedly, with different values for the BAUD parameter), possibly even within the same function. Assuming that the requested BAUD is valid for the given F_CPU then the macro UBRR_VALUE is set to the required prescaler value. Two additional macros are provided for the low and high bytes of the prescaler, respectively: UBRRL_VALUE is set to the lower byte of the UBRR_VALUE and UBRRH_VALUE is set to the upper byte. An additional macro USE_2X will be defined. Its value is set to 1 if the desired BAUD rate within the given tolerance could only be achieved by setting the U2X bit in the UART configuration. It will be defined to 0 if U2X is not needed. Example usage: \code #include #define F_CPU 4000000 static void uart_9600(void) { #define BAUD 9600 #include UBRRH = UBRRH_VALUE; UBRRL = UBRRL_VALUE; #if USE_2X UCSRA |= (1 << U2X); #else UCSRA &= ~(1 << U2X); #endif } static void uart_38400(void) { #undef BAUD // avoid compiler warning #define BAUD 38400 #include UBRRH = UBRRH_VALUE; UBRRL = UBRRL_VALUE; #if USE_2X UCSRA |= (1 << U2X); #else UCSRA &= ~(1 << U2X); #endif } \endcode In this example, two functions are defined to setup the UART to run at 9600 Bd, and 38400 Bd, respectively. Using a CPU clock of 4 MHz, 9600 Bd can be achieved with an acceptable tolerance without setting U2X (prescaler 25), while 38400 Bd require U2X to be set (prescaler 12). */ #ifndef F_CPU # error "setbaud.h requires F_CPU to be defined" #endif #ifndef BAUD # error "setbaud.h requires BAUD to be defined" #endif #if !(F_CPU) # error "F_CPU must be a constant value" #endif #if !(BAUD) # error "BAUD must be a constant value" #endif #if defined(__DOXYGEN__) /** \def BAUD_TOL \ingroup util_setbaud Input and output macro for Define the acceptable baud rate tolerance in percent. If not set on entry, it will be set to its default value of 2. */ #define BAUD_TOL 2 /** \def UBRR_VALUE \ingroup util_setbaud Output macro from Contains the calculated baud rate prescaler value for the UBRR register. */ #define UBRR_VALUE /** \def UBRRL_VALUE \ingroup util_setbaud Output macro from Contains the lower byte of the calculated prescaler value (UBRR_VALUE). */ #define UBRRL_VALUE /** \def UBRRH_VALUE \ingroup util_setbaud Output macro from Contains the upper byte of the calculated prescaler value (UBRR_VALUE). */ #define UBRRH_VALUE /** \def USE_2X \ingroup util_setbaud Output bacro from Contains the value 1 if the desired baud rate tolerance could only be achieved by setting the U2X bit in the UART configuration. Contains 0 otherwise. */ #define USE_2X 0 #else /* !__DOXYGEN__ */ #undef USE_2X /* Baud rate tolerance is 2 % unless previously defined */ #ifndef BAUD_TOL # define BAUD_TOL 2 #endif #ifdef __ASSEMBLER__ #define UBRR_VALUE (((F_CPU) + 8 * (BAUD)) / (16 * (BAUD)) -1) #else #define UBRR_VALUE (((F_CPU) + 8UL * (BAUD)) / (16UL * (BAUD)) -1UL) #endif #if 100 * (F_CPU) > \ (16 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) + (BAUD) * (BAUD_TOL)) # define USE_2X 1 #elif 100 * (F_CPU) < \ (16 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) - (BAUD) * (BAUD_TOL)) # define USE_2X 1 #else # define USE_2X 0 #endif #if USE_2X /* U2X required, recalculate */ #undef UBRR_VALUE #ifdef __ASSEMBLER__ #define UBRR_VALUE (((F_CPU) + 4 * (BAUD)) / (8 * (BAUD)) -1) #else #define UBRR_VALUE (((F_CPU) + 4UL * (BAUD)) / (8UL * (BAUD)) -1UL) #endif #if 100 * (F_CPU) > \ (8 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) + (BAUD) * (BAUD_TOL)) # warning "Baud rate achieved is higher than allowed" #endif #if 100 * (F_CPU) < \ (8 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) - (BAUD) * (BAUD_TOL)) # warning "Baud rate achieved is lower than allowed" #endif #endif /* USE_U2X */ #ifdef UBRR_VALUE # define UBRRL_VALUE (UBRR_VALUE & 0xff) # define UBRRH_VALUE (UBRR_VALUE >> 8) #endif #endif /* __DOXYGEN__ */ /* end of util/setbaud.h */ avr-libc-1.8.0.orig/include/util/Makefile.am0000644000000000000000000000343011732702554015506 0ustar # Copyright (c) 2005,2007 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 2103 2010-03-17 05:16:10Z joerg_wunsch $ # avrdir = $(prefix)/avr/include/util avr_HEADERS = \ atomic.h \ crc16.h \ delay_basic.h \ setbaud.h \ parity.h \ twi.h nodist_avr_HEADERS = \ delay.h EXTRA_DIST = \ delay.h.in avr-libc-1.8.0.orig/include/util/delay.h.in0000644000000000000000000002161411732702554015332 0ustar /* Copyright (c) 2002, Marek Michalkiewicz Copyright (c) 2004,2005,2007 Joerg Wunsch Copyright (c) 2007 Florin-Viorel Petrov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: delay.h.in 2251 2011-09-14 08:20:33Z joerg_wunsch $ */ #ifndef _UTIL_DELAY_H_ #define _UTIL_DELAY_H_ 1 #ifndef __HAS_DELAY_CYCLES #define __HAS_DELAY_CYCLES @HAS_DELAY_CYCLES@ #endif #include #include #include /** \file */ /** \defgroup util_delay : Convenience functions for busy-wait delay loops \code #define F_CPU 1000000UL // 1 MHz //#define F_CPU 14.7456E6 #include \endcode \note As an alternative method, it is possible to pass the F_CPU macro down to the compiler from the Makefile. Obviously, in that case, no \c \#define statement should be used. The functions in this header file are wrappers around the basic busy-wait functions from . They are meant as convenience functions where actual time values can be specified rather than a number of cycles to wait for. The idea behind is that compile-time constant expressions will be eliminated by compiler optimization so floating-point expressions can be used to calculate the number of delay cycles needed based on the CPU frequency passed by the macro F_CPU. \note In order for these functions to work as intended, compiler optimizations must be enabled, and the delay time must be an expression that is a known constant at compile-time. If these requirements are not met, the resulting delay will be much longer (and basically unpredictable), and applications that otherwise do not use floating-point calculations will experience severe code bloat by the floating-point library routines linked into the application. The functions available allow the specification of microsecond, and millisecond delays directly, using the application-supplied macro F_CPU as the CPU clock frequency (in Hertz). */ #if !defined(__DOXYGEN__) static inline void _delay_us(double __us) __attribute__((always_inline)); static inline void _delay_ms(double __ms) __attribute__((always_inline)); #endif #ifndef F_CPU /* prevent compiler error by supplying a default */ # warning "F_CPU not defined for " # define F_CPU 1000000UL #endif #ifndef __OPTIMIZE__ # warning "Compiler optimizations disabled; functions from won't work as designed" #endif #if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && \ !defined(__DELAY_BACKWARD_COMPATIBLE__) && \ __STDC_HOSTED__ # include #endif /** \ingroup util_delay Perform a delay of \c __ms milliseconds, using _delay_loop_2(). The macro F_CPU is supposed to be defined to a constant defining the CPU clock frequency (in Hertz). The maximal possible delay is 262.14 ms / F_CPU in MHz. When the user request delay which exceed the maximum possible one, _delay_ms() provides a decreased resolution functionality. In this mode _delay_ms() will work with a resolution of 1/10 ms, providing delays up to 6.5535 seconds (independent from CPU frequency). The user will not be informed about decreased resolution. If the avr-gcc toolchain has __builtin_avr_delay_cycles(unsigned long) support, maximal possible delay is 4294967.295 ms/ F_CPU in MHz. For values greater than the maximal possible delay, overflows results in no delay i.e., 0ms. Conversion of __us into clock cycles may not always result in integer. By default, the clock cycles rounded up to next integer. This ensures that the user gets atleast __us microseconds of delay. Alternatively, user can define __DELAY_ROUND_DOWN__ and __DELAY_ROUND_CLOSEST__ to round down and round to closest integer. Note: The new implementation of _delay_ms(double __ms) with __builtin_avr_delay_cycles(unsigned long) support is not backward compatible. User can define __DELAY_BACKWARD_COMPATIBLE__ to get a backward compatible delay. Also, the backward compatible algorithm will be chosen if the code is compiled in a freestanding environment (GCC option \c -ffreestanding), as the math functions required for rounding are not available to the compiler then. */ void _delay_ms(double __ms) { uint16_t __ticks; double __tmp ; #if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && \ !defined(__DELAY_BACKWARD_COMPATIBLE__) && \ __STDC_HOSTED__ uint32_t __ticks_dc; extern void __builtin_avr_delay_cycles(unsigned long); __tmp = ((F_CPU) / 1e3) * __ms; #if defined(__DELAY_ROUND_DOWN__) __ticks_dc = (uint32_t)fabs(__tmp); #elif defined(__DELAY_ROUND_CLOSEST__) __ticks_dc = (uint32_t)(fabs(__tmp)+0.5); #else //round up by default __ticks_dc = (uint32_t)(ceil(fabs(__tmp))); #endif __builtin_avr_delay_cycles(__ticks_dc); #else __tmp = ((F_CPU) / 4e3) * __ms; if (__tmp < 1.0) __ticks = 1; else if (__tmp > 65535) { // __ticks = requested delay in 1/10 ms __ticks = (uint16_t) (__ms * 10.0); while(__ticks) { // wait 1/10 ms _delay_loop_2(((F_CPU) / 4e3) / 10); __ticks --; } return; } else __ticks = (uint16_t)__tmp; _delay_loop_2(__ticks); #endif } /** \ingroup util_delay Perform a delay of \c __us microseconds, using _delay_loop_1(). The macro F_CPU is supposed to be defined to a constant defining the CPU clock frequency (in Hertz). The maximal possible delay is 768 us / F_CPU in MHz. If the user requests a delay greater than the maximal possible one, _delay_us() will automatically call _delay_ms() instead. The user will not be informed about this case. If the avr-gcc toolchain has __builtin_avr_delay_cycles(unsigned long) support, maximal possible delay is 4294967.295 us/ F_CPU in MHz. For values greater than the maximal possible delay, overflow results in no delay i.e., 0us. Conversion of __us into clock cycles may not always result in integer. By default, the clock cycles rounded up to next integer. This ensures that the user gets atleast __us microseconds of delay. Alternatively, user can define __DELAY_ROUND_DOWN__ and __DELAY_ROUND_CLOSEST__ to round down and round to closest integer. Note: The new implementation of _delay_us(double __us) with __builtin_avr_delay_cycles(unsigned long) support is not backward compatible. User can define __DELAY_BACKWARD_COMPATIBLE__ to get a backward compatible delay. Also, the backward compatible algorithm will be chosen if the code is compiled in a freestanding environment (GCC option \c -ffreestanding), as the math functions required for rounding are not available to the compiler then. */ void _delay_us(double __us) { uint8_t __ticks; double __tmp ; #if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && \ !defined(__DELAY_BACKWARD_COMPATIBLE__) && \ __STDC_HOSTED__ uint32_t __ticks_dc; extern void __builtin_avr_delay_cycles(unsigned long); __tmp = ((F_CPU) / 1e6) * __us; #if defined(__DELAY_ROUND_DOWN__) __ticks_dc = (uint32_t)fabs(__tmp); #elif defined(__DELAY_ROUND_CLOSEST__) __ticks_dc = (uint32_t)(fabs(__tmp)+0.5); #else //round up by default __ticks_dc = (uint32_t)(ceil(fabs(__tmp))); #endif __builtin_avr_delay_cycles(__ticks_dc); #else __tmp = ((F_CPU) / 3e6) * __us; if (__tmp < 1.0) __ticks = 1; else if (__tmp > 255) { _delay_ms(__us / 1000.0); return; } else __ticks = (uint8_t)__tmp; _delay_loop_1(__ticks); #endif } #endif /* _UTIL_DELAY_H_ */ avr-libc-1.8.0.orig/include/setjmp.h0000644000000000000000000001156711732702554014162 0ustar /* Copyright (c) 2002,2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: setjmp.h 1656 2008-03-24 11:29:55Z dmix $ */ #ifndef __SETJMP_H_ #define __SETJMP_H_ 1 #ifdef __cplusplus extern "C" { #endif /* jmp_buf: offset size description 0 16 call-saved registers (r2-r17) 16 2 frame pointer (r29:r28) 18 2 stack pointer (SPH:SPL) 20 1 status register (SREG) 21 2/3 return address (PC) (2 bytes used for <=128Kw flash) 23/24 = total size */ #if !defined(__DOXYGEN__) #if defined(__AVR_3_BYTE_PC__) && __AVR_3_BYTE_PC__ # define _JBLEN 24 #else # define _JBLEN 23 #endif typedef struct _jmp_buf { unsigned char _jb[_JBLEN]; } jmp_buf[1]; #endif /* not __DOXYGEN__ */ /** \file */ /** \defgroup setjmp : Non-local goto While the C language has the dreaded \c goto statement, it can only be used to jump to a label in the same (local) function. In order to jump directly to another (non-local) function, the C library provides the setjmp() and longjmp() functions. setjmp() and longjmp() are useful for dealing with errors and interrupts encountered in a low-level subroutine of a program. \note setjmp() and longjmp() make programs hard to understand and maintain. If possible, an alternative should be used. \note longjmp() can destroy changes made to global register variables (see \ref faq_regbind). For a very detailed discussion of setjmp()/longjmp(), see Chapter 7 of Advanced Programming in the UNIX Environment, by W. Richard Stevens. Example: \code #include jmp_buf env; int main (void) { if (setjmp (env)) { ... handle error ... } while (1) { ... main processing loop which calls foo() some where ... } } ... void foo (void) { ... blah, blah, blah ... if (err) { longjmp (env, 1); } } \endcode */ #ifndef __ATTR_NORETURN__ #define __ATTR_NORETURN__ __attribute__((__noreturn__)) #endif /** \ingroup setjmp \brief Save stack context for non-local goto. \code #include \endcode setjmp() saves the stack context/environment in \e __jmpb for later use by longjmp(). The stack context will be invalidated if the function which called setjmp() returns. \param __jmpb Variable of type \c jmp_buf which holds the stack information such that the environment can be restored. \returns setjmp() returns 0 if returning directly, and non-zero when returning from longjmp() using the saved context. */ extern int setjmp(jmp_buf __jmpb); /** \ingroup setjmp \brief Non-local jump to a saved stack context. \code #include \endcode longjmp() restores the environment saved by the last call of setjmp() with the corresponding \e __jmpb argument. After longjmp() is completed, program execution continues as if the corresponding call of setjmp() had just returned the value \e __ret. \note longjmp() cannot cause 0 to be returned. If longjmp() is invoked with a second argument of 0, 1 will be returned instead. \param __jmpb Information saved by a previous call to setjmp(). \param __ret Value to return to the caller of setjmp(). \returns This function never returns. */ extern void longjmp(jmp_buf __jmpb, int __ret) __ATTR_NORETURN__; #ifdef __cplusplus } #endif #endif /* !__SETJMP_H_ */ avr-libc-1.8.0.orig/include/math.h0000644000000000000000000003643011732702554013605 0ustar /* Copyright (c) 2002,2007-2009 Michael Stumpf Portions of documentation Copyright (c) 1990 - 1994 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: math.h 2264 2011-12-25 01:16:55Z dmix $ */ /* math.h - mathematical functions Author : Michael Stumpf Michael.Stumpf@t-online.de __ATTR_CONST__ added by marekm@linux.org.pl for functions that "do not examine any values except their arguments, and have no effects except the return value", for better optimization by gcc. */ #ifndef __MATH_H #define __MATH_H /** \file */ /** \defgroup avr_math : Mathematics \code #include \endcode This header file declares basic mathematics constants and functions. \par Notes: - In order to access the functions declared herein, it is usually also required to additionally link against the library \c libm.a. See also the related \ref faq_libm "FAQ entry". - Math functions do not raise exceptions and do not change the \c errno variable. Therefore the majority of them are declared with const attribute, for better optimization by GCC. */ /** \ingroup avr_math */ /*@{*/ /** The constant \a e. */ #define M_E 2.7182818284590452354 /** The logarithm of the \a e to base 2. */ #define M_LOG2E 1.4426950408889634074 /* log_2 e */ /** The logarithm of the \a e to base 10. */ #define M_LOG10E 0.43429448190325182765 /* log_10 e */ /** The natural logarithm of the 2. */ #define M_LN2 0.69314718055994530942 /* log_e 2 */ /** The natural logarithm of the 10. */ #define M_LN10 2.30258509299404568402 /* log_e 10 */ /** The constant \a pi. */ #define M_PI 3.14159265358979323846 /* pi */ /** The constant \a pi/2. */ #define M_PI_2 1.57079632679489661923 /* pi/2 */ /** The constant \a pi/4. */ #define M_PI_4 0.78539816339744830962 /* pi/4 */ /** The constant \a 1/pi. */ #define M_1_PI 0.31830988618379067154 /* 1/pi */ /** The constant \a 2/pi. */ #define M_2_PI 0.63661977236758134308 /* 2/pi */ /** The constant \a 2/sqrt(pi). */ #define M_2_SQRTPI 1.12837916709551257390 /* 2/sqrt(pi) */ /** The square root of 2. */ #define M_SQRT2 1.41421356237309504880 /* sqrt(2) */ /** The constant \a 1/sqrt(2). */ #define M_SQRT1_2 0.70710678118654752440 /* 1/sqrt(2) */ /** NAN constant. */ #define NAN __builtin_nan("") /** INFINITY constant. */ #define INFINITY __builtin_inf() #ifndef __ATTR_CONST__ # define __ATTR_CONST__ __attribute__((__const__)) #endif #ifdef __cplusplus extern "C" { #endif /** The cos() function returns the cosine of \a __x, measured in radians. */ extern double cos(double __x) __ATTR_CONST__; #define cosf cos /**< The alias for cos(). */ /** The sin() function returns the sine of \a __x, measured in radians. */ extern double sin(double __x) __ATTR_CONST__; #define sinf sin /**< The alias for sin(). */ /** The tan() function returns the tangent of \a __x, measured in radians. */ extern double tan(double __x) __ATTR_CONST__; #define tanf tan /**< The alias for tan(). */ /** The fabs() function computes the absolute value of a floating-point number \a __x. */ extern double fabs(double __x) __ATTR_CONST__; #define fabsf fabs /**< The alias for fabs(). */ /** The function fmod() returns the floating-point remainder of __x / __y. */ extern double fmod(double __x, double __y) __ATTR_CONST__; #define fmodf fmod /**< The alias for fmod(). */ /** The modf() function breaks the argument \a __x into integral and fractional parts, each of which has the same sign as the argument. It stores the integral part as a double in the object pointed to by \a __iptr. The modf() function returns the signed fractional part of \a __x. \note This implementation skips writing by zero pointer. However, the GCC 4.3 can replace this function with inline code that does not permit to use NULL address for the avoiding of storing. */ extern double modf(double __x, double *__iptr); /** The alias for modf(). */ extern float modff (float __x, float *__iptr); /** The sqrt() function returns the non-negative square root of \a __x. */ extern double sqrt(double __x) __ATTR_CONST__; #define sqrtf sqrt /**< The alias for sqrt(). */ /** The cbrt() function returns the cube root of \a __x. */ extern double cbrt(double __x) __ATTR_CONST__; #define cbrtf cbrt /**< The alias for cbrt(). */ /** The hypot() function returns sqrt(__x*__x + __y*__y). This is the length of the hypotenuse of a right triangle with sides of length \a __x and \a __y, or the distance of the point (\a __x, \a __y) from the origin. Using this function instead of the direct formula is wise, since the error is much smaller. No underflow with small \a __x and \a __y. No overflow if result is in range. */ extern double hypot (double __x, double __y) __ATTR_CONST__; #define hypotf hypot /**< The alias for hypot(). */ /** The function square() returns __x * __x. \note This function does not belong to the C standard definition. */ extern double square(double __x) __ATTR_CONST__; #define squaref square /**< The alias for square(). */ /** The floor() function returns the largest integral value less than or equal to \a __x, expressed as a floating-point number. */ extern double floor(double __x) __ATTR_CONST__; #define floorf floor /**< The alias for floor(). */ /** The ceil() function returns the smallest integral value greater than or equal to \a __x, expressed as a floating-point number. */ extern double ceil(double __x) __ATTR_CONST__; #define ceilf ceil /**< The alias for ceil(). */ /** The frexp() function breaks a floating-point number into a normalized fraction and an integral power of 2. It stores the integer in the \c int object pointed to by \a __pexp. If \a __x is a normal float point number, the frexp() function returns the value \c v, such that \c v has a magnitude in the interval [1/2, 1) or zero, and \a __x equals \c v times 2 raised to the power \a __pexp. If \a __x is zero, both parts of the result are zero. If \a __x is not a finite number, the frexp() returns \a __x as is and stores 0 by \a __pexp. \note This implementation permits a zero pointer as a directive to skip a storing the exponent. */ extern double frexp(double __x, int *__pexp); #define frexpf frexp /**< The alias for frexp(). */ /** The ldexp() function multiplies a floating-point number by an integral power of 2. It returns the value of \a __x times 2 raised to the power \a __exp. */ extern double ldexp(double __x, int __exp) __ATTR_CONST__; #define ldexpf ldexp /**< The alias for ldexp(). */ /** The exp() function returns the exponential value of \a __x. */ extern double exp(double __x) __ATTR_CONST__; #define expf exp /**< The alias for exp(). */ /** The cosh() function returns the hyperbolic cosine of \a __x. */ extern double cosh(double __x) __ATTR_CONST__; #define coshf cosh /**< The alias for cosh(). */ /** The sinh() function returns the hyperbolic sine of \a __x. */ extern double sinh(double __x) __ATTR_CONST__; #define sinhf sinh /**< The alias for sinh(). */ /** The tanh() function returns the hyperbolic tangent of \a __x. */ extern double tanh(double __x) __ATTR_CONST__; #define tanhf tanh /**< The alias for tanh(). */ /** The acos() function computes the principal value of the arc cosine of \a __x. The returned value is in the range [0, pi] radians. A domain error occurs for arguments not in the range [-1, +1]. */ extern double acos(double __x) __ATTR_CONST__; #define acosf acos /**< The alias for acos(). */ /** The asin() function computes the principal value of the arc sine of \a __x. The returned value is in the range [-pi/2, pi/2] radians. A domain error occurs for arguments not in the range [-1, +1]. */ extern double asin(double __x) __ATTR_CONST__; #define asinf asin /**< The alias for asin(). */ /** The atan() function computes the principal value of the arc tangent of \a __x. The returned value is in the range [-pi/2, pi/2] radians. */ extern double atan(double __x) __ATTR_CONST__; #define atanf atan /**< The alias for atan(). */ /** The atan2() function computes the principal value of the arc tangent of __y / __x, using the signs of both arguments to determine the quadrant of the return value. The returned value is in the range [-pi, +pi] radians. */ extern double atan2(double __y, double __x) __ATTR_CONST__; #define atan2f atan2 /**< The alias for atan2(). */ /** The log() function returns the natural logarithm of argument \a __x. */ extern double log(double __x) __ATTR_CONST__; #define logf log /**< The alias for log(). */ /** The log10() function returns the logarithm of argument \a __x to base 10. */ extern double log10(double __x) __ATTR_CONST__; #define log10f log10 /**< The alias for log10(). */ /** The function pow() returns the value of \a __x to the exponent \a __y. */ extern double pow(double __x, double __y) __ATTR_CONST__; #define powf pow /**< The alias for pow(). */ /** The function isnan() returns 1 if the argument \a __x represents a "not-a-number" (NaN) object, otherwise 0. */ extern int isnan(double __x) __ATTR_CONST__; #define isnanf isnan /**< The alias for isnan(). */ /** The function isinf() returns 1 if the argument \a __x is positive infinity, -1 if \a __x is negative infinity, and 0 otherwise. \note The GCC 4.3 can replace this function with inline code that returns the 1 value for both infinities (gcc bug #35509). */ extern int isinf(double __x) __ATTR_CONST__; #define isinff isinf /**< The alias for isinf(). */ /** The isfinite() function returns a nonzero value if \a __x is finite: not plus or minus infinity, and not NaN. */ __ATTR_CONST__ static inline int isfinite (double __x) { unsigned char __exp; __asm__ ( "mov %0, %C1 \n\t" "lsl %0 \n\t" "mov %0, %D1 \n\t" "rol %0 " : "=r" (__exp) : "r" (__x) ); return __exp != 0xff; } #define isfinitef isfinite /**< The alias for isfinite(). */ /** The copysign() function returns \a __x but with the sign of \a __y. They work even if \a __x or \a __y are NaN or zero. */ __ATTR_CONST__ static inline double copysign (double __x, double __y) { __asm__ ( "bst %D2, 7 \n\t" "bld %D0, 7 " : "=r" (__x) : "0" (__x), "r" (__y) ); return __x; } #define copysignf copysign /**< The alias for copysign(). */ /** The signbit() function returns a nonzero value if the value of \a __x has its sign bit set. This is not the same as `\a __x < 0.0', because IEEE 754 floating point allows zero to be signed. The comparison `-0.0 < 0.0' is false, but `signbit (-0.0)' will return a nonzero value. */ extern int signbit (double __x) __ATTR_CONST__; #define signbitf signbit /**< The alias for signbit(). */ /** The fdim() function returns max(__x - __y, 0). If \a __x or \a __y or both are NaN, NaN is returned. */ extern double fdim (double __x, double __y) __ATTR_CONST__; #define fdimf fdim /**< The alias for fdim(). */ /** The fma() function performs floating-point multiply-add. This is the operation (__x * __y) + __z, but the intermediate result is not rounded to the destination type. This can sometimes improve the precision of a calculation. */ extern double fma (double __x, double __y, double __z) __ATTR_CONST__; #define fmaf fma /**< The alias for fma(). */ /** The fmax() function returns the greater of the two values \a __x and \a __y. If an argument is NaN, the other argument is returned. If both arguments are NaN, NaN is returned. */ extern double fmax (double __x, double __y) __ATTR_CONST__; #define fmaxf fmax /**< The alias for fmax(). */ /** The fmin() function returns the lesser of the two values \a __x and \a __y. If an argument is NaN, the other argument is returned. If both arguments are NaN, NaN is returned. */ extern double fmin (double __x, double __y) __ATTR_CONST__; #define fminf fmin /**< The alias for fmin(). */ /** The trunc() function rounds \a __x to the nearest integer not larger in absolute value. */ extern double trunc (double __x) __ATTR_CONST__; #define truncf trunc /**< The alias for trunc(). */ /** The round() function rounds \a __x to the nearest integer, but rounds halfway cases away from zero (instead of to the nearest even integer). Overflow is impossible. \return The rounded value. If \a __x is an integral or infinite, \a __x itself is returned. If \a __x is \c NaN, then \c NaN is returned. */ extern double round (double __x) __ATTR_CONST__; #define roundf round /**< The alias for round(). */ /** The lround() function rounds \a __x to the nearest integer, but rounds halfway cases away from zero (instead of to the nearest even integer). This function is similar to round() function, but it differs in type of return value and in that an overflow is possible. \return The rounded long integer value. If \a __x is not a finite number or an overflow was, this realization returns the \c LONG_MIN value (0x80000000). */ extern long lround (double __x) __ATTR_CONST__; #define lroundf lround /**< The alias for lround(). */ /** The lrint() function rounds \a __x to the nearest integer, rounding the halfway cases to the even integer direction. (That is both 1.5 and 2.5 values are rounded to 2). This function is similar to rint() function, but it differs in type of return value and in that an overflow is possible. \return The rounded long integer value. If \a __x is not a finite number or an overflow was, this realization returns the \c LONG_MIN value (0x80000000). */ extern long lrint (double __x) __ATTR_CONST__; #define lrintf lrint /**< The alias for lrint(). */ #ifdef __cplusplus } #endif /*@}*/ #endif /* !__MATH_H */ avr-libc-1.8.0.orig/include/Makefile.am0000644000000000000000000000346111732702554014535 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 1406 2007-07-01 07:13:16Z joerg_wunsch $ # avrdir = $(prefix)/avr/include avr_HEADERS = \ alloca.h \ assert.h \ ctype.h \ errno.h \ inttypes.h \ math.h \ setjmp.h \ stdint.h \ stdio.h \ stdlib.h \ string.h SUBDIRS = avr compat util avr-libc-1.8.0.orig/include/ctype.h0000644000000000000000000001234611732702554014000 0ustar /* Copyright (c) 2002,2007 Michael Stumpf All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ctype.h 1504 2007-12-16 07:34:00Z dmix $ */ /* ctype.h - character conversion macros and ctype macros Author : Michael Stumpf Michael.Stumpf@t-online.de */ #ifndef __CTYPE_H_ #define __CTYPE_H_ 1 #ifndef __ATTR_CONST__ #define __ATTR_CONST__ __attribute__((__const__)) #endif #ifdef __cplusplus extern "C" { #endif /** \file */ /** \defgroup ctype : Character Operations These functions perform various operations on characters. \code #include \endcode */ /** \name Character classification routines These functions perform character classification. They return true or false status depending whether the character passed to the function falls into the function's classification (i.e. isdigit() returns true if its argument is any value '0' though '9', inclusive). If the input is not an unsigned char value, all of this function return false. */ /* @{ */ /** \ingroup ctype Checks for an alphanumeric character. It is equivalent to (isalpha(c) || isdigit(c)). */ extern int isalnum(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for an alphabetic character. It is equivalent to (isupper(c) || islower(c)). */ extern int isalpha(int __c) __ATTR_CONST__; /** \ingroup ctype Checks whether \c c is a 7-bit unsigned char value that fits into the ASCII character set. */ extern int isascii(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for a blank character, that is, a space or a tab. */ extern int isblank(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for a control character. */ extern int iscntrl(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for a digit (0 through 9). */ extern int isdigit(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for any printable character except space. */ extern int isgraph(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for a lower-case character. */ extern int islower(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for any printable character including space. */ extern int isprint(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for any printable character which is not a space or an alphanumeric character. */ extern int ispunct(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for white-space characters. For the avr-libc library, these are: space, form-feed ('\\f'), newline ('\\n'), carriage return ('\\r'), horizontal tab ('\\t'), and vertical tab ('\\v'). */ extern int isspace(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for an uppercase letter. */ extern int isupper(int __c) __ATTR_CONST__; /** \ingroup ctype Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 8 9 a b c d e f A B C D E F. */ extern int isxdigit(int __c) __ATTR_CONST__; /* @} */ /** \name Character convertion routines This realization permits all possible values of integer argument. The toascii() function clears all highest bits. The tolower() and toupper() functions return an input argument as is, if it is not an unsigned char value. */ /* @{ */ /** \ingroup ctype Converts \c c to a 7-bit unsigned char value that fits into the ASCII character set, by clearing the high-order bits. \warning Many people will be unhappy if you use this function. This function will convert accented letters into random characters. */ extern int toascii(int __c) __ATTR_CONST__; /** \ingroup ctype Converts the letter \c c to lower case, if possible. */ extern int tolower(int __c) __ATTR_CONST__; /** \ingroup ctype Converts the letter \c c to upper case, if possible. */ extern int toupper(int __c) __ATTR_CONST__; /* @} */ #ifdef __cplusplus } #endif #endif avr-libc-1.8.0.orig/include/avr/0000755000000000000000000000000011732702554013265 5ustar avr-libc-1.8.0.orig/include/avr/iotn44a.h0000644000000000000000000004215411732702554014726 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn44a.h 2035 2009-11-02 02:44:17Z arcanum $ */ /* avr/iotn44a.h - definitions for ATtiny44A */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn44a.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny44A_H_ #define _AVR_ATtiny44A_H_ 1 /* Registers and associated bit numbers. */ #define PRR _SFR_IO8(0x00) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define DIDR0 _SFR_IO8(0x01) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define ADCSRB _SFR_IO8(0x03) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADLAR 4 #define ACME 6 #define BIN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x05) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define MUX5 5 #define REFS0 6 #define REFS1 7 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define TIFR1 _SFR_IO8(0x0B) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIMSK1 _SFR_IO8(0x0C) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define USICR _SFR_IO8(0x0D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x0E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x0F) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define USIBR _SFR_IO8(0x10) #define USIBR0 0 #define USIBR1 1 #define USIBR2 2 #define USIBR3 3 #define USIBR4 4 #define USIBR5 5 #define USIBR6 6 #define USIBR7 7 #define PCMSK0 _SFR_IO8(0x12) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define GPIOR0 _SFR_IO8(0x13) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x14) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x15) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x18) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x1D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x1F) #define EEAR8 0 #define PCMSK1 _SFR_IO8(0x20) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define WDTCSR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define TCCR1C _SFR_IO8(0x22) #define FOC1B 6 #define FOC1A 7 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define TSM 7 #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_IO8(0x25) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define CLKPR _SFR_IO8(0x26) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define DWDR _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_IO8(0x29) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_IO8(0x2B) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_IO8(0x2D) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define TCCR1B _SFR_IO8(0x2E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x2F) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR0A _SFR_IO8(0x30) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define OSCCAL _SFR_IO8(0x31) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define TCNT0 _SFR_IO8(0x32) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0B _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 #define OCR0A _SFR_IO8(0x36) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR0 _SFR_IO8(0x38) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIMSK0 _SFR_IO8(0x39) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define GIFR _SFR_IO8(0x3A) #define PCIF0 4 #define PCIF1 5 #define INTF0 6 #define GIMSK _SFR_IO8(0x3B) #define PCIE0 4 #define PCIE1 5 #define INT0 6 #define OCR0B _SFR_IO8(0x3C) #define OCR0_0 0 #define OCR0_1 1 #define OCR0_2 2 #define OCR0_3 3 #define OCR0_4 4 #define OCR0_5 5 #define OCR0_6 6 #define OCR0_7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define EXT_INT0_vect_num 1 #define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ #define WATCHDOG_vect_num 4 #define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ #define TIM1_CAPT_vect_num 5 #define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIM1_COMPA_vect_num 6 #define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIM1_COMPB_vect_num 7 #define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIM1_OVF_vect_num 8 #define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIM0_COMPA_vect_num 9 #define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ #define TIM0_COMPB_vect_num 10 #define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ #define TIM0_OVF_vect_num 11 #define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ #define ANA_COMP_vect_num 12 #define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ #define ADC_vect_num 13 #define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ #define EE_RDY_vect_num 14 #define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ #define USI_STR_vect_num 15 #define USI_STR_vect _VECTOR(15) /* USI START */ #define USI_OVF_vect_num 16 #define USI_OVF_vect _VECTOR(16) /* USI Overflow */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (17 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x60) #define RAMSIZE (256) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0xFF) #define E2PAGESIZE (4) #define FLASHEND (0xFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x07 /* Device Pin Definitions */ #define ADC4_DDR DDRA #define ADC4_PORT PORTA #define ADC4_PIN PINA #define ADC4_BIT 4 #define USCK_DDR DDRA #define USCK_PORT PORTA #define USCK_PIN PINA #define USCK_BIT 4 #define SCL_DDR DDRA #define SCL_PORT PORTA #define SCL_PIN PINA #define SCL_BIT 4 #define T1_DDR DDRA #define T1_PORT PORTA #define T1_PIN PINA #define T1_BIT 4 #define PCINT4_DDR DDRA #define PCINT4_PORT PORTA #define PCINT4_PIN PINA #define PCINT4_BIT 4 #define ADC3_DDR DDRA #define ADC3_PORT PORTA #define ADC3_PIN PINA #define ADC3_BIT 3 #define T0_DDR DDRA #define T0_PORT PORTA #define T0_PIN PINA #define T0_BIT 3 #define PCINT3_DDR DDRA #define PCINT3_PORT PORTA #define PCINT3_PIN PINA #define PCINT3_BIT 3 #define ADC2_DDR DDRA #define ADC2_PORT PORTA #define ADC2_PIN PINA #define ADC2_BIT 2 #define AIN1_DDR DDRA #define AIN1_PORT PORTA #define AIN1_PIN PINA #define AIN1_BIT 2 #define PCINT2_DDR DDRA #define PCINT2_PORT PORTA #define PCINT2_PIN PINA #define PCINT2_BIT 2 #define ADC1_DDR DDRA #define ADC1_PORT PORTA #define ADC1_PIN PINA #define ADC1_BIT 1 #define AIN0_DDR DDRA #define AIN0_PORT PORTA #define AIN0_PIN PINA #define AIN0_BIT 1 #define PCINT1_DDR DDRA #define PCINT1_PORT PORTA #define PCINT1_PIN PINA #define PCINT1_BIT 1 #define ADC0_DDR DDRA #define ADC0_PORT PORTA #define ADC0_PIN PINA #define ADC0_BIT 0 #define PCINT0_DDR DDRA #define PCINT0_PORT PORTA #define PCINT0_PIN PINA #define PCINT0_BIT 0 #define PCINT8_DDR DDRB #define PCINT8_PORT PORTB #define PCINT8_PIN PINB #define PCINT8_BIT 0 #define PCINT9_DDR DDRB #define PCINT9_PORT PORTB #define PCINT9_PIN PINB #define PCINT9_BIT 1 #define PCINT11_DDR DDRB #define PCINT11_PORT PORTB #define PCINT11_PIN PINB #define PCINT11_BIT 3 #define dW_DDR DDRB #define dW_PORT PORTB #define dW_PIN PINB #define dW_BIT 3 #define PCINT10_DDR DDRB #define PCINT10_PORT PORTB #define PCINT10_PIN PINB #define PCINT10_BIT 2 #define INT0_DDR DDRB #define INT0_PORT PORTB #define INT0_PIN PINB #define INT0_BIT 2 #define OC0A_DDR DDRB #define OC0A_PORT PORTB #define OC0A_PIN PINB #define OC0A_BIT 2 #define CKOUT_DDR DDRB #define CKOUT_PORT PORTB #define CKOUT_PIN PINB #define CKOUT_BIT 2 #define PCINT7_DDR DDRA #define PCINT7_PORT PORTA #define PCINT7_PIN PINA #define PCINT7_BIT 7 #define ICP1_DDR DDRA #define ICP1_PORT PORTA #define ICP1_PIN PINA #define ICP1_BIT 7 #define OC0B_DDR DDRA #define OC0B_PORT PORTA #define OC0B_PIN PINA #define OC0B_BIT 7 #define ADC7_DDR DDRA #define ADC7_PORT PORTA #define ADC7_PIN PINA #define ADC7_BIT 7 #define PCINT6_DDR DDRA #define PCINT6_PORT PORTA #define PCINT6_PIN PINA #define PCINT6_BIT 6 #define OC1A_DDR DDRA #define OC1A_PORT PORTA #define OC1A_PIN PINA #define OC1A_BIT 6 #define DI_DDR DDRA #define DI_PORT PORTA #define DI_PIN PINA #define DI_BIT 6 #define SDA_DDR DDRA #define SDA_PORT PORTA #define SDA_PIN PINA #define SDA_BIT 6 #define MOSI_DDR DDRA #define MOSI_PORT PORTA #define MOSI_PIN PINA #define MOSI_BIT 6 #define ADC6_DDR DDRA #define ADC6_PORT PORTA #define ADC6_PIN PINA #define ADC6_BIT 6 #define ADC5_DDR DDRA #define ADC5_PORT PORTA #define ADC5_PIN PINA #define ADC5_BIT 5 #define DO_DDR DDRA #define DO_PORT PORTA #define DO_PIN PINA #define DO_BIT 5 #define MISO_DDR DDRA #define MISO_PORT PORTA #define MISO_PIN PINA #define MISO_BIT 5 #define OC1B_DDR DDRA #define OC1B_PORT PORTA #define OC1B_PIN PINA #define OC1B_BIT 5 #define PCINT5_DDR DDRA #define PCINT5_PORT PORTA #define PCINT5_PIN PINA #define PCINT5_BIT 5 #endif /* _AVR_ATtiny44A_H_ */ avr-libc-1.8.0.orig/include/avr/iox16d4.h0000644000000000000000000072331211732702554014644 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox16d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox16d4.h - definitions for ATxmega16D4 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox16d4.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega16D4_H_ #define _AVR_ATxmega16D4_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (91 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (20480) #define PROGMEM_PAGE_SIZE (256) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (16384) #define APP_SECTION_PAGE_SIZE (256) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x3000) #define APPTABLE_SECTION_SIZE (4096) #define APPTABLE_SECTION_PAGE_SIZE (256) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x4000) #define BOOT_SECTION_SIZE (4096) #define BOOT_SECTION_PAGE_SIZE (256) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (10240) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (1024) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (2048) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (1024) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (256) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x42 #endif /* _AVR_ATxmega16D4_H_ */ avr-libc-1.8.0.orig/include/avr/iotn461a.h0000644000000000000000000005054311732702554015012 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn461a.h 2063 2009-11-18 22:06:28Z arcanum $ */ /* avr/iotn461a.h - definitions for ATtiny461A */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn461a.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny461A_H_ #define _AVR_ATtiny461A_H_ 1 /* Registers and associated bit numbers. */ #define TCCR1E _SFR_IO8(0x00) #define OC1OE0 0 #define OC1OE1 1 #define OC1OE2 2 #define OC1OE3 3 #define OC1OE4 4 #define OC1OE5 5 #define DIDR0 _SFR_IO8(0x01) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define AREFD 3 #define ADC3D 4 #define ADC4D 5 #define ADC5D 6 #define ADC6D 7 #define DIDR1 _SFR_IO8(0x02) #define ADC7D 4 #define ADC8D 5 #define ADC9D 6 #define ADC10D 7 #define ADCSRB _SFR_IO8(0x03) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define MUX5 3 #define REFS2 4 #define IPR 5 #define GSEL 6 #define BIN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x05) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define ACSRA _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACME 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define ACSRB _SFR_IO8(0x09) #define ACM0 0 #define ACM1 1 #define ACM2 2 #define HLEV 6 #define HSEL 7 #define GPIOR0 _SFR_IO8(0x0A) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x0B) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x0C) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define USICR _SFR_IO8(0x0D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x0E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x0F) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define USIBR _SFR_IO8(0x10) #define USIBR0 0 #define USIBR1 1 #define USIBR2 2 #define USIBR3 3 #define USIBR4 4 #define USIBR5 5 #define USIBR6 6 #define USIBR7 7 #define USIPP _SFR_IO8(0x11) #define USIPOS 0 #define OCR0B _SFR_IO8(0x12) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define OCR0A _SFR_IO8(0x13) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define TCNT0H _SFR_IO8(0x14) #define TCNT0H_0 0 #define TCNT0H_1 1 #define TCNT0H_2 2 #define TCNT0H_3 3 #define TCNT0H_4 4 #define TCNT0H_5 5 #define TCNT0H_6 6 #define TCNT0H_7 7 #define TCCR0A _SFR_IO8(0x15) #define WGM00 0 #define ACIC0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x1D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x1F) #define EEAR8 0 #define DWDR _SFR_IO8(0x20) #define DWDR0 0 #define DWDR1 1 #define DWDR2 2 #define DWDR3 3 #define DWDR4 4 #define DWDR5 5 #define DWDR6 6 #define DWDR7 7 #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define PCMSK1 _SFR_IO8(0x22) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK0 _SFR_IO8(0x23) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define DT1 _SFR_IO8(0x24) #define DT1L0 0 #define DT1L1 1 #define DT1L2 2 #define DT1L3 3 #define DT1H0 4 #define DT1H1 5 #define DT1H2 6 #define DT1H3 7 #define TC1H _SFR_IO8(0x25) #define TC18 0 #define TC19 1 #define TCCR1D _SFR_IO8(0x26) #define WGM10 0 #define WGM11 1 #define FPF1 2 #define FPAC1 3 #define FPES1 4 #define FPNC1 5 #define FPEN1 6 #define FPIE1 7 #define TCCR1C _SFR_IO8(0x27) #define PWM1D 0 #define FOC1D 1 #define COM1D0 2 #define COM1D1 3 #define COM1B0S 4 #define COM1B1S 5 #define COM1A0S 6 #define COM1A1S 7 #define CLKPR _SFR_IO8(0x28) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PCKE 2 #define LSM 7 #define OCR1D _SFR_IO8(0x2A) #define OCR1D0 0 #define OCR1D1 1 #define OCR1D2 2 #define OCR1D3 3 #define OCR1D4 4 #define OCR1D5 5 #define OCR1D6 6 #define OCR1D7 7 #define OCR1C _SFR_IO8(0x2B) #define OCR1C0 0 #define OCR1C1 1 #define OCR1C2 2 #define OCR1C3 3 #define OCR1C4 4 #define OCR1C5 5 #define OCR1C6 6 #define OCR1C7 7 #define OCR1B _SFR_IO8(0x2C) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define OCR1A _SFR_IO8(0x2D) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define TCNT1 _SFR_IO8(0x2E) #define TC1H_0 0 #define TC1H_1 1 #define TC1H_2 2 #define TC1H_3 3 #define TC1H_4 4 #define TC1H_5 5 #define TC1H_6 6 #define TC1H_7 7 #define TCCR1B _SFR_IO8(0x2F) #define CS10 0 #define CS11 1 #define CS12 2 #define CS13 3 #define DTPS10 4 #define DTPS11 5 #define PSR1 6 #define TCCR1A _SFR_IO8(0x30) #define PWM1B 0 #define PWM1A 1 #define FOC1B 2 #define FOC1A 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define OSCCAL _SFR_IO8(0x31) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define TCNT0L _SFR_IO8(0x32) #define TCNT0L_0 0 #define TCNT0L_1 1 #define TCNT0L_2 2 #define TCNT0L_3 3 #define TCNT0L_4 4 #define TCNT0L_5 5 #define TCNT0L_6 6 #define TCNT0L_7 7 #define TCCR0B _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define PSR0 3 #define TSM 4 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define BODSE 2 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 #define BODS 7 #define PRR _SFR_IO8(0x36) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR _SFR_IO8(0x38) #define ICF0 0 #define TOV0 1 #define TOV1 2 #define OCF0B 3 #define OCF0A 4 #define OCF1B 5 #define OCF1A 6 #define OCF1D 7 #define TIMSK _SFR_IO8(0x39) #define TICIE0 0 #define TOIE0 1 #define TOIE1 2 #define OCIE0B 3 #define OCIE0A 4 #define OCIE1B 5 #define OCIE1A 6 #define OCIE1D 7 #define GIFR _SFR_IO8(0x3A) #define PCIF 5 #define INTF0 6 #define INTF1 7 #define GIMSK _SFR_IO8(0x3B) #define PCIE0 4 #define PCIE1 5 #define INT0 6 #define INT1 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt 0 */ #define PCINT_vect_num 2 #define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ #define TIMER1_COMPA_vect_num 3 #define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ #define TIMER1_COMPB_vect_num 4 #define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ #define TIMER1_OVF_vect_num 5 #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ #define TIMER0_OVF_vect_num 6 #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ #define USI_START_vect_num 7 #define USI_START_vect _VECTOR(7) /* USI Start */ #define USI_OVF_vect_num 8 #define USI_OVF_vect _VECTOR(8) /* USI Overflow */ #define EE_RDY_vect_num 9 #define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ #define ANA_COMP_vect_num 10 #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ #define ADC_vect_num 11 #define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ #define INT1_vect_num 13 #define INT1_vect _VECTOR(13) /* External Interrupt 1 */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ #define TIMER0_CAPT_vect_num 16 #define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ #define TIMER1_COMPD_vect_num 17 #define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ #define FAULT_PROTECTION_vect_num 18 #define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (19 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x60) #define RAMSIZE (256) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0xFF) #define E2PAGESIZE (4) #define FLASHEND (0xFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x08 /* Device Pin Definitions */ #define DI_B_DDR DDRMOSI #define DI_B_PORT PORTMOSI #define DI_B_PIN PINMOSI #define DI_B_BIT MOSI #define SDA_B_DDR DDRMOSI #define SDA_B_PORT PORTMOSI #define SDA_B_PIN PINMOSI #define SDA_B_BIT MOSI #define _OC1A_DDR DDRMOSI #define _OC1A_PORT PORTMOSI #define _OC1A_PIN PINMOSI #define _OC1A_BIT MOSI #define PCINT8_DDR DDRMOSI #define PCINT8_PORT PORTMOSI #define PCINT8_PIN PINMOSI #define PCINT8_BIT MOSI #define PB0_DDR DDRMOSI #define PB0_PORT PORTMOSI #define PB0_PIN PINMOSI #define PB0_BIT MOSI #define DO_B_DDR DDRMISO #define DO_B_PORT PORTMISO #define DO_B_PIN PINMISO #define DO_B_BIT MISO #define OC1A_DDR DDRMISO #define OC1A_PORT PORTMISO #define OC1A_PIN PINMISO #define OC1A_BIT MISO #define PCINT9_DDR DDRMISO #define PCINT9_PORT PORTMISO #define PCINT9_PIN PINMISO #define PCINT9_BIT MISO #define PB1_DDR DDRMISO #define PB1_PORT PORTMISO #define PB1_PIN PINMISO #define PB1_BIT MISO #define USCK_B_DDR DDRSCK #define USCK_B_PORT PORTSCK #define USCK_B_PIN PINSCK #define USCK_B_BIT SCK #define SCL_B_DDR DDRSCK #define SCL_B_PORT PORTSCK #define SCL_B_PIN PINSCK #define SCL_B_BIT SCK #define OC1B_DDR DDRSCK #define OC1B_PORT PORTSCK #define OC1B_PIN PINSCK #define OC1B_BIT SCK #define PCINT10_DDR DDRSCK #define PCINT10_PORT PORTSCK #define PCINT10_PIN PINSCK #define PCINT10_BIT SCK #define PB2_DDR DDRSCK #define PB2_PORT PORTSCK #define PB2_PIN PINSCK #define PB2_BIT SCK #define PCINT11_DDR DDROC1B #define PCINT11_PORT PORTOC1B #define PCINT11_PIN PINOC1B #define PCINT11_BIT OC1B #define PB3_DDR DDROC1B #define PB3_PORT PORTOC1B #define PB3_PIN PINOC1B #define PB3_BIT OC1B #define PCINT12_DDR DDRADC #define PCINT12_PORT PORTADC #define PCINT12_PIN PINADC #define PCINT12_BIT ADC7 #define _OC1D_DDR DDRADC #define _OC1D_PORT PORTADC #define _OC1D_PIN PINADC #define _OC1D_BIT ADC7 #define CLKI_DDR DDRADC #define CLKI_PORT PORTADC #define CLKI_PIN PINADC #define CLKI_BIT ADC7 #define PB4_DDR DDRADC #define PB4_PORT PORTADC #define PB4_PIN PINADC #define PB4_BIT ADC7 #define PCINT13_DDR DDRADC #define PCINT13_PORT PORTADC #define PCINT13_PIN PINADC #define PCINT13_BIT ADC8 #define OC1D_DDR DDRADC #define OC1D_PORT PORTADC #define OC1D_PIN PINADC #define OC1D_BIT ADC8 #define CKLO_DDR DDRADC #define CKLO_PORT PORTADC #define CKLO_PIN PINADC #define CKLO_BIT ADC8 #define PB5_DDR DDRADC #define PB5_PORT PORTADC #define PB5_PIN PINADC #define PB5_BIT ADC8 #define INT0_DDR DDRADC #define INT0_PORT PORTADC #define INT0_PIN PINADC #define INT0_BIT ADC9 #define T0_DDR DDRADC #define T0_PORT PORTADC #define T0_PIN PINADC #define T0_BIT ADC9 #define PCINT14_DDR DDRADC #define PCINT14_PORT PORTADC #define PCINT14_PIN PINADC #define PCINT14_BIT ADC9 #define PB6_DDR DDRADC #define PB6_PORT PORTADC #define PB6_PIN PINADC #define PB6_BIT ADC9 #define PCINT15_DDR DDRADC1 #define PCINT15_PORT PORTADC1 #define PCINT15_PIN PINADC1 #define PCINT15_BIT ADC10 #define PB7_DDR DDRADC1 #define PB7_PORT PORTADC1 #define PB7_PIN PINADC1 #define PB7_BIT ADC10 #define AIN1_DDR DDRADC #define AIN1_PORT PORTADC #define AIN1_PIN PINADC #define AIN1_BIT ADC6 #define PCINT7_DDR DDRADC #define PCINT7_PORT PORTADC #define PCINT7_PIN PINADC #define PCINT7_BIT ADC6 #define PA7_DDR DDRADC #define PA7_PORT PORTADC #define PA7_PIN PINADC #define PA7_BIT ADC6 #define AIN0_DDR DDRADC #define AIN0_PORT PORTADC #define AIN0_PIN PINADC #define AIN0_BIT ADC5 #define PCINT6_DDR DDRADC #define PCINT6_PORT PORTADC #define PCINT6_PIN PINADC #define PCINT6_BIT ADC5 #define PA6_DDR DDRADC #define PA6_PORT PORTADC #define PA6_PIN PINADC #define PA6_BIT ADC5 #define AIN2_DDR DDRADC #define AIN2_PORT PORTADC #define AIN2_PIN PINADC #define AIN2_BIT ADC4 #define PCINT5_DDR DDRADC #define PCINT5_PORT PORTADC #define PCINT5_PIN PINADC #define PCINT5_BIT ADC4 #define PA5_DDR DDRADC #define PA5_PORT PORTADC #define PA5_PIN PINADC #define PA5_BIT ADC4 #define ICP0_DDR DDRADC #define ICP0_PORT PORTADC #define ICP0_PIN PINADC #define ICP0_BIT ADC3 #define PCINT4_DDR DDRADC #define PCINT4_PORT PORTADC #define PCINT4_PIN PINADC #define PCINT4_BIT ADC3 #define PA4_DDR DDRADC #define PA4_PORT PORTADC #define PA4_PIN PINADC #define PA4_BIT ADC3 #define PCINT3_DDR DDRAREF #define PCINT3_PORT PORTAREF #define PCINT3_PIN PINAREF #define PCINT3_BIT AREF #define PA3_DDR DDRAREF #define PA3_PORT PORTAREF #define PA3_PIN PINAREF #define PA3_BIT AREF #define INT1_DDR DDRADC #define INT1_PORT PORTADC #define INT1_PIN PINADC #define INT1_BIT ADC2 #define USCK_A_DDR DDRADC #define USCK_A_PORT PORTADC #define USCK_A_PIN PINADC #define USCK_A_BIT ADC2 #define SCL_A_DDR DDRADC #define SCL_A_PORT PORTADC #define SCL_A_PIN PINADC #define SCL_A_BIT ADC2 #define PCINT2_DDR DDRADC #define PCINT2_PORT PORTADC #define PCINT2_PIN PINADC #define PCINT2_BIT ADC2 #define PA2_DDR DDRADC #define PA2_PORT PORTADC #define PA2_PIN PINADC #define PA2_BIT ADC2 #define DO_A_DDR DDRADC #define DO_A_PORT PORTADC #define DO_A_PIN PINADC #define DO_A_BIT ADC1 #define PCINT1_DDR DDRADC #define PCINT1_PORT PORTADC #define PCINT1_PIN PINADC #define PCINT1_BIT ADC1 #define PA1_DDR DDRADC #define PA1_PORT PORTADC #define PA1_PIN PINADC #define PA1_BIT ADC1 #define DI_A_DDR DDRADC #define DI_A_PORT PORTADC #define DI_A_PIN PINADC #define DI_A_BIT ADC0 #define SDA_A_DDR DDRADC #define SDA_A_PORT PORTADC #define SDA_A_PIN PINADC #define SDA_A_BIT ADC0 #define PCINT0_DDR DDRADC #define PCINT0_PORT PORTADC #define PCINT0_PIN PINADC #define PCINT0_BIT ADC0 #define PA0_DDR DDRADC #define PA0_PORT PORTADC #define PA0_PIN PINADC #define PA0_BIT ADC0 #endif /* _AVR_ATtiny461A_H_ */ avr-libc-1.8.0.orig/include/avr/signal.h0000644000000000000000000000340011732702554014710 0ustar /* Copyright (c) 2002,2005,2006 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: signal.h 1059 2006-02-02 19:42:12Z aesok $ */ #ifndef _AVR_SIGNAL_H_ #define _AVR_SIGNAL_H_ #warning "This header file is obsolete. Use ." #include #endif /* _AVR_SIGNAL_H_ */ avr-libc-1.8.0.orig/include/avr/iox64d3.h0000644000000000000000000073120711732702554014650 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox64d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ /* avr/iox64d3.h - definitions for ATxmega64D3 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox64d3.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega64D3_H_ #define _AVR_ATxmega64D3_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ register8_t CTRL; /* Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) /* DACB - Digital to Analog Converter B */ /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) #define TWIC_MASTER_DATA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_CTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRLA bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (114 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (69632) #define PROGMEM_PAGE_SIZE (256) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (65536) #define APP_SECTION_PAGE_SIZE (256) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x0F000) #define APPTABLE_SECTION_SIZE (4096) #define APPTABLE_SECTION_PAGE_SIZE (256) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x10000) #define BOOT_SECTION_SIZE (4096) #define BOOT_SECTION_PAGE_SIZE (256) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (12288) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (4096) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (256) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x4A #endif /* _AVR_ATxmega64D3_H_ */ avr-libc-1.8.0.orig/include/avr/iox128a1.h0000644000000000000000000113500311732702554014715 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox128a1.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox128a1.h - definitions for ATxmega128A1 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox128a1.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega128A1_H_ #define _AVR_ATxmega128A1_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* JTAG User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t GAINCAL; /* Gain Calibration */ register8_t OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register A */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ #define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTH (*(PORT_t *) 0x06E0) /* Port H */ #define PORTJ (*(PORT_t *) 0x0700) /* Port J */ #define PORTK (*(PORT_t *) 0x0720) /* Port K */ #define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* ADCB - Analog to Digital Converter B */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) #define ADCB_EVCTRL _SFR_MEM8(0x0243) #define ADCB_PRESCALER _SFR_MEM8(0x0244) #define ADCB_INTFLAGS _SFR_MEM8(0x0246) #define ADCB_CAL _SFR_MEM16(0x024C) #define ADCB_CH0RES _SFR_MEM16(0x0250) #define ADCB_CH1RES _SFR_MEM16(0x0252) #define ADCB_CH2RES _SFR_MEM16(0x0254) #define ADCB_CH3RES _SFR_MEM16(0x0256) #define ADCB_CMP _SFR_MEM16(0x0258) #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) /* DACA - Digital to Analog Converter A */ #define DACA_CTRLA _SFR_MEM8(0x0300) #define DACA_CTRLB _SFR_MEM8(0x0301) #define DACA_CTRLC _SFR_MEM8(0x0302) #define DACA_EVCTRL _SFR_MEM8(0x0303) #define DACA_TIMCTRL _SFR_MEM8(0x0304) #define DACA_STATUS _SFR_MEM8(0x0305) #define DACA_GAINCAL _SFR_MEM8(0x0308) #define DACA_OFFSETCAL _SFR_MEM8(0x0309) #define DACA_CH0DATA _SFR_MEM16(0x0318) #define DACA_CH1DATA _SFR_MEM16(0x031A) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_GAINCAL _SFR_MEM8(0x0328) #define DACB_OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* EBI - External Bus Interface */ #define EBI_CTRL _SFR_MEM8(0x0440) #define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) #define EBI_REFRESH _SFR_MEM16(0x0444) #define EBI_INITDLY _SFR_MEM16(0x0446) #define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) #define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) #define EBI_CS0_CTRLA _SFR_MEM8(0x0450) #define EBI_CS0_CTRLB _SFR_MEM8(0x0451) #define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) #define EBI_CS1_CTRLA _SFR_MEM8(0x0454) #define EBI_CS1_CTRLB _SFR_MEM8(0x0455) #define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) #define EBI_CS2_CTRLA _SFR_MEM8(0x0458) #define EBI_CS2_CTRLB _SFR_MEM8(0x0459) #define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) #define EBI_CS3_CTRLA _SFR_MEM8(0x045C) #define EBI_CS3_CTRLB _SFR_MEM8(0x045D) #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWID - Two-Wire Interface D */ #define TWID_CTRL _SFR_MEM8(0x0490) #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) #define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) #define TWID_MASTER_STATUS _SFR_MEM8(0x0494) #define TWID_MASTER_BAUD _SFR_MEM8(0x0495) #define TWID_MASTER_ADDR _SFR_MEM8(0x0496) #define TWID_MASTER_DATA _SFR_MEM8(0x0497) #define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) #define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) #define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) #define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) #define TWID_SLAVE_DATA _SFR_MEM8(0x049C) #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* TWIF - Two-Wire Interface F */ #define TWIF_CTRL _SFR_MEM8(0x04B0) #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) #define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) #define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) #define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) #define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) #define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) #define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) #define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) #define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) #define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTH - Port H */ #define PORTH_DIR _SFR_MEM8(0x06E0) #define PORTH_DIRSET _SFR_MEM8(0x06E1) #define PORTH_DIRCLR _SFR_MEM8(0x06E2) #define PORTH_DIRTGL _SFR_MEM8(0x06E3) #define PORTH_OUT _SFR_MEM8(0x06E4) #define PORTH_OUTSET _SFR_MEM8(0x06E5) #define PORTH_OUTCLR _SFR_MEM8(0x06E6) #define PORTH_OUTTGL _SFR_MEM8(0x06E7) #define PORTH_IN _SFR_MEM8(0x06E8) #define PORTH_INTCTRL _SFR_MEM8(0x06E9) #define PORTH_INT0MASK _SFR_MEM8(0x06EA) #define PORTH_INT1MASK _SFR_MEM8(0x06EB) #define PORTH_INTFLAGS _SFR_MEM8(0x06EC) #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) #define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) #define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) #define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) /* PORTJ - Port J */ #define PORTJ_DIR _SFR_MEM8(0x0700) #define PORTJ_DIRSET _SFR_MEM8(0x0701) #define PORTJ_DIRCLR _SFR_MEM8(0x0702) #define PORTJ_DIRTGL _SFR_MEM8(0x0703) #define PORTJ_OUT _SFR_MEM8(0x0704) #define PORTJ_OUTSET _SFR_MEM8(0x0705) #define PORTJ_OUTCLR _SFR_MEM8(0x0706) #define PORTJ_OUTTGL _SFR_MEM8(0x0707) #define PORTJ_IN _SFR_MEM8(0x0708) #define PORTJ_INTCTRL _SFR_MEM8(0x0709) #define PORTJ_INT0MASK _SFR_MEM8(0x070A) #define PORTJ_INT1MASK _SFR_MEM8(0x070B) #define PORTJ_INTFLAGS _SFR_MEM8(0x070C) #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) #define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) #define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) #define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) /* PORTK - Port K */ #define PORTK_DIR _SFR_MEM8(0x0720) #define PORTK_DIRSET _SFR_MEM8(0x0721) #define PORTK_DIRCLR _SFR_MEM8(0x0722) #define PORTK_DIRTGL _SFR_MEM8(0x0723) #define PORTK_OUT _SFR_MEM8(0x0724) #define PORTK_OUTSET _SFR_MEM8(0x0725) #define PORTK_OUTCLR _SFR_MEM8(0x0726) #define PORTK_OUTTGL _SFR_MEM8(0x0727) #define PORTK_IN _SFR_MEM8(0x0728) #define PORTK_INTCTRL _SFR_MEM8(0x0729) #define PORTK_INT0MASK _SFR_MEM8(0x072A) #define PORTK_INT1MASK _SFR_MEM8(0x072B) #define PORTK_INTFLAGS _SFR_MEM8(0x072C) #define PORTK_PIN0CTRL _SFR_MEM8(0x0730) #define PORTK_PIN1CTRL _SFR_MEM8(0x0731) #define PORTK_PIN2CTRL _SFR_MEM8(0x0732) #define PORTK_PIN3CTRL _SFR_MEM8(0x0733) #define PORTK_PIN4CTRL _SFR_MEM8(0x0734) #define PORTK_PIN5CTRL _SFR_MEM8(0x0735) #define PORTK_PIN6CTRL _SFR_MEM8(0x0736) #define PORTK_PIN7CTRL _SFR_MEM8(0x0737) /* PORTQ - Port Q */ #define PORTQ_DIR _SFR_MEM8(0x07C0) #define PORTQ_DIRSET _SFR_MEM8(0x07C1) #define PORTQ_DIRCLR _SFR_MEM8(0x07C2) #define PORTQ_DIRTGL _SFR_MEM8(0x07C3) #define PORTQ_OUT _SFR_MEM8(0x07C4) #define PORTQ_OUTSET _SFR_MEM8(0x07C5) #define PORTQ_OUTCLR _SFR_MEM8(0x07C6) #define PORTQ_OUTTGL _SFR_MEM8(0x07C7) #define PORTQ_IN _SFR_MEM8(0x07C8) #define PORTQ_INTCTRL _SFR_MEM8(0x07C9) #define PORTQ_INT0MASK _SFR_MEM8(0x07CA) #define PORTQ_INT1MASK _SFR_MEM8(0x07CB) #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) #define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) #define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) #define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* TCE1 - Timer/Counter E1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) #define TCE1_CTRLD _SFR_MEM8(0x0A43) #define TCE1_CTRLE _SFR_MEM8(0x0A44) #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) #define TCE1_TEMP _SFR_MEM8(0x0A4F) #define TCE1_CNT _SFR_MEM16(0x0A60) #define TCE1_PER _SFR_MEM16(0x0A66) #define TCE1_CCA _SFR_MEM16(0x0A68) #define TCE1_CCB _SFR_MEM16(0x0A6A) #define TCE1_PERBUF _SFR_MEM16(0x0A76) #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) #define USARTE1_CTRLB _SFR_MEM8(0x0AB4) #define USARTE1_CTRLC _SFR_MEM8(0x0AB5) #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /* TCF1 - Timer/Counter F1 */ #define TCF1_CTRLA _SFR_MEM8(0x0B40) #define TCF1_CTRLB _SFR_MEM8(0x0B41) #define TCF1_CTRLC _SFR_MEM8(0x0B42) #define TCF1_CTRLD _SFR_MEM8(0x0B43) #define TCF1_CTRLE _SFR_MEM8(0x0B44) #define TCF1_INTCTRLA _SFR_MEM8(0x0B46) #define TCF1_INTCTRLB _SFR_MEM8(0x0B47) #define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) #define TCF1_CTRLFSET _SFR_MEM8(0x0B49) #define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) #define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) #define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) #define TCF1_TEMP _SFR_MEM8(0x0B4F) #define TCF1_CNT _SFR_MEM16(0x0B60) #define TCF1_PER _SFR_MEM16(0x0B66) #define TCF1_CCA _SFR_MEM16(0x0B68) #define TCF1_CCB _SFR_MEM16(0x0B6A) #define TCF1_PERBUF _SFR_MEM16(0x0B76) #define TCF1_CCABUF _SFR_MEM16(0x0B78) #define TCF1_CCBBUF _SFR_MEM16(0x0B7A) /* HIRESF - High-Resolution Extension F */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) /* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) #define USARTF1_CTRLB _SFR_MEM8(0x0BB4) #define USARTF1_CTRLC _SFR_MEM8(0x0BB5) #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) /* SPIF - Serial Peripheral Interface F */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) #define SPIF_DATA _SFR_MEM8(0x0BC3) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ #define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ #define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ #define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ #define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ #define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ #define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ #define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ #define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ #define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ #define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ #define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ #define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ #define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ #define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ #define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ #define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ #define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ #define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ #define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRLA bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* ACB interrupt vectors */ #define ACB_AC0_vect_num 36 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ #define ACB_AC1_vect_num 37 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ #define ACB_ACW_vect_num 38 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ /* ADCB interrupt vectors */ #define ADCB_CH0_vect_num 39 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ #define ADCB_CH1_vect_num 40 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ #define ADCB_CH2_vect_num 41 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ #define ADCB_CH3_vect_num 42 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* SPIE interrupt vectors */ #define SPIE_INT_vect_num 57 #define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* USARTE1 interrupt vectors */ #define USARTE1_RXC_vect_num 61 #define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ #define USARTE1_DRE_vect_num 62 #define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ #define USARTE1_TXC_vect_num 63 #define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TWID interrupt vectors */ #define TWID_TWIS_vect_num 75 #define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ #define TWID_TWIM_vect_num 76 #define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ /* PORTQ interrupt vectors */ #define PORTQ_INT0_vect_num 94 #define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ #define PORTQ_INT1_vect_num 95 #define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ /* PORTH interrupt vectors */ #define PORTH_INT0_vect_num 96 #define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ #define PORTH_INT1_vect_num 97 #define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ /* PORTJ interrupt vectors */ #define PORTJ_INT0_vect_num 98 #define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ #define PORTJ_INT1_vect_num 99 #define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ /* PORTK interrupt vectors */ #define PORTK_INT0_vect_num 100 #define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ #define PORTK_INT1_vect_num 101 #define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TWIF interrupt vectors */ #define TWIF_TWIS_vect_num 106 #define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ #define TWIF_TWIM_vect_num 107 #define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ /* TCF1 interrupt vectors */ #define TCF1_OVF_vect_num 114 #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ #define TCF1_ERR_vect_num 115 #define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ #define TCF1_CCA_vect_num 116 #define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ #define TCF1_CCB_vect_num 117 #define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ /* SPIF interrupt vectors */ #define SPIF_INT_vect_num 118 #define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ /* USARTF0 interrupt vectors */ #define USARTF0_RXC_vect_num 119 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ #define USARTF0_DRE_vect_num 120 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ #define USARTF0_TXC_vect_num 121 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ /* USARTF1 interrupt vectors */ #define USARTF1_RXC_vect_num 122 #define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ #define USARTF1_DRE_vect_num 123 #define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ #define USARTF1_TXC_vect_num 124 #define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (125 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (139264) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (131072) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x1E000) #define APPTABLE_SECTION_SIZE (8192) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x20000) #define BOOT_SECTION_SIZE (8192) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (16777216) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (8192) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EXTERNAL_SRAM_START (0x4000) #define EXTERNAL_SRAM_SIZE (16760832) #define EXTERNAL_SRAM_PAGE_SIZE (0) #define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND EXTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ #define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ #define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ #define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ #define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ #define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ #define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ #define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x4C #endif /* _AVR_ATxmega128A1_H_ */ avr-libc-1.8.0.orig/include/avr/interrupt.h0000644000000000000000000002620211732702554015474 0ustar /* Copyright (c) 2002,2005,2007 Marek Michalkiewicz Copyright (c) 2007, Dean Camera All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: interrupt.h 2220 2011-02-22 21:08:58Z arcanum $ */ #ifndef _AVR_INTERRUPT_H_ #define _AVR_INTERRUPT_H_ #include #if !defined(__DOXYGEN__) && !defined(__STRINGIFY) /* Auxiliary macro for ISR_ALIAS(). */ #define __STRINGIFY(x) #x #endif /* !defined(__DOXYGEN__) */ /** \file \@{ */ /** \name Global manipulation of the interrupt flag The global interrupt flag is maintained in the I bit of the status register (SREG). Handling interrupts frequently requires attention regarding atomic access to objects that could be altered by code running within an interrupt context, see . Frequently, interrupts are being disabled for periods of time in order to perform certain operations without being disturbed; see \ref optim_code_reorder for things to be taken into account with respect to compiler optimizations. */ #if defined(__DOXYGEN__) /** \def sei() \ingroup avr_interrupts Enables interrupts by setting the global interrupt mask. This function actually compiles into a single line of assembly, so there is no function call overhead. However, the macro also implies a memory barrier which can cause additional loss of optimization. In order to implement atomic access to multi-byte objects, consider using the macros from , rather than implementing them manually with cli() and sei(). */ #define sei() #else /* !DOXYGEN */ # define sei() __asm__ __volatile__ ("sei" ::: "memory") #endif /* DOXYGEN */ #if defined(__DOXYGEN__) /** \def cli() \ingroup avr_interrupts Disables all interrupts by clearing the global interrupt mask. This function actually compiles into a single line of assembly, so there is no function call overhead. However, the macro also implies a memory barrier which can cause additional loss of optimization. In order to implement atomic access to multi-byte objects, consider using the macros from , rather than implementing them manually with cli() and sei(). */ #define cli() #else /* !DOXYGEN */ # define cli() __asm__ __volatile__ ("cli" ::: "memory") #endif /* DOXYGEN */ /** \name Macros for writing interrupt handler functions */ #if defined(__DOXYGEN__) /** \def ISR(vector [, attributes]) \ingroup avr_interrupts Introduces an interrupt handler function (interrupt service routine) that runs with global interrupts initially disabled by default with no attributes specified. The attributes are optional and alter the behaviour and resultant generated code of the interrupt routine. Multiple attributes may be used for a single function, with a space seperating each attribute. Valid attributes are ISR_BLOCK, ISR_NOBLOCK, ISR_NAKED and ISR_ALIASOF(vect). \c vector must be one of the interrupt vector names that are valid for the particular MCU type. */ # define ISR(vector, [attributes]) #else /* real code */ #if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4) # define __INTR_ATTRS used, externally_visible #else /* GCC < 4.1 */ # define __INTR_ATTRS used #endif #ifdef __cplusplus # define ISR(vector, ...) \ extern "C" void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \ void vector (void) #else # define ISR(vector, ...) \ void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \ void vector (void) #endif #endif /* DOXYGEN */ #if defined(__DOXYGEN__) /** \def SIGNAL(vector) \ingroup avr_interrupts Introduces an interrupt handler function that runs with global interrupts initially disabled. This is the same as the ISR macro without optional attributes. \deprecated Do not use SIGNAL() in new code. Use ISR() instead. */ # define SIGNAL(vector) #else /* real code */ #ifdef __cplusplus # define SIGNAL(vector) \ extern "C" void vector(void) __attribute__ ((signal, __INTR_ATTRS)); \ void vector (void) #else # define SIGNAL(vector) \ void vector (void) __attribute__ ((signal, __INTR_ATTRS)); \ void vector (void) #endif #endif /* DOXYGEN */ #if defined(__DOXYGEN__) /** \def EMPTY_INTERRUPT(vector) \ingroup avr_interrupts Defines an empty interrupt handler function. This will not generate any prolog or epilog code and will only return from the ISR. Do not define a function body as this will define it for you. Example: \code EMPTY_INTERRUPT(ADC_vect);\endcode */ # define EMPTY_INTERRUPT(vector) #else /* real code */ #ifdef __cplusplus # define EMPTY_INTERRUPT(vector) \ extern "C" void vector(void) __attribute__ ((signal,naked,__INTR_ATTRS)); \ void vector (void) { __asm__ __volatile__ ("reti" ::); } #else # define EMPTY_INTERRUPT(vector) \ void vector (void) __attribute__ ((signal,naked,__INTR_ATTRS)); \ void vector (void) { __asm__ __volatile__ ("reti" ::); } #endif #endif /* DOXYGEN */ #if defined(__DOXYGEN__) /** \def ISR_ALIAS(vector, target_vector) \ingroup avr_interrupts Aliases a given vector to another one in the same manner as the ISR_ALIASOF attribute for the ISR() macro. Unlike the ISR_ALIASOF attribute macro however, this is compatible for all versions of GCC rather than just GCC version 4.2 onwards. \note This macro creates a trampoline function for the aliased macro. This will result in a two cycle penalty for the aliased vector compared to the ISR the vector is aliased to, due to the JMP/RJMP opcode used. \deprecated For new code, the use of ISR(..., ISR_ALIASOF(...)) is recommended. Example: \code ISR(INT0_vect) { PORTB = 42; } ISR_ALIAS(INT1_vect, INT0_vect); \endcode */ # define ISR_ALIAS(vector, target_vector) #else /* real code */ #ifdef __cplusplus # if defined(__AVR_MEGA__) && __AVR_MEGA__ # define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \ __attribute__((signal, naked, __INTR_ATTRS)); \ void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); } # else /* !__AVR_MEGA */ # define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \ __attribute__((signal, naked, __INTR_ATTRS)); \ void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); } # endif /* __AVR_MEGA__ */ #else /* !__cplusplus */ # if defined(__AVR_MEGA__) && __AVR_MEGA__ # define ISR_ALIAS(vector, tgt) void vector (void) \ __attribute__((signal, naked, __INTR_ATTRS)); \ void vector (void) { asm volatile ("jmp " __STRINGIFY(tgt) ::); } # else /* !__AVR_MEGA */ # define ISR_ALIAS(vector, tgt) void vector (void) \ __attribute__((signal, naked, __INTR_ATTRS)); \ void vector (void) { asm volatile ("rjmp " __STRINGIFY(tgt) ::); } # endif /* __AVR_MEGA__ */ #endif /* __cplusplus */ #endif /* DOXYGEN */ #if defined(__DOXYGEN__) /** \def reti() \ingroup avr_interrupts Returns from an interrupt routine, enabling global interrupts. This should be the last command executed before leaving an ISR defined with the ISR_NAKED attribute. This macro actually compiles into a single line of assembly, so there is no function call overhead. */ # define reti() #else /* !DOXYGEN */ # define reti() __asm__ __volatile__ ("reti" ::) #endif /* DOXYGEN */ #if defined(__DOXYGEN__) /** \def BADISR_vect \ingroup avr_interrupts \code #include \endcode This is a vector which is aliased to __vector_default, the vector executed when an ISR fires with no accompanying ISR handler. This may be used along with the ISR() macro to create a catch-all for undefined but used ISRs for debugging purposes. */ # define BADISR_vect #else /* !DOXYGEN */ # define BADISR_vect __vector_default #endif /* DOXYGEN */ /** \name ISR attributes */ #if defined(__DOXYGEN__) /** \def ISR_BLOCK \ingroup avr_interrupts Identical to an ISR with no attributes specified. Global interrupts are initially disabled by the AVR hardware when entering the ISR, without the compiler modifying this state. Use this attribute in the attributes parameter of the ISR macro. */ # define ISR_BLOCK /** \def ISR_NOBLOCK \ingroup avr_interrupts ISR runs with global interrupts initially enabled. The interrupt enable flag is activated by the compiler as early as possible within the ISR to ensure minimal processing delay for nested interrupts. This may be used to create nested ISRs, however care should be taken to avoid stack overflows, or to avoid infinitely entering the ISR for those cases where the AVR hardware does not clear the respective interrupt flag before entering the ISR. Use this attribute in the attributes parameter of the ISR macro. */ # define ISR_NOBLOCK /** \def ISR_NAKED \ingroup avr_interrupts ISR is created with no prologue or epilogue code. The user code is responsible for preservation of the machine state including the SREG register, as well as placing a reti() at the end of the interrupt routine. Use this attribute in the attributes parameter of the ISR macro. */ # define ISR_NAKED /** \def ISR_ALIASOF(target_vector) \ingroup avr_interrupts The ISR is linked to another ISR, specified by the vect parameter. This is compatible with GCC 4.2 and greater only. Use this attribute in the attributes parameter of the ISR macro. */ # define ISR_ALIASOF(target_vector) #else /* !DOXYGEN */ # define ISR_BLOCK # define ISR_NOBLOCK __attribute__((interrupt)) # define ISR_NAKED __attribute__((naked)) # define ISR_ALIASOF(v) __attribute__((alias(__STRINGIFY(v)))) #endif /* DOXYGEN */ /* \@} */ #endif avr-libc-1.8.0.orig/include/avr/iomxx0_1.h0000644000000000000000000010466011732702554015111 0ustar /* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iomxx0_1.h 2235 2011-03-17 04:13:14Z arcanum $ */ /* avr/iomxx0_1.h - definitions for ATmega640, Atmega1280, ATmega1281, ATmega2560 and ATmega2561. */ #ifndef _AVR_IOMXX0_1_H_ #define _AVR_IOMXX0_1_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iomxx0_1.h" #else # error "Attempt to include more than one file." #endif #if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) # define __ATmegaxx0__ #elif defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) # define __ATmegaxx1__ #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0X00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0X01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0X02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0X03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG5 5 #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG5 5 #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define OCF0B 2 #define OCF0A 1 #define TOV0 0 #define TIFR1 _SFR_IO8(0x16) #define ICF1 5 #define OCF1C 3 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 #define TIFR2 _SFR_IO8(0x17) #define OCF2B 2 #define OCF2A 1 #define TOV2 0 #define TIFR3 _SFR_IO8(0x18) #define ICF3 5 #define OCF3C 3 #define OCF3B 2 #define OCF3A 1 #define TOV3 0 #define TIFR4 _SFR_IO8(0x19) #define ICF4 5 #define OCF4C 3 #define OCF4B 2 #define OCF4A 1 #define TOV4 0 #define TIFR5 _SFR_IO8(0x1A) #define ICF5 5 #define OCF5C 3 #define OCF5B 2 #define OCF5A 1 #define TOV5 0 #define PCIFR _SFR_IO8(0x1B) #if defined(__ATmegaxx0__) # define PCIF2 2 #endif /* __ATmegaxx0__ */ #define PCIF1 1 #define PCIF0 0 #define EIFR _SFR_IO8(0x1C) #define INTF7 7 #define INTF6 6 #define INTF5 5 #define INTF4 4 #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 #define EIMSK _SFR_IO8(0x1D) #define INT7 7 #define INT6 6 #define INT5 5 #define INT4 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define TSM 7 #define PSRASY 1 #define PSRSYNC 0 #define TCCR0A _SFR_IO8(0x24) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 #define TCCR0B _SFR_IO8(0x25) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) #define OCR0B _SFR_IO8(0X28) /* Reserved [0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 #define SPSR _SFR_IO8(0x2D) #define SPIF 7 #define WCOL 6 #define SPI2X 0 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 #define MONDR _SFR_IO8(0x31) #define OCDR _SFR_IO8(0x31) #define IDRD 7 #define OCDR7 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 #define MCUSR _SFR_IO8(0x34) #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 #define MCUCR _SFR_IO8(0X35) #define JTD 7 #define PUD 4 #define IVSEL 1 #define IVCE 0 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMIE 7 #define RWWSB 6 #define SIGRD 5 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* Reserved [0x38..0x3A] */ #define RAMPZ _SFR_IO8(0X3B) #define RAMPZ0 0 #define EIND _SFR_IO8(0X3C) #define EIND0 0 /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCSR _SFR_MEM8(0x60) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 #define CLKPR _SFR_MEM8(0x61) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 /* Reserved [0x62..0x63] */ #define PRR0 _SFR_MEM8(0x64) #define PRTWI 7 #define PRTIM2 6 #define PRTIM0 5 #define PRTIM1 3 #define PRSPI 2 #define PRUSART0 1 #define PRADC 0 #define PRR1 _SFR_MEM8(0x65) #define PRTIM5 5 #define PRTIM4 4 #define PRTIM3 3 #define PRUSART3 2 #define PRUSART2 1 #define PRUSART1 0 #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67] */ #define PCICR _SFR_MEM8(0x68) #if defined(__ATmegaxx0__) # define PCIE2 2 #endif /* __ATmegaxx0__ */ #define PCIE1 1 #define PCIE0 0 #define EICRA _SFR_MEM8(0x69) #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 #define EICRB _SFR_MEM8(0x6A) #define ISC71 7 #define ISC70 6 #define ISC61 5 #define ISC60 4 #define ISC51 3 #define ISC50 2 #define ISC41 1 #define ISC40 0 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT15 7 #define PCINT14 6 #define PCINT13 5 #define PCINT12 4 #define PCINT11 3 #define PCINT10 2 #define PCINT9 1 #define PCINT8 0 #if defined(__ATmegaxx0__) # define PCMSK2 _SFR_MEM8(0x6D) # define PCINT23 7 # define PCINT22 6 # define PCINT21 5 # define PCINT20 4 # define PCINT19 3 # define PCINT18 2 # define PCINT17 1 # define PCINT16 0 #endif /* __ATmegaxx0__ */ #define TIMSK0 _SFR_MEM8(0x6E) #define OCIE0B 2 #define OCIE0A 1 #define TOIE0 0 #define TIMSK1 _SFR_MEM8(0x6F) #define ICIE1 5 #define OCIE1C 3 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 #define TIMSK2 _SFR_MEM8(0x70) #define OCIE2B 2 #define OCIE2A 1 #define TOIE2 0 #define TIMSK3 _SFR_MEM8(0x71) #define ICIE3 5 #define OCIE3C 3 #define OCIE3B 2 #define OCIE3A 1 #define TOIE3 0 #define TIMSK4 _SFR_MEM8(0x72) #define ICIE4 5 #define OCIE4C 3 #define OCIE4B 2 #define OCIE4A 1 #define TOIE4 0 #define TIMSK5 _SFR_MEM8(0x73) #define ICIE5 5 #define OCIE5C 3 #define OCIE5B 2 #define OCIE5A 1 #define TOIE5 0 #define XMCRA _SFR_MEM8(0x74) #define SRE 7 #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW11 3 #define SRW10 2 #define SRW01 1 #define SRW00 0 #define XMCRB _SFR_MEM8(0x75) #define XMBK 7 #define XMM2 2 #define XMM1 1 #define XMM0 0 /* Reserved [0x76..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 #define ADCSRB _SFR_MEM8(0x7B) #define ACME 6 #if defined(__ATmegaxx0__) # define MUX5 3 #endif /* __ATmegaxx0__ */ #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 #define ADMUX _SFR_MEM8(0x7C) #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 #define DIDR2 _SFR_MEM8(0x7D) #define ADC15D 7 #define ADC14D 6 #define ADC13D 5 #define ADC12D 4 #define ADC11D 3 #define ADC10D 2 #define ADC9D 1 #define ADC8D 0 #define DIDR0 _SFR_MEM8(0x7E) #define ADC7D 7 #define ADC6D 6 #define ADC5D 5 #define ADC4D 4 #define ADC3D 3 #define ADC2D 2 #define ADC1D 1 #define ADC0D 0 #define DIDR1 _SFR_MEM8(0x7F) #define AIN1D 1 #define AIN0D 0 #define TCCR1A _SFR_MEM8(0x80) #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define COM1C1 3 #define COM1C0 2 #define WGM11 1 #define WGM10 0 #define TCCR1B _SFR_MEM8(0x81) #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 #define TCCR1C _SFR_MEM8(0x82) #define FOC1A 7 #define FOC1B 6 #define FOC1C 5 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Combine OCR1CL and OCR1CH */ #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CH _SFR_MEM8(0x8D) /* Reserved [0x8E..0x8F] */ #define TCCR3A _SFR_MEM8(0x90) #define COM3A1 7 #define COM3A0 6 #define COM3B1 5 #define COM3B0 4 #define COM3C1 3 #define COM3C0 2 #define WGM31 1 #define WGM30 0 #define TCCR3B _SFR_MEM8(0x91) #define ICNC3 7 #define ICES3 6 #define WGM33 4 #define WGM32 3 #define CS32 2 #define CS31 1 #define CS30 0 #define TCCR3C _SFR_MEM8(0x92) #define FOC3A 7 #define FOC3B 6 #define FOC3C 5 /* Reserved [0x93] */ /* Combine TCNT3L and TCNT3H */ #define TCNT3 _SFR_MEM16(0x94) #define TCNT3L _SFR_MEM8(0x94) #define TCNT3H _SFR_MEM8(0x95) /* Combine ICR3L and ICR3H */ #define ICR3 _SFR_MEM16(0x96) #define ICR3L _SFR_MEM8(0x96) #define ICR3H _SFR_MEM8(0x97) /* Combine OCR3AL and OCR3AH */ #define OCR3A _SFR_MEM16(0x98) #define OCR3AL _SFR_MEM8(0x98) #define OCR3AH _SFR_MEM8(0x99) /* Combine OCR3BL and OCR3BH */ #define OCR3B _SFR_MEM16(0x9A) #define OCR3BL _SFR_MEM8(0x9A) #define OCR3BH _SFR_MEM8(0x9B) /* Combine OCR3CL and OCR3CH */ #define OCR3C _SFR_MEM16(0x9C) #define OCR3CL _SFR_MEM8(0x9C) #define OCR3CH _SFR_MEM8(0x9D) /* Reserved [0x9E..0x9F] */ #define TCCR4A _SFR_MEM8(0xA0) #define COM4A1 7 #define COM4A0 6 #define COM4B1 5 #define COM4B0 4 #define COM4C1 3 #define COM4C0 2 #define WGM41 1 #define WGM40 0 #define TCCR4B _SFR_MEM8(0xA1) #define ICNC4 7 #define ICES4 6 #define WGM43 4 #define WGM42 3 #define CS42 2 #define CS41 1 #define CS40 0 #define TCCR4C _SFR_MEM8(0xA2) #define FOC4A 7 #define FOC4B 6 #define FOC4C 5 /* Reserved [0xA3] */ /* Combine TCNT4L and TCNT4H */ #define TCNT4 _SFR_MEM16(0xA4) #define TCNT4L _SFR_MEM8(0xA4) #define TCNT4H _SFR_MEM8(0xA5) /* Combine ICR4L and ICR4H */ #define ICR4 _SFR_MEM16(0xA6) #define ICR4L _SFR_MEM8(0xA6) #define ICR4H _SFR_MEM8(0xA7) /* Combine OCR4AL and OCR4AH */ #define OCR4A _SFR_MEM16(0xA8) #define OCR4AL _SFR_MEM8(0xA8) #define OCR4AH _SFR_MEM8(0xA9) /* Combine OCR4BL and OCR4BH */ #define OCR4B _SFR_MEM16(0xAA) #define OCR4BL _SFR_MEM8(0xAA) #define OCR4BH _SFR_MEM8(0xAB) /* Combine OCR4CL and OCR4CH */ #define OCR4C _SFR_MEM16(0xAC) #define OCR4CL _SFR_MEM8(0xAC) #define OCR4CH _SFR_MEM8(0xAD) /* Reserved [0xAE..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define COM2A1 7 #define COM2A0 6 #define COM2B1 5 #define COM2B0 4 #define WGM21 1 #define WGM20 0 #define TCCR2B _SFR_MEM8(0xB1) #define FOC2A 7 #define FOC2B 6 #define WGM22 3 #define CS22 2 #define CS21 1 #define CS20 0 #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) #define OCR2B _SFR_MEM8(0xB4) /* Reserved [0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define EXCLK 6 #define AS2 5 #define TCN2UB 4 #define OCR2AUB 3 #define OCR2BUB 2 #define TCR2AUB 1 #define TCR2BUB 0 /* Reserved [0xB7] */ #define TWBR _SFR_MEM8(0xB8) #define TWSR _SFR_MEM8(0xB9) #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 #define TWAR _SFR_MEM8(0xBA) #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 #define TWDR _SFR_MEM8(0xBB) #define TWCR _SFR_MEM8(0xBC) #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 #define TWAMR _SFR_MEM8(0xBD) #define TWAM6 7 #define TWAM5 6 #define TWAM4 5 #define TWAM3 4 #define TWAM2 3 #define TWAM1 2 #define TWAM0 1 /* Reserved [0xBE..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 #define UCSR0B _SFR_MEM8(0XC1) #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 #define UCSR0C _SFR_MEM8(0xC2) #define UMSEL01 7 #define UMSEL00 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UCSZ00 1 #define UCPOL0 0 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7] */ #define UCSR1A _SFR_MEM8(0xC8) #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 #define UCSR1B _SFR_MEM8(0XC9) #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 #define UCSR1C _SFR_MEM8(0xCA) #define UMSEL11 7 #define UMSEL10 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPOL1 0 /* Reserved [0xCB] */ /* Combine UBRR1L and UBRR1H */ #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1H _SFR_MEM8(0xCD) #define UDR1 _SFR_MEM8(0XCE) /* Reserved [0xCF] */ #if defined(__ATmegaxx0__) # define UCSR2A _SFR_MEM8(0xD0) # define RXC2 7 # define TXC2 6 # define UDRE2 5 # define FE2 4 # define DOR2 3 # define UPE2 2 # define U2X2 1 # define MPCM2 0 # define UCSR2B _SFR_MEM8(0XD1) # define RXCIE2 7 # define TXCIE2 6 # define UDRIE2 5 # define RXEN2 4 # define TXEN2 3 # define UCSZ22 2 # define RXB82 1 # define TXB82 0 # define UCSR2C _SFR_MEM8(0xD2) # define UMSEL21 7 # define UMSEL20 6 # define UPM21 5 # define UPM20 4 # define USBS2 3 # define UCSZ21 2 # define UCSZ20 1 # define UCPOL2 0 /* Reserved [0xD3] */ /* Combine UBRR2L and UBRR2H */ # define UBRR2 _SFR_MEM16(0xD4) # define UBRR2L _SFR_MEM8(0xD4) # define UBRR2H _SFR_MEM8(0xD5) # define UDR2 _SFR_MEM8(0XD6) #endif /* __ATmegaxx0__ */ /* Reserved [0xD7..0xFF] */ #if defined(__ATmegaxx0__) # define PINH _SFR_MEM8(0x100) # define PINH7 7 # define PINH6 6 # define PINH5 5 # define PINH4 4 # define PINH3 3 # define PINH2 2 # define PINH1 1 # define PINH0 0 # define DDRH _SFR_MEM8(0x101) # define DDH7 7 # define DDH6 6 # define DDH5 5 # define DDH4 4 # define DDH3 3 # define DDH2 2 # define DDH1 1 # define DDH0 0 # define PORTH _SFR_MEM8(0x102) # define PH7 7 # define PH6 6 # define PH5 5 # define PH4 4 # define PH3 3 # define PH2 2 # define PH1 1 # define PH0 0 # define PINJ _SFR_MEM8(0x103) # define PINJ7 7 # define PINJ6 6 # define PINJ5 5 # define PINJ4 4 # define PINJ3 3 # define PINJ2 2 # define PINJ1 1 # define PINJ0 0 # define DDRJ _SFR_MEM8(0x104) # define DDJ7 7 # define DDJ6 6 # define DDJ5 5 # define DDJ4 4 # define DDJ3 3 # define DDJ2 2 # define DDJ1 1 # define DDJ0 0 # define PORTJ _SFR_MEM8(0x105) # define PJ7 7 # define PJ6 6 # define PJ5 5 # define PJ4 4 # define PJ3 3 # define PJ2 2 # define PJ1 1 # define PJ0 0 # define PINK _SFR_MEM8(0x106) # define PINK7 7 # define PINK6 6 # define PINK5 5 # define PINK4 4 # define PINK3 3 # define PINK2 2 # define PINK1 1 # define PINK0 0 # define DDRK _SFR_MEM8(0x107) # define DDK7 7 # define DDK6 6 # define DDK5 5 # define DDK4 4 # define DDK3 3 # define DDK2 2 # define DDK1 1 # define DDK0 0 # define PORTK _SFR_MEM8(0x108) # define PK7 7 # define PK6 6 # define PK5 5 # define PK4 4 # define PK3 3 # define PK2 2 # define PK1 1 # define PK0 0 # define PINL _SFR_MEM8(0x109) # define PINL7 7 # define PINL6 6 # define PINL5 5 # define PINL4 4 # define PINL3 3 # define PINL2 2 # define PINL1 1 # define PINL0 0 # define DDRL _SFR_MEM8(0x10A) # define DDL7 7 # define DDL6 6 # define DDL5 5 # define DDL4 4 # define DDL3 3 # define DDL2 2 # define DDL1 1 # define DDL0 0 # define PORTL _SFR_MEM8(0x10B) # define PL7 7 # define PL6 6 # define PL5 5 # define PL4 4 # define PL3 3 # define PL2 2 # define PL1 1 # define PL0 0 #endif /* __ATmegaxx0__ */ /* Reserved [0x10C..0x11F] */ #define TCCR5A _SFR_MEM8(0x120) #define COM5A1 7 #define COM5A0 6 #define COM5B1 5 #define COM5B0 4 #define COM5C1 3 #define COM5C0 2 #define WGM51 1 #define WGM50 0 #define TCCR5B _SFR_MEM8(0x121) #define ICNC5 7 #define ICES5 6 #define WGM53 4 #define WGM52 3 #define CS52 2 #define CS51 1 #define CS50 0 #define TCCR5C _SFR_MEM8(0x122) #define FOC5A 7 #define FOC5B 6 #define FOC5C 5 /* Reserved [0x123] */ /* Combine TCNT5L and TCNT5H */ #define TCNT5 _SFR_MEM16(0x124) #define TCNT5L _SFR_MEM8(0x124) #define TCNT5H _SFR_MEM8(0x125) /* Combine ICR5L and ICR5H */ #define ICR5 _SFR_MEM16(0x126) #define ICR5L _SFR_MEM8(0x126) #define ICR5H _SFR_MEM8(0x127) /* Combine OCR5AL and OCR5AH */ #define OCR5A _SFR_MEM16(0x128) #define OCR5AL _SFR_MEM8(0x128) #define OCR5AH _SFR_MEM8(0x129) /* Combine OCR5BL and OCR5BH */ #define OCR5B _SFR_MEM16(0x12A) #define OCR5BL _SFR_MEM8(0x12A) #define OCR5BH _SFR_MEM8(0x12B) /* Combine OCR5CL and OCR5CH */ #define OCR5C _SFR_MEM16(0x12C) #define OCR5CL _SFR_MEM8(0x12C) #define OCR5CH _SFR_MEM8(0x12D) /* Reserved [0x12E..0x12F] */ #if defined(__ATmegaxx0__) # define UCSR3A _SFR_MEM8(0x130) # define RXC3 7 # define TXC3 6 # define UDRE3 5 # define FE3 4 # define DOR3 3 # define UPE3 2 # define U2X3 1 # define MPCM3 0 # define UCSR3B _SFR_MEM8(0X131) # define RXCIE3 7 # define TXCIE3 6 # define UDRIE3 5 # define RXEN3 4 # define TXEN3 3 # define UCSZ32 2 # define RXB83 1 # define TXB83 0 # define UCSR3C _SFR_MEM8(0x132) # define UMSEL31 7 # define UMSEL30 6 # define UPM31 5 # define UPM30 4 # define USBS3 3 # define UCSZ31 2 # define UCSZ30 1 # define UCPOL3 0 /* Reserved [0x133] */ /* Combine UBRR3L and UBRR3H */ # define UBRR3 _SFR_MEM16(0x134) # define UBRR3L _SFR_MEM8(0x134) # define UBRR3H _SFR_MEM8(0x135) # define UDR3 _SFR_MEM8(0X136) #endif /* __ATmegaxx0__ */ /* Reserved [0x137..1FF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* External Interrupt Request 3 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) #define SIG_INTERRUPT3 _VECTOR(4) /* External Interrupt Request 4 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) #define SIG_INTERRUPT4 _VECTOR(5) /* External Interrupt Request 5 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) #define SIG_INTERRUPT5 _VECTOR(6) /* External Interrupt Request 6 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) #define SIG_INTERRUPT6 _VECTOR(7) /* External Interrupt Request 7 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) #define SIG_INTERRUPT7 _VECTOR(8) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 9 #define PCINT0_vect _VECTOR(9) #define SIG_PIN_CHANGE0 _VECTOR(9) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 10 #define PCINT1_vect _VECTOR(10) #define SIG_PIN_CHANGE1 _VECTOR(10) #if defined(__ATmegaxx0__) /* Pin Change Interrupt Request 2 */ #define PCINT2_vect_num 11 #define PCINT2_vect _VECTOR(11) #define SIG_PIN_CHANGE2 _VECTOR(11) #endif /* __ATmegaxx0__ */ /* Watchdog Time-out Interrupt */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) #define SIG_WATCHDOG_TIMEOUT _VECTOR(12) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPA_vect_num 13 #define TIMER2_COMPA_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE2A _VECTOR(13) /* Timer/Counter2 Compare Match B */ #define TIMER2_COMPB_vect_num 14 #define TIMER2_COMPB_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE2B _VECTOR(14) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 15 #define TIMER2_OVF_vect _VECTOR(15) #define SIG_OVERFLOW2 _VECTOR(15) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 16 #define TIMER1_CAPT_vect _VECTOR(16) #define SIG_INPUT_CAPTURE1 _VECTOR(16) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 17 #define TIMER1_COMPA_vect _VECTOR(17) #define SIG_OUTPUT_COMPARE1A _VECTOR(17) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 18 #define TIMER1_COMPB_vect _VECTOR(18) #define SIG_OUTPUT_COMPARE1B _VECTOR(18) /* Timer/Counter1 Compare Match C */ #define TIMER1_COMPC_vect_num 19 #define TIMER1_COMPC_vect _VECTOR(19) #define SIG_OUTPUT_COMPARE1C _VECTOR(19) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 20 #define TIMER1_OVF_vect _VECTOR(20) #define SIG_OVERFLOW1 _VECTOR(20) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPA_vect_num 21 #define TIMER0_COMPA_vect _VECTOR(21) #define SIG_OUTPUT_COMPARE0A _VECTOR(21) /* Timer/Counter0 Compare Match B */ #define TIMER0_COMPB_vect_num 22 #define TIMER0_COMPB_vect _VECTOR(22) #define SIG_OUTPUT_COMPARE0B _VECTOR(22) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 23 #define TIMER0_OVF_vect _VECTOR(23) #define SIG_OVERFLOW0 _VECTOR(23) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 24 #define SPI_STC_vect _VECTOR(24) #define SIG_SPI _VECTOR(24) /* USART0, Rx Complete */ #define USART0_RX_vect_num 25 #define USART0_RX_vect _VECTOR(25) #define SIG_USART0_RECV _VECTOR(25) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 26 #define USART0_UDRE_vect _VECTOR(26) #define SIG_USART0_DATA _VECTOR(26) /* USART0, Tx Complete */ #define USART0_TX_vect_num 27 #define USART0_TX_vect _VECTOR(27) #define SIG_USART0_TRANS _VECTOR(27) /* Analog Comparator */ #define ANALOG_COMP_vect_num 28 #define ANALOG_COMP_vect _VECTOR(28) #define SIG_COMPARATOR _VECTOR(28) /* ADC Conversion Complete */ #define ADC_vect_num 29 #define ADC_vect _VECTOR(29) #define SIG_ADC _VECTOR(29) /* EEPROM Ready */ #define EE_READY_vect_num 30 #define EE_READY_vect _VECTOR(30) #define SIG_EEPROM_READY _VECTOR(30) /* Timer/Counter3 Capture Event */ #define TIMER3_CAPT_vect_num 31 #define TIMER3_CAPT_vect _VECTOR(31) #define SIG_INPUT_CAPTURE3 _VECTOR(31) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPA_vect_num 32 #define TIMER3_COMPA_vect _VECTOR(32) #define SIG_OUTPUT_COMPARE3A _VECTOR(32) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPB_vect_num 33 #define TIMER3_COMPB_vect _VECTOR(33) #define SIG_OUTPUT_COMPARE3B _VECTOR(33) /* Timer/Counter3 Compare Match C */ #define TIMER3_COMPC_vect_num 34 #define TIMER3_COMPC_vect _VECTOR(34) #define SIG_OUTPUT_COMPARE3C _VECTOR(34) /* Timer/Counter3 Overflow */ #define TIMER3_OVF_vect_num 35 #define TIMER3_OVF_vect _VECTOR(35) #define SIG_OVERFLOW3 _VECTOR(35) /* USART1, Rx Complete */ #define USART1_RX_vect_num 36 #define USART1_RX_vect _VECTOR(36) #define SIG_USART1_RECV _VECTOR(36) /* USART1 Data register Empty */ #define USART1_UDRE_vect_num 37 #define USART1_UDRE_vect _VECTOR(37) #define SIG_USART1_DATA _VECTOR(37) /* USART1, Tx Complete */ #define USART1_TX_vect_num 38 #define USART1_TX_vect _VECTOR(38) #define SIG_USART1_TRANS _VECTOR(38) /* 2-wire Serial Interface */ #define TWI_vect_num 39 #define TWI_vect _VECTOR(39) #define SIG_2WIRE_SERIAL _VECTOR(39) /* Store Program Memory Read */ #define SPM_READY_vect_num 40 #define SPM_READY_vect _VECTOR(40) #define SIG_SPM_READY _VECTOR(40) #if defined(__ATmegaxx0__) /* Timer/Counter4 Capture Event */ #define TIMER4_CAPT_vect_num 41 #define TIMER4_CAPT_vect _VECTOR(41) #define SIG_INPUT_CAPTURE4 _VECTOR(41) #endif /* __ATmegaxx0__ */ /* Timer/Counter4 Compare Match A */ #define TIMER4_COMPA_vect_num 42 #define TIMER4_COMPA_vect _VECTOR(42) #define SIG_OUTPUT_COMPARE4A _VECTOR(42) /* Timer/Counter4 Compare Match B */ #define TIMER4_COMPB_vect_num 43 #define TIMER4_COMPB_vect _VECTOR(43) #define SIG_OUTPUT_COMPARE4B _VECTOR(43) /* Timer/Counter4 Compare Match C */ #define TIMER4_COMPC_vect_num 44 #define TIMER4_COMPC_vect _VECTOR(44) #define SIG_OUTPUT_COMPARE4C _VECTOR(44) /* Timer/Counter4 Overflow */ #define TIMER4_OVF_vect_num 45 #define TIMER4_OVF_vect _VECTOR(45) #define SIG_OVERFLOW4 _VECTOR(45) #if defined(__ATmegaxx0__) /* Timer/Counter5 Capture Event */ #define TIMER5_CAPT_vect_num 46 #define TIMER5_CAPT_vect _VECTOR(46) #define SIG_INPUT_CAPTURE5 _VECTOR(46) #endif /* __ATmegaxx0__ */ /* Timer/Counter5 Compare Match A */ #define TIMER5_COMPA_vect_num 47 #define TIMER5_COMPA_vect _VECTOR(47) #define SIG_OUTPUT_COMPARE5A _VECTOR(47) /* Timer/Counter5 Compare Match B */ #define TIMER5_COMPB_vect_num 48 #define TIMER5_COMPB_vect _VECTOR(48) #define SIG_OUTPUT_COMPARE5B _VECTOR(48) /* Timer/Counter5 Compare Match C */ #define TIMER5_COMPC_vect_num 49 #define TIMER5_COMPC_vect _VECTOR(49) #define SIG_OUTPUT_COMPARE5C _VECTOR(49) /* Timer/Counter5 Overflow */ #define TIMER5_OVF_vect_num 50 #define TIMER5_OVF_vect _VECTOR(50) #define SIG_OVERFLOW5 _VECTOR(50) #if defined(__ATmegaxx1__) # define _VECTORS_SIZE 204 #else /* USART2, Rx Complete */ #define USART2_RX_vect_num 51 #define USART2_RX_vect _VECTOR(51) #define SIG_USART2_RECV _VECTOR(51) /* USART2 Data register Empty */ #define USART2_UDRE_vect_num 52 #define USART2_UDRE_vect _VECTOR(52) #define SIG_USART2_DATA _VECTOR(52) /* USART2, Tx Complete */ #define USART2_TX_vect_num 53 #define USART2_TX_vect _VECTOR(53) #define SIG_USART2_TRANS _VECTOR(53) /* USART3, Rx Complete */ #define USART3_RX_vect_num 54 #define USART3_RX_vect _VECTOR(54) #define SIG_USART3_RECV _VECTOR(54) /* USART3 Data register Empty */ #define USART3_UDRE_vect_num 55 #define USART3_UDRE_vect _VECTOR(55) #define SIG_USART3_DATA _VECTOR(55) /* USART3, Tx Complete */ #define USART3_TX_vect_num 56 #define USART3_TX_vect _VECTOR(56) #define SIG_USART3_TRANS _VECTOR(56) # define _VECTORS_SIZE 228 #endif /* __ATmegaxx1__ */ #if defined(__ATmegaxx0__) # undef __ATmegaxx0__ #endif #if defined(__ATmegaxx1__) # undef __ATmegaxx1__ #endif /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_INTERRUPT3 #pragma GCC poison SIG_INTERRUPT4 #pragma GCC poison SIG_INTERRUPT5 #pragma GCC poison SIG_INTERRUPT6 #pragma GCC poison SIG_INTERRUPT7 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_PIN_CHANGE2 #pragma GCC poison SIG_WATCHDOG_TIMEOUT #pragma GCC poison SIG_OUTPUT_COMPARE2A #pragma GCC poison SIG_OUTPUT_COMPARE2B #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OUTPUT_COMPARE1C #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0A #pragma GCC poison SIG_OUTPUT_COMPARE0B #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_USART0_RECV #pragma GCC poison SIG_USART0_DATA #pragma GCC poison SIG_USART0_TRANS #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_INPUT_CAPTURE3 #pragma GCC poison SIG_OUTPUT_COMPARE3A #pragma GCC poison SIG_OUTPUT_COMPARE3B #pragma GCC poison SIG_OUTPUT_COMPARE3C #pragma GCC poison SIG_OVERFLOW3 #pragma GCC poison SIG_USART1_RECV #pragma GCC poison SIG_USART1_DATA #pragma GCC poison SIG_USART1_TRANS #pragma GCC poison SIG_2WIRE_SERIAL #pragma GCC poison SIG_SPM_READY #pragma GCC poison SIG_INPUT_CAPTURE4 #pragma GCC poison SIG_OUTPUT_COMPARE4A #pragma GCC poison SIG_OUTPUT_COMPARE4B #pragma GCC poison SIG_OUTPUT_COMPARE4C #pragma GCC poison SIG_OVERFLOW4 #pragma GCC poison SIG_INPUT_CAPTURE5 #pragma GCC poison SIG_OUTPUT_COMPARE5A #pragma GCC poison SIG_OUTPUT_COMPARE5B #pragma GCC poison SIG_OUTPUT_COMPARE5C #pragma GCC poison SIG_OVERFLOW5 #pragma GCC poison SIG_USART2_RECV #pragma GCC poison SIG_USART2_DATA #pragma GCC poison SIG_USART2_TRANS #pragma GCC poison SIG_USART3_RECV #pragma GCC poison SIG_USART3_DATA #pragma GCC poison SIG_USART3_TRANS #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOMXX0_1_H_ */ avr-libc-1.8.0.orig/include/avr/iotn22.h0000644000000000000000000001216711732702554014562 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn22.h 2236 2011-03-17 21:53:39Z arcanum $ */ /* avr/iotn22.h - definitions for ATtiny22 */ #ifndef _AVR_IOTN22_H_ #define _AVR_IOTN22_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn22.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3D SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Timer/Counter0 Overflow */ #define TIMER0_OVF0_vect_num 2 #define TIMER0_OVF0_vect _VECTOR(2) #define SIG_OVERFLOW0 _VECTOR(2) #define _VECTORS_SIZE 6 /* The Register Bit names are represented by their bit number (0-7). */ /* General Interrupt MaSK register */ #define INT0 6 #define INTF0 6 /* General Interrupt Flag Register */ #define TOIE0 1 #define TOV0 1 /* MCU general Control Register */ #define SE 5 #define SM 4 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PB2 = SCK/T0 PB1 = MISO/INT0 PB0 = MOSI */ /* Data Register, Port B */ #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 0 #define FLASHEND 0x07FF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Fuse Byte */ #define FUSE_CKSEL (unsigned char)~_BV(0) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DEFAULT (FUSE_SPIEN) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x06 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_OVERFLOW0 #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOTN22_H_ */ avr-libc-1.8.0.orig/include/avr/iom325.h0000644000000000000000000004437611732702554014472 0ustar /* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom325.h 2234 2011-03-16 04:32:21Z arcanum $ */ /* avr/iom325.h - definitions for ATmega325 and ATmega325P. */ #ifndef _AVR_IOM325_H_ #define _AVR_IOM325_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom325.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #if defined(__AVR_ATmega325P__) #define BODSE 5 #define BODS 6 #endif #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 /* Reserved [0x6D] */ #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0XC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7..0xFF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART0, Rx Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* Vector 22 is Reserved */ #define _VECTORS_SIZE 92 /* Constants */ #define SPM_PAGESIZE 128 #define RAMSTART (0x100) #define RAMEND 0x8FF #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 4 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x05 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM325_H_ */ avr-libc-1.8.0.orig/include/avr/iom644pa.h0000644000000000000000000006672011732702554015014 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom644pa.h 2035 2009-11-02 02:44:17Z arcanum $ */ /* avr/iom644PA.h - definitions for ATmega644PA */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom644PA.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega644PA_H_ #define _AVR_ATmega644PA_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 #define BODS 6 #define JTD 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRUSART1 4 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #define PCMSK3 _SFR_MEM8(0x73) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define PCINT27 3 #define PCINT28 4 #define PCINT29 5 #define PCINT30 6 #define PCINT31 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2A_0 0 #define OCR2A_1 1 #define OCR2A_2 2 #define OCR2A_3 3 #define OCR2A_4 4 #define OCR2A_5 5 #define OCR2A_6 6 #define OCR2A_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2B_0 0 #define OCR2B_1 1 #define OCR2B_2 2 #define OCR2B_3 3 #define OCR2B_4 4 #define OCR2B_5 5 #define OCR2B_6 6 #define OCR2B_7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL01 7 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define _UBRR0 0 #define _UBRR1 1 #define UBRR2 2 #define UBRR3 3 #define UBRR4 4 #define UBRR5 5 #define UBRR6 6 #define UBRR7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR8 0 #define UBRR9 1 #define UBRR10 2 #define UBRR11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR0_0 0 #define UDR0_1 1 #define UDR0_2 2 #define UDR0_3 3 #define UDR0_4 4 #define UDR0_5 5 #define UDR0_6 6 #define UDR0_7 7 #define UCSR1A _SFR_MEM8(0xC8) #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 #define UCSR1B _SFR_MEM8(0xC9) #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 #define UCSR1C _SFR_MEM8(0xCA) #define UCPOL1 0 #define UCSZ10 1 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR_0 0 #define UBRR_1 1 #define UBRR_2 2 #define UBRR_3 3 #define UBRR_4 4 #define UBRR_5 5 #define UBRR_6 6 #define UBRR_7 7 #define UBRR1H _SFR_MEM8(0xCD) #define UBRR_8 0 #define UBRR_9 1 #define UBRR_10 2 #define UBRR_11 3 #define UDR1 _SFR_MEM8(0xCE) #define UDR1_0 0 #define UDR1_1 1 #define UDR1_2 2 #define UDR1_3 3 #define UDR1_4 4 #define UDR1_5 5 #define UDR1_6 6 #define UDR1_7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define PCINT0_vect_num 4 #define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 5 #define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 6 #define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */ #define PCINT3_vect_num 7 #define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 9 #define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 10 #define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ #define TIMER2_OVF_vect_num 11 #define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 12 #define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 16 #define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 17 #define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 18 #define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 19 #define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ #define USART0_RX_vect_num 20 #define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ #define USART0_UDRE_vect_num 21 #define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ #define USART0_TX_vect_num 22 #define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ #define ADC_vect_num 24 #define ADC_vect _VECTOR(24) /* ADC Conversion Complete */ #define EE_READY_vect_num 25 #define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ #define TWI_vect_num 26 #define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ #define SPM_READY_vect_num 27 #define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ #define USART1_RX_vect_num 28 #define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */ #define USART1_UDRE_vect_num 29 #define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */ #define USART1_TX_vect_num 30 #define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (31 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (256) #define RAMSTART (0x100) #define RAMSIZE (4096) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (0x0) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x7FF) #define E2PAGESIZE (8) #define FLASHEND (0xFFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x0A /* Device Pin Definitions */ #define MOSI_DDR DDRB #define MOSI_PORT PORTB #define MOSI_PIN PINB #define MOSI_BIT 5 #define PCINT13_DDR DDRB #define PCINT13_PORT PORTB #define PCINT13_PIN PINB #define PCINT13_BIT 5 #define MISO_DDR DDRB #define MISO_PORT PORTB #define MISO_PIN PINB #define MISO_BIT 6 #define PCINT14_DDR DDRB #define PCINT14_PORT PORTB #define PCINT14_PIN PINB #define PCINT14_BIT 6 #define SCK_DDR DDRB #define SCK_PORT PORTB #define SCK_PIN PINB #define SCK_BIT 7 #define PCINT15_DDR DDRB #define PCINT15_PORT PORTB #define PCINT15_PIN PINB #define PCINT15_BIT 7 #define RXD_DDR DDRD #define RXD_PORT PORTD #define RXD_PIN PIND #define RXD_BIT 0 #define PCINT24_DDR DDRD #define PCINT24_PORT PORTD #define PCINT24_PIN PIND #define PCINT24_BIT 0 #define TXD_DDR DDRD #define TXD_PORT PORTD #define TXD_PIN PIND #define TXD_BIT 1 #define PCINT25_DDR DDRD #define PCINT25_PORT PORTD #define PCINT25_PIN PIND #define PCINT25_BIT 1 #define INT0_DDR DDRD #define INT0_PORT PORTD #define INT0_PIN PIND #define INT0_BIT 2 #define RDX1_DDR DDRD #define RDX1_PORT PORTD #define RDX1_PIN PIND #define RDX1_BIT 2 #define PCINT26_DDR DDRD #define PCINT26_PORT PORTD #define PCINT26_PIN PIND #define PCINT26_BIT 2 #define INT1_DDR DDRD #define INT1_PORT PORTD #define INT1_PIN PIND #define INT1_BIT 3 #define TXD1_DDR DDRD #define TXD1_PORT PORTD #define TXD1_PIN PIND #define TXD1_BIT 3 #define PCINT27_DDR DDRD #define PCINT27_PORT PORTD #define PCINT27_PIN PIND #define PCINT27_BIT 3 #define OC1B_DDR DDRD #define OC1B_PORT PORTD #define OC1B_PIN PIND #define OC1B_BIT 4 #define XCK1_DDR DDRD #define XCK1_PORT PORTD #define XCK1_PIN PIND #define XCK1_BIT 4 #define PCINT28_DDR DDRD #define PCINT28_PORT PORTD #define PCINT28_PIN PIND #define PCINT28_BIT 4 #define OC1A_DDR DDRD #define OC1A_PORT PORTD #define OC1A_PIN PIND #define OC1A_BIT 5 #define PCINT29_DDR DDRD #define PCINT29_PORT PORTD #define PCINT29_PIN PIND #define PCINT29_BIT 5 #define ICP_DDR DDRD #define ICP_PORT PORTD #define ICP_PIN PIND #define ICP_BIT 6 #define OC2B_DDR DDRD #define OC2B_PORT PORTD #define OC2B_PIN PIND #define OC2B_BIT 6 #define PCINT30_DDR DDRD #define PCINT30_PORT PORTD #define PCINT30_PIN PIND #define PCINT30_BIT 6 #define OC2A_DDR DDRD #define OC2A_PORT PORTD #define OC2A_PIN PIND #define OC2A_BIT 7 #define PCINT31_DDR DDRD #define PCINT31_PORT PORTD #define PCINT31_PIN PIND #define PCINT31_BIT 7 #define SCL_DDR DDRC #define SCL_PORT PORTC #define SCL_PIN PINC #define SCL_BIT 0 #define PCINT16_DDR DDRC #define PCINT16_PORT PORTC #define PCINT16_PIN PINC #define PCINT16_BIT 0 #define SDA_DDR DDRC #define SDA_PORT PORTC #define SDA_PIN PINC #define SDA_BIT 1 #define PCINT17_DDR DDRC #define PCINT17_PORT PORTC #define PCINT17_PIN PINC #define PCINT17_BIT 1 #define PCINT18_DDR DDRC #define PCINT18_PORT PORTC #define PCINT18_PIN PINC #define PCINT18_BIT 2 #define PCINT19_DDR DDRC #define PCINT19_PORT PORTC #define PCINT19_PIN PINC #define PCINT19_BIT 3 #define PCINT20_DDR DDRC #define PCINT20_PORT PORTC #define PCINT20_PIN PINC #define PCINT20_BIT 4 #define PCINT21_DDR DDRC #define PCINT21_PORT PORTC #define PCINT21_PIN PINC #define PCINT21_BIT 5 #define PCINT22_DDR DDRC #define PCINT22_PORT PORTC #define PCINT22_PIN PINC #define PCINT22_BIT 6 #define PCINT23_DDR DDRC #define PCINT23_PORT PORTC #define PCINT23_PIN PINC #define PCINT23_BIT 7 #define ADC7_DDR DDRA #define ADC7_PORT PORTA #define ADC7_PIN PINA #define ADC7_BIT 7 #define PCINT7_DDR DDRA #define PCINT7_PORT PORTA #define PCINT7_PIN PINA #define PCINT7_BIT 7 #define ADC6_DDR DDRA #define ADC6_PORT PORTA #define ADC6_PIN PINA #define ADC6_BIT 6 #define PCINT6_DDR DDRA #define PCINT6_PORT PORTA #define PCINT6_PIN PINA #define PCINT6_BIT 6 #define ADC5_DDR DDRA #define ADC5_PORT PORTA #define ADC5_PIN PINA #define ADC5_BIT 5 #define PCINT5_DDR DDRA #define PCINT5_PORT PORTA #define PCINT5_PIN PINA #define PCINT5_BIT 5 #define ADC4_DDR DDRA #define ADC4_PORT PORTA #define ADC4_PIN PINA #define ADC4_BIT 4 #define PCINT4_DDR DDRA #define PCINT4_PORT PORTA #define PCINT4_PIN PINA #define PCINT4_BIT 4 #define ADC3_DDR DDRA #define ADC3_PORT PORTA #define ADC3_PIN PINA #define ADC3_BIT 3 #define PCINT3_DDR DDRA #define PCINT3_PORT PORTA #define PCINT3_PIN PINA #define PCINT3_BIT 3 #define ADC2_DDR DDRA #define ADC2_PORT PORTA #define ADC2_PIN PINA #define ADC2_BIT 2 #define PCINT2_DDR DDRA #define PCINT2_PORT PORTA #define PCINT2_PIN PINA #define PCINT2_BIT 2 #define ADC1_DDR DDRA #define ADC1_PORT PORTA #define ADC1_PIN PINA #define ADC1_BIT 1 #define PCINT1_DDR DDRA #define PCINT1_PORT PORTA #define PCINT1_PIN PINA #define PCINT1_BIT 1 #define ADC0_DDR DDRA #define ADC0_PORT PORTA #define ADC0_PIN PINA #define ADC0_BIT 0 #define PCINT0_DDR DDRA #define PCINT0_PORT PORTA #define PCINT0_PIN PINA #define PCINT0_BIT 0 #define XCK_DDR DDRB #define XCK_PORT PORTB #define XCK_PIN PINB #define XCK_BIT 0 #define T0_DDR DDRB #define T0_PORT PORTB #define T0_PIN PINB #define T0_BIT 0 #define PCINT8_DDR DDRB #define PCINT8_PORT PORTB #define PCINT8_PIN PINB #define PCINT8_BIT 0 #define T1_DDR DDRB #define T1_PORT PORTB #define T1_PIN PINB #define T1_BIT 1 #define CLKO_DDR DDRB #define CLKO_PORT PORTB #define CLKO_PIN PINB #define CLKO_BIT 1 #define PCINT9_DDR DDRB #define PCINT9_PORT PORTB #define PCINT9_PIN PINB #define PCINT9_BIT 1 #define AIN0_DDR DDRB #define AIN0_PORT PORTB #define AIN0_PIN PINB #define AIN0_BIT 2 #define INT2_DDR DDRB #define INT2_PORT PORTB #define INT2_PIN PINB #define INT2_BIT 2 #define PCINT10_DDR DDRB #define PCINT10_PORT PORTB #define PCINT10_PIN PINB #define PCINT10_BIT 2 #define AIN1_DDR DDRB #define AIN1_PORT PORTB #define AIN1_PIN PINB #define AIN1_BIT 3 #define OC0A_DDR DDRB #define OC0A_PORT PORTB #define OC0A_PIN PINB #define OC0A_BIT 3 #define PCINT11_DDR DDRB #define PCINT11_PORT PORTB #define PCINT11_PIN PINB #define PCINT11_BIT 3 #define SS_DDR DDRB #define SS_PORT PORTB #define SS_PIN PINB #define SS_BIT 4 #define OC0B_DDR DDRB #define OC0B_PORT PORTB #define OC0B_PIN PINB #define OC0B_BIT 4 #define PCINT12_DDR DDRB #define PCINT12_PORT PORTB #define PCINT12_PIN PINB #define PCINT12_BIT 4 #endif /* _AVR_ATmega644PA_H_ */ avr-libc-1.8.0.orig/include/avr/iotnx61.h0000644000000000000000000002652111732702554014754 0ustar /* Copyright (c) 2006, 2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotnx61.h 2247 2011-05-23 19:39:56Z joerg_wunsch $ */ /* avr/iotnx61.h - definitions for ATtiny261, ATtiny461 and ATtiny861 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotnx61.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOTNx61_H_ #define _AVR_IOTNx61_H_ 1 /* Registers and associated bit numbers */ #define TCCR1E _SFR_IO8(0x00) #define OC1OE0 0 #define OC1OE1 1 #define OC1OE2 2 #define OC1OE3 3 #define OC1OE4 4 #define OC1OE5 5 #define DIDR0 _SFR_IO8(0x01) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define AREFD 3 #define ADC3D 4 #define ADC4D 5 #define ADC5D 6 #define ADC6D 7 #define DIDR1 _SFR_IO8(0x02) #define ADC7D 4 #define ADC8D 5 #define ADC9D 6 #define ADC10D 7 #define ADCSRB _SFR_IO8(0x03) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define MUX5 3 #define REFS2 4 #define IRP 5 #define GSEL 6 #define BIN 7 #define ADCW _SFR_IO16(0x04) #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define ACSRA _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACME 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define ACSRB _SFR_IO8(0x09) #define ACM0 0 #define ACM1 1 #define ACM2 2 #define HLEV 6 #define HSEL 7 #define GPIOR0 _SFR_IO8(0x0A) #define GPIOR1 _SFR_IO8(0x0B) #define GPIOR2 _SFR_IO8(0x0C) #define USICR _SFR_IO8(0x0D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x0E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x0F) #define USIBR _SFR_IO8(0x10) #define USIPP _SFR_IO8(0x11) #define USIPOS 0 #define OCR0B _SFR_IO8(0x12) #define OCR0A _SFR_IO8(0x13) #define TCNT0H _SFR_IO8(0x14) #define TCCR0A _SFR_IO8(0x15) #define WGM00 0 /* up to at least datasheet rev. B */ #define CTC0 0 /* newer revisions; change not mentioned * in revision history */ #define ACIC0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PB0 0 #define PB1 1 #define PB2 2 #define PB3 3 #define PB4 4 #define PB5 5 #define PB6 6 #define PB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PA0 0 #define PA1 1 #define PA2 2 #define PA3 3 #define PA4 4 #define PA5 5 #define PA6 6 #define PA7 7 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define DWDR _SFR_IO8(0x20) #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define PCMSK1 _SFR_IO8(0x22) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK0 _SFR_IO8(0x23) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define DT1 _SFR_IO8(0x24) #define DT1L0 0 #define DT1L1 1 #define DT1L2 2 #define DT1L3 3 #define DT1H0 4 #define DT1H1 5 #define DT1H2 6 #define DT1H3 7 #define TC1H _SFR_IO8(0x25) #define TC18 0 #define TC19 1 #define TCCR1D _SFR_IO8(0x26) #define WGM10 0 #define WGM11 1 #define FPF1 2 #define FPAC1 3 #define FPES1 4 #define FPNC1 5 #define FPEN1 6 #define FPIE1 7 #define TCCR1C _SFR_IO8(0x27) #define PWM1D 0 #define FOC1D 1 #define COM1D0 2 #define COM1D1 3 #define COM1B0S 4 #define COM1B1S 5 #define COM1A0S 6 #define COM1A1S 7 #define CLKPR _SFR_IO8(0x28) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PCKE 2 #define LSM 7 #define OCR1D _SFR_IO8(0x2A) #define OCR1C _SFR_IO8(0x2B) #define OCR1B _SFR_IO8(0x2C) #define OCR1A _SFR_IO8(0x2D) #define TCNT1 _SFR_IO8(0x2E) #define TCCR1B _SFR_IO8(0x2F) #define CS10 0 #define CS11 1 #define CS12 2 #define CS13 3 #define DTPS10 4 #define DTPS11 5 #define PSR1 6 #define PWM1X 7 #define TCCR1A _SFR_IO8(0x30) #define PWM1B 0 #define PWM1A 1 #define FOC1B 2 #define FOC1A 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define OSCCAL _SFR_IO8(0x31) #define TCNT0L _SFR_IO8(0x32) #define TCCR0B _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define PSR0 3 #define TSM 4 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 #define PRR _SFR_IO8(0x36) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR _SFR_IO8(0x38) #define ICF0 0 #define TOV0 1 #define TOV1 2 #define OCF0B 3 #define OCF0A 4 #define OCF1B 5 #define OCF1A 6 #define OCF1D 7 #define TIMSK _SFR_IO8(0x39) #define TICIE0 0 #define TOIE0 1 #define TOIE1 2 #define OCIE0B 3 #define OCIE0A 4 #define OCIE1B 5 #define OCIE1A 6 #define OCIE1D 7 #define GIFR _SFR_IO8(0x3A) #define PCIF 5 #define INTF0 6 #define INTF1 7 #define GIMSK _SFR_IO8(0x3B) #define PCIE0 4 #define PCIE1 5 #define INT0 6 #define INT1 7 /* Reserved [0x3C] */ /* 0x3D..0x3E SP [defined in ] */ /* 0x3F SREG [defined in ] */ /* Interrupt vectors */ /* Interrupt vector 0 is the reset vector. */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt */ #define PCINT_vect_num 2 #define PCINT_vect _VECTOR(2) #define SIG_PIN_CHANGE _VECTOR(2) /* Timer/Counter1 Compare Match 1A */ #define TIMER1_COMPA_vect_num 3 #define TIMER1_COMPA_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE1A _VECTOR(3) /* Timer/Counter1 Compare Match 1B */ #define TIMER1_COMPB_vect_num 4 #define TIMER1_COMPB_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1B _VECTOR(4) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 5 #define TIMER1_OVF_vect _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(5) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 6 #define TIMER0_OVF_vect _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(6) /* USI Start */ #define USI_START_vect_num 7 #define USI_START_vect _VECTOR(7) #define SIG_USI_START _VECTOR(7) /* USI Overflow */ #define USI_OVF_vect_num 8 #define USI_OVF_vect _VECTOR(8) #define SIG_USI_OVERFLOW _VECTOR(8) /* EEPROM Ready */ #define EE_RDY_vect_num 9 #define EE_RDY_vect _VECTOR(9) #define SIG_EEPROM_READY _VECTOR(9) /* Analog Comparator */ #define ANA_COMP_vect_num 10 #define ANA_COMP_vect _VECTOR(10) #define SIG_ANA_COMP _VECTOR(10) #define SIG_COMPARATOR _VECTOR(10) /* ADC Conversion Complete */ #define ADC_vect_num 11 #define ADC_vect _VECTOR(11) #define SIG_ADC _VECTOR(11) /* Watchdog Time-Out */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) #define SIG_WDT _VECTOR(12) /* External Interrupt 1 */ #define INT1_vect_num 13 #define INT1_vect _VECTOR(13) #define SIG_INTERRUPT1 _VECTOR(13) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE0A _VECTOR(14) /* Timer/Counter0 Compare Match B */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) #define SIG_OUTPUT_COMPARE0B _VECTOR(15) /* ADC Conversion Complete */ #define TIMER0_CAPT_vect_num 16 #define TIMER0_CAPT_vect _VECTOR(16) #define SIG_INPUT_CAPTURE0 _VECTOR(16) /* Timer/Counter1 Compare Match D */ #define TIMER1_COMPD_vect_num 17 #define TIMER1_COMPD_vect _VECTOR(17) #define SIG_OUTPUT_COMPARE0D _VECTOR(17) /* Timer/Counter1 Fault Protection */ #define FAULT_PROTECTION_vect_num 18 #define FAULT_PROTECTION_vect _VECTOR(18) #define _VECTORS_SIZE 38 #endif /* _AVR_IOTNx61_H_ */ avr-libc-1.8.0.orig/include/avr/io90pwm2b.h0000644000000000000000000006747011732702554015204 0ustar /* Copyright (c) 2007 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io90pwm2b.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwm2b.h - definitions for AT90PWM2B */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io90pwm2b.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IO90PWM2B_H_ #define _AVR_IO90PWM2B_H_ 1 /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define GPIOR1 _SFR_IO8(0x19) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x1A) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define GPIOR3 _SFR_IO8(0x1B) #define GPIOR30 0 #define GPIOR31 1 #define GPIOR32 2 #define GPIOR33 3 #define GPIOR34 4 #define GPIOR35 5 #define GPIOR36 6 #define GPIOR37 7 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARL0 0 #define EEARL1 1 #define EEARL2 2 #define EEARL3 3 #define EEARL4 4 #define EEARL5 5 #define EEARL6 6 #define EEARL7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSRSYNC 0 #define ICPSEL1 2 #define TSM 3 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define OCR0_0 0 /* Deprecated */ #define OCR0_1 1 /* Deprecated */ #define OCR0_2 2 /* Deprecated */ #define OCR0_3 3 /* Deprecated */ #define OCR0_4 4 /* Deprecated */ #define OCR0_5 5 /* Deprecated */ #define OCR0_6 6 /* Deprecated */ #define OCR0_7 7 /* Deprecated */ #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLF 2 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define AC0O 0 #define AC1O 1 #define AC2O 2 #define AC0IF 4 #define AC1IF 5 #define AC2IF 6 #define ACCKDIV 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPIPS 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM0 3 #define PRTIM1 4 #define PRPSC0 5 #define PRPSC1 6 #define PRPSC2 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define AMP0CSR _SFR_MEM8(0x76) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 #define AMP1CSR _SFR_MEM8(0x77) #define AMP1TS0 0 #define AMP1TS1 1 #define AMP1G0 4 #define AMP1G1 5 #define AMP1IS 6 #define AMP1EN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define ADASCR 4 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define AMP0ND 3 #define AMP0PD 4 #define ACMP0D 5 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define PIFR0 _SFR_MEM8(0xA0) #define PEOP0 0 #define PRN00 1 #define PRN01 2 #define PEV0A 3 #define PEV0B 4 #define PSEI0 5 #define POAC0A 6 #define POAC0B 7 #define PIM0 _SFR_MEM8(0xA1) #define PEOPE0 0 #define PEVE0A 3 #define PEVE0B 4 #define PSEIE0 5 #define PIFR1 _SFR_MEM8(0xA2) #define PEOP1 0 #define PRN10 1 #define PRN11 2 #define PEV1A 3 #define PEV1B 4 #define PSEI1 5 #define POAC1A 6 #define POAC1B 7 #define PIM1 _SFR_MEM8(0xA3) #define PEOPE1 0 #define PEVE1A 3 #define PEVE1B 4 #define PSEIE1 5 #define PIFR2 _SFR_MEM8(0xA4) #define PEOP2 0 #define PRN20 1 #define PRN21 2 #define PEV2A 3 #define PEV2B 4 #define PSEI2 5 #define POAC2A 6 #define POAC2B 7 #define PIM2 _SFR_MEM8(0xA5) #define PEOPE2 0 #define PEVE2A 3 #define PEVE2B 4 #define PSEIE2 5 #define DACON _SFR_MEM8(0xAA) #define DAEN 0 #define DAOE 1 #define DALA 2 #define DATS0 4 #define DATS1 5 #define DATS2 6 #define DAATE 7 #define DAC _SFR_MEM16(0xAB) #define DACL _SFR_MEM8(0xAB) #define DACL0 0 #define DACL1 1 #define DACL2 2 #define DACL3 3 #define DACL4 4 #define DACL5 5 #define DACL6 6 #define DACL7 7 #define DACH _SFR_MEM8(0xAC) #define DACH0 0 #define DACH1 1 #define DACH2 2 #define DACH3 3 #define DACH4 4 #define DACH5 5 #define DACH6 6 #define DACH7 7 #define AC0CON _SFR_MEM8(0xAD) #define AC0M0 0 #define AC0M1 1 #define AC0M2 2 #define AC0IS0 4 #define AC0IS1 5 #define AC0IE 6 #define AC0EN 7 #define AC1CON _SFR_MEM8(0xAE) #define AC1M0 0 #define AC1M1 1 #define AC1M2 2 #define AC1ICE 3 #define AC1IS0 4 #define AC1IS1 5 #define AC1IE 6 #define AC1EN 7 #define AC2CON _SFR_MEM8(0xAF) #define AC2M0 0 #define AC2M1 1 #define AC2M2 2 #define AC2IS0 4 #define AC2IS1 5 #define AC2IE 6 #define AC2EN 7 #define UCSRA _SFR_MEM8(0xC0) #define MPCM 0 #define U2X 1 #define UPE 2 #define DOR 3 #define FE 4 #define UDRE 5 #define TXC 6 #define RXC 7 #define UCSRB _SFR_MEM8(0xC1) #define TXB8 0 #define RXB8 1 #define UCSZ2 2 #define TXEN 3 #define RXEN 4 #define UDRIE 5 #define TXCIE 6 #define RXCIE 7 #define UCSRC _SFR_MEM8(0xC2) #define UCPOL 0 #define UCSZ0 1 #define UCSZ1 2 #define USBS 3 #define UPM0 4 #define UPM1 5 #define UMSEL0 6 #define UBRR _SFR_MEM16(0xC4) #define UBRRL _SFR_MEM8(0xC4) #define UBRR0 0 #define UBRR1 1 #define UBRR2 2 #define UBRR3 3 #define UBRR4 4 #define UBRR5 5 #define UBRR6 6 #define UBRR7 7 #define UBRRH _SFR_MEM8(0xC5) #define UBRR8 0 #define UBRR9 1 #define UBRR10 2 #define UBRR11 3 #define UDR _SFR_MEM8(0xC6) #define UDR0 0 #define UDR1 1 #define UDR2 2 #define UDR3 3 #define UDR4 4 #define UDR5 5 #define UDR6 6 #define UDR7 7 #define EUCSRA _SFR_MEM8(0xC8) #define URxS0 0 #define URxS1 1 #define URxS2 2 #define URxS3 3 #define UTxS0 4 #define UTxS1 5 #define UTxS2 6 #define UTxS3 7 #define EUCSRB _SFR_MEM8(0xC9) #define BODR 0 #define EMCH 1 #define EUSBS 3 #define EUSART 4 #define EUCSRC _SFR_MEM8(0xCA) #define STP0 0 #define STP1 1 #define F1617 2 #define FEM 3 #define MUBRR _SFR_MEM16(0xCC) #define MUBRRL _SFR_MEM8(0xCC) #define MUBRR0 0 #define MUBRR1 1 #define MUBRR2 2 #define MUBRR3 3 #define MUBRR4 4 #define MUBRR5 5 #define MUBRR6 6 #define MUBRR7 7 #define MUBRRH _SFR_MEM8(0xCD) #define MUBRR8 0 #define MUBRR9 1 #define MUBRR10 2 #define MUBRR11 3 #define MUBRR12 4 #define MUBRR13 5 #define MUBRR14 6 #define MUBRR15 7 #define EUDR _SFR_MEM8(0xCE) #define EUDR0 0 #define EUDR1 1 #define EUDR2 2 #define EUDR3 3 #define EUDR4 4 #define EUDR5 5 #define EUDR6 6 #define EUDR7 7 #define PSOC0 _SFR_MEM8(0xD0) #define POEN0A 0 #define POEN0B 2 #define PSYNC00 4 #define PSYNC01 5 #define OCR0SA _SFR_MEM16(0xD2) #define OCR0SAL _SFR_MEM8(0xD2) #define OCR0SA_0 0 #define OCR0SA_1 1 #define OCR0SA_2 2 #define OCR0SA_3 3 #define OCR0SA_4 4 #define OCR0SA_5 5 #define OCR0SA_6 6 #define OCR0SA_7 7 #define OCR0SAH _SFR_MEM8(0xD3) #define OCR0SA_8 0 #define OCR0SA_9 1 #define OCR0SA_00 2 #define OCR0SA_01 3 #define OCR0RA _SFR_MEM16(0xD4) #define OCR0RAL _SFR_MEM8(0xD4) #define OCR0RA_0 0 #define OCR0RA_1 1 #define OCR0RA_2 2 #define OCR0RA_3 3 #define OCR0RA_4 4 #define OCR0RA_5 5 #define OCR0RA_6 6 #define OCR0RA_7 7 #define OCR0RAH _SFR_MEM8(0xD5) #define OCR0RA_8 0 #define OCR0RA_9 1 #define OCR0RA_00 2 #define OCR0RA_01 3 #define OCR0SB _SFR_MEM16(0xD6) #define OCR0SBL _SFR_MEM8(0xD6) #define OCR0SB_0 0 #define OCR0SB_1 1 #define OCR0SB_2 2 #define OCR0SB_3 3 #define OCR0SB_4 4 #define OCR0SB_5 5 #define OCR0SB_6 6 #define OCR0SB_7 7 #define OCR0SBH _SFR_MEM8(0xD7) #define OCR0SB_8 0 #define OCR0SB_9 1 #define OCR0SB_00 2 #define OCR0SB_01 3 #define OCR0RB _SFR_MEM16(0xD8) #define OCR0RBL _SFR_MEM8(0xD8) #define OCR0RB_0 0 #define OCR0RB_1 1 #define OCR0RB_2 2 #define OCR0RB_3 3 #define OCR0RB_4 4 #define OCR0RB_5 5 #define OCR0RB_6 6 #define OCR0RB_7 7 #define OCR0RBH _SFR_MEM8(0xD9) #define OCR0RB_8 0 #define OCR0RB_9 1 #define OCR0RB_00 2 #define OCR0RB_01 3 #define OCR0RB_02 4 #define OCR0RB_03 5 #define OCR0RB_04 6 #define OCR0RB_05 7 #define PCNF0 _SFR_MEM8(0xDA) #define PCLKSEL0 1 #define POP0 2 #define PMODE00 3 #define PMODE01 4 #define PLOCK0 5 #define PALOCK0 6 #define PFIFTY0 7 #define PCTL0 _SFR_MEM8(0xDB) #define PRUN0 0 #define PCCYC0 1 #define PARUN0 2 #define PAOC0A 3 #define PAOC0B 4 #define PBFM0 5 #define PPRE00 6 #define PPRE01 7 #define PFRC0A _SFR_MEM8(0xDC) #define PRFM0A0 0 #define PRFM0A1 1 #define PRFM0A2 2 #define PRFM0A3 3 #define PFLTE0A 4 #define PELEV0A 5 #define PISEL0A 6 #define PCAE0A 7 #define PFRC0B _SFR_MEM8(0xDD) #define PRFM0B0 0 #define PRFM0B1 1 #define PRFM0B2 2 #define PRFM0B3 3 #define PFLTE0B 4 #define PELEV0B 5 #define PISEL0B 6 #define PCAE0B 7 #define PICR0 _SFR_MEM16(0xDE) #define PICR0L _SFR_MEM8(0xDE) #define PICR0_0 0 #define PICR0_1 1 #define PICR0_2 2 #define PICR0_3 3 #define PICR0_4 4 #define PICR0_5 5 #define PICR0_6 6 #define PICR0_7 7 #define PICR0H _SFR_MEM8(0xDF) #define PICR0_8 0 #define PICR0_9 1 #define PICR0_10 2 #define PICR0_11 3 #define PCST0 7 #define PSOC1 _SFR_MEM8(0xE0) #define POEN1A 0 #define POEN1B 2 #define PSYNC1_0 4 #define PSYNC1_1 5 #define OCR1SA _SFR_MEM16(0xE2) #define OCR1SAL _SFR_MEM8(0xE2) #define OCR1SA_0 0 #define OCR1SA_1 1 #define OCR1SA_2 2 #define OCR1SA_3 3 #define OCR1SA_4 4 #define OCR1SA_5 5 #define OCR1SA_6 6 #define OCR1SA_7 7 #define OCR1SAH _SFR_MEM8(0xE3) #define OCR1SA_8 0 #define OCR1SA_9 1 #define OCR1SA_10 2 #define OCR1SA_11 3 #define OCR1RA _SFR_MEM16(0xE4) #define OCR1RAL _SFR_MEM8(0xE4) #define OCR1RA_0 0 #define OCR1RA_1 1 #define OCR1RA_2 2 #define OCR1RA_3 3 #define OCR1RA_4 4 #define OCR1RA_5 5 #define OCR1RA_6 6 #define OCR1RA_7 7 #define OCR1RAH _SFR_MEM8(0xE5) #define OCR1RA_8 0 #define OCR1RA_9 1 #define OCR1RA_10 2 #define OCR1RA_11 3 #define OCR1SB _SFR_MEM16(0xE6) #define OCR1SBL _SFR_MEM8(0xE6) #define OCR1SB_0 0 #define OCR1SB_1 1 #define OCR1SB_2 2 #define OCR1SB_3 3 #define OCR1SB_4 4 #define OCR1SB_5 5 #define OCR1SB_6 6 #define OCR1SB_7 7 #define OCR1SBH _SFR_MEM8(0xE7) #define OCR1SB_8 0 #define OCR1SB_9 1 #define OCR1SB_10 2 #define OCR1SB_11 3 #define OCR1RB _SFR_MEM16(0xE8) #define OCR1RBL _SFR_MEM8(0xE8) #define OCR1RB_0 0 #define OCR1RB_1 1 #define OCR1RB_2 2 #define OCR1RB_3 3 #define OCR1RB_4 4 #define OCR1RB_5 5 #define OCR1RB_6 6 #define OCR1RB_7 7 #define OCR1RBH _SFR_MEM8(0xE9) #define OCR1RB_8 0 #define OCR1RB_9 1 #define OCR1RB_10 2 #define OCR1RB_11 3 #define OCR1RB_12 4 #define OCR1RB_13 5 #define OCR1RB_14 6 #define OCR1RB_15 7 #define PCNF1 _SFR_MEM8(0xEA) #define PCLKSEL1 1 #define POP1 2 #define PMODE10 3 #define PMODE11 4 #define PLOCK1 5 #define PALOCK1 6 #define PFIFTY1 7 #define PCTL1 _SFR_MEM8(0xEB) #define PRUN1 0 #define PCCYC1 1 #define PARUN1 2 #define PAOC1A 3 #define PAOC1B 4 #define PBFM1 5 #define PPRE10 6 #define PPRE11 7 #define PFRC1A _SFR_MEM8(0xEC) #define PRFM1A0 0 #define PRFM1A1 1 #define PRFM1A2 2 #define PRFM1A3 3 #define PFLTE1A 4 #define PELEV1A 5 #define PISEL1A 6 #define PCAE1A 7 #define PFRC1B _SFR_MEM8(0xED) #define PRFM1B0 0 #define PRFM1B1 1 #define PRFM1B2 2 #define PRFM1B3 3 #define PFLTE1B 4 #define PELEV1B 5 #define PISEL1B 6 #define PCAE1B 7 #define PICR1 _SFR_MEM16(0xEE) #define PICR1L _SFR_MEM8(0xEE) #define PICR1_0 0 #define PICR1_1 1 #define PICR1_2 2 #define PICR1_3 3 #define PICR1_4 4 #define PICR1_5 5 #define PICR1_6 6 #define PICR1_7 7 #define PICR1H _SFR_MEM8(0xEF) #define PICR1_8 0 #define PICR1_9 1 #define PICR1_10 2 #define PICR1_11 3 #define PCST1 7 #define PSOC2 _SFR_MEM8(0xF0) #define POEN2A 0 #define POEN2C 1 #define POEN2B 2 #define POEN2D 3 #define PSYNC2_0 4 #define PSYNC2_1 5 #define POS22 6 #define POS23 7 #define POM2 _SFR_MEM8(0xF1) #define POMV2A0 0 #define POMV2A1 1 #define POMV2A2 2 #define POMV2A3 3 #define POMV2B0 4 #define POMV2B1 5 #define POMV2B2 6 #define POMV2B3 7 #define OCR2SA _SFR_MEM16(0xF2) #define OCR2SAL _SFR_MEM8(0xF2) #define OCR2SA_0 0 #define OCR2SA_1 1 #define OCR2SA_2 2 #define OCR2SA_3 3 #define OCR2SA_4 4 #define OCR2SA_5 5 #define OCR2SA_6 6 #define OCR2SA_7 7 #define OCR2SAH _SFR_MEM8(0xF3) #define OCR2SA_8 0 #define OCR2SA_9 1 #define OCR2SA_10 2 #define OCR2SA_11 3 #define OCR2RA _SFR_MEM16(0xF4) #define OCR2RAL _SFR_MEM8(0xF4) #define OCR2RA_0 0 #define OCR2RA_1 1 #define OCR2RA_2 2 #define OCR2RA_3 3 #define OCR2RA_4 4 #define OCR2RA_5 5 #define OCR2RA_6 6 #define OCR2RA_7 7 #define OCR2RAH _SFR_MEM8(0xF5) #define OCR2RA_8 0 #define OCR2RA_9 1 #define OCR2RA_10 2 #define OCR2RA_11 3 #define OCR2SB _SFR_MEM16(0xF6) #define OCR2SBL _SFR_MEM8(0xF6) #define OCR2SB_0 0 #define OCR2SB_1 1 #define OCR2SB_2 2 #define OCR2SB_3 3 #define OCR2SB_4 4 #define OCR2SB_5 5 #define OCR2SB_6 6 #define OCR2SB_7 7 #define OCR2SBH _SFR_MEM8(0xF7) #define OCR2SB_8 0 #define OCR2SB_9 1 #define OCR2SB_10 2 #define OCR2SB_11 3 #define OCR2RB _SFR_MEM16(0xF8) #define OCR2RBL _SFR_MEM8(0xF8) #define OCR2RB_0 0 #define OCR2RB_1 1 #define OCR2RB_2 2 #define OCR2RB_3 3 #define OCR2RB_4 4 #define OCR2RB_5 5 #define OCR2RB_6 6 #define OCR2RB_7 7 #define OCR2RBH _SFR_MEM8(0xF9) #define OCR2RB_8 0 #define OCR2RB_9 1 #define OCR2RB_10 2 #define OCR2RB_11 3 #define OCR2RB_12 4 #define OCR2RB_13 5 #define OCR2RB_14 6 #define OCR2RB_15 7 #define PCNF2 _SFR_MEM8(0xFA) #define POME2 0 #define PCLKSEL2 1 #define POP2 2 #define PMODE20 3 #define PMODE21 4 #define PLOCK2 5 #define PALOCK2 6 #define PFIFTY2 7 #define PCTL2 _SFR_MEM8(0xFB) #define PRUN2 0 #define PCCYC2 1 #define PARUN2 2 #define PAOC2A 3 #define PAOC2B 4 #define PBFM2 5 #define PPRE20 6 #define PPRE21 7 #define PFRC2A _SFR_MEM8(0xFC) #define PRFM2A0 0 #define PRFM2A1 1 #define PRFM2A2 2 #define PRFM2A3 3 #define PFLTE2A 4 #define PELEV2A 5 #define PISEL2A 6 #define PCAE2A 7 #define PFRC2B _SFR_MEM8(0xFD) #define PRFM2B0 0 #define PRFM2B1 1 #define PRFM2B2 2 #define PRFM2B3 3 #define PFLTE2B 4 #define PELEV2B 5 #define PISEL2B 6 #define PCAE2B 7 #define PICR2 _SFR_MEM16(0xFE) #define PICR2L _SFR_MEM8(0xFE) #define PICR2_0 0 #define PICR2_1 1 #define PICR2_2 2 #define PICR2_3 3 #define PICR2_4 4 #define PICR2_5 5 #define PICR2_6 6 #define PICR2_7 7 #define PICR2H _SFR_MEM8(0xFF) #define PICR2_8 0 #define PICR2_9 1 #define PICR2_10 2 #define PICR2_11 3 #define PCST2 7 /* Interrupt Vectors */ /* Interrupt vector 0 is the reset vector. */ #define PSC2_CAPT_vect_num 1 #define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ #define PSC2_EC_vect_num 2 #define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ #define PSC1_CAPT_vect_num 3 #define PSC1_CAPT_vect _VECTOR(3) /* PSC1 Capture Event */ #define PSC1_EC_vect_num 4 #define PSC1_EC_vect _VECTOR(4) /* PSC1 End Cycle */ #define PSC0_CAPT_vect_num 5 #define PSC0_CAPT_vect _VECTOR(5) /* PSC0 Capture Event */ #define PSC0_EC_vect_num 6 #define PSC0_EC_vect _VECTOR(6) /* PSC0 End Cycle */ #define ANALOG_COMP_0_vect_num 7 #define ANALOG_COMP_0_vect _VECTOR(7) /* Analog Comparator 0 */ #define ANALOG_COMP_1_vect_num 8 #define ANALOG_COMP_1_vect _VECTOR(8) /* Analog Comparator 1 */ #define ANALOG_COMP_2_vect_num 9 #define ANALOG_COMP_2_vect _VECTOR(9) /* Analog Comparator 2 */ #define INT0_vect_num 10 #define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter Compare Match B */ /* Vector 14, Reserved */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 16 #define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ #define ADC_vect_num 18 #define ADC_vect _VECTOR(18) /* ADC Conversion Complete */ #define INT1_vect_num 19 #define INT1_vect _VECTOR(19) /* External Interrupt Request 1 */ #define SPI_STC_vect_num 20 #define SPI_STC_vect _VECTOR(20) /* SPI Serial Transfer Complete */ #define USART_RX_vect_num 21 #define USART_RX_vect _VECTOR(21) /* USART, Rx Complete */ #define USART_UDRE_vect_num 22 #define USART_UDRE_vect _VECTOR(22) /* USART Data Register Empty */ #define USART_TX_vect_num 23 #define USART_TX_vect _VECTOR(23) /* USART, Tx Complete */ #define INT2_vect_num 24 #define INT2_vect _VECTOR(24) /* External Interrupt Request 2 */ #define WDT_vect_num 25 #define WDT_vect _VECTOR(25) /* Watchdog Timeout Interrupt */ #define EE_READY_vect_num 26 #define EE_READY_vect _VECTOR(26) /* EEPROM Ready */ #define TIMER0_COMPB_vect_num 27 #define TIMER0_COMPB_vect _VECTOR(27) /* Timer Counter 0 Compare Match B */ #define INT3_vect_num 28 #define INT3_vect _VECTOR(28) /* External Interrupt Request 3 */ /* Vector 29, Reserved */ /* Vector 30, Reserved */ #define SPM_READY_vect_num 31 #define SPM_READY_vect _VECTOR(31) /* Store Program Memory Read */ #define _VECTORS_SIZE 64 /* Memory Sizes */ #define RAMEND 0x2FF #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF #define SPM_PAGESIZE 64 /* Fuse Information */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ #define FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ #define FUSE_PSC1RB (unsigned char)~_BV(6) /* PSC1 Reset Behaviour */ #define FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x83 #endif /* _AVR_IO90PWM2B_H_ */ avr-libc-1.8.0.orig/include/avr/crc16.h0000644000000000000000000000334411732702554014360 0ustar /* Copyright (c) 2005 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: crc16.h 933 2005-11-05 22:23:16Z joerg_wunsch $ */ #ifndef _AVR_CRC16_H_ #define _AVR_CRC16_H_ #warning "This file has been moved to ." #include #endif /* _AVR_CRC16_H_ */ avr-libc-1.8.0.orig/include/avr/iom162.h0000644000000000000000000005265611732702554014471 0ustar /* Copyright (c) 2002, Nils Kristian Strom All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom162.h 2230 2011-03-06 02:42:04Z arcanum $ */ /* iom162.h - definitions for ATmega162 */ #ifndef _AVR_IOM162_H_ #define _AVR_IOM162_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom162.h" #else # error "Attempt to include more than one file." #endif /* Memory mapped I/O registers */ /* Timer/Counter3 Control Register A */ #define TCCR3A _SFR_MEM8(0x8B) /* Timer/Counter3 Control Register B */ #define TCCR3B _SFR_MEM8(0x8A) /* Timer/Counter3 - Counter Register */ #define TCNT3H _SFR_MEM8(0x89) #define TCNT3L _SFR_MEM8(0x88) #define TCNT3 _SFR_MEM16(0x88) /* Timer/Counter3 - Output Compare Register A */ #define OCR3AH _SFR_MEM8(0x87) #define OCR3AL _SFR_MEM8(0x86) #define OCR3A _SFR_MEM16(0x86) /* Timer/Counter3 - Output Compare Register B */ #define OCR3BH _SFR_MEM8(0x85) #define OCR3BL _SFR_MEM8(0x84) #define OCR3B _SFR_MEM16(0x84) /* Timer/Counter3 - Input Capture Register */ #define ICR3H _SFR_MEM8(0x81) #define ICR3L _SFR_MEM8(0x80) #define ICR3 _SFR_MEM16(0x80) /* Extended Timer/Counter Interrupt Mask */ #define ETIMSK _SFR_MEM8(0x7D) /* Extended Timer/Counter Interrupt Flag Register */ #define ETIFR _SFR_MEM8(0x7C) /* Pin Change Mask Register 1 */ #define PCMSK1 _SFR_MEM8(0x6C) /* Pin Change Mask Register 0 */ #define PCMSK0 _SFR_MEM8(0x6B) /* Clock PRescale */ #define CLKPR _SFR_MEM8(0x61) /* Standard I/O registers */ /* 0x3F SREG */ /* 0x3D..0x3E SP */ #define UBRR1H _SFR_IO8(0x3C) /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */ #define UCSR1C _SFR_IO8(0x3C) /* USART 1 Control and Status Register, Shared with UBRR1H */ #define GICR _SFR_IO8(0x3B) /* General Interrupt Control Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt Flag Register */ #define TIMSK _SFR_IO8(0x39) /* Timer Interrupt Mask */ #define TIFR _SFR_IO8(0x38) /* Timer Interrupt Flag Register */ #define SPMCR _SFR_IO8(0x37) /* Store Program Memory Control Register */ #define EMCUCR _SFR_IO8(0x36) /* Extended MCU Control Register */ #define MCUCR _SFR_IO8(0x35) /* MCU Control Register */ #define MCUCSR _SFR_IO8(0x34) /* MCU Control and Status Register */ #define TCCR0 _SFR_IO8(0x33) /* Timer/Counter 0 Control Register */ #define TCNT0 _SFR_IO8(0x32) /* TImer/Counter 0 */ #define OCR0 _SFR_IO8(0x31) /* Output Compare Register 0 */ #define SFIOR _SFR_IO8(0x30) /* Special Function I/O Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 1 Control Register A */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register A */ #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 High Byte */ #define TCNT1L _SFR_IO8(0x2C) /* Timer/Counter 1 Low Byte */ #define TCNT1 _SFR_IO16(0x2C) /* Timer/Counter 1 */ #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 Output Compare Register A High Byte */ #define OCR1AL _SFR_IO8(0x2A) /* Timer/Counter 1 Output Compare Register A Low Byte */ #define OCR1A _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */ #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter 1 Output Compare Register B High Byte */ #define OCR1BL _SFR_IO8(0x28) /* Timer/Counter 1 Output Compare Register B Low Byte */ #define OCR1B _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */ #define TCCR2 _SFR_IO8(0x27) /* Timer/Counter 2 Control Register */ #define ASSR _SFR_IO8(0x26) /* Asynchronous Status Register */ #define ICR1H _SFR_IO8(0x25) /* Input Capture Register 1 High Byte */ #define ICR1L _SFR_IO8(0x24) /* Input Capture Register 1 Low Byte */ #define ICR1 _SFR_IO16(0x24) /* Input Capture Register 1 */ #define TCNT2 _SFR_IO8(0x23) /* Timer/Counter 2 */ #define OCR2 _SFR_IO8(0x22) /* Timer/Counter 2 Output Compare Register */ #define WDTCR _SFR_IO8(0x21) /* Watchdow Timer Control Register */ #define UBRR0H _SFR_IO8(0x20) /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */ #define UCSR0C _SFR_IO8(0x20) /* USART 0 Control and Status Register C, Shared with UBRR0H */ #define EEARH _SFR_IO8(0x1F) /* EEPROM Address Register High Byte */ #define EEARL _SFR_IO8(0x1E) /* EEPROM Address Register Low Byte */ #define EEAR _SFR_IO16(0x1E) /* EEPROM Address Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Data Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Control Register */ #define PORTA _SFR_IO8(0x1B) /* Port A */ #define DDRA _SFR_IO8(0x1A) /* Port A Data Direction Register */ #define PINA _SFR_IO8(0x19) /* Port A Pin Register */ #define PORTB _SFR_IO8(0x18) /* Port B */ #define DDRB _SFR_IO8(0x17) /* Port B Data Direction Register */ #define PINB _SFR_IO8(0x16) /* Port B Pin Register */ #define PORTC _SFR_IO8(0x15) /* Port C */ #define DDRC _SFR_IO8(0x14) /* Port C Data Direction Register */ #define PINC _SFR_IO8(0x13) /* Port C Pin Register */ #define PORTD _SFR_IO8(0x12) /* Port D */ #define DDRD _SFR_IO8(0x11) /* Port D Data Direction Register */ #define PIND _SFR_IO8(0x10) /* Port D Pin Register */ #define SPDR _SFR_IO8(0x0F) /* SPI Data Register */ #define SPSR _SFR_IO8(0x0E) /* SPI Status Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Control Register */ #define UDR0 _SFR_IO8(0x0C) /* USART 0 Data Register */ #define UCSR0A _SFR_IO8(0x0B) /* USART 0 Control and Status Register A */ #define UCSR0B _SFR_IO8(0x0A) /* USART 0 Control and Status Register B */ #define UBRR0L _SFR_IO8(0x09) /* USART 0 Baud-Rate Register Low Byte */ #define ACSR _SFR_IO8(0x08) /* Analog Comparator Status Register */ #define PORTE _SFR_IO8(0x07) /* Port E */ #define DDRE _SFR_IO8(0x06) /* Port E Data Direction Register */ #define PINE _SFR_IO8(0x05) /* Port E Pin Register */ #define OSCCAL _SFR_IO8(0x04) /* Oscillator Calibration, Shared with OCDR */ #define OCDR _SFR_IO8(0x04) /* On-Chip Debug Register, Shared with OSCCAL */ #define UDR1 _SFR_IO8(0x03) /* USART 1 Data Register */ #define UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */ #define UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */ #define UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */ /* Interrupt vectors (byte addresses) */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 4 #define PCINT0_vect _VECTOR(4) #define SIG_PIN_CHANGE0 _VECTOR(4) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 5 #define PCINT1_vect _VECTOR(5) #define SIG_PIN_CHANGE1 _VECTOR(5) /* Timer/Counter3 Capture Event */ #define TIMER3_CAPT_vect_num 6 #define TIMER3_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE3 _VECTOR(6) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPA_vect_num 7 #define TIMER3_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE3A _VECTOR(7) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPB_vect_num 8 #define TIMER3_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE3B _VECTOR(8) /* Timer/Counter3 Overflow */ #define TIMER3_OVF_vect_num 9 #define TIMER3_OVF_vect _VECTOR(9) #define SIG_OVERFLOW3 _VECTOR(9) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 10 #define TIMER2_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE2 _VECTOR(10) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 11 #define TIMER2_OVF_vect _VECTOR(11) #define SIG_OVERFLOW2 _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 12 #define TIMER1_CAPT_vect _VECTOR(12) #define SIG_INPUT_CAPTURE1 _VECTOR(12) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1A _VECTOR(13) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE1B _VECTOR(14) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) #define SIG_OVERFLOW1 _VECTOR(15) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 16 #define TIMER0_COMP_vect _VECTOR(16) #define SIG_OUTPUT_COMPARE0 _VECTOR(16) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) #define SIG_OVERFLOW0 _VECTOR(17) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 18 #define SPI_STC_vect _VECTOR(18) #define SIG_SPI _VECTOR(18) /* USART0, Rx Complete */ #define USART0_RXC_vect_num 19 #define USART0_RXC_vect _VECTOR(19) #define SIG_USART0_RECV _VECTOR(19) /* USART1, Rx Complete */ #define USART1_RXC_vect_num 20 #define USART1_RXC_vect _VECTOR(20) #define SIG_USART1_RECV _VECTOR(20) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 21 #define USART0_UDRE_vect _VECTOR(21) #define SIG_USART0_DATA _VECTOR(21) /* USART1, Data register Empty */ #define USART1_UDRE_vect_num 22 #define USART1_UDRE_vect _VECTOR(22) #define SIG_USART1_DATA _VECTOR(22) /* USART0, Tx Complete */ #define USART0_TXC_vect_num 23 #define USART0_TXC_vect _VECTOR(23) #define SIG_USART0_TRANS _VECTOR(23) /* USART1, Tx Complete */ #define USART1_TXC_vect_num 24 #define USART1_TXC_vect _VECTOR(24) #define SIG_USART1_TRANS _VECTOR(24) /* EEPROM Ready */ #define EE_RDY_vect_num 25 #define EE_RDY_vect _VECTOR(25) #define SIG_EEPROM_READY _VECTOR(25) /* Analog Comparator */ #define ANA_COMP_vect_num 26 #define ANA_COMP_vect _VECTOR(26) #define SIG_COMPARATOR _VECTOR(26) /* Store Program Memory Read */ #define SPM_RDY_vect_num 27 #define SPM_RDY_vect _VECTOR(27) #define SIG_SPM_READY _VECTOR(27) #define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */ /* TCCR3B bit definitions, memory mapped I/O */ #define ICNC3 7 #define ICES3 6 #define WGM33 4 #define WGM32 3 #define CS32 2 #define CS31 1 #define CS30 0 /* TCCR3A bit definitions, memory mapped I/O */ #define COM3A1 7 #define COM3A0 6 #define COM3B1 5 #define COM3B0 4 #define FOC3A 3 #define FOC3B 2 #define WGM31 1 #define WGM30 0 /* ETIMSK bit definitions, memory mapped I/O */ #define TICIE3 5 #define OCIE3A 4 #define OCIE3B 3 #define TOIE3 2 /* ETIFR bit definitions, memory mapped I/O */ #define ICF3 5 #define OCF3A 4 #define OCF3B 3 #define TOV3 2 /* PCMSK1 bit definitions, memory mapped I/O */ #define PCINT15 7 #define PCINT14 6 #define PCINT13 5 #define PCINT12 4 #define PCINT11 3 #define PCINT10 2 #define PCINT9 1 #define PCINT8 0 /* PCMSK0 bit definitions, memory mapped I/O */ #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 /* CLKPR bit definitions, memory mapped I/O */ #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 /* SPH bit definitions */ #define SP15 15 #define SP14 14 #define SP13 13 #define SP12 12 #define SP11 11 #define SP10 10 #define SP9 9 #define SP8 8 /* SPL bit definitions */ #define SP7 7 #define SP6 6 #define SP5 5 #define SP4 4 #define SP3 3 #define SP2 2 #define SP1 1 #define SP0 0 /* UBRR1H bit definitions */ #define URSEL1 7 #define UBRR111 3 #define UBRR110 2 #define UBRR19 1 #define UBRR18 0 /* UCSR1C bit definitions */ #define URSEL1 7 #define UMSEL1 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPOL1 0 /* GICR bit definitions */ #define INT1 7 #define INT0 6 #define INT2 5 #define PCIE1 4 #define PCIE0 3 #define IVSEL 1 #define IVCE 0 /* GIFR bit definitions */ #define INTF1 7 #define INTF0 6 #define INTF2 5 #define PCIF1 4 #define PCIF0 3 /* TIMSK bit definitions */ #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 #define OCIE2 4 #define TICIE1 3 #define TOIE2 2 #define TOIE0 1 #define OCIE0 0 /* TIFR bit definitions */ #define TOV1 7 #define OCF1A 6 #define OCF1B 5 #define OCF2 4 #define ICF1 3 #define TOV2 2 #define TOV0 1 #define OCF0 0 /* SPMCR bit definitions */ #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* EMCUCR bit definitions */ #define SM0 7 #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW01 3 #define SRW00 2 #define SRW11 1 #define ISC2 0 /* MCUCR bit definitions */ #define SRE 7 #define SRW10 6 #define SE 5 #define SM1 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* MCUCSR bit definitions */ #define JTD 7 #define SM2 5 #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* TCCR0 bit definitions */ #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* SFIOR bit definitions */ #define TSM 7 #define XMBK 6 #define XMM2 5 #define XMM1 4 #define XMM0 3 #define PUD 2 #define PSR2 1 #define PSR310 0 /* TCCR1A bit definitions */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define WGM11 1 #define WGM10 0 /* TCCR1B bit definitions */ #define ICNC1 7 /* Input Capture Noise Canceler */ #define ICES1 6 /* Input Capture Edge Select */ #define WGM13 4 /* Waveform Generation Mode 3 */ #define WGM12 3 /* Waveform Generation Mode 2 */ #define CS12 2 /* Clock Select 2 */ #define CS11 1 /* Clock Select 1 */ #define CS10 0 /* Clock Select 0 */ /* TCCR2 bit definitions */ #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* ASSR bit definitions */ #define AS2 3 #define TCN2UB 2 #define TCON2UB 2 /* Kept for backwards compatibility. */ #define OCR2UB 1 #define TCR2UB 0 /* WDTCR bit definitions */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* UBRR0H bif definitions */ #define URSEL0 7 #define UBRR011 3 #define UBRR010 2 #define UBRR09 1 #define UBRR08 0 /* UCSR0C bit definitions */ #define URSEL0 7 #define UMSEL0 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UCSZ00 1 #define UCPOL0 0 /* EEARH bit definitions */ #define EEAR8 0 /* EECR bit definitions */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* PORTA bit definitions */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* DDRA bit definitions */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* PINA bit definitions */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* PORTB bit definitions */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB bit definitions */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB bit definitions */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PORTC bit definitions */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* DDRC bit definitions */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* PINC bit definitions */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* PORTD bit definitions */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD bit definitions */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND bit definitions */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPSR bit definitions */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPCR bit definitions */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UCSR0A bit definitions */ #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 /* UCSR0B bit definitions */ #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 /* ACSR bit definitions */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* PORTE bit definitions */ #define PE2 2 #define PE1 1 #define PE0 0 /* DDRE bit definitions */ #define DDE2 2 #define DDE1 1 #define DDE0 0 /* PINE bit definitions */ #define PINE2 2 #define PINE1 1 #define PINE0 0 /* UCSR1A bit definitions */ #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 /* UCSR1B bit definitions */ #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x4FF #define XRAMEND 0xFFFF #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define FUSE_M161C (unsigned char)~_BV(4) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x04 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_INPUT_CAPTURE3 #pragma GCC poison SIG_OUTPUT_COMPARE3A #pragma GCC poison SIG_OUTPUT_COMPARE3B #pragma GCC poison SIG_OVERFLOW3 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_USART0_RECV #pragma GCC poison SIG_USART1_RECV #pragma GCC poison SIG_USART0_DATA #pragma GCC poison SIG_USART1_DATA #pragma GCC poison SIG_USART0_TRANS #pragma GCC poison SIG_USART1_TRANS #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM162_H_ */ avr-libc-1.8.0.orig/include/avr/iocan128.h0000644000000000000000000000655011732702554014770 0ustar /* Copyright (c) 2004,2005, Colin O'Flynn All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iocan128.h 1767 2008-10-17 23:27:53Z arcanum $ */ /* iocan128.h - definitions for CAN128 */ #ifndef _AVR_IOCAN128_H_ #define _AVR_IOCAN128_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x10FF /* Last On-Chip SRAM Location */ #define XRAMEND 0xFFFF #define E2END 0x0FFF #define E2PAGESIZE 8 #define FLASHEND 0x1FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x81 #endif /* _AVR_IOCAN128_H_ */ avr-libc-1.8.0.orig/include/avr/builtins.h.in0000644000000000000000000000677511732702554015713 0ustar /* Copyright (c) 2008 Anatoly Sokolov Copyright (c) 2010 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: builtins.h.in 2103 2010-03-17 05:16:10Z joerg_wunsch $ */ /* avr/builtins.h - Intrinsic functions built into the compiler */ #ifndef _AVR_BUILTINS_H_ #define _AVR_BUILTINS_H_ #ifndef __HAS_DELAY_CYCLES #define __HAS_DELAY_CYCLES @HAS_DELAY_CYCLES@ #endif /** \file */ /** \defgroup avr_builtins : GCC builtins \code #include \endcode This header file declares AVR builtins. All the functions documented here are built into the compiler, and cause it to emit the corresponding assembly code instructions. */ /** \ingroup avr_builtins Enables interrupts by setting the global interrupt mask. */ extern void __builtin_avr_sei(void); /** \ingroup avr_builtins Disables all interrupts by clearing the global interrupt mask. */ extern void __builtin_avr_cli(void); /** \ingroup avr_builtins Emits a \c SLEEP instruction. */ extern void __builtin_avr_sleep(void); /** \ingroup avr_builtins Emits a WDR (watchdog reset) instruction. */ extern void __builtin_avr_wdr(void); /** \ingroup avr_builtins Emits a SWAP (nibble swap) instruction on __b. */ extern unsigned char __builtin_avr_swap(unsigned char __b); /** \ingroup avr_builtins Emits an FMUL (fractional multiply unsigned) instruction. */ extern unsigned int __builtin_avr_fmul(unsigned char __a, unsigned char __b); /** \ingroup avr_builtins Emits an FMUL (fractional multiply signed) instruction. */ extern int __builtin_avr_fmuls(char __a, char __b); /** \ingroup avr_builtins Emits an FMUL (fractional multiply signed with unsigned) instruction. */ extern int __builtin_avr_fmulsu(char __a, unsigned char __b); #if __HAS_DELAY_CYCLES || defined(__DOXYGEN__) /** \ingroup avr_builtins Emits a sequence of instructions causing the CPU to spend \c __n cycles on it. */ extern void __builtin_avr_delay_cycles(unsigned long __n); #endif #endif /* _AVR_BUILTINS_H_ */ avr-libc-1.8.0.orig/include/avr/iotn2313.h0000644000000000000000000004251711732702554014731 0ustar /* Copyright (c) 2004, 2005, 2006 Bob Paddock All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn2313.h 2236 2011-03-17 21:53:39Z arcanum $ */ /* iotn2313.h derived from io2313.h by Bob Paddock. The changes between the AT90S2313 and the ATtiny2313 are extensive. Atmel has renamed several registers, and bits. See Atmel application note AVR091, as well as the errata at the end of the current ATtiny2313 data sheet. Some of the names have changed more than once during the sampling period of the ATtiny2313. Where there is no conflict the new and old names are both supported. In the case of a new feature in a register, only the new name is used. This intentionally breaks old code, so that there are no silent bugs. The source code must be updated to the new name in this case. The hardware interrupt vector table has changed from that of the AT90S2313. ATtiny2313 programs in page mode rather than the byte mode of the AT90S2313. Beware of programming the ATtiny2313 as a AT90S2313 device, when programming the Flash. ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. Changes and/or additions are noted by "ATtiny" in the comments below. */ /* avr/iotn2313.h - definitions for ATtiny2313 */ #ifndef _AVR_IOTN2313_H_ #define _AVR_IOTN2313_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn2313.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* * The Register Bit names are represented by their bit number (0-7). * Example: PORTB |= _BV(PORTB7); Set MSB of PORTB. */ /* 0x00 Reserved */ /* ATtiny Digital Input Disable Register DIDR */ #define DIDR _SFR_IO8(0x01) #define AIN1D 1 #define AIN0D 0 /* ATtiny USART Baud Rate Register High UBBRH[11:8] */ #define UBRRH _SFR_IO8(0x02) /* ATtiny USART Control and Status Register C UCSRC */ #define UCSRC _SFR_IO8(0x03) #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* 0x04 -> 0x07 Reserved */ /* ATtiny Analog Comparator Control and Status Register ACSR */ #define ACSR _SFR_IO8(0x08) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* USART Baud Rate Register Low UBBRL[7:0] */ #define UBRRL _SFR_IO8(0x09) /* ATtiny USART Control Register UCSRB */ #define UCSRB _SFR_IO8(0x0A) #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 /* ATtiny USART Status Register UCSRA */ #define UCSRA _SFR_IO8(0x0B) #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define UPE 2 #define U2X 1 #define MPCM 0 /* USART I/O Data Register UBR or RXB[7:0], TXB[7:0] */ #define UDR _SFR_IO8(0x0C) #define RXB _SFR_IO8(0x0C) #define TXB _SFR_IO8(0x0C) /* ATtiny USI Control Register USICR */ #define USICR _SFR_IO8(0x0D) #define USISIE 7 #define USIOIE 6 #define USIWM1 5 #define USIWM0 4 #define USICS1 3 #define USICS0 2 #define USICLK 1 #define USITC 0 /* ATtiny USI Status Register USISR */ #define USISR _SFR_IO8(0x0E) #define USISIF 7 #define USIOIF 6 #define USIPF 5 #define USIDC 4 #define USICNT3 3 #define USICNT2 2 #define USICNT1 1 #define USICNT0 0 /* ATtiny USI Data Register USIDR[7:0] */ #define USIDR _SFR_IO8(0x0F) /* Input Pins, Port D PIND[6:0] */ #define PIND _SFR_IO8(0x10) #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Data Direction Register, Port D DDRD[6:0] */ #define DDRD _SFR_IO8(0x11) #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Data Register, Port D PORTD[6:0] */ #define PORTD _SFR_IO8(0x12) #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* ATtiny General Purpose I/O Register Zero GPIOR0[7:0] */ #define GPIOR0 _SFR_IO8(0x13) /* ATtiny General Purpose I/O Register One GPIOR1[7:0] */ #define GPIOR1 _SFR_IO8(0x14) /* ATtiny General Purpose I/O Register Two One GPIOR2[7:0] */ #define GPIOR2 _SFR_IO8(0x15) /* Input Pins, Port B PORTB[7:0] */ #define PINB _SFR_IO8(0x16) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Direction Register, Port B PORTB[7:0] */ #define DDRB _SFR_IO8(0x17) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Data Register, Port B PORTB[7:0] */ #define PORTB _SFR_IO8(0x18) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Port A Input Pins Address PINA[2:0] */ #define PINA _SFR_IO8(0x19) #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Port A Data Direction Register DDRA[2:0] */ #define DDRA _SFR_IO8(0x1A) #define DDRA2 2 #define DDRA1 1 #define DDRA0 0 /* Port A Data Register PORTA[2:0] */ #define PORTA _SFR_IO8(0x1B) #define PA2 2 #define PA1 1 #define PA0 0 /* ATtiny EEPROM Control Register EECR */ #define EECR _SFR_IO8(0x1C) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* The EEPROM Address Register EEAR[6:0] */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR6 6 #define EEAR5 5 #define EEAR4 4 #define EEAR3 3 #define EEAR2 2 #define EEAR1 1 #define EEAR0 0 /* 0x1F Reserved */ /* ATtiny Pin Change Mask Register PCMSK PCINT[7:0] */ #define PCMSK _SFR_IO8(0x20) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 /* ATtiny Watchdog Timer Control Register WDTCSR */ #define WDTCSR _SFR_IO8(0x21) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* ATtiny Timer/Counter1 Control Register C TCCR1C */ #define TCCR1C _SFR_IO8(0x22) #define FOC1A 7 #define FOC1B 6 /* General Timer/Counter Control Register GTCCR */ #define GTCCR _SFR_IO8(0x23) #define PSR10 0 /* T/C 1 Input Capture Register ICR1[15:0] */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* ATtiny Clock Prescale Register */ #define CLKPR _SFR_IO8(0x26) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 /* 0x27 Reserved */ /* ATtiny Output Compare Register 1 B OCR1B[15:0] */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Output Compare Register 1 OCR1A[15:0] */ #define OCR1 _SFR_IO16(0x2A) #define OCR1L _SFR_IO8(0x2A) #define OCR1H _SFR_IO8(0x2B) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 TCNT1[15:0] */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* ATtiny Timer/Counter 1 Control and Status Register TCCR1B */ #define TCCR1B _SFR_IO8(0x2E) #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 /* Was CTC1 in AT90S2313 */ #define CS12 2 #define CS11 1 #define CS10 0 /* ATtiny Timer/Counter 1 Control Register TCCR1A */ #define TCCR1A _SFR_IO8(0x2F) #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define WGM11 1 /* Was PWM11 in AT90S2313 */ #define WGM10 0 /* Was PWM10 in AT90S2313 */ /* ATtiny Timer/Counter Control Register A TCCR0A */ #define TCCR0A _SFR_IO8(0x30) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 /* ATtiny Oscillator Calibration Register OSCCAL[6:0] */ #define OSCCAL _SFR_IO8(0x31) #define CAL6 6 #define CAL5 5 #define CAL4 4 #define CAL3 3 #define CAL2 2 #define CAL1 1 #define CAL0 0 /* Timer/Counter 0 TCNT0[7:0] */ #define TCNT0 _SFR_IO8(0x32) /* ATtiny Timer/Counter 0 Control Register TCCR0B */ #define TCCR0B _SFR_IO8(0x33) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 /* ATtiny MCU Status Register MCUSR */ #define MCUSR _SFR_IO8(0x34) #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* ATtiny MCU general Control Register MCUCR */ #define MCUCR _SFR_IO8(0x35) #define PUD 7 #define SM1 6 #define SE 5 #define SM0 4 /* Some preliminary ATtiny2313 data sheets incorrectly refer to this bit as SMD; was SM in AT90S2313. */ #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* ATtiny Output Compare Register A OCR0A[7:0] */ #define OCR0A _SFR_IO8(0x36) /* ATtiny Store Program Memory Control and Status Register SPMCSR */ #define SPMCSR _SFR_IO8(0x37) #define CTPB 4 #define RFLB 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* The name is used in ATtiny2313.xml file. */ #define SELFPRGEN 0 /* The name is used in datasheet. */ #define SELFPRGE 0 /* The name is left for compatibility. */ /* ATtiny Timer/Counter Interrupt Flag register TIFR */ #define TIFR _SFR_IO8(0x38) #define TOV1 7 #define OCF1A 6 #define OCF1B 5 #define ICF1 3 #define OCF0B 2 #define TOV0 1 #define OCF0A 0 /* ATtiny Timer/Counter Interrupt MaSK register TIMSK */ #define TIMSK _SFR_IO8(0x39) #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 #define ICIE1 3 #define OCIE0B 2 #define TOIE0 1 #define OCIE0A 0 /* ATtiny External Interrupt Flag Register EIFR, was GIFR */ #define EIFR _SFR_IO8(0x3A) #define INTF1 7 #define INTF0 6 #define PCIF 5 /* ATtiny General Interrupt MaSK register GIMSK */ #define GIMSK _SFR_IO8(0x3B) #define INT1 7 #define INT0 6 #define PCIE 5 /* ATtiny Output Compare Register B OCR0B[7:0] */ #define OCR0B _SFR_IO8(0x3C) /* Interrupt vectors: */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) #define SIG_INT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) #define SIG_INT1 _VECTOR(2) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 3 #define TIMER1_CAPT_vect _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) #define SIG_TIMER1_CAPT _VECTOR(3) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 4 #define TIMER1_COMPA_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) #define SIG_TIMER1_COMPA _VECTOR(4) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 5 #define TIMER1_OVF_vect _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(5) #define SIG_TIMER1_OVF _VECTOR(5) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 6 #define TIMER0_OVF_vect _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(6) #define SIG_TIMER0_OVF _VECTOR(6) /* USART, Rx Complete */ #define USART_RX_vect_num 7 #define USART_RX_vect _VECTOR(7) #define SIG_USART0_RECV _VECTOR(7) #define SIG_USART0_RX _VECTOR(7) /* USART Data Register Empty */ #define USART_UDRE_vect_num 8 #define USART_UDRE_vect _VECTOR(8) #define SIG_USART0_DATA _VECTOR(8) #define SIG_USART0_UDRE _VECTOR(8) /* USART, Tx Complete */ #define USART_TX_vect_num 9 #define USART_TX_vect _VECTOR(9) #define SIG_USART0_TRANS _VECTOR(9) #define SIG_USART0_TX _VECTOR(9) /* Analog Comparator */ #define ANA_COMP_vect_num 10 #define ANA_COMP_vect _VECTOR(10) #define SIG_COMPARATOR _VECTOR(10) #define SIG_ANALOG_COMP _VECTOR(10) #define PCINT_vect_num 11 #define PCINT_vect _VECTOR(11) #define SIG_PIN_CHANGE _VECTOR(11) #define SIG_PCINT _VECTOR(11) #define TIMER1_COMPB_vect_num 12 #define TIMER1_COMPB_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1B _VECTOR(12) #define SIG_TIMER1_COMPB _VECTOR(12) #define TIMER0_COMPA_vect_num 13 #define TIMER0_COMPA_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE0A _VECTOR(13) #define SIG_TIMER0_COMPA _VECTOR(13) #define TIMER0_COMPB_vect_num 14 #define TIMER0_COMPB_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE0B _VECTOR(14) #define SIG_TIMER0_COMPB _VECTOR(14) /* USI Start Condition */ #define USI_START_vect_num 15 #define USI_START_vect _VECTOR(15) #define SIG_USI_START _VECTOR(15) /* USI Overflow */ #define USI_OVERFLOW_vect_num 16 #define USI_OVERFLOW_vect _VECTOR(16) #define SIG_USI_OVERFLOW _VECTOR(16) #define EEPROM_READY_vect_num 17 #define EEPROM_READY_vect _VECTOR(17) #define SIG_EEPROM_READY _VECTOR(17) #define SIG_EE_READY _VECTOR(17) /* Watchdog Timer Overflow */ #define WDT_OVERFLOW_vect_num 18 #define WDT_OVERFLOW_vect _VECTOR(18) #define SIG_WATCHDOG_TIMEOUT _VECTOR(18) #define SIG_WDT_OVERFLOW _VECTOR(18) /* 38 = (18*2)+2: Number of vectors times two, plus the reset vector */ #define _VECTORS_SIZE 38 /* Constants */ #define SPM_PAGESIZE 32 #define RAMSTART (0x60) #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 4 #define FLASHEND 0x07FF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_EESAVE (unsigned char)~_BV(6) #define FUSE_DWEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x0A /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INT1 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_TIMER1_CAPT #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_TIMER1_COMPA #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_TIMER1_OVF #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_TIMER0_OVF #pragma GCC poison SIG_USART0_RECV #pragma GCC poison SIG_USART0_RX #pragma GCC poison SIG_USART0_DATA #pragma GCC poison SIG_USART0_UDRE #pragma GCC poison SIG_USART0_TRANS #pragma GCC poison SIG_USART0_TX #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ANALOG_COMP #pragma GCC poison SIG_PIN_CHANGE #pragma GCC poison SIG_PCINT #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_TIMER1_COMPB #pragma GCC poison SIG_OUTPUT_COMPARE0A #pragma GCC poison SIG_TIMER0_COMPA #pragma GCC poison SIG_OUTPUT_COMPARE0B #pragma GCC poison SIG_TIMER0_COMPB #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_EE_READY #pragma GCC poison SIG_WATCHDOG_TIMEOUT #pragma GCC poison SIG_WDT_OVERFLOW #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOTN2313_H_ */ avr-libc-1.8.0.orig/include/avr/iocanxx.h0000644000000000000000000014520211732702554015113 0ustar /* Copyright (c) 2004,2005,2006 Colin O'Flynn All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iocanxx.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* This file is based largely on: - iom128.h by Peter Jansen (bit defines) - iom169.h by Juergen Schilling (register addresses) - AT90CAN128 Datasheet (bit defines and register addresses) - Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need to change) */ /* iocanxx.h - definitions for AT90CAN32, AT90CAN64 and AT90CAN128 */ #ifndef _AVR_IOCANXX_H_ #define _AVR_IOCANXX_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iocanxx.h" #else # error "Attempt to include more than one file." #endif /* I/O registers and bit definitions. */ /* RegDef: Port A */ #define PINA _SFR_IO8(0x00) #define DDRA _SFR_IO8(0x01) #define PORTA _SFR_IO8(0x02) /* RegDef: Port B */ #define PINB _SFR_IO8(0x03) #define DDRB _SFR_IO8(0x04) #define PORTB _SFR_IO8(0x05) /* RegDef: Port C */ #define PINC _SFR_IO8(0x06) #define DDRC _SFR_IO8(0x07) #define PORTC _SFR_IO8(0x08) /* RegDef: Port D */ #define PIND _SFR_IO8(0x09) #define DDRD _SFR_IO8(0x0A) #define PORTD _SFR_IO8(0x0B) /* RegDef: Port E */ #define PINE _SFR_IO8(0x0C) #define DDRE _SFR_IO8(0x0D) #define PORTE _SFR_IO8(0x0E) /* RegDef: Port F */ #define PINF _SFR_IO8(0x0F) #define DDRF _SFR_IO8(0x10) #define PORTF _SFR_IO8(0x11) /* RegDef: Port G */ #define PING _SFR_IO8(0x12) #define DDRG _SFR_IO8(0x13) #define PORTG _SFR_IO8(0x14) /* RegDef: Timer/Counter 0 interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) /* RegDef: Timer/Counter 1 interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) /* RegDef: Timer/Counter 2 interrupt Flag Register */ #define TIFR2 _SFR_IO8(0x17) /* RegDef: Timer/Counter 3 interrupt Flag Register */ #define TIFR3 _SFR_IO8(0x18) /* RegDef: External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) /* RegDef: External Interrupt Mask Register */ #define EIMSK _SFR_IO8(0x1D) /* RegDef: General Purpose I/O Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) /* RegDef: EEPROM Control Register */ #define EECR _SFR_IO8(0x1F) /* RegDef: EEPROM Data Register */ #define EEDR _SFR_IO8(0x20) /* RegDef: EEPROM Address Register */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0x22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* RegDef: General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) /* RegDef: Timer/Counter Control Register A */ #define TCCR0A _SFR_IO8(0x24) /* RegDef: Timer/Counter Register */ #define TCNT0 _SFR_IO8(0x26) /* RegDef: Output Compare Register A */ #define OCR0A _SFR_IO8(0x27) /* RegDef: General Purpose I/O Register 1 */ #define GPIOR1 _SFR_IO8(0x2A) /* RegDef: General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x2B) /* RegDef: SPI Control Register */ #define SPCR _SFR_IO8(0x2C) /* RegDef: SPI Status Register */ #define SPSR _SFR_IO8(0x2D) /* RegDef: SPI Data Register */ #define SPDR _SFR_IO8(0x2E) /* RegDef: Analog Comperator Control and Status Register */ #define ACSR _SFR_IO8(0x30) /* RegDef: On-chip Debug Register */ #define OCDR _SFR_IO8(0x31) /* RegDef: Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) /* RegDef: MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* RegDef: MCU Control Rgeister */ #define MCUCR _SFR_IO8(0x35) /* RegDef: Store Program Memory Control and Status Register */ #define SPMCSR _SFR_IO8(0x37) /* RegDef: RAMPZ register. */ #define RAMPZ _SFR_IO8(0x3B) /* RegDef: Watchdog Timer Control Register */ #define WDTCR _SFR_MEM8(0x60) /* RegDef: Clock Prescale Register */ #define CLKPR _SFR_MEM8(0x61) /* RegDef: Oscillator Calibration Register */ #define OSCCAL _SFR_MEM8(0x66) /* RegDef: External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x69) /* RegDef: External Interrupt Control Register B */ #define EICRB _SFR_MEM8(0x6A) /* RegDef: Timer/Counter 0 Interrupt Mask Register */ #define TIMSK0 _SFR_MEM8(0x6E) /* RegDef: Timer/Counter 1 Interrupt Mask Register */ #define TIMSK1 _SFR_MEM8(0x6F) /* RegDef: Timer/Counter 2 Interrupt Mask Register */ #define TIMSK2 _SFR_MEM8(0x70) /* RegDef: Timer/Counter 3 Interrupt Mask Register */ #define TIMSK3 _SFR_MEM8(0x71) /* RegDef: External Memory Control Register A */ #define XMCRA _SFR_MEM8(0x74) /* RegDef: External Memory Control Register A */ #define XMCRB _SFR_MEM8(0x75) /* RegDef: ADC Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) /* RegDef: ADC Control and Status Register A */ #define ADCSRA _SFR_MEM8(0x7A) /* RegDef: ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x7B) /* RegDef: ADC Multiplex Selection Register */ #define ADMUX _SFR_MEM8(0x7C) /* RegDef: Digital Input Disable Register 0 */ #define DIDR0 _SFR_MEM8(0x7E) /* RegDef: Digital Input Disable Register 1 */ #define DIDR1 _SFR_MEM8(0x7F) /* RegDef: Timer/Counter1 Control Register A */ #define TCCR1A _SFR_MEM8(0x80) /* RegDef: Timer/Counter1 Control Register B */ #define TCCR1B _SFR_MEM8(0x81) /* RegDef: Timer/Counter1 Control Register C */ #define TCCR1C _SFR_MEM8(0x82) /* RegDef: Timer/Counter1 Register */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* RegDef: Timer/Counter1 Input Capture Register */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* RegDef: Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* RegDef: Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* RegDef: Timer/Counter1 Output Compare Register C */ #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CH _SFR_MEM8(0x8D) /* RegDef: Timer/Counter3 Control Register A */ #define TCCR3A _SFR_MEM8(0x90) /* RegDef: Timer/Counter3 Control Register B */ #define TCCR3B _SFR_MEM8(0x91) /* RegDef: Timer/Counter3 Control Register C */ #define TCCR3C _SFR_MEM8(0x92) /* RegDef: Timer/Counter3 Register */ #define TCNT3 _SFR_MEM16(0x94) #define TCNT3L _SFR_MEM8(0x94) #define TCNT3H _SFR_MEM8(0x95) /* RegDef: Timer/Counter3 Input Capture Register */ #define ICR3 _SFR_MEM16(0x96) #define ICR3L _SFR_MEM8(0x96) #define ICR3H _SFR_MEM8(0x97) /* RegDef: Timer/Counter3 Output Compare Register A */ #define OCR3A _SFR_MEM16(0x98) #define OCR3AL _SFR_MEM8(0x98) #define OCR3AH _SFR_MEM8(0x99) /* RegDef: Timer/Counter3 Output Compare Register B */ #define OCR3B _SFR_MEM16(0x9A) #define OCR3BL _SFR_MEM8(0x9A) #define OCR3BH _SFR_MEM8(0x9B) /* RegDef: Timer/Counter3 Output Compare Register C */ #define OCR3C _SFR_MEM16(0x9C) #define OCR3CL _SFR_MEM8(0x9C) #define OCR3CH _SFR_MEM8(0x9D) /* RegDef: Timer/Counter2 Control Register A */ #define TCCR2A _SFR_MEM8(0xB0) /* RegDef: Timer/Counter2 Register */ #define TCNT2 _SFR_MEM8(0xB2) /* RegDef: Timer/Counter2 Output Compare Register */ #define OCR2A _SFR_MEM8(0xB3) /* RegDef: Asynchronous Status Register */ #define ASSR _SFR_MEM8(0xB6) /* RegDef: TWI Bit Rate Register */ #define TWBR _SFR_MEM8(0xB8) /* RegDef: TWI Status Register */ #define TWSR _SFR_MEM8(0xB9) /* RegDef: TWI (Slave) Address Register */ #define TWAR _SFR_MEM8(0xBA) /* RegDef: TWI Data Register */ #define TWDR _SFR_MEM8(0xBB) /* RegDef: TWI Control Register */ #define TWCR _SFR_MEM8(0xBC) /* RegDef: USART0 Control and Status Register A */ #define UCSR0A _SFR_MEM8(0xC0) /* RegDef: USART0 Control and Status Register B */ #define UCSR0B _SFR_MEM8(0xC1) /* RegDef: USART0 Control and Status Register C */ #define UCSR0C _SFR_MEM8(0xC2) /* RegDef: USART0 Baud Rate Register */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) /* RegDef: USART0 I/O Data Register */ #define UDR0 _SFR_MEM8(0xC6) /* RegDef: USART1 Control and Status Register A */ #define UCSR1A _SFR_MEM8(0xC8) /* RegDef: USART1 Control and Status Register B */ #define UCSR1B _SFR_MEM8(0xC9) /* RegDef: USART1 Control and Status Register C */ #define UCSR1C _SFR_MEM8(0xCA) /* RegDef: USART1 Baud Rate Register */ #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1H _SFR_MEM8(0xCD) /* RegDef: USART1 I/O Data Register */ #define UDR1 _SFR_MEM8(0xCE) /* RegDef: CAN General Control Register*/ #define CANGCON _SFR_MEM8(0xD8) /* RegDef: CAN General Status Register*/ #define CANGSTA _SFR_MEM8(0xD9) /* RegDef: CAN General Interrupt Register*/ #define CANGIT _SFR_MEM8(0xDA) /* RegDef: CAN General Interrupt Enable Register*/ #define CANGIE _SFR_MEM8(0xDB) /* Word Definition: CAN Enable MOb Register*/ #define CANEN _SFR_MEM16(0xDC) /* RegDef: CAN Enable MOb Register*/ #define CANEN2 _SFR_MEM8(0xDC) /* RegDef: CAN Enable MOb Register*/ #define CANEN1 _SFR_MEM8(0xDD) /* Word Definition: CAN Enable Interrupt MOb Register*/ #define CANIE _SFR_MEM16(0xDE) /* RegDef: CAN Enable Interrupt MOb Register*/ #define CANIE2 _SFR_MEM8(0xDE) /* RegDef: CAN Enable Interrupt MOb Register*/ #define CANIE1 _SFR_MEM8(0xDF) /* RegDef: CAN Status Interrupt MOb Register*/ /* * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT * register. */ #define CANSIT _SFR_MEM16(0xE0) #define CANSIT2 _SFR_MEM8(0xE0) #define CANSIT1 _SFR_MEM8(0xE1) /* RegDef: CAN Bit Timing Register 1*/ #define CANBT1 _SFR_MEM8(0xE2) /* RegDef: CAN Bit Timing Register 2*/ #define CANBT2 _SFR_MEM8(0xE3) /* RegDef: CAN Bit Timing Register 3*/ #define CANBT3 _SFR_MEM8(0xE4) /* RegDef: CAN Timer Control Register*/ #define CANTCON _SFR_MEM8(0xE5) /* RegDef: CAN Timer Register*/ #define CANTIM _SFR_MEM16(0xE6) #define CANTIML _SFR_MEM8(0xE6) #define CANTIMH _SFR_MEM8(0xE7) /* RegDef: CAN TTC Timer Register*/ #define CANTTC _SFR_MEM16(0xE8) #define CANTTCL _SFR_MEM8(0xE8) #define CANTTCH _SFR_MEM8(0xE9) /* RegDef: CAN Transmitt Error Counter Register*/ #define CANTEC _SFR_MEM8(0xEA) /* RegDef: CAN Receive Error Counter Register*/ #define CANREC _SFR_MEM8(0xEB) /* RegDef: CAN Highest Priority MOb Register*/ #define CANHPMOB _SFR_MEM8(0xEC) /* RegDef: CAN Page MOb Register*/ #define CANPAGE _SFR_MEM8(0xED) /* RegDef: CAN MOb Status Register*/ #define CANSTMOB _SFR_MEM8(0xEE) /* RegDef: CAN MOb Control and DLC Register*/ #define CANCDMOB _SFR_MEM8(0xEF) /* RegDef: CAN Identifier Tag Registers*/ #define CANIDT _SFR_MEM32(0xF0) #define CANIDT4 _SFR_MEM8(0xF0) #define CANIDT3 _SFR_MEM8(0xF1) #define CANIDT2 _SFR_MEM8(0xF2) #define CANIDT1 _SFR_MEM8(0xF3) /* RegDef: CAN Identifier Mask Registers */ #define CANIDM _SFR_MEM32(0xF4) #define CANIDM4 _SFR_MEM8(0xF4) #define CANIDM3 _SFR_MEM8(0xF5) #define CANIDM2 _SFR_MEM8(0xF6) #define CANIDM1 _SFR_MEM8(0xF7) /* RegDef: CAN TTC Timer Register*/ #define CANSTM _SFR_MEM16(0xF8) #define CANSTML _SFR_MEM8(0xF8) #define CANSTMH _SFR_MEM8(0xF9) /* RegDef: CAN Message Register*/ #define CANMSG _SFR_MEM8(0xFA) /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* External Interrupt Request 3 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) #define SIG_INTERRUPT3 _VECTOR(4) /* External Interrupt Request 4 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) #define SIG_INTERRUPT4 _VECTOR(5) /* External Interrupt Request 5 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) #define SIG_INTERRUPT5 _VECTOR(6) /* External Interrupt Request 6 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) #define SIG_INTERRUPT6 _VECTOR(7) /* External Interrupt Request 7 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) #define SIG_INTERRUPT7 _VECTOR(8) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 9 #define TIMER2_COMP_vect _VECTOR(9) #define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 10 #define TIMER2_OVF_vect _VECTOR(10) #define SIG_OVERFLOW2 _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) #define SIG_INPUT_CAPTURE1 _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* Timer/Counter1 Compare Match C */ #define TIMER1_COMPC_vect_num 14 #define TIMER1_COMPC_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE1C _VECTOR(14) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) #define SIG_OVERFLOW1 _VECTOR(15) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 16 #define TIMER0_COMP_vect _VECTOR(16) #define SIG_OUTPUT_COMPARE0 _VECTOR(16) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) #define SIG_OVERFLOW0 _VECTOR(17) /* CAN Transfer Complete or Error */ #define CANIT_vect_num 18 #define CANIT_vect _VECTOR(18) #define SIG_CAN_INTERRUPT1 _VECTOR(18) /* CAN Timer Overrun */ #define OVRIT_vect_num 19 #define OVRIT_vect _VECTOR(19) #define SIG_CAN_OVERFLOW1 _VECTOR(19) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 20 #define SPI_STC_vect _VECTOR(20) #define SIG_SPI _VECTOR(20) /* USART0, Rx Complete */ #define USART0_RX_vect_num 21 #define USART0_RX_vect _VECTOR(21) #define SIG_UART0_RECV _VECTOR(21) #define SIG_USART0_RECV _VECTOR(21) /* USART0 Data Register Empty */ #define USART0_UDRE_vect_num 22 #define USART0_UDRE_vect _VECTOR(22) #define SIG_UART0_DATA _VECTOR(22) #define SIG_USART0_DATA _VECTOR(22) /* USART0, Tx Complete */ #define USART0_TX_vect_num 23 #define USART0_TX_vect _VECTOR(23) #define SIG_UART0_TRANS _VECTOR(23) #define SIG_USART0_TRANS _VECTOR(23) /* Analog Comparator */ #define ANALOG_COMP_vect_num 24 #define ANALOG_COMP_vect _VECTOR(24) #define SIG_COMPARATOR _VECTOR(24) /* ADC Conversion Complete */ #define ADC_vect_num 25 #define ADC_vect _VECTOR(25) #define SIG_ADC _VECTOR(25) /* EEPROM Ready */ #define EE_READY_vect_num 26 #define EE_READY_vect _VECTOR(26) #define SIG_EEPROM_READY _VECTOR(26) /* Timer/Counter3 Capture Event */ #define TIMER3_CAPT_vect_num 27 #define TIMER3_CAPT_vect _VECTOR(27) #define SIG_INPUT_CAPTURE3 _VECTOR(27) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPA_vect_num 28 #define TIMER3_COMPA_vect _VECTOR(28) #define SIG_OUTPUT_COMPARE3A _VECTOR(28) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPB_vect_num 29 #define TIMER3_COMPB_vect _VECTOR(29) #define SIG_OUTPUT_COMPARE3B _VECTOR(29) /* Timer/Counter3 Compare Match C */ #define TIMER3_COMPC_vect_num 30 #define TIMER3_COMPC_vect _VECTOR(30) #define SIG_OUTPUT_COMPARE3C _VECTOR(30) /* Timer/Counter3 Overflow */ #define TIMER3_OVF_vect_num 31 #define TIMER3_OVF_vect _VECTOR(31) #define SIG_OVERFLOW3 _VECTOR(31) /* USART1, Rx Complete */ #define USART1_RX_vect_num 32 #define USART1_RX_vect _VECTOR(32) #define SIG_UART1_RECV _VECTOR(32) #define SIG_USART1_RECV _VECTOR(32) /* USART1, Data Register Empty */ #define USART1_UDRE_vect_num 33 #define USART1_UDRE_vect _VECTOR(33) #define SIG_UART1_DATA _VECTOR(33) #define SIG_USART1_DATA _VECTOR(33) /* USART1, Tx Complete */ #define USART1_TX_vect_num 34 #define USART1_TX_vect _VECTOR(34) #define SIG_UART1_TRANS _VECTOR(34) #define SIG_USART1_TRANS _VECTOR(34) /* 2-wire Serial Interface */ #define TWI_vect_num 35 #define TWI_vect _VECTOR(35) #define SIG_2WIRE_SERIAL _VECTOR(35) /* Store Program Memory Read */ #define SPM_READY_vect_num 36 #define SPM_READY_vect _VECTOR(36) #define SIG_SPM_READY _VECTOR(36) #define _VECTORS_SIZE 148 /* The Register Bit names are represented by their bit number (0-7). */ /* Register Bits [ASSR] */ /* Asynchronous Status Register */ #define EXCLK 4 #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* End Register Bits */ /* Register Bits [TWCR] */ /* 2-wire Control Register - TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 /* End Register Bits */ /* Register Bits [TWAR] */ /* 2-wire Address Register - TWAR */ #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 /* End Register Bits */ /* Register Bits [TWSR] */ /* 2-wire Status Register - TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 /* End Register Bits */ /* Register Bits [XMCRB] */ /* External Memory Control Register B - XMCRB */ #define XMBK 7 #define XMM2 2 #define XMM1 1 #define XMM0 0 /* End Register Bits */ /* Register Bits [XMCRA] */ /* External Memory Control Register A - XMCRA */ #define SRE 7 #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW11 3 #define SRW10 2 #define SRW01 1 #define SRW00 0 /* End Register Bits */ /* Register Bits [RAMPZ] */ /* RAM Page Z select register - RAMPZ */ #define RAMPZ0 0 /* End Register Bits */ /* Register Bits [EICRA] */ /* External Interrupt Control Register A - EICRA */ #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* End Register Bits */ /* Register Bits [EICRB] */ /* External Interrupt Control Register B - EICRB */ #define ISC71 7 #define ISC70 6 #define ISC61 5 #define ISC60 4 #define ISC51 3 #define ISC50 2 #define ISC41 1 #define ISC40 0 /* End Register Bits */ /* Register Bits [SPMCSR] */ /* Store Program Memory Control Register - SPMCSR, SPMCR */ #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* End Register Bits */ /* Register Bits [EIMSK] */ /* External Interrupt MaSK register - EIMSK */ #define INT7 7 #define INT6 6 #define INT5 5 #define INT4 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 /* End Register Bits */ /* Register Bits [EIFR] */ /* External Interrupt Flag Register - EIFR */ #define INTF7 7 #define INTF6 6 #define INTF5 5 #define INTF4 4 #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 /* End Register Bits */ /* Register Bits [TCCR2] */ /* Timer/Counter 2 Control Register - TCCR2 */ #define FOC2A 7 #define WGM20 6 #define COM2A1 5 #define COM2A0 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* End Register Bits */ /* Register Bits [TCCR1A] */ /* Timer/Counter 1 Control and Status Register A - TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define COM1C1 3 #define COM1C0 2 #define WGM11 1 #define WGM10 0 /* End Register Bits */ /* Register Bits [TCCR3A] */ /* Timer/Counter 3 Control and Status Register A - TCCR3A */ #define COM3A1 7 #define COM3A0 6 #define COM3B1 5 #define COM3B0 4 #define COM3C1 3 #define COM3C0 2 #define WGM31 1 #define WGM30 0 /* End Register Bits */ /* Register Bits [TCCR1B] */ /* Timer/Counter 1 Control and Status Register B - TCCR1B */ #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* End Register Bits */ /* Register Bits [TCCR3B] */ /* Timer/Counter 3 Control and Status Register B - TCCR3B */ #define ICNC3 7 #define ICES3 6 #define WGM33 4 #define WGM32 3 #define CS32 2 #define CS31 1 #define CS30 0 /* End Register Bits */ /* Register Bits [TCCR3C] */ /* Timer/Counter 3 Control Register C - TCCR3C */ #define FOC3A 7 #define FOC3B 6 #define FOC3C 5 /* End Register Bits */ /* Register Bits [TCCR1C] */ /* Timer/Counter 1 Control Register C - TCCR1C */ #define FOC1A 7 #define FOC1B 6 #define FOC1C 5 /* End Register Bits */ /* Register Bits [OCDR] */ /* On-chip Debug Register - OCDR */ #define IDRD 7 #define OCDR7 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 /* End Register Bits */ /* Register Bits [WDTCR] */ /* Watchdog Timer Control Register - WDTCR */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* End Register Bits */ /* Register Bits [SPSR] */ /* SPI Status Register - SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* End Register Bits */ /* Register Bits [SPCR] */ /* SPI Control Register - SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* End Register Bits */ /* Register Bits [UCSR1C] */ /* USART1 Register C - UCSR1C */ #define UMSEL1 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPOL1 0 /* End Register Bits */ /* Register Bits [UCSR0C] */ /* USART0 Register C - UCSR0C */ #define UMSEL0 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UCSZ00 1 #define UCPOL0 0 /* End Register Bits */ /* Register Bits [UCSR1A] */ /* USART1 Status Register A - UCSR1A */ #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 /* End Register Bits */ /* Register Bits [UCSR0A] */ /* USART0 Status Register A - UCSR0A */ #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 /* End Register Bits */ /* Register Bits [UCSR1B] */ /* USART1 Control Register B - UCSR1B */ #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 /* End Register Bits */ /* Register Bits [UCSR0B] */ /* USART0 Control Register B - UCSR0B */ #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 /* End Register Bits */ /* Register Bits [ACSR] */ /* Analog Comparator Control and Status Register - ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* End Register Bits */ /* Register Bits [ADCSRA] */ /* ADC Control and status register - ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* End Register Bits */ /* The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ /* Register Bits [ADCSRB] */ /* ADC Control and status register - ADCSRB */ #define ACME 6 #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 /* End Register Bits */ /* Register Bits [ADMUX] */ /* ADC Multiplexer select - ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* End Register Bits */ /* Register Bits [DIDR0] */ /* Digital Input Disable Register 0 */ #define ADC7D 7 #define ADC6D 6 #define ADC5D 5 #define ADC4D 4 #define ADC3D 3 #define ADC2D 2 #define ADC1D 1 #define ADC0D 0 /* End Register Bits */ /* Register Bits [DIDR1] */ /* Digital Input Disable Register 1 */ #define AIN1D 1 #define AIN0D 0 /* End Register Bits */ /* Register Bits [PORTA] */ /* Port A Data Register - PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* End Register Bits */ /* Register Bits [DDRA] */ /* Port A Data Direction Register - DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* End Register Bits */ /* Register Bits [PINA] */ /* Port A Input Pins - PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* End Register Bits */ /* Register Bits [PORTB] */ /* Port B Data Register - PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* End Register Bits */ /* Register Bits [DDRB] */ /* Port B Data Direction Register - DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* End Register Bits */ /* Register Bits [PINB] */ /* Port B Input Pins - PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* End Register Bits */ /* Register Bits [PORTC] */ /* Port C Data Register - PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* End Register Bits */ /* Register Bits [DDRC] */ /* Port C Data Direction Register - DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* End Register Bits */ /* Register Bits [PINC] */ /* Port C Input Pins - PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* End Register Bits */ /* Register Bits [PORTD] */ /* Port D Data Register - PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* End Register Bits */ /* Register Bits [DDRD] */ /* Port D Data Direction Register - DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* End Register Bits */ /* Register Bits [PIND] */ /* Port D Input Pins - PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* End Register Bits */ /* Register Bits [PORTE] */ /* Port E Data Register - PORTE */ #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 /* End Register Bits */ /* Register Bits [DDRE] */ /* Port E Data Direction Register - DDRE */ #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 /* End Register Bits */ /* Register Bits [PINE] */ /* Port E Input Pins - PINE */ #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 /* End Register Bits */ /* Register Bits [PORTF] */ /* Port F Data Register - PORTF */ #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 /* End Register Bits */ /* Register Bits [DDRF] */ /* Port F Data Direction Register - DDRF */ #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 /* End Register Bits */ /* Register Bits [PINF] */ /* Port F Input Pins - PINF */ #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 /* End Register Bits */ /* Register Bits [PORTG] */ /* Port G Data Register - PORTG */ #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 /* End Register Bits */ /* Register Bits [DDRG] */ /* Port G Data Direction Register - DDRG */ #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 /* End Register Bits */ /* Register Bits [PING] */ /* Port G Input Pins - PING */ #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 /* End Register Bits */ /* Register Bits [TIFR0] */ /* Timer/Counter 0 interrupt Flag Register */ #define OCF0A 1 #define TOV0 0 /* End Register Bits */ /* Register Bits [TIFR1] */ /* Timer/Counter 1 interrupt Flag Register */ #define ICF1 5 #define OCF1C 3 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 /* End Register Bits */ /* Register Bits [TIFR2] */ /* Timer/Counter 2 interrupt Flag Register */ #define OCF2A 1 #define TOV2 0 /* End Register Bits */ /* Register Bits [TIFR3] */ /* Timer/Counter 3 interrupt Flag Register */ #define ICF3 5 #define OCF3C 3 #define OCF3B 2 #define OCF3A 1 #define TOV3 0 /* End Register Bits */ /* Register Bits [GPIOR0] */ /* General Purpose I/O Register 0 */ #define GPIOR07 7 #define GPIOR06 6 #define GPIOR05 5 #define GPIOR04 4 #define GPIOR03 3 #define GPIOR02 2 #define GPIOR01 1 #define GPIOR00 0 /* End Register Bits */ /* Register Bits [GPIOR1] */ /* General Purpose I/O Register 1 */ #define GPIOR17 7 #define GPIOR16 6 #define GPIOR15 5 #define GPIOR14 4 #define GPIOR13 3 #define GPIOR12 2 #define GPIOR11 1 #define GPIOR10 0 /* End Register Bits */ /* Register Bits [GPIOR2] */ /* General Purpose I/O Register 2 */ #define GPIOR27 7 #define GPIOR26 6 #define GPIOR25 5 #define GPIOR24 4 #define GPIOR23 3 #define GPIOR22 2 #define GPIOR21 1 #define GPIOR20 0 /* End Register Bits */ /* Register Bits [EECR] */ /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* End Register Bits */ /* Register Bits [EEDR] */ /* EEPROM Data Register */ #define EEDR7 7 #define EEDR6 6 #define EEDR5 5 #define EEDR4 4 #define EEDR3 3 #define EEDR2 2 #define EEDR1 1 #define EEDR0 0 /* End Register Bits */ /* Register Bits [EEARL] */ /* EEPROM Address Register */ #define EEAR7 7 #define EEAR6 6 #define EEAR5 5 #define EEAR4 4 #define EEAR3 3 #define EEAR2 2 #define EEAR1 1 #define EEAR0 0 /* End Register Bits */ /* Register Bits [EEARH] */ /* EEPROM Address Register */ #define EEAR11 3 #define EEAR10 2 #define EEAR9 1 #define EEAR8 0 /* End Register Bits */ /* Register Bits [GTCCR] */ /* General Timer/Counter Control Register */ #define TSM 7 #define PSR2 1 #define PSR310 0 /* End Register Bits */ /* Register Bits [TCCR0A] */ /* Timer/Counter Control Register A */ /* ALSO COVERED IN GENERIC SECTION */ #define FOC0A 7 #define WGM00 6 #define COM0A1 5 #define COM0A0 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* End Register Bits */ /* Register Bits [OCR0A] */ /* Output Compare Register A */ #define OCR0A7 7 #define OCR0A6 6 #define OCR0A5 5 #define OCR0A4 4 #define OCR0A3 3 #define OCR0A2 2 #define OCR0A1 1 #define OCR0A0 0 /* End Register Bits */ /* Register Bits [SPIDR] */ /* SPI Data Register */ #define SPD7 7 #define SPD6 6 #define SPD5 5 #define SPD4 4 #define SPD3 3 #define SPD2 2 #define SPD1 1 #define SPD0 0 /* End Register Bits */ /* Register Bits [SMCR] */ /* Sleep Mode Control Register */ #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 /* End Register Bits */ /* Register Bits [MCUSR] */ /* MCU Status Register */ #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* End Register Bits */ /* Register Bits [MCUCR] */ /* MCU Control Register */ #define JTD 7 #define PUD 4 #define IVSEL 1 #define IVCE 0 /* End Register Bits */ /* Register Bits [CLKPR] */ /* Clock Prescale Register */ #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 /* End Register Bits */ /* Register Bits [OSCCAL] */ /* Oscillator Calibration Register */ #define CAL6 6 #define CAL5 5 #define CAL4 4 #define CAL3 3 #define CAL2 2 #define CAL1 1 #define CAL0 0 /* End Register Bits */ /* Register Bits [TIMSK0] */ /* Timer/Counter 0 interrupt mask Register */ #define OCIE0A 1 #define TOIE0 0 /* End Register Bits */ /* Register Bits [TIMSK1] */ /* Timer/Counter 1 interrupt mask Register */ #define ICIE1 5 #define OCIE1C 3 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 /* End Register Bits */ /* Register Bits [TIMSK2] */ /* Timer/Counter 2 interrupt mask Register */ #define OCIE2A 1 #define TOIE2 0 /* End Register Bits */ /* Register Bits [TIMSK3] */ /* Timer/Counter 3 interrupt mask Register */ #define ICIE3 5 #define OCIE3C 3 #define OCIE3B 2 #define OCIE3A 1 #define TOIE3 0 /* End Register Bits */ //Begin CAN specific parts /* Register Bits [CANGCON] */ /* CAN General Control Register */ #define ABRQ 7 #define OVRQ 6 #define TTC 5 #define SYNTTC 4 #define LISTEN 3 #define TEST 2 #define ENASTB 1 #define SWRES 0 /* End Register Bits */ /* Register Bits [CANGSTA] */ /* CAN General Status Register */ #define OVFG 6 #define OVRG 6 #define TXBSY 4 #define RXBSY 3 #define ENFG 2 #define BOFF 1 #define ERRP 0 /* End Register Bits */ /* Register Bits [CANGIT] */ /* CAN General Interrupt Register */ #define CANIT 7 #define BOFFIT 6 #define OVRTIM 5 #define BXOK 4 #define SERG 3 #define CERG 2 #define FERG 1 #define AERG 0 /* End Register Bits */ /* Register Bits [CANGIE] */ /* CAN General Interrupt Enable */ #define ENIT 7 #define ENBOFF 6 #define ENRX 5 #define ENTX 4 #define ENERR 3 #define ENBX 2 #define ENERG 1 #define ENOVRT 0 /* End Register Bits */ /* Register Bits [CANEN2] */ /* CAN Enable MOb Register */ #define ENMOB7 7 #define ENMOB6 6 #define ENMOB5 5 #define ENMOB4 4 #define ENMOB3 3 #define ENMOB2 2 #define ENMOB1 1 #define ENMOB0 0 /* End Register Bits */ /* Register Bits [CANEN1] */ /* CAN Enable MOb Register */ #define ENMOB14 6 #define ENMOB13 5 #define ENMOB12 4 #define ENMOB11 3 #define ENMOB10 2 #define ENMOB9 1 #define ENMOB8 0 /* End Register Bits */ /* Register Bits [CANIE2] */ /* CAN Interrupt Enable MOb Register */ #define IEMOB7 7 #define IEMOB6 6 #define IEMOB5 5 #define IEMOB4 4 #define IEMOB3 3 #define IEMOB2 2 #define IEMOB1 1 #define IEMOB0 0 /* End Register Bits */ /* Register Bits [CANIE1] */ /* CAN Interrupt Enable MOb Register */ #define IEMOB14 6 #define IEMOB13 5 #define IEMOB12 4 #define IEMOB11 3 #define IEMOB10 2 #define IEMOB9 1 #define IEMOB8 0 /* End Register Bits */ /* Register Bits [CANSIT2] */ /* CAN Status Interrupt MOb Register */ #define SIT7 7 #define SIT6 6 #define SIT5 5 #define SIT4 4 #define SIT3 3 #define SIT2 2 #define SIT1 1 #define SIT0 0 /* End Register Bits */ /* Register Bits [CANSIT1] */ /* CAN Status Interrupt MOb Register */ #define SIT14 6 #define SIT13 5 #define SIT12 4 #define SIT11 3 #define SIT10 2 #define SIT9 1 #define SIT8 0 /* End Register Bits */ /* Register Bits [CANBT1] */ /* Bit Timing Register 1 */ #define BRP5 6 #define BRP4 5 #define BRP3 4 #define BRP2 3 #define BRP1 2 #define BRP0 1 /* End Register Bits */ /* Register Bits [CANBT2] */ /* Bit Timing Register 2 */ #define SJW1 6 #define SJW0 5 #define PRS2 3 #define PRS1 2 #define PRS0 1 /* End Register Bits */ /* Register Bits [CANBT3] */ /* Bit Timing Register 3 */ #define PHS22 6 #define PHS21 5 #define PHS20 4 #define PHS12 3 #define PHS11 2 #define PHS10 1 #define SMP 0 /* End Register Bits */ /* Register Bits [CANTCON] */ /* CAN Timer Control Register */ #define TPRSC7 7 #define TPRSC6 6 #define TPRSC5 5 #define TPRSC4 4 #define TPRSC3 3 #define TPRSC2 2 #define TPRSC1 1 #define TPRSC0 0 /* End Register Bits */ /* Register Bits [CANTIML] */ /* CAN Timer Register Low */ #define CANTIM7 7 #define CANTIM6 6 #define CANTIM5 5 #define CANTIM4 4 #define CANTIM3 3 #define CANTIM2 2 #define CANTIM1 1 #define CANTIM0 0 /* End Register Bits */ /* Register Bits [CANTIMH] */ /* CAN Timer Register High */ #define CANTIM15 7 #define CANTIM14 6 #define CANTIM13 5 #define CANTIM12 4 #define CANTIM11 3 #define CANTIM10 2 #define CANTIM9 1 #define CANTIM8 0 /* End Register Bits */ /* Register Bits [CANTTCL] */ /* CAN TTC Timer Register Low */ #define TIMTTC7 7 #define TIMTTC6 6 #define TIMTTC5 5 #define TIMTTC4 4 #define TIMTTC3 3 #define TIMTTC2 2 #define TIMTTC1 1 #define TIMTTC0 0 /* End Register Bits */ /* Register Bits [CANTTCH] */ /* CAN TTC Timer Register High */ #define TIMTTC15 7 #define TIMTTC14 6 #define TIMTTC13 5 #define TIMTTC12 4 #define TIMTTC11 3 #define TIMTTC10 2 #define TIMTTC9 1 #define TIMTTC8 0 /* End Register Bits */ /* Register Bits [CANTEC] */ /* CAN Transmitt Error Counter */ #define TEC7 7 #define TEC6 6 #define TEC5 5 #define TEC4 4 #define TEC3 3 #define TEC2 2 #define TEC1 1 #define TEC0 0 /* End Register Bits */ /* Register Bits [CANREC] */ /* CAN Receive Error Counter */ #define REC7 7 #define REC6 6 #define REC5 5 #define REC4 4 #define REC3 3 #define REC2 2 #define REC1 1 #define REC0 0 /* End Register Bits */ /* Register Bits [CANHPMOB] */ /* Highest Priority MOb */ #define HPMOB3 7 #define HPMOB2 6 #define HPMOB1 5 #define HPMOB0 4 #define CGP3 3 #define CGP2 2 #define CGP1 1 #define CGP0 0 /* End Register Bits */ /* Register Bits [CANPAGE] */ /* CAN Page MOb Register */ #define MOBNB3 7 #define MOBNB2 6 #define MOBNB1 5 #define MOBNB0 4 #define AINC 3 #define INDX2 2 #define INDX1 1 #define INDX0 0 /* End Register Bits */ /* Register Bits [CANSTMOB] */ /* CAN MOb Status Register */ #define DLCW 7 #define TXOK 6 #define RXOK 5 #define BERR 4 #define SERR 3 #define CERR 2 #define FERR 1 #define AERR 0 /* End Register Bits */ /* Register Bits [CANCDMOB] */ /* CAN MOb Control and DLC Register */ #define CONMOB1 7 #define CONMOB0 6 #define RPLV 5 #define IDE 4 #define DLC3 3 #define DLC2 2 #define DLC1 1 #define DLC0 0 /* End Register Bits */ /* Register Bits [CANIDT4] */ /* CAN Identifier Tag Register 4 */ #define IDT4 7 #define IDT3 6 #define IDT2 5 #define IDT1 4 #define IDT0 3 #define RTRTAG 2 #define RB1TAG 1 #define RB0TAG 0 /* End Register Bits */ /* Register Bits [CANIDT3] */ /* CAN Identifier Tag Register 3 */ #define IDT12 7 #define IDT11 6 #define IDT10 5 #define IDT9 4 #define IDT8 3 #define IDT7 2 #define IDT6 1 #define IDT5 0 /* End Register Bits */ /* Register Bits [CANIDT2] */ /* CAN Identifier Tag Register 2 */ #define IDT20 7 #define IDT19 6 #define IDT18 5 #define IDT17 4 #define IDT16 3 #define IDT15 2 #define IDT14 1 #define IDT13 0 /* End Register Bits */ /* Register Bits [CANIDT1] */ /* CAN Identifier Tag Register 1 */ #define IDT28 7 #define IDT27 6 #define IDT26 5 #define IDT25 4 #define IDT24 3 #define IDT23 2 #define IDT22 1 #define IDT21 0 /* End Register Bits */ /* Register Bits [CANIDM4] */ /* CAN Identifier Mask Register 4 */ #define IDMSK4 7 #define IDMSK3 6 #define IDMSK2 5 #define IDMSK1 4 #define IDMSK0 3 #define RTRMSK 2 #define IDEMSK 0 /* End Register Bits */ /* Register Bits [CANIDM3] */ /* CAN Identifier Mask Register 3 */ #define IDMSK12 7 #define IDMSK11 6 #define IDMSK10 5 #define IDMSK9 4 #define IDMSK8 3 #define IDMSK7 2 #define IDMSK6 1 #define IDMSK5 0 /* End Register Bits */ /* Register Bits [CANIDM2] */ /* CAN Identifier Mask Register 2 */ #define IDMSK20 7 #define IDMSK19 6 #define IDMSK18 5 #define IDMSK17 4 #define IDMSK16 3 #define IDMSK15 2 #define IDMSK14 1 #define IDMSK13 0 /* End Register Bits */ /* Register Bits [CANIDM1] */ /* CAN Identifier Mask Register 1 */ #define IDMSK28 7 #define IDMSK27 6 #define IDMSK26 5 #define IDMSK25 4 #define IDMSK24 3 #define IDMSK23 2 #define IDMSK22 1 #define IDMSK21 0 /* End Register Bits */ /* Register Bits [CANSTML] */ /* CAN Timer Register of some sort, low*/ #define TIMSTM7 7 #define TIMSTM6 6 #define TIMSTM5 5 #define TIMSTM4 4 #define TIMSTM3 3 #define TIMSTM2 2 #define TIMSTM1 1 #define TIMSTM0 0 /* End Register Bits */ /* Register Bits [CANSTMH] */ /* CAN Timer Register of some sort, high */ #define TIMSTM15 7 #define TIMSTM14 6 #define TIMSTM13 5 #define TIMSTM12 4 #define TIMSTM11 3 #define TIMSTM10 2 #define TIMSTM9 1 #define TIMSTM8 0 /* End Register Bits */ /* Register Bits [CANMSG] */ /* CAN Message Register */ #define MSG7 7 #define MSG6 6 #define MSG5 5 #define MSG4 4 #define MSG3 3 #define MSG2 2 #define MSG1 1 #define MSG0 0 /* End Register Bits */ /* Begin Verbatim */ /* Timer/Counter Control Register (generic) */ #define FOC 7 #define WGM0 6 #define COM1 5 #define COM0 4 #define WGM1 3 #define CS2 2 #define CS1 1 #define CS0 0 /* Timer/Counter Control Register A (generic) */ #define COMA1 7 #define COMA0 6 #define COMB1 5 #define COMB0 4 #define COMC1 3 #define COMC0 2 #define WGMA1 1 #define WGMA0 0 /* Timer/Counter Control and Status Register B (generic) */ #define ICNC 7 #define ICES 6 #define WGMB3 4 #define WGMB2 3 #define CSB2 2 #define CSB1 1 #define CSB0 0 /* Timer/Counter Control Register C (generic) */ #define FOCA 7 #define FOCB 6 #define FOCC 5 /* Port Data Register (generic) */ #define PORT7 7 #define PORT6 6 #define PORT5 5 #define PORT4 4 #define PORT3 3 #define PORT2 2 #define PORT1 1 #define PORT0 0 /* Port Data Direction Register (generic) */ #define DD7 7 #define DD6 6 #define DD5 5 #define DD4 4 #define DD3 3 #define DD2 2 #define DD1 1 #define DD0 0 /* Port Input Pins (generic) */ #define PIN7 7 #define PIN6 6 #define PIN5 5 #define PIN4 4 #define PIN3 3 #define PIN2 2 #define PIN1 1 #define PIN0 0 /* USART Status Register A (generic) */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define UPE 2 #define U2X 1 #define MPCM 0 /* USART Control Register B (generic) */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ 2 #define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ #define RXB8 1 #define TXB8 0 /* USART Register C (generic) */ #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* End Verbatim */ #endif /* _AVR_IOCANXX_H_ */ avr-libc-1.8.0.orig/include/avr/iom640.h0000644000000000000000000000647611732702554014471 0ustar /* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom640.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/iom640.h - definitions for ATmega640 */ #ifndef _AVR_IOM640_H_ #define _AVR_IOM640_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x21FF #define XRAMEND 0xFFFF #define E2END 0xFFF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x08 #endif /* _AVR_IOM640_H_ */ avr-libc-1.8.0.orig/include/avr/version.h0000644000000000000000000000725011732702554015127 0ustar /* Copyright (c) 2005, Joerg Wunsch -*- c -*- All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: version.h.in 870 2005-09-12 20:18:12Z joerg_wunsch $ */ /** \defgroup avr_version : avr-libc version macros \code #include \endcode This header file defines macros that contain version numbers and strings describing the current version of avr-libc. The version number itself basically consists of three pieces that are separated by a dot: the major number, the minor number, and the revision number. For development versions (which use an odd minor number), the string representation additionally gets the date code (YYYYMMDD) appended. This file will also be included by \c . That way, portable tests can be implemented using \c that can be used in code that wants to remain backwards-compatible to library versions prior to the date when the library version API had been added, as referenced but undefined C preprocessor macros automatically evaluate to 0. */ #ifndef _AVR_VERSION_H_ #define _AVR_VERSION_H_ /** \ingroup avr_version String literal representation of the current library version. */ #define __AVR_LIBC_VERSION_STRING__ "1.8.0" /** \ingroup avr_version Numerical representation of the current library version. In the numerical representation, the major number is multiplied by 10000, the minor number by 100, and all three parts are then added. It is intented to provide a monotonically increasing numerical value that can easily be used in numerical checks. */ #define __AVR_LIBC_VERSION__ 10800UL /** \ingroup avr_version String literal representation of the release date. */ #define __AVR_LIBC_DATE_STRING__ "20111228" /** \ingroup avr_version Numerical representation of the release date. */ #define __AVR_LIBC_DATE_ 20111228UL /** \ingroup avr_version Library major version number. */ #define __AVR_LIBC_MAJOR__ 1 /** \ingroup avr_version Library minor version number. */ #define __AVR_LIBC_MINOR__ 8 /** \ingroup avr_version Library revision number. */ #define __AVR_LIBC_REVISION__ 0 #endif /* _AVR_VERSION_H_ */ avr-libc-1.8.0.orig/include/avr/cpufunc.h0000644000000000000000000000616311732702554015107 0ustar /* Copyright (c) 2010, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: cpufunc.h 2158 2010-06-10 15:48:28Z joerg_wunsch $ */ /* avr/cpufunc.h - Special CPU functions */ #ifndef _AVR_CPUFUNC_H_ #define _AVR_CPUFUNC_H_ 1 /** \file */ /** \defgroup avr_cpufunc : Special AVR CPU functions \code #include \endcode This header file contains macros that access special functions of the AVR CPU which do not fit into any of the other header files. */ #if defined(__DOXYGEN__) /** \ingroup avr_cpufunc \def _NOP Execute a no operation (NOP) CPU instruction. This should not be used to implement delays, better use the functions from or for this. For debugging purposes, a NOP can be useful to have an instruction that is guaranteed to be not optimized away by the compiler, so it can always become a breakpoint in the debugger. */ #define _NOP() #else /* real code */ #define _NOP() __asm__ __volatile__("nop") #endif /* __DOXYGEN__ */ #if defined(__DOXYGEN__) /** \ingroup avr_cpufunc \def _MemoryBarrier Implement a read/write memory barrier. A memory barrier instructs the compiler to not cache any memory data in registers beyond the barrier. This can sometimes be more effective than blocking certain optimizations by declaring some object with a \c volatile qualifier. See \ref optim_code_reorder for things to be taken into account with respect to compiler optimizations. */ #define _MemoryBarrier() #else /* real code */ #define _MemoryBarrier() __asm__ __volatile__(:::"memory") #endif /* __DOXYGEN__ */ #endif /* _AVR_CPUFUNC_H_ */ avr-libc-1.8.0.orig/include/avr/io4434.h0000644000000000000000000003273111732702554014372 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io4434.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io4434.h - definitions for AT90S4434 */ #ifndef _AVR_IO4434_H_ #define _AVR_IO4434_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io4434.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* ADC Data register */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and Status Register */ #define ADCSR _SFR_IO8(0x06) /* ADC MUX */ #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART Baud Rate Register */ #define UBRR _SFR_IO8(0x09) /* UART Control Register */ #define UCR _SFR_IO8(0x0A) /* UART Status Register */ #define USR _SFR_IO8(0x0B) /* UART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* Asynchronous mode Status Register */ #define ASSR _SFR_IO8(0x22) /* Timer/Counter2 Output Compare Register */ #define OCR2 _SFR_IO8(0x23) /* Timer/Counter 2 */ #define TCNT2 _SFR_IO8(0x24) /* Timer/Counter 2 Control Register */ #define TCCR2 _SFR_IO8(0x25) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 3 #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 4 #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 5 #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 6 #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 7 #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 8 #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 9 #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 10 #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) /* UART, RX Complete */ #define UART_RX_vect_num 11 #define UART_RX_vect _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) /* UART Data Register Empty */ #define UART_UDRE_vect_num 12 #define UART_UDRE_vect _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) /* UART, TX Complete */ #define UART_TX_vect_num 13 #define UART_TX_vect _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) /* ADC Conversion Complete */ #define ADC_vect_num 14 #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) /* EEPROM Ready */ #define EE_RDY_vect_num 15 #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) /* Analog Comparator */ #define ANA_COMP_vect_num 16 #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) #define _VECTORS_SIZE 34 /* The Register Bit names are represented by their bit number (0-7). */ /* MCU general Status Register */ #define EXTRF 1 #define PORF 0 /* General Interrupt MaSK register */ #define INT1 7 #define INT0 6 /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 /* Timer/Counter Interrupt MaSK register */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define TOIE0 0 /* Timer/Counter Interrupt Flag register */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define TOV0 0 /* MCU general Control Register */ #define SE 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Timer/Counter 2 Control Register */ #define PWM2 6 #define COM21 5 #define COM20 4 #define CTC2 3 #define CS22 2 #define CS21 1 #define CS20 0 /* Asynchronous mode Status Register */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Data Register, Port A */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Data Direction Register, Port A */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Input Pins, Port A */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port C */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Direction Register, Port C */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADC MUX */ #define MUX2 2 #define MUX1 1 #define MUX0 0 /* ADC Control and Status Register */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0x15F /*Last On-Chip SRAM location*/ #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 0 #define FLASHEND 0xFFF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ #define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ #define LFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x03 #endif /* _AVR_IO4434_H_ */ avr-libc-1.8.0.orig/include/avr/iom16.h0000644000000000000000000003526011732702554014377 0ustar /* Copyright (c) 2004 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16.h 2228 2011-03-05 15:33:19Z arcanum $ */ /* avr/iom16.h - definitions for ATmega16 */ #ifndef _AVR_IOM16_H_ #define _AVR_IOM16_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_IO8(0x02) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_IO8(0x03) /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define UBRRL _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define TXB8 0 #define RXB8 1 #define UCSZ2 2 #define TXEN 3 #define RXEN 4 #define UDRIE 5 #define TXCIE 6 #define RXCIE 7 #define UCSRA _SFR_IO8(0x0B) #define MPCM 0 #define U2X 1 #define PE 2 #define DOR 3 #define FE 4 #define UDRE 5 #define TXC 6 #define RXC 7 #define UDR _SFR_IO8(0x0C) #define SPCR _SFR_IO8(0x0D) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x0E) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x0F) #define PIND _SFR_IO8(0x10) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x11) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x12) #define PD0 0 #define PD1 1 #define PD2 2 #define PD3 3 #define PD4 4 #define PD5 5 #define PD6 6 #define PD7 7 #define PINC _SFR_IO8(0x13) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x14) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x15) #define PC0 0 #define PC1 1 #define PC2 2 #define PC3 3 #define PC4 4 #define PC5 5 #define PC6 6 #define PC7 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PB0 0 #define PB1 1 #define PB2 2 #define PB3 3 #define PB4 4 #define PB5 5 #define PB6 6 #define PB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PA0 0 #define PA1 1 #define PA2 2 #define PA3 3 #define PA4 4 #define PA5 5 #define PA6 6 #define PA7 7 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UCSRC _SFR_IO8(0x20) #define UCPOL 0 #define UCSZ0 1 #define UCSZ1 2 #define USBS 3 #define UPM0 4 #define UPM1 5 #define UMSEL 6 #define URSEL 7 #define UBRRH _SFR_IO8(0x20) #define URSEL 7 #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDTOE 4 #define ASSR _SFR_IO8(0x22) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM20 4 #define COM21 5 #define WGM20 6 #define FOC2 7 /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x2F) #define WGM10 0 #define WGM11 1 #define FOC1B 2 #define FOC1A 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 /* The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ #define SFIOR _SFR_IO8(0x30) #define PSR10 0 #define PSR2 1 #define PUD 2 #define ACME 3 #define ADTS0 5 #define ADTS1 6 #define ADTS2 7 #define OSCCAL _SFR_IO8(0x31) #define OCDR _SFR_IO8(0x31) #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM00 4 #define COM01 5 #define WGM00 6 #define FOC0 7 #define MCUCSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define ISC2 6 #define JTD 7 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define SM0 4 #define SM1 5 #define SE 6 #define SM2 7 #define TWCR _SFR_IO8(0x36) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define SPMCR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define TIFR _SFR_IO8(0x38) #define TOV0 0 #define OCF0 1 #define TOV1 2 #define OCF1B 3 #define OCF1A 4 #define ICF1 5 #define TOV2 6 #define OCF2 7 #define TIMSK _SFR_IO8(0x39) #define TOIE0 0 #define OCIE0 1 #define TOIE1 2 #define OCIE1B 3 #define OCIE1A 4 #define TICIE1 5 #define TOIE2 6 #define OCIE2 7 #define GIFR _SFR_IO8(0x3A) #define INTF2 5 #define INTF0 6 #define INTF1 7 #define GICR _SFR_IO8(0x3B) #define IVCE 0 #define IVSEL 1 #define INT2 5 #define INT0 6 #define INT1 7 #define OCR0 _SFR_IO8(0x3C) /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ /* Interrupt vectors */ /* Vector 0 is the reset vector. */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 3 #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 4 #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 5 #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 6 #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 7 #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 8 #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 9 #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) /* Serial Transfer Complete */ #define SPI_STC_vect_num 10 #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) /* USART, Rx Complete */ #define USART_RXC_vect_num 11 #define USART_RXC_vect _VECTOR(11) #define SIG_USART_RECV _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) /* USART Data Register Empty */ #define USART_UDRE_vect_num 12 #define USART_UDRE_vect _VECTOR(12) #define SIG_USART_DATA _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) /* USART, Tx Complete */ #define USART_TXC_vect_num 13 #define USART_TXC_vect _VECTOR(13) #define SIG_USART_TRANS _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) /* ADC Conversion Complete */ #define ADC_vect_num 14 #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) /* EEPROM Ready */ #define EE_RDY_vect_num 15 #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) /* Analog Comparator */ #define ANA_COMP_vect_num 16 #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) /* 2-wire Serial Interface */ #define TWI_vect_num 17 #define TWI_vect _VECTOR(17) #define SIG_2WIRE_SERIAL _VECTOR(17) /* External Interrupt Request 2 */ #define INT2_vect_num 18 #define INT2_vect _VECTOR(18) #define SIG_INTERRUPT2 _VECTOR(18) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 19 #define TIMER0_COMP_vect _VECTOR(19) #define SIG_OUTPUT_COMPARE0 _VECTOR(19) /* Store Program Memory Ready */ #define SPM_RDY_vect_num 20 #define SPM_RDY_vect _VECTOR(20) #define SIG_SPM_READY _VECTOR(20) #define _VECTORS_SIZE 84 /* Constants */ #define SPM_PAGESIZE 128 #define RAMSTART (0x60) #define RAMEND 0x45F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x03 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_USART_RECV #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_USART_DATA #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_USART_TRANS #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_2WIRE_SERIAL #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM16_H_ */ avr-libc-1.8.0.orig/include/avr/iom88p.h0000644000000000000000000004444711732702554014577 0ustar /* Copyright (c) 2007 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom88p.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iom88p.h - definitions for ATmega88P. */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom88p.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOM88P_H_ #define _AVR_IOM88P_H_ 1 /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEPROM_REG_LOCATIONS 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 #define BODS 6 #define SPMCSR _SFR_IO8(0x37) #define SELFPRGEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 0 #define TWAM1 1 #define TWAM2 2 #define TWAM3 3 #define TWAM4 4 #define TWAM5 5 #define TWAM6 6 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCPHA0 1 #define UCSZ01 2 #define UDORD0 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL01 7 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0_0 0 #define UBRR0_1 1 #define UBRR0_2 2 #define UBRR0_3 3 #define UBRR0_4 4 #define UBRR0_5 5 #define UBRR0_6 6 #define UBRR0_7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR0_8 0 #define UBRR0_9 1 #define UBRR0_10 2 #define UBRR0_11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR0_0 0 #define UDR0_1 1 #define UDR0_2 2 #define UDR0_3 3 #define UDR0_4 4 #define UDR0_5 5 #define UDR0_6 6 #define UDR0_7 7 /* Interrupt Vectors */ /* Interrupt Vector 0 is the reset vector. */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ #define PCINT2_vect_num 5 #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ #define WDT_vect_num 6 #define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 7 #define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 8 #define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ #define TIMER2_OVF_vect_num 9 #define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 10 #define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 11 #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 12 #define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ #define TIMER0_OVF_vect_num 16 #define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ #define SPI_STC_vect_num 17 #define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ #define USART_RX_vect_num 18 #define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ #define USART_UDRE_vect_num 19 #define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ #define USART_TX_vect_num 20 #define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ #define ADC_vect_num 21 #define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ #define EE_READY_vect_num 22 #define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ #define TWI_vect_num 24 #define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ #define SPM_READY_vect_num 25 #define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ #define _VECTORS_SIZE (26 * 2) /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x100) #define RAMEND 0x4FF /* Last On-Chip SRAM Location */ #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x0F #endif /* _AVR_IOM88P_H_ */ avr-libc-1.8.0.orig/include/avr/iotn13.h0000644000000000000000000002744511732702554014567 0ustar /* Copyright (c) 2004, Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn13.h 2236 2011-03-17 21:53:39Z arcanum $ */ /* avr/iotn13.h - definitions for ATtiny13 */ /* Verified 5/20/04 by Bruce Graham */ #ifndef _AVR_IOTN13_H_ #define _AVR_IOTN13_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn13.h" #else # error "Attempt to include more than one file." #endif /* I/O registers and bit names */ /* ADC Control and Status Register B */ #define ADCSRB _SFR_IO8(0x03) # define ACME 6 # define ADTS2 2 # define ADTS1 1 # define ADTS0 0 /* ADC Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16 (0x04) #endif #define ADCW _SFR_IO16 (0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and Status Register A */ #define ADCSRA _SFR_IO8(0x06) # define ADEN 7 # define ADSC 6 # define ADATE 5 # define ADIF 4 # define ADIE 3 # define ADPS2 2 # define ADPS1 1 # define ADPS0 0 /* ADC Multiplex Selection Register */ #define ADMUX _SFR_IO8(0x07) # define REFS0 6 # define ADLAR 5 # define MUX1 1 # define MUX0 0 /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) # define ACD 7 # define ACBG 6 # define ACO 5 # define ACI 4 # define ACIE 3 # define ACIS1 1 # define ACIS0 0 /* Digital Input Disable Register 0 */ #define DIDR0 _SFR_IO8(0x14) # define ADC0D 5 # define ADC2D 4 # define ADC3D 3 # define ADC1D 2 # define AIN1D 1 # define AIN0D 0 /* PIN Change Mask Register */ #define PCMSK _SFR_IO8(0x15) # define PCINT5 5 # define PCINT4 4 # define PCINT3 3 # define PCINT2 2 # define PCINT1 1 # define PCINT0 0 /* Port B Pin Utilization [2535D-AVR-04/04] - PORTB5 = PCINT5/RESET#/ADC0/dW - PORTB4 = PCINT4/ADC2 - PORTB3 = PCINT3/CLKI/ADC3 - PORTB2 = SCK/ADC1/T0/PCINT2 - PORTB1 = MISO/AIN1/OC0B/INT0/PCINT1 - PORTB0 = MOSI/AIN0/OC0A/PCINT0 */ /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) # define PINB5 5 # define PINB4 4 # define PINB3 3 # define PINB2 2 # define PINB1 1 # define PINB0 0 /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) # define DDB5 5 # define DDB4 4 # define DDB3 3 # define DDB2 2 # define DDB1 1 # define DDB0 0 /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) # define PB5 5 # define PB4 4 # define PB3 3 # define PB2 2 # define PB1 1 # define PB0 0 /* ATtiny EEPROM Control Register EECR */ #define EECR _SFR_IO8(0x1C) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* The EEPROM Address Register EEAR[6:0] */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) # define WDTIF 7 # define WDTIE 6 # define WDP3 5 # define WDCE 4 # define WDE 3 # define WDP2 2 # define WDP1 1 # define WDP0 0 /* Clock Prescale Register */ #define CLKPR _SFR_IO8(0x26) # define CLKPCE 7 # define CLKPS3 3 # define CLKPS2 2 # define CLKPS1 1 # define CLKPS0 0 /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x28) # define TSM 7 # define PSR10 0 /* Output Compare 0 Register B */ #define OCR0B _SFR_IO8(0x29) /* debugWIRE Data Register */ #define DWDR _SFR_IO8(0x2e) /* Timer/Counter 0 Control Register A */ #define TCCR0A _SFR_IO8(0x2f) # define COM0A1 7 # define COM0A0 6 # define COM0B1 5 # define COM0B0 4 # define WGM01 1 # define WGM00 0 /* Oscillator Calibration Register */ #define OSCCAL _SFR_IO8(0x31) /* Timer/Counter0 (8-bit) */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register B */ #define TCCR0B _SFR_IO8(0x33) # define FOC0A 7 # define FOC0B 6 # define WGM02 3 # define CS02 2 # define CS01 1 # define CS00 0 /* MCU General Status Register */ #define MCUSR _SFR_IO8(0x34) # define WDRF 3 # define BORF 2 # define EXTRF 1 # define PORF 0 /* MCU General Control Register */ #define MCUCR _SFR_IO8(0x35) # define PUD 6 # define SE 5 # define SM1 4 # define SM0 3 # define ISC01 1 # define ISC00 0 /* Output Compare 0 REgister A */ #define OCR0A _SFR_IO8(0x36) /* Store Program Memory Control and Status Register */ #define SPMCSR _SFR_IO8(0x37) # define CTPB 4 # define RFLB 3 # define PGWRT 2 # define PGERS 1 # define SPMEN 0 # define SELFPRGEN 0 /* Timer/Counter 0 Interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x38) # define OCF0B 3 # define OCF0A 2 # define TOV0 1 /* Timer/Counter 0 Interrupt MaSK Register */ #define TIMSK0 _SFR_IO8(0x39) # define OCIE0B 3 # define OCIE0A 2 # define TOIE0 1 /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3a) # define INTF0 6 # define PCIF 5 /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3b) # define INT0 6 # define PCIE 5 /* SPL and SREG are defined in */ /* From the datasheet: 1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset 2 0x0001 INT0 External Interrupt Request 0 3 0x0002 PCINT0 Pin Change Interrupt Request 0 4 0x0003 TIM0_OVF Timer/Counter Overflow 5 0x0004 EE_RDY EEPROM Ready 6 0x0005 ANA_COMP Analog Comparator 7 0x0006 TIM0_COMPA Timer/Counter Compare Match A 8 0x0007 TIM0_COMPB Timer/Counter Compare Match B 9 0x0008 WDT Watchdog Time-out 10 0x0009 ADC ADC Conversion Complete */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Timer/Counter0 Overflow */ #define TIM0_OVF_vect_num 3 #define TIM0_OVF_vect _VECTOR(3) #define SIG_OVERFLOW0 _VECTOR(3) /* EEPROM Ready */ #define EE_RDY_vect_num 4 #define EE_RDY_vect _VECTOR(4) #define SIG_EEPROM_READY _VECTOR(4) /* Analog Comparator */ #define ANA_COMP_vect_num 5 #define ANA_COMP_vect _VECTOR(5) #define SIG_COMPARATOR _VECTOR(5) /* Timer/Counter Compare Match A */ #define TIM0_COMPA_vect_num 6 #define TIM0_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE0A _VECTOR(6) /* Timer/Counter Compare Match B */ #define TIM0_COMPB_vect_num 7 #define TIM0_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE0B _VECTOR(7) /* Watchdog Time-out */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) #define SIG_WATCHDOG_TIMEOUT _VECTOR(8) /* ADC Conversion Complete */ #define ADC_vect_num 9 #define ADC_vect _VECTOR(9) #define SIG_ADC _VECTOR(9) #define _VECTORS_SIZE 20 #define SPM_PAGESIZE 32 #define RAMSTART (0x60) #define RAMEND 0x9F #define XRAMEND RAMEND #define E2END 0x3F #define E2PAGESIZE 4 #define FLASHEND 0x3FF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_SUT0 (unsigned char)~_BV(2) #define FUSE_SUT1 (unsigned char)~_BV(3) #define FUSE_CKDIV8 (unsigned char)~_BV(4) #define FUSE_WDTON (unsigned char)~_BV(5) #define FUSE_EESAVE (unsigned char)~_BV(6) #define FUSE_SPIEN (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT0 & FUSE_CKDIV8 & FUSE_SPIEN) /* High Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_DWEN (unsigned char)~_BV(3) #define FUSE_SPMEN (unsigned char)~_BV(4) #define HFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x07 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_OUTPUT_COMPARE0A #pragma GCC poison SIG_OUTPUT_COMPARE0B #pragma GCC poison SIG_WATCHDOG_TIMEOUT #pragma GCC poison SIG_ADC #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOTN13_H_*/ avr-libc-1.8.0.orig/include/avr/io8535.h0000644000000000000000000003302711732702554014377 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io8535.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io8535.h - definitions for AT90S8535 */ #ifndef _AVR_IO8535_H_ #define _AVR_IO8535_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io8535.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* ADC Data register */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and Status Register */ #define ADCSR _SFR_IO8(0x06) /* ADC MUX */ #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART Baud Rate Register */ #define UBRR _SFR_IO8(0x09) /* UART Control Register */ #define UCR _SFR_IO8(0x0A) /* UART Status Register */ #define USR _SFR_IO8(0x0B) /* UART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* Asynchronous mode Status Register */ #define ASSR _SFR_IO8(0x22) /* Timer/Counter2 Output Compare Register */ #define OCR2 _SFR_IO8(0x23) /* Timer/Counter 2 */ #define TCNT2 _SFR_IO8(0x24) /* Timer/Counter 2 Control Register */ #define TCCR2 _SFR_IO8(0x25) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 3 #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 4 #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 5 #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 6 #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 7 #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 8 #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 9 #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 10 #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) /* UART, RX Complete */ #define UART_RX_vect_num 11 #define UART_RX_vect _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) /* UART Data Register Empty */ #define UART_UDRE_vect_num 12 #define UART_UDRE_vect _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) /* UART, TX Complete */ #define UART_TX_vect_num 13 #define UART_TX_vect _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) /* ADC Conversion Complete */ #define ADC_vect_num 14 #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) /* EEPROM Ready */ #define EE_RDY_vect_num 15 #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) /* Analog Comparator */ #define ANA_COMP_vect_num 16 #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) #define _VECTORS_SIZE 34 /* The Register Bit names are represented by their bit number (0-7). */ /* MCU general Status Register */ #define EXTRF 1 #define PORF 0 /* General Interrupt MaSK register */ #define INT1 7 #define INT0 6 /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 /* Timer/Counter Interrupt MaSK register */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define TOIE0 0 /* Timer/Counter Interrupt Flag register */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define TOV0 0 /* MCU general Control Register */ #define SE 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Timer/Counter 2 Control Register */ #define PWM2 6 #define COM21 5 #define COM20 4 #define CTC2 3 #define CS22 2 #define CS21 1 #define CS20 0 /* Asynchronous mode Status Register */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Data Register, Port A */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Data Direction Register, Port A */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Input Pins, Port A */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port C */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Direction Register, Port C */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADC MUX */ #define MUX2 2 #define MUX1 1 #define MUX0 0 /* ADC Control and Status Register */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0x25F /*Last On-Chip SRAM location*/ #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 0 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ #define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ #define LFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x03 #endif /* _AVR_IO8535_H_ */ avr-libc-1.8.0.orig/include/avr/iom1281.h0000644000000000000000000000654011732702554014543 0ustar /* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom1281.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iom1281.h - definitions for ATmega1281 */ #ifndef _AVR_IOM1281_H_ #define _AVR_IOM1281_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMSTART (0x200) #define RAMEND 0x21FF #define XRAMEND 0xFFFF #define E2END 0xFFF #define E2PAGESIZE 8 #define FLASHEND 0x1FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x04 #endif /* _AVR_IOM1281_H_ */ avr-libc-1.8.0.orig/include/avr/iom649.h0000644000000000000000000005225011732702554014471 0ustar /* Copyright (c) 2004 Eric B. Weddington Copyright (c) 2005,2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/iom649.h - definitions for ATmega649 */ #ifndef _AVR_IOM649_H_ #define _AVR_IOM649_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom649.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRLCD 4 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 /* Reserved [0x6D] */ #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0XC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7..0xE3] */ #define LCDCRA _SFR_MEM8(0XE4) #define LCDBL 0 #define LCDIE 3 #define LCDIF 4 #define LCDAB 6 #define LCDEN 7 #define LCDCRB _SFR_MEM8(0XE5) #define LCDPM0 0 #define LCDPM1 1 #define LCDPM2 2 #define LCDMUX0 4 #define LCDMUX1 5 #define LCD2B 6 #define LCDCS 7 #define LCDFRR _SFR_MEM8(0XE6) #define LCDCD0 0 #define LCDCD1 1 #define LCDCD2 2 #define LCDPS0 4 #define LCDPS1 5 #define LCDPS2 6 #define LCDCCR _SFR_MEM8(0XE7) #define LCDCC0 0 #define LCDCC1 1 #define LCDCC2 2 #define LCDCC3 3 #define LCDDC0 5 #define LCDDC1 6 #define LCDDC2 7 /* Reserved [0xE8..0xEB] */ #define LCDDR00 _SFR_MEM8(0XEC) #define SEG000 0 #define SEG001 1 #define SEG002 2 #define SEG003 3 #define SEG004 4 #define SEG005 5 #define SEG006 6 #define SEG007 7 #define LCDDR01 _SFR_MEM8(0XED) #define SEG008 0 #define SEG009 1 #define SEG010 2 #define SEG011 3 #define SEG012 4 #define SEG013 5 #define SEG014 6 #define SEG015 7 #define LCDDR02 _SFR_MEM8(0XEE) #define SEG016 0 #define SEG017 1 #define SEG018 2 #define SEG019 3 #define SEG020 4 #define SEG021 5 #define SEG022 6 #define SEG023 7 #define LCDDR03 _SFR_MEM8(0XEF) #define SEG024 0 /* Reserved [0xF0] */ #define LCDDR05 _SFR_MEM8(0XF1) #define SEG100 0 #define SEG101 1 #define SEG102 2 #define SEG103 3 #define SEG104 4 #define SEG105 5 #define SEG106 6 #define SEG107 7 #define LCDDR06 _SFR_MEM8(0XF2) #define SEG108 0 #define SEG109 1 #define SEG110 2 #define SEG111 3 #define SEG112 4 #define SEG113 5 #define SEG114 6 #define SEG115 7 #define LCDDR07 _SFR_MEM8(0XF3) #define SEG116 0 #define SEG117 1 #define SEG118 2 #define SEG119 3 #define SEG120 4 #define SEG121 5 #define SEG122 6 #define SEG123 7 #define LCDDR08 _SFR_MEM8(0XF4) #define SEG124 0 /* Reserved [0xF5] */ #define LCDDR10 _SFR_MEM8(0XF6) #define SEG200 0 #define SEG201 1 #define SEG202 2 #define SEG203 3 #define SEG204 4 #define SEG205 5 #define SEG206 6 #define SEG207 7 #define LCDDR11 _SFR_MEM8(0XF7) #define SEG208 0 #define SEG209 1 #define SEG210 2 #define SEG211 3 #define SEG212 4 #define SEG213 5 #define SEG214 6 #define SEG215 7 #define LCDDR12 _SFR_MEM8(0XF8) #define SEG216 0 #define SEG217 1 #define SEG218 2 #define SEG219 3 #define SEG220 4 #define SEG221 5 #define SEG222 6 #define SEG223 7 #define LCDDR13 _SFR_MEM8(0XF9) #define SEG224 0 /* Reserved [0xFA] */ #define LCDDR15 _SFR_MEM8(0XFB) #define SEG300 0 #define SEG301 1 #define SEG302 2 #define SEG303 3 #define SEG304 4 #define SEG305 5 #define SEG306 6 #define SEG307 7 #define LCDDR16 _SFR_MEM8(0XFC) #define SEG308 0 #define SEG309 1 #define SEG310 2 #define SEG311 3 #define SEG312 4 #define SEG313 5 #define SEG314 6 #define SEG315 7 #define LCDDR17 _SFR_MEM8(0XFD) #define SEG316 0 #define SEG217 1 #define SEG318 2 #define SEG319 3 #define SEG320 4 #define SEG321 5 #define SEG322 6 #define SEG323 7 #define LCDDR18 _SFR_MEM8(0XFE) #define SEG324 0 /* Reserved [0xFF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART0, Rx Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* LCD Start of Frame */ #define LCD_vect_num 22 #define LCD_vect _VECTOR(22) #define SIG_LCD _VECTOR(22) #define _VECTORS_SIZE 92 /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x10FF #define XRAMEND RAMEND #define E2END 0x7FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x03 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #pragma GCC poison SIG_LCD #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM649_H_ */ avr-libc-1.8.0.orig/include/avr/iomxx4.h0000644000000000000000000004520611732702554014675 0ustar /* Copyright (c) 2005, 2006, 2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/iomXX4.h - definitions for ATmega164P/324P/644P and ATmega644 */ /* $Id: iomxx4.h 2235 2011-03-17 04:13:14Z arcanum $ */ #ifndef _AVR_IOMXX4_H_ #define _AVR_IOMXX4_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom164.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0X00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0X01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0X02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0X03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Reserved [0x0C..0x14] */ #define TIFR0 _SFR_IO8(0x15) #define OCF0B 2 #define OCF0A 1 #define TOV0 0 #define TIFR1 _SFR_IO8(0x16) #define ICF1 5 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 #define TIFR2 _SFR_IO8(0x17) #define OCF2B 2 #define OCF2A 1 #define TOV2 0 /* Reserved [0x18..0x1A] */ #define PCIFR _SFR_IO8(0x1B) #define PCIF3 3 #define PCIF2 2 #define PCIF1 1 #define PCIF0 0 #define EIFR _SFR_IO8(0x1C) #define INTF2 2 #define INTF1 1 #define INTF0 0 #define EIMSK _SFR_IO8(0x1D) #define INT2 2 #define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) /* EECR - EEPROM Control Register */ #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define TSM 7 #define PSRASY 1 #define PSRSYNC 0 #define TCCR0A _SFR_IO8(0x24) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 #define TCCR0B _SFR_IO8(0x25) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) #define OCR0B _SFR_IO8(0X28) /* Reserved [0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 #define SPSR _SFR_IO8(0x2D) #define SPIF 7 #define WCOL 6 #define SPI2X 0 #define SPDR _SFR_IO8(0x2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 #define MONDR _SFR_IO8(0x31) #define OCDR _SFR_IO8(0x31) #define IDRD 7 #define OCDR7 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 #define MCUSR _SFR_IO8(0x34) #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 #define MCUCR _SFR_IO8(0X35) #define JTD 7 #if !defined(__AVR_ATmega644__) #define BODS 6 #define BODSE 5 #endif #define PUD 4 #define IVSEL 1 #define IVCE 0 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMIE 7 #define RWWSB 6 #define SIGRD 5 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCSR _SFR_MEM8(0x60) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 #define CLKPR _SFR_MEM8(0x61) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) /* Datasheets: ATmega164P/324P/644P 8011D–AVR–02/07 and ATmega644 2593L–AVR–02/07. */ #define PRR0 _SFR_MEM8(0x64) /* AVR Studio 4.13, build 524. */ #define PRTWI 7 #define PRTIM2 6 #define PRTIM0 5 #if !defined(__AVR_ATmega644__) # define PRUSART1 4 #endif #define PRTIM1 3 #define PRSPI 2 #define PRUSART0 1 #define PRADC 0 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67] */ #define PCICR _SFR_MEM8(0x68) #define PCIE3 3 #define PCIE2 2 #define PCIE1 1 #define PCIE0 0 #define EICRA _SFR_MEM8(0x69) #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Reserved [0x6A] */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT15 7 #define PCINT14 6 #define PCINT13 5 #define PCINT12 4 #define PCINT11 3 #define PCINT10 2 #define PCINT9 1 #define PCINT8 0 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT23 7 #define PCINT22 6 #define PCINT21 5 #define PCINT20 4 #define PCINT19 3 #define PCINT18 2 #define PCINT17 1 #define PCINT16 0 #define TIMSK0 _SFR_MEM8(0x6E) #define OCIE0B 2 #define OCIE0A 1 #define TOIE0 0 #define TIMSK1 _SFR_MEM8(0x6F) #define ICIE1 5 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 #define TIMSK2 _SFR_MEM8(0x70) #define OCIE2B 2 #define OCIE2A 1 #define TOIE2 0 /* Reserved [0x71..0x72] */ #define PCMSK3 _SFR_MEM8(0x73) #define PCINT31 7 #define PCINT30 6 #define PCINT29 5 #define PCINT28 4 #define PCINT27 3 #define PCINT26 2 #define PCINT25 1 #define PCINT24 0 /* Reserved [0x74..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 #define ADCSRB _SFR_MEM8(0x7B) #define ACME 6 #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 #define ADMUX _SFR_MEM8(0x7C) #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC7D 7 #define ADC6D 6 #define ADC5D 5 #define ADC4D 4 #define ADC3D 3 #define ADC2D 2 #define ADC1D 1 #define ADC0D 0 #define DIDR1 _SFR_MEM8(0x7F) #define AIN1D 1 #define AIN0D 0 #define TCCR1A _SFR_MEM8(0x80) #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define WGM11 1 #define WGM10 0 #define TCCR1B _SFR_MEM8(0x81) #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 #define TCCR1C _SFR_MEM8(0x82) #define FOC1A 7 #define FOC1B 6 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define COM2A1 7 #define COM2A0 6 #define COM2B1 5 #define COM2B0 4 #define WGM21 1 #define WGM20 0 #define TCCR2B _SFR_MEM8(0xB1) #define FOC2A 7 #define FOC2B 6 #define WGM22 3 #define CS22 2 #define CS21 1 #define CS20 0 #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) #define OCR2B _SFR_MEM8(0xB4) /* Reserved [0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define EXCLK 6 #define AS2 5 #define TCN2UB 4 #define OCR2AUB 3 #define OCR2BUB 2 #define TCR2AUB 1 #define TCR2BUB 0 /* Reserved [0xB7] */ #define TWBR _SFR_MEM8(0xB8) #define TWSR _SFR_MEM8(0xB9) #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 #define TWAR _SFR_MEM8(0xBA) #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 #define TWDR _SFR_MEM8(0xBB) #define TWCR _SFR_MEM8(0xBC) #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 #define TWAMR _SFR_MEM8(0xBD) #define TWAM6 7 #define TWAM5 6 #define TWAM4 5 #define TWAM3 4 #define TWAM2 3 #define TWAM1 2 #define TWAM0 1 /* Reserved [0xBE..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 #define UCSR0B _SFR_MEM8(0XC1) #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 #define UCSR0C _SFR_MEM8(0xC2) #define UMSEL01 7 #define UMSEL00 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UCSZ00 1 #define UCPHA0 1 #define UCPOL0 0 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) #if !defined(__AVR_ATmega644__) /* * Only ATmega164P/324P/644P have a second USART. */ /* Reserved [0xC7] */ #define UCSR1A _SFR_MEM8(0xC8) #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 #define UCSR1B _SFR_MEM8(0XC9) #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 #define UCSR1C _SFR_MEM8(0xCA) #define UMSEL11 7 #define UMSEL10 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPHA1 1 #define UCPOL1 0 /* Reserved [0xCB] */ /* Combine UBRR1L and UBRR1H */ #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1H _SFR_MEM8(0xCD) #define UDR1 _SFR_MEM8(0XCE) #endif /* !defined(__AVR_ATmega644) */ /* Reserved [0xCF..0xFF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 4 #define PCINT0_vect _VECTOR(4) #define SIG_PIN_CHANGE0 _VECTOR(4) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 5 #define PCINT1_vect _VECTOR(5) #define SIG_PIN_CHANGE1 _VECTOR(5) /* Pin Change Interrupt Request 2 */ #define PCINT2_vect_num 6 #define PCINT2_vect _VECTOR(6) #define SIG_PIN_CHANGE2 _VECTOR(6) /* Pin Change Interrupt Request 3 */ #define PCINT3_vect_num 7 #define PCINT3_vect _VECTOR(7) #define SIG_PIN_CHANGE3 _VECTOR(7) /* Watchdog Time-out Interrupt */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) #define SIG_WATCHDOG_TIMEOUT _VECTOR(8) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPA_vect_num 9 #define TIMER2_COMPA_vect _VECTOR(9) #define SIG_OUTPUT_COMPARE2A _VECTOR(9) /* Timer/Counter2 Compare Match B */ #define TIMER2_COMPB_vect_num 10 #define TIMER2_COMPB_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE2B _VECTOR(10) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 11 #define TIMER2_OVF_vect _VECTOR(11) #define SIG_OVERFLOW2 _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 12 #define TIMER1_CAPT_vect _VECTOR(12) #define SIG_INPUT_CAPTURE1 _VECTOR(12) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1A _VECTOR(13) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE1B _VECTOR(14) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) #define SIG_OVERFLOW1 _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPA_vect_num 16 #define TIMER0_COMPA_vect _VECTOR(16) #define SIG_OUTPUT_COMPARE0A _VECTOR(16) /* Timer/Counter0 Compare Match B */ #define TIMER0_COMPB_vect_num 17 #define TIMER0_COMPB_vect _VECTOR(17) #define SIG_OUTPUT_COMPARE0B _VECTOR(17) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 18 #define TIMER0_OVF_vect _VECTOR(18) #define SIG_OVERFLOW0 _VECTOR(18) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 19 #define SPI_STC_vect _VECTOR(19) #define SIG_SPI _VECTOR(19) /* USART0, Rx Complete */ #define USART0_RX_vect_num 20 #define USART0_RX_vect _VECTOR(20) #define SIG_USART_RECV _VECTOR(20) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 21 #define USART0_UDRE_vect _VECTOR(21) #define SIG_USART_DATA _VECTOR(21) /* USART0, Tx Complete */ #define USART0_TX_vect_num 22 #define USART0_TX_vect _VECTOR(22) #define SIG_USART_TRANS _VECTOR(22) /* Analog Comparator */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) #define SIG_COMPARATOR _VECTOR(23) /* ADC Conversion Complete */ #define ADC_vect_num 24 #define ADC_vect _VECTOR(24) #define SIG_ADC _VECTOR(24) /* EEPROM Ready */ #define EE_READY_vect_num 25 #define EE_READY_vect _VECTOR(25) #define SIG_EEPROM_READY _VECTOR(25) /* 2-wire Serial Interface */ #define TWI_vect_num 26 #define TWI_vect _VECTOR(26) #define SIG_2WIRE_SERIAL _VECTOR(26) /* Store Program Memory Read */ #define SPM_READY_vect_num 27 #define SPM_READY_vect _VECTOR(27) #define SIG_SPM_READY _VECTOR(27) #if defined(__AVR_ATmega644__) # define _VECTORS_SIZE 112 #else /* !defined(__AVR_ATmega644__) */ /* USART1, Rx Complete */ /* USART1 RX complete */ #define USART1_RX_vect_num 28 #define USART1_RX_vect _VECTOR(28) #define SIG_USART1_RECV _VECTOR(28) /* USART1 Data register Empty */ /* USART1 Data Register Empty */ #define USART1_UDRE_vect_num 29 #define USART1_UDRE_vect _VECTOR(29) #define SIG_USART1_DATA _VECTOR(29) /* USART1, Tx Complete */ /* USART1 TX complete */ #define USART1_TX_vect_num 30 #define USART1_TX_vect _VECTOR(30) #define SIG_USART1_TRANS _VECTOR(30) # define _VECTORS_SIZE 124 #endif /* defined(__AVR_ATmega644__) */ /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_PIN_CHANGE2 #pragma GCC poison SIG_PIN_CHANGE3 #pragma GCC poison SIG_WATCHDOG_TIMEOUT #pragma GCC poison SIG_OUTPUT_COMPARE2A #pragma GCC poison SIG_OUTPUT_COMPARE2B #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0A #pragma GCC poison SIG_OUTPUT_COMPARE0B #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_USART_RECV #pragma GCC poison SIG_USART_DATA #pragma GCC poison SIG_USART_TRANS #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_2WIRE_SERIAL #pragma GCC poison SIG_SPM_READY #pragma GCC poison SIG_USART1_RECV #pragma GCC poison SIG_USART1_DATA #pragma GCC poison SIG_USART1_TRANS #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOMXX4_H_ */ avr-libc-1.8.0.orig/include/avr/iotn4313.h0000644000000000000000000004015411732702554014726 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn4313.h 2035 2009-11-02 02:44:17Z arcanum $ */ /* avr/iotn4313.h - definitions for ATtiny4313 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn4313.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny4313_H_ #define _AVR_ATtiny4313_H_ 1 /* Registers and associated bit numbers. */ #define DIDR _SFR_IO8(0x001) #define AIN0D 0 #define AIN1D 1 #define UBRRH _SFR_IO8(0x002) #define UBRR8 0 #define UBRR9 1 #define UBRR10 2 #define UBRR11 3 #define UCSRC _SFR_IO8(0x003) #define UCPOL 0 #define UCSZ0 1 #define UCSZ1 2 #define USBS 3 #define UPM0 4 #define UPM1 5 #define UMSEL 6 #define PCMSK1 _SFR_IO8(0x004) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCMSK2 _SFR_IO8(0x005) #define PCINT11 0 #define PCINT12 1 #define PCINT13 2 #define PCINT14 3 #define PCINT15 4 #define PCINT16 5 #define PCINT17 6 #define PRR _SFR_IO8(0x006) #define PRUSART 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define BODCR _SFR_IO8(0x007) #define BPDSE 0 #define BPDS 1 #define ACSR _SFR_IO8(0x008) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define UBRRL _SFR_IO8(0x009) #define UBRR0 0 #define UBRR1 1 #define UBRR2 2 #define UBRR3 3 #define UBRR4 4 #define UBRR5 5 #define UBRR6 6 #define UBRR7 7 #define UCSRB _SFR_IO8(0x00A) #define TXB8 0 #define RXB8 1 #define UCSZ2 2 #define TXEN 3 #define RXEN 4 #define UDRIE 5 #define TXCIE 6 #define RXCIE 7 #define UCSRA _SFR_IO8(0x00B) #define MPCM 0 #define U2X 1 #define UPE 2 #define DOR 3 #define FE 4 #define UDRE 5 #define TXC 6 #define RXC 7 #define UDR _SFR_IO8(0x00C) #define UDR0 0 #define UDR1 1 #define UDR2 2 #define UDR3 3 #define UDR4 4 #define UDR5 5 #define UDR6 6 #define UDR7 7 #define USICR _SFR_IO8(0x00D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x00E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x00F) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define PIND _SFR_IO8(0x010) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define DDRD _SFR_IO8(0x011) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define PORTD _SFR_IO8(0x012) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define GPIOR0 _SFR_IO8(0x013) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x014) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x015) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PINB _SFR_IO8(0x016) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x017) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x018) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINA _SFR_IO8(0x019) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define DDRA _SFR_IO8(0x01A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define PORTA _SFR_IO8(0x01B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define EECR _SFR_IO8(0x01C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x01D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO8(0x01E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define PCMSK _SFR_IO8(0x020) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define WDTCR _SFR_IO8(0x021) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define TCCR1C _SFR_IO8(0x022) #define FOC1B 6 #define FOC1A 7 #define GTCCR _SFR_IO8(0x023) #define PSR10 0 #define ICR1 _SFR_IO16(0x024) #define ICR1L _SFR_IO8(0x024) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_IO8(0x025) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define CLKPR _SFR_IO8(0x026) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define OCR1B _SFR_IO16(0x028) #define OCR1BL _SFR_IO8(0x028) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_IO8(0x029) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1A _SFR_IO16(0x02A) #define OCR1AL _SFR_IO8(0x02A) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_IO8(0x02B) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define TCNT1 _SFR_IO16(0x02C) #define TCNT1L _SFR_IO8(0x02C) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_IO8(0x02D) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define TCCR1B _SFR_IO8(0x02E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x02F) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR0A _SFR_IO8(0x030) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define OSCCAL _SFR_IO8(0x031) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define TCNT0 _SFR_IO8(0x032) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0B _SFR_IO8(0x033) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define MCUSR _SFR_IO8(0x034) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x035) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define SM0 4 #define SE 5 #define SM1 6 #define PUD 7 #define OCR0A _SFR_IO8(0x036) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define SPMCSR _SFR_IO8(0x037) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR _SFR_IO8(0x038) #define OCF0A 0 #define TOV0 1 #define OCF0B 2 #define ICF1 3 #define OCF1B 5 #define OCF1A 6 #define TOV1 7 #define TIMSK _SFR_IO8(0x039) #define OCIE0A 0 #define TOIE0 1 #define OCIE0B 2 #define ICIE1 3 #define OCIE1B 5 #define OCIE1A 6 #define TOIE1 7 #define EIFR _SFR_IO8(0x03A) #define PCIF 5 #define INTF0 6 #define INTF1 7 #define GIMSK _SFR_IO8(0x03B) #define PCIE 5 #define INT0 6 #define INT1 7 #define OCR0B _SFR_IO8(0x03C) #define OCR0_0 0 #define OCR0_1 1 #define OCR0_2 2 #define OCR0_3 3 #define OCR0_4 4 #define OCR0_5 5 #define OCR0_6 6 #define OCR0_7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define TIMER1_CAPT_vect_num 3 #define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 4 #define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */ #define TIMER1_OVF_vect_num 5 #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ #define TIMER0_OVF_vect_num 6 #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ #define USART_RX_vect_num 7 #define USART_RX_vect _VECTOR(7) /* USART, Rx Complete */ #define USART_UDRE_vect_num 8 #define USART_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ #define USART_TX_vect_num 9 #define USART_TX_vect _VECTOR(9) /* USART, Tx Complete */ #define ANA_COMP_vect_num 10 #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ #define PCINT_B_vect_num 11 #define PCINT_B_vect _VECTOR(11) /* Pin Change Interrupt Request B */ #define TIMER1_COMPB_vect_num 12 #define TIMER1_COMPB_vect _VECTOR(12) /* */ #define TIMER0_COMPA_vect_num 13 #define TIMER0_COMPA_vect _VECTOR(13) /* */ #define TIMER0_COMPB_vect_num 14 #define TIMER0_COMPB_vect _VECTOR(14) /* */ #define USI_START_vect_num 15 #define USI_START_vect _VECTOR(15) /* USI Start Condition */ #define USI_OVERFLOW_vect_num 16 #define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ #define WDT_OVERFLOW_vect_num 18 #define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ #define PCINT_D_vect_num 20 #define PCINT_D_vect _VECTOR(20) /* Pin Change Interrupt Request D */ #define EEPROM_Ready_vect_num 17 #define EEPROM_Ready_vect _VECTOR(17) /* */ #define PCINT_A_vect_num 19 #define PCINT_A_vect _VECTOR(19) /* Pin Change Interrupt Request A */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (21 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x60) #define RAMSIZE (256) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0xFF) #define E2PAGESIZE (4) #define FLASHEND (0xFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x0D /* Device Pin Definitions */ #define RXD_DDR DDRD #define RXD_PORT PORTD #define RXD_PIN PIND #define RXD_BIT 0 #define TXD_DDR DDRD #define TXD_PORT PORTD #define TXD_PIN PIND #define TXD_BIT 1 #define PA1_DDR DDRXTAL #define PA1_PORT PORTXTAL #define PA1_PIN PINXTAL #define PA1_BIT XTAL2 #define PA0_DDR DDRXTAL #define PA0_PORT PORTXTAL #define PA0_PIN PINXTAL #define PA0_BIT XTAL1 #define INT0_DDR DDRD #define INT0_PORT PORTD #define INT0_PIN PIND #define INT0_BIT 2 #define XCK_DDR DDRD #define XCK_PORT PORTD #define XCK_PIN PIND #define XCK_BIT 2 #define CKOUT_DDR DDRD #define CKOUT_PORT PORTD #define CKOUT_PIN PIND #define CKOUT_BIT 2 #define INT1_DDR DDRD #define INT1_PORT PORTD #define INT1_PIN PIND #define INT1_BIT 3 #define T0_DDR DDRD #define T0_PORT PORTD #define T0_PIN PIND #define T0_BIT 4 #define T1_DDR DDRD #define T1_PORT PORTD #define T1_PIN PIND #define T1_BIT 5 #define OC0B_DDR DDRD #define OC0B_PORT PORTD #define OC0B_PIN PIND #define OC0B_BIT 5 #define ICP_DDR DDRD #define ICP_PORT PORTD #define ICP_PIN PIND #define ICP_BIT 6 #define AIN0_DDR DDRB #define AIN0_PORT PORTB #define AIN0_PIN PINB #define AIN0_BIT 0 #define AIN1_DDR DDRB #define AIN1_PORT PORTB #define AIN1_PIN PINB #define AIN1_BIT 1 #define OC0A_DDR DDRB #define OC0A_PORT PORTB #define OC0A_PIN PINB #define OC0A_BIT 2 #define OC1A_DDR DDRB #define OC1A_PORT PORTB #define OC1A_PIN PINB #define OC1A_BIT 3 #define OC1B_DDR DDRB #define OC1B_PORT PORTB #define OC1B_PIN PINB #define OC1B_BIT 4 #define MOSI_DDR DDRB #define MOSI_PORT PORTB #define MOSI_PIN PINB #define MOSI_BIT 5 #define DI_DDR DDRB #define DI_PORT PORTB #define DI_PIN PINB #define DI_BIT 5 #define MISO_DDR DDRB #define MISO_PORT PORTB #define MISO_PIN PINB #define MISO_BIT 6 #define DO_DDR DDRB #define DO_PORT PORTB #define DO_PIN PINB #define DO_BIT 6 #define SCK_DDR DDRB #define SCK_PORT PORTB #define SCK_PIN PINB #define SCK_BIT 7 #define SCL_DDR DDRB #define SCL_PORT PORTB #define SCL_PIN PINB #define SCL_BIT 7 #endif /* _AVR_ATtiny4313_H_ */ avr-libc-1.8.0.orig/include/avr/iom64m1.h0000644000000000000000000007404011732702554014637 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom64m1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ /* avr/iom64m1.h - definitions for ATmega64M1 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom64m1.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega64M1_H_ #define _AVR_ATmega64M1_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define GPIOR1 _SFR_IO8(0x19) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x1A) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSRSYNC 0 #define ICPSEL1 6 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLF 2 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define AC0O 0 #define AC1O 1 #define AC2O 2 #define AC3O 3 #define AC0IF 4 #define AC1IF 5 #define AC2IF 6 #define AC3IF 7 #define DWDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPIPS 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRLIN 1 #define PRSPI 2 #define PRTIM0 3 #define PRTIM1 4 #define PRPSC 5 #define PRCAN 6 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6A) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6B) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6C) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define PCMSK3 _SFR_MEM8(0x6D) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define AMP0CSR _SFR_MEM8(0x75) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0TS2 2 #define AMPCMP0 3 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 #define AMP1CSR _SFR_MEM8(0x76) #define AMP1TS0 0 #define AMP1TS1 1 #define AMP1TS2 2 #define AMPCMP1 3 #define AMP1G0 4 #define AMP1G1 5 #define AMP1IS 6 #define AMP1EN 7 #define AMP2CSR _SFR_MEM8(0x77) #define AMP2TS0 0 #define AMP2TS1 1 #define AMP2TS2 2 #define AMPCMP2 3 #define AMP2G0 4 #define AMP2G1 5 #define AMP2IS 6 #define AMP2EN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define AREFEN 5 #define ISRCEN 6 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define AMP0ND 3 #define AMP0PD 4 #define ACMP0D 5 #define AMP2PD 6 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define DACON _SFR_MEM8(0x90) #define DAEN 0 #define DAOE 1 #define DALA 2 #define DATS0 4 #define DATS1 5 #define DATS2 6 #define DAATE 7 #define DAC _SFR_MEM16(0x91) #define DACL _SFR_MEM8(0x91) #define DACL0 0 #define DACL1 1 #define DACL2 2 #define DACL3 3 #define DACL4 4 #define DACL5 5 #define DACL6 6 #define DACL7 7 #define DACH _SFR_MEM8(0x92) #define DACH0 0 #define DACH1 1 #define DACH2 2 #define DACH3 3 #define DACH4 4 #define DACH5 5 #define DACH6 6 #define DACH7 7 #define AC0CON _SFR_MEM8(0x94) #define AC0M0 0 #define AC0M1 1 #define AC0M2 2 #define ACCKSEL 3 #define AC0IS0 4 #define AC0IS1 5 #define AC0IE 6 #define AC0EN 7 #define AC1CON _SFR_MEM8(0x95) #define AC1M0 0 #define AC1M1 1 #define AC1M2 2 #define AC1ICE 3 #define AC1IS0 4 #define AC1IS1 5 #define AC1IE 6 #define AC1EN 7 #define AC2CON _SFR_MEM8(0x96) #define AC2M0 0 #define AC2M1 1 #define AC2M2 2 #define AC2IS0 4 #define AC2IS1 5 #define AC2IE 6 #define AC2EN 7 #define AC3CON _SFR_MEM8(0x97) #define AC3M0 0 #define AC3M1 1 #define AC3M2 2 #define AC3IS0 4 #define AC3IS1 5 #define AC3IE 6 #define AC3EN 7 #define POCR0SA _SFR_MEM16(0xA0) #define POCR0SAL _SFR_MEM8(0xA0) #define POCR0SA_0 0 #define POCR0SA_1 1 #define POCR0SA_2 2 #define POCR0SA_3 3 #define POCR0SA_4 4 #define POCR0SA_5 5 #define POCR0SA_6 6 #define POCR0SA_7 7 #define POCR0SAH _SFR_MEM8(0xA1) #define POCR0SA_8 0 #define POCR0SA_9 1 #define POCR0SA_10 2 #define POCR0SA_11 3 #define POCR0RA _SFR_MEM16(0xA2) #define POCR0RAL _SFR_MEM8(0xA2) #define POCR0RA_0 0 #define POCR0RA_1 1 #define POCR0RA_2 2 #define POCR0RA_3 3 #define POCR0RA_4 4 #define POCR0RA_5 5 #define POCR0RA_6 6 #define POCR0RA_7 7 #define POCR0RAH _SFR_MEM8(0xA3) #define POCR0RA_8 0 #define POCR0RA_9 1 #define POCR0RA_10 2 #define POCR0RA_11 3 #define POCR0SB _SFR_MEM16(0xA4) #define POCR0SBL _SFR_MEM8(0xA4) #define POCR0SB_0 0 #define POCR0SB_1 1 #define POCR0SB_2 2 #define POCR0SB_3 3 #define POCR0SB_4 4 #define POCR0SB_5 5 #define POCR0SB_6 6 #define POCR0SB_7 7 #define POCR0SBH _SFR_MEM8(0xA5) #define POCR0SB_8 0 #define POCR0SB_9 1 #define POCR0SB_10 2 #define POCR0SB_11 3 #define POCR1SA _SFR_MEM16(0xA6) #define POCR1SAL _SFR_MEM8(0xA6) #define POCR1SA_0 0 #define POCR1SA_1 1 #define POCR1SA_2 2 #define POCR1SA_3 3 #define POCR1SA_4 4 #define POCR1SA_5 5 #define POCR1SA_6 6 #define POCR1SA_7 7 #define POCR1SAH _SFR_MEM8(0xA7) #define POCR1SA_8 0 #define POCR1SA_9 1 #define POCR1SA_10 2 #define POCR1SA_11 3 #define POCR1RA _SFR_MEM16(0xA8) #define POCR1RAL _SFR_MEM8(0xA8) #define POCR1RA_0 0 #define POCR1RA_1 1 #define POCR1RA_2 2 #define POCR1RA_3 3 #define POCR1RA_4 4 #define POCR1RA_5 5 #define POCR1RA_6 6 #define POCR1RA_7 7 #define POCR1RAH _SFR_MEM8(0xA9) #define POCR1RA_8 0 #define POCR1RA_9 1 #define POCR1RA_10 2 #define POCR1RA_11 3 #define POCR1SB _SFR_MEM16(0xAA) #define POCR1SBL _SFR_MEM8(0xAA) #define POCR1SB_0 0 #define POCR1SB_1 1 #define POCR1SB_2 2 #define POCR1SB_3 3 #define POCR1SB_4 4 #define POCR1SB_5 5 #define POCR1SB_6 6 #define POCR1SB_7 7 #define POCR1SBH _SFR_MEM8(0xAB) #define POCR1SB_8 0 #define POCR1SB_9 1 #define POCR1SB_10 2 #define POCR1SB_11 3 #define POCR2SA _SFR_MEM16(0xAC) #define POCR2SAL _SFR_MEM8(0xAC) #define POCR2SA_0 0 #define POCR2SA_1 1 #define POCR2SA_2 2 #define POCR2SA_3 3 #define POCR2SA_4 4 #define POCR2SA_5 5 #define POCR2SA_6 6 #define POCR2SA_7 7 #define POCR2SAH _SFR_MEM8(0xAD) #define POCR2SA_8 0 #define POCR2SA_9 1 #define POCR2SA_10 2 #define POCR2SA_11 3 #define POCR2RA _SFR_MEM16(0xAE) #define POCR2RAL _SFR_MEM8(0xAE) #define POCR2RA_0 0 #define POCR2RA_1 1 #define POCR2RA_2 2 #define POCR2RA_3 3 #define POCR2RA_4 4 #define POCR2RA_5 5 #define POCR2RA_6 6 #define POCR2RA_7 7 #define POCR2RAH _SFR_MEM8(0xAF) #define POCR2RA_8 0 #define POCR2RA_9 1 #define POCR2RA_10 2 #define POCR2RA_11 3 #define POCR2SB _SFR_MEM16(0xB0) #define POCR2SBL _SFR_MEM8(0xB0) #define POCR2SB_0 0 #define POCR2SB_1 1 #define POCR2SB_2 2 #define POCR2SB_3 3 #define POCR2SB_4 4 #define POCR2SB_5 5 #define POCR2SB_6 6 #define POCR2SB_7 7 #define POCR2SBH _SFR_MEM8(0xB1) #define POCR2SB_8 0 #define POCR2SB_9 1 #define POCR2SB_10 2 #define POCR2SB_11 3 #define POCR_RB _SFR_MEM16(0xB2) #define POCR_RBL _SFR_MEM8(0xB2) #define POCR_RB_0 0 #define POCR_RB_1 1 #define POCR_RB_2 2 #define POCR_RB_3 3 #define POCR_RB_4 4 #define POCR_RB_5 5 #define POCR_RB_6 6 #define POCR_RB_7 7 #define POCR_RBH _SFR_MEM8(0xB3) #define POCR_RB_8 0 #define POCR_RB_9 1 #define POCR_RB_10 2 #define POCR_RB_11 3 #define PSYNC _SFR_MEM8(0xB4) #define PSYNC00 0 #define PSYNC01 1 #define PSYNC10 2 #define PSYNC11 3 #define PSYNC20 4 #define PSYNC21 5 #define PCNF _SFR_MEM8(0xB5) #define POPA 2 #define POPB 3 #define PMODE 4 #define PULOCK 5 #define POC _SFR_MEM8(0xB6) #define POEN0A 0 #define POEN0B 1 #define POEN1A 2 #define POEN1B 3 #define POEN2A 4 #define POEN2B 5 #define PCTL _SFR_MEM8(0xB7) #define PRUN 0 #define PCCYC 1 #define PCLKSEL 5 #define PPRE0 6 #define PPRE1 7 #define PMIC0 _SFR_MEM8(0xB8) #define PRFM00 0 #define PRFM01 1 #define PRFM02 2 #define PAOC0 3 #define PFLTE0 4 #define PELEV0 5 #define PISEL0 6 #define POVEN0 7 #define PMIC1 _SFR_MEM8(0xB9) #define PRFM10 0 #define PRFM11 1 #define PRFM12 2 #define PAOC1 3 #define PFLTE1 4 #define PELEV1 5 #define PISEL1 6 #define POVEN1 7 #define PMIC2 _SFR_MEM8(0xBA) #define PRFM20 0 #define PRFM21 1 #define PRFM22 2 #define PAOC2 3 #define PFLTE2 4 #define PELEV2 5 #define PISEL2 6 #define POVEN2 7 #define PIM _SFR_MEM8(0xBB) #define PEOPE 0 #define PEVE0 1 #define PEVE1 2 #define PEVE2 3 #define PIFR _SFR_MEM8(0xBC) #define PEOP 0 #define PEV0 1 #define PEV1 2 #define PEV2 3 #define LINCR _SFR_MEM8(0xC8) #define LCMD0 0 #define LCMD1 1 #define LCMD2 2 #define LENA 3 #define LCONF0 4 #define LCONF1 5 #define LIN13 6 #define LSWRES 7 #define LINSIR _SFR_MEM8(0xC9) #define LRXOK 0 #define LTXOK 1 #define LIDOK 2 #define LERR 3 #define LBUSY 4 #define LIDST0 5 #define LIDST1 6 #define LIDST2 7 #define LINENIR _SFR_MEM8(0xCA) #define LENRXOK 0 #define LENTXOK 1 #define LENIDOK 2 #define LENERR 3 #define LINERR _SFR_MEM8(0xCB) #define LBERR 0 #define LCERR 1 #define LPERR 2 #define LSERR 3 #define LFERR 4 #define LOVERR 5 #define LTOERR 6 #define LABORT 7 #define LINBTR _SFR_MEM8(0xCC) #define LBT0 0 #define LBT1 1 #define LBT2 2 #define LBT3 3 #define LBT4 4 #define LBT5 5 #define LDISR 7 #define LINBRR _SFR_MEM16(0xCD) #define LINBRRL _SFR_MEM8(0xCD) #define LDIV0 0 #define LDIV1 1 #define LDIV2 2 #define LDIV3 3 #define LDIV4 4 #define LDIV5 5 #define LDIV6 6 #define LDIV7 7 #define LINBRRH _SFR_MEM8(0xCE) #define LDIV8 0 #define LDIV9 1 #define LDIV10 2 #define LDIV11 3 #define LINDLR _SFR_MEM8(0xCF) #define LRXDL0 0 #define LRXDL1 1 #define LRXDL2 2 #define LRXDL3 3 #define LTXDL0 4 #define LTXDL1 5 #define LTXDL2 6 #define LTXDL3 7 #define LINIDR _SFR_MEM8(0xD0) #define LID0 0 #define LID1 1 #define LID2 2 #define LID3 3 #define LID4 4 #define LID5 5 #define LP0 6 #define LP1 7 #define LINSEL _SFR_MEM8(0xD1) #define LINDX0 0 #define LINDX1 1 #define LINDX2 2 #define LAINC 3 #define LINDAT _SFR_MEM8(0xD2) #define LDATA0 0 #define LDATA1 1 #define LDATA2 2 #define LDATA3 3 #define LDATA4 4 #define LDATA5 5 #define LDATA6 6 #define LDATA7 7 #define CANGCON _SFR_MEM8(0xD8) #define SWRES 0 #define ENASTB 1 #define TEST 2 #define LISTEN 3 #define SYNTTC 4 #define TTC 5 #define OVRQ 6 #define ABRQ 7 #define CANGSTA _SFR_MEM8(0xD9) #define ERRP 0 #define BOFF 1 #define ENFG 2 #define RXBSY 3 #define TXBSY 4 #define OVFG 6 #define CANGIT _SFR_MEM8(0xDA) #define AERG 0 #define FERG 1 #define CERG 2 #define SERG 3 #define BXOK 4 #define OVRTIM 5 #define BOFFIT 6 #define CANIT 7 #define CANGIE _SFR_MEM8(0xDB) #define ENOVRT 0 #define ENERG 1 #define ENBX 2 #define ENERR 3 #define ENTX 4 #define ENRX 5 #define ENBOFF 6 #define ENIT 7 #define CANEN2 _SFR_MEM8(0xDC) #define ENMOB0 0 #define ENMOB1 1 #define ENMOB2 2 #define ENMOB3 3 #define ENMOB4 4 #define ENMOB5 5 #define CANEN1 _SFR_MEM8(0xDD) #define CANIE2 _SFR_MEM8(0xDE) #define IEMOB0 0 #define IEMOB1 1 #define IEMOB2 2 #define IEMOB3 3 #define IEMOB4 4 #define IEMOB5 5 #define CANIE1 _SFR_MEM8(0xDF) /* RegDef: CAN Status Interrupt MOb Register*/ #define CANSIT _SFR_MEM16(0xE0) #define CANSIT2 _SFR_MEM8(0xE0) #define SIT0 0 #define SIT1 1 #define SIT2 2 #define SIT3 3 #define SIT4 4 #define SIT5 5 #define CANSIT1 _SFR_MEM8(0xE1) #define CANBT1 _SFR_MEM8(0xE2) #define BRP0 1 #define BRP1 2 #define BRP2 3 #define BRP3 4 #define BRP4 5 #define BRP5 6 #define CANBT2 _SFR_MEM8(0xE3) #define PRS0 1 #define PRS1 2 #define PRS2 3 #define SJW0 5 #define SJW1 6 #define CANBT3 _SFR_MEM8(0xE4) #define SMP 0 #define PHS10 1 #define PHS11 2 #define PHS12 3 #define PHS20 4 #define PHS21 5 #define PHS22 6 #define CANTCON _SFR_MEM8(0xE5) #define TPRSC0 0 #define TPRSC1 1 #define TPRSC2 2 #define TPRSC3 3 #define TPRSC4 4 #define TPRSC5 5 #define TPRSC6 6 #define TPRSC7 7 #define CANTIM _SFR_MEM16(0xE6) #define CANTIML _SFR_MEM8(0xE6) #define CANTIM0 0 #define CANTIM1 1 #define CANTIM2 2 #define CANTIM3 3 #define CANTIM4 4 #define CANTIM5 5 #define CANTIM6 6 #define CANTIM7 7 #define CANTIMH _SFR_MEM8(0xE7) #define CANTIM8 0 #define CANTIM9 1 #define CANTIM10 2 #define CANTIM11 3 #define CANTIM12 4 #define CANTIM13 5 #define CANTIM14 6 #define CANTIM15 7 #define CANTTC _SFR_MEM16(0xE8) #define CANTTCL _SFR_MEM8(0xE8) #define TIMTCC0 0 #define TIMTCC1 1 #define TIMTCC2 2 #define TIMTCC3 3 #define TIMTCC4 4 #define TIMTCC5 5 #define TIMTCC6 6 #define TIMTCC7 7 #define CANTTCH _SFR_MEM8(0xE9) #define TIMTCC8 0 #define TIMTCC9 1 #define TIMTCC10 2 #define TIMTCC11 3 #define TIMTCC12 4 #define TIMTCC13 5 #define TIMTCC14 6 #define TIMTCC15 7 #define CANTEC _SFR_MEM8(0xEA) #define TEC0 0 #define TEC1 1 #define TEC2 2 #define TEC3 3 #define TEC4 4 #define TEC5 5 #define TEC6 6 #define TEC7 7 #define CANREC _SFR_MEM8(0xEB) #define REC0 0 #define REC1 1 #define REC2 2 #define REC3 3 #define REC4 4 #define REC5 5 #define REC6 6 #define REC7 7 #define CANHPMOB _SFR_MEM8(0xEC) #define CGP0 0 #define CGP1 1 #define CGP2 2 #define CGP3 3 #define HPMOB0 4 #define HPMOB1 5 #define HPMOB2 6 #define HPMOB3 7 #define CANPAGE _SFR_MEM8(0xED) #define INDX0 0 #define INDX1 1 #define INDX2 2 #define AINC 3 #define MOBNB0 4 #define MOBNB1 5 #define MOBNB2 6 #define MOBNB3 7 #define CANSTMOB _SFR_MEM8(0xEE) #define AERR 0 #define FERR 1 #define CERR 2 #define SERR 3 #define BERR 4 #define RXOK 5 #define TXOK 6 #define DLCW 7 #define CANCDMOB _SFR_MEM8(0xEF) #define DLC0 0 #define DLC1 1 #define DLC2 2 #define DLC3 3 #define IDE 4 #define RPLV 5 #define CONMOB0 6 #define CONMOB1 7 /* RegDef: CAN Identifier Tag Registers*/ #define CANIDT _SFR_MEM32(0xF0) #define CANIDT4 _SFR_MEM8(0xF0) #define RB0TAG 0 #define RB1TAG 1 #define RTRTAG 2 #define IDT0 3 #define IDT1 4 #define IDT2 5 #define IDT3 6 #define IDT4 7 #define CANIDT3 _SFR_MEM8(0xF1) #define IDT5 0 #define IDT6 1 #define IDT7 2 #define IDT8 3 #define IDT9 4 #define IDT10 5 #define IDT11 6 #define IDT12 7 #define CANIDT2 _SFR_MEM8(0xF2) #define IDT13 0 #define IDT14 1 #define IDT15 2 #define IDT16 3 #define IDT17 4 #define IDT18 5 #define IDT19 6 #define IDT20 7 #define CANIDT1 _SFR_MEM8(0xF3) #define IDT21 0 #define IDT22 1 #define IDT23 2 #define IDT24 3 #define IDT25 4 #define IDT26 5 #define IDT27 6 #define IDT28 7 /* RegDef: CAN Identifier Mask Registers */ #define CANIDM _SFR_MEM32(0xF4) #define CANIDM4 _SFR_MEM8(0xF4) #define IDEMSK 0 #define RTRMSK 2 #define IDMSK0 3 #define IDMSK1 4 #define IDMSK2 5 #define IDMSK3 6 #define IDMSK4 7 #define CANIDM3 _SFR_MEM8(0xF5) #define IDMSK5 0 #define IDMSK6 1 #define IDMSK7 2 #define IDMSK8 3 #define IDMSK9 4 #define IDMSK10 5 #define IDMSK11 6 #define IDMSK12 7 #define CANIDM2 _SFR_MEM8(0xF6) #define IDMSK13 0 #define IDMSK14 1 #define IDMSK15 2 #define IDMSK16 3 #define IDMSK17 4 #define IDMSK18 5 #define IDMSK19 6 #define IDMSK20 7 #define CANIDM1 _SFR_MEM8(0xF7) #define IDMSK21 0 #define IDMSK22 1 #define IDMSK23 2 #define IDMSK24 3 #define IDMSK25 4 #define IDMSK26 5 #define IDMSK27 6 #define IDMSK28 7 #define CANSTM _SFR_MEM16(0xF8) #define CANSTML _SFR_MEM8(0xF8) #define TIMSTM0 0 #define TIMSTM1 1 #define TIMSTM2 2 #define TIMSTM3 3 #define TIMSTM4 4 #define TIMSTM5 5 #define TIMSTM6 6 #define TIMSTM7 7 #define CANSTMH _SFR_MEM8(0xF9) #define TIMSTM8 0 #define TIMSTM9 1 #define TIMSTM10 2 #define TIMSTM11 3 #define TIMSTM12 4 #define TIMSTM13 5 #define TIMSTM14 6 #define TIMSTM15 7 #define CANMSG _SFR_MEM8(0xFA) #define MSG0 0 #define MSG1 1 #define MSG2 2 #define MSG3 3 #define MSG4 4 #define MSG5 5 #define MSG6 6 #define MSG7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define ANACOMP0_vect_num 1 #define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ #define ANACOMP1_vect_num 2 #define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ #define ANACOMP2_vect_num 3 #define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ #define ANACOMP3_vect_num 4 #define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ #define PSC_FAULT_vect_num 5 #define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ #define PSC_EC_vect_num 6 #define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ #define INT0_vect_num 7 #define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ #define INT1_vect_num 8 #define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ #define INT2_vect_num 9 #define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ #define INT3_vect_num 10 #define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 14 #define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 15 #define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 16 #define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ #define CAN_INT_vect_num 18 #define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ #define CAN_TOVF_vect_num 19 #define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ #define LIN_TC_vect_num 20 #define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ #define LIN_ERR_vect_num 21 #define LIN_ERR_vect _VECTOR(21) /* LIN Error */ #define PCINT0_vect_num 22 #define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 23 #define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 24 #define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ #define PCINT3_vect_num 25 #define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ #define SPI_STC_vect_num 26 #define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ #define ADC_vect_num 27 #define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ #define WDT_vect_num 28 #define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ #define EE_READY_vect_num 29 #define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ #define SPM_READY_vect_num 30 #define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (31 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (256) #define RAMSTART (0x0100) #define RAMSIZE (4096) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (0x0) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x7FF) #define E2PAGESIZE (8) #define FLASHEND (0xFFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ #define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ #define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ #define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x84 #endif /* _AVR_ATmega64M1_H_ */ avr-libc-1.8.0.orig/include/avr/pgmspace.h0000644000000000000000000012170711732702554015245 0ustar /* Copyright (c) 2002-2007 Marek Michalkiewicz Copyright (c) 2006, Carlos Lamas Copyright (c) 2009-2010, Jan Waclawek All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: pgmspace.h 2270 2011-12-29 08:42:00Z joerg_wunsch $ */ /* pgmspace.h Contributors: Created by Marek Michalkiewicz Eric B. Weddington Wolfgang Haidinger (pgm_read_dword()) Ivanov Anton (pgm_read_float()) */ /** \file */ /** \defgroup avr_pgmspace : Program Space Utilities \code #include #include \endcode The functions in this module provide interfaces for a program to access data stored in program space (flash memory) of the device. In order to use these functions, the target device must support either the \c LPM or \c ELPM instructions. \note These functions are an attempt to provide some compatibility with header files that come with IAR C, to make porting applications between different compilers easier. This is not 100% compatibility though (GCC does not have full support for multiple address spaces yet). \note If you are working with strings which are completely based in ram, use the standard string functions described in \ref avr_string. \note If possible, put your constant tables in the lower 64 KB and use pgm_read_byte_near() or pgm_read_word_near() instead of pgm_read_byte_far() or pgm_read_word_far() since it is more efficient that way, and you can still use the upper 64K for executable code. All functions that are suffixed with a \c _P \e require their arguments to be in the lower 64 KB of the flash ROM, as they do not use ELPM instructions. This is normally not a big concern as the linker setup arranges any program space constants declared using the macros from this header file so they are placed right after the interrupt vectors, and in front of any executable code. However, it can become a problem if there are too many of these constants, or for bootloaders on devices with more than 64 KB of ROM. All these functions will not work in that situation. \note For Xmega devices, make sure the NVM controller command register (\c NVM.CMD or \c NVM_CMD) is set to 0x00 (NOP) before using any of these functions. */ #ifndef __PGMSPACE_H_ #define __PGMSPACE_H_ 1 #define __need_size_t #include #include #include #ifndef __ATTR_CONST__ #define __ATTR_CONST__ __attribute__((__const__)) #endif #ifndef __ATTR_PROGMEM__ #define __ATTR_PROGMEM__ __attribute__((__progmem__)) #endif #ifndef __ATTR_PURE__ #define __ATTR_PURE__ __attribute__((__pure__)) #endif /** \ingroup avr_pgmspace \def PROGMEM Attribute to use in order to declare an object being located in flash ROM. */ #define PROGMEM __ATTR_PROGMEM__ #ifdef __cplusplus extern "C" { #endif #if defined(__DOXYGEN__) /* * Doxygen doesn't grok the appended attribute syntax of * GCC, and confuses the typedefs with function decls, so * supply a doxygen-friendly view. */ /** \ingroup avr_pgmspace \typedef prog_void \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of a "void" object located in flash ROM. Does not make much sense by itself, but can be used to declare a "void *" object in flash ROM. */ typedef void PROGMEM prog_void; /** \ingroup avr_pgmspace \typedef prog_char \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of a "char" object located in flash ROM. */ typedef char PROGMEM prog_char; /** \ingroup avr_pgmspace \typedef prog_uchar \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of an "unsigned char" object located in flash ROM. */ typedef unsigned char PROGMEM prog_uchar; /** \ingroup avr_pgmspace \typedef prog_int8_t \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of an "int8_t" object located in flash ROM. */ typedef int8_t PROGMEM prog_int8_t; /** \ingroup avr_pgmspace \typedef prog_uint8_t \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of an "uint8_t" object located in flash ROM. */ typedef uint8_t PROGMEM prog_uint8_t; /** \ingroup avr_pgmspace \typedef prog_int16_t \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of an "int16_t" object located in flash ROM. */ typedef int16_t PROGMEM prog_int16_t; /** \ingroup avr_pgmspace \typedef prog_uint16_t \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of an "uint16_t" object located in flash ROM. */ typedef uint16_t PROGMEM prog_uint16_t; /** \ingroup avr_pgmspace \typedef prog_int32_t \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of an "int32_t" object located in flash ROM. */ typedef int32_t PROGMEM prog_int32_t; /** \ingroup avr_pgmspace \typedef prog_uint32_t \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of an "uint32_t" object located in flash ROM. */ typedef uint32_t PROGMEM prog_uint32_t; /** \ingroup avr_pgmspace \typedef prog_int64_t \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of an "int64_t" object located in flash ROM. \note This type is not available when the compiler option -mint8 is in effect. */ typedef int64_t PROGMEM prog_int64_t; /** \ingroup avr_pgmspace \typedef prog_uint64_t \note DEPRECATED This typedef is now deprecated because the usage of the __progmem__ attribute on a type is not supported in GCC. However, the use of the __progmem__ attribute on a variable declaration is supported, and this is now the recommended usage. The typedef is only visible if the macro __PROG_TYPES_COMPAT__ has been defined before including (either by a #define directive, or by a -D compiler option.) Type of an "uint64_t" object located in flash ROM. \note This type is not available when the compiler option -mint8 is in effect. */ typedef uint64_t PROGMEM prog_uint64_t; /** \ingroup avr_pgmspace \def PGM_P Used to declare a variable that is a pointer to a string in program space. */ #ifndef PGM_P #define PGM_P const char * #endif /** \ingroup avr_pgmspace \def PGM_VOID_P Used to declare a generic pointer to an object in program space. */ #ifndef PGM_VOID_P #define PGM_VOID_P const void * #endif #elif defined(__PROG_TYPES_COMPAT__) /* !DOXYGEN */ typedef void prog_void __attribute__((__progmem__,deprecated("prog_void type is deprecated."))); typedef char prog_char __attribute__((__progmem__,deprecated("prog_char type is deprecated."))); typedef unsigned char prog_uchar __attribute__((__progmem__,deprecated("prog_uchar type is deprecated."))); typedef int8_t prog_int8_t __attribute__((__progmem__,deprecated("prog_int8_t type is deprecated."))); typedef uint8_t prog_uint8_t __attribute__((__progmem__,deprecated("prog_uint8_t type is deprecated."))); typedef int16_t prog_int16_t __attribute__((__progmem__,deprecated("prog_int16_t type is deprecated."))); typedef uint16_t prog_uint16_t __attribute__((__progmem__,deprecated("prog_uint16_t type is deprecated."))); typedef int32_t prog_int32_t __attribute__((__progmem__,deprecated("prog_int32_t type is deprecated."))); typedef uint32_t prog_uint32_t __attribute__((__progmem__,deprecated("prog_uint32_t type is deprecated."))); #if !__USING_MINT8 typedef int64_t prog_int64_t __attribute__((__progmem__,deprecated("prog_int64_t type is deprecated."))); typedef uint64_t prog_uint64_t __attribute__((__progmem__,deprecated("prog_uint64_t type is deprecated."))); #endif #ifndef PGM_P #define PGM_P const prog_char * #endif #ifndef PGM_VOID_P #define PGM_VOID_P const prog_void * #endif #else /* !defined(__DOXYGEN__), !defined(__PROG_TYPES_COMPAT__) */ #ifndef PGM_P #define PGM_P const char * #endif #ifndef PGM_VOID_P #define PGM_VOID_P const void * #endif #endif /* defined(__DOXYGEN__), defined(__PROG_TYPES_COMPAT__) */ /* Although in C, we can get away with just using __c, it does not work in C++. We need to use &__c[0] to avoid the compiler puking. Dave Hylands explaned it thusly, Let's suppose that we use PSTR("Test"). In this case, the type returned by __c is a prog_char[5] and not a prog_char *. While these are compatible, they aren't the same thing (especially in C++). The type returned by &__c[0] is a prog_char *, which explains why it works fine. */ #if defined(__DOXYGEN__) /* * The #define below is just a dummy that serves documentation * purposes only. */ /** \ingroup avr_pgmspace \def PSTR(s) Used to declare a static pointer to a string in program space. */ # define PSTR(s) ((const PROGMEM char *)(s)) #else /* !DOXYGEN */ /* The real thing. */ # define PSTR(s) (__extension__({static const char __c[] PROGMEM = (s); &__c[0];})) #endif /* DOXYGEN */ #define __LPM_classic__(addr) \ (__extension__({ \ uint16_t __addr16 = (uint16_t)(addr); \ uint8_t __result; \ __asm__ \ ( \ "lpm" "\n\t" \ "mov %0, r0" "\n\t" \ : "=r" (__result) \ : "z" (__addr16) \ : "r0" \ ); \ __result; \ })) #define __LPM_enhanced__(addr) \ (__extension__({ \ uint16_t __addr16 = (uint16_t)(addr); \ uint8_t __result; \ __asm__ \ ( \ "lpm %0, Z" "\n\t" \ : "=r" (__result) \ : "z" (__addr16) \ ); \ __result; \ })) #define __LPM_word_classic__(addr) \ (__extension__({ \ uint16_t __addr16 = (uint16_t)(addr); \ uint16_t __result; \ __asm__ \ ( \ "lpm" "\n\t" \ "mov %A0, r0" "\n\t" \ "adiw r30, 1" "\n\t" \ "lpm" "\n\t" \ "mov %B0, r0" "\n\t" \ : "=r" (__result), "=z" (__addr16) \ : "1" (__addr16) \ : "r0" \ ); \ __result; \ })) #define __LPM_word_enhanced__(addr) \ (__extension__({ \ uint16_t __addr16 = (uint16_t)(addr); \ uint16_t __result; \ __asm__ \ ( \ "lpm %A0, Z+" "\n\t" \ "lpm %B0, Z" "\n\t" \ : "=r" (__result), "=z" (__addr16) \ : "1" (__addr16) \ ); \ __result; \ })) #define __LPM_dword_classic__(addr) \ (__extension__({ \ uint16_t __addr16 = (uint16_t)(addr); \ uint32_t __result; \ __asm__ \ ( \ "lpm" "\n\t" \ "mov %A0, r0" "\n\t" \ "adiw r30, 1" "\n\t" \ "lpm" "\n\t" \ "mov %B0, r0" "\n\t" \ "adiw r30, 1" "\n\t" \ "lpm" "\n\t" \ "mov %C0, r0" "\n\t" \ "adiw r30, 1" "\n\t" \ "lpm" "\n\t" \ "mov %D0, r0" "\n\t" \ : "=r" (__result), "=z" (__addr16) \ : "1" (__addr16) \ : "r0" \ ); \ __result; \ })) #define __LPM_dword_enhanced__(addr) \ (__extension__({ \ uint16_t __addr16 = (uint16_t)(addr); \ uint32_t __result; \ __asm__ \ ( \ "lpm %A0, Z+" "\n\t" \ "lpm %B0, Z+" "\n\t" \ "lpm %C0, Z+" "\n\t" \ "lpm %D0, Z" "\n\t" \ : "=r" (__result), "=z" (__addr16) \ : "1" (__addr16) \ ); \ __result; \ })) #define __LPM_float_classic__(addr) \ (__extension__({ \ uint16_t __addr16 = (uint16_t)(addr); \ float __result; \ __asm__ \ ( \ "lpm" "\n\t" \ "mov %A0, r0" "\n\t" \ "adiw r30, 1" "\n\t" \ "lpm" "\n\t" \ "mov %B0, r0" "\n\t" \ "adiw r30, 1" "\n\t" \ "lpm" "\n\t" \ "mov %C0, r0" "\n\t" \ "adiw r30, 1" "\n\t" \ "lpm" "\n\t" \ "mov %D0, r0" "\n\t" \ : "=r" (__result), "=z" (__addr16) \ : "1" (__addr16) \ : "r0" \ ); \ __result; \ })) #define __LPM_float_enhanced__(addr) \ (__extension__({ \ uint16_t __addr16 = (uint16_t)(addr); \ float __result; \ __asm__ \ ( \ "lpm %A0, Z+" "\n\t" \ "lpm %B0, Z+" "\n\t" \ "lpm %C0, Z+" "\n\t" \ "lpm %D0, Z" "\n\t" \ : "=r" (__result), "=z" (__addr16) \ : "1" (__addr16) \ ); \ __result; \ })) #if defined (__AVR_HAVE_LPMX__) #define __LPM(addr) __LPM_enhanced__(addr) #define __LPM_word(addr) __LPM_word_enhanced__(addr) #define __LPM_dword(addr) __LPM_dword_enhanced__(addr) #define __LPM_float(addr) __LPM_float_enhanced__(addr) #else #define __LPM(addr) __LPM_classic__(addr) #define __LPM_word(addr) __LPM_word_classic__(addr) #define __LPM_dword(addr) __LPM_dword_classic__(addr) #define __LPM_float(addr) __LPM_float_classic__(addr) #endif /** \ingroup avr_pgmspace \def pgm_read_byte_near(address_short) Read a byte from the program space with a 16-bit (near) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_byte_near(address_short) __LPM((uint16_t)(address_short)) /** \ingroup avr_pgmspace \def pgm_read_word_near(address_short) Read a word from the program space with a 16-bit (near) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_word_near(address_short) __LPM_word((uint16_t)(address_short)) /** \ingroup avr_pgmspace \def pgm_read_dword_near(address_short) Read a double word from the program space with a 16-bit (near) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_dword_near(address_short) \ __LPM_dword((uint16_t)(address_short)) /** \ingroup avr_pgmspace \def pgm_read_float_near(address_short) Read a float from the program space with a 16-bit (near) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_float_near(address_short) \ __LPM_float((uint16_t)(address_short)) #if defined(RAMPZ) || defined(__DOXYGEN__) /* Only for devices with more than 64K of program memory. RAMPZ must be defined (see iom103.h, iom128.h). */ /* The classic functions are needed for ATmega103. */ #define __ELPM_classic__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ uint8_t __result; \ __asm__ \ ( \ "out %2, %C1" "\n\t" \ "mov r31, %B1" "\n\t" \ "mov r30, %A1" "\n\t" \ "elpm" "\n\t" \ "mov %0, r0" "\n\t" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r0", "r30", "r31" \ ); \ __result; \ })) #define __ELPM_enhanced__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ uint8_t __result; \ __asm__ \ ( \ "out %2, %C1" "\n\t" \ "movw r30, %1" "\n\t" \ "elpm %0, Z+" "\n\t" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r30", "r31" \ ); \ __result; \ })) #define __ELPM_xmega__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ uint8_t __result; \ __asm__ \ ( \ "in __tmp_reg__, %2" "\n\t" \ "out %2, %C1" "\n\t" \ "movw r30, %1" "\n\t" \ "elpm %0, Z+" "\n\t" \ "out %2, __tmp_reg__" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r30", "r31" \ ); \ __result; \ })) #define __ELPM_word_classic__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ uint16_t __result; \ __asm__ \ ( \ "out %2, %C1" "\n\t" \ "mov r31, %B1" "\n\t" \ "mov r30, %A1" "\n\t" \ "elpm" "\n\t" \ "mov %A0, r0" "\n\t" \ "in r0, %2" "\n\t" \ "adiw r30, 1" "\n\t" \ "adc r0, __zero_reg__" "\n\t" \ "out %2, r0" "\n\t" \ "elpm" "\n\t" \ "mov %B0, r0" "\n\t" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r0", "r30", "r31" \ ); \ __result; \ })) #define __ELPM_word_enhanced__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ uint16_t __result; \ __asm__ \ ( \ "out %2, %C1" "\n\t" \ "movw r30, %1" "\n\t" \ "elpm %A0, Z+" "\n\t" \ "elpm %B0, Z" "\n\t" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r30", "r31" \ ); \ __result; \ })) #define __ELPM_word_xmega__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ uint16_t __result; \ __asm__ \ ( \ "in __tmp_reg__, %2" "\n\t" \ "out %2, %C1" "\n\t" \ "movw r30, %1" "\n\t" \ "elpm %A0, Z+" "\n\t" \ "elpm %B0, Z" "\n\t" \ "out %2, __tmp_reg__" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r30", "r31" \ ); \ __result; \ })) #define __ELPM_dword_classic__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ uint32_t __result; \ __asm__ \ ( \ "out %2, %C1" "\n\t" \ "mov r31, %B1" "\n\t" \ "mov r30, %A1" "\n\t" \ "elpm" "\n\t" \ "mov %A0, r0" "\n\t" \ "in r0, %2" "\n\t" \ "adiw r30, 1" "\n\t" \ "adc r0, __zero_reg__" "\n\t" \ "out %2, r0" "\n\t" \ "elpm" "\n\t" \ "mov %B0, r0" "\n\t" \ "in r0, %2" "\n\t" \ "adiw r30, 1" "\n\t" \ "adc r0, __zero_reg__" "\n\t" \ "out %2, r0" "\n\t" \ "elpm" "\n\t" \ "mov %C0, r0" "\n\t" \ "in r0, %2" "\n\t" \ "adiw r30, 1" "\n\t" \ "adc r0, __zero_reg__" "\n\t" \ "out %2, r0" "\n\t" \ "elpm" "\n\t" \ "mov %D0, r0" "\n\t" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r0", "r30", "r31" \ ); \ __result; \ })) #define __ELPM_dword_enhanced__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ uint32_t __result; \ __asm__ \ ( \ "out %2, %C1" "\n\t" \ "movw r30, %1" "\n\t" \ "elpm %A0, Z+" "\n\t" \ "elpm %B0, Z+" "\n\t" \ "elpm %C0, Z+" "\n\t" \ "elpm %D0, Z" "\n\t" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r30", "r31" \ ); \ __result; \ })) #define __ELPM_dword_xmega__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ uint32_t __result; \ __asm__ \ ( \ "in __tmp_reg__, %2" "\n\t" \ "out %2, %C1" "\n\t" \ "movw r30, %1" "\n\t" \ "elpm %A0, Z+" "\n\t" \ "elpm %B0, Z+" "\n\t" \ "elpm %C0, Z+" "\n\t" \ "elpm %D0, Z" "\n\t" \ "out %2, __tmp_reg__" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r30", "r31" \ ); \ __result; \ })) #define __ELPM_float_classic__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ float __result; \ __asm__ \ ( \ "out %2, %C1" "\n\t" \ "mov r31, %B1" "\n\t" \ "mov r30, %A1" "\n\t" \ "elpm" "\n\t" \ "mov %A0, r0" "\n\t" \ "in r0, %2" "\n\t" \ "adiw r30, 1" "\n\t" \ "adc r0, __zero_reg__" "\n\t" \ "out %2, r0" "\n\t" \ "elpm" "\n\t" \ "mov %B0, r0" "\n\t" \ "in r0, %2" "\n\t" \ "adiw r30, 1" "\n\t" \ "adc r0, __zero_reg__" "\n\t" \ "out %2, r0" "\n\t" \ "elpm" "\n\t" \ "mov %C0, r0" "\n\t" \ "in r0, %2" "\n\t" \ "adiw r30, 1" "\n\t" \ "adc r0, __zero_reg__" "\n\t" \ "out %2, r0" "\n\t" \ "elpm" "\n\t" \ "mov %D0, r0" "\n\t" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r0", "r30", "r31" \ ); \ __result; \ })) #define __ELPM_float_enhanced__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ float __result; \ __asm__ \ ( \ "out %2, %C1" "\n\t" \ "movw r30, %1" "\n\t" \ "elpm %A0, Z+" "\n\t" \ "elpm %B0, Z+" "\n\t" \ "elpm %C0, Z+" "\n\t" \ "elpm %D0, Z" "\n\t" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r30", "r31" \ ); \ __result; \ })) #define __ELPM_float_xmega__(addr) \ (__extension__({ \ uint32_t __addr32 = (uint32_t)(addr); \ float __result; \ __asm__ \ ( \ "in __tmp_reg__, %2" "\n\t" \ "out %2, %C1" "\n\t" \ "movw r30, %1" "\n\t" \ "elpm %A0, Z+" "\n\t" \ "elpm %B0, Z+" "\n\t" \ "elpm %C0, Z+" "\n\t" \ "elpm %D0, Z" "\n\t" \ "out %2, __tmp_reg__" \ : "=r" (__result) \ : "r" (__addr32), \ "I" (_SFR_IO_ADDR(RAMPZ)) \ : "r30", "r31" \ ); \ __result; \ })) /* Check for architectures that implement RAMPD (avrxmega3, avrxmega5, avrxmega7) as they need to save/restore RAMPZ for ELPM macros so it does not interfere with data accesses. */ #if defined (__AVR_HAVE_RAMPD__) #define __ELPM(addr) __ELPM_xmega__(addr) #define __ELPM_word(addr) __ELPM_word_xmega__(addr) #define __ELPM_dword(addr) __ELPM_dword_xmega__(addr) #define __ELPM_float(addr) __ELPM_float_xmega__(addr) #else #if defined (__AVR_HAVE_LPMX__) #define __ELPM(addr) __ELPM_enhanced__(addr) #define __ELPM_word(addr) __ELPM_word_enhanced__(addr) #define __ELPM_dword(addr) __ELPM_dword_enhanced__(addr) #define __ELPM_float(addr) __ELPM_float_enhanced__(addr) #else #define __ELPM(addr) __ELPM_classic__(addr) #define __ELPM_word(addr) __ELPM_word_classic__(addr) #define __ELPM_dword(addr) __ELPM_dword_classic__(addr) #define __ELPM_float(addr) __ELPM_float_classic__(addr) #endif /* __AVR_HAVE_LPMX__ */ #endif /* __AVR_HAVE_RAMPD__ */ /** \ingroup avr_pgmspace \def pgm_read_byte_far(address_long) Read a byte from the program space with a 32-bit (far) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_byte_far(address_long) __ELPM((uint32_t)(address_long)) /** \ingroup avr_pgmspace \def pgm_read_word_far(address_long) Read a word from the program space with a 32-bit (far) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_word_far(address_long) __ELPM_word((uint32_t)(address_long)) /** \ingroup avr_pgmspace \def pgm_read_dword_far(address_long) Read a double word from the program space with a 32-bit (far) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_dword_far(address_long) __ELPM_dword((uint32_t)(address_long)) /** \ingroup avr_pgmspace \def pgm_read_float_far(address_long) Read a float from the program space with a 32-bit (far) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_float_far(address_long) __ELPM_float((uint32_t)(address_long)) #endif /* RAMPZ or __DOXYGEN__ */ /** \ingroup avr_pgmspace \def pgm_read_byte(address_short) Read a byte from the program space with a 16-bit (near) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_byte(address_short) pgm_read_byte_near(address_short) /** \ingroup avr_pgmspace \def pgm_read_word(address_short) Read a word from the program space with a 16-bit (near) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_word(address_short) pgm_read_word_near(address_short) /** \ingroup avr_pgmspace \def pgm_read_dword(address_short) Read a double word from the program space with a 16-bit (near) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_dword(address_short) pgm_read_dword_near(address_short) /** \ingroup avr_pgmspace \def pgm_read_float(address_short) Read a float from the program space with a 16-bit (near) address. \note The address is a byte address. The address is in the program space. */ #define pgm_read_float(address_short) pgm_read_float_near(address_short) /* pgm_get_far_address() macro This macro facilitates the obtention of a 32 bit "far" pointer (only 24 bits used) to data even passed the 64KB limit for the 16 bit ordinary pointer. It is similar to the '&' operator, with some limitations. Comments: - The overhead is minimal and it's mainly due to the 32 bit size operation. - 24 bit sizes guarantees the code compatibility for use in future devices. - hh8() is an undocumented feature but seems to give the third significant byte of a 32 bit data and accepts symbols, complementing the functionality of hi8() and lo8(). There is not an equivalent assembler function to get the high significant byte. - 'var' has to be resolved at linking time as an existing symbol, i.e, a simple type variable name, an array name (not an indexed element of the array, if the index is a constant the compiler does not complain but fails to get the address if optimization is enabled), a struct name or a struct field name, a function identifier, a linker defined identifier,... - The returned value is the identifier's VMA (virtual memory address) determined by the linker and falls in the corresponding memory region. The AVR Harvard architecture requires non overlapping VMA areas for the multiple address spaces in the processor: Flash ROM, RAM, and EEPROM. Typical offset for this are 0x00000000, 0x00800xx0, and 0x00810000 respectively, derived from the linker script used and linker options. The value returned can be seen then as a universal pointer. */ #define pgm_get_far_address(var) \ ({ \ uint_farptr_t tmp; \ \ __asm__ __volatile__( \ \ "ldi %A0, lo8(%1)" "\n\t" \ "ldi %B0, hi8(%1)" "\n\t" \ "ldi %C0, hh8(%1)" "\n\t" \ "clr %D0" "\n\t" \ : \ "=d" (tmp) \ : \ "p" (&(var)) \ ); \ tmp; \ }) extern const void * memchr_P(const void *, int __val, size_t __len) __ATTR_CONST__; extern int memcmp_P(const void *, const void *, size_t) __ATTR_PURE__; extern void *memccpy_P(void *, const void *, int __val, size_t); extern void *memcpy_P(void *, const void *, size_t); extern void *memmem_P(const void *, size_t, const void *, size_t) __ATTR_PURE__; extern const void * memrchr_P(const void *, int __val, size_t __len) __ATTR_CONST__; extern char *strcat_P(char *, const char *); extern const char * strchr_P(const char *, int __val) __ATTR_CONST__; extern const char * strchrnul_P(const char *, int __val) __ATTR_CONST__; extern int strcmp_P(const char *, const char *) __ATTR_PURE__; extern char *strcpy_P(char *, const char *); extern int strcasecmp_P(const char *, const char *) __ATTR_PURE__; extern char *strcasestr_P(const char *, const char *) __ATTR_PURE__; extern size_t strcspn_P(const char *__s, const char * __reject) __ATTR_PURE__; extern size_t strlcat_P (char *, const char *, size_t ); extern size_t strlcpy_P (char *, const char *, size_t ); extern size_t __strlen_P(const char *) __ATTR_CONST__; /* program memory can't change */ extern size_t strnlen_P(const char *, size_t) __ATTR_CONST__; /* program memory can't change */ extern int strncmp_P(const char *, const char *, size_t) __ATTR_PURE__; extern int strncasecmp_P(const char *, const char *, size_t) __ATTR_PURE__; extern char *strncat_P(char *, const char *, size_t); extern char *strncpy_P(char *, const char *, size_t); extern char *strpbrk_P(const char *__s, const char * __accept) __ATTR_PURE__; extern const char * strrchr_P(const char *, int __val) __ATTR_CONST__; extern char *strsep_P(char **__sp, const char * __delim); extern size_t strspn_P(const char *__s, const char * __accept) __ATTR_PURE__; extern char *strstr_P(const char *, const char *) __ATTR_PURE__; extern char *strtok_P(char *__s, const char * __delim); extern char *strtok_rP(char *__s, const char * __delim, char **__last); extern size_t strlen_PF (uint_farptr_t src) __ATTR_CONST__; /* program memory can't change */ extern size_t strnlen_PF (uint_farptr_t src, size_t len) __ATTR_CONST__; /* program memory can't change */ extern void *memcpy_PF (void *dest, uint_farptr_t src, size_t len); extern char *strcpy_PF (char *dest, uint_farptr_t src); extern char *strncpy_PF (char *dest, uint_farptr_t src, size_t len); extern char *strcat_PF (char *dest, uint_farptr_t src); extern size_t strlcat_PF (char *dst, uint_farptr_t src, size_t siz); extern char *strncat_PF (char *dest, uint_farptr_t src, size_t len); extern int strcmp_PF (const char *s1, uint_farptr_t s2) __ATTR_PURE__; extern int strncmp_PF (const char *s1, uint_farptr_t s2, size_t n) __ATTR_PURE__; extern int strcasecmp_PF (const char *s1, uint_farptr_t s2) __ATTR_PURE__; extern int strncasecmp_PF (const char *s1, uint_farptr_t s2, size_t n) __ATTR_PURE__; extern char *strstr_PF (const char *s1, uint_farptr_t s2); extern size_t strlcpy_PF (char *dst, uint_farptr_t src, size_t siz); extern int memcmp_PF(const void *, uint_farptr_t, size_t) __ATTR_PURE__; __attribute__((__always_inline__)) static inline size_t strlen_P(const char * s); static inline size_t strlen_P(const char *s) { return __builtin_constant_p(__builtin_strlen(s)) ? __builtin_strlen(s) : __strlen_P(s); } #ifdef __cplusplus } #endif #endif /* __PGMSPACE_H_ */ avr-libc-1.8.0.orig/include/avr/iom16hvbrevb.h0000755000000000000000000005156111732702554015763 0ustar /* Copyright (c) 2009, 2011 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16hvbrevb.h 2086 2009-12-15 03:24:16Z arcanum $ */ /* avr/iom16hvbrevb.h - definitions for ATmega16HVB revision B */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16hvbrevb.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega16HVBREVB_H_ #define _AVR_ATmega16HVBREVB_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 3 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 3 #define OSICSR _SFR_IO8(0x17) #define OSIEN 0 #define OSIST 1 #define OSISEL0 4 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define ICS0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define TCNT0 _SFR_IO16(0x26) #define TCNT0L _SFR_IO8(0x26) #define TCNT0L0 0 #define TCNT0L1 1 #define TCNT0L2 2 #define TCNT0L3 3 #define TCNT0L4 4 #define TCNT0L5 5 #define TCNT0L6 6 #define TCNT0L7 7 #define TCNT0H _SFR_IO8(0x27) #define TCNT0H0 0 #define TCNT0H1 1 #define TCNT0H2 2 #define TCNT0H3 3 #define TCNT0H4 4 #define TCNT0H5 5 #define TCNT0H6 6 #define TCNT0H7 7 #define OCR0A _SFR_IO8(0x28) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0B _SFR_IO8(0x29) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define DWDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BODRF 2 #define WDRF 3 #define OCDRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define CKOE 5 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define LBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRVADC 0 #define PRTIM0 1 #define PRTIM1 2 #define PRSPI 3 #define PRVRM 5 #define PRTWI 6 #define FOSCCAL _SFR_MEM8(0x66) #define FCAL0 0 #define FCAL1 1 #define FCAL2 2 #define FCAL3 3 #define FCAL4 4 #define FCAL5 5 #define FCAL6 6 #define FCAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT4 0 #define PCINT5 1 #define PCINT6 2 #define PCINT7 3 #define PCINT8 4 #define PCINT9 5 #define PCINT10 6 #define PCINT11 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 3 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 3 #define VADC _SFR_MEM16(0x78) #define VADCL _SFR_MEM8(0x78) #define VADC0 0 #define VADC1 1 #define VADC2 2 #define VADC3 3 #define VADC4 4 #define VADC5 5 #define VADC6 6 #define VADC7 7 #define VADCH _SFR_MEM8(0x79) #define VADC8 0 #define VADC9 1 #define VADC10 2 #define VADC11 3 #define VADCSR _SFR_MEM8(0x7A) #define VADCCIE 0 #define VADCCIF 1 #define VADSC 2 #define VADEN 3 #define VADMUX _SFR_MEM8(0x7C) #define VADMUX0 0 #define VADMUX1 1 #define VADMUX2 2 #define VADMUX3 3 #define DIDR0 _SFR_MEM8(0x7E) #define PA0DID 0 #define PA1DID 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define ICS1 3 #define ICES1 4 #define ICNC1 5 #define ICEN1 6 #define TCW1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define OCR1A _SFR_MEM8(0x88) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define OCR1B _SFR_MEM8(0x89) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define TWBCSR _SFR_MEM8(0xBE) #define TWBCIP 0 #define TWBDT0 1 #define TWBDT1 2 #define TWBCIE 6 #define TWBCIF 7 #define ROCR _SFR_MEM8(0xC8) #define ROCWIE 0 #define ROCWIF 1 #define ROCD 4 #define ROCS 7 #define BGCCR _SFR_MEM8(0xD0) #define BGCC0 0 #define BGCC1 1 #define BGCC2 2 #define BGCC3 3 #define BGCC4 4 #define BGCC5 5 #define BGCRR _SFR_MEM8(0xD1) #define BGCR0 0 #define BGCR1 1 #define BGCR2 2 #define BGCR3 3 #define BGCR4 4 #define BGCR5 5 #define BGCR6 6 #define BGCR7 7 #define BGCSR _SFR_MEM8(0xD2) #define BGSCDIE 0 #define BGSCDIF 1 #define BGSCDE 4 #define BGD 5 #define CHGDCSR _SFR_MEM8(0xD4) #define CHGDIE 0 #define CHGDIF 1 #define CHGDISC0 2 #define CHGDISC1 3 #define BATTPVL 4 #define CADAC0 _SFR_MEM8(0xE0) #define CADAC00 0 #define CADAC01 1 #define CADAC02 2 #define CADAC03 3 #define CADAC04 4 #define CADAC05 5 #define CADAC06 6 #define CADAC07 7 #define CADAC1 _SFR_MEM8(0xE1) #define CADAC08 0 #define CADAC09 1 #define CADAC10 2 #define CADAC11 3 #define CADAC12 4 #define CADAC13 5 #define CADAC14 6 #define CADAC15 7 #define CADAC2 _SFR_MEM8(0xE2) #define CADAC16 0 #define CADAC17 1 #define CADAC18 2 #define CADAC19 3 #define CADAC20 4 #define CADAC21 5 #define CADAC22 6 #define CADAC23 7 #define CADAC3 _SFR_MEM8(0xE3) #define CADAC24 0 #define CADAC25 1 #define CADAC26 2 #define CADAC27 3 #define CADAC28 4 #define CADAC29 5 #define CADAC30 6 #define CADAC31 7 #define CADIC _SFR_MEM16(0xE4) #define CADICL _SFR_MEM8(0xE4) #define CADICL0 0 #define CADICL1 1 #define CADICL2 2 #define CADICL3 3 #define CADICL4 4 #define CADICL5 5 #define CADICL6 6 #define CADICL7 7 #define CADICH _SFR_MEM8(0xE5) #define CADICH0 0 #define CADICH1 1 #define CADICH2 2 #define CADICH3 3 #define CADICH4 4 #define CADICH5 5 #define CADICH6 6 #define CADICH7 7 #define CADCSRA _SFR_MEM8(0xE6) #define CADSE 0 #define CADSI0 1 #define CADSI1 2 #define CADAS0 3 #define CADAS1 4 #define CADUB 5 #define CADPOL 6 #define CADEN 7 #define CADCSRB _SFR_MEM8(0xE7) #define CADICIF 0 #define CADRCIF 1 #define CADACIF 2 #define CADICIE 4 #define CADRCIE 5 #define CADACIE 6 #define CADCSRC _SFR_MEM8(0xE8) #define CADVSE 0 #define CADRCC _SFR_MEM8(0xE9) #define CADRCC0 0 #define CADRCC1 1 #define CADRCC2 2 #define CADRCC3 3 #define CADRCC4 4 #define CADRCC5 5 #define CADRCC6 6 #define CADRCC7 7 #define CADRDC _SFR_MEM8(0xEA) #define CADRDC0 0 #define CADRDC1 1 #define CADRDC2 2 #define CADRDC3 3 #define CADRDC4 4 #define CADRDC5 5 #define CADRDC6 6 #define CADRDC7 7 #define FCSR _SFR_MEM8(0xF0) #define CFE 0 #define DFE 1 #define CPS 2 #define DUVRD 3 #define CBCR _SFR_MEM8(0xF1) #define CBE1 0 #define CBE2 1 #define CBE3 2 #define CBE4 3 #define BPIMSK _SFR_MEM8(0xF2) #define CHCIE 0 #define DHCIE 1 #define COCIE 2 #define DOCIE 3 #define SCIE 4 #define BPIFR _SFR_MEM8(0xF3) #define CHCIF 0 #define DHCIF 1 #define COCIF 2 #define DOCIF 3 #define SCIF 4 #define BPSCD _SFR_MEM8(0xF5) #define SCDL0 0 #define SCDL1 1 #define SCDL2 2 #define SCDL3 3 #define SCDL4 4 #define SCDL5 5 #define SCDL6 6 #define SCDL7 7 #define BPDOCD _SFR_MEM8(0xF6) #define DOCDL0 0 #define DOCDL1 1 #define DOCDL2 2 #define DOCDL3 3 #define DOCDL4 4 #define DOCDL5 5 #define DOCDL6 6 #define DOCDL7 7 #define BPCOCD _SFR_MEM8(0xF7) #define COCDL0 0 #define COCDL1 1 #define COCDL2 2 #define COCDL3 3 #define COCDL4 4 #define COCDL5 5 #define COCDL6 6 #define COCDL7 7 #define BPDHCD _SFR_MEM8(0xF8) #define DHCDL0 0 #define DHCDL1 1 #define DHCDL2 2 #define DHCDL3 3 #define DHCDL4 4 #define DHCDL5 5 #define DHCDL6 6 #define DHCDL7 7 #define BPCHCD _SFR_MEM8(0xF9) #define CHCDL0 0 #define CHCDL1 1 #define CHCDL2 2 #define CHCDL3 3 #define CHCDL4 4 #define CHCDL5 5 #define CHCDL6 6 #define CHCDL7 7 #define BPSCTR _SFR_MEM8(0xFA) #define SCPT0 0 #define SCPT1 1 #define SCPT2 2 #define SCPT3 3 #define SCPT4 4 #define SCPT5 5 #define SCPT6 6 #define BPOCTR _SFR_MEM8(0xFB) #define OCPT0 0 #define OCPT1 1 #define OCPT2 2 #define OCPT3 3 #define OCPT4 4 #define OCPT5 5 #define BPHCTR _SFR_MEM8(0xFC) #define HCPT0 0 #define HCPT1 1 #define HCPT2 2 #define HCPT3 3 #define HCPT4 4 #define HCPT5 5 #define BPCR _SFR_MEM8(0xFD) #define CHCD 0 #define DHCD 1 #define COCD 2 #define DOCD 3 #define SCD 4 #define EPID 5 #define BPPLR _SFR_MEM8(0xFE) #define BPPL 0 #define BPPLE 1 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define BPINT_vect_num 1 #define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ #define VREGMON_vect_num 2 #define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ #define INT0_vect_num 3 #define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ #define INT1_vect_num 4 #define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ #define INT2_vect_num 5 #define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ #define INT3_vect_num 6 #define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ #define PCINT0_vect_num 7 #define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ #define PCINT1_vect_num 8 #define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ #define WDT_vect_num 9 #define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ #define BGSCD_vect_num 10 #define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ #define CHDET_vect_num 11 #define CHDET_vect _VECTOR(11) /* Charger Detect */ #define TIMER1_IC_vect_num 12 #define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ #define TIMER0_IC_vect_num 16 #define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ #define TIMER0_COMPA_vect_num 17 #define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ #define TIMER0_COMPB_vect_num 18 #define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ #define TIMER0_OVF_vect_num 19 #define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ #define TWIBUSCD_vect_num 20 #define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ #define TWI_vect_num 21 #define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ #define SPI_STC_vect_num 22 #define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ #define VADC_vect_num 23 #define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ #define CCADC_CONV_vect_num 24 #define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ #define CCADC_REG_CUR_vect_num 25 #define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ #define CCADC_ACC_vect_num 26 #define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ #define EE_READY_vect_num 27 #define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ #define SPM_vect_num 28 #define SPM_vect _VECTOR(28) /* SPM Ready */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (29 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (1024) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (NA) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x3FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ #define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ #define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ #define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ #define FUSE_DUVRDINIT (unsigned char)~_BV(4) /* Reset Value of DUVRDRegister */ #define HFUSE_DEFAULT (FUSE_DUVRDINIT & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x0D /* Device Pin Definitions */ #define PV2_DDR DDRV #define PV2_PORT PORTV #define PV2_PIN PINV #define PV2_BIT 2 #define PV1_DDR DDRV #define PV1_PORT PORTV #define PV1_PIN PINV #define PV1_BIT 1 #define NV_DDR DDRNV #define NV_PORT PORTNV #define NV_PIN PINNV #define NV_BIT NV #define VFET_DDR DDRVFET #define VFET_PORT PORTVFET #define VFET_PIN PINVFET #define VFET_BIT VFET #define CF1P_DDR DDRCF1P #define CF1P_PORT PORTCF1P #define CF1P_PIN PINCF1P #define CF1P_BIT CF1P #define CF1N_DDR DDRCF1N #define CF1N_PORT PORTCF1N #define CF1N_PIN PINCF1N #define CF1N_BIT CF1N #define CF2P_DDR DDRCF2P #define CF2P_PORT PORTCF2P #define CF2P_PIN PINCF2P #define CF2P_BIT CF2P #define CF2N_DDR DDRCF2N #define CF2N_PORT PORTCF2N #define CF2N_PIN PINCF2N #define CF2N_BIT CF2N #define VREG_DDR DDRVREG #define VREG_PORT PORTVREG #define VREG_PIN PINVREG #define VREG_BIT VREG #define VREF_DDR DDRVREF #define VREF_PORT PORTVREF #define VREF_PIN PINVREF #define VREF_BIT VREF #define VREFGND_DDR DDRVREFGND #define VREFGND_PORT PORTVREFGND #define VREFGND_PIN PINVREFGND #define VREFGND_BIT VREFGND #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI #define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI #define NI_PIN PINNI #define NI_BIT NI #define PA0_DDR DDRA #define PA0_PORT PORTA #define PA0_PIN PINA #define PA0_BIT 0 #define PA1_DDR DDRA #define PA1_PORT PORTA #define PA1_PIN PINA #define PA1_BIT 1 #define PA2_DDR DDRA #define PA2_PORT PORTA #define PA2_PIN PINA #define PA2_BIT 2 #define PB0_DDR DDRB #define PB0_PORT PORTB #define PB0_PIN PINB #define PB0_BIT 0 #define PB1_DDR DDRB #define PB1_PORT PORTB #define PB1_PIN PINB #define PB1_BIT 1 #define PB2_DDR DDRB #define PB2_PORT PORTB #define PB2_PIN PINB #define PB2_BIT 2 #define PB3_DDR DDRB #define PB3_PORT PORTB #define PB3_PIN PINB #define PB3_BIT 3 #define PC0_DDR DDRC #define PC0_PORT PORTC #define PC0_PIN PINC #define PC0_BIT 0 #define BATT_DDR DDRBATT #define BATT_PORT PORTBATT #define BATT_PIN PINBATT #define BATT_BIT BATT #define OC_DDR DDROC #define OC_PORT PORTOC #define OC_PIN PINOC #define OC_BIT OC #endif /* _AVR_ATmega16HVBREVB_H_ */ avr-libc-1.8.0.orig/include/avr/sfr_defs.h0000644000000000000000000002127411732702554015237 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/sfr_defs.h - macros for accessing AVR special function registers */ /* $Id: sfr_defs.h 1691 2008-04-28 22:05:42Z arcanum $ */ #ifndef _AVR_SFR_DEFS_H_ #define _AVR_SFR_DEFS_H_ 1 /** \defgroup avr_sfr_notes Additional notes from \ingroup avr_sfr The \c file is included by all of the \c files, which use macros defined here to make the special function register definitions look like C variables or simple constants, depending on the _SFR_ASM_COMPAT define. Some examples from \c to show how to define such macros: \code #define PORTA _SFR_IO8(0x02) #define EEAR _SFR_IO16(0x21) #define UDR0 _SFR_MEM8(0xC6) #define TCNT3 _SFR_MEM16(0x94) #define CANIDT _SFR_MEM32(0xF0) \endcode If \c _SFR_ASM_COMPAT is not defined, C programs can use names like PORTA directly in C expressions (also on the left side of assignment operators) and GCC will do the right thing (use short I/O instructions if possible). The \c __SFR_OFFSET definition is not used in any way in this case. Define \c _SFR_ASM_COMPAT as 1 to make these names work as simple constants (addresses of the I/O registers). This is necessary when included in preprocessed assembler (*.S) source files, so it is done automatically if \c __ASSEMBLER__ is defined. By default, all addresses are defined as if they were memory addresses (used in \c lds/sts instructions). To use these addresses in \c in/out instructions, you must subtract 0x20 from them. For more backwards compatibility, insert the following at the start of your old assembler source file: \code #define __SFR_OFFSET 0 \endcode This automatically subtracts 0x20 from I/O space addresses, but it's a hack, so it is recommended to change your source: wrap such addresses in macros defined here, as shown below. After this is done, the __SFR_OFFSET definition is no longer necessary and can be removed. Real example - this code could be used in a boot loader that is portable between devices with \c SPMCR at different addresses. \verbatim : #define SPMCR _SFR_IO8(0x37) : #define SPMCR _SFR_MEM8(0x68) \endverbatim \code #if _SFR_IO_REG_P(SPMCR) out _SFR_IO_ADDR(SPMCR), r24 #else sts _SFR_MEM_ADDR(SPMCR), r24 #endif \endcode You can use the \c in/out/cbi/sbi/sbic/sbis instructions, without the _SFR_IO_REG_P test, if you know that the register is in the I/O space (as with \c SREG, for example). If it isn't, the assembler will complain (I/O address out of range 0...0x3f), so this should be fairly safe. If you do not define \c __SFR_OFFSET (so it will be 0x20 by default), all special register addresses are defined as memory addresses (so \c SREG is 0x5f), and (if code size and speed are not important, and you don't like the ugly \#if above) you can always use lds/sts to access them. But, this will not work if __SFR_OFFSET != 0x20, so use a different macro (defined only if __SFR_OFFSET == 0x20) for safety: \code sts _SFR_ADDR(SPMCR), r24 \endcode In C programs, all 3 combinations of \c _SFR_ASM_COMPAT and __SFR_OFFSET are supported - the \c _SFR_ADDR(SPMCR) macro can be used to get the address of the \c SPMCR register (0x57 or 0x68 depending on device). */ #ifdef __ASSEMBLER__ #define _SFR_ASM_COMPAT 1 #elif !defined(_SFR_ASM_COMPAT) #define _SFR_ASM_COMPAT 0 #endif #ifndef __ASSEMBLER__ /* These only work in C programs. */ #include #define _MMIO_BYTE(mem_addr) (*(volatile uint8_t *)(mem_addr)) #define _MMIO_WORD(mem_addr) (*(volatile uint16_t *)(mem_addr)) #define _MMIO_DWORD(mem_addr) (*(volatile uint32_t *)(mem_addr)) #endif #if _SFR_ASM_COMPAT #ifndef __SFR_OFFSET /* Define as 0 before including this file for compatibility with old asm sources that don't subtract __SFR_OFFSET from symbolic I/O addresses. */ # if __AVR_ARCH__ >= 100 # define __SFR_OFFSET 0x00 # else # define __SFR_OFFSET 0x20 # endif #endif #if (__SFR_OFFSET != 0) && (__SFR_OFFSET != 0x20) #error "__SFR_OFFSET must be 0 or 0x20" #endif #define _SFR_MEM8(mem_addr) (mem_addr) #define _SFR_MEM16(mem_addr) (mem_addr) #define _SFR_MEM32(mem_addr) (mem_addr) #define _SFR_IO8(io_addr) ((io_addr) + __SFR_OFFSET) #define _SFR_IO16(io_addr) ((io_addr) + __SFR_OFFSET) #define _SFR_IO_ADDR(sfr) ((sfr) - __SFR_OFFSET) #define _SFR_MEM_ADDR(sfr) (sfr) #define _SFR_IO_REG_P(sfr) ((sfr) < 0x40 + __SFR_OFFSET) #if (__SFR_OFFSET == 0x20) /* No need to use ?: operator, so works in assembler too. */ #define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr) #elif !defined(__ASSEMBLER__) #define _SFR_ADDR(sfr) (_SFR_IO_REG_P(sfr) ? (_SFR_IO_ADDR(sfr) + 0x20) : _SFR_MEM_ADDR(sfr)) #endif #else /* !_SFR_ASM_COMPAT */ #ifndef __SFR_OFFSET # if __AVR_ARCH__ >= 100 # define __SFR_OFFSET 0x00 # else # define __SFR_OFFSET 0x20 # endif #endif #define _SFR_MEM8(mem_addr) _MMIO_BYTE(mem_addr) #define _SFR_MEM16(mem_addr) _MMIO_WORD(mem_addr) #define _SFR_MEM32(mem_addr) _MMIO_DWORD(mem_addr) #define _SFR_IO8(io_addr) _MMIO_BYTE((io_addr) + __SFR_OFFSET) #define _SFR_IO16(io_addr) _MMIO_WORD((io_addr) + __SFR_OFFSET) #define _SFR_MEM_ADDR(sfr) ((uint16_t) &(sfr)) #define _SFR_IO_ADDR(sfr) (_SFR_MEM_ADDR(sfr) - __SFR_OFFSET) #define _SFR_IO_REG_P(sfr) (_SFR_MEM_ADDR(sfr) < 0x40 + __SFR_OFFSET) #define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr) #endif /* !_SFR_ASM_COMPAT */ #define _SFR_BYTE(sfr) _MMIO_BYTE(_SFR_ADDR(sfr)) #define _SFR_WORD(sfr) _MMIO_WORD(_SFR_ADDR(sfr)) #define _SFR_DWORD(sfr) _MMIO_DWORD(_SFR_ADDR(sfr)) /** \name Bit manipulation */ /*@{*/ /** \def _BV \ingroup avr_sfr \code #include \endcode Converts a bit number into a byte value. \note The bit shift is performed by the compiler which then inserts the result into the code. Thus, there is no run-time overhead when using _BV(). */ #define _BV(bit) (1 << (bit)) /*@}*/ #ifndef _VECTOR #define _VECTOR(N) __vector_ ## N #endif #ifndef __ASSEMBLER__ /** \name IO register bit manipulation */ /*@{*/ /** \def bit_is_set \ingroup avr_sfr \code #include \endcode Test whether bit \c bit in IO register \c sfr is set. This will return a 0 if the bit is clear, and non-zero if the bit is set. */ #define bit_is_set(sfr, bit) (_SFR_BYTE(sfr) & _BV(bit)) /** \def bit_is_clear \ingroup avr_sfr \code #include \endcode Test whether bit \c bit in IO register \c sfr is clear. This will return non-zero if the bit is clear, and a 0 if the bit is set. */ #define bit_is_clear(sfr, bit) (!(_SFR_BYTE(sfr) & _BV(bit))) /** \def loop_until_bit_is_set \ingroup avr_sfr \code #include \endcode Wait until bit \c bit in IO register \c sfr is set. */ #define loop_until_bit_is_set(sfr, bit) do { } while (bit_is_clear(sfr, bit)) /** \def loop_until_bit_is_clear \ingroup avr_sfr \code #include \endcode Wait until bit \c bit in IO register \c sfr is clear. */ #define loop_until_bit_is_clear(sfr, bit) do { } while (bit_is_set(sfr, bit)) /*@}*/ #endif /* !__ASSEMBLER__ */ #endif /* _SFR_DEFS_H_ */ avr-libc-1.8.0.orig/include/avr/iocan64.h0000644000000000000000000000655111732702554014710 0ustar /* Copyright (c) 2004,2005, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iocan64.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* iocan64.h - definitions for CAN64 */ #ifndef _AVR_IOCAN64_H_ #define _AVR_IOCAN64_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x10FF /* Last On-Chip SRAM Location */ #define XRAMEND 0xFFFF #define E2END 0x07FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x81 #endif /* _AVR_IOCAN64_H_ */ avr-libc-1.8.0.orig/include/avr/wdt.h0000644000000000000000000003325111732702554014240 0ustar /* Copyright (c) 2002, 2004 Marek Michalkiewicz Copyright (c) 2005, 2006, 2007 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: wdt.h 2211 2011-02-14 14:04:25Z aboyapati $ */ /* avr/wdt.h - macros for AVR watchdog timer */ #ifndef _AVR_WDT_H_ #define _AVR_WDT_H_ #include #include /** \file */ /** \defgroup avr_watchdog : Watchdog timer handling \code #include \endcode This header file declares the interface to some inline macros handling the watchdog timer present in many AVR devices. In order to prevent the watchdog timer configuration from being accidentally altered by a crashing application, a special timed sequence is required in order to change it. The macros within this header file handle the required sequence automatically before changing any value. Interrupts will be disabled during the manipulation. \note Depending on the fuse configuration of the particular device, further restrictions might apply, in particular it might be disallowed to turn off the watchdog timer. Note that for newer devices (ATmega88 and newer, effectively any AVR that has the option to also generate interrupts), the watchdog timer remains active even after a system reset (except a power-on condition), using the fastest prescaler value (approximately 15 ms). It is therefore required to turn off the watchdog early during program startup, the datasheet recommends a sequence like the following: \code #include #include uint8_t mcusr_mirror __attribute__ ((section (".noinit"))); void get_mcusr(void) \ __attribute__((naked)) \ __attribute__((section(".init3"))); void get_mcusr(void) { mcusr_mirror = MCUSR; MCUSR = 0; wdt_disable(); } \endcode Saving the value of MCUSR in \c mcusr_mirror is only needed if the application later wants to examine the reset source, but in particular, clearing the watchdog reset flag before disabling the watchdog is required, according to the datasheet. */ /** \ingroup avr_watchdog Reset the watchdog timer. When the watchdog timer is enabled, a call to this instruction is required before the timer expires, otherwise a watchdog-initiated device reset will occur. */ #define wdt_reset() __asm__ __volatile__ ("wdr") #if defined(WDP3) # define _WD_PS3_MASK _BV(WDP3) #else # define _WD_PS3_MASK 0x00 #endif #if defined(WDTCSR) # define _WD_CONTROL_REG WDTCSR #else # define _WD_CONTROL_REG WDTCR #endif #if defined(WDTOE) #define _WD_CHANGE_BIT WDTOE #else #define _WD_CHANGE_BIT WDCE #endif /** \ingroup avr_watchdog Enable the watchdog timer, configuring it for expiry after \c timeout (which is a combination of the \c WDP0 through \c WDP2 bits to write into the \c WDTCR register; For those devices that have a \c WDTCSR register, it uses the combination of the \c WDP0 through \c WDP3 bits). See also the symbolic constants \c WDTO_15MS et al. */ #if defined(__AVR_ATxmega16A4__) \ || defined(__AVR_ATxmega16D4__) \ || defined(__AVR_ATxmega32A4__) \ || defined(__AVR_ATxmega32D4__) \ || defined(__AVR_ATxmega64A1U__) \ || defined(__AVR_ATxmega64A3__) \ || defined(__AVR_ATxmega64D3__) \ || defined(__AVR_ATxmega128A1__) \ || defined(__AVR_ATxmega128A1U__) \ || defined(__AVR_ATxmega128A3__) \ || defined(__AVR_ATxmega128D3__) \ || defined(__AVR_ATxmega192A3__) \ || defined(__AVR_ATxmega192D3__) \ || defined(__AVR_ATxmega256A3__) \ || defined(__AVR_ATxmega256D3__) \ || defined(__AVR_ATxmega256A3B__) /* wdt_enable(WDT_PER_8KCLK_gc); */ #define wdt_enable(value) \ __asm__ __volatile__ ( \ "in __tmp_reg__, %0" "\n\t" \ "out %1, %3" "\n\t" \ "sts %2, %4" "\n\t" \ "wdr" "\n\t" \ "out %0, __tmp_reg__" "\n\t" \ : \ : "M" (_SFR_MEM_ADDR(RAMPD)), \ "M" (_SFR_MEM_ADDR(CCP)), \ "M" (_SFR_MEM_ADDR(WDT_CTRL)), \ "r" ((uint8_t)0xD8), \ "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | value)) \ : "r0" \ ) #elif defined(__AVR_AT90CAN32__) \ || defined(__AVR_AT90CAN64__) \ || defined(__AVR_AT90CAN128__) \ || defined(__AVR_AT90PWM1__) \ || defined(__AVR_AT90PWM2__) \ || defined(__AVR_AT90PWM216__) \ || defined(__AVR_AT90PWM2B__) \ || defined(__AVR_AT90PWM3__) \ || defined(__AVR_AT90PWM316__) \ || defined(__AVR_AT90PWM3B__) \ || defined(__AVR_AT90PWM81__) \ || defined(__AVR_AT90USB1286__) \ || defined(__AVR_AT90USB1287__) \ || defined(__AVR_AT90USB162__) \ || defined(__AVR_AT90USB646__) \ || defined(__AVR_AT90USB647__) \ || defined(__AVR_AT90USB82__) \ || defined(__AVR_ATmega1280__) \ || defined(__AVR_ATmega1281__) \ || defined(__AVR_ATmega1284P__) \ || defined(__AVR_ATmega128RFA1__) \ || defined(__AVR_ATmega164__) \ || defined(__AVR_ATmega164A__) \ || defined(__AVR_ATmega164P__) \ || defined(__AVR_ATmega165__) \ || defined(__AVR_ATmega165A__) \ || defined(__AVR_ATmega165P__) \ || defined(__AVR_ATmega168__) \ || defined(__AVR_ATmega168A__) \ || defined(__AVR_ATmega168P__) \ || defined(__AVR_ATmega169__) \ || defined(__AVR_ATmega169A__) \ || defined(__AVR_ATmega169P__) \ || defined(__AVR_ATmega169PA__) \ || defined(__AVR_ATmega16HVA__) \ || defined(__AVR_ATmega16HVA2__) \ || defined(__AVR_ATmega16HVB__) \ || defined(__AVR_ATmega16HVBREVB__) \ || defined(__AVR_ATmega16M1__) \ || defined(__AVR_ATmega16U2__) \ || defined(__AVR_ATmega16U4__) \ || defined(__AVR_ATmega2560__) \ || defined(__AVR_ATmega2561__) \ || defined(__AVR_ATmega324__) \ || defined(__AVR_ATmega324A__) \ || defined(__AVR_ATmega324P__) \ || defined(__AVR_ATmega324PA__) \ || defined(__AVR_ATmega325__) \ || defined(__AVR_ATmega325A__) \ || defined(__AVR_ATmega325P__) \ || defined(__AVR_ATmega3250__) \ || defined(__AVR_ATmega3250A__) \ || defined(__AVR_ATmega3250P__) \ || defined(__AVR_ATmega328__) \ || defined(__AVR_ATmega328P__) \ || defined(__AVR_ATmega329__) \ || defined(__AVR_ATmega329A__) \ || defined(__AVR_ATmega329P__) \ || defined(__AVR_ATmega329PA__) \ || defined(__AVR_ATmega3290__) \ || defined(__AVR_ATmega3290A__) \ || defined(__AVR_ATmega3290P__) \ || defined(__AVR_ATmega32C1__) \ || defined(__AVR_ATmega32HVB__) \ || defined(__AVR_ATmega32HVBREVB__) \ || defined(__AVR_ATmega32M1__) \ || defined(__AVR_ATmega32U2__) \ || defined(__AVR_ATmega32U4__) \ || defined(__AVR_ATmega32U6__) \ || defined(__AVR_ATmega406__) \ || defined(__AVR_ATmega48__) \ || defined(__AVR_ATmega48A__) \ || defined(__AVR_ATmega48P__) \ || defined(__AVR_ATmega640__) \ || defined(__AVR_ATmega644__) \ || defined(__AVR_ATmega644A__) \ || defined(__AVR_ATmega644P__) \ || defined(__AVR_ATmega644PA__) \ || defined(__AVR_ATmega645__) \ || defined(__AVR_ATmega645A__) \ || defined(__AVR_ATmega645P__) \ || defined(__AVR_ATmega6450__) \ || defined(__AVR_ATmega6450A__) \ || defined(__AVR_ATmega6450P__) \ || defined(__AVR_ATmega649__) \ || defined(__AVR_ATmega649A__) \ || defined(__AVR_ATmega6490__) \ || defined(__AVR_ATmega6490A__) \ || defined(__AVR_ATmega6490P__) \ || defined(__AVR_ATmega649P__) \ || defined(__AVR_ATmega64C1__) \ || defined(__AVR_ATmega64HVE__) \ || defined(__AVR_ATmega64M1__) \ || defined(__AVR_ATmega88__) \ || defined(__AVR_ATmega88A__) \ || defined(__AVR_ATmega88P__) \ || defined(__AVR_ATmega88PA__) \ || defined(__AVR_ATmega8HVA__) \ || defined(__AVR_ATmega8U2__) \ || defined(__AVR_ATtiny48__) \ || defined(__AVR_ATtiny88__) \ || defined(__AVR_ATtiny87__) \ || defined(__AVR_ATtiny167__) \ || defined(__AVR_AT90SCR100__) \ || defined(__AVR_ATA6289__) /* Use STS instruction. */ #define wdt_enable(value) \ __asm__ __volatile__ ( \ "in __tmp_reg__,__SREG__" "\n\t" \ "cli" "\n\t" \ "wdr" "\n\t" \ "sts %0,%1" "\n\t" \ "out __SREG__,__tmp_reg__" "\n\t" \ "sts %0,%2" "\n\t" \ : /* no outputs */ \ : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \ "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \ "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \ _BV(WDE) | (value & 0x07)) ) \ : "r0" \ ) #define wdt_disable() \ __asm__ __volatile__ ( \ "in __tmp_reg__, __SREG__" "\n\t" \ "cli" "\n\t" \ "sts %0, %1" "\n\t" \ "sts %0, __zero_reg__" "\n\t" \ "out __SREG__,__tmp_reg__" "\n\t" \ : /* no outputs */ \ : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \ "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \ : "r0" \ ) #else /* Use OUT instruction. */ #define wdt_enable(value) \ __asm__ __volatile__ ( \ "in __tmp_reg__,__SREG__" "\n\t" \ "cli" "\n\t" \ "wdr" "\n\t" \ "out %0,%1" "\n\t" \ "out __SREG__,__tmp_reg__" "\n\t" \ "out %0,%2" \ : /* no outputs */ \ : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \ "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \ _BV(WDE) | (value & 0x07)) ) \ : "r0" \ ) /** \ingroup avr_watchdog Disable the watchdog timer, if possible. This attempts to turn off the Enable bit in the watchdog control register. See the datasheet for details. */ #define wdt_disable() \ __asm__ __volatile__ ( \ "in __tmp_reg__, __SREG__" "\n\t" \ "cli" "\n\t" \ "out %0, %1" "\n\t" \ "out %0, __zero_reg__" "\n\t" \ "out __SREG__,__tmp_reg__" "\n\t" \ : /* no outputs */ \ : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \ : "r0" \ ) #endif /** \ingroup avr_watchdog Symbolic constants for the watchdog timeout. Since the watchdog timer is based on a free-running RC oscillator, the times are approximate only and apply to a supply voltage of 5 V. At lower supply voltages, the times will increase. For older devices, the times will be as large as three times when operating at Vcc = 3 V, while the newer devices (e. g. ATmega128, ATmega8) only experience a negligible change. Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms, 500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.) Symbolic constants are formed by the prefix \c WDTO_, followed by the time. Example that would select a watchdog timer expiry of approximately 500 ms: \code wdt_enable(WDTO_500MS); \endcode */ #define WDTO_15MS 0 /** \ingroup avr_watchdog See \c WDT0_15MS */ #define WDTO_30MS 1 /** \ingroup avr_watchdog See \c WDT0_15MS */ #define WDTO_60MS 2 /** \ingroup avr_watchdog See \c WDT0_15MS */ #define WDTO_120MS 3 /** \ingroup avr_watchdog See \c WDT0_15MS */ #define WDTO_250MS 4 /** \ingroup avr_watchdog See \c WDT0_15MS */ #define WDTO_500MS 5 /** \ingroup avr_watchdog See \c WDT0_15MS */ #define WDTO_1S 6 /** \ingroup avr_watchdog See \c WDT0_15MS */ #define WDTO_2S 7 #if defined(__DOXYGEN__) || defined(WDP3) /** \ingroup avr_watchdog See \c WDT0_15MS Note: This is only available on the ATtiny2313, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega48, ATmega88, ATmega168, ATmega48P, ATmega88P, ATmega168P, ATmega328P, ATmega164P, ATmega324P, ATmega644P, ATmega644, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega8HVA, ATmega16HVA, ATmega32HVB, ATmega406, ATmega1284P, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90USB82, AT90USB162, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATtiny48, ATtiny88. */ #define WDTO_4S 8 /** \ingroup avr_watchdog See \c WDT0_15MS Note: This is only available on the ATtiny2313, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, ATmega48, ATmega88, ATmega168, ATmega48P, ATmega88P, ATmega168P, ATmega328P, ATmega164P, ATmega324P, ATmega644P, ATmega644, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega8HVA, ATmega16HVA, ATmega32HVB, ATmega406, ATmega1284P, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90USB82, AT90USB162, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATtiny48, ATtiny88. */ #define WDTO_8S 9 #endif /* defined(__DOXYGEN__) || defined(WDP3) */ #endif /* _AVR_WDT_H_ */ avr-libc-1.8.0.orig/include/avr/iom168.h0000644000000000000000000000727311732702554014472 0ustar /* Copyright (c) 2004, Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom168.h 2115 2010-04-05 23:19:53Z arcanum $ */ #ifndef _AVR_IOM168_H_ #define _AVR_IOM168_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 128 #define RAMSTART (0x100) #define RAMEND 0x4FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x06 #endif /* _AVR_IOM168_H_ */ avr-libc-1.8.0.orig/include/avr/iom16hva.h0000644000000000000000000000501111732702554015065 0ustar /* Copyright (c) 2007, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* iom16hva.h - definitions for ATmega16HVA. */ #ifndef _AVR_IOM16HVA_H_ #define _AVR_IOM16HVA_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x2FF #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_SUT0 (unsigned char)~_BV(0) #define FUSE_SUT1 (unsigned char)~_BV(1) #define FUSE_SUT2 (unsigned char)~_BV(2) #define FUSE_SELFPRGEN (unsigned char)~_BV(3) #define FUSE_DWEN (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_EESAVE (unsigned char)~_BV(6) #define FUSE_WDTON (unsigned char)~_BV(7) #define FUSE_DEFAULT (FUSE_SPIEN) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x0C #endif /* _AVR_IOM16HVA_H_ */ avr-libc-1.8.0.orig/include/avr/iousb1286.h0000644000000000000000000000661311732702554015106 0ustar /* Copyright (c) 2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iousb1286.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/iousb1286.h - definitions for AT90USB1286 */ #ifndef _AVR_AT90USB1286_H_ #define _AVR_AT90USB1286_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x20FF #define XRAMEND 0xFFFF #define E2END 0xFFF #define E2PAGESIZE 8 #define FLASHEND 0x1FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_HWBE (unsigned char)~_BV(3) #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x82 #endif /* _AVR_AT90USB1286_H_ */ avr-libc-1.8.0.orig/include/avr/iotn84.h0000644000000000000000000000616311732702554014571 0ustar /* Copyright (c) 2005, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn84.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iotn84.h - definitions for ATtiny84 */ #ifndef _AVR_IOTN84_H_ #define _AVR_IOTN84_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x60) #define RAMEND 0x25F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define FUSE_HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x0C #endif /* _AVR_IOTN84_H_ */ avr-libc-1.8.0.orig/include/avr/iox64a3.h0000644000000000000000000111150111732702554014633 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox64a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox64a3.h - definitions for ATxmega64A3 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox64a3.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega64A3_H_ #define _AVR_ATxmega64A3_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* JTAG User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t GAINCAL; /* Gain Calibration */ register8_t OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* ADCB - Analog to Digital Converter B */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) #define ADCB_EVCTRL _SFR_MEM8(0x0243) #define ADCB_PRESCALER _SFR_MEM8(0x0244) #define ADCB_INTFLAGS _SFR_MEM8(0x0246) #define ADCB_CAL _SFR_MEM16(0x024C) #define ADCB_CH0RES _SFR_MEM16(0x0250) #define ADCB_CH1RES _SFR_MEM16(0x0252) #define ADCB_CH2RES _SFR_MEM16(0x0254) #define ADCB_CH3RES _SFR_MEM16(0x0256) #define ADCB_CMP _SFR_MEM16(0x0258) #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_GAINCAL _SFR_MEM8(0x0328) #define DACB_OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* TCE1 - Timer/Counter E1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) #define TCE1_CTRLD _SFR_MEM8(0x0A43) #define TCE1_CTRLE _SFR_MEM8(0x0A44) #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) #define TCE1_TEMP _SFR_MEM8(0x0A4F) #define TCE1_CNT _SFR_MEM16(0x0A60) #define TCE1_PER _SFR_MEM16(0x0A66) #define TCE1_CCA _SFR_MEM16(0x0A68) #define TCE1_CCB _SFR_MEM16(0x0A6A) #define TCE1_PERBUF _SFR_MEM16(0x0A76) #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) #define USARTE1_CTRLB _SFR_MEM8(0x0AB4) #define USARTE1_CTRLC _SFR_MEM8(0x0AB5) #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /* HIRESF - High-Resolution Extension F */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) /* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) #define USARTF1_CTRLB _SFR_MEM8(0x0BB4) #define USARTF1_CTRLC _SFR_MEM8(0x0BB5) #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) /* SPIF - Serial Peripheral Interface F */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) #define SPIF_DATA _SFR_MEM8(0x0BC3) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ #define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ #define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ #define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ #define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ #define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ #define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ #define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ #define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ #define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ #define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ #define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ #define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ #define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ #define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ #define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ #define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ #define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ #define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ #define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* ACB interrupt vectors */ #define ACB_AC0_vect_num 36 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ #define ACB_AC1_vect_num 37 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ #define ACB_ACW_vect_num 38 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ /* ADCB interrupt vectors */ #define ADCB_CH0_vect_num 39 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ #define ADCB_CH1_vect_num 40 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ #define ADCB_CH2_vect_num 41 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ #define ADCB_CH3_vect_num 42 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* SPIE interrupt vectors */ #define SPIE_INT_vect_num 57 #define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* USARTE1 interrupt vectors */ #define USARTE1_RXC_vect_num 61 #define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ #define USARTE1_DRE_vect_num 62 #define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ #define USARTE1_TXC_vect_num 63 #define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ /* USARTF0 interrupt vectors */ #define USARTF0_RXC_vect_num 119 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ #define USARTF0_DRE_vect_num 120 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ #define USARTF0_TXC_vect_num 121 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (122 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (69632) #define PROGMEM_PAGE_SIZE (256) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (65536) #define APP_SECTION_PAGE_SIZE (256) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x0F000) #define APPTABLE_SECTION_SIZE (4096) #define APPTABLE_SECTION_PAGE_SIZE (256) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x10000) #define BOOT_SECTION_SIZE (4096) #define BOOT_SECTION_PAGE_SIZE (256) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (12288) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (4096) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (256) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ #define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ #define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ #define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ #define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ #define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ #define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ #define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x42 #endif /* _AVR_ATxmega64A3_H_ */ avr-libc-1.8.0.orig/include/avr/iom16u2.h0000644000000000000000000005013311732702554014642 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16u2.h 2240 2011-05-09 22:18:18Z arcanum $ */ /* avr/iom16u2.h - definitions for ATmega16U2 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16u2.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega16U2_H_ #define _AVR_ATmega16U2_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define OCF1C 3 #define ICF1 5 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define INTF4 4 #define INTF5 5 #define INTF6 6 #define INTF7 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define INT4 4 #define INT5 5 #define INT6 6 #define INT7 7 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLP0 2 #define PLLP1 3 #define PLLP2 4 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define DWDR _SFR_IO8(0x31) #define DWDR0 0 #define DWDR1 1 #define DWDR2 2 #define DWDR3 3 #define DWDR4 4 #define DWDR5 5 #define DWDR6 6 #define DWDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define USBRF 5 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define EIND _SFR_IO8(0x3C) #define EIND0 0 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define WDTCKD _SFR_MEM8(0x62) #define WCLKD0 0 #define WCLKD1 1 #define WDEWIE 2 #define WDEWIF 3 #define REGCR _SFR_MEM8(0x63) #define REGDIS 0 #define PRR0 _SFR_MEM8(0x64) #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRR1 _SFR_MEM8(0x65) #define PRUSART1 0 #define PRUSB 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define EICRB _SFR_MEM8(0x6A) #define ISC40 0 #define ISC41 1 #define ISC50 2 #define ISC51 3 #define ISC60 4 #define ISC61 5 #define ISC70 6 #define ISC71 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define OCIE1C 3 #define ICIE1 5 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1C0 2 #define COM1C1 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1C 5 #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CL0 0 #define OCR1CL1 1 #define OCR1CL2 2 #define OCR1CL3 3 #define OCR1CL4 4 #define OCR1CL5 5 #define OCR1CL6 6 #define OCR1CL7 7 #define OCR1CH _SFR_MEM8(0x8D) #define OCR1CH0 0 #define OCR1CH1 1 #define OCR1CH2 2 #define OCR1CH3 3 #define OCR1CH4 4 #define OCR1CH5 5 #define OCR1CH6 6 #define OCR1CH7 7 #define UCSR1A _SFR_MEM8(0xC8) #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 #define UCSR1B _SFR_MEM8(0xC9) #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 #define UCSR1C _SFR_MEM8(0xCA) #define UCPOL1 0 #define UCSZ10 1 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 #define UCSR1D _SFR_MEM8(0xCB) #define RTSEN 0 #define CTSEN 1 #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1_0 0 #define UBRR1_1 1 #define UBRR1_2 2 #define UBRR1_3 3 #define UBRR1_4 4 #define UBRR1_5 5 #define UBRR1_6 6 #define UBRR1_7 7 #define UBRR1H _SFR_MEM8(0xCD) #define UBRR1_8 0 #define UBRR1_9 1 #define UBRR1_10 2 #define UBRR1_11 3 #define UDR1 _SFR_MEM8(0xCE) #define UDR1_0 0 #define UDR1_1 1 #define UDR1_2 2 #define UDR1_3 3 #define UDR1_4 4 #define UDR1_5 5 #define UDR1_6 6 #define UDR1_7 7 #define CLKSEL0 _SFR_MEM8(0xD0) #define CLKS 0 #define EXTE 2 #define RCE 3 #define EXSUT0 4 #define EXSUT1 5 #define RCSUT0 6 #define RCSUT1 7 #define CLKSEL1 _SFR_MEM8(0xD1) #define EXCKSEL0 0 #define EXCKSEL1 1 #define EXCKSEL2 2 #define EXCKSEL3 3 #define RCCKSEL0 4 #define RCCKSEL1 5 #define RCCKSEL2 6 #define RCCKSEL3 7 #define CLKSTA _SFR_MEM8(0xD2) #define EXTON 0 #define RCON 1 #define USBCON _SFR_MEM8(0xD8) #define FRZCLK 5 #define USBE 7 #define UDCON _SFR_MEM8(0xE0) #define DETACH 0 #define RMWKUP 1 #define RSTCPU 2 #define UDINT _SFR_MEM8(0xE1) #define SUSPI 0 #define SOFI 2 #define EORSTI 3 #define WAKEUPI 4 #define EORSMI 5 #define UPRSMI 6 #define UDIEN _SFR_MEM8(0xE2) #define SUSPE 0 #define SOFE 2 #define EORSTE 3 #define WAKEUPE 4 #define EORSME 5 #define UPRSME 6 #define UDADDR _SFR_MEM8(0xE3) #define UADD0 0 #define UADD1 1 #define UADD2 2 #define UADD3 3 #define UADD4 4 #define UADD5 5 #define UADD6 6 #define ADDEN 7 #define UDFNUM _SFR_MEM16(0xE4) #define UDFNUML _SFR_MEM8(0xE4) #define FNUM0 0 #define FNUM1 1 #define FNUM2 2 #define FNUM3 3 #define FNUM4 4 #define FNUM5 5 #define FNUM6 6 #define FNUM7 7 #define UDFNUMH _SFR_MEM8(0xE5) #define FNUM8 0 #define FNUM9 1 #define FNUM10 2 #define UDMFN _SFR_MEM8(0xE6) #define FNCERR 4 #define UEINTX _SFR_MEM8(0xE8) #define TXINI 0 #define STALLEDI 1 #define RXOUTI 2 #define RXSTPI 3 #define NAKOUTI 4 #define RWAL 5 #define NAKINI 6 #define FIFOCON 7 #define UENUM _SFR_MEM8(0xE9) #define EPNUM0 0 #define EPNUM1 1 #define EPNUM2 2 #define UERST _SFR_MEM8(0xEA) #define EPRST0 0 #define EPRST1 1 #define EPRST2 2 #define EPRST3 3 #define EPRST4 4 #define UECONX _SFR_MEM8(0xEB) #define EPEN 0 #define RSTDT 3 #define STALLRQC 4 #define STALLRQ 5 #define UECFG0X _SFR_MEM8(0xEC) #define EPDIR 0 #define EPTYPE0 6 #define EPTYPE1 7 #define UECFG1X _SFR_MEM8(0xED) #define ALLOC 1 #define EPBK0 2 #define EPBK1 3 #define EPSIZE0 4 #define EPSIZE1 5 #define EPSIZE2 6 #define UESTA0X _SFR_MEM8(0xEE) #define NBUSYBK0 0 #define NBUSYBK1 1 #define DTSEQ0 2 #define DTSEQ1 3 #define UNDERFI 5 #define OVERFI 6 #define CFGOK 7 #define UESTA1X _SFR_MEM8(0xEF) #define CURRBK0 0 #define CURRBK1 1 #define CTRLDIR 2 #define UEIENX _SFR_MEM8(0xF0) #define TXINE 0 #define STALLEDE 1 #define RXOUTE 2 #define RXSTPE 3 #define NAKOUTE 4 #define NAKINE 6 #define FLERRE 7 #define UEDATX _SFR_MEM8(0xF1) #define DAT0 0 #define DAT1 1 #define DAT2 2 #define DAT3 3 #define DAT4 4 #define DAT5 5 #define DAT6 6 #define DAT7 7 #define UEBCLX _SFR_MEM8(0xF2) #define BYCT0 0 #define BYCT1 1 #define BYCT2 2 #define BYCT3 3 #define BYCT4 4 #define BYCT5 5 #define BYCT6 6 #define BYCT7 7 #define UEINT _SFR_MEM8(0xF4) #define EPINT0 0 #define EPINT1 1 #define EPINT2 2 #define EPINT3 3 #define EPINT4 4 #define PS2CON _SFR_MEM8(0xFA) #define PS2EN 0 #define UPOE _SFR_MEM8(0xFB) #define DMI 0 #define DPI 1 #define DATAI 2 #define SCKI 3 #define UPDRV0 4 #define UPDRV1 5 #define UPWE0 6 #define UPWE1 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ #define PCINT0_vect_num 9 #define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 10 #define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */ #define USB_GEN_vect_num 11 #define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */ #define USB_COM_vect_num 12 #define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */ #define WDT_vect_num 13 #define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */ #define TIMER1_CAPT_vect_num 14 #define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ #define TIMER1_COMPA_vect_num 15 #define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ #define TIMER0_COMPA_vect_num 19 #define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 20 #define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 21 #define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 22 #define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */ #define USART1_RX_vect_num 23 #define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */ #define USART1_UDRE_vect_num 24 #define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */ #define USART1_TX_vect_num 25 #define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */ #define ANALOG_COMP_vect_num 26 #define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */ #define EE_READY_vect_num 27 #define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ #define SPM_READY_vect_num 28 #define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */ #define TIMER1_COMPB_vect_num 16 #define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */ #define TIMER1_COMPC_vect_num 17 #define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */ #define TIMER1_OVF_vect_num 18 #define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (29 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (512) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x3FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */ #define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x89 /* Device Pin Definitions */ #endif /* _AVR_ATmega16U2_H_ */ avr-libc-1.8.0.orig/include/avr/iotn13a.h0000644000000000000000000002110011732702554014706 0ustar /* Copyright (c) 2008 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn13a.h 1955 2009-04-28 08:51:16Z arcanum $ */ /* avr/iotn13a.h - definitions for ATtiny13 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn13a.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATTINY13A_H_ #define _AVR_ATTINY13A_H_ 1 /* Registers and associated bit numbers. */ #define ADCSRB _SFR_IO8(0x03) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x05) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define ADLAR 5 #define REFS0 6 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define DIDR0 _SFR_IO8(0x14) #define AIN0D 0 #define AIN1D 1 #define ADC1D 2 #define ADC3D 3 #define ADC2D 4 #define ADC0D 5 #define PCMSK _SFR_IO8(0x15) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define PORTB _SFR_IO8(0x18) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x1D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEARL _SFR_IO8(0x1E) #define EEAR _SFR_IO8(0x1E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDTIE 6 #define WDTIF 7 #define PRR _SFR_IO8(0x25) #define PRADC 0 #define PRTIM0 1 #define CLKPR _SFR_IO8(0x26) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define GTCCR _SFR_IO8(0x28) #define PSR10 0 #define TSM 7 #define OCR0B _SFR_IO8(0x29) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define DWDR _SFR_IO8(0x2E) #define DWDR0 0 #define DWDR1 1 #define DWDR2 2 #define DWDR3 3 #define DWDR4 4 #define DWDR5 5 #define DWDR6 6 #define DWDR7 7 #define TCCR0A _SFR_IO8(0x2F) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define BODCR _SFR_IO8(0x30) #define BPDSE 0 #define BPDS 1 #define OSCCAL _SFR_IO8(0x31) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define TCNT0 _SFR_IO8(0x32) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0B _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 #define OCR0A _SFR_IO8(0x36) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR0 _SFR_IO8(0x38) #define TOV0 1 #define OCF0A 2 #define OCF0B 3 #define TIMSK0 _SFR_IO8(0x39) #define TOIE0 1 #define OCIE0A 2 #define OCIE0B 3 #define GIFR _SFR_IO8(0x3A) #define PCIF 5 #define INTF0 6 #define GIMSK _SFR_IO8(0x3B) #define PCIE 5 #define INT0 6 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* External Interrupt Request 0 */ #define TIM0_OVF_vect_num 3 #define TIM0_OVF_vect _VECTOR(3) /* Timer/Counter0 Overflow */ #define EE_RDY_vect_num 4 #define EE_RDY_vect _VECTOR(4) /* EEPROM Ready */ #define ANA_COMP_vect_num 5 #define ANA_COMP_vect _VECTOR(5) /* Analog Comparator */ #define TIM0_COMPA_vect_num 6 #define TIM0_COMPA_vect _VECTOR(6) /* Timer/Counter Compare Match A */ #define TIM0_COMPB_vect_num 7 #define TIM0_COMPB_vect _VECTOR(7) /* Timer/Counter Compare Match B */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Watchdog Time-out */ #define ADC_vect_num 9 #define ADC_vect _VECTOR(9) /* ADC Conversion Complete */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (10 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (32) #define RAMSTART (0x60) #define RAMSIZE (64) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND RAMEND #define E2END (64 - 1) #define E2PAGESIZE (4) #define FLASHEND (1024 - 1) /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ #define FUSE_CKDIV8 (unsigned char)~_BV(4) /* Start up with system clock divided by 8 */ #define FUSE_WDTON (unsigned char)~_BV(5) /* Watch dog timer always on */ #define FUSE_EESAVE (unsigned char)~_BV(6) /* Keep EEprom contents during chip erase */ #define FUSE_SPIEN (unsigned char)~_BV(7) /* SPI programming enable */ #define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Enable BOD and select level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Enable BOD and select level */ #define FUSE_DWEN (unsigned char)~_BV(3) /* DebugWire Enable */ #define FUSE_SELFPRGEN (unsigned char)~_BV(4) /* Self Programming Enable */ #define HFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x07 #endif /* _AVR_ATTINY13A_H_ */ avr-libc-1.8.0.orig/include/avr/iotn85.h0000644000000000000000000000615311732702554014571 0ustar /* Copyright (c) 2005, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn85.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iotn85.h - definitions for ATtiny85 */ #ifndef _AVR_IOTN85_H_ #define _AVR_IOTN85_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x60) #define RAMEND 0x25F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x0B #endif /* _AVR_IOTN85_H_ */ avr-libc-1.8.0.orig/include/avr/iom48p.h0000644000000000000000000004425611732702554014571 0ustar /* Copyright (c) 2007 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom48p.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iom48p.h - definitions for ATmega48P. */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom48p.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOM48P_H_ #define _AVR_IOM48P_H_ 1 /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 /* Only valid for ATmega88P-168P-328P */ /* EEARH _SFR_IO8(0x22) */ #define EEPROM_REG_LOCATIONS 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define PUD 4 #define BODSE 5 #define BODS 6 #define SPMCSR _SFR_IO8(0x37) #define SELFPRGEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 0 #define TWAM1 1 #define TWAM2 2 #define TWAM3 3 #define TWAM4 4 #define TWAM5 5 #define TWAM6 6 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCPHA0 1 #define UCSZ01 2 #define UDORD0 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL01 7 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0_0 0 #define UBRR0_1 1 #define UBRR0_2 2 #define UBRR0_3 3 #define UBRR0_4 4 #define UBRR0_5 5 #define UBRR0_6 6 #define UBRR0_7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR0_8 0 #define UBRR0_9 1 #define UBRR0_10 2 #define UBRR0_11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR0_0 0 #define UDR0_1 1 #define UDR0_2 2 #define UDR0_3 3 #define UDR0_4 4 #define UDR0_5 5 #define UDR0_6 6 #define UDR0_7 7 /* Interrupt Vectors */ /* Interrupt Vector 0 is the reset vector. */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ #define PCINT2_vect_num 5 #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ #define WDT_vect_num 6 #define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 7 #define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 8 #define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ #define TIMER2_OVF_vect_num 9 #define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 10 #define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 11 #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 12 #define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ #define TIMER0_OVF_vect_num 16 #define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ #define SPI_STC_vect_num 17 #define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ #define USART_RX_vect_num 18 #define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ #define USART_UDRE_vect_num 19 #define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ #define USART_TX_vect_num 20 #define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ #define ADC_vect_num 21 #define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ #define EE_READY_vect_num 22 #define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ #define TWI_vect_num 24 #define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ #define SPM_READY_vect_num 25 #define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ #define _VECTORS_SIZE (26 * 2) /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x100) #define RAMEND 0x2FF /* Last On-Chip SRAM Location */ #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 4 #define FLASHEND 0xFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x0A #endif /* _AVR_IOM48P_H_ */ avr-libc-1.8.0.orig/include/avr/iox16a4.h0000644000000000000000000106553311732702554014646 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox16a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox16a4.h - definitions for ATxmega16A4 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox16a4.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega16A4_H_ #define _AVR_ATxmega16A4_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t GAINCAL; /* Gain Calibration */ register8_t OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_GAINCAL _SFR_MEM8(0x0328) #define DACB_OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (94 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (20480) #define PROGMEM_PAGE_SIZE (256) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (16384) #define APP_SECTION_PAGE_SIZE (256) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x3000) #define APPTABLE_SECTION_SIZE (4096) #define APPTABLE_SECTION_PAGE_SIZE (256) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x4000) #define BOOT_SECTION_SIZE (4096) #define BOOT_SECTION_PAGE_SIZE (256) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (10240) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (1024) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (2048) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (1024) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (256) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x41 #endif /* _AVR_ATxmega16A4_H_ */ avr-libc-1.8.0.orig/include/avr/io8534.h0000644000000000000000000001133511732702554014374 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io8534.h 1873 2009-02-11 17:53:39Z arcanum $ */ /* avr/io8534.h - definitions for AT90C8534 */ #ifndef _AVR_IO8534_ #define _AVR_IO8534_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io8534.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* 0x00..0x03 reserved */ /* ADC Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and Status Register */ #define ADCSR _SFR_IO8(0x06) /* ADC Multiplexer Select Register */ #define ADMUX _SFR_IO8(0x07) /* 0x08..0x0F reserved */ /* General Interrupt Pin Register */ #define GIPR _SFR_IO8(0x10) /* 0x11..0x19 reserved */ /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* 0x20..0x2B reserved */ /* Timer/Counter1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter1 Control Register */ #define TCCR1 _SFR_IO8(0x2E) /* 0x2F..0x31 reserved */ /* Timer/Counter0 (8-bit) */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* 0x34 reserved */ /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* 0x36..0x37 reserved */ /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK Register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3C reserved */ /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ #define SIG_INTERRUPT0 _VECTOR(1) #define SIG_INTERRUPT1 _VECTOR(2) #define SIG_OVERFLOW1 _VECTOR(3) #define SIG_OVERFLOW0 _VECTOR(4) #define SIG_ADC _VECTOR(5) #define SIG_EEPROM_READY _VECTOR(6) #define _VECTORS_SIZE 14 /* Bit numbers */ /* GIMSK */ #define INT1 7 #define INT0 6 /* GIFR */ #define INTF1 7 #define INTF0 6 /* GIPR */ #define IPIN1 3 #define IPIN0 2 /* TIMSK */ #define TOIE1 2 #define TOIE0 0 /* TIFR */ #define TOV1 2 #define TOV0 0 /* MCUCR */ #define SE 6 #define SM 5 #define ISC1 2 #define ISC0 0 /* TCCR0 */ #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR1 */ #define CS12 2 #define CS11 1 #define CS10 0 /* PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Last memory addresses */ #define RAMEND 0x15F #define XRAMEND RAMEND #define E2END 0x1FF #define FLASHEND 0x1FFF #endif /* _AVR_IO8534_H_ */ avr-libc-1.8.0.orig/include/avr/iotn24a.h0000644000000000000000000004215411732702554014724 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn24a.h 2035 2009-11-02 02:44:17Z arcanum $ */ /* avr/iotn24a.h - definitions for ATtiny24A */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn24a.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny24A_H_ #define _AVR_ATtiny24A_H_ 1 /* Registers and associated bit numbers. */ #define PRR _SFR_IO8(0x00) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define DIDR0 _SFR_IO8(0x01) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define ADCSRB _SFR_IO8(0x03) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADLAR 4 #define ACME 6 #define BIN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x05) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define MUX5 5 #define REFS0 6 #define REFS1 7 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define TIFR1 _SFR_IO8(0x0B) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIMSK1 _SFR_IO8(0x0C) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define USICR _SFR_IO8(0x0D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x0E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x0F) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define USIBR _SFR_IO8(0x10) #define USIBR0 0 #define USIBR1 1 #define USIBR2 2 #define USIBR3 3 #define USIBR4 4 #define USIBR5 5 #define USIBR6 6 #define USIBR7 7 #define PCMSK0 _SFR_IO8(0x12) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define GPIOR0 _SFR_IO8(0x13) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x14) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x15) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x18) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x1D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x1F) #define EEAR8 0 #define PCMSK1 _SFR_IO8(0x20) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define WDTCSR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define TCCR1C _SFR_IO8(0x22) #define FOC1B 6 #define FOC1A 7 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define TSM 7 #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_IO8(0x25) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define CLKPR _SFR_IO8(0x26) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define DWDR _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_IO8(0x29) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_IO8(0x2B) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_IO8(0x2D) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define TCCR1B _SFR_IO8(0x2E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x2F) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR0A _SFR_IO8(0x30) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define OSCCAL _SFR_IO8(0x31) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define TCNT0 _SFR_IO8(0x32) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0B _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 #define OCR0A _SFR_IO8(0x36) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR0 _SFR_IO8(0x38) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIMSK0 _SFR_IO8(0x39) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define GIFR _SFR_IO8(0x3A) #define PCIF0 4 #define PCIF1 5 #define INTF0 6 #define GIMSK _SFR_IO8(0x3B) #define PCIE0 4 #define PCIE1 5 #define INT0 6 #define OCR0B _SFR_IO8(0x3C) #define OCR0_0 0 #define OCR0_1 1 #define OCR0_2 2 #define OCR0_3 3 #define OCR0_4 4 #define OCR0_5 5 #define OCR0_6 6 #define OCR0_7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define EXT_INT0_vect_num 1 #define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ #define WATCHDOG_vect_num 4 #define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ #define TIM1_CAPT_vect_num 5 #define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIM1_COMPA_vect_num 6 #define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIM1_COMPB_vect_num 7 #define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIM1_OVF_vect_num 8 #define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIM0_COMPA_vect_num 9 #define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ #define TIM0_COMPB_vect_num 10 #define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ #define TIM0_OVF_vect_num 11 #define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ #define ANA_COMP_vect_num 12 #define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ #define ADC_vect_num 13 #define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ #define EE_RDY_vect_num 14 #define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ #define USI_STR_vect_num 15 #define USI_STR_vect _VECTOR(15) /* USI START */ #define USI_OVF_vect_num 16 #define USI_OVF_vect _VECTOR(16) /* USI Overflow */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (17 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (32) #define RAMSTART (0x60) #define RAMSIZE (128) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x7F) #define E2PAGESIZE (4) #define FLASHEND (0x7FF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x0B /* Device Pin Definitions */ #define ADC4_DDR DDRA #define ADC4_PORT PORTA #define ADC4_PIN PINA #define ADC4_BIT 4 #define USCK_DDR DDRA #define USCK_PORT PORTA #define USCK_PIN PINA #define USCK_BIT 4 #define SCL_DDR DDRA #define SCL_PORT PORTA #define SCL_PIN PINA #define SCL_BIT 4 #define T1_DDR DDRA #define T1_PORT PORTA #define T1_PIN PINA #define T1_BIT 4 #define PCINT4_DDR DDRA #define PCINT4_PORT PORTA #define PCINT4_PIN PINA #define PCINT4_BIT 4 #define ADC3_DDR DDRA #define ADC3_PORT PORTA #define ADC3_PIN PINA #define ADC3_BIT 3 #define T0_DDR DDRA #define T0_PORT PORTA #define T0_PIN PINA #define T0_BIT 3 #define PCINT3_DDR DDRA #define PCINT3_PORT PORTA #define PCINT3_PIN PINA #define PCINT3_BIT 3 #define ADC2_DDR DDRA #define ADC2_PORT PORTA #define ADC2_PIN PINA #define ADC2_BIT 2 #define AIN1_DDR DDRA #define AIN1_PORT PORTA #define AIN1_PIN PINA #define AIN1_BIT 2 #define PCINT2_DDR DDRA #define PCINT2_PORT PORTA #define PCINT2_PIN PINA #define PCINT2_BIT 2 #define ADC1_DDR DDRA #define ADC1_PORT PORTA #define ADC1_PIN PINA #define ADC1_BIT 1 #define AIN0_DDR DDRA #define AIN0_PORT PORTA #define AIN0_PIN PINA #define AIN0_BIT 1 #define PCINT1_DDR DDRA #define PCINT1_PORT PORTA #define PCINT1_PIN PINA #define PCINT1_BIT 1 #define ADC0_DDR DDRA #define ADC0_PORT PORTA #define ADC0_PIN PINA #define ADC0_BIT 0 #define PCINT0_DDR DDRA #define PCINT0_PORT PORTA #define PCINT0_PIN PINA #define PCINT0_BIT 0 #define PCINT8_DDR DDRB #define PCINT8_PORT PORTB #define PCINT8_PIN PINB #define PCINT8_BIT 0 #define PCINT9_DDR DDRB #define PCINT9_PORT PORTB #define PCINT9_PIN PINB #define PCINT9_BIT 1 #define PCINT11_DDR DDRB #define PCINT11_PORT PORTB #define PCINT11_PIN PINB #define PCINT11_BIT 3 #define dW_DDR DDRB #define dW_PORT PORTB #define dW_PIN PINB #define dW_BIT 3 #define PCINT10_DDR DDRB #define PCINT10_PORT PORTB #define PCINT10_PIN PINB #define PCINT10_BIT 2 #define INT0_DDR DDRB #define INT0_PORT PORTB #define INT0_PIN PINB #define INT0_BIT 2 #define OC0A_DDR DDRB #define OC0A_PORT PORTB #define OC0A_PIN PINB #define OC0A_BIT 2 #define CKOUT_DDR DDRB #define CKOUT_PORT PORTB #define CKOUT_PIN PINB #define CKOUT_BIT 2 #define PCINT7_DDR DDRA #define PCINT7_PORT PORTA #define PCINT7_PIN PINA #define PCINT7_BIT 7 #define ICP1_DDR DDRA #define ICP1_PORT PORTA #define ICP1_PIN PINA #define ICP1_BIT 7 #define OC0B_DDR DDRA #define OC0B_PORT PORTA #define OC0B_PIN PINA #define OC0B_BIT 7 #define ADC7_DDR DDRA #define ADC7_PORT PORTA #define ADC7_PIN PINA #define ADC7_BIT 7 #define PCINT6_DDR DDRA #define PCINT6_PORT PORTA #define PCINT6_PIN PINA #define PCINT6_BIT 6 #define OC1A_DDR DDRA #define OC1A_PORT PORTA #define OC1A_PIN PINA #define OC1A_BIT 6 #define DI_DDR DDRA #define DI_PORT PORTA #define DI_PIN PINA #define DI_BIT 6 #define SDA_DDR DDRA #define SDA_PORT PORTA #define SDA_PIN PINA #define SDA_BIT 6 #define MOSI_DDR DDRA #define MOSI_PORT PORTA #define MOSI_PIN PINA #define MOSI_BIT 6 #define ADC6_DDR DDRA #define ADC6_PORT PORTA #define ADC6_PIN PINA #define ADC6_BIT 6 #define ADC5_DDR DDRA #define ADC5_PORT PORTA #define ADC5_PIN PINA #define ADC5_BIT 5 #define DO_DDR DDRA #define DO_PORT PORTA #define DO_PIN PINA #define DO_BIT 5 #define MISO_DDR DDRA #define MISO_PORT PORTA #define MISO_PIN PINA #define MISO_BIT 5 #define OC1B_DDR DDRA #define OC1B_PORT PORTA #define OC1B_PIN PINA #define OC1B_BIT 5 #define PCINT5_DDR DDRA #define PCINT5_PORT PORTA #define PCINT5_PIN PINA #define PCINT5_BIT 5 #endif /* _AVR_ATtiny24A_H_ */ avr-libc-1.8.0.orig/include/avr/iotn861a.h0000644000000000000000000005054511732702554015020 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn861a.h 2063 2009-11-18 22:06:28Z arcanum $ */ /* avr/iotn861a.h - definitions for ATtiny861A */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn861a.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny861A_H_ #define _AVR_ATtiny861A_H_ 1 /* Registers and associated bit numbers. */ #define TCCR1E _SFR_IO8(0x00) #define OC1OE0 0 #define OC1OE1 1 #define OC1OE2 2 #define OC1OE3 3 #define OC1OE4 4 #define OC1OE5 5 #define DIDR0 _SFR_IO8(0x01) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define AREFD 3 #define ADC3D 4 #define ADC4D 5 #define ADC5D 6 #define ADC6D 7 #define DIDR1 _SFR_IO8(0x02) #define ADC7D 4 #define ADC8D 5 #define ADC9D 6 #define ADC10D 7 #define ADCSRB _SFR_IO8(0x03) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define MUX5 3 #define REFS2 4 #define IPR 5 #define GSEL 6 #define BIN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x05) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define ACSRA _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACME 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define ACSRB _SFR_IO8(0x09) #define ACM0 0 #define ACM1 1 #define ACM2 2 #define HLEV 6 #define HSEL 7 #define GPIOR0 _SFR_IO8(0x0A) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x0B) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x0C) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define USICR _SFR_IO8(0x0D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x0E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x0F) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define USIBR _SFR_IO8(0x10) #define USIBR0 0 #define USIBR1 1 #define USIBR2 2 #define USIBR3 3 #define USIBR4 4 #define USIBR5 5 #define USIBR6 6 #define USIBR7 7 #define USIPP _SFR_IO8(0x11) #define USIPOS 0 #define OCR0B _SFR_IO8(0x12) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define OCR0A _SFR_IO8(0x13) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define TCNT0H _SFR_IO8(0x14) #define TCNT0H_0 0 #define TCNT0H_1 1 #define TCNT0H_2 2 #define TCNT0H_3 3 #define TCNT0H_4 4 #define TCNT0H_5 5 #define TCNT0H_6 6 #define TCNT0H_7 7 #define TCCR0A _SFR_IO8(0x15) #define WGM00 0 #define ACIC0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x1D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x1F) #define EEAR8 0 #define DWDR _SFR_IO8(0x20) #define DWDR0 0 #define DWDR1 1 #define DWDR2 2 #define DWDR3 3 #define DWDR4 4 #define DWDR5 5 #define DWDR6 6 #define DWDR7 7 #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define PCMSK1 _SFR_IO8(0x22) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK0 _SFR_IO8(0x23) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define DT1 _SFR_IO8(0x24) #define DT1L0 0 #define DT1L1 1 #define DT1L2 2 #define DT1L3 3 #define DT1H0 4 #define DT1H1 5 #define DT1H2 6 #define DT1H3 7 #define TC1H _SFR_IO8(0x25) #define TC18 0 #define TC19 1 #define TCCR1D _SFR_IO8(0x26) #define WGM10 0 #define WGM11 1 #define FPF1 2 #define FPAC1 3 #define FPES1 4 #define FPNC1 5 #define FPEN1 6 #define FPIE1 7 #define TCCR1C _SFR_IO8(0x27) #define PWM1D 0 #define FOC1D 1 #define COM1D0 2 #define COM1D1 3 #define COM1B0S 4 #define COM1B1S 5 #define COM1A0S 6 #define COM1A1S 7 #define CLKPR _SFR_IO8(0x28) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PCKE 2 #define LSM 7 #define OCR1D _SFR_IO8(0x2A) #define OCR1D0 0 #define OCR1D1 1 #define OCR1D2 2 #define OCR1D3 3 #define OCR1D4 4 #define OCR1D5 5 #define OCR1D6 6 #define OCR1D7 7 #define OCR1C _SFR_IO8(0x2B) #define OCR1C0 0 #define OCR1C1 1 #define OCR1C2 2 #define OCR1C3 3 #define OCR1C4 4 #define OCR1C5 5 #define OCR1C6 6 #define OCR1C7 7 #define OCR1B _SFR_IO8(0x2C) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define OCR1A _SFR_IO8(0x2D) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define TCNT1 _SFR_IO8(0x2E) #define TC1H_0 0 #define TC1H_1 1 #define TC1H_2 2 #define TC1H_3 3 #define TC1H_4 4 #define TC1H_5 5 #define TC1H_6 6 #define TC1H_7 7 #define TCCR1B _SFR_IO8(0x2F) #define CS10 0 #define CS11 1 #define CS12 2 #define CS13 3 #define DTPS10 4 #define DTPS11 5 #define PSR1 6 #define TCCR1A _SFR_IO8(0x30) #define PWM1B 0 #define PWM1A 1 #define FOC1B 2 #define FOC1A 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define OSCCAL _SFR_IO8(0x31) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define TCNT0L _SFR_IO8(0x32) #define TCNT0L_0 0 #define TCNT0L_1 1 #define TCNT0L_2 2 #define TCNT0L_3 3 #define TCNT0L_4 4 #define TCNT0L_5 5 #define TCNT0L_6 6 #define TCNT0L_7 7 #define TCCR0B _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define PSR0 3 #define TSM 4 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define BODSE 2 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 #define BODS 7 #define PRR _SFR_IO8(0x36) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR _SFR_IO8(0x38) #define ICF0 0 #define TOV0 1 #define TOV1 2 #define OCF0B 3 #define OCF0A 4 #define OCF1B 5 #define OCF1A 6 #define OCF1D 7 #define TIMSK _SFR_IO8(0x39) #define TICIE0 0 #define TOIE0 1 #define TOIE1 2 #define OCIE0B 3 #define OCIE0A 4 #define OCIE1B 5 #define OCIE1A 6 #define OCIE1D 7 #define GIFR _SFR_IO8(0x3A) #define PCIF 5 #define INTF0 6 #define INTF1 7 #define GIMSK _SFR_IO8(0x3B) #define PCIE0 4 #define PCIE1 5 #define INT0 6 #define INT1 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt 0 */ #define PCINT_vect_num 2 #define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ #define TIMER1_COMPA_vect_num 3 #define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ #define TIMER1_COMPB_vect_num 4 #define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ #define TIMER1_OVF_vect_num 5 #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ #define TIMER0_OVF_vect_num 6 #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ #define USI_START_vect_num 7 #define USI_START_vect _VECTOR(7) /* USI Start */ #define USI_OVF_vect_num 8 #define USI_OVF_vect _VECTOR(8) /* USI Overflow */ #define EE_RDY_vect_num 9 #define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ #define ANA_COMP_vect_num 10 #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ #define ADC_vect_num 11 #define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ #define INT1_vect_num 13 #define INT1_vect _VECTOR(13) /* External Interrupt 1 */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ #define TIMER0_CAPT_vect_num 16 #define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ #define TIMER1_COMPD_vect_num 17 #define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ #define FAULT_PROTECTION_vect_num 18 #define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (19 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x60) #define RAMSIZE (512) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x1FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x0D /* Device Pin Definitions */ #define DI_B_DDR DDRMOSI #define DI_B_PORT PORTMOSI #define DI_B_PIN PINMOSI #define DI_B_BIT MOSI #define SDA_B_DDR DDRMOSI #define SDA_B_PORT PORTMOSI #define SDA_B_PIN PINMOSI #define SDA_B_BIT MOSI #define _OC1A_DDR DDRMOSI #define _OC1A_PORT PORTMOSI #define _OC1A_PIN PINMOSI #define _OC1A_BIT MOSI #define PCINT8_DDR DDRMOSI #define PCINT8_PORT PORTMOSI #define PCINT8_PIN PINMOSI #define PCINT8_BIT MOSI #define PB0_DDR DDRMOSI #define PB0_PORT PORTMOSI #define PB0_PIN PINMOSI #define PB0_BIT MOSI #define DO_B_DDR DDRMISO #define DO_B_PORT PORTMISO #define DO_B_PIN PINMISO #define DO_B_BIT MISO #define OC1A_DDR DDRMISO #define OC1A_PORT PORTMISO #define OC1A_PIN PINMISO #define OC1A_BIT MISO #define PCINT9_DDR DDRMISO #define PCINT9_PORT PORTMISO #define PCINT9_PIN PINMISO #define PCINT9_BIT MISO #define PB1_DDR DDRMISO #define PB1_PORT PORTMISO #define PB1_PIN PINMISO #define PB1_BIT MISO #define USCK_B_DDR DDRSCK #define USCK_B_PORT PORTSCK #define USCK_B_PIN PINSCK #define USCK_B_BIT SCK #define SCL_B_DDR DDRSCK #define SCL_B_PORT PORTSCK #define SCL_B_PIN PINSCK #define SCL_B_BIT SCK #define OC1B_DDR DDRSCK #define OC1B_PORT PORTSCK #define OC1B_PIN PINSCK #define OC1B_BIT SCK #define PCINT10_DDR DDRSCK #define PCINT10_PORT PORTSCK #define PCINT10_PIN PINSCK #define PCINT10_BIT SCK #define PB2_DDR DDRSCK #define PB2_PORT PORTSCK #define PB2_PIN PINSCK #define PB2_BIT SCK #define PCINT11_DDR DDROC1B #define PCINT11_PORT PORTOC1B #define PCINT11_PIN PINOC1B #define PCINT11_BIT OC1B #define PB3_DDR DDROC1B #define PB3_PORT PORTOC1B #define PB3_PIN PINOC1B #define PB3_BIT OC1B #define PCINT12_DDR DDRADC #define PCINT12_PORT PORTADC #define PCINT12_PIN PINADC #define PCINT12_BIT ADC7 #define _OC1D_DDR DDRADC #define _OC1D_PORT PORTADC #define _OC1D_PIN PINADC #define _OC1D_BIT ADC7 #define CLKI_DDR DDRADC #define CLKI_PORT PORTADC #define CLKI_PIN PINADC #define CLKI_BIT ADC7 #define PB4_DDR DDRADC #define PB4_PORT PORTADC #define PB4_PIN PINADC #define PB4_BIT ADC7 #define PCINT13_DDR DDRADC #define PCINT13_PORT PORTADC #define PCINT13_PIN PINADC #define PCINT13_BIT ADC8 #define OC1D_DDR DDRADC #define OC1D_PORT PORTADC #define OC1D_PIN PINADC #define OC1D_BIT ADC8 #define CKLO_DDR DDRADC #define CKLO_PORT PORTADC #define CKLO_PIN PINADC #define CKLO_BIT ADC8 #define PB5_DDR DDRADC #define PB5_PORT PORTADC #define PB5_PIN PINADC #define PB5_BIT ADC8 #define INT0_DDR DDRADC #define INT0_PORT PORTADC #define INT0_PIN PINADC #define INT0_BIT ADC9 #define T0_DDR DDRADC #define T0_PORT PORTADC #define T0_PIN PINADC #define T0_BIT ADC9 #define PCINT14_DDR DDRADC #define PCINT14_PORT PORTADC #define PCINT14_PIN PINADC #define PCINT14_BIT ADC9 #define PB6_DDR DDRADC #define PB6_PORT PORTADC #define PB6_PIN PINADC #define PB6_BIT ADC9 #define PCINT15_DDR DDRADC1 #define PCINT15_PORT PORTADC1 #define PCINT15_PIN PINADC1 #define PCINT15_BIT ADC10 #define PB7_DDR DDRADC1 #define PB7_PORT PORTADC1 #define PB7_PIN PINADC1 #define PB7_BIT ADC10 #define AIN1_DDR DDRADC #define AIN1_PORT PORTADC #define AIN1_PIN PINADC #define AIN1_BIT ADC6 #define PCINT7_DDR DDRADC #define PCINT7_PORT PORTADC #define PCINT7_PIN PINADC #define PCINT7_BIT ADC6 #define PA7_DDR DDRADC #define PA7_PORT PORTADC #define PA7_PIN PINADC #define PA7_BIT ADC6 #define AIN0_DDR DDRADC #define AIN0_PORT PORTADC #define AIN0_PIN PINADC #define AIN0_BIT ADC5 #define PCINT6_DDR DDRADC #define PCINT6_PORT PORTADC #define PCINT6_PIN PINADC #define PCINT6_BIT ADC5 #define PA6_DDR DDRADC #define PA6_PORT PORTADC #define PA6_PIN PINADC #define PA6_BIT ADC5 #define AIN2_DDR DDRADC #define AIN2_PORT PORTADC #define AIN2_PIN PINADC #define AIN2_BIT ADC4 #define PCINT5_DDR DDRADC #define PCINT5_PORT PORTADC #define PCINT5_PIN PINADC #define PCINT5_BIT ADC4 #define PA5_DDR DDRADC #define PA5_PORT PORTADC #define PA5_PIN PINADC #define PA5_BIT ADC4 #define ICP0_DDR DDRADC #define ICP0_PORT PORTADC #define ICP0_PIN PINADC #define ICP0_BIT ADC3 #define PCINT4_DDR DDRADC #define PCINT4_PORT PORTADC #define PCINT4_PIN PINADC #define PCINT4_BIT ADC3 #define PA4_DDR DDRADC #define PA4_PORT PORTADC #define PA4_PIN PINADC #define PA4_BIT ADC3 #define PCINT3_DDR DDRAREF #define PCINT3_PORT PORTAREF #define PCINT3_PIN PINAREF #define PCINT3_BIT AREF #define PA3_DDR DDRAREF #define PA3_PORT PORTAREF #define PA3_PIN PINAREF #define PA3_BIT AREF #define INT1_DDR DDRADC #define INT1_PORT PORTADC #define INT1_PIN PINADC #define INT1_BIT ADC2 #define USCK_A_DDR DDRADC #define USCK_A_PORT PORTADC #define USCK_A_PIN PINADC #define USCK_A_BIT ADC2 #define SCL_A_DDR DDRADC #define SCL_A_PORT PORTADC #define SCL_A_PIN PINADC #define SCL_A_BIT ADC2 #define PCINT2_DDR DDRADC #define PCINT2_PORT PORTADC #define PCINT2_PIN PINADC #define PCINT2_BIT ADC2 #define PA2_DDR DDRADC #define PA2_PORT PORTADC #define PA2_PIN PINADC #define PA2_BIT ADC2 #define DO_A_DDR DDRADC #define DO_A_PORT PORTADC #define DO_A_PIN PINADC #define DO_A_BIT ADC1 #define PCINT1_DDR DDRADC #define PCINT1_PORT PORTADC #define PCINT1_PIN PINADC #define PCINT1_BIT ADC1 #define PA1_DDR DDRADC #define PA1_PORT PORTADC #define PA1_PIN PINADC #define PA1_BIT ADC1 #define DI_A_DDR DDRADC #define DI_A_PORT PORTADC #define DI_A_PIN PINADC #define DI_A_BIT ADC0 #define SDA_A_DDR DDRADC #define SDA_A_PORT PORTADC #define SDA_A_PIN PINADC #define SDA_A_BIT ADC0 #define PCINT0_DDR DDRADC #define PCINT0_PORT PORTADC #define PCINT0_PIN PINADC #define PCINT0_BIT ADC0 #define PA0_DDR DDRADC #define PA0_PORT PORTADC #define PA0_PIN PINADC #define PA0_BIT ADC0 #endif /* _AVR_ATtiny861A_H_ */ avr-libc-1.8.0.orig/include/avr/iom16m1.h0000644000000000000000000007401711732702554014640 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16m1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ /* avr/iom16m1.h - definitions for ATmega16M1 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16m1.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega16M1_H_ #define _AVR_ATmega16M1_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define GPIOR1 _SFR_IO8(0x19) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x1A) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSRSYNC 0 #define ICPSEL1 6 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLF 2 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define AC0O 0 #define AC1O 1 #define AC2O 2 #define AC3O 3 #define AC0IF 4 #define AC1IF 5 #define AC2IF 6 #define AC3IF 7 #define DWDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPIPS 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRLIN 1 #define PRSPI 2 #define PRTIM0 3 #define PRTIM1 4 #define PRPSC 5 #define PRCAN 6 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6A) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6B) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6C) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define PCMSK3 _SFR_MEM8(0x6D) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define AMP0CSR _SFR_MEM8(0x75) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0TS2 2 #define AMPCMP0 3 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 #define AMP1CSR _SFR_MEM8(0x76) #define AMP1TS0 0 #define AMP1TS1 1 #define AMP1TS2 2 #define AMPCMP1 3 #define AMP1G0 4 #define AMP1G1 5 #define AMP1IS 6 #define AMP1EN 7 #define AMP2CSR _SFR_MEM8(0x77) #define AMP2TS0 0 #define AMP2TS1 1 #define AMP2TS2 2 #define AMPCMP2 3 #define AMP2G0 4 #define AMP2G1 5 #define AMP2IS 6 #define AMP2EN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define AREFEN 5 #define ISRCEN 6 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define AMP0ND 3 #define AMP0PD 4 #define ACMP0D 5 #define AMP2PD 6 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define DACON _SFR_MEM8(0x90) #define DAEN 0 #define DAOE 1 #define DALA 2 #define DATS0 4 #define DATS1 5 #define DATS2 6 #define DAATE 7 #define DAC _SFR_MEM16(0x91) #define DACL _SFR_MEM8(0x91) #define DACL0 0 #define DACL1 1 #define DACL2 2 #define DACL3 3 #define DACL4 4 #define DACL5 5 #define DACL6 6 #define DACL7 7 #define DACH _SFR_MEM8(0x92) #define DACH0 0 #define DACH1 1 #define DACH2 2 #define DACH3 3 #define DACH4 4 #define DACH5 5 #define DACH6 6 #define DACH7 7 #define AC0CON _SFR_MEM8(0x94) #define AC0M0 0 #define AC0M1 1 #define AC0M2 2 #define ACCKSEL 3 #define AC0IS0 4 #define AC0IS1 5 #define AC0IE 6 #define AC0EN 7 #define AC1CON _SFR_MEM8(0x95) #define AC1M0 0 #define AC1M1 1 #define AC1M2 2 #define AC1ICE 3 #define AC1IS0 4 #define AC1IS1 5 #define AC1IE 6 #define AC1EN 7 #define AC2CON _SFR_MEM8(0x96) #define AC2M0 0 #define AC2M1 1 #define AC2M2 2 #define AC2IS0 4 #define AC2IS1 5 #define AC2IE 6 #define AC2EN 7 #define AC3CON _SFR_MEM8(0x97) #define AC3M0 0 #define AC3M1 1 #define AC3M2 2 #define AC3IS0 4 #define AC3IS1 5 #define AC3IE 6 #define AC3EN 7 #define POCR0SA _SFR_MEM16(0xA0) #define POCR0SAL _SFR_MEM8(0xA0) #define POCR0SA_0 0 #define POCR0SA_1 1 #define POCR0SA_2 2 #define POCR0SA_3 3 #define POCR0SA_4 4 #define POCR0SA_5 5 #define POCR0SA_6 6 #define POCR0SA_7 7 #define POCR0SAH _SFR_MEM8(0xA1) #define POCR0SA_8 0 #define POCR0SA_9 1 #define POCR0SA_10 2 #define POCR0SA_11 3 #define POCR0RA _SFR_MEM16(0xA2) #define POCR0RAL _SFR_MEM8(0xA2) #define POCR0RA_0 0 #define POCR0RA_1 1 #define POCR0RA_2 2 #define POCR0RA_3 3 #define POCR0RA_4 4 #define POCR0RA_5 5 #define POCR0RA_6 6 #define POCR0RA_7 7 #define POCR0RAH _SFR_MEM8(0xA3) #define POCR0RA_8 0 #define POCR0RA_9 1 #define POCR0RA_10 2 #define POCR0RA_11 3 #define POCR0SB _SFR_MEM16(0xA4) #define POCR0SBL _SFR_MEM8(0xA4) #define POCR0SB_0 0 #define POCR0SB_1 1 #define POCR0SB_2 2 #define POCR0SB_3 3 #define POCR0SB_4 4 #define POCR0SB_5 5 #define POCR0SB_6 6 #define POCR0SB_7 7 #define POCR0SBH _SFR_MEM8(0xA5) #define POCR0SB_8 0 #define POCR0SB_9 1 #define POCR0SB_10 2 #define POCR0SB_11 3 #define POCR1SA _SFR_MEM16(0xA6) #define POCR1SAL _SFR_MEM8(0xA6) #define POCR1SA_0 0 #define POCR1SA_1 1 #define POCR1SA_2 2 #define POCR1SA_3 3 #define POCR1SA_4 4 #define POCR1SA_5 5 #define POCR1SA_6 6 #define POCR1SA_7 7 #define POCR1SAH _SFR_MEM8(0xA7) #define POCR1SA_8 0 #define POCR1SA_9 1 #define POCR1SA_10 2 #define POCR1SA_11 3 #define POCR1RA _SFR_MEM16(0xA8) #define POCR1RAL _SFR_MEM8(0xA8) #define POCR1RA_0 0 #define POCR1RA_1 1 #define POCR1RA_2 2 #define POCR1RA_3 3 #define POCR1RA_4 4 #define POCR1RA_5 5 #define POCR1RA_6 6 #define POCR1RA_7 7 #define POCR1RAH _SFR_MEM8(0xA9) #define POCR1RA_8 0 #define POCR1RA_9 1 #define POCR1RA_10 2 #define POCR1RA_11 3 #define POCR1SB _SFR_MEM16(0xAA) #define POCR1SBL _SFR_MEM8(0xAA) #define POCR1SB_0 0 #define POCR1SB_1 1 #define POCR1SB_2 2 #define POCR1SB_3 3 #define POCR1SB_4 4 #define POCR1SB_5 5 #define POCR1SB_6 6 #define POCR1SB_7 7 #define POCR1SBH _SFR_MEM8(0xAB) #define POCR1SB_8 0 #define POCR1SB_9 1 #define POCR1SB_10 2 #define POCR1SB_11 3 #define POCR2SA _SFR_MEM16(0xAC) #define POCR2SAL _SFR_MEM8(0xAC) #define POCR2SA_0 0 #define POCR2SA_1 1 #define POCR2SA_2 2 #define POCR2SA_3 3 #define POCR2SA_4 4 #define POCR2SA_5 5 #define POCR2SA_6 6 #define POCR2SA_7 7 #define POCR2SAH _SFR_MEM8(0xAD) #define POCR2SA_8 0 #define POCR2SA_9 1 #define POCR2SA_10 2 #define POCR2SA_11 3 #define POCR2RA _SFR_MEM16(0xAE) #define POCR2RAL _SFR_MEM8(0xAE) #define POCR2RA_0 0 #define POCR2RA_1 1 #define POCR2RA_2 2 #define POCR2RA_3 3 #define POCR2RA_4 4 #define POCR2RA_5 5 #define POCR2RA_6 6 #define POCR2RA_7 7 #define POCR2RAH _SFR_MEM8(0xAF) #define POCR2RA_8 0 #define POCR2RA_9 1 #define POCR2RA_10 2 #define POCR2RA_11 3 #define POCR2SB _SFR_MEM16(0xB0) #define POCR2SBL _SFR_MEM8(0xB0) #define POCR2SB_0 0 #define POCR2SB_1 1 #define POCR2SB_2 2 #define POCR2SB_3 3 #define POCR2SB_4 4 #define POCR2SB_5 5 #define POCR2SB_6 6 #define POCR2SB_7 7 #define POCR2SBH _SFR_MEM8(0xB1) #define POCR2SB_8 0 #define POCR2SB_9 1 #define POCR2SB_10 2 #define POCR2SB_11 3 #define POCR_RB _SFR_MEM16(0xB2) #define POCR_RBL _SFR_MEM8(0xB2) #define POCR_RB_0 0 #define POCR_RB_1 1 #define POCR_RB_2 2 #define POCR_RB_3 3 #define POCR_RB_4 4 #define POCR_RB_5 5 #define POCR_RB_6 6 #define POCR_RB_7 7 #define POCR_RBH _SFR_MEM8(0xB3) #define POCR_RB_8 0 #define POCR_RB_9 1 #define POCR_RB_10 2 #define POCR_RB_11 3 #define PSYNC _SFR_MEM8(0xB4) #define PSYNC00 0 #define PSYNC01 1 #define PSYNC10 2 #define PSYNC11 3 #define PSYNC20 4 #define PSYNC21 5 #define PCNF _SFR_MEM8(0xB5) #define POPA 2 #define POPB 3 #define PMODE 4 #define PULOCK 5 #define POC _SFR_MEM8(0xB6) #define POEN0A 0 #define POEN0B 1 #define POEN1A 2 #define POEN1B 3 #define POEN2A 4 #define POEN2B 5 #define PCTL _SFR_MEM8(0xB7) #define PRUN 0 #define PCCYC 1 #define PCLKSEL 5 #define PPRE0 6 #define PPRE1 7 #define PMIC0 _SFR_MEM8(0xB8) #define PRFM00 0 #define PRFM01 1 #define PRFM02 2 #define PAOC0 3 #define PFLTE0 4 #define PELEV0 5 #define PISEL0 6 #define POVEN0 7 #define PMIC1 _SFR_MEM8(0xB9) #define PRFM10 0 #define PRFM11 1 #define PRFM12 2 #define PAOC1 3 #define PFLTE1 4 #define PELEV1 5 #define PISEL1 6 #define POVEN1 7 #define PMIC2 _SFR_MEM8(0xBA) #define PRFM20 0 #define PRFM21 1 #define PRFM22 2 #define PAOC2 3 #define PFLTE2 4 #define PELEV2 5 #define PISEL2 6 #define POVEN2 7 #define PIM _SFR_MEM8(0xBB) #define PEOPE 0 #define PEVE0 1 #define PEVE1 2 #define PEVE2 3 #define PIFR _SFR_MEM8(0xBC) #define PEOP 0 #define PEV0 1 #define PEV1 2 #define PEV2 3 #define LINCR _SFR_MEM8(0xC8) #define LCMD0 0 #define LCMD1 1 #define LCMD2 2 #define LENA 3 #define LCONF0 4 #define LCONF1 5 #define LIN13 6 #define LSWRES 7 #define LINSIR _SFR_MEM8(0xC9) #define LRXOK 0 #define LTXOK 1 #define LIDOK 2 #define LERR 3 #define LBUSY 4 #define LIDST0 5 #define LIDST1 6 #define LIDST2 7 #define LINENIR _SFR_MEM8(0xCA) #define LENRXOK 0 #define LENTXOK 1 #define LENIDOK 2 #define LENERR 3 #define LINERR _SFR_MEM8(0xCB) #define LBERR 0 #define LCERR 1 #define LPERR 2 #define LSERR 3 #define LFERR 4 #define LOVERR 5 #define LTOERR 6 #define LABORT 7 #define LINBTR _SFR_MEM8(0xCC) #define LBT0 0 #define LBT1 1 #define LBT2 2 #define LBT3 3 #define LBT4 4 #define LBT5 5 #define LDISR 7 #define LINBRR _SFR_MEM16(0xCD) #define LINBRRL _SFR_MEM8(0xCD) #define LDIV0 0 #define LDIV1 1 #define LDIV2 2 #define LDIV3 3 #define LDIV4 4 #define LDIV5 5 #define LDIV6 6 #define LDIV7 7 #define LINBRRH _SFR_MEM8(0xCE) #define LDIV8 0 #define LDIV9 1 #define LDIV10 2 #define LDIV11 3 #define LINDLR _SFR_MEM8(0xCF) #define LRXDL0 0 #define LRXDL1 1 #define LRXDL2 2 #define LRXDL3 3 #define LTXDL0 4 #define LTXDL1 5 #define LTXDL2 6 #define LTXDL3 7 #define LINIDR _SFR_MEM8(0xD0) #define LID0 0 #define LID1 1 #define LID2 2 #define LID3 3 #define LID4 4 #define LID5 5 #define LP0 6 #define LP1 7 #define LINSEL _SFR_MEM8(0xD1) #define LINDX0 0 #define LINDX1 1 #define LINDX2 2 #define LAINC 3 #define LINDAT _SFR_MEM8(0xD2) #define LDATA0 0 #define LDATA1 1 #define LDATA2 2 #define LDATA3 3 #define LDATA4 4 #define LDATA5 5 #define LDATA6 6 #define LDATA7 7 #define CANGCON _SFR_MEM8(0xD8) #define SWRES 0 #define ENASTB 1 #define TEST 2 #define LISTEN 3 #define SYNTTC 4 #define TTC 5 #define OVRQ 6 #define ABRQ 7 #define CANGSTA _SFR_MEM8(0xD9) #define ERRP 0 #define BOFF 1 #define ENFG 2 #define RXBSY 3 #define TXBSY 4 #define OVFG 6 #define CANGIT _SFR_MEM8(0xDA) #define AERG 0 #define FERG 1 #define CERG 2 #define SERG 3 #define BXOK 4 #define OVRTIM 5 #define BOFFIT 6 #define CANIT 7 #define CANGIE _SFR_MEM8(0xDB) #define ENOVRT 0 #define ENERG 1 #define ENBX 2 #define ENERR 3 #define ENTX 4 #define ENRX 5 #define ENBOFF 6 #define ENIT 7 #define CANEN2 _SFR_MEM8(0xDC) #define ENMOB0 0 #define ENMOB1 1 #define ENMOB2 2 #define ENMOB3 3 #define ENMOB4 4 #define ENMOB5 5 #define CANEN1 _SFR_MEM8(0xDD) #define CANIE2 _SFR_MEM8(0xDE) #define IEMOB0 0 #define IEMOB1 1 #define IEMOB2 2 #define IEMOB3 3 #define IEMOB4 4 #define IEMOB5 5 #define CANIE1 _SFR_MEM8(0xDF) /* RegDef: CAN Status Interrupt MOb Register*/ #define CANSIT _SFR_MEM16(0xE0) #define CANSIT2 _SFR_MEM8(0xE0) #define SIT0 0 #define SIT1 1 #define SIT2 2 #define SIT3 3 #define SIT4 4 #define SIT5 5 #define CANSIT1 _SFR_MEM8(0xE1) #define CANBT1 _SFR_MEM8(0xE2) #define BRP0 1 #define BRP1 2 #define BRP2 3 #define BRP3 4 #define BRP4 5 #define BRP5 6 #define CANBT2 _SFR_MEM8(0xE3) #define PRS0 1 #define PRS1 2 #define PRS2 3 #define SJW0 5 #define SJW1 6 #define CANBT3 _SFR_MEM8(0xE4) #define SMP 0 #define PHS10 1 #define PHS11 2 #define PHS12 3 #define PHS20 4 #define PHS21 5 #define PHS22 6 #define CANTCON _SFR_MEM8(0xE5) #define TPRSC0 0 #define TPRSC1 1 #define TPRSC2 2 #define TPRSC3 3 #define TPRSC4 4 #define TPRSC5 5 #define TPRSC6 6 #define TPRSC7 7 #define CANTIM _SFR_MEM16(0xE6) #define CANTIML _SFR_MEM8(0xE6) #define CANTIM0 0 #define CANTIM1 1 #define CANTIM2 2 #define CANTIM3 3 #define CANTIM4 4 #define CANTIM5 5 #define CANTIM6 6 #define CANTIM7 7 #define CANTIMH _SFR_MEM8(0xE7) #define CANTIM8 0 #define CANTIM9 1 #define CANTIM10 2 #define CANTIM11 3 #define CANTIM12 4 #define CANTIM13 5 #define CANTIM14 6 #define CANTIM15 7 #define CANTTC _SFR_MEM16(0xE8) #define CANTTCL _SFR_MEM8(0xE8) #define TIMTCC0 0 #define TIMTCC1 1 #define TIMTCC2 2 #define TIMTCC3 3 #define TIMTCC4 4 #define TIMTCC5 5 #define TIMTCC6 6 #define TIMTCC7 7 #define CANTTCH _SFR_MEM8(0xE9) #define TIMTCC8 0 #define TIMTCC9 1 #define TIMTCC10 2 #define TIMTCC11 3 #define TIMTCC12 4 #define TIMTCC13 5 #define TIMTCC14 6 #define TIMTCC15 7 #define CANTEC _SFR_MEM8(0xEA) #define TEC0 0 #define TEC1 1 #define TEC2 2 #define TEC3 3 #define TEC4 4 #define TEC5 5 #define TEC6 6 #define TEC7 7 #define CANREC _SFR_MEM8(0xEB) #define REC0 0 #define REC1 1 #define REC2 2 #define REC3 3 #define REC4 4 #define REC5 5 #define REC6 6 #define REC7 7 #define CANHPMOB _SFR_MEM8(0xEC) #define CGP0 0 #define CGP1 1 #define CGP2 2 #define CGP3 3 #define HPMOB0 4 #define HPMOB1 5 #define HPMOB2 6 #define HPMOB3 7 #define CANPAGE _SFR_MEM8(0xED) #define INDX0 0 #define INDX1 1 #define INDX2 2 #define AINC 3 #define MOBNB0 4 #define MOBNB1 5 #define MOBNB2 6 #define MOBNB3 7 #define CANSTMOB _SFR_MEM8(0xEE) #define AERR 0 #define FERR 1 #define CERR 2 #define SERR 3 #define BERR 4 #define RXOK 5 #define TXOK 6 #define DLCW 7 #define CANCDMOB _SFR_MEM8(0xEF) #define DLC0 0 #define DLC1 1 #define DLC2 2 #define DLC3 3 #define IDE 4 #define RPLV 5 #define CONMOB0 6 #define CONMOB1 7 /* RegDef: CAN Identifier Tag Registers*/ #define CANIDT _SFR_MEM32(0xF0) #define CANIDT4 _SFR_MEM8(0xF0) #define RB0TAG 0 #define RB1TAG 1 #define RTRTAG 2 #define IDT0 3 #define IDT1 4 #define IDT2 5 #define IDT3 6 #define IDT4 7 #define CANIDT3 _SFR_MEM8(0xF1) #define IDT5 0 #define IDT6 1 #define IDT7 2 #define IDT8 3 #define IDT9 4 #define IDT10 5 #define IDT11 6 #define IDT12 7 #define CANIDT2 _SFR_MEM8(0xF2) #define IDT13 0 #define IDT14 1 #define IDT15 2 #define IDT16 3 #define IDT17 4 #define IDT18 5 #define IDT19 6 #define IDT20 7 #define CANIDT1 _SFR_MEM8(0xF3) #define IDT21 0 #define IDT22 1 #define IDT23 2 #define IDT24 3 #define IDT25 4 #define IDT26 5 #define IDT27 6 #define IDT28 7 /* RegDef: CAN Identifier Mask Registers */ #define CANIDM _SFR_MEM32(0xF4) #define CANIDM4 _SFR_MEM8(0xF4) #define IDEMSK 0 #define RTRMSK 2 #define IDMSK0 3 #define IDMSK1 4 #define IDMSK2 5 #define IDMSK3 6 #define IDMSK4 7 #define CANIDM3 _SFR_MEM8(0xF5) #define IDMSK5 0 #define IDMSK6 1 #define IDMSK7 2 #define IDMSK8 3 #define IDMSK9 4 #define IDMSK10 5 #define IDMSK11 6 #define IDMSK12 7 #define CANIDM2 _SFR_MEM8(0xF6) #define IDMSK13 0 #define IDMSK14 1 #define IDMSK15 2 #define IDMSK16 3 #define IDMSK17 4 #define IDMSK18 5 #define IDMSK19 6 #define IDMSK20 7 #define CANIDM1 _SFR_MEM8(0xF7) #define IDMSK21 0 #define IDMSK22 1 #define IDMSK23 2 #define IDMSK24 3 #define IDMSK25 4 #define IDMSK26 5 #define IDMSK27 6 #define IDMSK28 7 #define CANSTM _SFR_MEM16(0xF8) #define CANSTML _SFR_MEM8(0xF8) #define TIMSTM0 0 #define TIMSTM1 1 #define TIMSTM2 2 #define TIMSTM3 3 #define TIMSTM4 4 #define TIMSTM5 5 #define TIMSTM6 6 #define TIMSTM7 7 #define CANSTMH _SFR_MEM8(0xF9) #define TIMSTM8 0 #define TIMSTM9 1 #define TIMSTM10 2 #define TIMSTM11 3 #define TIMSTM12 4 #define TIMSTM13 5 #define TIMSTM14 6 #define TIMSTM15 7 #define CANMSG _SFR_MEM8(0xFA) #define MSG0 0 #define MSG1 1 #define MSG2 2 #define MSG3 3 #define MSG4 4 #define MSG5 5 #define MSG6 6 #define MSG7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define ANACOMP0_vect_num 1 #define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ #define ANACOMP1_vect_num 2 #define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ #define ANACOMP2_vect_num 3 #define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ #define ANACOMP3_vect_num 4 #define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ #define PSC_FAULT_vect_num 5 #define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ #define PSC_EC_vect_num 6 #define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ #define INT0_vect_num 7 #define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ #define INT1_vect_num 8 #define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ #define INT2_vect_num 9 #define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ #define INT3_vect_num 10 #define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 14 #define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 15 #define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 16 #define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ #define CAN_INT_vect_num 18 #define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ #define CAN_TOVF_vect_num 19 #define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ #define LIN_TC_vect_num 20 #define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ #define LIN_ERR_vect_num 21 #define LIN_ERR_vect _VECTOR(21) /* LIN Error */ #define PCINT0_vect_num 22 #define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 23 #define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 24 #define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ #define PCINT3_vect_num 25 #define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ #define SPI_STC_vect_num 26 #define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ #define ADC_vect_num 27 #define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ #define WDT_vect_num 28 #define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ #define EE_READY_vect_num 29 #define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ #define SPM_READY_vect_num 30 #define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (31 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x0100) #define RAMSIZE (1024) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (0x0) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x3FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ #define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ #define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ #define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x84 #endif /* _AVR_ATmega16M1_H_ */ avr-libc-1.8.0.orig/include/avr/iom16a.h0000644000000000000000000004510611732702554014540 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16a.h 2248 2011-05-23 19:54:32Z joerg_wunsch $ */ /* avr/iom16a.h - definitions for ATmega16A */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16a.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega16A_H_ #define _AVR_ATmega16A_H_ 1 /* Registers and associated bit numbers. */ #define TWBR _SFR_IO8(0x00) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_IO8(0x01) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_IO8(0x02) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_IO8(0x03) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x05) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define UBRRL _SFR_IO8(0x09) #define UBRR0 0 #define UBRR1 1 #define UBRR2 2 #define UBRR3 3 #define UBRR4 4 #define UBRR5 5 #define UBRR6 6 #define UBRR7 7 #define UCSRB _SFR_IO8(0x0A) #define TXB8 0 #define RXB8 1 #define UCSZ2 2 #define TXEN 3 #define RXEN 4 #define UDRIE 5 #define TXCIE 6 #define RXCIE 7 #define UCSRA _SFR_IO8(0x0B) #define MPCM 0 #define U2X 1 #define UPE 2 #define DOR 3 #define FE 4 #define UDRE 5 #define TXC 6 #define RXC 7 #define UDR _SFR_IO8(0x0C) #define UDR0 0 #define UDR1 1 #define UDR2 2 #define UDR3 3 #define UDR4 4 #define UDR5 5 #define UDR6 6 #define UDR7 7 #define SPCR _SFR_IO8(0x0D) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x0E) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x0F) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define PIND _SFR_IO8(0x10) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x11) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x12) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINC _SFR_IO8(0x13) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x14) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x15) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEDR _SFR_IO8(0x1D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x1F) #define EEAR8 0 #define UBRRH _SFR_IO8(0x20) #define UBRR8 0 #define UBRR9 1 #define UBRR10 2 #define UBRR11 3 #define UCSRC _SFR_IO8(0x20) #define UCPOL 0 #define UCSZ0 1 #define UCSZ1 2 #define USBS 3 #define UPM0 4 #define UPM1 5 #define UMSEL 6 #define URSEL 7 #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDTOE 4 #define ASSR _SFR_IO8(0x22) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define OCR2 _SFR_IO8(0x23) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define TCNT2 _SFR_IO8(0x24) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define TCCR2 _SFR_IO8(0x25) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM20 4 #define COM21 5 #define WGM20 6 #define FOC2 7 #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_IO8(0x27) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_IO8(0x29) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_IO8(0x2B) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_IO8(0x2D) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define TCCR1B _SFR_IO8(0x2E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x2F) #define WGM10 0 #define WGM11 1 #define FOC1B 2 #define FOC1A 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define SFIOR _SFR_IO8(0x30) #define PSR10 0 #define PSR2 1 #define PUD 2 #define ACME 3 #define ADTS0 5 #define ADTS1 6 #define ADTS2 7 #define OSCCAL _SFR_IO8(0x31) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define TCNT0 _SFR_IO8(0x32) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0 _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM00 4 #define COM01 5 #define WGM00 6 #define FOC0 7 #define MCUCSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define ISC2 6 #define JTD 7 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define SM0 4 #define SM1 5 #define SE 6 #define SM2 7 #define TWCR _SFR_IO8(0x36) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define TIFR _SFR_IO8(0x38) #define TOV0 0 #define OCF0 1 #define TOV1 2 #define OCF1B 3 #define OCF1A 4 #define ICF1 5 #define TOV2 6 #define OCF2 7 #define TIMSK _SFR_IO8(0x39) #define TOIE0 0 #define OCIE0 1 #define TOIE1 2 #define OCIE1B 3 #define OCIE1A 4 #define TICIE1 5 #define TOIE2 6 #define OCIE2 7 #define GIFR _SFR_IO8(0x3A) #define INTF2 5 #define INTF0 6 #define INTF1 7 #define GICR _SFR_IO8(0x3B) #define IVCE 0 #define IVSEL 1 #define INT2 5 #define INT0 6 #define INT1 7 #define OCR0 _SFR_IO8(0x3C) #define OCR0_0 0 #define OCR0_1 1 #define OCR0_2 2 #define OCR0_3 3 #define OCR0_4 4 #define OCR0_5 5 #define OCR0_6 6 #define OCR0_7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define TIMER2_COMP_vect_num 3 #define TIMER2_COMP_vect _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_OVF_vect_num 4 #define TIMER2_OVF_vect _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 5 #define TIMER1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 6 #define TIMER1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 7 #define TIMER1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 8 #define TIMER1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER0_OVF_vect_num 9 #define TIMER0_OVF_vect _VECTOR(9) /* Timer/Counter0 Overflow */ #define SPISTC_vect_num 10 #define SPISTC_vect _VECTOR(10) /* Serial Transfer Complete */ /* The following vectors use an inconsistent (to the ATmega16 etc.) naming scheme. The inconsistent names are preserved here for softwares that already use them: */ #define USARTRXC_vect_num 11 #define USARTRXC_vect _VECTOR(11) /* USART, Rx Complete */ #define USARTUDRE_vect_num 12 #define USARTUDRE_vect _VECTOR(12) /* USART Data Register Empty */ #define USARTTXC_vect_num 13 #define USARTTXC_vect _VECTOR(13) /* USART, Tx Complete */ /* The "classic" designators: */ #define USART_RXC_vect_num 11 #define USART_RXC_vect _VECTOR(11) /* USART, Rx Complete */ #define USART_UDRE_vect_num 12 #define USART_UDRE_vect _VECTOR(12) /* USART Data Register Empty */ #define USART_TXC_vect_num 13 #define USART_TXC_vect _VECTOR(13) /* USART, Tx Complete */ #define ADC_vect_num 14 #define ADC_vect _VECTOR(14) /* ADC Conversion Complete */ #define EE_RDY_vect_num 15 #define EE_RDY_vect _VECTOR(15) /* EEPROM Ready */ #define ANA_COMP_vect_num 16 #define ANA_COMP_vect _VECTOR(16) /* Analog Comparator */ #define TWI_vect_num 17 #define TWI_vect _VECTOR(17) /* 2-wire Serial Interface */ #define INT2_vect_num 18 #define INT2_vect _VECTOR(18) /* External Interrupt Request 2 */ #define TIMER0_COMP_vect_num 19 #define TIMER0_COMP_vect _VECTOR(19) /* Timer/Counter0 Compare Match */ #define SPM_RDY_vect_num 20 #define SPM_RDY_vect _VECTOR(20) /* Store Program Memory Ready */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (21 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x60) #define RAMSIZE (1024) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x3FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ #define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ #define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_CKOPT (unsigned char)~_BV(4) /* Oscillator Options */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x03 /* Device Pin Definitions */ #define MOSI_DDR DDRB #define MOSI_PORT PORTB #define MOSI_PIN PINB #define MOSI_BIT 5 #define MISO_DDR DDRB #define MISO_PORT PORTB #define MISO_PIN PINB #define MISO_BIT 6 #define PB7_SCK_DDR DDRB7_SCK #define PB7_SCK_PORT PORTB7_SCK #define PB7_SCK_PIN PINB7_SCK #define PB7_SCK_BIT 7_SCK #define RXD_DDR DDRD #define RXD_PORT PORTD #define RXD_PIN PIND #define RXD_BIT 0 #define TXD_DDR DDRD #define TXD_PORT PORTD #define TXD_PIN PIND #define TXD_BIT 1 #define INT0_DDR DDRD #define INT0_PORT PORTD #define INT0_PIN PIND #define INT0_BIT 2 #define INT1_DDR DDRD #define INT1_PORT PORTD #define INT1_PIN PIND #define INT1_BIT 3 #define OC1B_DDR DDRD #define OC1B_PORT PORTD #define OC1B_PIN PIND #define OC1B_BIT 4 #define OC1A_DDR DDRD #define OC1A_PORT PORTD #define OC1A_PIN PIND #define OC1A_BIT 5 #define ICP_DDR DDRD #define ICP_PORT PORTD #define ICP_PIN PIND #define ICP_BIT 6 #define OC2_DDR DDRD #define OC2_PORT PORTD #define OC2_PIN PIND #define OC2_BIT 7 #define SCL_DDR DDRC #define SCL_PORT PORTC #define SCL_PIN PINC #define SCL_BIT 0 #define SDA_DDR DDRC #define SDA_PORT PORTC #define SDA_PIN PINC #define SDA_BIT 1 #define PC3_DDR DDRC #define PC3_PORT PORTC #define PC3_PIN PINC #define PC3_BIT 3 #define PC4_DDR DDRC #define PC4_PORT PORTC #define PC4_PIN PINC #define PC4_BIT 4 #define PC5_DDR DDRC #define PC5_PORT PORTC #define PC5_PIN PINC #define PC5_BIT 5 #define ADC7_DDR DDRA #define ADC7_PORT PORTA #define ADC7_PIN PINA #define ADC7_BIT 7 #define ADC6_DDR DDRA #define ADC6_PORT PORTA #define ADC6_PIN PINA #define ADC6_BIT 6 #define ADc5_DDR DDRA #define ADc5_PORT PORTA #define ADc5_PIN PINA #define ADc5_BIT 5 #define ADC4_DDR DDRA #define ADC4_PORT PORTA #define ADC4_PIN PINA #define ADC4_BIT 4 #define ADC3_DDR DDRA #define ADC3_PORT PORTA #define ADC3_PIN PINA #define ADC3_BIT 3 #define ADC2_DDR DDRA #define ADC2_PORT PORTA #define ADC2_PIN PINA #define ADC2_BIT 2 #define ADC1_DDR DDRA #define ADC1_PORT PORTA #define ADC1_PIN PINA #define ADC1_BIT 1 #define ADC0_DDR DDRA #define ADC0_PORT PORTA #define ADC0_PIN PINA #define ADC0_BIT 0 #define T0_DDR DDRB #define T0_PORT PORTB #define T0_PIN PINB #define T0_BIT 0 #define T1_DDR DDRB #define T1_PORT PORTB #define T1_PIN PINB #define T1_BIT 1 #define AIN0_DDR DDRB #define AIN0_PORT PORTB #define AIN0_PIN PINB #define AIN0_BIT 2 #define AIN1_DDR DDRB #define AIN1_PORT PORTB #define AIN1_PIN PINB #define AIN1_BIT 3 #define SS_DDR DDRB #define SS_PORT PORTB #define SS_PIN PINB #define SS_BIT 4 #endif /* _AVR_ATmega16A_H_ */ avr-libc-1.8.0.orig/include/avr/iom3250.h0000644000000000000000000005035211732702554014541 0ustar /* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom3250.h 2234 2011-03-16 04:32:21Z arcanum $ */ /* avr/iom3250.h - definitions for ATmega3250 and ATmega3250P. */ #ifndef _AVR_IOM3250_H_ #define _AVR_IOM3250_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom3250.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define PCIF2 6 #define PCIF3 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define PCIE2 6 #define PCIE3 7 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #if defined(__AVR_ATmega3250P__) #define BODSE 5 #define BODS 6 #endif #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x72] */ #define PCMSK3 _SFR_MEM8(0x73) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define PCINT27 3 #define PCINT28 4 #define PCINT29 5 #define PCINT30 6 /* Reserved [0x74..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0XC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7..0xD7] */ #define PINH _SFR_MEM8(0xD8) #define PINH7 7 #define PINH6 6 #define PINH5 5 #define PINH4 4 #define PINH3 3 #define PINH2 2 #define PINH1 1 #define PINH0 0 #define DDRH _SFR_MEM8(0xD9) #define DDH7 7 #define DDH6 6 #define DDH5 5 #define DDH4 4 #define DDH3 3 #define DDH2 2 #define DDH1 1 #define DDH0 0 #define PORTH _SFR_MEM8(0xDA) #define PH7 7 #define PH6 6 #define PH5 5 #define PH4 4 #define PH3 3 #define PH2 2 #define PH1 1 #define PH0 0 #define PINJ _SFR_MEM8(0xDB) #define PINJ6 6 #define PINJ5 5 #define PINJ4 4 #define PINJ3 3 #define PINJ2 2 #define PINJ1 1 #define PINJ0 0 #define DDRJ _SFR_MEM8(0xDC) #define DDJ6 6 #define DDJ5 5 #define DDJ4 4 #define DDJ3 3 #define DDJ2 2 #define DDJ1 1 #define DDJ0 0 #define PORTJ _SFR_MEM8(0xDD) #define PJ6 6 #define PJ5 5 #define PJ4 4 #define PJ3 3 #define PJ2 2 #define PJ1 1 #define PJ0 0 /* Reserved [0xDE..0xFF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART, Rx Complete */ #define USART_RX_vect_num 13 #define USART_RX_vect _VECTOR(13) #define USART0_RX_vect _VECTOR(13) /* Alias */ #define SIG_UART_RECV _VECTOR(13) /* USART Data register Empty */ #define USART_UDRE_vect_num 14 #define USART_UDRE_vect _VECTOR(14) #define USART0_UDRE_vect _VECTOR(14) /* Alias */ #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define USART_TX_vect _VECTOR(15) /* Alias */ #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* Pin Change Interrupt Request 2 */ #define PCINT2_vect_num 23 #define PCINT2_vect _VECTOR(23) #define SIG_PIN_CHANGE2 _VECTOR(23) /* Pin Change Interrupt Request 3 */ #define PCINT3_vect_num 24 #define PCINT3_vect _VECTOR(24) #define SIG_PIN_CHANGE3 _VECTOR(24) #define _VECTORS_SIZE 100 /* Constants */ #define SPM_PAGESIZE 128 #define RAMSTART (0x100) #define RAMEND 0x8FF #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 4 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x06 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison USART0_RX_vect #pragma GCC poison SIG_UART_RECV #pragma GCC poison USART0_UDRE_vect #pragma GCC poison SIG_UART_DATA #pragma GCC poison USART_TX_vect #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #pragma GCC poison SIG_PIN_CHANGE2 #pragma GCC poison SIG_PIN_CHANGE3 #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM3250_H_ */ avr-libc-1.8.0.orig/include/avr/io43u32x.h0000644000000000000000000002562711732702554014752 0ustar /* Copyright (c) 2003,2005 Keith Gudger All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io43u32x.h 1873 2009-02-11 17:53:39Z arcanum $ */ /* avr/io43u32x.h - definitions for AT43USB32x */ #ifndef _AVR_IO43U32X_H_ #define _AVR_IO43U32X_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io43u32x.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART Baud Rate Register */ #define UBRR _SFR_IO8(0x09) /* UART Control Register */ #define UCR _SFR_IO8(0x0A) /* UART Status Register */ #define USR _SFR_IO8(0x0B) /* UART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* Input Pins, Port E */ // new port for 43324/6 #define PINE _SFR_IO8(0x01) /* Data Direction Register, Port E */ #define DDRE _SFR_IO8(0x02) /* Data Register, Port E */ #define PORTE _SFR_IO8(0x03) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* 0x1C..0x1F reserved */ /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Control Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt Mask register */ #define GIMSK _SFR_IO8(0x3B) /* Interrupt vectors */ #define SIG_INTERRUPT0 _VECTOR(1) #define SIG_INTERRUPT1 _VECTOR(2) #define SIG_TIMER1_CAPT1 _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) #define SIG_OUTPUT_COMPARE1B _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(7) #define SIG_SPI _VECTOR(8) #define SIG_UART_RECV _VECTOR(9) #define SIG_UART_DATA _VECTOR(10) #define SIG_UART_TRANS _VECTOR(11) #define SIG_USB_INT _VECTOR(12) #define _VECTORS_SIZE 52 /* The Register Bit names are represented by their bit number (0-7). */ /* Timer/Counter Interrupt MaSK register */ #define TICIE1 3 #define OCIE1A 6 #define OCIE1B 5 #define TOIE1 7 #define TOIE0 1 /* Timer/Counter Interrupt Flag Register */ #define ICF1 3 #define OCF1A 6 #define OCF1B 5 #define TOV1 7 #define TOV0 1 /* MCU general Control Register */ #define SE 5 #define SM 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Data Register, Port A */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Data Direction Register, Port A */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Input Pins, Port A */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Direction Register, Port C */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port C */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Data Register, Port E */ #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 /* Data Direction Register, Port E */ #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 /* Input Pins, Port E */ #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* Constants */ #define RAMEND 0x025F /*Last On-Chip SRAM Location*/ #define XRAMEND RAMEND #define E2END 0x0000 /* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory, but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now... */ #define FLASHEND 0x0FFFF #endif /* _AVR_43USB32X_H_ */ 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that may require special tools to rebuild." clean: clean-am clean-am: clean-generic mostlyclean-am distclean: distclean-am -rm -f Makefile distclean-am: clean-am distclean-generic distclean-tags dvi: dvi-am dvi-am: html: html-am html-am: info: info-am info-am: install-data-am: install-avrHEADERS install-nodist_avrHEADERS install-dvi: install-dvi-am install-dvi-am: install-exec-am: install-html: install-html-am install-html-am: install-info: install-info-am install-info-am: install-man: install-pdf: install-pdf-am install-pdf-am: install-ps: install-ps-am install-ps-am: installcheck-am: maintainer-clean: maintainer-clean-am -rm -f Makefile maintainer-clean-am: distclean-am maintainer-clean-generic mostlyclean: mostlyclean-am mostlyclean-am: mostlyclean-generic pdf: pdf-am pdf-am: ps: ps-am ps-am: uninstall-am: uninstall-avrHEADERS uninstall-nodist_avrHEADERS .MAKE: install-am install-strip .PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ ctags distclean distclean-generic distclean-tags distdir dvi \ dvi-am html html-am info info-am install install-am \ install-avrHEADERS install-data install-data-am install-dvi \ install-dvi-am install-exec install-exec-am install-html \ install-html-am install-info install-info-am install-man \ install-nodist_avrHEADERS install-pdf install-pdf-am \ install-ps install-ps-am install-strip installcheck \ installcheck-am installdirs maintainer-clean \ maintainer-clean-generic mostlyclean mostlyclean-generic pdf \ pdf-am ps ps-am tags uninstall uninstall-am \ uninstall-avrHEADERS uninstall-nodist_avrHEADERS version.h: version.h.in $(top_builddir)/config.h $(do_subst) < $(srcdir)/version.h.in > version.h # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: avr-libc-1.8.0.orig/include/avr/io90scr100.h0000644000000000000000000007757311732702554015172 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io90scr100.h 1910 2009-03-04 17:45:30Z arcanum $ */ /* avr/io90scr100.h - definitions for AT90SCR100 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io90scr100.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_AT90SCR100_H_ #define _AVR_AT90SCR100_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define PINE3 3 #define PINE4 4 #define PINE5 5 #define PINE6 6 #define PINE7 7 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define DDE3 3 #define DDE4 4 #define DDE5 5 #define DDE6 6 #define DDE7 7 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define PORTE3 3 #define PORTE4 4 #define PORTE5 5 #define PORTE6 6 #define PORTE7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define EIRR _SFR_IO8(0x1A) #define INTD2 2 #define INTD3 3 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 #define BODS 6 #define JTD 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define RAMPZ _SFR_IO8(0x3B) #define RAMPZ0 0 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PLLCR _SFR_MEM8(0x62) #define ON 0 #define LOCK 1 #define PLLMUX 7 #define SMONCR _SFR_MEM8(0x63) #define SMONEN 0 #define SMONIE 1 #define SMONIF 4 #define PRR0 _SFR_MEM8(0x64) #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define PRR1 _SFR_MEM8(0x65) #define PRUSBH 0 #define PRUSB 1 #define PRHSSPI 2 #define PRSCI 3 #define PRAES 4 #define PRKB 5 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #define PCMSK3 _SFR_MEM8(0x73) #define LEDCR _SFR_MEM8(0x75) #define LED00 0 #define LED01 1 #define LED10 2 #define LED11 3 #define LED20 4 #define LED21 5 #define lED30 6 #define LED31 7 #define AESCR _SFR_MEM8(0x78) #define AESGO 0 #define ENCRYPT 1 #define KS 3 #define KEYGN 4 #define AUTOKEY 5 #define AESIF 6 #define AESIE 7 #define AESACR _SFR_MEM8(0x79) #define KD 0 #define AUTOINC 1 #define MANINC 2 #define XOR 3 #define AESADDR _SFR_MEM8(0x7A) #define ADDR0 0 #define ADDR1 1 #define ADDR2 2 #define ADDR3 3 #define ADDR4 4 #define ADDR5 5 #define ADDR6 6 #define ADDR7 7 #define AESDR _SFR_MEM8(0x7B) #define DATA0 0 #define DATA1 1 #define DATA2 2 #define DATA3 3 #define DATA4 4 #define DATA5 5 #define DATA6 6 #define DATA7 7 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define KBLSR _SFR_MEM8(0x8D) #define KBLS0 0 #define KBLS1 1 #define KBLS2 2 #define KBLS3 3 #define KBLS4 4 #define KBLS5 5 #define KBLS6 6 #define KBLS7 7 #define KBER _SFR_MEM8(0x8E) #define KBE0 0 #define KBE1 1 #define KBE2 2 #define KBE3 3 #define KBE4 4 #define KBE5 5 #define KBE6 6 #define KBE7 7 #define KBFR _SFR_MEM8(0x8F) #define KBF0 0 #define KBF1 1 #define KBF2 2 #define KBF3 3 #define KBF4 4 #define KBF5 5 #define KBF6 6 #define KBF7 7 #define RDWDR _SFR_MEM8(0x90) #define RDD0 0 #define RDD1 1 #define RDD2 2 #define RDD3 3 #define RDD4 4 #define RDD5 5 #define RDD6 6 #define RDD7 7 #define LFSR0 _SFR_MEM8(0x91) #define LFSD0 0 #define LFSD1 1 #define LFSD2 2 #define LFSD3 3 #define LFSD4 4 #define LFSD5 5 #define LFSD6 6 #define LFSD7 7 #define LFSR1 _SFR_MEM8(0x92) #define LFSD8 0 #define LFSD9 1 #define LFSD10 2 #define LFSD11 3 #define LFSD12 4 #define LFSD13 5 #define LFSD14 6 #define LFSD15 7 #define LFSR2 _SFR_MEM8(0x93) #define LFSD16 0 #define LFSD17 1 #define LFSD18 2 #define LFSD19 3 #define LFSD20 4 #define LFSD21 5 #define LFSD22 6 #define LFSD23 7 #define LFSR3 _SFR_MEM8(0x94) #define LFSD24 0 #define LFSD25 1 #define LFSD26 2 #define LFSD27 3 #define LFSD28 4 #define LFSD29 5 #define LFSD30 6 #define LFSD31 7 #define RNGCR _SFR_MEM8(0x95) #define ROSCE 0 #define UHSR _SFR_MEM8(0x99) #define SPEED 3 #define UPINT _SFR_MEM8(0x9A) #define PINT0 0 #define PINT1 1 #define PINT2 2 #define PINT3 3 #define UPBCX _SFR_MEM16(0x9B) #define UPBCXL _SFR_MEM8(0x9B) #define PBYTCT0 0 #define PBYTCT1 1 #define PBYTCT2 2 #define PBYTCT3 3 #define PBYTCT4 4 #define PBYTCT5 5 #define PBYTCT6 6 #define PBYTCT7 7 #define UPBCXH _SFR_MEM8(0x9C) #define PBYTCT8 0 #define PBYTCT9 1 #define PBYTCT10 2 #define UPERRX _SFR_MEM8(0x9D) #define DATATGL 0 #define DATAPID 1 #define PID 2 #define PTIMEOUT 3 #define CRC16 4 #define COUNTER0 5 #define COUNTER1 6 #define UHCR _SFR_MEM8(0x9E) #define SOFEN 0 #define RESET 1 #define RESUME 2 #define FRZCLK 4 #define PAD0 5 #define PAD1 6 #define UHEN 7 #define UHINT _SFR_MEM8(0x9F) #define DCONNI 0 #define DDISCI 1 #define RSTI 2 #define RSMEDI 3 #define RXRSMI 4 #define HSOFI 5 #define HWUPI 6 #define UHIEN _SFR_MEM8(0xA0) #define DCONNE 0 #define DDISCE 1 #define RSTE 2 #define RSMEDE 3 #define RXRSME 4 #define HSOFE 5 #define HWUPE 6 #define UHADDR _SFR_MEM8(0xA1) #define HADDR0 0 #define HADDR1 1 #define HADDR2 2 #define HADDR3 3 #define HADDR4 4 #define HADDR5 5 #define HADDR6 6 #define UHFNUM _SFR_MEM16(0xA2) #define UHFNUML _SFR_MEM8(0xA2) #define FNUM0 0 #define FNUM1 1 #define FNUM2 2 #define FNUM3 3 #define FNUM4 4 #define FNUM5 5 #define FNUM6 6 #define FNUM7 7 #define UHFNUMH _SFR_MEM8(0xA3) #define FNUM8 0 #define FNUM9 1 #define FNUM10 2 #define UHFLEN _SFR_MEM8(0xA4) #define FLEN0 0 #define FLEN1 1 #define FLEN2 2 #define FLEN3 3 #define FLEN4 4 #define FLEN5 5 #define FLEN6 6 #define FLEN7 7 #define UPINRQX _SFR_MEM8(0xA5) #define INRQ0 0 #define INRQ1 1 #define INRQ2 2 #define INRQ3 3 #define INRQ4 4 #define INRQ5 5 #define INRQ6 6 #define INRQ7 7 #define UPINTX _SFR_MEM8(0xA6) #define RXINI 0 #define RXSTALLI 1 #define TXOUTI 2 #define TXSTPI 3 #define PERRI 4 #define RWAL 5 #define NAKEDI 6 #define FIFOCON 7 #define UPNUM _SFR_MEM8(0xA7) #define PNUM0 0 #define PNUM1 1 #define UPRST _SFR_MEM8(0xA8) #define P0RST 0 #define P1RST 1 #define P2RST 2 #define P3RST 3 #define UPCRX _SFR_MEM8(0xA9) #define PEN 0 #define RSTDT 3 #define INMODE 5 #define PFREEZE 6 #define UPCFG0X _SFR_MEM8(0xAA) #define PEPNUM0 0 #define PEPNUM1 1 #define PEPNUM2 2 #define PEPNUM3 3 #define PTOKEN0 4 #define PTOKEN1 5 #define PTYPE0 6 #define PTYPE1 7 #define UPCFG1X _SFR_MEM8(0xAB) #define ALLOC 1 #define PBK0 2 #define PBK1 3 #define PSIZE0 4 #define PSIZE1 5 #define PSIZE2 6 #define UPSTAX _SFR_MEM8(0xAC) #define NBUSYBK0 0 #define NBUSYBK1 1 #define DTSEQ0 2 #define DTSEQ1 3 #define UNDERFI 5 #define OVERFI 6 #define CFGOK 7 #define UPCFG2X _SFR_MEM8(0xAD) #define INTFRQ0 0 #define INTFRQ1 1 #define INTFRQ2 2 #define INTFRQ3 3 #define INTFRQ4 4 #define INTFRQ5 5 #define INTFRQ6 6 #define INTFRQ7 7 #define UPIENX _SFR_MEM8(0xAE) #define RXINE 0 #define RXSTALLE 1 #define TXOUTE 2 #define TXSTPE 3 #define PERRE 4 #define NAKEDE 6 #define FLERRE 7 #define UPDATX _SFR_MEM8(0xAF) #define PDAT0 0 #define PDAT1 1 #define PDAT2 2 #define PDAT3 3 #define PDAT4 4 #define PDAT5 5 #define PDAT6 6 #define PDAT7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2A0 0 #define OCR2A1 1 #define OCR2A2 2 #define OCR2A3 3 #define OCR2A4 4 #define OCR2A5 5 #define OCR2A6 6 #define OCR2A7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2B0 0 #define OCR2B1 1 #define OCR2B2 2 #define OCR2B3 3 #define OCR2B4 4 #define OCR2B5 5 #define OCR2B6 6 #define OCR2B7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL01 7 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR00 0 #define UBRR01 1 #define UBRR02 2 #define UBRR03 3 #define UBRR04 4 #define UBRR05 5 #define UBRR06 6 #define UBRR07 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR08 0 #define UBRR09 1 #define UBRR010 2 #define UBRR011 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR00 0 #define UDR01 1 #define UDR02 2 #define UDR03 3 #define UDR04 4 #define UDR05 5 #define UDR06 6 #define UDR07 7 #define USBENUM _SFR_MEM8(0xCA) #define USBENUM0 0 #define USBENUM1 1 #define USBENUM2 2 #define USBCSEX _SFR_MEM8(0xCB) #define TXC 0 #define RCVD 1 #define RXSETUP 2 #define STSENT 3 #define TXPB 4 #define FSTALL 5 #define IERR 6 #define USBDBCEX _SFR_MEM8(0xCC) #define BCT0 0 #define BCT1 1 #define BCT2 2 #define BCT3 3 #define BCT4 4 #define BCT5 5 #define BCT6 6 #define BCT7 7 #define USBFCEX _SFR_MEM8(0xCD) #define EPTYP0 0 #define EPTYP1 1 #define EPDIR 2 #define EPE 7 #define HSSPITO _SFR_MEM16(0xD1) #define HSSPITOL _SFR_MEM8(0xD1) #define HSSPITOD0 0 #define HSSPITOD1 1 #define HSSPITOD2 2 #define HSSPITOD3 3 #define HSSPITOD4 4 #define HSSPITOD5 5 #define HSSPITOD6 6 #define HSSPITOD7 7 #define HSSPITOH _SFR_MEM8(0xD2) #define HSSPITOD8 0 #define HSSPITOD9 1 #define HSSPITOD10 2 #define HSSPITOD11 3 #define HSSPITOD12 4 #define HSSPITOD13 5 #define HSSPITOD14 6 #define HSSPITOD15 7 #define HSSPICNT _SFR_MEM8(0xD3) #define HSSPICNTD0 0 #define HSSPICNTD1 1 #define HSSPICNTD2 2 #define HSSPICNTD3 3 #define HSSPICNTD4 4 #define HSSPIIER _SFR_MEM8(0xD4) #define NSSIE 4 #define RCVOFIE 5 #define BTDIE 6 #define TIMEOUTIE 7 #define HSSPIGTR _SFR_MEM8(0xD5) #define HSSPIGTD0 0 #define HSSPIGTD1 1 #define HSSPIGTD2 2 #define HSSPIGTD3 3 #define HSSPIGTD4 4 #define HSSPIGTD5 5 #define HSSPIGTD6 6 #define HSSPIGTD7 7 #define HSSPIRDR _SFR_MEM8(0xD6) #define HSSPIRDD0 0 #define HSSPIRDD1 1 #define HSSPIRDD2 2 #define HSSPIRDD3 3 #define HSSPIRDD4 4 #define HSSPIRDD5 5 #define HSSPIRDD6 6 #define HSSPIRDD7 7 #define HSSPITDR _SFR_MEM8(0xD7) #define HSSPITDD0 0 #define HSSPITDD1 1 #define HSSPITDD2 2 #define HSSPITDD3 3 #define HSSPITDD4 4 #define HSSPITDD5 5 #define HSSPITDD6 6 #define HSSPITDD7 7 #define HSSPISR _SFR_MEM8(0xD8) #define SPICKRDY 0 #define TXBUFE 1 #define RXBUFF 2 #define NSS 3 #define DPRAMRDY 4 #define HSSPICFG _SFR_MEM8(0xD9) #define HSSPIEN 0 #define HSMSTR 1 #define HSCPOL 2 #define HSCPHA 3 #define DPRAM 4 #define SPICKDIV0 5 #define SPICKDIV1 6 #define SPICKDIV2 7 #define HSSPIIR _SFR_MEM8(0xDA) #define NSSFE 3 #define NSSRE 4 #define RCVOF 5 #define BTD 6 #define TIMEOUT 7 #define HSSPICR _SFR_MEM8(0xDB) #define CS 0 #define RETTO 1 #define STTTO 2 #define HSSPIDMACS _SFR_MEM8(0xDC) #define HSSPIDMAR 0 #define HSSPIDMADIR 1 #define HSSPIDMAERR 2 #define HSSPIDMAD _SFR_MEM16(0xDD) #define HSSPIDMADL _SFR_MEM8(0xDD) #define HSSPIDMAD0 0 #define HSSPIDMAD1 1 #define HSSPIDMAD2 2 #define HSSPIDMAD3 3 #define HSSPIDMAD4 4 #define HSSPIDMAD5 5 #define HSSPIDMAD6 6 #define HSSPIDMAD7 7 #define HSSPIDMADH _SFR_MEM8(0xDE) #define HSSPIDMAD8 0 #define HSSPIDMAD9 1 #define HSSPIDMAD10 2 #define HSSPIDMAD11 3 #define HSSPIDMAD12 4 #define HSSPIDMAD13 5 #define HSSPIDMAB _SFR_MEM8(0xDF) #define HSSPIDMAB0 0 #define HSSPIDMAB1 1 #define HSSPIDMAB2 2 #define HSSPIDMAB3 3 #define HSSPIDMAB4 4 #define USBCR _SFR_MEM8(0xE0) #define USBE 1 #define UPUC 5 #define URMWU 7 #define USBPI _SFR_MEM8(0xE1) #define SUSI 0 #define RESI 1 #define RMWUI 2 #define SOFI 3 #define FEURI 4 #define USBPIM _SFR_MEM8(0xE2) #define SUSIM 0 #define RESIM 1 #define RMWUIM 2 #define SOFIM 3 #define USBEI _SFR_MEM8(0xE3) #define EP0I 0 #define EP1I 1 #define EP2I 2 #define EP3I 3 #define EP4I 4 #define EP5I 5 #define EP6I 6 #define EP7I 7 #define USBEIM _SFR_MEM8(0xE4) #define EP0IM 0 #define EP1IM 1 #define EP2IM 2 #define EP3IM 3 #define EP4IM 4 #define EP5IM 5 #define EP6IM 6 #define EP7IM 7 #define USBRSTE _SFR_MEM8(0xE5) #define RSTE0 0 #define RSTE1 1 #define RSTE2 2 #define RSTE3 3 #define RSTE4 4 #define RSTE5 5 #define RSTE6 6 #define RST7 7 #define USBGS _SFR_MEM8(0xE6) #define FAF 0 #define FCF 1 #define RMWUE 2 #define RSMON 3 #define USBFA _SFR_MEM8(0xE7) #define FADD0 0 #define FADD1 1 #define FADD2 2 #define FADD3 3 #define FADD4 4 #define FADD5 5 #define FADD6 6 #define USBFN _SFR_MEM16(0xE8) #define USBFNL _SFR_MEM8(0xE8) #define FN0 0 #define FN1 1 #define FN2 2 #define FN3 3 #define FN4 4 #define FN5 5 #define FN6 6 #define FN7 7 #define USBFNH _SFR_MEM8(0xE9) #define FN8 0 #define FN9 1 #define FN10 2 #define FNERR 3 #define FNEND 4 #define USBDMACS _SFR_MEM8(0xEA) #define USBDMAR 0 #define USBDMADIR 1 #define USBDMAERR 2 #define EPS0 4 #define EPS1 5 #define EPS2 6 #define USBDMAD _SFR_MEM16(0xEB) #define USBDMADL _SFR_MEM8(0xEB) #define USBDMAD0 0 #define USBDMAD1 1 #define USBDMAD2 2 #define USBDMAD3 3 #define USBDMAD4 4 #define USBDMAD5 5 #define USBDMAD6 6 #define USBDMAD7 7 #define USBDMADH _SFR_MEM8(0xEC) #define USBDMAD8 0 #define USBDMAD9 1 #define USBDMAD10 2 #define USBDMAD11 3 #define USBDMAD12 4 #define USBDMAD13 5 #define USBDMAB _SFR_MEM8(0xED) #define USBDMAB0 0 #define USBDMAB1 1 #define USBDMAB2 2 #define USBDMAB3 3 #define USBDMAB4 4 #define USBDMAB5 5 #define USBDMAB6 6 #define DCCR _SFR_MEM8(0xEF) #define DCBUSY 5 #define DCRDY 6 #define DCON 7 #define SCICLK _SFR_MEM8(0xF0) #define SCICLK0 0 #define SCICLK1 1 #define SCICLK2 2 #define SCICLK3 3 #define SCICLK4 4 #define SCICLK5 5 #define SCWT0 _SFR_MEM8(0xF1) #define WT0 0 #define WT1 1 #define WT2 2 #define WT3 3 #define WT4 4 #define WT5 5 #define WT6 6 #define WT7 7 #define SCWT1 _SFR_MEM8(0xF2) #define WT8 0 #define WT9 1 #define WT10 2 #define WT11 3 #define WT12 4 #define WT13 5 #define WT14 6 #define WT15 7 #define SCWT2 _SFR_MEM8(0xF3) #define WT16 0 #define WT17 1 #define WT18 2 #define WT19 3 #define WT20 4 #define WT21 5 #define WT22 6 #define WT23 7 #define SCWT3 _SFR_MEM8(0xF4) #define WT24 0 #define WT25 1 #define WT26 2 #define WT27 3 #define WT28 4 #define WT29 5 #define WT30 6 #define WT31 7 #define SCGT _SFR_MEM16(0xF5) #define SCGTL _SFR_MEM8(0xF5) #define GT0 0 #define GT1 1 #define GT2 2 #define GT3 3 #define GT4 4 #define GT5 5 #define GT6 6 #define GT7 7 #define SCGTH _SFR_MEM8(0xF6) #define GT8 0 #define SCETU _SFR_MEM16(0xF7) #define SCETUL _SFR_MEM8(0xF7) #define ETU0 0 #define ETU1 1 #define ETU2 2 #define ETU3 3 #define ETU4 4 #define ETU5 5 #define ETU6 6 #define ETU7 7 #define SCETUH _SFR_MEM8(0xF8) #define ETU8 0 #define ETU9 1 #define ETU10 2 #define COMP 7 #define SCIBUF _SFR_MEM8(0xF9) #define SCIBUFD0 0 #define SCIBUFD1 1 #define SCIBUFD2 2 #define SCIBUFD3 3 #define SCIBUFD4 4 #define SCIBUFD5 5 #define SCIBUFD6 6 #define SCIBUFD7 7 #define SCSR _SFR_MEM8(0xFA) #define CPRESRES 3 #define CREPSEL 4 #define BGTEN 6 #define SCIER _SFR_MEM8(0xFB) #define ESCPI 0 #define ESCRI 1 #define ESCTI 2 #define ESCWTI 3 #define EVCARDER 4 #define CARDINE 6 #define ESCTBI 7 #define SCIIR _SFR_MEM8(0xFC) #define SCPI 0 #define SCRI 1 #define SCTI 2 #define SCWTI 3 #define VCARDERR 4 #define SCTBI 7 #define SCISR _SFR_MEM8(0xFD) #define SCPE 0 #define SCRC 1 #define SCTC 2 #define SCWTO 3 #define VCARDOK 4 #define CARDIN 6 #define SCTBE 7 #define SCCON _SFR_MEM8(0xFE) #define CARDVCC 0 #define CARDRST 1 #define CARDCLK 2 #define CARDIO 3 #define CARDC4 4 #define CARDC8 5 #define CLK 7 #define SCICR _SFR_MEM8(0xFF) #define CONV 0 #define CREP 1 #define WTEN 2 #define UART 3 #define VCARD0 4 #define VCARD1 5 #define CARDDET 6 #define SCIRESET 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ #define PCINT0_vect_num 5 #define PCINT0_vect _VECTOR(5) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 6 #define PCINT1_vect _VECTOR(6) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 7 #define PCINT2_vect _VECTOR(7) /* Pin Change Interrupt Request 2 */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 9 #define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 10 #define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ #define TIMER2_OVF_vect_num 11 #define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 12 #define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 16 #define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 17 #define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 18 #define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 19 #define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ #define USART0_RX_vect_num 20 #define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ #define USART0_UDRE_vect_num 21 #define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ #define USART0_TX_vect_num 22 #define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ #define SUPPLY_MON_vect_num 23 #define SUPPLY_MON_vect _VECTOR(23) /* Supply Monitor Interruption */ #define RFU_vect_num 24 #define RFU_vect _VECTOR(24) /* Reserved for Future Use */ #define EE_READY_vect_num 25 #define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ #define TWI_vect_num 26 #define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ #define SPM_READY_vect_num 27 #define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ #define KEYBOARD_vect_num 28 #define KEYBOARD_vect _VECTOR(28) /* Keyboard Input Changed */ #define AES_Operation_vect_num 29 #define AES_Operation_vect _VECTOR(29) /* AES Block Operation Ended */ #define HSSPI_vect_num 30 #define HSSPI_vect _VECTOR(30) /* High-Speed SPI Interruption */ #define USB_Endpoint_vect_num 31 #define USB_Endpoint_vect _VECTOR(31) /* USB Endpoint Related Interruption */ #define USB_Protocol_vect_num 32 #define USB_Protocol_vect _VECTOR(32) /* USB Protocol Related Interruption */ #define SCIB_vect_num 33 #define SCIB_vect _VECTOR(33) /* Smart Card Reader Interface */ #define USBHost_Control_vect_num 34 #define USBHost_Control_vect _VECTOR(34) /* USB Host Controller Interrupt */ #define USBHost_Pipe_vect_num 35 #define USBHost_Pipe_vect _VECTOR(35) /* USB Host Pipe Interrupt */ #define CPRES_vect_num 36 #define CPRES_vect _VECTOR(36) /* Card Presence Detection */ #define PCINT3_vect_num 37 #define PCINT3_vect _VECTOR(37) /* Pin Change Interrupt Request 3 */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (38 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (256) #define RAMSTART (0x100) #define RAMSIZE (4096) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (0x0) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x7FF) #define E2PAGESIZE (4) #define FLASHEND (0xFFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Clock Selection */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Clock Selection */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define LFUSE_DEFAULT (FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODENABLE (unsigned char)~_BV(0) /* Brown-out Detector Enable Signal */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0xC1 #endif /* _AVR_AT90SCR100_H_ */ avr-libc-1.8.0.orig/include/avr/io90pwm3b.h0000644000000000000000000006746511732702554015211 0ustar /* Copyright (c) 2007 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io90pwm3b.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwm3b.h - definitions for AT90PWM3B */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io90pwm3b.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IO90PWM3B_H_ #define _AVR_IO90PWM3B_H_ 1 /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define GPIOR1 _SFR_IO8(0x19) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x1A) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define GPIOR3 _SFR_IO8(0x1B) #define GPIOR30 0 #define GPIOR31 1 #define GPIOR32 2 #define GPIOR33 3 #define GPIOR34 4 #define GPIOR35 5 #define GPIOR36 6 #define GPIOR37 7 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARL0 0 #define EEARL1 1 #define EEARL2 2 #define EEARL3 3 #define EEARL4 4 #define EEARL5 5 #define EEARL6 6 #define EEARL7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSRSYNC 0 #define ICPSEL1 2 #define TSM 3 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define OCR0_0 0 /* Deprecated */ #define OCR0_1 1 /* Deprecated */ #define OCR0_2 2 /* Deprecated */ #define OCR0_3 3 /* Deprecated */ #define OCR0_4 4 /* Deprecated */ #define OCR0_5 5 /* Deprecated */ #define OCR0_6 6 /* Deprecated */ #define OCR0_7 7 /* Deprecated */ #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLF 2 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define AC0O 0 #define AC1O 1 #define AC2O 2 #define AC0IF 4 #define AC1IF 5 #define AC2IF 6 #define ACCKDIV 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPIPS 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM0 3 #define PRTIM1 4 #define PRPSC0 5 #define PRPSC1 6 #define PRPSC2 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define AMP0CSR _SFR_MEM8(0x76) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 #define AMP1CSR _SFR_MEM8(0x77) #define AMP1TS0 0 #define AMP1TS1 1 #define AMP1G0 4 #define AMP1G1 5 #define AMP1IS 6 #define AMP1EN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define ADASCR 4 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define AMP0ND 3 #define AMP0PD 4 #define ACMP0D 5 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define PIFR0 _SFR_MEM8(0xA0) #define PEOP0 0 #define PRN00 1 #define PRN01 2 #define PEV0A 3 #define PEV0B 4 #define PSEI0 5 #define POAC0A 6 #define POAC0B 7 #define PIM0 _SFR_MEM8(0xA1) #define PEOPE0 0 #define PEVE0A 3 #define PEVE0B 4 #define PSEIE0 5 #define PIFR1 _SFR_MEM8(0xA2) #define PEOP1 0 #define PRN10 1 #define PRN11 2 #define PEV1A 3 #define PEV1B 4 #define PSEI1 5 #define POAC1A 6 #define POAC1B 7 #define PIM1 _SFR_MEM8(0xA3) #define PEOPE1 0 #define PEVE1A 3 #define PEVE1B 4 #define PSEIE1 5 #define PIFR2 _SFR_MEM8(0xA4) #define PEOP2 0 #define PRN20 1 #define PRN21 2 #define PEV2A 3 #define PEV2B 4 #define PSEI2 5 #define POAC2A 6 #define POAC2B 7 #define PIM2 _SFR_MEM8(0xA5) #define PEOPE2 0 #define PEVE2A 3 #define PEVE2B 4 #define PSEIE2 5 #define DACON _SFR_MEM8(0xAA) #define DAEN 0 #define DAOE 1 #define DALA 2 #define DATS0 4 #define DATS1 5 #define DATS2 6 #define DAATE 7 #define DAC _SFR_MEM16(0xAB) #define DACL _SFR_MEM8(0xAB) #define DACL0 0 #define DACL1 1 #define DACL2 2 #define DACL3 3 #define DACL4 4 #define DACL5 5 #define DACL6 6 #define DACL7 7 #define DACH _SFR_MEM8(0xAC) #define DACH0 0 #define DACH1 1 #define DACH2 2 #define DACH3 3 #define DACH4 4 #define DACH5 5 #define DACH6 6 #define DACH7 7 #define AC0CON _SFR_MEM8(0xAD) #define AC0M0 0 #define AC0M1 1 #define AC0M2 2 #define AC0IS0 4 #define AC0IS1 5 #define AC0IE 6 #define AC0EN 7 #define AC1CON _SFR_MEM8(0xAE) #define AC1M0 0 #define AC1M1 1 #define AC1M2 2 #define AC1ICE 3 #define AC1IS0 4 #define AC1IS1 5 #define AC1IE 6 #define AC1EN 7 #define AC2CON _SFR_MEM8(0xAF) #define AC2M0 0 #define AC2M1 1 #define AC2M2 2 #define AC2IS0 4 #define AC2IS1 5 #define AC2IE 6 #define AC2EN 7 #define UCSRA _SFR_MEM8(0xC0) #define MPCM 0 #define U2X 1 #define UPE 2 #define DOR 3 #define FE 4 #define UDRE 5 #define TXC 6 #define RXC 7 #define UCSRB _SFR_MEM8(0xC1) #define TXB8 0 #define RXB8 1 #define UCSZ2 2 #define TXEN 3 #define RXEN 4 #define UDRIE 5 #define TXCIE 6 #define RXCIE 7 #define UCSRC _SFR_MEM8(0xC2) #define UCPOL 0 #define UCSZ0 1 #define UCSZ1 2 #define USBS 3 #define UPM0 4 #define UPM1 5 #define UMSEL0 6 #define UBRR _SFR_MEM16(0xC4) #define UBRRL _SFR_MEM8(0xC4) #define UBRR0 0 #define UBRR1 1 #define UBRR2 2 #define UBRR3 3 #define UBRR4 4 #define UBRR5 5 #define UBRR6 6 #define UBRR7 7 #define UBRRH _SFR_MEM8(0xC5) #define UBRR8 0 #define UBRR9 1 #define UBRR10 2 #define UBRR11 3 #define UDR _SFR_MEM8(0xC6) #define UDR0 0 #define UDR1 1 #define UDR2 2 #define UDR3 3 #define UDR4 4 #define UDR5 5 #define UDR6 6 #define UDR7 7 #define EUCSRA _SFR_MEM8(0xC8) #define URxS0 0 #define URxS1 1 #define URxS2 2 #define URxS3 3 #define UTxS0 4 #define UTxS1 5 #define UTxS2 6 #define UTxS3 7 #define EUCSRB _SFR_MEM8(0xC9) #define BODR 0 #define EMCH 1 #define EUSBS 3 #define EUSART 4 #define EUCSRC _SFR_MEM8(0xCA) #define STP0 0 #define STP1 1 #define F1617 2 #define FEM 3 #define MUBRR _SFR_MEM16(0xCC) #define MUBRRL _SFR_MEM8(0xCC) #define MUBRR0 0 #define MUBRR1 1 #define MUBRR2 2 #define MUBRR3 3 #define MUBRR4 4 #define MUBRR5 5 #define MUBRR6 6 #define MUBRR7 7 #define MUBRRH _SFR_MEM8(0xCD) #define MUBRR8 0 #define MUBRR9 1 #define MUBRR10 2 #define MUBRR11 3 #define MUBRR12 4 #define MUBRR13 5 #define MUBRR14 6 #define MUBRR15 7 #define EUDR _SFR_MEM8(0xCE) #define EUDR0 0 #define EUDR1 1 #define EUDR2 2 #define EUDR3 3 #define EUDR4 4 #define EUDR5 5 #define EUDR6 6 #define EUDR7 7 #define PSOC0 _SFR_MEM8(0xD0) #define POEN0A 0 #define POEN0B 2 #define PSYNC00 4 #define PSYNC01 5 #define OCR0SA _SFR_MEM16(0xD2) #define OCR0SAL _SFR_MEM8(0xD2) #define OCR0SA_0 0 #define OCR0SA_1 1 #define OCR0SA_2 2 #define OCR0SA_3 3 #define OCR0SA_4 4 #define OCR0SA_5 5 #define OCR0SA_6 6 #define OCR0SA_7 7 #define OCR0SAH _SFR_MEM8(0xD3) #define OCR0SA_8 0 #define OCR0SA_9 1 #define OCR0SA_00 2 #define OCR0SA_01 3 #define OCR0RA _SFR_MEM16(0xD4) #define OCR0RAL _SFR_MEM8(0xD4) #define OCR0RA_0 0 #define OCR0RA_1 1 #define OCR0RA_2 2 #define OCR0RA_3 3 #define OCR0RA_4 4 #define OCR0RA_5 5 #define OCR0RA_6 6 #define OCR0RA_7 7 #define OCR0RAH _SFR_MEM8(0xD5) #define OCR0RA_8 0 #define OCR0RA_9 1 #define OCR0RA_00 2 #define OCR0RA_01 3 #define OCR0SB _SFR_MEM16(0xD6) #define OCR0SBL _SFR_MEM8(0xD6) #define OCR0SB_0 0 #define OCR0SB_1 1 #define OCR0SB_2 2 #define OCR0SB_3 3 #define OCR0SB_4 4 #define OCR0SB_5 5 #define OCR0SB_6 6 #define OCR0SB_7 7 #define OCR0SBH _SFR_MEM8(0xD7) #define OCR0SB_8 0 #define OCR0SB_9 1 #define OCR0SB_00 2 #define OCR0SB_01 3 #define OCR0RB _SFR_MEM16(0xD8) #define OCR0RBL _SFR_MEM8(0xD8) #define OCR0RB_0 0 #define OCR0RB_1 1 #define OCR0RB_2 2 #define OCR0RB_3 3 #define OCR0RB_4 4 #define OCR0RB_5 5 #define OCR0RB_6 6 #define OCR0RB_7 7 #define OCR0RBH _SFR_MEM8(0xD9) #define OCR0RB_8 0 #define OCR0RB_9 1 #define OCR0RB_00 2 #define OCR0RB_01 3 #define OCR0RB_02 4 #define OCR0RB_03 5 #define OCR0RB_04 6 #define OCR0RB_05 7 #define PCNF0 _SFR_MEM8(0xDA) #define PCLKSEL0 1 #define POP0 2 #define PMODE00 3 #define PMODE01 4 #define PLOCK0 5 #define PALOCK0 6 #define PFIFTY0 7 #define PCTL0 _SFR_MEM8(0xDB) #define PRUN0 0 #define PCCYC0 1 #define PARUN0 2 #define PAOC0A 3 #define PAOC0B 4 #define PBFM0 5 #define PPRE00 6 #define PPRE01 7 #define PFRC0A _SFR_MEM8(0xDC) #define PRFM0A0 0 #define PRFM0A1 1 #define PRFM0A2 2 #define PRFM0A3 3 #define PFLTE0A 4 #define PELEV0A 5 #define PISEL0A 6 #define PCAE0A 7 #define PFRC0B _SFR_MEM8(0xDD) #define PRFM0B0 0 #define PRFM0B1 1 #define PRFM0B2 2 #define PRFM0B3 3 #define PFLTE0B 4 #define PELEV0B 5 #define PISEL0B 6 #define PCAE0B 7 #define PICR0 _SFR_MEM16(0xDE) #define PICR0L _SFR_MEM8(0xDE) #define PICR0_0 0 #define PICR0_1 1 #define PICR0_2 2 #define PICR0_3 3 #define PICR0_4 4 #define PICR0_5 5 #define PICR0_6 6 #define PICR0_7 7 #define PICR0H _SFR_MEM8(0xDF) #define PICR0_8 0 #define PICR0_9 1 #define PICR0_10 2 #define PICR0_11 3 #define PCST0 7 #define PSOC1 _SFR_MEM8(0xE0) #define POEN1A 0 #define POEN1B 2 #define PSYNC1_0 4 #define PSYNC1_1 5 #define OCR1SA _SFR_MEM16(0xE2) #define OCR1SAL _SFR_MEM8(0xE2) #define OCR1SA_0 0 #define OCR1SA_1 1 #define OCR1SA_2 2 #define OCR1SA_3 3 #define OCR1SA_4 4 #define OCR1SA_5 5 #define OCR1SA_6 6 #define OCR1SA_7 7 #define OCR1SAH _SFR_MEM8(0xE3) #define OCR1SA_8 0 #define OCR1SA_9 1 #define OCR1SA_10 2 #define OCR1SA_11 3 #define OCR1RA _SFR_MEM16(0xE4) #define OCR1RAL _SFR_MEM8(0xE4) #define OCR1RA_0 0 #define OCR1RA_1 1 #define OCR1RA_2 2 #define OCR1RA_3 3 #define OCR1RA_4 4 #define OCR1RA_5 5 #define OCR1RA_6 6 #define OCR1RA_7 7 #define OCR1RAH _SFR_MEM8(0xE5) #define OCR1RA_8 0 #define OCR1RA_9 1 #define OCR1RA_10 2 #define OCR1RA_11 3 #define OCR1SB _SFR_MEM16(0xE6) #define OCR1SBL _SFR_MEM8(0xE6) #define OCR1SB_0 0 #define OCR1SB_1 1 #define OCR1SB_2 2 #define OCR1SB_3 3 #define OCR1SB_4 4 #define OCR1SB_5 5 #define OCR1SB_6 6 #define OCR1SB_7 7 #define OCR1SBH _SFR_MEM8(0xE7) #define OCR1SB_8 0 #define OCR1SB_9 1 #define OCR1SB_10 2 #define OCR1SB_11 3 #define OCR1RB _SFR_MEM16(0xE8) #define OCR1RBL _SFR_MEM8(0xE8) #define OCR1RB_0 0 #define OCR1RB_1 1 #define OCR1RB_2 2 #define OCR1RB_3 3 #define OCR1RB_4 4 #define OCR1RB_5 5 #define OCR1RB_6 6 #define OCR1RB_7 7 #define OCR1RBH _SFR_MEM8(0xE9) #define OCR1RB_8 0 #define OCR1RB_9 1 #define OCR1RB_10 2 #define OCR1RB_11 3 #define OCR1RB_12 4 #define OCR1RB_13 5 #define OCR1RB_14 6 #define OCR1RB_15 7 #define PCNF1 _SFR_MEM8(0xEA) #define PCLKSEL1 1 #define POP1 2 #define PMODE10 3 #define PMODE11 4 #define PLOCK1 5 #define PALOCK1 6 #define PFIFTY1 7 #define PCTL1 _SFR_MEM8(0xEB) #define PRUN1 0 #define PCCYC1 1 #define PARUN1 2 #define PAOC1A 3 #define PAOC1B 4 #define PBFM1 5 #define PPRE10 6 #define PPRE11 7 #define PFRC1A _SFR_MEM8(0xEC) #define PRFM1A0 0 #define PRFM1A1 1 #define PRFM1A2 2 #define PRFM1A3 3 #define PFLTE1A 4 #define PELEV1A 5 #define PISEL1A 6 #define PCAE1A 7 #define PFRC1B _SFR_MEM8(0xED) #define PRFM1B0 0 #define PRFM1B1 1 #define PRFM1B2 2 #define PRFM1B3 3 #define PFLTE1B 4 #define PELEV1B 5 #define PISEL1B 6 #define PCAE1B 7 #define PICR1 _SFR_MEM16(0xEE) #define PICR1L _SFR_MEM8(0xEE) #define PICR1_0 0 #define PICR1_1 1 #define PICR1_2 2 #define PICR1_3 3 #define PICR1_4 4 #define PICR1_5 5 #define PICR1_6 6 #define PICR1_7 7 #define PICR1H _SFR_MEM8(0xEF) #define PICR1_8 0 #define PICR1_9 1 #define PICR1_10 2 #define PICR1_11 3 #define PCST1 7 #define PSOC2 _SFR_MEM8(0xF0) #define POEN2A 0 #define POEN2C 1 #define POEN2B 2 #define POEN2D 3 #define PSYNC2_0 4 #define PSYNC2_1 5 #define POS22 6 #define POS23 7 #define POM2 _SFR_MEM8(0xF1) #define POMV2A0 0 #define POMV2A1 1 #define POMV2A2 2 #define POMV2A3 3 #define POMV2B0 4 #define POMV2B1 5 #define POMV2B2 6 #define POMV2B3 7 #define OCR2SA _SFR_MEM16(0xF2) #define OCR2SAL _SFR_MEM8(0xF2) #define OCR2SA_0 0 #define OCR2SA_1 1 #define OCR2SA_2 2 #define OCR2SA_3 3 #define OCR2SA_4 4 #define OCR2SA_5 5 #define OCR2SA_6 6 #define OCR2SA_7 7 #define OCR2SAH _SFR_MEM8(0xF3) #define OCR2SA_8 0 #define OCR2SA_9 1 #define OCR2SA_10 2 #define OCR2SA_11 3 #define OCR2RA _SFR_MEM16(0xF4) #define OCR2RAL _SFR_MEM8(0xF4) #define OCR2RA_0 0 #define OCR2RA_1 1 #define OCR2RA_2 2 #define OCR2RA_3 3 #define OCR2RA_4 4 #define OCR2RA_5 5 #define OCR2RA_6 6 #define OCR2RA_7 7 #define OCR2RAH _SFR_MEM8(0xF5) #define OCR2RA_8 0 #define OCR2RA_9 1 #define OCR2RA_10 2 #define OCR2RA_11 3 #define OCR2SB _SFR_MEM16(0xF6) #define OCR2SBL _SFR_MEM8(0xF6) #define OCR2SB_0 0 #define OCR2SB_1 1 #define OCR2SB_2 2 #define OCR2SB_3 3 #define OCR2SB_4 4 #define OCR2SB_5 5 #define OCR2SB_6 6 #define OCR2SB_7 7 #define OCR2SBH _SFR_MEM8(0xF7) #define OCR2SB_8 0 #define OCR2SB_9 1 #define OCR2SB_10 2 #define OCR2SB_11 3 #define OCR2RB _SFR_MEM16(0xF8) #define OCR2RBL _SFR_MEM8(0xF8) #define OCR2RB_0 0 #define OCR2RB_1 1 #define OCR2RB_2 2 #define OCR2RB_3 3 #define OCR2RB_4 4 #define OCR2RB_5 5 #define OCR2RB_6 6 #define OCR2RB_7 7 #define OCR2RBH _SFR_MEM8(0xF9) #define OCR2RB_8 0 #define OCR2RB_9 1 #define OCR2RB_10 2 #define OCR2RB_11 3 #define OCR2RB_12 4 #define OCR2RB_13 5 #define OCR2RB_14 6 #define OCR2RB_15 7 #define PCNF2 _SFR_MEM8(0xFA) #define POME2 0 #define PCLKSEL2 1 #define POP2 2 #define PMODE20 3 #define PMODE21 4 #define PLOCK2 5 #define PALOCK2 6 #define PFIFTY2 7 #define PCTL2 _SFR_MEM8(0xFB) #define PRUN2 0 #define PCCYC2 1 #define PARUN2 2 #define PAOC2A 3 #define PAOC2B 4 #define PBFM2 5 #define PPRE20 6 #define PPRE21 7 #define PFRC2A _SFR_MEM8(0xFC) #define PRFM2A0 0 #define PRFM2A1 1 #define PRFM2A2 2 #define PRFM2A3 3 #define PFLTE2A 4 #define PELEV2A 5 #define PISEL2A 6 #define PCAE2A 7 #define PFRC2B _SFR_MEM8(0xFD) #define PRFM2B0 0 #define PRFM2B1 1 #define PRFM2B2 2 #define PRFM2B3 3 #define PFLTE2B 4 #define PELEV2B 5 #define PISEL2B 6 #define PCAE2B 7 #define PICR2 _SFR_MEM16(0xFE) #define PICR2L _SFR_MEM8(0xFE) #define PICR2_0 0 #define PICR2_1 1 #define PICR2_2 2 #define PICR2_3 3 #define PICR2_4 4 #define PICR2_5 5 #define PICR2_6 6 #define PICR2_7 7 #define PICR2H _SFR_MEM8(0xFF) #define PICR2_8 0 #define PICR2_9 1 #define PICR2_10 2 #define PICR2_11 3 #define PCST2 7 /* Interrupt Vectors */ /* Interrupt vector 0 is the reset vector. */ #define PSC2_CAPT_vect_num 1 #define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ #define PSC2_EC_vect_num 2 #define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ #define PSC1_CAPT_vect_num 3 #define PSC1_CAPT_vect _VECTOR(3) /* PSC1 Capture Event */ #define PSC1_EC_vect_num 4 #define PSC1_EC_vect _VECTOR(4) /* PSC1 End Cycle */ #define PSC0_CAPT_vect_num 5 #define PSC0_CAPT_vect _VECTOR(5) /* PSC0 Capture Event */ #define PSC0_EC_vect_num 6 #define PSC0_EC_vect _VECTOR(6) /* PSC0 End Cycle */ #define ANALOG_COMP_0_vect_num 7 #define ANALOG_COMP_0_vect _VECTOR(7) /* Analog Comparator 0 */ #define ANALOG_COMP_1_vect_num 8 #define ANALOG_COMP_1_vect _VECTOR(8) /* Analog Comparator 1 */ #define ANALOG_COMP_2_vect_num 9 #define ANALOG_COMP_2_vect _VECTOR(9) /* Analog Comparator 2 */ #define INT0_vect_num 10 #define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter Compare Match B */ /* Vector 14, Reserved */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 16 #define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ #define ADC_vect_num 18 #define ADC_vect _VECTOR(18) /* ADC Conversion Complete */ #define INT1_vect_num 19 #define INT1_vect _VECTOR(19) /* External Interrupt Request 1 */ #define SPI_STC_vect_num 20 #define SPI_STC_vect _VECTOR(20) /* SPI Serial Transfer Complete */ #define USART_RX_vect_num 21 #define USART_RX_vect _VECTOR(21) /* USART, Rx Complete */ #define USART_UDRE_vect_num 22 #define USART_UDRE_vect _VECTOR(22) /* USART Data Register Empty */ #define USART_TX_vect_num 23 #define USART_TX_vect _VECTOR(23) /* USART, Tx Complete */ #define INT2_vect_num 24 #define INT2_vect _VECTOR(24) /* External Interrupt Request 2 */ #define WDT_vect_num 25 #define WDT_vect _VECTOR(25) /* Watchdog Timeout Interrupt */ #define EE_READY_vect_num 26 #define EE_READY_vect _VECTOR(26) /* EEPROM Ready */ #define TIMER0_COMPB_vect_num 27 #define TIMER0_COMPB_vect _VECTOR(27) /* Timer Counter 0 Compare Match B */ #define INT3_vect_num 28 #define INT3_vect _VECTOR(28) /* External Interrupt Request 3 */ /* Vector 29, Reserved */ /* Vector 30, Reserved */ #define SPM_READY_vect_num 31 #define SPM_READY_vect _VECTOR(31) /* Store Program Memory Read */ #define _VECTORS_SIZE 64 /* Memory Sizes */ #define RAMEND 0x2FF #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF #define SPM_PAGESIZE 64 /* Fuse Information */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ #define FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ #define FUSE_PSC1RB (unsigned char)~_BV(6) /* PSC1 Reset Behaviour */ #define FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x83 #endif /* _AVR_IO90PWM3B_H_ */ avr-libc-1.8.0.orig/include/avr/iousb82.h0000644000000000000000000000645411732702554014742 0ustar /* Copyright (c) 2007 Anatoly Sokolov Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iousb82.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/iousb82.h - definitions for AT90USB82 */ #ifndef _AVR_AT90USB82_H_ #define _AVR_AT90USB82_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x2FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_RSTDSBL (unsigned char)~_BV(6) #define FUSE_DWEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_HWBE (unsigned char)~_BV(3) #define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST #endif /* _AVR_AT90USB82_H_ */ avr-libc-1.8.0.orig/include/avr/iotn88.h0000644000000000000000000003620011732702554014570 0ustar /* Copyright (c) 2007 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn88.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iotn88.h - definitions for ATtiny88 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn88.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOTN88_H_ #define _AVR_IOTN88_H_ 1 /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINA _SFR_IO8(0x0C) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define DDRA _SFR_IO8(0x0D) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define PORTA _SFR_IO8(0x0E) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTCR _SFR_IO8(0x12) #define PUDA 0 #define PUDB 1 #define PUDC 2 #define PUDD 3 #define BBMA 4 #define BBMB 5 #define BBMC 6 #define BBMD 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define CTC0 3 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define PUD 4 #define BODSE 5 #define BODS 6 #define SPMCSR _SFR_IO8(0x37) #define SELFPRGEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define RWWSB 6 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTWI 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK3 _SFR_MEM8(0x6A) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define PCINT27 3 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define TWHSR _SFR_MEM8(0xBE) #define TWIHS 0 /* Interrupt Vectors */ /* Interrupt vector 0 is the reset vector. */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) #define PCINT2_vect_num 5 #define PCINT2_vect _VECTOR(5) #define PCINT3_vect_num 6 #define PCINT3_vect _VECTOR(6) #define WDT_vect_num 7 #define WDT_vect _VECTOR(7) #define TIMER1_CAPT_vect_num 8 #define TIMER1_CAPT_vect _VECTOR(8) #define TIMER1_COMPA_vect_num 9 #define TIMER1_COMPA_vect _VECTOR(9) #define TIMER1_COMPB_vect_num 10 #define TIMER1_COMPB_vect _VECTOR(10) #define TIMER1_OVF_vect_num 11 #define TIMER1_OVF_vect _VECTOR(11) #define TIMER0_COMPA_vect_num 12 #define TIMER0_COMPA_vect _VECTOR(12) #define TIMER0_COMPB_vect_num 13 #define TIMER0_COMPB_vect _VECTOR(13) #define TIMER0_OVF_vect_num 14 #define TIMER0_OVF_vect _VECTOR(14) #define SPI_STC_vect_num 15 #define SPI_STC_vect _VECTOR(15) #define ADC_vect_num 16 #define ADC_vect _VECTOR(16) #define EE_READY_vect_num 17 #define EE_READY_vect _VECTOR(17) #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define TWI_vect_num 19 #define TWI_vect _VECTOR(19) #define _VECTORS_SIZE 40 /* Constants */ #define RAMEND 0x2FF #define RAMSTART (0x100) #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x3F #define E2PAGESIZE 4 #define FLASHEND 0x1FFF #define SPM_PAGESIZE 32 /* Fuse Information */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN ~_BV(0) /* Self Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x11 #endif /* _AVR_IOTN88_H_ */ avr-libc-1.8.0.orig/include/avr/boot.h0000644000000000000000000006267511732702554014421 0ustar /* Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: boot.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ #ifndef _AVR_BOOT_H_ #define _AVR_BOOT_H_ 1 /** \file */ /** \defgroup avr_boot : Bootloader Support Utilities \code #include #include \endcode The macros in this module provide a C language interface to the bootloader support functionality of certain AVR processors. These macros are designed to work with all sizes of flash memory. Global interrupts are not automatically disabled for these macros. It is left up to the programmer to do this. See the code example below. Also see the processor datasheet for caveats on having global interrupts enabled during writing of the Flash. \note Not all AVR processors provide bootloader support. See your processor datasheet to see if it provides bootloader support. \todo From email with Marek: On smaller devices (all except ATmega64/128), __SPM_REG is in the I/O space, accessible with the shorter "in" and "out" instructions - since the boot loader has a limited size, this could be an important optimization. \par API Usage Example The following code shows typical usage of the boot API. \code #include #include #include void boot_program_page (uint32_t page, uint8_t *buf) { uint16_t i; uint8_t sreg; // Disable interrupts. sreg = SREG; cli(); eeprom_busy_wait (); boot_page_erase (page); boot_spm_busy_wait (); // Wait until the memory is erased. for (i=0; i #include #include #include /* Check for SPM Control Register in processor. */ #if defined (SPMCSR) # define __SPM_REG SPMCSR #elif defined (SPMCR) # define __SPM_REG SPMCR #else # error AVR processor does not provide bootloader support! #endif /* Check for SPM Enable bit. */ #if defined(SPMEN) # define __SPM_ENABLE SPMEN #elif defined(SELFPRGEN) # define __SPM_ENABLE SELFPRGEN #else # error Cannot find SPM Enable bit definition! #endif /** \ingroup avr_boot \def BOOTLOADER_SECTION Used to declare a function or variable to be placed into a new section called .bootloader. This section and its contents can then be relocated to any address (such as the bootloader NRWW area) at link-time. */ #define BOOTLOADER_SECTION __attribute__ ((section (".bootloader"))) /* Create common bit definitions. */ #ifdef ASB #define __COMMON_ASB ASB #else #define __COMMON_ASB RWWSB #endif #ifdef ASRE #define __COMMON_ASRE ASRE #else #define __COMMON_ASRE RWWSRE #endif /* Define the bit positions of the Boot Lock Bits. */ #define BLB12 5 #define BLB11 4 #define BLB02 3 #define BLB01 2 /** \ingroup avr_boot \def boot_spm_interrupt_enable() Enable the SPM interrupt. */ #define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE)) /** \ingroup avr_boot \def boot_spm_interrupt_disable() Disable the SPM interrupt. */ #define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE)) /** \ingroup avr_boot \def boot_is_spm_interrupt() Check if the SPM interrupt is enabled. */ #define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE)) /** \ingroup avr_boot \def boot_rww_busy() Check if the RWW section is busy. */ #define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB)) /** \ingroup avr_boot \def boot_spm_busy() Check if the SPM instruction is busy. */ #define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE)) /** \ingroup avr_boot \def boot_spm_busy_wait() Wait while the SPM instruction is busy. */ #define boot_spm_busy_wait() do{}while(boot_spm_busy()) #define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS)) #define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT)) #define __BOOT_PAGE_FILL _BV(__SPM_ENABLE) #define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE)) #if defined(BLBSET) #define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET)) #elif defined(RFLB) /* Some devices have RFLB defined instead of BLBSET. */ #define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RFLB)) #endif #define __boot_page_fill_normal(address, data) \ (__extension__({ \ __asm__ __volatile__ \ ( \ "movw r0, %3\n\t" \ "sts %0, %1\n\t" \ "spm\n\t" \ "clr r1\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_PAGE_FILL)), \ "z" ((uint16_t)(address)), \ "r" ((uint16_t)(data)) \ : "r0" \ ); \ })) #define __boot_page_fill_alternate(address, data)\ (__extension__({ \ __asm__ __volatile__ \ ( \ "movw r0, %3\n\t" \ "sts %0, %1\n\t" \ "spm\n\t" \ ".word 0xffff\n\t" \ "nop\n\t" \ "clr r1\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_PAGE_FILL)), \ "z" ((uint16_t)(address)), \ "r" ((uint16_t)(data)) \ : "r0" \ ); \ })) #define __boot_page_fill_extended(address, data) \ (__extension__({ \ __asm__ __volatile__ \ ( \ "movw r0, %4\n\t" \ "movw r30, %A3\n\t" \ "sts %1, %C3\n\t" \ "sts %0, %2\n\t" \ "spm\n\t" \ "clr r1\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "i" (_SFR_MEM_ADDR(RAMPZ)), \ "r" ((uint8_t)(__BOOT_PAGE_FILL)), \ "r" ((uint32_t)(address)), \ "r" ((uint16_t)(data)) \ : "r0", "r30", "r31" \ ); \ })) #define __boot_page_erase_normal(address) \ (__extension__({ \ __asm__ __volatile__ \ ( \ "sts %0, %1\n\t" \ "spm\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ "z" ((uint16_t)(address)) \ ); \ })) #define __boot_page_erase_alternate(address) \ (__extension__({ \ __asm__ __volatile__ \ ( \ "sts %0, %1\n\t" \ "spm\n\t" \ ".word 0xffff\n\t" \ "nop\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ "z" ((uint16_t)(address)) \ ); \ })) #define __boot_page_erase_extended(address) \ (__extension__({ \ __asm__ __volatile__ \ ( \ "movw r30, %A3\n\t" \ "sts %1, %C3\n\t" \ "sts %0, %2\n\t" \ "spm\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "i" (_SFR_MEM_ADDR(RAMPZ)), \ "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \ "r" ((uint32_t)(address)) \ : "r30", "r31" \ ); \ })) #define __boot_page_write_normal(address) \ (__extension__({ \ __asm__ __volatile__ \ ( \ "sts %0, %1\n\t" \ "spm\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ "z" ((uint16_t)(address)) \ ); \ })) #define __boot_page_write_alternate(address) \ (__extension__({ \ __asm__ __volatile__ \ ( \ "sts %0, %1\n\t" \ "spm\n\t" \ ".word 0xffff\n\t" \ "nop\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ "z" ((uint16_t)(address)) \ ); \ })) #define __boot_page_write_extended(address) \ (__extension__({ \ __asm__ __volatile__ \ ( \ "movw r30, %A3\n\t" \ "sts %1, %C3\n\t" \ "sts %0, %2\n\t" \ "spm\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "i" (_SFR_MEM_ADDR(RAMPZ)), \ "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \ "r" ((uint32_t)(address)) \ : "r30", "r31" \ ); \ })) #define __boot_rww_enable() \ (__extension__({ \ __asm__ __volatile__ \ ( \ "sts %0, %1\n\t" \ "spm\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \ ); \ })) #define __boot_rww_enable_alternate() \ (__extension__({ \ __asm__ __volatile__ \ ( \ "sts %0, %1\n\t" \ "spm\n\t" \ ".word 0xffff\n\t" \ "nop\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \ ); \ })) /* From the mega16/mega128 data sheets (maybe others): Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write "X0001001" to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU. If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is don't care during this operation, but for future compatibility it is recommended to load the Z-pointer with $0001 (same as used for reading the Lock bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the Lock bits the entire Flash can be read during the operation. */ #define __boot_lock_bits_set(lock_bits) \ (__extension__({ \ uint8_t value = (uint8_t)(~(lock_bits)); \ __asm__ __volatile__ \ ( \ "ldi r30, 1\n\t" \ "ldi r31, 0\n\t" \ "mov r0, %2\n\t" \ "sts %0, %1\n\t" \ "spm\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ "r" (value) \ : "r0", "r30", "r31" \ ); \ })) #define __boot_lock_bits_set_alternate(lock_bits) \ (__extension__({ \ uint8_t value = (uint8_t)(~(lock_bits)); \ __asm__ __volatile__ \ ( \ "ldi r30, 1\n\t" \ "ldi r31, 0\n\t" \ "mov r0, %2\n\t" \ "sts %0, %1\n\t" \ "spm\n\t" \ ".word 0xffff\n\t" \ "nop\n\t" \ : \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ "r" (value) \ : "r0", "r30", "r31" \ ); \ })) /* Reading lock and fuse bits: Similarly to writing the lock bits above, set BLBSET and SPMEN (or SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an LPM instruction. Z address: contents: 0x0000 low fuse bits 0x0001 lock bits 0x0002 extended fuse bits 0x0003 high fuse bits Sounds confusing, doesn't it? Unlike the macros in pgmspace.h, no need to care for non-enhanced cores here as these old cores do not provide SPM support anyway. */ /** \ingroup avr_boot \def GET_LOW_FUSE_BITS address to read the low fuse bits, using boot_lock_fuse_bits_get */ #define GET_LOW_FUSE_BITS (0x0000) /** \ingroup avr_boot \def GET_LOCK_BITS address to read the lock bits, using boot_lock_fuse_bits_get */ #define GET_LOCK_BITS (0x0001) /** \ingroup avr_boot \def GET_EXTENDED_FUSE_BITS address to read the extended fuse bits, using boot_lock_fuse_bits_get */ #define GET_EXTENDED_FUSE_BITS (0x0002) /** \ingroup avr_boot \def GET_HIGH_FUSE_BITS address to read the high fuse bits, using boot_lock_fuse_bits_get */ #define GET_HIGH_FUSE_BITS (0x0003) /** \ingroup avr_boot \def boot_lock_fuse_bits_get(address) Read the lock or fuse bits at \c address. Parameter \c address can be any of GET_LOW_FUSE_BITS, GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS. \note The lock and fuse bits returned are the physical values, i.e. a bit returned as 0 means the corresponding fuse or lock bit is programmed. */ #define boot_lock_fuse_bits_get(address) \ (__extension__({ \ uint8_t __result; \ __asm__ __volatile__ \ ( \ "sts %1, %2\n\t" \ "lpm %0, Z\n\t" \ : "=r" (__result) \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \ "z" ((uint16_t)(address)) \ ); \ __result; \ })) /** \ingroup avr_boot \def boot_signature_byte_get(address) Read the Signature Row byte at \c address. For some MCU types, this function can also retrieve the factory-stored oscillator calibration bytes. Parameter \c address can be 0-0x1f as documented by the datasheet. \note The values are MCU type dependent. */ #define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD)) #define boot_signature_byte_get(addr) \ (__extension__({ \ uint8_t __result; \ __asm__ __volatile__ \ ( \ "sts %1, %2\n\t" \ "lpm %0, Z" "\n\t" \ : "=r" (__result) \ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ "r" ((uint8_t)(__BOOT_SIGROW_READ)), \ "z" ((uint16_t)(addr)) \ ); \ __result; \ })) /** \ingroup avr_boot \def boot_page_fill(address, data) Fill the bootloader temporary page buffer for flash address with data word. \note The address is a byte address. The data is a word. The AVR writes data to the buffer a word at a time, but addresses the buffer per byte! So, increment your address by 2 between calls, and send 2 data bytes in a word format! The LSB of the data is written to the lower address; the MSB of the data is written to the higher address.*/ /** \ingroup avr_boot \def boot_page_erase(address) Erase the flash page that contains address. \note address is a byte address in flash, not a word address. */ /** \ingroup avr_boot \def boot_page_write(address) Write the bootloader temporary page buffer to flash page that contains address. \note address is a byte address in flash, not a word address. */ /** \ingroup avr_boot \def boot_rww_enable() Enable the Read-While-Write memory section. */ /** \ingroup avr_boot \def boot_lock_bits_set(lock_bits) Set the bootloader lock bits. \param lock_bits A mask of which Boot Loader Lock Bits to set. \note In this context, a 'set bit' will be written to a zero value. Note also that only BLBxx bits can be programmed by this command. For example, to disallow the SPM instruction from writing to the Boot Loader memory section of flash, you would use this macro as such: \code boot_lock_bits_set (_BV (BLB11)); \endcode \note Like any lock bits, the Boot Loader Lock Bits, once set, cannot be cleared again except by a chip erase which will in turn also erase the boot loader itself. */ /* Normal versions of the macros use 16-bit addresses. Extended versions of the macros use 32-bit addresses. Alternate versions of the macros use 16-bit addresses and require special instruction sequences after LPM. FLASHEND is defined in the ioXXXX.h file. USHRT_MAX is defined in . */ #if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \ || defined(__AVR_ATmega323__) /* Alternate: ATmega161/163/323 and 16 bit address */ #define boot_page_fill(address, data) __boot_page_fill_alternate(address, data) #define boot_page_erase(address) __boot_page_erase_alternate(address) #define boot_page_write(address) __boot_page_write_alternate(address) #define boot_rww_enable() __boot_rww_enable_alternate() #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits) #elif (FLASHEND > USHRT_MAX) /* Extended: >16 bit address */ #define boot_page_fill(address, data) __boot_page_fill_extended(address, data) #define boot_page_erase(address) __boot_page_erase_extended(address) #define boot_page_write(address) __boot_page_write_extended(address) #define boot_rww_enable() __boot_rww_enable() #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) #else /* Normal: 16 bit address */ #define boot_page_fill(address, data) __boot_page_fill_normal(address, data) #define boot_page_erase(address) __boot_page_erase_normal(address) #define boot_page_write(address) __boot_page_write_normal(address) #define boot_rww_enable() __boot_rww_enable() #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) #endif /** \ingroup avr_boot Same as boot_page_fill() except it waits for eeprom and spm operations to complete before filling the page. */ #define boot_page_fill_safe(address, data) \ do { \ boot_spm_busy_wait(); \ eeprom_busy_wait(); \ boot_page_fill(address, data); \ } while (0) /** \ingroup avr_boot Same as boot_page_erase() except it waits for eeprom and spm operations to complete before erasing the page. */ #define boot_page_erase_safe(address) \ do { \ boot_spm_busy_wait(); \ eeprom_busy_wait(); \ boot_page_erase (address); \ } while (0) /** \ingroup avr_boot Same as boot_page_write() except it waits for eeprom and spm operations to complete before writing the page. */ #define boot_page_write_safe(address) \ do { \ boot_spm_busy_wait(); \ eeprom_busy_wait(); \ boot_page_write (address); \ } while (0) /** \ingroup avr_boot Same as boot_rww_enable() except waits for eeprom and spm operations to complete before enabling the RWW mameory. */ #define boot_rww_enable_safe() \ do { \ boot_spm_busy_wait(); \ eeprom_busy_wait(); \ boot_rww_enable(); \ } while (0) /** \ingroup avr_boot Same as boot_lock_bits_set() except waits for eeprom and spm operations to complete before setting the lock bits. */ #define boot_lock_bits_set_safe(lock_bits) \ do { \ boot_spm_busy_wait(); \ eeprom_busy_wait(); \ boot_lock_bits_set (lock_bits); \ } while (0) #endif /* _AVR_BOOT_H_ */ avr-libc-1.8.0.orig/include/avr/iomx8.h0000644000000000000000000004204711732702554014511 0ustar /* Copyright (c) 2004,2005, Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iomx8.h 2235 2011-03-17 04:13:14Z arcanum $ */ /* avr/iomx8.h - definitions for ATmega48, ATmega88 and ATmega168 */ #ifndef _AVR_IOMX8_H_ #define _AVR_IOMX8_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iomx8.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Port B */ #define PINB _SFR_IO8 (0x03) /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8 (0x04) /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8 (0x05) /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Port C */ #define PINC _SFR_IO8 (0x06) /* PINC */ #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8 (0x07) /* DDRC */ #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8 (0x08) /* PORTC */ #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Port D */ #define PIND _SFR_IO8 (0x09) /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8 (0x0A) /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8 (0x0B) /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define TIFR0 _SFR_IO8 (0x15) /* TIFR0 */ #define OCF0B 2 #define OCF0A 1 #define TOV0 0 #define TIFR1 _SFR_IO8 (0x16) /* TIFR1 */ #define ICF1 5 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 #define TIFR2 _SFR_IO8 (0x17) /* TIFR2 */ #define OCF2B 2 #define OCF2A 1 #define TOV2 0 #define PCIFR _SFR_IO8 (0x1B) /* PCIFR */ #define PCIF2 2 #define PCIF1 1 #define PCIF0 0 #define EIFR _SFR_IO8 (0x1C) /* EIFR */ #define INTF1 1 #define INTF0 0 #define EIMSK _SFR_IO8 (0x1D) /* EIMSK */ #define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8 (0x1E) #define EECR _SFR_IO8(0x1F) /* EECT - EEPROM Control Register */ #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* Even though EEARH is not used by the mega48, the EEAR8 bit in the register must be written to 0, according to the datasheet, hence the EEARH register must be defined for the mega48. */ /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8 (0x23) /* GTCCR */ #define TSM 7 #define PSRASY 1 #define PSRSYNC 0 #define TCCR0A _SFR_IO8 (0x24) /* TCCR0A */ #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 #define TCCR0B _SFR_IO8 (0x25) /* TCCR0A */ #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 #define TCNT0 _SFR_IO8 (0x26) #define OCR0A _SFR_IO8 (0x27) #define OCR0B _SFR_IO8 (0x28) #define GPIOR1 _SFR_IO8 (0x2A) #define GPIOR2 _SFR_IO8 (0x2B) #define SPCR _SFR_IO8 (0x2C) /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 #define SPSR _SFR_IO8 (0x2D) /* SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 #define SPDR _SFR_IO8 (0x2E) #define ACSR _SFR_IO8 (0x30) /* ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 #define MONDR _SFR_IO8 (0x31) #define SMCR _SFR_IO8 (0x33) /* SMCR */ #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 #define MCUSR _SFR_IO8 (0x34) /* MCUSR */ #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 #define MCUCR _SFR_IO8 (0x35) /* MCUCR */ #define PUD 4 #if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) #define IVSEL 1 #define IVCE 0 #endif #define SPMCSR _SFR_IO8 (0x37) /* SPMCSR */ #define SPMIE 7 #if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) # define RWWSB 6 # define RWWSRE 4 #endif #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SELFPRGEN 0 #define SPMEN 0 /* 0x3D..0x3E SP [defined in ] */ /* 0x3F SREG [defined in ] */ #define WDTCSR _SFR_MEM8 (0x60) /* WDTCSR */ #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 #define CLKPR _SFR_MEM8 (0x61) /* CLKPR */ #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 #define PRR _SFR_MEM8 (0x64) /* PRR */ #define PRTWI 7 #define PRTIM2 6 #define PRTIM0 5 #define PRTIM1 3 #define PRSPI 2 #define PRUSART0 1 #define PRADC 0 #define OSCCAL _SFR_MEM8 (0x66) #define PCICR _SFR_MEM8 (0x68) /* PCICR */ #define PCIE2 2 #define PCIE1 1 #define PCIE0 0 #define EICRA _SFR_MEM8 (0x69) /* EICRA */ #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 #define PCMSK0 _SFR_MEM8 (0x6B) /* PCMSK0 */ #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 #define PCMSK1 _SFR_MEM8 (0x6C) /* PCMSK1 */ #define PCINT14 6 #define PCINT13 5 #define PCINT12 4 #define PCINT11 3 #define PCINT10 2 #define PCINT9 1 #define PCINT8 0 #define PCMSK2 _SFR_MEM8 (0x6D) /* PCMSK2 */ #define PCINT23 7 #define PCINT22 6 #define PCINT21 5 #define PCINT20 4 #define PCINT19 3 #define PCINT18 2 #define PCINT17 1 #define PCINT16 0 #define TIMSK0 _SFR_MEM8 (0x6E) /* TIMSK0 */ #define OCIE0B 2 #define OCIE0A 1 #define TOIE0 0 #define TIMSK1 _SFR_MEM8 (0x6F) /* TIMSK1 */ #define ICIE1 5 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 #define TIMSK2 _SFR_MEM8 (0x70) /* TIMSK2 */ #define OCIE2B 2 #define OCIE2A 1 #define TOIE2 0 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16 (0x78) #endif #define ADCW _SFR_MEM16 (0x78) #define ADCL _SFR_MEM8 (0x78) #define ADCH _SFR_MEM8 (0x79) #define ADCSRA _SFR_MEM8 (0x7A) /* ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 #define ADCSRB _SFR_MEM8 (0x7B) /* ADCSRB */ #define ACME 6 #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 #define ADMUX _SFR_MEM8 (0x7C) /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 #define DIDR0 _SFR_MEM8 (0x7E) /* DIDR0 */ #define ADC5D 5 #define ADC4D 4 #define ADC3D 3 #define ADC2D 2 #define ADC1D 1 #define ADC0D 0 #define DIDR1 _SFR_MEM8 (0x7F) /* DIDR1 */ #define AIN1D 1 #define AIN0D 0 #define TCCR1A _SFR_MEM8 (0x80) /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define WGM11 1 #define WGM10 0 #define TCCR1B _SFR_MEM8 (0x81) /* TCCR1B */ #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 #define TCCR1C _SFR_MEM8 (0x82) /* TCCR1C */ #define FOC1A 7 #define FOC1B 6 #define TCNT1 _SFR_MEM16 (0x84) #define TCNT1L _SFR_MEM8 (0x84) #define TCNT1H _SFR_MEM8 (0x85) #define ICR1 _SFR_MEM16 (0x86) #define ICR1L _SFR_MEM8 (0x86) #define ICR1H _SFR_MEM8 (0x87) #define OCR1A _SFR_MEM16 (0x88) #define OCR1AL _SFR_MEM8 (0x88) #define OCR1AH _SFR_MEM8 (0x89) #define OCR1B _SFR_MEM16 (0x8A) #define OCR1BL _SFR_MEM8 (0x8A) #define OCR1BH _SFR_MEM8 (0x8B) #define TCCR2A _SFR_MEM8 (0xB0) /* TCCR2A */ #define COM2A1 7 #define COM2A0 6 #define COM2B1 5 #define COM2B0 4 #define WGM21 1 #define WGM20 0 #define TCCR2B _SFR_MEM8 (0xB1) /* TCCR2B */ #define FOC2A 7 #define FOC2B 6 #define WGM22 3 #define CS22 2 #define CS21 1 #define CS20 0 #define TCNT2 _SFR_MEM8 (0xB2) #define OCR2A _SFR_MEM8 (0xB3) #define OCR2B _SFR_MEM8 (0xB4) #define ASSR _SFR_MEM8 (0xB6) /* ASSR */ #define EXCLK 6 #define AS2 5 #define TCN2UB 4 #define OCR2AUB 3 #define OCR2BUB 2 #define TCR2AUB 1 #define TCR2BUB 0 #define TWBR _SFR_MEM8 (0xB8) #define TWSR _SFR_MEM8 (0xB9) /* TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 #define TWAR _SFR_MEM8 (0xBA) /* TWAR */ #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 #define TWDR _SFR_MEM8 (0xBB) #define TWCR _SFR_MEM8 (0xBC) /* TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 #define TWAMR _SFR_MEM8 (0xBD) /* TWAMR */ #define TWAM6 7 #define TWAM5 6 #define TWAM4 5 #define TWAM3 4 #define TWAM2 3 #define TWAM1 2 #define TWAM0 1 #define UCSR0A _SFR_MEM8 (0xC0) /* UCSR0A */ #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 #define UCSR0B _SFR_MEM8 (0xC1) /* UCSR0B */ #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 #define UCSR0C _SFR_MEM8 (0xC2) /* UCSR0C */ #define UMSEL01 7 #define UMSEL00 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UDORD0 2 #define UCSZ00 1 #define UCPHA0 1 #define UCPOL0 0 #define UBRR0 _SFR_MEM16 (0xC4) #define UBRR0L _SFR_MEM8 (0xC4) #define UBRR0H _SFR_MEM8 (0xC5) #define UDR0 _SFR_MEM8 (0xC6) /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) #define SIG_PIN_CHANGE0 _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) #define SIG_PIN_CHANGE1 _VECTOR(4) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 5 #define PCINT2_vect _VECTOR(5) #define SIG_PIN_CHANGE2 _VECTOR(5) /* Watchdog Time-out Interrupt */ #define WDT_vect_num 6 #define WDT_vect _VECTOR(6) #define SIG_WATCHDOG_TIMEOUT _VECTOR(6) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPA_vect_num 7 #define TIMER2_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE2A _VECTOR(7) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 8 #define TIMER2_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE2B _VECTOR(8) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 9 #define TIMER2_OVF_vect _VECTOR(9) #define SIG_OVERFLOW2 _VECTOR(9) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 10 #define TIMER1_CAPT_vect _VECTOR(10) #define SIG_INPUT_CAPTURE1 _VECTOR(10) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 11 #define TIMER1_COMPA_vect _VECTOR(11) #define SIG_OUTPUT_COMPARE1A _VECTOR(11) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 12 #define TIMER1_COMPB_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1B _VECTOR(12) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) #define SIG_OVERFLOW1 _VECTOR(13) /* TimerCounter0 Compare Match A */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE0A _VECTOR(14) /* TimerCounter0 Compare Match B */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) #define SIG_OUTPUT_COMPARE0B _VECTOR(15) /* Timer/Couner0 Overflow */ #define TIMER0_OVF_vect_num 16 #define TIMER0_OVF_vect _VECTOR(16) #define SIG_OVERFLOW0 _VECTOR(16) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 17 #define SPI_STC_vect _VECTOR(17) #define SIG_SPI _VECTOR(17) /* USART Rx Complete */ #define USART_RX_vect_num 18 #define USART_RX_vect _VECTOR(18) #define SIG_USART_RECV _VECTOR(18) /* USART, Data Register Empty */ #define USART_UDRE_vect_num 19 #define USART_UDRE_vect _VECTOR(19) #define SIG_USART_DATA _VECTOR(19) /* USART Tx Complete */ #define USART_TX_vect_num 20 #define USART_TX_vect _VECTOR(20) #define SIG_USART_TRANS _VECTOR(20) /* ADC Conversion Complete */ #define ADC_vect_num 21 #define ADC_vect _VECTOR(21) #define SIG_ADC _VECTOR(21) /* EEPROM Ready */ #define EE_READY_vect_num 22 #define EE_READY_vect _VECTOR(22) #define SIG_EEPROM_READY _VECTOR(22) /* Analog Comparator */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) #define SIG_COMPARATOR _VECTOR(23) /* Two-wire Serial Interface */ #define TWI_vect_num 24 #define TWI_vect _VECTOR(24) #define SIG_TWI _VECTOR(24) #define SIG_2WIRE_SERIAL _VECTOR(24) /* Store Program Memory Read */ #define SPM_READY_vect_num 25 #define SPM_READY_vect _VECTOR(25) #define SIG_SPM_READY _VECTOR(25) /* The mega48 and mega88 vector tables are single instruction entries (16 bits per entry for an RJMP) while the mega168 table has double instruction entries (32 bits per entry for a JMP). */ #if defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__) # define _VECTORS_SIZE 104 #else # define _VECTORS_SIZE 52 #endif /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_PIN_CHANGE2 #pragma GCC poison SIG_WATCHDOG_TIMEOUT #pragma GCC poison SIG_OUTPUT_COMPARE2A #pragma GCC poison SIG_OUTPUT_COMPARE2B #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0A #pragma GCC poison SIG_OUTPUT_COMPARE0B #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_USART_RECV #pragma GCC poison SIG_USART_DATA #pragma GCC poison SIG_USART_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_TWI #pragma GCC poison SIG_2WIRE_SERIAL #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM8_H_ */ avr-libc-1.8.0.orig/include/avr/iotn9.h0000644000000000000000000002323411732702554014504 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn9.h 2063 2009-11-18 22:06:28Z arcanum $ */ /* avr/iotn9.h - definitions for ATtiny9 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn9.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny9_H_ #define _AVR_ATtiny9_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x00) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x01) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x02) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PUEB _SFR_IO8(0x03) #define PUEB0 0 #define PUEB1 1 #define PUEB2 2 #define PUEB3 3 #define PORTCR _SFR_IO8(0x0C) #define BBMB 1 #define PCMSK _SFR_IO8(0x10) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCIFR _SFR_IO8(0x11) #define PCIF0 0 #define PCICR _SFR_IO8(0x12) #define PCIE0 0 #define EIMSK _SFR_IO8(0x13) #define INT0 0 #define EIFR _SFR_IO8(0x14) #define INTF0 0 #define EICRA _SFR_IO8(0x15) #define ISC00 0 #define ISC01 1 #define DIDR0 _SFR_IO8(0x17) #define AIN0D 0 #define AIN1D 1 #define ACSR _SFR_IO8(0x1F) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACD 7 #define ICR0 _SFR_IO16(0x22) #define ICR0L _SFR_IO8(0x22) #define ICR0_0 0 #define ICR0_1 1 #define ICR0_2 2 #define ICR0_3 3 #define ICR0_4 4 #define ICR0_5 5 #define ICR0_6 6 #define ICR0_7 7 #define ICR0H _SFR_IO8(0x23) #define ICR0_8 0 #define ICR0_9 1 #define ICR0_10 2 #define ICR0_11 3 #define ICR0_12 4 #define ICR0_13 5 #define ICR0_14 6 #define ICR0_15 7 #define OCR0B _SFR_IO16(0x24) #define OCR0BL _SFR_IO8(0x24) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define OCR0BH _SFR_IO8(0x25) #define OCR0B8 0 #define OCR0B9 1 #define OCR0B10 2 #define OCR0B11 3 #define OCR0B12 4 #define OCR0B13 5 #define OCR0B14 6 #define OCR0B15 7 #define OCR0A _SFR_IO16(0x26) #define OCR0AL _SFR_IO8(0x26) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0AH _SFR_IO8(0x27) #define OCR0A8 0 #define OCR0A9 1 #define OCR0A10 2 #define OCR0A11 3 #define OCR0A12 4 #define OCR0A13 5 #define OCR0A14 6 #define OCR0A15 7 #define TCNT0 _SFR_IO16(0x28) #define TCNT0L _SFR_IO8(0x28) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCNT0H _SFR_IO8(0x29) #define TCNT0_8 0 #define TCNT0_9 1 #define TCNT0_10 2 #define TCNT0_11 3 #define TCNT0_12 4 #define TCNT0_13 5 #define TCNT0_14 6 #define TCNT0_15 7 #define TIFR0 _SFR_IO8(0x2A) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 5 #define TIMSK0 _SFR_IO8(0x2B) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 5 #define TCCR0C _SFR_IO8(0x2C) #define FOC0B 6 #define FOC0A 7 #define TCCR0B _SFR_IO8(0x2D) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define WGM03 4 #define ICES0 6 #define ICNC0 7 #define TCCR0A _SFR_IO8(0x2E) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define GTCCR _SFR_IO8(0x2F) #define PSR 0 #define TSM 7 #define WDTCSR _SFR_IO8(0x31) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define NVMCSR _SFR_IO8(0x32) #define NVMBSY 7 #define NVMCMD _SFR_IO8(0x33) #define NVMCMD0 0 #define NVMCMD1 1 #define NVMCMD2 2 #define NVMCMD3 3 #define NVMCMD4 4 #define NVMCMD5 5 #define VLMCSR _SFR_IO8(0x34) #define VLM0 0 #define VLM1 1 #define VLM2 2 #define VLMIE 6 #define VLMF 7 #define PRR _SFR_IO8(0x35) #define PRTIM0 0 #define PRADC 1 #define CLKPSR _SFR_IO8(0x36) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKMSR _SFR_IO8(0x37) #define CLKMS0 0 #define CLKMS1 1 #define OSCCAL _SFR_IO8(0x39) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define SMCR _SFR_IO8(0x3A) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define RSTFLR _SFR_IO8(0x3B) #define PORF 0 #define EXTRF 1 #define WDRF 3 #define CCP _SFR_IO8(0x3C) #define CCP0 0 #define CCP1 1 #define CCP2 2 #define CCP3 3 #define CCP4 4 #define CCP5 5 #define CCP6 6 #define CCP7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define TIM0_CAPT_vect_num 3 #define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ #define TIM0_OVF_vect_num 4 #define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ #define TIM0_COMPA_vect_num 5 #define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ #define TIM0_COMPB_vect_num 6 #define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ #define ANA_COMP_vect_num 7 #define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Watchdog Time-out */ #define VLM_vect_num 9 #define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (10 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (32) #define RAMSTART (0x40) #define RAMSIZE (32) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x0) #define E2PAGESIZE (0) #define FLASHEND (0x3FF) /* Fuses */ #define FUSE_MEMORY_SIZE 0 /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x08 /* Device Pin Definitions */ #define SPDATA_DDR DDRCINT #define SPDATA_PORT PORTCINT #define SPDATA_PIN PINCINT #define SPDATA_BIT INT0 #define OC0A_DDR DDRCINT #define OC0A_PORT PORTCINT #define OC0A_PIN PINCINT #define OC0A_BIT INT0 #define ADC0_DDR DDRCINT #define ADC0_PORT PORTCINT #define ADC0_PIN PINCINT #define ADC0_BIT INT0 #define AIN0_DDR DDRCINT #define AIN0_PORT PORTCINT #define AIN0_PIN PINCINT #define AIN0_BIT INT0 #define PB0_DDR DDRCINT #define PB0_PORT PORTCINT #define PB0_PIN PINCINT #define PB0_BIT INT0 #define SPCLK_DDR DDRCINT #define SPCLK_PORT PORTCINT #define SPCLK_PIN PINCINT #define SPCLK_BIT INT1 #define CLKI_DDR DDRCINT #define CLKI_PORT PORTCINT #define CLKI_PIN PINCINT #define CLKI_BIT INT1 #define ICP0_DDR DDRCINT #define ICP0_PORT PORTCINT #define ICP0_PIN PINCINT #define ICP0_BIT INT1 #define OC0B_DDR DDRCINT #define OC0B_PORT PORTCINT #define OC0B_PIN PINCINT #define OC0B_BIT INT1 #define ADC1_DDR DDRCINT #define ADC1_PORT PORTCINT #define ADC1_PIN PINCINT #define ADC1_BIT INT1 #define AIN1_DDR DDRCINT #define AIN1_PORT PORTCINT #define AIN1_PIN PINCINT #define AIN1_BIT INT1 #define PB1_DDR DDRCINT #define PB1_PORT PORTCINT #define PB1_PIN PINCINT #define PB1_BIT INT1 #define CLKO_DDR DDRT #define CLKO_PORT PORTT #define CLKO_PIN PINT #define CLKO_BIT T0 #define PCINT2_DDR DDRT #define PCINT2_PORT PORTT #define PCINT2_PIN PINT #define PCINT2_BIT T0 #define INT0_DDR DDRT #define INT0_PORT PORTT #define INT0_PIN PINT #define INT0_BIT T0 #define ADC2_DDR DDRT #define ADC2_PORT PORTT #define ADC2_PIN PINT #define ADC2_BIT T0 #define PB2_DDR DDRT #define PB2_PORT PORTT #define PB2_PIN PINT #define PB2_BIT T0 #define PCINT3_DDR DDRRESET #define PCINT3_PORT PORTRESET #define PCINT3_PIN PINRESET #define PCINT3_BIT RESET #define ADC3_DDR DDRRESET #define ADC3_PORT PORTRESET #define ADC3_PIN PINRESET #define ADC3_BIT RESET #define PB3_DDR DDRRESET #define PB3_PORT PORTRESET #define PB3_PIN PINRESET #define PB3_BIT RESET #endif /* _AVR_ATtiny9_H_ */ avr-libc-1.8.0.orig/include/avr/iousbxx6_7.h0000644000000000000000000006303211732702554015457 0ustar /* Copyright (c) 2006, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iousbxx6_7.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286 and AT90USB1287 */ #ifndef _AVR_IOUSBXX6_7_H_ #define _AVR_IOUSBXX6_7_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iousbxx6_7.h" #else # error "Attempt to include more than one file." #endif #if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) # define __AT90USBxx6__ 1 #elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__) # define __AT90USBxx7__ 1 #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0X00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0X01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0X02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0X03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 /* Reserved [0x12..0x14] */ #define TIFR0 _SFR_IO8(0x15) #define OCF0B 2 #define OCF0A 1 #define TOV0 0 #define TIFR1 _SFR_IO8(0x16) #define ICF1 5 #define OCF1C 3 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 #define TIFR2 _SFR_IO8(0x17) #define OCF2B 2 #define OCF2A 1 #define TOV2 0 #define TIFR3 _SFR_IO8(0x18) #define ICF3 5 #define OCF3C 3 #define OCF3B 2 #define OCF3A 1 #define TOV3 0 /* Reserved [0x19..0x1A] */ #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define EIFR _SFR_IO8(0x1C) #define INTF7 7 #define INTF6 6 #define INTF5 5 #define INTF4 4 #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 #define EIMSK _SFR_IO8(0x1D) #define INT7 7 #define INT6 6 #define INT5 5 #define INT4 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 #define EEDR _SFR_IO8(0x20) #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0x22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define TSM 7 #define PSRASY 1 #define PSRSYNC 0 #define TCCR0A _SFR_IO8(0x24) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 #define TCCR0B _SFR_IO8(0x25) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0x27) #define OCR0B _SFR_IO8(0X28) #define PLLCSR _SFR_IO8(0x29) #define PLLP2 4 #define PLLP1 3 #define PLLP0 2 #define PLLE 1 #define PLOCK 0 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 #define SPSR _SFR_IO8(0x2D) #define SPIF 7 #define WCOL 6 #define SPI2X 0 #define SPDR _SFR_IO8(0x2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 #define MONDR _SFR_IO8(0x31) #define OCDR _SFR_IO8(0x31) #define IDRD 7 #define OCDR7 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 #define MCUSR _SFR_IO8(0x34) #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 #define MCUCR _SFR_IO8(0x35) #define JTD 7 #define PUD 4 #define IVSEL 1 #define IVCE 0 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMIE 7 #define RWWSB 6 #define SIGRD 5 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* Reserved [0x38..0x3A] */ #if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) #define RAMPZ _SFR_IO8(0x3B) #endif /* Reserved [0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCSR _SFR_MEM8(0x60) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 #define CLKPR _SFR_MEM8(0x61) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 /* Reserved [0x62..0x63] */ #define PRR0 _SFR_MEM8(0x64) #define PRTWI 7 #define PRTIM2 6 #define PRTIM0 5 #define PRTIM1 3 #define PRSPI 2 #define PRADC 0 #define PRR1 _SFR_MEM8(0x65) #define PRUSB 7 #define PRTIM3 3 #define PRUSART1 0 #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67] */ #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define EICRA _SFR_MEM8(0x69) #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 #define EICRB _SFR_MEM8(0x6A) #define ISC71 7 #define ISC70 6 #define ISC61 5 #define ISC60 4 #define ISC51 3 #define ISC50 2 #define ISC41 1 #define ISC40 0 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 /* Reserved [0x6C..0x6D] */ #define TIMSK0 _SFR_MEM8(0x6E) #define OCIE0B 2 #define OCIE0A 1 #define TOIE0 0 #define TIMSK1 _SFR_MEM8(0x6F) #define ICIE1 5 #define OCIE1C 3 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 #define TIMSK2 _SFR_MEM8(0x70) #define OCIE2B 2 #define OCIE2A 1 #define TOIE2 0 #define TIMSK3 _SFR_MEM8(0x71) #define ICIE3 5 #define OCIE3C 3 #define OCIE3B 2 #define OCIE3A 1 #define TOIE3 0 /* Reserved [0x72..0x73] */ #define XMCRA _SFR_MEM8(0x74) #define SRE 7 #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW11 3 #define SRW10 2 #define SRW01 1 #define SRW00 0 #define XMCRB _SFR_MEM8(0x75) #define XMBK 7 #define XMM2 2 #define XMM1 1 #define XMM0 0 /* Reserved [0x76..0x77] */ /* RegDef: ADC Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 #define ADCSRB _SFR_MEM8(0x7B) #define ACME 6 #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 #define ADMUX _SFR_MEM8(0x7C) #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC7D 7 #define ADC6D 6 #define ADC5D 5 #define ADC4D 4 #define ADC3D 3 #define ADC2D 2 #define ADC1D 1 #define ADC0D 0 #define DIDR1 _SFR_MEM8(0x7F) #define AIN1D 1 #define AIN0D 0 #define TCCR1A _SFR_MEM8(0x80) #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define COM1C1 3 #define COM1C0 2 #define WGM11 1 #define WGM10 0 #define TCCR1B _SFR_MEM8(0x81) #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 #define TCCR1C _SFR_MEM8(0x82) #define FOC1A 7 #define FOC1B 6 #define FOC1C 5 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Combine OCR1CL and OCR1CH */ #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CH _SFR_MEM8(0x8D) /* Reserved [0x8E..0x8F] */ #define TCCR3A _SFR_MEM8(0x90) #define COM3A1 7 #define COM3A0 6 #define COM3B1 5 #define COM3B0 4 #define COM3C1 3 #define COM3C0 2 #define WGM31 1 #define WGM30 0 #define TCCR3B _SFR_MEM8(0x91) #define ICNC3 7 #define ICES3 6 #define WGM33 4 #define WGM32 3 #define CS32 2 #define CS31 1 #define CS30 0 #define TCCR3C _SFR_MEM8(0x92) #define FOC3A 7 #define FOC3B 6 #define FOC3C 5 /* Reserved [0x93] */ /* Combine TCNT3L and TCNT3H */ #define TCNT3 _SFR_MEM16(0x94) #define TCNT3L _SFR_MEM8(0x94) #define TCNT3H _SFR_MEM8(0x95) /* Combine ICR3L and ICR3H */ #define ICR3 _SFR_MEM16(0x96) #define ICR3L _SFR_MEM8(0x96) #define ICR3H _SFR_MEM8(0x97) /* Combine OCR3AL and OCR3AH */ #define OCR3A _SFR_MEM16(0x98) #define OCR3AL _SFR_MEM8(0x98) #define OCR3AH _SFR_MEM8(0x99) /* Combine OCR3BL and OCR3BH */ #define OCR3B _SFR_MEM16(0x9A) #define OCR3BL _SFR_MEM8(0x9A) #define OCR3BH _SFR_MEM8(0x9B) /* Combine OCR3CL and OCR3CH */ #define OCR3C _SFR_MEM16(0x9C) #define OCR3CL _SFR_MEM8(0x9C) #define OCR3CH _SFR_MEM8(0x9D) #if defined(__AT90USBxx7__) #define UHCON _SFR_MEM8(0x9E) #define RESUME 2 #define RESET 1 #define SOFEN 0 #define UHINT _SFR_MEM8(0x9F) #define HWUPI 6 #define HSOFI 5 #define RXRSMI 4 #define RSMEDI 3 #define RSTI 2 #define DDISCI 1 #define DCONNI 0 #define UHIEN _SFR_MEM8(0xA0) #define HWUPE 6 #define HSOFE 5 #define RXRSME 4 #define RSMEDE 3 #define RSTE 2 #define DDISCE 1 #define DCONNE 0 #define UHADDR _SFR_MEM8(0xA1) /* Combine UHFNUML and UHFNUMH */ #define UHFNUM _SFR_MEM16(0xA2) #define UHFNUML _SFR_MEM8(0xA2) #define UHFNUMH _SFR_MEM8(0xA3) #define UHFLEN _SFR_MEM8(0xA4) #define UPINRQX _SFR_MEM8(0xA5) #define UPINTX _SFR_MEM8(0xA6) #define FIFOCON 7 #define NAKEDI 6 #define RWAL 5 #define PERRI 4 #define TXSTPI 3 #define TXOUTI 2 #define RXSTALLI 1 #define RXINI 0 #define UPNUM _SFR_MEM8(0xA7) #define UPRST _SFR_MEM8(0xA8) #define PRST6 6 #define PRST5 5 #define PRST4 4 #define PRST3 3 #define PRST2 2 #define PRST1 1 #define PRST0 0 #define UPCONX _SFR_MEM8(0xA9) #define PFREEZE 6 #define INMODE 5 /* #define AUTOSW 4 */ /* Reserved */ #define RSTDT 3 #define PEN 0 #define UPCFG0X _SFR_MEM8(0XAA) #define PTYPE1 7 #define PTYPE0 6 #define PTOKEN1 5 #define PTOKEN0 4 #define PEPNUM3 3 #define PEPNUM2 2 #define PEPNUM1 1 #define PEPNUM0 0 #define UPCFG1X _SFR_MEM8(0XAB) #define PSIZE2 6 #define PSIZE1 5 #define PSIZE0 4 #define PBK1 3 #define PBK0 2 #define ALLOC 1 #define UPSTAX _SFR_MEM8(0XAC) #define CFGOK 7 #define OVERFI 6 #define UNDERFI 5 #define DTSEQ1 3 #define DTSEQ0 2 #define NBUSYBK1 1 #define NBUSYBK0 0 #define UPCFG2X _SFR_MEM8(0XAD) #define UPIENX _SFR_MEM8(0XAE) #define FLERRE 7 #define NAKEDE 6 #define PERRE 4 #define TXSTPE 3 #define TXOUTE 2 #define RXSTALLE 1 #define RXINE 0 #define UPDATX _SFR_MEM8(0XAF) #endif /* __AT90USBxx7__ */ #define TCCR2A _SFR_MEM8(0xB0) #define COM2A1 7 #define COM2A0 6 #define COM2B1 5 #define COM2B0 4 #define WGM21 1 #define WGM20 0 #define TCCR2B _SFR_MEM8(0xB1) #define FOC2A 7 #define FOC2B 6 #define WGM22 3 #define CS22 2 #define CS21 1 #define CS20 0 #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) #define OCR2B _SFR_MEM8(0xB4) /* Reserved [0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define EXCLK 6 #define AS2 5 #define TCN2UB 4 #define OCR2AUB 3 #define OCR2BUB 2 #define TCR2AUB 1 #define TCR2BUB 0 /* Reserved [0xB7] */ #define TWBR _SFR_MEM8(0xB8) #define TWSR _SFR_MEM8(0xB9) #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 #define TWAR _SFR_MEM8(0xBA) #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 #define TWDR _SFR_MEM8(0xBB) #define TWCR _SFR_MEM8(0xBC) #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 #define TWAMR _SFR_MEM8(0xBD) #define TWAM6 7 #define TWAM5 6 #define TWAM4 5 #define TWAM3 4 #define TWAM2 3 #define TWAM1 2 #define TWAM0 1 /* Reserved [0xBE..0xC7] */ #define UCSR1A _SFR_MEM8(0xC8) #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 #define UCSR1B _SFR_MEM8(0XC9) #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 #define UCSR1C _SFR_MEM8(0xCA) #define UMSEL11 7 #define UMSEL10 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPOL1 0 /* Reserved [0xCB] */ /* Combine UBRR1L and UBRR1H */ #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1H _SFR_MEM8(0xCD) #define UDR1 _SFR_MEM8(0XCE) /* Reserved [0xCF..0xD6] */ #define UHWCON _SFR_MEM8(0XD7) #define UIMOD 7 #define UIDE 6 #define UVCONE 4 #define UVREGE 0 #define USBCON _SFR_MEM8(0XD8) #define USBE 7 #define HOST 6 #define FRZCLK 5 #define OTGPADE 4 #define IDTE 1 #define VBUSTE 0 #define USBSTA _SFR_MEM8(0XD9) #define SPEED 3 #define ID 1 #define VBUS 0 #define USBINT _SFR_MEM8(0XDA) #define IDTI 1 #define VBUSTI 0 /* Combine UDPADDL and UDPADDH */ #define UDPADD _SFR_MEM16(0xDB) #define UDPADDL _SFR_MEM8(0xDB) #define UDPADDH _SFR_MEM8(0xDC) #define DPACC 7 #if defined(__AT90USBxx7__) #define OTGCON _SFR_MEM8(0XDD) #define HNPREQ 5 #define SRPREQ 4 #define SRPSEL 3 #define VBUSHWC 2 #define VBUSREQ 1 #define VBUSRQC 0 #define OTGIEN _SFR_MEM8(0XDE) #define STOE 5 #define HNPERRE 4 #define ROLEEXE 3 #define BCERRE 2 #define VBERRE 1 #define SRPE 0 #define OTGINT _SFR_MEM8(0XDF) #define STOI 5 #define HNPERRI 4 #define ROLEEXI 3 #define BCERRI 2 #define VBERRI 1 #define SRPI 0 #endif /* __AT90USBxx7__ */ #define UDCON _SFR_MEM8(0XE0) #define LSM 2 #define RMWKUP 1 #define DETACH 0 #define UDINT _SFR_MEM8(0XE1) #define UPRSMI 6 #define EORSMI 5 #define WAKEUPI 4 #define EORSTI 3 #define SOFI 2 /* #define MSOFI 1 */ /* Reserved */ #define SUSPI 0 #define UDIEN _SFR_MEM8(0XE2) #define UPRSME 6 #define EORSME 5 #define WAKEUPE 4 #define EORSTE 3 #define SOFE 2 /* #define MSOFE 1 */ /* Reserved */ #define SUSPE 0 #define UDADDR _SFR_MEM8(0XE3) #define ADDEN 7 /* Combine UDFNUML and UDFNUMH */ #define UDFNUM _SFR_MEM16(0xE4) #define UDFNUML _SFR_MEM8(0xE4) #define UDFNUMH _SFR_MEM8(0xE5) #define UDMFN _SFR_MEM8(0XE6) #define FNCERR 4 #define UDTST _SFR_MEM8(0XE7) #define OPMODE2 5 #define TSTPCKT 4 #define TSTK 3 #define TSTJ 2 #define UEINTX _SFR_MEM8(0XE8) #define FIFOCON 7 #define NAKINI 6 #define RWAL 5 #define NAKOUTI 4 #define RXSTPI 3 #define RXOUTI 2 #define STALLEDI 1 #define TXINI 0 #define UENUM _SFR_MEM8(0XE9) #define UERST _SFR_MEM8(0XEA) #define EPRST6 6 #define EPRST5 5 #define EPRST4 4 #define EPRST3 3 #define EPRST2 2 #define EPRST1 1 #define EPRST0 0 #define UECONX _SFR_MEM8(0XEB) #define STALLRQ 5 #define STALLRQC 4 #define RSTDT 3 #define EPEN 0 #define UECFG0X _SFR_MEM8(0XEC) #define EPTYPE1 7 #define EPTYPE0 6 /* #define ISOSW 3 */ /* Reserved */ /* #define AUTOSW 2 */ /* Reserved */ /* #define NYETSDIS 1 */ /* Reserved */ #define EPDIR 0 #define UECFG1X _SFR_MEM8(0XED) #define EPSIZE2 6 #define EPSIZE1 5 #define EPSIZE0 4 #define EPBK1 3 #define EPBK0 2 #define ALLOC 1 #define UESTA0X _SFR_MEM8(0XEE) #define CFGOK 7 #define OVERFI 6 #define UNDERFI 5 #define ZLPSEEN 4 #define DTSEQ1 3 #define DTSEQ0 2 #define NBUSYBK1 1 #define NBUSYBK0 0 #define UESTA1X _SFR_MEM8(0XEF) #define CTRLDIR 2 #define CURRBK1 1 #define CURRBK0 0 #define UEIENX _SFR_MEM8(0XF0) #define FLERRE 7 #define NAKINE 6 #define NAKOUTE 4 #define RXSTPE 3 #define RXOUTE 2 #define STALLEDE 1 #define TXINE 0 #define UEDATX _SFR_MEM8(0XF1) /* Combine UEBCLX and UEBCHX */ #define UEBCX _SFR_MEM16(0xF2) #define UEBCLX _SFR_MEM8(0xF2) #define UEBCHX _SFR_MEM8(0xF3) #define UEINT _SFR_MEM8(0XF4) #define EPINT6 6 #define EPINT5 5 #define EPINT4 4 #define EPINT3 3 #define EPINT2 2 #define EPINT1 1 #define EPINT0 0 #if defined(__AT90USBxx7__) #define UPERRX _SFR_MEM8(0XF5) #define COUNTER1 6 #define COUNTER0 5 #define CRC16 4 #define TIMEOUT 3 #define PID 2 #define DATAPID 1 #define DATATGL 0 /* Combine UPBCLX and UPBCHX */ #define UPBCX _SFR_MEM16(0xF6) #define UPBCLX _SFR_MEM8(0xF6) #define UPBCHX _SFR_MEM8(0xF7) #define UPINT _SFR_MEM8(0XF8) #define PINT6 6 #define PINT5 5 #define PINT4 4 #define PINT3 3 #define PINT2 2 #define PINT1 1 #define PINT0 0 #define OTGTCON _SFR_MEM8(0XF9) #define PAGE1 6 #define PAGE0 5 #define VALUE1 1 #define VALUE0 0 #endif /* __AT90USBxx7__ */ /* Reserved [0xFA..0xFF] */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 3 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) /* External Interrupt Request 4 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) /* External Interrupt Request 5 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) /* External Interrupt Request 6 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) /* External Interrupt Request 7 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 9 #define PCINT0_vect _VECTOR(9) /* USB General Interrupt Request */ #define USB_GEN_vect_num 10 #define USB_GEN_vect _VECTOR(10) /* USB Endpoint/Pipe Interrupt Communication Request */ #define USB_COM_vect_num 11 #define USB_COM_vect _VECTOR(11) /* Watchdog Time-out Interrupt */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPA_vect_num 13 #define TIMER2_COMPA_vect _VECTOR(13) /* Timer/Counter2 Compare Match B */ #define TIMER2_COMPB_vect_num 14 #define TIMER2_COMPB_vect _VECTOR(14) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 15 #define TIMER2_OVF_vect _VECTOR(15) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 16 #define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 17 #define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 18 #define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match C */ #define TIMER1_COMPC_vect_num 19 #define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 20 #define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPA_vect_num 21 #define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match B */ #define TIMER0_COMPB_vect_num 22 #define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 23 #define TIMER0_OVF_vect _VECTOR(23) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 24 #define SPI_STC_vect _VECTOR(24) /* USART1, Rx Complete */ #define USART1_RX_vect_num 25 #define USART1_RX_vect _VECTOR(25) /* USART1 Data register Empty */ #define USART1_UDRE_vect_num 26 #define USART1_UDRE_vect _VECTOR(26) /* USART1, Tx Complete */ #define USART1_TX_vect_num 27 #define USART1_TX_vect _VECTOR(27) /* Analog Comparator */ #define ANALOG_COMP_vect_num 28 #define ANALOG_COMP_vect _VECTOR(28) /* ADC Conversion Complete */ #define ADC_vect_num 29 #define ADC_vect _VECTOR(29) /* EEPROM Ready */ #define EE_READY_vect_num 30 #define EE_READY_vect _VECTOR(30) /* Timer/Counter3 Capture Event */ #define TIMER3_CAPT_vect_num 31 #define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPA_vect_num 32 #define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPB_vect_num 33 #define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match C */ #define TIMER3_COMPC_vect_num 34 #define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Overflow */ #define TIMER3_OVF_vect_num 35 #define TIMER3_OVF_vect _VECTOR(35) /* 2-wire Serial Interface */ #define TWI_vect_num _VECTOR(36) #define TWI_vect _VECTOR(36) /* Store Program Memory Read */ #define SPM_READY_vect_num 37 #define SPM_READY_vect _VECTOR(37) #define _VECTORS_SIZE 152 #if defined(__AT90USBxx6__) # undef __AT90USBxx6__ #endif /* __AT90USBxx6__ */ #if defined(__AT90USBxx7__) # undef __AT90USBxx7__ #endif /* __AT90USBxx7__ */ #endif /* _AVR_IOUSBXX6_7_H_ */ avr-libc-1.8.0.orig/include/avr/iotn2313a.h0000644000000000000000000004016311732702554015065 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn2313a.h 2035 2009-11-02 02:44:17Z arcanum $ */ /* avr/iotn2313a.h - definitions for ATtiny2313A */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn2313a.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny2313A_H_ #define _AVR_ATtiny2313A_H_ 1 /* Registers and associated bit numbers. */ #define DIDR _SFR_IO8(0x001) #define AIN0D 0 #define AIN1D 1 #define UBRRH _SFR_IO8(0x002) #define UBRR8 0 #define UBRR9 1 #define UBRR10 2 #define UBRR11 3 #define UCSRC _SFR_IO8(0x003) #define UCPOL 0 #define UCSZ0 1 #define UCSZ1 2 #define USBS 3 #define UPM0 4 #define UPM1 5 #define UMSEL 6 #define PCMSK1 _SFR_IO8(0x004) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCMSK2 _SFR_IO8(0x005) #define PCINT11 0 #define PCINT12 1 #define PCINT13 2 #define PCINT14 3 #define PCINT15 4 #define PCINT16 5 #define PCINT17 6 #define PRR _SFR_IO8(0x006) #define PRUSART 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define BODCR _SFR_IO8(0x007) #define BPDSE 0 #define BPDS 1 #define ACSR _SFR_IO8(0x008) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define UBRRL _SFR_IO8(0x009) #define UBRR0 0 #define UBRR1 1 #define UBRR2 2 #define UBRR3 3 #define UBRR4 4 #define UBRR5 5 #define UBRR6 6 #define UBRR7 7 #define UCSRB _SFR_IO8(0x00A) #define TXB8 0 #define RXB8 1 #define UCSZ2 2 #define TXEN 3 #define RXEN 4 #define UDRIE 5 #define TXCIE 6 #define RXCIE 7 #define UCSRA _SFR_IO8(0x00B) #define MPCM 0 #define U2X 1 #define UPE 2 #define DOR 3 #define FE 4 #define UDRE 5 #define TXC 6 #define RXC 7 #define UDR _SFR_IO8(0x00C) #define UDR0 0 #define UDR1 1 #define UDR2 2 #define UDR3 3 #define UDR4 4 #define UDR5 5 #define UDR6 6 #define UDR7 7 #define USICR _SFR_IO8(0x00D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x00E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x00F) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define PIND _SFR_IO8(0x010) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define DDRD _SFR_IO8(0x011) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define PORTD _SFR_IO8(0x012) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define GPIOR0 _SFR_IO8(0x013) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x014) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x015) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PINB _SFR_IO8(0x016) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x017) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x018) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINA _SFR_IO8(0x019) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define DDRA _SFR_IO8(0x01A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define PORTA _SFR_IO8(0x01B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define EECR _SFR_IO8(0x01C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x01D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO8(0x01E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define PCMSK _SFR_IO8(0x020) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define WDTCR _SFR_IO8(0x021) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define TCCR1C _SFR_IO8(0x022) #define FOC1B 6 #define FOC1A 7 #define GTCCR _SFR_IO8(0x023) #define PSR10 0 #define ICR1 _SFR_IO16(0x024) #define ICR1L _SFR_IO8(0x024) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_IO8(0x025) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define CLKPR _SFR_IO8(0x026) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define OCR1B _SFR_IO16(0x028) #define OCR1BL _SFR_IO8(0x028) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_IO8(0x029) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1A _SFR_IO16(0x02A) #define OCR1AL _SFR_IO8(0x02A) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_IO8(0x02B) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define TCNT1 _SFR_IO16(0x02C) #define TCNT1L _SFR_IO8(0x02C) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_IO8(0x02D) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define TCCR1B _SFR_IO8(0x02E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x02F) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR0A _SFR_IO8(0x030) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define OSCCAL _SFR_IO8(0x031) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define TCNT0 _SFR_IO8(0x032) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0B _SFR_IO8(0x033) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define MCUSR _SFR_IO8(0x034) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x035) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define SM0 4 #define SE 5 #define SM1 6 #define PUD 7 #define OCR0A _SFR_IO8(0x036) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define SPMCSR _SFR_IO8(0x037) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR _SFR_IO8(0x038) #define OCF0A 0 #define TOV0 1 #define OCF0B 2 #define ICF1 3 #define OCF1B 5 #define OCF1A 6 #define TOV1 7 #define TIMSK _SFR_IO8(0x039) #define OCIE0A 0 #define TOIE0 1 #define OCIE0B 2 #define ICIE1 3 #define OCIE1B 5 #define OCIE1A 6 #define TOIE1 7 #define EIFR _SFR_IO8(0x03A) #define PCIF 5 #define INTF0 6 #define INTF1 7 #define GIMSK _SFR_IO8(0x03B) #define PCIE 5 #define INT0 6 #define INT1 7 #define OCR0B _SFR_IO8(0x03C) #define OCR0_0 0 #define OCR0_1 1 #define OCR0_2 2 #define OCR0_3 3 #define OCR0_4 4 #define OCR0_5 5 #define OCR0_6 6 #define OCR0_7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define TIMER1_CAPT_vect_num 3 #define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 4 #define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */ #define TIMER1_OVF_vect_num 5 #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ #define TIMER0_OVF_vect_num 6 #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ #define USART_RX_vect_num 7 #define USART_RX_vect _VECTOR(7) /* USART, Rx Complete */ #define USART_UDRE_vect_num 8 #define USART_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ #define USART_TX_vect_num 9 #define USART_TX_vect _VECTOR(9) /* USART, Tx Complete */ #define ANA_COMP_vect_num 10 #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ #define PCINT_B_vect_num 11 #define PCINT_B_vect _VECTOR(11) /* Pin Change Interrupt Request B */ #define TIMER1_COMPB_vect_num 12 #define TIMER1_COMPB_vect _VECTOR(12) /* */ #define TIMER0_COMPA_vect_num 13 #define TIMER0_COMPA_vect _VECTOR(13) /* */ #define TIMER0_COMPB_vect_num 14 #define TIMER0_COMPB_vect _VECTOR(14) /* */ #define USI_START_vect_num 15 #define USI_START_vect _VECTOR(15) /* USI Start Condition */ #define USI_OVERFLOW_vect_num 16 #define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ #define WDT_OVERFLOW_vect_num 18 #define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ #define PCINT_D_vect_num 20 #define PCINT_D_vect _VECTOR(20) /* Pin Change Interrupt Request D */ #define EEPROM_Ready_vect_num 17 #define EEPROM_Ready_vect _VECTOR(17) /* */ #define PCINT_A_vect_num 19 #define PCINT_A_vect _VECTOR(19) /* Pin Change Interrupt Request A */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (21 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (32) #define RAMSTART (0x60) #define RAMSIZE (128) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x7F) #define E2PAGESIZE (4) #define FLASHEND (0x7FF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x0A /* Device Pin Definitions */ #define RXD_DDR DDRD #define RXD_PORT PORTD #define RXD_PIN PIND #define RXD_BIT 0 #define TXD_DDR DDRD #define TXD_PORT PORTD #define TXD_PIN PIND #define TXD_BIT 1 #define PA1_DDR DDRXTAL #define PA1_PORT PORTXTAL #define PA1_PIN PINXTAL #define PA1_BIT XTAL2 #define PA0_DDR DDRXTAL #define PA0_PORT PORTXTAL #define PA0_PIN PINXTAL #define PA0_BIT XTAL1 #define INT0_DDR DDRD #define INT0_PORT PORTD #define INT0_PIN PIND #define INT0_BIT 2 #define XCK_DDR DDRD #define XCK_PORT PORTD #define XCK_PIN PIND #define XCK_BIT 2 #define CKOUT_DDR DDRD #define CKOUT_PORT PORTD #define CKOUT_PIN PIND #define CKOUT_BIT 2 #define INT1_DDR DDRD #define INT1_PORT PORTD #define INT1_PIN PIND #define INT1_BIT 3 #define T0_DDR DDRD #define T0_PORT PORTD #define T0_PIN PIND #define T0_BIT 4 #define T1_DDR DDRD #define T1_PORT PORTD #define T1_PIN PIND #define T1_BIT 5 #define OC0B_DDR DDRD #define OC0B_PORT PORTD #define OC0B_PIN PIND #define OC0B_BIT 5 #define ICP_DDR DDRD #define ICP_PORT PORTD #define ICP_PIN PIND #define ICP_BIT 6 #define AIN0_DDR DDRB #define AIN0_PORT PORTB #define AIN0_PIN PINB #define AIN0_BIT 0 #define AIN1_DDR DDRB #define AIN1_PORT PORTB #define AIN1_PIN PINB #define AIN1_BIT 1 #define OC0A_DDR DDRB #define OC0A_PORT PORTB #define OC0A_PIN PINB #define OC0A_BIT 2 #define OC1A_DDR DDRB #define OC1A_PORT PORTB #define OC1A_PIN PINB #define OC1A_BIT 3 #define OC1B_DDR DDRB #define OC1B_PORT PORTB #define OC1B_PIN PINB #define OC1B_BIT 4 #define MOSI_DDR DDRB #define MOSI_PORT PORTB #define MOSI_PIN PINB #define MOSI_BIT 5 #define DI_DDR DDRB #define DI_PORT PORTB #define DI_PIN PINB #define DI_BIT 5 #define MISO_DDR DDRB #define MISO_PORT PORTB #define MISO_PIN PINB #define MISO_BIT 6 #define DO_DDR DDRB #define DO_PORT PORTB #define DO_PIN PINB #define DO_BIT 6 #define SCK_DDR DDRB #define SCK_PORT PORTB #define SCK_PIN PINB #define SCK_BIT 7 #define SCL_DDR DDRB #define SCL_PORT PORTB #define SCL_PIN PINB #define SCL_BIT 7 #endif /* _AVR_ATtiny2313A_H_ */ avr-libc-1.8.0.orig/include/avr/iox128a1u.h0000644000000000000000000123047511732702554015113 0ustar /* Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox128a1u.h 2162 2010-06-11 17:26:12Z arcanum $ */ /* avr/iox128a1u.h - definitions for ATxmega128A1U */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox128a1u.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega128A1U_H_ #define _AVR_ATxmega128A1U_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- VPORT - Virtual Ports -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ register8_t USBCTRL; /* USB Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ } CLK_RTCSRC_t; /* USB Prescaler Division Factor */ typedef enum CLK_USBPSDIV_enum { CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ } CLK_USBPSDIV_t; /* USB Clock Source */ typedef enum CLK_USBSRC_enum { CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ } CLK_USBSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* 32 MHz Calibration Reference */ typedef enum OSC_RC32MCREF_enum { OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ } OSC_RC32MCREF_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t ANAINIT; /* Analog Startup Delay */ register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- PORTCFG - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* Virtual Port Mapping */ typedef enum PORTCFG_VP02MAP_enum { PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP02MAP_t; /* Virtual Port Mapping */ typedef enum PORTCFG_VP13MAP_enum { PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP13MAP_t; /* System Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Peripheral Clock Output Select */ typedef enum PORTCFG_CLKOUTSEL_enum { PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ } PORTCFG_CLKOUTSEL_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* -------------------------------------------------------------------------- CRC - Cyclic Redundancy Checker -------------------------------------------------------------------------- */ /* Cyclic Redundancy Checker */ typedef struct CRC_struct { register8_t CTRL; /* CRC Control Register */ register8_t STATUS; /* CRC Status Register */ register8_t DATAIN; /* CRC Data Input */ register8_t CHECKSUM0; /* CRC Checksum byte 0 */ register8_t CHECKSUM1; /* CRC Checksum byte 1 */ register8_t CHECKSUM2; /* CRC Checksum byte 2 */ register8_t CHECKSUM3; /* CRC Checksum byte 3 */ } CRC_t; /* CRC Reset */ typedef enum CRC_RESET_enum { CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ } CRC_RESET_t; /* CRC Input Source */ typedef enum CRC_SOURCE_enum { CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ } CRC_SOURCE_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Current Limitation Mode */ typedef enum ADC_CURRENT_enum { ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */ ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */ ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */ ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */ } ADC_CURRENT_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t CH0GAINCAL; /* Gain Calibration */ register8_t CH0OFFSETCAL; /* Offset Calibration */ register8_t CH1GAINCAL; /* Gain Calibration */ register8_t CH1OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Analog Comparator 0 Control */ register8_t AC1CTRL; /* Analog Comparator 1 Control */ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- USB - USB Module -------------------------------------------------------------------------- */ /* USB Endpoint */ typedef struct USB_EP_struct { register8_t STATUS; /* Endpoint Status */ register8_t CTRL; /* Endpoint Control */ register8_t CNTL; /* USB Endpoint Counter Low Byte */ register8_t CNTH; /* USB Endpoint Counter High Byte */ register8_t DATAPTRL; /* Data Pointer Low Byte */ register8_t DATAPTRH; /* Data Pointer High Byte */ register8_t AUXDATAL; /* Auxiliary Data Low Byte */ register8_t AUXDATAH; /* Auxiliary Data High Byte */ } USB_EP_t; /* -------------------------------------------------------------------------- USB - USB Module -------------------------------------------------------------------------- */ /* USB Endpoint table */ typedef struct USB_EP_TABLE_struct { USB_EP_t EP0OUT; /* USB Endpoint 0 Output */ USB_EP_t EP0IN; /* USB Endpoint 0 Input */ USB_EP_t EP1OUT; /* USB Endpoint 1 Output */ USB_EP_t EP1IN; /* USB Endpoint 1 Input */ USB_EP_t EP2OUT; /* USB Endpoint 2 Output */ USB_EP_t EP2IN; /* USB Endpoint 2 Input */ USB_EP_t EP3OUT; /* USB Endpoint 3 Output */ USB_EP_t EP3IN; /* USB Endpoint 3 Input */ USB_EP_t EP4OUT; /* USB Endpoint 4 Output */ USB_EP_t EP4IN; /* USB Endpoint 4 Input */ USB_EP_t EP5OUT; /* USB Endpoint 5 Output */ USB_EP_t EP5IN; /* USB Endpoint 5 Input */ USB_EP_t EP6OUT; /* USB Endpoint 6 Output */ USB_EP_t EP6IN; /* USB Endpoint 6 Input */ USB_EP_t EP7OUT; /* USB Endpoint 7 Output */ USB_EP_t EP7IN; /* USB Endpoint 7 Input */ USB_EP_t EP8OUT; /* USB Endpoint 8 Output */ USB_EP_t EP8IN; /* USB Endpoint 8 Input */ USB_EP_t EP9OUT; /* USB Endpoint 9 Output */ USB_EP_t EP9IN; /* USB Endpoint 9 Input */ USB_EP_t EP10OUT; /* USB Endpoint 10 Output */ USB_EP_t EP10IN; /* USB Endpoint 10 Input */ USB_EP_t EP11OUT; /* USB Endpoint 11 Output */ USB_EP_t EP11IN; /* USB Endpoint 11 Input */ USB_EP_t EP12OUT; /* USB Endpoint 12 Output */ USB_EP_t EP12IN; /* USB Endpoint 12 Input */ USB_EP_t EP13OUT; /* USB Endpoint 13 Output */ USB_EP_t EP13IN; /* USB Endpoint 13 Input */ USB_EP_t EP14OUT; /* USB Endpoint 14 Output */ USB_EP_t EP14IN; /* USB Endpoint 14 Input */ USB_EP_t EP15OUT; /* USB Endpoint 15 Output */ USB_EP_t EP15IN; /* USB Endpoint 15 Input */ register8_t FRAMENUML; /* Frame Number Low Byte */ register8_t FRAMENUMH; /* Frame Number High Byte */ } USB_EP_TABLE_t; /* -------------------------------------------------------------------------- USB - USB Module -------------------------------------------------------------------------- */ /* USB Module */ typedef struct USB_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t FIFOWP; /* FIFO Write Pointer Register */ register8_t FIFORP; /* FIFO Read Pointer Register */ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t reserved_0x20; register8_t reserved_0x21; register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t CAL0; /* Calibration Byte 0 */ register8_t CAL1; /* Calibration Byte 1 */ } USB_t; /* USB Endpoint Type */ typedef enum USB_EP_TYPE_enum { USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ } USB_EP_TYPE_t; /* USB Endpoint Buffer Size */ typedef enum USB_EP_SIZE_enum { USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ USB_EP_SIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ USB_EP_SIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ USB_EP_SIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ USB_EP_SIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ USB_EP_SIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ } USB_EP_SIZE_t; /* Interrupt level */ typedef enum USB_INTLVL_enum { USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ USB_INTLVL_LO_gc = (0x01<<0), /* Low Level */ USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ USB_INTLVL_HI_gc = (0x03<<0), /* High Level */ } USB_INTLVL_t; /* -------------------------------------------------------------------------- PORT - I/O Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* -------------------------------------------------------------------------- AWEX - Timer/Counter Advanced Waveform Extension -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* -------------------------------------------------------------------------- HIRES - Timer/Counter High-Resolution Extension -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- PRESC - Prescaler -------------------------------------------------------------------------- */ /* Prescaler */ typedef struct PRESC_struct { register8_t PRESCALER; /* Control Register */ } PRESC_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define USB_EP_TABLE (*(USB_EP_TABLE_t *) ) /* Universal Serial Bus Module */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define CRC (*(CRC_t *) 0x00D0) /* CRC Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ #define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ #define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus Module */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTH (*(PORT_t *) 0x06E0) /* Port H */ #define PORTJ (*(PORT_t *) 0x0700) /* Port J */ #define PORTK (*(PORT_t *) 0x0720) /* Port K */ #define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* USB_EP_TABLE - Universal Serial Bus Module */ #define USB_EP_TABLE_EP0OUT_STATUS _SFR_MEM8(0x0000) #define USB_EP_TABLE_EP0OUT_CTRL _SFR_MEM8(0x0001) #define USB_EP_TABLE_EP0OUT_CNTL _SFR_MEM8(0x0002) #define USB_EP_TABLE_EP0OUT_CNTH _SFR_MEM8(0x0003) #define USB_EP_TABLE_EP0OUT_DATAPTRL _SFR_MEM8(0x0004) #define USB_EP_TABLE_EP0OUT_DATAPTRH _SFR_MEM8(0x0005) #define USB_EP_TABLE_EP0OUT_AUXDATAL _SFR_MEM8(0x0006) #define USB_EP_TABLE_EP0OUT_AUXDATAH _SFR_MEM8(0x0007) #define USB_EP_TABLE_EP0IN_STATUS _SFR_MEM8(0x0008) #define USB_EP_TABLE_EP0IN_CTRL _SFR_MEM8(0x0009) #define USB_EP_TABLE_EP0IN_CNTL _SFR_MEM8(0x000A) #define USB_EP_TABLE_EP0IN_CNTH _SFR_MEM8(0x000B) #define USB_EP_TABLE_EP0IN_DATAPTRL _SFR_MEM8(0x000C) #define USB_EP_TABLE_EP0IN_DATAPTRH _SFR_MEM8(0x000D) #define USB_EP_TABLE_EP0IN_AUXDATAL _SFR_MEM8(0x000E) #define USB_EP_TABLE_EP0IN_AUXDATAH _SFR_MEM8(0x000F) #define USB_EP_TABLE_EP1OUT_STATUS _SFR_MEM8(0x0010) #define USB_EP_TABLE_EP1OUT_CTRL _SFR_MEM8(0x0011) #define USB_EP_TABLE_EP1OUT_CNTL _SFR_MEM8(0x0012) #define USB_EP_TABLE_EP1OUT_CNTH _SFR_MEM8(0x0013) #define USB_EP_TABLE_EP1OUT_DATAPTRL _SFR_MEM8(0x0014) #define USB_EP_TABLE_EP1OUT_DATAPTRH _SFR_MEM8(0x0015) #define USB_EP_TABLE_EP1OUT_AUXDATAL _SFR_MEM8(0x0016) #define USB_EP_TABLE_EP1OUT_AUXDATAH _SFR_MEM8(0x0017) #define USB_EP_TABLE_EP1IN_STATUS _SFR_MEM8(0x0018) #define USB_EP_TABLE_EP1IN_CTRL _SFR_MEM8(0x0019) #define USB_EP_TABLE_EP1IN_CNTL _SFR_MEM8(0x001A) #define USB_EP_TABLE_EP1IN_CNTH _SFR_MEM8(0x001B) #define USB_EP_TABLE_EP1IN_DATAPTRL _SFR_MEM8(0x001C) #define USB_EP_TABLE_EP1IN_DATAPTRH _SFR_MEM8(0x001D) #define USB_EP_TABLE_EP1IN_AUXDATAL _SFR_MEM8(0x001E) #define USB_EP_TABLE_EP1IN_AUXDATAH _SFR_MEM8(0x001F) #define USB_EP_TABLE_EP2OUT_STATUS _SFR_MEM8(0x0020) #define USB_EP_TABLE_EP2OUT_CTRL _SFR_MEM8(0x0021) #define USB_EP_TABLE_EP2OUT_CNTL _SFR_MEM8(0x0022) #define USB_EP_TABLE_EP2OUT_CNTH _SFR_MEM8(0x0023) #define USB_EP_TABLE_EP2OUT_DATAPTRL _SFR_MEM8(0x0024) #define USB_EP_TABLE_EP2OUT_DATAPTRH _SFR_MEM8(0x0025) #define USB_EP_TABLE_EP2OUT_AUXDATAL _SFR_MEM8(0x0026) #define USB_EP_TABLE_EP2OUT_AUXDATAH _SFR_MEM8(0x0027) #define USB_EP_TABLE_EP2IN_STATUS _SFR_MEM8(0x0028) #define USB_EP_TABLE_EP2IN_CTRL _SFR_MEM8(0x0029) #define USB_EP_TABLE_EP2IN_CNTL _SFR_MEM8(0x002A) #define USB_EP_TABLE_EP2IN_CNTH _SFR_MEM8(0x002B) #define USB_EP_TABLE_EP2IN_DATAPTRL _SFR_MEM8(0x002C) #define USB_EP_TABLE_EP2IN_DATAPTRH _SFR_MEM8(0x002D) #define USB_EP_TABLE_EP2IN_AUXDATAL _SFR_MEM8(0x002E) #define USB_EP_TABLE_EP2IN_AUXDATAH _SFR_MEM8(0x002F) #define USB_EP_TABLE_EP3OUT_STATUS _SFR_MEM8(0x0030) #define USB_EP_TABLE_EP3OUT_CTRL _SFR_MEM8(0x0031) #define USB_EP_TABLE_EP3OUT_CNTL _SFR_MEM8(0x0032) #define USB_EP_TABLE_EP3OUT_CNTH _SFR_MEM8(0x0033) #define USB_EP_TABLE_EP3OUT_DATAPTRL _SFR_MEM8(0x0034) #define USB_EP_TABLE_EP3OUT_DATAPTRH _SFR_MEM8(0x0035) #define USB_EP_TABLE_EP3OUT_AUXDATAL _SFR_MEM8(0x0036) #define USB_EP_TABLE_EP3OUT_AUXDATAH _SFR_MEM8(0x0037) #define USB_EP_TABLE_EP3IN_STATUS _SFR_MEM8(0x0038) #define USB_EP_TABLE_EP3IN_CTRL _SFR_MEM8(0x0039) #define USB_EP_TABLE_EP3IN_CNTL _SFR_MEM8(0x003A) #define USB_EP_TABLE_EP3IN_CNTH _SFR_MEM8(0x003B) #define USB_EP_TABLE_EP3IN_DATAPTRL _SFR_MEM8(0x003C) #define USB_EP_TABLE_EP3IN_DATAPTRH _SFR_MEM8(0x003D) #define USB_EP_TABLE_EP3IN_AUXDATAL _SFR_MEM8(0x003E) #define USB_EP_TABLE_EP3IN_AUXDATAH _SFR_MEM8(0x003F) #define USB_EP_TABLE_EP4OUT_STATUS _SFR_MEM8(0x0040) #define USB_EP_TABLE_EP4OUT_CTRL _SFR_MEM8(0x0041) #define USB_EP_TABLE_EP4OUT_CNTL _SFR_MEM8(0x0042) #define USB_EP_TABLE_EP4OUT_CNTH _SFR_MEM8(0x0043) #define USB_EP_TABLE_EP4OUT_DATAPTRL _SFR_MEM8(0x0044) #define USB_EP_TABLE_EP4OUT_DATAPTRH _SFR_MEM8(0x0045) #define USB_EP_TABLE_EP4OUT_AUXDATAL _SFR_MEM8(0x0046) #define USB_EP_TABLE_EP4OUT_AUXDATAH _SFR_MEM8(0x0047) #define USB_EP_TABLE_EP4IN_STATUS _SFR_MEM8(0x0048) #define USB_EP_TABLE_EP4IN_CTRL _SFR_MEM8(0x0049) #define USB_EP_TABLE_EP4IN_CNTL _SFR_MEM8(0x004A) #define USB_EP_TABLE_EP4IN_CNTH _SFR_MEM8(0x004B) #define USB_EP_TABLE_EP4IN_DATAPTRL _SFR_MEM8(0x004C) #define USB_EP_TABLE_EP4IN_DATAPTRH _SFR_MEM8(0x004D) #define USB_EP_TABLE_EP4IN_AUXDATAL _SFR_MEM8(0x004E) #define USB_EP_TABLE_EP4IN_AUXDATAH _SFR_MEM8(0x004F) #define USB_EP_TABLE_EP5OUT_STATUS _SFR_MEM8(0x0050) #define USB_EP_TABLE_EP5OUT_CTRL _SFR_MEM8(0x0051) #define USB_EP_TABLE_EP5OUT_CNTL _SFR_MEM8(0x0052) #define USB_EP_TABLE_EP5OUT_CNTH _SFR_MEM8(0x0053) #define USB_EP_TABLE_EP5OUT_DATAPTRL _SFR_MEM8(0x0054) #define USB_EP_TABLE_EP5OUT_DATAPTRH _SFR_MEM8(0x0055) #define USB_EP_TABLE_EP5OUT_AUXDATAL _SFR_MEM8(0x0056) #define USB_EP_TABLE_EP5OUT_AUXDATAH _SFR_MEM8(0x0057) #define USB_EP_TABLE_EP5IN_STATUS _SFR_MEM8(0x0058) #define USB_EP_TABLE_EP5IN_CTRL _SFR_MEM8(0x0059) #define USB_EP_TABLE_EP5IN_CNTL _SFR_MEM8(0x005A) #define USB_EP_TABLE_EP5IN_CNTH _SFR_MEM8(0x005B) #define USB_EP_TABLE_EP5IN_DATAPTRL _SFR_MEM8(0x005C) #define USB_EP_TABLE_EP5IN_DATAPTRH _SFR_MEM8(0x005D) #define USB_EP_TABLE_EP5IN_AUXDATAL _SFR_MEM8(0x005E) #define USB_EP_TABLE_EP5IN_AUXDATAH _SFR_MEM8(0x005F) #define USB_EP_TABLE_EP6OUT_STATUS _SFR_MEM8(0x0060) #define USB_EP_TABLE_EP6OUT_CTRL _SFR_MEM8(0x0061) #define USB_EP_TABLE_EP6OUT_CNTL _SFR_MEM8(0x0062) #define USB_EP_TABLE_EP6OUT_CNTH _SFR_MEM8(0x0063) #define USB_EP_TABLE_EP6OUT_DATAPTRL _SFR_MEM8(0x0064) #define USB_EP_TABLE_EP6OUT_DATAPTRH _SFR_MEM8(0x0065) #define USB_EP_TABLE_EP6OUT_AUXDATAL _SFR_MEM8(0x0066) #define USB_EP_TABLE_EP6OUT_AUXDATAH _SFR_MEM8(0x0067) #define USB_EP_TABLE_EP6IN_STATUS _SFR_MEM8(0x0068) #define USB_EP_TABLE_EP6IN_CTRL _SFR_MEM8(0x0069) #define USB_EP_TABLE_EP6IN_CNTL _SFR_MEM8(0x006A) #define USB_EP_TABLE_EP6IN_CNTH _SFR_MEM8(0x006B) #define USB_EP_TABLE_EP6IN_DATAPTRL _SFR_MEM8(0x006C) #define USB_EP_TABLE_EP6IN_DATAPTRH _SFR_MEM8(0x006D) #define USB_EP_TABLE_EP6IN_AUXDATAL _SFR_MEM8(0x006E) #define USB_EP_TABLE_EP6IN_AUXDATAH _SFR_MEM8(0x006F) #define USB_EP_TABLE_EP7OUT_STATUS _SFR_MEM8(0x0070) #define USB_EP_TABLE_EP7OUT_CTRL _SFR_MEM8(0x0071) #define USB_EP_TABLE_EP7OUT_CNTL _SFR_MEM8(0x0072) #define USB_EP_TABLE_EP7OUT_CNTH _SFR_MEM8(0x0073) #define USB_EP_TABLE_EP7OUT_DATAPTRL _SFR_MEM8(0x0074) #define USB_EP_TABLE_EP7OUT_DATAPTRH _SFR_MEM8(0x0075) #define USB_EP_TABLE_EP7OUT_AUXDATAL _SFR_MEM8(0x0076) #define USB_EP_TABLE_EP7OUT_AUXDATAH _SFR_MEM8(0x0077) #define USB_EP_TABLE_EP7IN_STATUS _SFR_MEM8(0x0078) #define USB_EP_TABLE_EP7IN_CTRL _SFR_MEM8(0x0079) #define USB_EP_TABLE_EP7IN_CNTL _SFR_MEM8(0x007A) #define USB_EP_TABLE_EP7IN_CNTH _SFR_MEM8(0x007B) #define USB_EP_TABLE_EP7IN_DATAPTRL _SFR_MEM8(0x007C) #define USB_EP_TABLE_EP7IN_DATAPTRH _SFR_MEM8(0x007D) #define USB_EP_TABLE_EP7IN_AUXDATAL _SFR_MEM8(0x007E) #define USB_EP_TABLE_EP7IN_AUXDATAH _SFR_MEM8(0x007F) #define USB_EP_TABLE_EP8OUT_STATUS _SFR_MEM8(0x0080) #define USB_EP_TABLE_EP8OUT_CTRL _SFR_MEM8(0x0081) #define USB_EP_TABLE_EP8OUT_CNTL _SFR_MEM8(0x0082) #define USB_EP_TABLE_EP8OUT_CNTH _SFR_MEM8(0x0083) #define USB_EP_TABLE_EP8OUT_DATAPTRL _SFR_MEM8(0x0084) #define USB_EP_TABLE_EP8OUT_DATAPTRH _SFR_MEM8(0x0085) #define USB_EP_TABLE_EP8OUT_AUXDATAL _SFR_MEM8(0x0086) #define USB_EP_TABLE_EP8OUT_AUXDATAH _SFR_MEM8(0x0087) #define USB_EP_TABLE_EP8IN_STATUS _SFR_MEM8(0x0088) #define USB_EP_TABLE_EP8IN_CTRL _SFR_MEM8(0x0089) #define USB_EP_TABLE_EP8IN_CNTL _SFR_MEM8(0x008A) #define USB_EP_TABLE_EP8IN_CNTH _SFR_MEM8(0x008B) #define USB_EP_TABLE_EP8IN_DATAPTRL _SFR_MEM8(0x008C) #define USB_EP_TABLE_EP8IN_DATAPTRH _SFR_MEM8(0x008D) #define USB_EP_TABLE_EP8IN_AUXDATAL _SFR_MEM8(0x008E) #define USB_EP_TABLE_EP8IN_AUXDATAH _SFR_MEM8(0x008F) #define USB_EP_TABLE_EP9OUT_STATUS _SFR_MEM8(0x0090) #define USB_EP_TABLE_EP9OUT_CTRL _SFR_MEM8(0x0091) #define USB_EP_TABLE_EP9OUT_CNTL _SFR_MEM8(0x0092) #define USB_EP_TABLE_EP9OUT_CNTH _SFR_MEM8(0x0093) #define USB_EP_TABLE_EP9OUT_DATAPTRL _SFR_MEM8(0x0094) #define USB_EP_TABLE_EP9OUT_DATAPTRH _SFR_MEM8(0x0095) #define USB_EP_TABLE_EP9OUT_AUXDATAL _SFR_MEM8(0x0096) #define USB_EP_TABLE_EP9OUT_AUXDATAH _SFR_MEM8(0x0097) #define USB_EP_TABLE_EP9IN_STATUS _SFR_MEM8(0x0098) #define USB_EP_TABLE_EP9IN_CTRL _SFR_MEM8(0x0099) #define USB_EP_TABLE_EP9IN_CNTL _SFR_MEM8(0x009A) #define USB_EP_TABLE_EP9IN_CNTH _SFR_MEM8(0x009B) #define USB_EP_TABLE_EP9IN_DATAPTRL _SFR_MEM8(0x009C) #define USB_EP_TABLE_EP9IN_DATAPTRH _SFR_MEM8(0x009D) #define USB_EP_TABLE_EP9IN_AUXDATAL _SFR_MEM8(0x009E) #define USB_EP_TABLE_EP9IN_AUXDATAH _SFR_MEM8(0x009F) #define USB_EP_TABLE_EP10OUT_STATUS _SFR_MEM8(0x00A0) #define USB_EP_TABLE_EP10OUT_CTRL _SFR_MEM8(0x00A1) #define USB_EP_TABLE_EP10OUT_CNTL _SFR_MEM8(0x00A2) #define USB_EP_TABLE_EP10OUT_CNTH _SFR_MEM8(0x00A3) #define USB_EP_TABLE_EP10OUT_DATAPTRL _SFR_MEM8(0x00A4) #define USB_EP_TABLE_EP10OUT_DATAPTRH _SFR_MEM8(0x00A5) #define USB_EP_TABLE_EP10OUT_AUXDATAL _SFR_MEM8(0x00A6) #define USB_EP_TABLE_EP10OUT_AUXDATAH _SFR_MEM8(0x00A7) #define USB_EP_TABLE_EP10IN_STATUS _SFR_MEM8(0x00A8) #define USB_EP_TABLE_EP10IN_CTRL _SFR_MEM8(0x00A9) #define USB_EP_TABLE_EP10IN_CNTL _SFR_MEM8(0x00AA) #define USB_EP_TABLE_EP10IN_CNTH _SFR_MEM8(0x00AB) #define USB_EP_TABLE_EP10IN_DATAPTRL _SFR_MEM8(0x00AC) #define USB_EP_TABLE_EP10IN_DATAPTRH _SFR_MEM8(0x00AD) #define USB_EP_TABLE_EP10IN_AUXDATAL _SFR_MEM8(0x00AE) #define USB_EP_TABLE_EP10IN_AUXDATAH _SFR_MEM8(0x00AF) #define USB_EP_TABLE_EP11OUT_STATUS _SFR_MEM8(0x00B0) #define USB_EP_TABLE_EP11OUT_CTRL _SFR_MEM8(0x00B1) #define USB_EP_TABLE_EP11OUT_CNTL _SFR_MEM8(0x00B2) #define USB_EP_TABLE_EP11OUT_CNTH _SFR_MEM8(0x00B3) #define USB_EP_TABLE_EP11OUT_DATAPTRL _SFR_MEM8(0x00B4) #define USB_EP_TABLE_EP11OUT_DATAPTRH _SFR_MEM8(0x00B5) #define USB_EP_TABLE_EP11OUT_AUXDATAL _SFR_MEM8(0x00B6) #define USB_EP_TABLE_EP11OUT_AUXDATAH _SFR_MEM8(0x00B7) #define USB_EP_TABLE_EP11IN_STATUS _SFR_MEM8(0x00B8) #define USB_EP_TABLE_EP11IN_CTRL _SFR_MEM8(0x00B9) #define USB_EP_TABLE_EP11IN_CNTL _SFR_MEM8(0x00BA) #define USB_EP_TABLE_EP11IN_CNTH _SFR_MEM8(0x00BB) #define USB_EP_TABLE_EP11IN_DATAPTRL _SFR_MEM8(0x00BC) #define USB_EP_TABLE_EP11IN_DATAPTRH _SFR_MEM8(0x00BD) #define USB_EP_TABLE_EP11IN_AUXDATAL _SFR_MEM8(0x00BE) #define USB_EP_TABLE_EP11IN_AUXDATAH _SFR_MEM8(0x00BF) #define USB_EP_TABLE_EP12OUT_STATUS _SFR_MEM8(0x00C0) #define USB_EP_TABLE_EP12OUT_CTRL _SFR_MEM8(0x00C1) #define USB_EP_TABLE_EP12OUT_CNTL _SFR_MEM8(0x00C2) #define USB_EP_TABLE_EP12OUT_CNTH _SFR_MEM8(0x00C3) #define USB_EP_TABLE_EP12OUT_DATAPTRL _SFR_MEM8(0x00C4) #define USB_EP_TABLE_EP12OUT_DATAPTRH _SFR_MEM8(0x00C5) #define USB_EP_TABLE_EP12OUT_AUXDATAL _SFR_MEM8(0x00C6) #define USB_EP_TABLE_EP12OUT_AUXDATAH _SFR_MEM8(0x00C7) #define USB_EP_TABLE_EP12IN_STATUS _SFR_MEM8(0x00C8) #define USB_EP_TABLE_EP12IN_CTRL _SFR_MEM8(0x00C9) #define USB_EP_TABLE_EP12IN_CNTL _SFR_MEM8(0x00CA) #define USB_EP_TABLE_EP12IN_CNTH _SFR_MEM8(0x00CB) #define USB_EP_TABLE_EP12IN_DATAPTRL _SFR_MEM8(0x00CC) #define USB_EP_TABLE_EP12IN_DATAPTRH _SFR_MEM8(0x00CD) #define USB_EP_TABLE_EP12IN_AUXDATAL _SFR_MEM8(0x00CE) #define USB_EP_TABLE_EP12IN_AUXDATAH _SFR_MEM8(0x00CF) #define USB_EP_TABLE_EP13OUT_STATUS _SFR_MEM8(0x00D0) #define USB_EP_TABLE_EP13OUT_CTRL _SFR_MEM8(0x00D1) #define USB_EP_TABLE_EP13OUT_CNTL _SFR_MEM8(0x00D2) #define USB_EP_TABLE_EP13OUT_CNTH _SFR_MEM8(0x00D3) #define USB_EP_TABLE_EP13OUT_DATAPTRL _SFR_MEM8(0x00D4) #define USB_EP_TABLE_EP13OUT_DATAPTRH _SFR_MEM8(0x00D5) #define USB_EP_TABLE_EP13OUT_AUXDATAL _SFR_MEM8(0x00D6) #define USB_EP_TABLE_EP13OUT_AUXDATAH _SFR_MEM8(0x00D7) #define USB_EP_TABLE_EP13IN_STATUS _SFR_MEM8(0x00D8) #define USB_EP_TABLE_EP13IN_CTRL _SFR_MEM8(0x00D9) #define USB_EP_TABLE_EP13IN_CNTL _SFR_MEM8(0x00DA) #define USB_EP_TABLE_EP13IN_CNTH _SFR_MEM8(0x00DB) #define USB_EP_TABLE_EP13IN_DATAPTRL _SFR_MEM8(0x00DC) #define USB_EP_TABLE_EP13IN_DATAPTRH _SFR_MEM8(0x00DD) #define USB_EP_TABLE_EP13IN_AUXDATAL _SFR_MEM8(0x00DE) #define USB_EP_TABLE_EP13IN_AUXDATAH _SFR_MEM8(0x00DF) #define USB_EP_TABLE_EP14OUT_STATUS _SFR_MEM8(0x00E0) #define USB_EP_TABLE_EP14OUT_CTRL _SFR_MEM8(0x00E1) #define USB_EP_TABLE_EP14OUT_CNTL _SFR_MEM8(0x00E2) #define USB_EP_TABLE_EP14OUT_CNTH _SFR_MEM8(0x00E3) #define USB_EP_TABLE_EP14OUT_DATAPTRL _SFR_MEM8(0x00E4) #define USB_EP_TABLE_EP14OUT_DATAPTRH _SFR_MEM8(0x00E5) #define USB_EP_TABLE_EP14OUT_AUXDATAL _SFR_MEM8(0x00E6) #define USB_EP_TABLE_EP14OUT_AUXDATAH _SFR_MEM8(0x00E7) #define USB_EP_TABLE_EP14IN_STATUS _SFR_MEM8(0x00E8) #define USB_EP_TABLE_EP14IN_CTRL _SFR_MEM8(0x00E9) #define USB_EP_TABLE_EP14IN_CNTL _SFR_MEM8(0x00EA) #define USB_EP_TABLE_EP14IN_CNTH _SFR_MEM8(0x00EB) #define USB_EP_TABLE_EP14IN_DATAPTRL _SFR_MEM8(0x00EC) #define USB_EP_TABLE_EP14IN_DATAPTRH _SFR_MEM8(0x00ED) #define USB_EP_TABLE_EP14IN_AUXDATAL _SFR_MEM8(0x00EE) #define USB_EP_TABLE_EP14IN_AUXDATAH _SFR_MEM8(0x00EF) #define USB_EP_TABLE_EP15OUT_STATUS _SFR_MEM8(0x00F0) #define USB_EP_TABLE_EP15OUT_CTRL _SFR_MEM8(0x00F1) #define USB_EP_TABLE_EP15OUT_CNTL _SFR_MEM8(0x00F2) #define USB_EP_TABLE_EP15OUT_CNTH _SFR_MEM8(0x00F3) #define USB_EP_TABLE_EP15OUT_DATAPTRL _SFR_MEM8(0x00F4) #define USB_EP_TABLE_EP15OUT_DATAPTRH _SFR_MEM8(0x00F5) #define USB_EP_TABLE_EP15OUT_AUXDATAL _SFR_MEM8(0x00F6) #define USB_EP_TABLE_EP15OUT_AUXDATAH _SFR_MEM8(0x00F7) #define USB_EP_TABLE_EP15IN_STATUS _SFR_MEM8(0x00F8) #define USB_EP_TABLE_EP15IN_CTRL _SFR_MEM8(0x00F9) #define USB_EP_TABLE_EP15IN_CNTL _SFR_MEM8(0x00FA) #define USB_EP_TABLE_EP15IN_CNTH _SFR_MEM8(0x00FB) #define USB_EP_TABLE_EP15IN_DATAPTRL _SFR_MEM8(0x00FC) #define USB_EP_TABLE_EP15IN_DATAPTRH _SFR_MEM8(0x00FD) #define USB_EP_TABLE_EP15IN_AUXDATAL _SFR_MEM8(0x00FE) #define USB_EP_TABLE_EP15IN_AUXDATAH _SFR_MEM8(0x00FF) #define USB_EP_TABLE_FRAMENUML _SFR_MEM8(0x0110) #define USB_EP_TABLE_FRAMENUMH _SFR_MEM8(0x0111) /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) #define CLK_USBCTRL _SFR_MEM8(0x0044) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x005F) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_ANAINIT _SFR_MEM8(0x0097) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* CRC - CRC Module */ #define CRC_CTRL _SFR_MEM8(0x00D0) #define CRC_STATUS _SFR_MEM8(0x00D1) #define CRC_DATAIN _SFR_MEM8(0x00D3) #define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) #define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) #define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) #define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_TEMP _SFR_MEM8(0x0207) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* ADCB - Analog to Digital Converter B */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) #define ADCB_EVCTRL _SFR_MEM8(0x0243) #define ADCB_PRESCALER _SFR_MEM8(0x0244) #define ADCB_INTFLAGS _SFR_MEM8(0x0246) #define ADCB_TEMP _SFR_MEM8(0x0247) #define ADCB_CAL _SFR_MEM16(0x024C) #define ADCB_CH0RES _SFR_MEM16(0x0250) #define ADCB_CH1RES _SFR_MEM16(0x0252) #define ADCB_CH2RES _SFR_MEM16(0x0254) #define ADCB_CH3RES _SFR_MEM16(0x0256) #define ADCB_CMP _SFR_MEM16(0x0258) #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) /* DACA - Digital to Analog Converter A */ #define DACA_CTRLA _SFR_MEM8(0x0300) #define DACA_CTRLB _SFR_MEM8(0x0301) #define DACA_CTRLC _SFR_MEM8(0x0302) #define DACA_EVCTRL _SFR_MEM8(0x0303) #define DACA_TIMCTRL _SFR_MEM8(0x0304) #define DACA_STATUS _SFR_MEM8(0x0305) #define DACA_CH0GAINCAL _SFR_MEM8(0x0308) #define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) #define DACA_CH1GAINCAL _SFR_MEM8(0x030A) #define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) #define DACA_CH0DATA _SFR_MEM16(0x0318) #define DACA_CH1DATA _SFR_MEM16(0x031A) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_CH0GAINCAL _SFR_MEM8(0x0328) #define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH1GAINCAL _SFR_MEM8(0x032A) #define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* EBI - External Bus Interface */ #define EBI_CTRL _SFR_MEM8(0x0440) #define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) #define EBI_REFRESH _SFR_MEM16(0x0444) #define EBI_INITDLY _SFR_MEM16(0x0446) #define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) #define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) #define EBI_CS0_CTRLA _SFR_MEM8(0x0450) #define EBI_CS0_CTRLB _SFR_MEM8(0x0451) #define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) #define EBI_CS1_CTRLA _SFR_MEM8(0x0454) #define EBI_CS1_CTRLB _SFR_MEM8(0x0455) #define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) #define EBI_CS2_CTRLA _SFR_MEM8(0x0458) #define EBI_CS2_CTRLB _SFR_MEM8(0x0459) #define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) #define EBI_CS3_CTRLA _SFR_MEM8(0x045C) #define EBI_CS3_CTRLB _SFR_MEM8(0x045D) #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWID - Two-Wire Interface D */ #define TWID_CTRL _SFR_MEM8(0x0490) #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) #define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) #define TWID_MASTER_STATUS _SFR_MEM8(0x0494) #define TWID_MASTER_BAUD _SFR_MEM8(0x0495) #define TWID_MASTER_ADDR _SFR_MEM8(0x0496) #define TWID_MASTER_DATA _SFR_MEM8(0x0497) #define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) #define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) #define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) #define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) #define TWID_SLAVE_DATA _SFR_MEM8(0x049C) #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* TWIF - Two-Wire Interface F */ #define TWIF_CTRL _SFR_MEM8(0x04B0) #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) #define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) #define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) #define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) #define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) #define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) #define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) #define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) #define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) #define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) /* USB - Universal Serial Bus Module */ #define USB_CTRLA _SFR_MEM8(0x04C0) #define USB_CTRLB _SFR_MEM8(0x04C1) #define USB_STATUS _SFR_MEM8(0x04C2) #define USB_ADDR _SFR_MEM8(0x04C3) #define USB_FIFOWP _SFR_MEM8(0x04C4) #define USB_FIFORP _SFR_MEM8(0x04C5) #define USB_EPPTR _SFR_MEM16(0x04C6) #define USB_INTCTRLA _SFR_MEM8(0x04C8) #define USB_INTCTRLB _SFR_MEM8(0x04C9) #define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) #define USB_INTFLAGSASET _SFR_MEM8(0x04CB) #define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) #define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) #define USB_CAL0 _SFR_MEM8(0x04FA) #define USB_CAL1 _SFR_MEM8(0x04FB) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTH - Port H */ #define PORTH_DIR _SFR_MEM8(0x06E0) #define PORTH_DIRSET _SFR_MEM8(0x06E1) #define PORTH_DIRCLR _SFR_MEM8(0x06E2) #define PORTH_DIRTGL _SFR_MEM8(0x06E3) #define PORTH_OUT _SFR_MEM8(0x06E4) #define PORTH_OUTSET _SFR_MEM8(0x06E5) #define PORTH_OUTCLR _SFR_MEM8(0x06E6) #define PORTH_OUTTGL _SFR_MEM8(0x06E7) #define PORTH_IN _SFR_MEM8(0x06E8) #define PORTH_INTCTRL _SFR_MEM8(0x06E9) #define PORTH_INT0MASK _SFR_MEM8(0x06EA) #define PORTH_INT1MASK _SFR_MEM8(0x06EB) #define PORTH_INTFLAGS _SFR_MEM8(0x06EC) #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) #define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) #define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) #define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) /* PORTJ - Port J */ #define PORTJ_DIR _SFR_MEM8(0x0700) #define PORTJ_DIRSET _SFR_MEM8(0x0701) #define PORTJ_DIRCLR _SFR_MEM8(0x0702) #define PORTJ_DIRTGL _SFR_MEM8(0x0703) #define PORTJ_OUT _SFR_MEM8(0x0704) #define PORTJ_OUTSET _SFR_MEM8(0x0705) #define PORTJ_OUTCLR _SFR_MEM8(0x0706) #define PORTJ_OUTTGL _SFR_MEM8(0x0707) #define PORTJ_IN _SFR_MEM8(0x0708) #define PORTJ_INTCTRL _SFR_MEM8(0x0709) #define PORTJ_INT0MASK _SFR_MEM8(0x070A) #define PORTJ_INT1MASK _SFR_MEM8(0x070B) #define PORTJ_INTFLAGS _SFR_MEM8(0x070C) #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) #define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) #define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) #define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) /* PORTK - Port K */ #define PORTK_DIR _SFR_MEM8(0x0720) #define PORTK_DIRSET _SFR_MEM8(0x0721) #define PORTK_DIRCLR _SFR_MEM8(0x0722) #define PORTK_DIRTGL _SFR_MEM8(0x0723) #define PORTK_OUT _SFR_MEM8(0x0724) #define PORTK_OUTSET _SFR_MEM8(0x0725) #define PORTK_OUTCLR _SFR_MEM8(0x0726) #define PORTK_OUTTGL _SFR_MEM8(0x0727) #define PORTK_IN _SFR_MEM8(0x0728) #define PORTK_INTCTRL _SFR_MEM8(0x0729) #define PORTK_INT0MASK _SFR_MEM8(0x072A) #define PORTK_INT1MASK _SFR_MEM8(0x072B) #define PORTK_INTFLAGS _SFR_MEM8(0x072C) #define PORTK_PIN0CTRL _SFR_MEM8(0x0730) #define PORTK_PIN1CTRL _SFR_MEM8(0x0731) #define PORTK_PIN2CTRL _SFR_MEM8(0x0732) #define PORTK_PIN3CTRL _SFR_MEM8(0x0733) #define PORTK_PIN4CTRL _SFR_MEM8(0x0734) #define PORTK_PIN5CTRL _SFR_MEM8(0x0735) #define PORTK_PIN6CTRL _SFR_MEM8(0x0736) #define PORTK_PIN7CTRL _SFR_MEM8(0x0737) /* PORTQ - Port Q */ #define PORTQ_DIR _SFR_MEM8(0x07C0) #define PORTQ_DIRSET _SFR_MEM8(0x07C1) #define PORTQ_DIRCLR _SFR_MEM8(0x07C2) #define PORTQ_DIRTGL _SFR_MEM8(0x07C3) #define PORTQ_OUT _SFR_MEM8(0x07C4) #define PORTQ_OUTSET _SFR_MEM8(0x07C5) #define PORTQ_OUTCLR _SFR_MEM8(0x07C6) #define PORTQ_OUTTGL _SFR_MEM8(0x07C7) #define PORTQ_IN _SFR_MEM8(0x07C8) #define PORTQ_INTCTRL _SFR_MEM8(0x07C9) #define PORTQ_INT0MASK _SFR_MEM8(0x07CA) #define PORTQ_INT1MASK _SFR_MEM8(0x07CB) #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) #define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) #define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) #define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* TCE1 - Timer/Counter E1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) #define TCE1_CTRLD _SFR_MEM8(0x0A43) #define TCE1_CTRLE _SFR_MEM8(0x0A44) #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) #define TCE1_TEMP _SFR_MEM8(0x0A4F) #define TCE1_CNT _SFR_MEM16(0x0A60) #define TCE1_PER _SFR_MEM16(0x0A66) #define TCE1_CCA _SFR_MEM16(0x0A68) #define TCE1_CCB _SFR_MEM16(0x0A6A) #define TCE1_PERBUF _SFR_MEM16(0x0A76) #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) #define USARTE1_CTRLB _SFR_MEM8(0x0AB4) #define USARTE1_CTRLC _SFR_MEM8(0x0AB5) #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /* TCF1 - Timer/Counter F1 */ #define TCF1_CTRLA _SFR_MEM8(0x0B40) #define TCF1_CTRLB _SFR_MEM8(0x0B41) #define TCF1_CTRLC _SFR_MEM8(0x0B42) #define TCF1_CTRLD _SFR_MEM8(0x0B43) #define TCF1_CTRLE _SFR_MEM8(0x0B44) #define TCF1_INTCTRLA _SFR_MEM8(0x0B46) #define TCF1_INTCTRLB _SFR_MEM8(0x0B47) #define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) #define TCF1_CTRLFSET _SFR_MEM8(0x0B49) #define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) #define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) #define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) #define TCF1_TEMP _SFR_MEM8(0x0B4F) #define TCF1_CNT _SFR_MEM16(0x0B60) #define TCF1_PER _SFR_MEM16(0x0B66) #define TCF1_CCA _SFR_MEM16(0x0B68) #define TCF1_CCB _SFR_MEM16(0x0B6A) #define TCF1_PERBUF _SFR_MEM16(0x0B76) #define TCF1_CCABUF _SFR_MEM16(0x0B78) #define TCF1_CCBBUF _SFR_MEM16(0x0B7A) /* HIRESF - High-Resolution Extension F */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) /* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) #define USARTF1_CTRLB _SFR_MEM8(0x0BB4) #define USARTF1_CTRLC _SFR_MEM8(0x0BB5) #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) /* SPIF - Serial Peripheral Interface F */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) #define SPIF_DATA _SFR_MEM8(0x0BC3) /*================== Bitfield Definitions ================== */ /* VPORT - Virtual Ports */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ /* CLK.USBCTRL bit masks and bit positions */ #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ #define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ #define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ #define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ #define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ #define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ #define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ #define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ #define CLK_USBSRC_gp 1 /* Clock Source group position. */ #define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_USBEN_bm 0x01 /* Clock Source Enable bit mask. */ #define CLK_USBEN_bp 0 /* Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_USB_bm 0x40 /* USB bit mask. */ #define PR_USB_bp 6 /* USB bit position. */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ #define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ #define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ #define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_gm 0x06 /* 32 MHz Calibration Reference group mask. */ #define OSC_RC32MCREF_gp 1 /* 32 MHz Calibration Reference group position. */ #define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz Calibration Reference bit 0 mask. */ #define OSC_RC32MCREF0_bp 1 /* 32 MHz Calibration Reference bit 0 position. */ #define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz Calibration Reference bit 1 mask. */ #define OSC_RC32MCREF1_bp 2 /* 32 MHz Calibration Reference bit 1 position. */ #define OSC_RC2MCREF_bm 0x01 /* 2 MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2 MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.ANAINIT bit masks and bit positions */ #define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port A group mask. */ #define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port A group position. */ #define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port A bit 0 mask. */ #define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port A bit 0 position. */ #define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port A bit 1 mask. */ #define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port A bit 1 position. */ #define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port B group mask. */ #define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port B group position. */ #define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port B bit 0 mask. */ #define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port B bit 0 position. */ #define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port B bit 1 mask. */ #define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port B bit 1 position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* PORTCFG - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ #define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ #define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ #define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ #define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ #define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ #define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ #define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ #define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* CRC - Cyclic Redundancy Checker */ /* CRC.CTRL bit masks and bit positions */ #define CRC_RESET_gm 0xC0 /* CRC Reset group mask. */ #define CRC_RESET_gp 6 /* CRC Reset group position. */ #define CRC_RESET0_bm (1<<6) /* CRC Reset bit 0 mask. */ #define CRC_RESET0_bp 6 /* CRC Reset bit 0 position. */ #define CRC_RESET1_bm (1<<7) /* CRC Reset bit 1 mask. */ #define CRC_RESET1_bp 7 /* CRC Reset bit 1 position. */ #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ #define CRC_SOURCE_gm 0x0F /* CRC Input Source group mask. */ #define CRC_SOURCE_gp 0 /* CRC Input Source group position. */ #define CRC_SOURCE0_bm (1<<0) /* CRC Input Source bit 0 mask. */ #define CRC_SOURCE0_bp 0 /* CRC Input Source bit 0 position. */ #define CRC_SOURCE1_bm (1<<1) /* CRC Input Source bit 1 mask. */ #define CRC_SOURCE1_bp 1 /* CRC Input Source bit 1 position. */ #define CRC_SOURCE2_bm (1<<2) /* CRC Input Source bit 2 mask. */ #define CRC_SOURCE2_bp 2 /* CRC Input Source bit 2 position. */ #define CRC_SOURCE3_bm (1<<3) /* CRC Input Source bit 3 mask. */ #define CRC_SOURCE3_bp 3 /* CRC Input Source bit 3 position. */ /* CRC.STATUS bit masks and bit positions */ #define CRC_ZERO_bm 0x02 /* Zero CRC detection bit mask. */ #define CRC_ZERO_bp 1 /* Zero CRC detection bit position. */ #define CRC_BUSY_bm 0x01 /* Enable bit mask. */ #define CRC_BUSY_bp 0 /* Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0x7F /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ #define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ #define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ #define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ #define ADC_CURRENT_gm 0x60 /* Current Limitation group mask. */ #define ADC_CURRENT_gp 5 /* Current Limitation group position. */ #define ADC_CURRENT0_bm (1<<5) /* Current Limitation bit 0 mask. */ #define ADC_CURRENT0_bp 5 /* Current Limitation bit 0 position. */ #define ADC_CURRENT1_bm (1<<6) /* Current Limitation bit 1 mask. */ #define ADC_CURRENT1_bp 6 /* Current Limitation bit 1 position. */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ #define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ #define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* DAC.CH0GAINCAL bit masks and bit positions */ #define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ #define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ #define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ #define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ #define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ #define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ #define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ #define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ #define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ #define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ #define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ #define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ #define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ #define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ #define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ #define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ /* DAC.CH0OFFSETCAL bit masks and bit positions */ #define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ #define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ #define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ #define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ #define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ #define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ #define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ #define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ #define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ #define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ #define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ #define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ #define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ #define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ #define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ #define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ /* DAC.CH1GAINCAL bit masks and bit positions */ #define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ #define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ #define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ #define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ #define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ #define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ #define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ #define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ #define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ #define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ #define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ #define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ #define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ #define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ #define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ #define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ /* DAC.CH1OFFSETCAL bit masks and bit positions */ #define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ #define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ #define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ #define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ #define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ #define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ #define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ #define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ #define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ #define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ #define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ #define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ #define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ #define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ #define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ #define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* USB - USB Module */ /* USB_EP.STATUS bit masks and bit positions */ #define USB_EP_STALL_bm 0x80 /* Endpoint Stall Flag bit mask. */ #define USB_EP_STALL_bp 7 /* Endpoint Stall Flag bit position. */ #define USB_EP_CRC_bm 0x80 /* CRC Error Flag for Isochronous Out Endpoints bit mask. */ #define USB_EP_CRC_bp 7 /* CRC Error Flag for Isochronous Out Endpoints bit position. */ #define USB_EP_UNF_bm 0x40 /* Underflow Enpoint Flag for Input Endpoints bit mask. */ #define USB_EP_UNF_bp 6 /* Underflow Enpoint Flag for Input Endpoints bit position. */ #define USB_EP_OVF_bm 0x40 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */ #define USB_EP_OVF_bp 6 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */ #define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete Flag bit mask. */ #define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete Flag bit position. */ #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ #define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ #define USB_EP_BANK_bp 3 /* Bank Select bit position. */ #define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ #define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ #define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ #define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ /* USB_EP.CTRL bit masks and bit positions */ #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ #define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ #define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ #define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ #define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ #define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ #define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ #define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ #define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ /* USB_EP_STALL_bm Predefined. */ /* USB_EP_STALL_bp Predefined. */ #define USB_EP_SIZE_gm 0x07 /* Data Buffer Size group mask. */ #define USB_EP_SIZE_gp 0 /* Data Buffer Size group position. */ #define USB_EP_SIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ #define USB_EP_SIZE0_bp 0 /* Data Buffer Size bit 0 position. */ #define USB_EP_SIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ #define USB_EP_SIZE1_bp 1 /* Data Buffer Size bit 1 position. */ #define USB_EP_SIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ #define USB_EP_SIZE2_bp 2 /* Data Buffer Size bit 2 position. */ /* USB_EP.CNTH bit masks and bit positions */ #define USB_EP_ZLP_bm 0x80 /* Zero Length Packet bit mask. */ #define USB_EP_ZLP_bp 7 /* Zero Length Packet bit position. */ #define USB_EP_CNT_gm 0x03 /* Endpoint Byte Counter group mask. */ #define USB_EP_CNT_gp 0 /* Endpoint Byte Counter group position. */ #define USB_EP_CNT0_bm (1<<0) /* Endpoint Byte Counter bit 0 mask. */ #define USB_EP_CNT0_bp 0 /* Endpoint Byte Counter bit 0 position. */ #define USB_EP_CNT1_bm (1<<1) /* Endpoint Byte Counter bit 1 mask. */ #define USB_EP_CNT1_bp 1 /* Endpoint Byte Counter bit 1 position. */ /* USB.CTRLA bit masks and bit positions */ #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ #define USB_ENABLE_bp 7 /* USB Enable bit position. */ #define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ #define USB_SPEED_bp 6 /* Speed Select bit position. */ #define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ #define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ #define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ #define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ #define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ #define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ #define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ #define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ #define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ #define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ #define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ #define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ /* USB.CTRLB bit masks and bit positions */ #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ #define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ #define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ #define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ #define USB_GNACK_bp 1 /* Global NACK bit position. */ #define USB_ATTACH_bm 0x01 /* Attach bit mask. */ #define USB_ATTACH_bp 0 /* Attach bit position. */ /* USB.STATUS bit masks and bit positions */ #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ #define USB_URESUME_bp 3 /* Upstream Resume bit position. */ #define USB_RESUME_bm 0x04 /* Resume bit mask. */ #define USB_RESUME_bp 2 /* Resume bit position. */ #define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ #define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ #define USB_BUSRST_bp 0 /* Bus Reset bit position. */ /* USB.ADDR bit masks and bit positions */ #define USB_ADDR_gm 0x7F /* Device Address group mask. */ #define USB_ADDR_gp 0 /* Device Address group position. */ #define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ #define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ #define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ #define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ #define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ #define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ #define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ #define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ #define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ #define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ #define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ #define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ /* USB.FIFOWP bit masks and bit positions */ #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ #define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ #define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ #define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ #define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ #define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ #define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ #define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ #define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ /* USB.FIFORP bit masks and bit positions */ #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ #define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ #define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ #define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ #define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ #define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ #define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ #define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ #define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ /* USB.INTCTRLA bit masks and bit positions */ #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ #define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ #define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ #define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ #define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ #define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ #define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ #define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define USB_INTLVL_gp 0 /* Interrupt Level group position. */ #define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* USB.INTCTRLB bit masks and bit positions */ #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ /* USB.INTFLAGSACLR bit masks and bit positions */ #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ #define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ #define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ #define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ #define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ #define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ #define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ #define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ #define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ #define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ #define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ #define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ #define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ /* USB.INTFLAGSASET bit masks and bit positions */ /* USB_SOFIF_bm Predefined. */ /* USB_SOFIF_bp Predefined. */ /* USB_SUSPENDIF_bm Predefined. */ /* USB_SUSPENDIF_bp Predefined. */ /* USB_RESUMEIF_bm Predefined. */ /* USB_RESUMEIF_bp Predefined. */ /* USB_RSTIF_bm Predefined. */ /* USB_RSTIF_bp Predefined. */ /* USB_CRCIF_bm Predefined. */ /* USB_CRCIF_bp Predefined. */ /* USB_UNFIF_bm Predefined. */ /* USB_UNFIF_bp Predefined. */ /* USB_OVFIF_bm Predefined. */ /* USB_OVFIF_bp Predefined. */ /* USB_STALLIF_bm Predefined. */ /* USB_STALLIF_bp Predefined. */ /* USB.INTFLAGSBCLR bit masks and bit positions */ #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ #define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ /* USB.INTFLAGSBSET bit masks and bit positions */ /* USB_TRNIF_bm Predefined. */ /* USB_TRNIF_bp Predefined. */ /* USB_SETUPIF_bm Predefined. */ /* USB_SETUPIF_bp Predefined. */ /* PORT - I/O Port Configuration */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX - Timer/Counter Advanced Waveform Extension */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES - Timer/Counter High-Resolution Extension */ /* HIRES.CTRLA bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* PRESC - Prescaler */ /* PRESC.PRESCALER bit masks and bit positions */ #define PRESC_RESET_bm 0x01 /* Reset bit mask. */ #define PRESC_RESET_bp 0 /* Reset bit position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_OSCF_vect_num 1 #define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_SPM_vect_num 32 #define NVM_SPM_vect _VECTOR(32) /* SPM Interrupt */ #define NVM_EE_vect_num 33 #define NVM_EE_vect _VECTOR(33) /* EE Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* ACB interrupt vectors */ #define ACB_AC0_vect_num 36 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ #define ACB_AC1_vect_num 37 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ #define ACB_ACW_vect_num 38 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ /* ADCB interrupt vectors */ #define ADCB_CH0_vect_num 39 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ #define ADCB_CH1_vect_num 40 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ #define ADCB_CH2_vect_num 41 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ #define ADCB_CH3_vect_num 42 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* SPIE interrupt vectors */ #define SPIE_INT_vect_num 57 #define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* USARTE1 interrupt vectors */ #define USARTE1_RXC_vect_num 61 #define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ #define USARTE1_DRE_vect_num 62 #define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ #define USARTE1_TXC_vect_num 63 #define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TWID interrupt vectors */ #define TWID_TWIS_vect_num 75 #define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ #define TWID_TWIM_vect_num 76 #define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ /* PORTQ interrupt vectors */ #define PORTQ_INT0_vect_num 94 #define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ #define PORTQ_INT1_vect_num 95 #define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ /* PORTH interrupt vectors */ #define PORTH_INT0_vect_num 96 #define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ #define PORTH_INT1_vect_num 97 #define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ /* PORTJ interrupt vectors */ #define PORTJ_INT0_vect_num 98 #define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ #define PORTJ_INT1_vect_num 99 #define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ /* PORTK interrupt vectors */ #define PORTK_INT0_vect_num 100 #define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ #define PORTK_INT1_vect_num 101 #define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TWIF interrupt vectors */ #define TWIF_TWIS_vect_num 106 #define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ #define TWIF_TWIM_vect_num 107 #define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ /* TCF1 interrupt vectors */ #define TCF1_OVF_vect_num 114 #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ #define TCF1_ERR_vect_num 115 #define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ #define TCF1_CCA_vect_num 116 #define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ #define TCF1_CCB_vect_num 117 #define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ /* SPIF interrupt vectors */ #define SPIF_INT_vect_num 118 #define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ /* USARTF0 interrupt vectors */ #define USARTF0_RXC_vect_num 119 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ #define USARTF0_DRE_vect_num 120 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ #define USARTF0_TXC_vect_num 121 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ /* USARTF1 interrupt vectors */ #define USARTF1_RXC_vect_num 122 #define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ #define USARTF1_DRE_vect_num 123 #define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ #define USARTF1_TXC_vect_num 124 #define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ /* USB interrupt vectors */ #define USB_BUSEVENT_vect_num 125 #define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts and crc, underflow, overflow and stall error interrupts */ #define USB_TRNCOMPL_vect_num 127 #define USB_TRNCOMPL_vect _VECTOR(127) /* Transaction complete interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (128 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x00000) #define PROGMEM_SIZE (139264) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x00000) #define APP_SECTION_SIZE (131072) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x1E000) #define APPTABLE_SECTION_SIZE (8192) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x20000) #define BOOT_SECTION_SIZE (8192) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (16777216) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (8192) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EXTERNAL_SRAM_START (0x4000) #define EXTERNAL_SRAM_SIZE (16760832) #define EXTERNAL_SRAM_PAGE_SIZE (0) #define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND EXTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 0 /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x4C #endif /* _AVR_ATxmega128A1U_H_ */ avr-libc-1.8.0.orig/include/avr/iousb646.h0000644000000000000000000000665311732702554015031 0ustar /* Copyright (c) 2006 Anatoly Sokolov Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iousb646.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/iousb646.h - definitions for AT90USB646 */ #ifndef _AVR_AT90USB646_H_ #define _AVR_AT90USB646_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x10FF #define XRAMEND 0xFFFF #define E2END 0x7FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_HWBE (unsigned char)~_BV(3) #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x82 #endif /* _AVR_AT90USB646_H_ */ avr-libc-1.8.0.orig/include/avr/iom64.h0000644000000000000000000010260711732702554014402 0ustar /* Copyright (c) 2002, Steinar Haugen All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom64.h 2235 2011-03-17 04:13:14Z arcanum $ */ /* avr/iom64.h - defines for ATmega64 As of 2002-11-23: - This should be up to date with data sheet Rev. 2490C-AVR-09/02 */ #ifndef _AVR_IOM64_H_ #define _AVR_IOM64_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom64.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Input Pins, Port F */ #define PINF _SFR_IO8(0x00) /* Input Pins, Port E */ #define PINE _SFR_IO8(0x01) /* Data Direction Register, Port E */ #define DDRE _SFR_IO8(0x02) /* Data Register, Port E */ #define PORTE _SFR_IO8(0x03) /* ADC Data Register */ #define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and Status Register A */ #define ADCSR _SFR_IO8(0x06) /* for backwards compatibility */ #define ADCSRA _SFR_IO8(0x06) /* ADC Multiplexer select */ #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* USART0 Baud Rate Register Low */ #define UBRR0L _SFR_IO8(0x09) /* USART0 Control and Status Register B */ #define UCSR0B _SFR_IO8(0x0A) /* USART0 Control and Status Register A */ #define UCSR0A _SFR_IO8(0x0B) /* USART0 I/O Data Register */ #define UDR0 _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* Special Function I/O Register */ #define SFIOR _SFR_IO8(0x20) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* On-chip Debug Register */ #define OCDR _SFR_IO8(0x22) /* Timer2 Output Compare Register */ #define OCR2 _SFR_IO8(0x23) /* Timer/Counter 2 */ #define TCNT2 _SFR_IO8(0x24) /* Timer/Counter 2 Control register */ #define TCCR2 _SFR_IO8(0x25) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 Asynchronous Control & Status Register */ #define ASSR _SFR_IO8(0x30) /* Output Compare Register 0 */ #define OCR0 _SFR_IO8(0x31) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* for backwards compatibility */ #define MCUCSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x36) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x37) /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x38) /* External Interrupt MaSK register */ #define EIMSK _SFR_IO8(0x39) /* External Interrupt Control Register B */ #define EICRB _SFR_IO8(0x3A) /* XDIV Divide control register */ #define XDIV _SFR_IO8(0x3C) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Extended I/O registers */ /* Data Direction Register, Port F */ #define DDRF _SFR_MEM8(0x61) /* Data Register, Port F */ #define PORTF _SFR_MEM8(0x62) /* Input Pins, Port G */ #define PING _SFR_MEM8(0x63) /* Data Direction Register, Port G */ #define DDRG _SFR_MEM8(0x64) /* Data Register, Port G */ #define PORTG _SFR_MEM8(0x65) /* Store Program Memory Control and Status Register */ #define SPMCR _SFR_MEM8(0x68) #define SPMCSR _SFR_MEM8(0x68) /* for backwards compatibility with m128*/ /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x6A) /* External Memory Control Register B */ #define XMCRB _SFR_MEM8(0x6C) /* External Memory Control Register A */ #define XMCRA _SFR_MEM8(0x6D) /* Oscillator Calibration Register */ #define OSCCAL _SFR_MEM8(0x6F) /* 2-wire Serial Interface Bit Rate Register */ #define TWBR _SFR_MEM8(0x70) /* 2-wire Serial Interface Status Register */ #define TWSR _SFR_MEM8(0x71) /* 2-wire Serial Interface Address Register */ #define TWAR _SFR_MEM8(0x72) /* 2-wire Serial Interface Data Register */ #define TWDR _SFR_MEM8(0x73) /* 2-wire Serial Interface Control Register */ #define TWCR _SFR_MEM8(0x74) /* Time Counter 1 Output Compare Register C */ #define OCR1C _SFR_MEM16(0x78) #define OCR1CL _SFR_MEM8(0x78) #define OCR1CH _SFR_MEM8(0x79) /* Timer/Counter 1 Control Register C */ #define TCCR1C _SFR_MEM8(0x7A) /* Extended Timer Interrupt Flag Register */ #define ETIFR _SFR_MEM8(0x7C) /* Extended Timer Interrupt Mask Register */ #define ETIMSK _SFR_MEM8(0x7D) /* Timer/Counter 3 Input Capture Register */ #define ICR3 _SFR_MEM16(0x80) #define ICR3L _SFR_MEM8(0x80) #define ICR3H _SFR_MEM8(0x81) /* Timer/Counter 3 Output Compare Register C */ #define OCR3C _SFR_MEM16(0x82) #define OCR3CL _SFR_MEM8(0x82) #define OCR3CH _SFR_MEM8(0x83) /* Timer/Counter 3 Output Compare Register B */ #define OCR3B _SFR_MEM16(0x84) #define OCR3BL _SFR_MEM8(0x84) #define OCR3BH _SFR_MEM8(0x85) /* Timer/Counter 3 Output Compare Register A */ #define OCR3A _SFR_MEM16(0x86) #define OCR3AL _SFR_MEM8(0x86) #define OCR3AH _SFR_MEM8(0x87) /* Timer/Counter 3 Counter Register */ #define TCNT3 _SFR_MEM16(0x88) #define TCNT3L _SFR_MEM8(0x88) #define TCNT3H _SFR_MEM8(0x89) /* Timer/Counter 3 Control Register B */ #define TCCR3B _SFR_MEM8(0x8A) /* Timer/Counter 3 Control Register A */ #define TCCR3A _SFR_MEM8(0x8B) /* Timer/Counter 3 Control Register C */ #define TCCR3C _SFR_MEM8(0x8C) /* ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x8E) /* USART0 Baud Rate Register High */ #define UBRR0H _SFR_MEM8(0x90) /* USART0 Control and Status Register C */ #define UCSR0C _SFR_MEM8(0x95) /* USART1 Baud Rate Register High */ #define UBRR1H _SFR_MEM8(0x98) /* USART1 Baud Rate Register Low*/ #define UBRR1L _SFR_MEM8(0x99) /* USART1 Control and Status Register B */ #define UCSR1B _SFR_MEM8(0x9A) /* USART1 Control and Status Register A */ #define UCSR1A _SFR_MEM8(0x9B) /* USART1 I/O Data Register */ #define UDR1 _SFR_MEM8(0x9C) /* USART1 Control and Status Register C */ #define UCSR1C _SFR_MEM8(0x9D) /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* External Interrupt Request 3 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) #define SIG_INTERRUPT3 _VECTOR(4) /* External Interrupt Request 4 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) #define SIG_INTERRUPT4 _VECTOR(5) /* External Interrupt Request 5 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) #define SIG_INTERRUPT5 _VECTOR(6) /* External Interrupt Request 6 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) #define SIG_INTERRUPT6 _VECTOR(7) /* External Interrupt Request 7 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) #define SIG_INTERRUPT7 _VECTOR(8) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 9 #define TIMER2_COMP_vect _VECTOR(9) #define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 10 #define TIMER2_OVF_vect _VECTOR(10) #define SIG_OVERFLOW2 _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) #define SIG_INPUT_CAPTURE1 _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 14 #define TIMER1_OVF_vect _VECTOR(14) #define SIG_OVERFLOW1 _VECTOR(14) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 15 #define TIMER0_COMP_vect _VECTOR(15) #define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 16 #define TIMER0_OVF_vect _VECTOR(16) #define SIG_OVERFLOW0 _VECTOR(16) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 17 #define SPI_STC_vect _VECTOR(17) #define SIG_SPI _VECTOR(17) /* USART0, Rx Complete */ #define USART0_RX_vect_num 18 #define USART0_RX_vect _VECTOR(18) #define SIG_UART0_RECV _VECTOR(18) /* USART0 Data Register Empty */ #define USART0_UDRE_vect_num 19 #define USART0_UDRE_vect _VECTOR(19) #define SIG_UART0_DATA _VECTOR(19) /* USART0, Tx Complete */ #define USART0_TX_vect_num 20 #define USART0_TX_vect _VECTOR(20) #define SIG_UART0_TRANS _VECTOR(20) /* ADC Conversion Complete */ #define ADC_vect_num 21 #define ADC_vect _VECTOR(21) #define SIG_ADC _VECTOR(21) /* EEPROM Ready */ #define EE_READY_vect_num 22 #define EE_READY_vect _VECTOR(22) #define SIG_EEPROM_READY _VECTOR(22) /* Analog Comparator */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) #define SIG_COMPARATOR _VECTOR(23) /* Timer/Counter1 Compare Match C */ #define TIMER1_COMPC_vect_num 24 #define TIMER1_COMPC_vect _VECTOR(24) #define SIG_OUTPUT_COMPARE1C _VECTOR(24) /* Timer/Counter3 Capture Event */ #define TIMER3_CAPT_vect_num 25 #define TIMER3_CAPT_vect _VECTOR(25) #define SIG_INPUT_CAPTURE3 _VECTOR(25) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPA_vect_num 26 #define TIMER3_COMPA_vect _VECTOR(26) #define SIG_OUTPUT_COMPARE3A _VECTOR(26) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPB_vect_num 27 #define TIMER3_COMPB_vect _VECTOR(27) #define SIG_OUTPUT_COMPARE3B _VECTOR(27) /* Timer/Counter3 Compare Match C */ #define TIMER3_COMPC_vect_num 28 #define TIMER3_COMPC_vect _VECTOR(28) #define SIG_OUTPUT_COMPARE3C _VECTOR(28) /* Timer/Counter3 Overflow */ #define TIMER3_OVF_vect_num 29 #define TIMER3_OVF_vect _VECTOR(29) #define SIG_OVERFLOW3 _VECTOR(29) /* USART1, Rx Complete */ #define USART1_RX_vect_num 30 #define USART1_RX_vect _VECTOR(30) #define SIG_UART1_RECV _VECTOR(30) /* USART1, Data Register Empty */ #define USART1_UDRE_vect_num 31 #define USART1_UDRE_vect _VECTOR(31) #define SIG_UART1_DATA _VECTOR(31) /* USART1, Tx Complete */ #define USART1_TX_vect_num 32 #define USART1_TX_vect _VECTOR(32) #define SIG_UART1_TRANS _VECTOR(32) /* 2-wire Serial Interface */ #define TWI_vect_num 33 #define TWI_vect _VECTOR(33) #define SIG_2WIRE_SERIAL _VECTOR(33) /* Store Program Memory Read */ #define SPM_READY_vect_num 34 #define SPM_READY_vect _VECTOR(34) #define SIG_SPM_READY _VECTOR(34) #define _VECTORS_SIZE 140 /* The Register Bit names are represented by their bit number (0-7). */ /* 2-wire Control Register - TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 /* 2-wire Address Register - TWAR */ #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 /* 2-wire Status Register - TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 /* External Memory Control Register A - XMCRA */ #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW01 3 #define SRW00 2 #define SRW11 1 /* External Memory Control Register B - XMCRA */ #define XMBK 7 #define XMM2 2 #define XMM1 1 #define XMM0 0 /* XDIV Divide control register - XDIV */ #define XDIVEN 7 #define XDIV6 6 #define XDIV5 5 #define XDIV4 4 #define XDIV3 3 #define XDIV2 2 #define XDIV1 1 #define XDIV0 0 /* External Interrupt Control Register A - EICRA */ #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* External Interrupt Control Register B - EICRB */ #define ISC71 7 #define ISC70 6 #define ISC61 5 #define ISC60 4 #define ISC51 3 #define ISC50 2 #define ISC41 1 #define ISC40 0 /* Store Program Memory Control Register - SPMCSR, SPMCR */ #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* External Interrupt MaSK register - EIMSK */ #define INT7 7 #define INT6 6 #define INT5 5 #define INT4 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 /* External Interrupt Flag Register - EIFR */ #define INTF7 7 #define INTF6 6 #define INTF5 5 #define INTF4 4 #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 /* Timer/Counter Interrupt MaSK register - TIMSK */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 /* Timer/Counter Interrupt Flag Register - TIFR */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 /* Extended Timer Interrupt MaSK register - ETIMSK */ #define TICIE3 5 #define OCIE3A 4 #define OCIE3B 3 #define TOIE3 2 #define OCIE3C 1 #define OCIE1C 0 /* Extended Timer Interrupt Flag Register - ETIFR */ #define ICF3 5 #define OCF3A 4 #define OCF3B 3 #define TOV3 2 #define OCF3C 1 #define OCF1C 0 /* MCU Control Register - MCUCR */ #define SRE 7 #define SRW10 6 #define SE 5 #define SM1 4 #define SM0 3 #define SM2 2 #define IVSEL 1 #define IVCE 0 /* MCU Control And Status Register - MCUCSR */ #define JTD 7 #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* Timer/Counter Control Register (generic) */ #define FOC 7 #define WGM0 6 #define COM1 5 #define COM0 4 #define WGM1 3 #define CS2 2 #define CS1 1 #define CS0 0 /* Timer/Counter 0 Control Register - TCCR0 */ #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 2 Control Register - TCCR2 */ #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ #define AS0 3 #define TCN0UB 2 #define OCR0UB 1 #define TCR0UB 0 /* Timer/Counter Control Register A (generic) */ #define COMA1 7 #define COMA0 6 #define COMB1 5 #define COMB0 4 #define COMC1 3 #define COMC0 2 #define WGMA1 1 #define WGMA0 0 /* Timer/Counter 1 Control and Status Register A - TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define COM1C1 3 #define COM1C0 2 #define WGM11 1 #define WGM10 0 /* Timer/Counter 3 Control and Status Register A - TCCR3A */ #define COM3A1 7 #define COM3A0 6 #define COM3B1 5 #define COM3B0 4 #define COM3C1 3 #define COM3C0 2 #define WGM31 1 #define WGM30 0 /* Timer/Counter Control and Status Register B (generic) */ #define ICNC 7 #define ICES 6 #define WGMB3 4 #define WGMB2 3 #define CSB2 2 #define CSB1 1 #define CSB0 0 /* Timer/Counter 1 Control and Status Register B - TCCR1B */ #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Timer/Counter 3 Control and Status Register B - TCCR3B */ #define ICNC3 7 #define ICES3 6 #define WGM33 4 #define WGM32 3 #define CS32 2 #define CS31 1 #define CS30 0 /* Timer/Counter Control Register C (generic) */ #define FOCA 7 #define FOCB 6 #define FOCC 5 /* Timer/Counter 3 Control Register C - TCCR3C */ #define FOC3A 7 #define FOC3B 6 #define FOC3C 5 /* Timer/Counter 1 Control Register C - TCCR1C */ #define FOC1A 7 #define FOC1B 6 #define FOC1C 5 /* On-chip Debug Register - OCDR */ #define IDRD 7 #define OCDR7 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 /* Watchdog Timer Control Register - WDTCR */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ /* Special Function I/O Register - SFIOR */ #define TSM 7 #define ACME 3 #define PUD 2 #define PSR0 1 #define PSR321 0 /* Port Data Register (generic) */ #define PORT7 7 #define PORT6 6 #define PORT5 5 #define PORT4 4 #define PORT3 3 #define PORT2 2 #define PORT1 1 #define PORT0 0 /* Port Data Direction Register (generic) */ #define DD7 7 #define DD6 6 #define DD5 5 #define DD4 4 #define DD3 3 #define DD2 2 #define DD1 1 #define DD0 0 /* Port Input Pins (generic) */ #define PIN7 7 #define PIN6 6 #define PIN5 5 #define PIN4 4 #define PIN3 3 #define PIN2 2 #define PIN1 1 #define PIN0 0 /* SPI Status Register - SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPI Control Register - SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* USART Register C (generic) */ #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* USART1 Register C - UCSR1C */ #define UMSEL1 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPOL1 0 /* USART0 Register C - UCSR0C */ #define UMSEL0 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UCSZ00 1 #define UCPOL0 0 /* USART Status Register A (generic) */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define UPE 2 #define U2X 1 #define MPCM 0 /* USART1 Status Register A - UCSR1A */ #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 /* USART0 Status Register A - UCSR0A */ #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 /* USART Control Register B (generic) */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ 2 #define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ #define RXB8 1 #define TXB8 0 /* USART1 Control Register B - UCSR1B */ #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 /* USART0 Control Register B - UCSR0B */ #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 /* Analog Comparator Control and Status Register - ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADC Control and Status Register B - ADCSRB */ #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 /* ADC Control and status Register A - ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADC Multiplexer select - ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* Port A Data Register - PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Port A Data Direction Register - DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Port A Input Pins - PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Port B Data Register - PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Port B Data Direction Register - DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Port B Input Pins - PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Port C Data Register - PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Port C Data Direction Register - DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Port C Input Pins - PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Port D Data Register - PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Port D Data Direction Register - DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Port D Input Pins - PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Port E Data Register - PORTE */ #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 /* Port E Data Direction Register - DDRE */ #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 /* Port E Input Pins - PINE */ #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 /* Port F Data Register - PORTF */ #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 /* Port F Data Direction Register - DDRF */ #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 /* Port F Input Pins - PINF */ #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 /* Port G Data Register - PORTG */ #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 /* Port G Data Direction Register - DDRG */ #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 /* Port G Input Pins - PING */ #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x10FF /* Last On-Chip SRAM Location */ #define XRAMEND 0xFFFF #define E2END 0x07FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_WDTON (unsigned char)~_BV(0) #define FUSE_M103C (unsigned char)~_BV(1) #define EFUSE_DEFAULT (FUSE_M103C) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x02 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_INTERRUPT3 #pragma GCC poison SIG_INTERRUPT4 #pragma GCC poison SIG_INTERRUPT5 #pragma GCC poison SIG_INTERRUPT6 #pragma GCC poison SIG_INTERRUPT7 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART0_RECV #pragma GCC poison SIG_UART0_DATA #pragma GCC poison SIG_UART0_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_OUTPUT_COMPARE1C #pragma GCC poison SIG_INPUT_CAPTURE3 #pragma GCC poison SIG_OUTPUT_COMPARE3A #pragma GCC poison SIG_OUTPUT_COMPARE3B #pragma GCC poison SIG_OUTPUT_COMPARE3C #pragma GCC poison SIG_OVERFLOW3 #pragma GCC poison SIG_UART1_RECV #pragma GCC poison SIG_UART1_DATA #pragma GCC poison SIG_UART1_TRANS #pragma GCC poison SIG_2WIRE_SERIAL #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM64_H_ */ avr-libc-1.8.0.orig/include/avr/io90pwm316.h0000644000000000000000000011522111732702554015176 0ustar /* Copyright (c) 2007, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io90pwm316.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwm316.h - definitions for AT90PWM316 */ #ifndef _AVR_IO90PWM316_H_ #define _AVR_IO90PWM316_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io90pwm316.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Port B Input Pins Address */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 /* Port B Data Direction Register */ #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 /* Port B Data Register */ #define PORTB _SFR_IO8(0x05) #define PB0 0 #define PB1 1 #define PB2 2 #define PB3 3 #define PB4 4 #define PB5 5 #define PB6 6 #define PB7 7 /* Port C Input Pins Address */ #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 /* Port C Data Direction Register */ #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 /* Port C Data Register */ #define PORTC _SFR_IO8(0x08) #define PC0 0 #define PC1 1 #define PC2 2 #define PC3 3 #define PC4 4 #define PC5 5 #define PC6 6 #define PC7 7 /* Port D Input Pins Address */ #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 /* Port D Data Direction Register */ #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 /* Port D Data Register */ #define PORTD _SFR_IO8(0x0B) #define PD0 0 #define PD1 1 #define PD2 2 #define PD3 3 #define PD4 4 #define PD5 5 #define PD6 6 #define PD7 7 /* Port E Input Pins Address */ #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 /* Port E Data Direction Register */ #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 /* Port E Data Register */ #define PORTE _SFR_IO8(0x0E) #define PE0 0 #define PE1 1 #define PE2 2 /* Timer/Counter 0 Interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 /* Overflow Flag */ #define OCF0A 1 /* Output Compare Flag 0A */ #define OCF0B 2 /* Output Compare Flag 0B */ /* Timer/Counter1 Interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 /* Overflow Flag */ #define OCF1A 1 /* Output Compare Flag 1A*/ #define OCF1B 2 /* Output Compare Flag 1B*/ #define ICF1 5 /* Input Capture Flag 1 */ /* General Purpose I/O Register 1 */ #define GPIOR1 _SFR_IO8(0x19) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 /* General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x1A) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 /* General Purpose I/O Register 3 */ #define GPIOR3 _SFR_IO8(0x1B) #define GPIOR30 0 #define GPIOR31 1 #define GPIOR32 2 #define GPIOR33 3 #define GPIOR34 4 #define GPIOR35 5 #define GPIOR36 6 #define GPIOR37 7 /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 /* External Interrupt Mask Register */ #define EIMSK _SFR_IO8(0x1D) #define INT0 0 /* External Interrupt Request 0 Enable */ #define INT1 1 /* External Interrupt Request 1 Enable */ #define INT2 2 /* External Interrupt Request 2 Enable */ #define INT3 3 /* External Interrupt Request 3 Enable */ /* General Purpose I/O Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1F) #define EERE 0 /* EEPROM Read Enable */ #define EEWE 1 /* EEPROM Write Enable */ #define EEMWE 2 /* EEPROM Master Write Enable */ #define EERIE 3 /* EEPROM Ready Interrupt Enable */ /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 /* The EEPROM Address Registers */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) #define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ #define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ #define TSM 7 /* Timer/Counter Synchronization Mode */ /* Timer/Counter Control Register A */ #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 /* Waveform Generation Mode */ #define WGM01 1 /* Waveform Generation Mode */ #define COM0B0 4 /* Compare Output Mode, Fast PWm */ #define COM0B1 5 /* Compare Output Mode, Fast PWm */ #define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ #define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ /* Timer/Counter Control Register B */ #define TCCR0B _SFR_IO8(0x25) #define CS00 0 /* Clock Select */ #define CS01 1 /* Clock Select */ #define CS02 2 /* Clock Select */ #define WGM02 3 /* Waveform Generation Mode */ #define FOC0B 6 /* Force Output Compare B */ #define FOC0A 7 /* Force Output Compare A */ /* Timer/Counter0 Register */ #define TCNT0 _SFR_IO8(0x26) #define TCNT00 0 #define TCNT01 1 #define TCNT02 2 #define TCNT03 3 #define TCNT04 4 #define TCNT05 5 #define TCNT06 6 #define TCNT07 7 /* Timer/Counter0 Output Compare Register A */ #define OCR0A _SFR_IO8(0x27) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 /* Timer/Counter0 Output Compare Register B */ #define OCR0B _SFR_IO8(0x28) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 /* PLL Control and Status Register */ #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 /* PLL Lock Detector */ #define PLLE 1 /* PLL Enable */ #define PLLF 2 /* PLL Factor */ /* SPI Control Register */ #define SPCR _SFR_IO8(0x2C) #define SPR0 0 /* SPI Clock Rate Select 0 */ #define SPR1 1 /* SPI Clock Rate Select 1 */ #define CPHA 2 /* Clock Phase */ #define CPOL 3 /* Clock polarity */ #define MSTR 4 /* Master/Slave Select */ #define DORD 5 /* Data Order */ #define SPE 6 /* SPI Enable */ #define SPIE 7 /* SPI Interrupt Enable */ /* SPI Status Register */ #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 /* Double SPI Speed Bit */ #define WCOL 6 /* Write Collision Flag */ #define SPIF 7 /* SPI Interrupt Flag */ /* SPI Data Register */ #define SPDR _SFR_IO8(0x2E) #define SPD0 0 #define SPD1 1 #define SPD2 2 #define SPD3 3 #define SPD4 4 #define SPD5 5 #define SPD6 6 #define SPD7 7 /* Analog Comparator Status Register */ #define ACSR _SFR_IO8(0x30) #define AC0O 0 /* Analog Comparator 0 Output Bit */ #define AC1O 1 /* Analog Comparator 1 Output Bit */ #define AC2O 2 /* Analog Comparator 2 Output Bit */ #define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ #define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ #define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ #define ACCKDIV 7 /* Analog Comparator Clock Divider */ /* Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) #define SE 0 /* Sleep Enable */ #define SM0 1 /* Sleep Mode Select bit0 */ #define SM1 2 /* Sleep Mode Select bit1 */ #define SM2 3 /* Sleep Mode Select bit2 */ /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) #define PORF 0 /* Power-on reset flag */ #define EXTRF 1 /* External Reset Flag */ #define BORF 2 /* Brown-out Reset Flag */ #define WDRF 3 /* Watchdog Reset Flag */ /* MCU Control Register */ #define MCUCR _SFR_IO8(0x35) #define IVCE 0 /* Interrupt Vector Change Enable */ #define IVSEL 1 /* Interrupt Vector Select */ #define PUD 4 /* Pull-up disable */ #define SPIPS 7 /* SPI Pin Select */ /* Store Program Memory Control Register */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 /* Store Program Memory Enable */ #define PGERS 1 /* Page Erase */ #define PGWRT 2 /* Page Write */ #define BLBSET 3 /* Boot Lock Bit Set */ #define RWWSRE 4 /* Read While Write section read enable */ #define RWWSB 6 /* Read While Write Section Busy */ #define SPMIE 7 /* SPM Interrupt Enable */ /* Watchdog Timer Control Register */ #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 /* Watchdog Timer Prescaler bit0 */ #define WDP1 1 /* Watchdog Timer Prescaler bit1 */ #define WDP2 2 /* Watchdog Timer Prescaler bit2 */ #define WDE 3 /* Watchdog Enable */ #define WDCE 4 /* Watchdog Change Enable */ #define WDP3 5 /* Watchdog Timer Prescaler bit3 */ #define WDIE 6 /* Watchdog Timeout Interrupt Enable */ #define WDIF 7 /* Watchdog Timeout Interrupt Flag */ /* Clock Prescaler Register */ #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 /* Clock Prescaler Select bit0 */ #define CLKPS1 1 /* Clock Prescaler Select bit1 */ #define CLKPS2 2 /* Clock Prescaler Select bit2 */ #define CLKPS3 3 /* Clock Prescaler Select bit3 */ #define CLKPCE 7 /* Clock Prescaler Change Enable */ /* Power Reduction Register */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 /* Power Reduction ADC */ #define PRUSART 1 /* Power Reduction USART */ #define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ #define PRTIM0 3 /* Power Reduction Timer/Counter0 */ #define PRTIM1 4 /* Power Reduction Timer/Counter1 */ #define PRPSC0 5 /* Power Reduction PSC0 */ #define PRPSC1 6 /* Power Reduction PSC1 */ #define PRPSC2 7 /* Power Reduction PSC2 */ /* Oscillator Calibration Value */ #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 /* Timer/Counter0 Interrupt Mask Register */ #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 /* Overflow Interrupt Enable */ #define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ #define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ /* Timer/Counter1 Interrupt Mask Register */ #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 /* Overflow Interrupt Enable */ #define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ #define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ #define ICIE1 5 /* Input Capture Interrupt Enable */ /* Amplifier 0 Control and Status register */ #define AMP0CSR _SFR_MEM8(0x76) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 /* Amplifier 1 Control and Status register */ #define AMP1CSR _SFR_MEM8(0x77) #define AMP1TS0 0 #define AMP1TS1 1 #define AMP1G0 4 #define AMP1G1 5 #define AMP1IS 6 #define AMP1EN 7 /* ADC Result Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) /* ADC Control and Status Register A */ #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 /* ADC Prescaler Select bit0 */ #define ADPS1 1 /* ADC Prescaler Select bit1 */ #define ADPS2 2 /* ADC Prescaler Select bit2 */ #define ADIE 3 /* ADC Interrupt Enable */ #define ADIF 4 /* ADC Interrupt Flag */ #define ADATE 5 /* ADC Auto Trigger Enable */ #define ADSC 6 /* ADC Start Conversion */ #define ADEN 7 /* ADC Enable */ /* ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 /* ADC Auto Trigger Source 0 */ #define ADTS1 1 /* ADC Auto Trigger Source 1 */ #define ADTS2 2 /* ADC Auto Trigger Source 2 */ #define ADTS3 3 /* ADC Auto Trigger Source 3 */ #define ADHSM 7 /* ADC High Speed Mode */ /* ADC multiplexer Selection Register */ #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 /* Analog Channel and Gain Selection bit0 */ #define MUX1 1 /* Analog Channel and Gain Selection bit1 */ #define MUX2 2 /* Analog Channel and Gain Selection bit2 */ #define MUX3 3 /* Analog Channel and Gain Selection bit3 */ #define ADLAR 5 /* Left Adjust Result */ #define REFS0 6 /* Reference Selection bit0 */ #define REFS1 7 /* Reference Selection bit1 */ /* Digital Input Disable Register 0 */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 /* ADC0 Digital input Disable */ #define ADC1D 1 /* ADC1 Digital input Disable */ #define ADC2D 2 /* ADC2 Digital input Disable */ #define ADC3D 3 /* ADC3 Digital input Disable */ #define ADC4D 4 /* ADC4 Digital input Disable */ #define ADC5D 5 /* ADC5 Digital input Disable */ #define ADC6D 6 /* ADC6 Digital input Disable */ #define ADC7D 7 /* ADC7 Digital input Disable */ /* Digital Input Disable Register 1 */ #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 /* ADC8 Digital input Disable */ #define ADC9D 1 /* ADC9 Digital input Disable */ #define ADC10D 2 /* ADC10 Digital input Disable */ #define AMP0ND 3 #define AMP0PD 4 #define ACMP0D 5 /* Timer/Counter1 Control Register A */ #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 /* Waveform Generation Mode */ #define WGM11 1 /* Waveform Generation Mode */ #define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ #define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ #define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ #define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ /* Timer/Counter1 Control Register B */ #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 /* Prescaler source of Timer/Counter 1 */ #define CS11 1 /* Prescaler source of Timer/Counter 1 */ #define CS12 2 /* Prescaler source of Timer/Counter 1 */ #define WGM12 3 /* Waveform Generation Mode */ #define WGM13 4 /* Waveform Generation Mode */ #define ICES1 6 /* Input Capture 1 Edge Select */ #define ICNC1 7 /* Input Capture 1 Noise Canceler */ /* Timer/Counter1 Control Register C */ #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 /* Force Output Compare for Channel B */ #define FOC1A 7 /* Force Output Compare for Channel A */ /* Timer/Counter1 */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT10 0 #define TCNT11 1 #define TCNT12 2 #define TCNT13 3 #define TCNT14 4 #define TCNT15 5 #define TCNT16 6 #define TCNT17 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT18 0 #define TCNT19 1 #define TCNT110 2 #define TCNT111 3 #define TCNT112 4 #define TCNT113 5 #define TCNT114 6 #define TCNT115 7 /* Input Capture Register 1 */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR17 7 #define ICR16 6 #define ICR15 5 #define ICR14 4 #define ICR13 3 #define ICR12 2 #define ICR11 1 #define ICR10 0 #define ICR1H _SFR_MEM8(0x87) #define ICR115 7 #define ICR114 6 #define ICR113 5 #define ICR112 4 #define ICR111 3 #define ICR110 2 #define ICR19 1 #define ICR18 0 /* Output Compare Register 1 A */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1A8 0 #define OCR1A9 1 #define OCR1A10 2 #define OCR1A11 3 #define OCR1A12 4 #define OCR1A13 5 #define OCR1A14 6 #define OCR1A15 7 /* Output Compare Register 1 B */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1B8 0 #define OCR1B9 1 #define OCR1B10 2 #define OCR1B11 3 #define OCR1B12 4 #define OCR1B13 5 #define OCR1B14 6 #define OCR1B15 7 /* PSC0 Interrupt Flag Register */ #define PIFR0 _SFR_MEM8(0xA0) #define PEOP0 0 /* End Of PSC0 Interrupt */ #define PRN00 1 /* PSC0 Ramp Number bit0 */ #define PRN01 2 /* PSC0 Ramp Number bit1 */ #define PEV0A 3 /* PSC0 External Event A Interrupt */ #define PEV0B 4 /* PSC0 External Event B Interrupt */ #define PSEI0 5 /* PSC0 Synchro Error Interrupt */ #define POAC0A 6 /* PSC0 Output A Activity */ #define POAC0B 7 /* PSC0 Output B Activity */ /* PSC0 Interrupt Mask Register */ #define PIM0 _SFR_MEM8(0xA1) #define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ #define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ #define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ #define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ /* PSC1 Interrupt Flag Register */ #define PIFR1 _SFR_MEM8(0xA2) #define PEOP1 0 #define PRN10 1 #define PRN11 2 #define PEV1A 3 #define PEV1B 4 #define PSEI1 5 #define POAC1A 6 #define POAC1B 7 /* PSC1 Interrupt Mask Register */ #define PIM1 _SFR_MEM8(0xA3) /* PSC2 Interrupt Flag Register */ #define PIFR2 _SFR_MEM8(0xA4) #define PEOP2 0 /* End Of PSC2 Interrupt */ #define PRN20 1 /* PSC2 Ramp Number bit0 */ #define PRN21 2 /* PSC2 Ramp Number bit1 */ #define PEV2A 3 /* PSC2 External Event A Interrupt */ #define PEV2B 4 /* PSC2 External Event B Interrupt */ #define PSEI2 5 /* PSC2 Synchro Error Interrupt */ #define POAC2A 6 /* PSC2 Output A Activity */ #define POAC2B 7 /* PSC2 Output B Activity */ /* PSC2 Interrupt Mask Register */ #define PIM2 _SFR_MEM8(0xA5) #define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ #define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ #define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ #define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ /* Digital to Analog Conversion Control Register */ #define DACON _SFR_MEM8(0xAA) #define DAEN 0 /* Digital to Analog Enable bit */ #define DAOE 1 /* Digital to Analog Output Enable bit */ #define DALA 2 /* Digital to Analog Left Adjust */ #define DATS0 4 /* DAC Trigger Selection bit0 */ #define DATS1 5 /* DAC Trigger Selection bit1 */ #define DATS2 6 /* DAC Trigger Selection bit2 */ #define DAATE 7 /* DAC Auto Trigger Enable bit */ /* Digital to Analog Converter input Register */ #define DAC _SFR_MEM16(0xAB) #define DACL _SFR_MEM8(0xAB) #define DACH _SFR_MEM8(0xAC) /* Analog Comparator 0 Control Register */ #define AC0CON _SFR_MEM8(0xAD) #define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ #define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ #define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ #define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ #define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ #define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ #define AC0EN 7 /* Analog Comparator 0 Enable Bit */ /* Analog Comparator 1 Control Register */ #define AC1CON _SFR_MEM8(0xAE) #define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */ #define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */ #define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */ #define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */ #define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */ #define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */ #define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */ #define AC1EN 7 /* Analog Comparator 1 Enable Bit */ /* Analog Comparator 2 Control Register */ #define AC2CON _SFR_MEM8(0xAF) #define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ #define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ #define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ #define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ #define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ #define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ #define AC2EN 7 /* Analog Comparator 2 Enable Bit */ /* USART Control and Status Register A */ #define UCSRA _SFR_MEM8(0xC0) #define MPCM 0 /* Multi-processor Communication Mode */ #define U2X 1 /* Double the USART Transmission Speed */ #define UPE 2 /* USART Parity Error */ #define DOR 3 /* Data OverRun */ #define FE 4 /* Frame Error */ #define UDRE 5 /* USART Data Register Empty */ #define TXC 6 /* USART Transmit Complete */ #define RXC 7 /* USART Receive Complete */ /* USART Control and Status Register B */ #define UCSRB _SFR_MEM8(0xC1) #define TXB8 0 /* Transmit Data Bit 8 */ #define RXB8 1 /* Receive Data Bit 8 */ #define UCSZ2 2 /* Character Size */ #define TXEN 3 /* Transmitter Enable */ #define RXEN 4 /* Receiver Enable */ #define UDRIE 5 /* USART Data Register Empty Interrupt Enable */ #define TXCIE 6 /* TX Complete Interrupt Enable */ #define RXCIE 7 /* RX Complete Interrupt Enable */ /* USART Control and Status Register C */ #define UCSRC _SFR_MEM8(0xC2) #define UCPOL 0 /* Clock Polarity */ #define UCSZ0 1 /* Character Size bit0 */ #define UCSZ1 2 /* Character Size bit1 */ #define USBS 3 /* Stop Bit Select */ #define UPM0 4 /* Parity Mode bit0 */ #define UPM1 5 /* Parity Mode bit1 */ #define UMSEL 6 /* USART Mode Select */ /* USART Baud Rate Register */ #define UBRR _SFR_MEM16(0xC4) #define UBRRL _SFR_MEM8(0xC4) #define UBRRH _SFR_MEM8(0xC5) /* USART I/O Data Register */ #define UDR _SFR_MEM8(0xC6) /* EUSART Control and Status Register A */ #define EUCSRA _SFR_MEM8(0xC8) #define URxS0 0 /* EUSART Receive Character Size bit0 */ #define URxS1 1 /* EUSART Receive Character Size bit1 */ #define URxS2 2 /* EUSART Receive Character Size bit2 */ #define URxS3 3 /* EUSART Receive Character Size bit3 */ #define UTxS0 4 /* EUSART Transmit Character Size bit0 */ #define UTxS1 5 /* EUSART Transmit Character Size bit1 */ #define UTxS2 6 /* EUSART Transmit Character Size bit2 */ #define UTxS3 7 /* EUSART Transmit Character Size bit3 */ /* EUSART Control and Status Register B */ #define EUCSRB _SFR_MEM8(0xC9) #define BODR 0 /* Bit Order */ #define EMCH 1 /* Manchester mode */ #define EUSBS 3 /* EUSBS Enable Bit */ #define EUSART 4 /* EUSART Enable Bit */ /* EUSART Control and Status Register C */ #define EUCSRC _SFR_MEM8(0xCA) #define STP0 0 /* Stop bits values bit0 */ #define STP1 1 /* Stop bits values bit1 */ #define F1617 2 #define FEM 3 /* Frame Error Manchester */ /* Manchester receiver Baud Rate Registers */ #define MUBRR _SFR_MEM16(0xCC) #define MUBRRL _SFR_MEM8(0xCC) #define MUBRRH _SFR_MEM8(0xCD) /* EUSART I/O Data Register */ #define EUDR _SFR_MEM8(0xCE) /* PSC 0 Synchro and Output Configuration */ #define PSOC0 _SFR_MEM8(0xD0) #define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ #define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ #define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ #define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ /* Output Compare SA Registers */ #define OCR0SA _SFR_MEM16(0xD2) #define OCR0SAL _SFR_MEM8(0xD2) #define OCR0SAH _SFR_MEM8(0xD3) /* Output Compare RA Registers */ #define OCR0RA _SFR_MEM16(0xD4) #define OCR0RAL _SFR_MEM8(0xD4) #define OCR0RAH _SFR_MEM8(0xD5) /* Output Compare SB Registers */ #define OCR0SB _SFR_MEM16(0xD6) #define OCR0SBL _SFR_MEM8(0xD6) #define OCR0SBH _SFR_MEM8(0xD7) /* Output Compare RB Registers */ #define OCR0RB _SFR_MEM16(0xD8) #define OCR0RBL _SFR_MEM8(0xD8) #define OCR0RBH _SFR_MEM8(0xD9) /* PSC 0 Configuration Register */ #define PCNF0 _SFR_MEM8(0xDA) #define PCLKSEL0 1 /* PSC 0 Input Clock Select */ #define POP0 2 /* PSC 0 Output Polarity */ #define PMODE00 3 /* PSC 0 Mode bit0 */ #define PMODE01 4 /* PSC 0 Mode bit1 */ #define PLOCK0 5 /* PSC 0 Lock */ #define PALOCK0 6 /* PSC 0 Autolock */ #define PFIFTY0 7 /* PSC 0 Fifty */ /* PSC 0 Control Register */ #define PCTL0 _SFR_MEM8(0xDB) #define PRUN0 0 /* PSC 0 Run */ #define PCCYC0 1 /* PSC 0 Complete Cycle */ #define PARUN0 2 /* PSC 0 Autorun */ #define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ #define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ #define PBFM0 5 /* Balance Flank Width Modulation */ #define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ #define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ /* PSC 0 Input A Control Register */ #define PFRC0A _SFR_MEM8(0xDC) #define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ #define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ #define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ #define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ #define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ #define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ #define PISEL0A 6 /* PSC 0 Input Select for Part A */ #define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ /* PSC 0 Input B Control Register */ #define PFRC0B _SFR_MEM8(0xDD) #define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ #define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ #define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ #define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ #define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ #define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ #define PISEL0B 6 /* PSC 0 Input Select for Part B */ #define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ /* PSC 0 Input Capture Registers */ #define PICR0 _SFR_MEM16(0xDE) #define PICR0L _SFR_MEM8(0xDE) #define PICR0H _SFR_MEM8(0xDF) #define PCST0 7 /* PSC Capture Software Trig bit */ /* PSC 1 Synchro and Output Configuration */ #define PSOC1 _SFR_MEM8(0xE0) #define POEN1A 0 #define POEN1B 2 #define PSYNC1_0 4 #define PSYNC1_1 5 /* Output Compare SA Registers */ #define OCR1SA _SFR_MEM16(0xE2) #define OCR1SAL _SFR_MEM8(0xE2) #define OCR1SAH _SFR_MEM8(0xE3) /* Output Compare RA Registers */ #define OCR1RA _SFR_MEM16(0xE4) #define OCR1RAL _SFR_MEM8(0xE4) #define OCR1RAH _SFR_MEM8(0xE5) /* Output Compare SB Registers */ #define OCR1SB _SFR_MEM16(0xE6) #define OCR1SBL _SFR_MEM8(0xE6) #define OCR1SBH _SFR_MEM8(0xE7) /* Output Compare RB Registers */ #define OCR1RB _SFR_MEM16(0xE8) #define OCR1RBL _SFR_MEM8(0xE8) #define OCR1RBH _SFR_MEM8(0xE9) /* PSC 1 Configuration Register */ #define PCNF1 _SFR_MEM8(0xEA) #define PCLKSEL1 1 #define POP1 2 #define PMODE10 3 #define PMODE11 4 #define PLOCK1 5 #define PALOCK1 6 #define PFIFTY1 7 /* PSC 1 Control Register */ #define PCTL1 _SFR_MEM8(0xEB) #define PRUN1 0 #define PCCYC1 1 #define PARUN1 2 #define PAOC1A 3 #define PAOC1B 4 #define PBFM1 5 #define PPRE10 6 #define PPRE11 7 /* PSC 1 Input A Control Register */ #define PFRC1A _SFR_MEM8(0xEC) #define PRFM1A0 0 #define PRFM1A1 1 #define PRFM1A2 2 #define PRFM1A3 3 #define PFLTE1A 4 #define PELEV1A 5 #define PISEL1A 6 #define PCAE1A 7 /* PSC 1 Input B Control Register */ #define PFRC1B _SFR_MEM8(0xED) #define PRFM1B0 0 #define PRFM1B1 1 #define PRFM1B2 2 #define PRFM1B3 3 #define PFLTE1B 4 #define PELEV1B 5 #define PISEL1B 6 #define PCAE1B 7 /* PSC 1 Input Capture Registers */ #define PICR1 _SFR_MEM16(0xEE) #define PICR1L _SFR_MEM8(0xEE) #define PICR1H _SFR_MEM8(0xEF) /* PSC 2 Synchro and Output Configuration */ #define PSOC2 _SFR_MEM8(0xF0) #define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ #define POEN2C 1 /* PSCOUT22 Output Enable */ #define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ #define POEN2D 3 /* PSCOUT23 Output Enable */ #define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ #define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ #define POS22 6 /* PSCOUT22 Selection */ #define POS23 7 /* PSCOUT23 Selection */ /* PSC 2 Output Matrix */ #define POM2 _SFR_MEM8(0xF1) #define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ #define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ #define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ #define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ #define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ #define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ #define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ #define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ /* Output Compare SA Registers */ #define OCR2SA _SFR_MEM16(0xF2) #define OCR2SAL _SFR_MEM8(0xF2) #define OCR2SAH _SFR_MEM8(0xF3) /* Output Compare RA Registers */ #define OCR2RA _SFR_MEM16(0xF4) #define OCR2RAL _SFR_MEM8(0xF4) #define OCR2RAH _SFR_MEM8(0xF5) /* Output Compare SB Registers */ #define OCR2SB _SFR_MEM16(0xF6) #define OCR2SBL _SFR_MEM8(0xF6) #define OCR2SBH _SFR_MEM8(0xF7) /* Output Compare RB Registers */ #define OCR2RB _SFR_MEM16(0xF8) #define OCR2RBL _SFR_MEM8(0xF8) #define OCR2RBH _SFR_MEM8(0xF9) /* PSC 2 Configuration Register */ #define PCNF2 _SFR_MEM8(0xFA) #define POME2 0 /* PSC 2 Output Matrix Enable */ #define PCLKSEL2 1 /* PSC 2 Input Clock Select */ #define POP2 2 /* PSC 2 Output Polarity */ #define PMODE20 3 /* PSC 2 Mode bit0 */ #define PMODE21 4 /* PSC 2 Mode bit1 */ #define PLOCK2 5 /* PSC 2 Lock */ #define PALOCK2 6 /* PSC 2 Autolock */ #define PFIFTY2 7 /* PSC 2 Fifty */ /* PSC 2 Control Register */ #define PCTL2 _SFR_MEM8(0xFB) #define PRUN2 0 /* PSC 2 Run */ #define PCCYC2 1 /* PSC 2 Complete Cycle */ #define PARUN2 2 /* PSC 2 Autorun */ #define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ #define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ #define PBFM2 5 /* Balance Flank Width Modulation */ #define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ #define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ /* PSC 2 Input A Control Register */ #define PFRC2A _SFR_MEM8(0xFC) #define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ #define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ #define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ #define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ #define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ #define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ #define PISEL2A 6 /* PSC 2 Input Select for Part A */ #define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ /* PSC 2 Input B Control Register */ #define PFRC2B _SFR_MEM8(0xFD) #define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ #define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ #define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ #define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ #define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ #define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ #define PISEL2B 6 /* PSC 2 Input Select for Part B */ #define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ /* PSC 2 Input Capture Registers */ #define PICR2 _SFR_MEM16(0xFE) #define PICR2L _SFR_MEM8(0xFE) #define PICR2H _SFR_MEM8(0xFF) #define PCST2 7 /* PSC Capture Software Trig bit */ /* Interrupt Vectors */ /* Interrupt 0 is the reset vector. */ /* PSC2 Capture Event */ #define PSC2_CAPT_vect_num 1 #define PSC2_CAPT_vect _VECTOR(1) /* PSC2 End Cycle */ #define PSC2_EC_vect_num 2 #define PSC2_EC_vect _VECTOR(2) /* PSC1 Capture Event */ #define PSC1_CAPT_vect_num 3 #define PSC1_CAPT_vect _VECTOR(3) /* PSC1 End Cycle */ #define PSC1_EC_vect_num 4 #define PSC1_EC_vect _VECTOR(4) /* PSC0 Capture Event */ #define PSC0_CAPT_vect_num 5 #define PSC0_CAPT_vect _VECTOR(5) /* PSC0 End Cycle */ #define PSC0_EC_vect_num 6 #define PSC0_EC_vect _VECTOR(6) /* Analog Comparator 0 */ #define ANALOG_COMP_0_vect_num 7 #define ANALOG_COMP_0_vect _VECTOR(7) /* Analog Comparator 1 */ #define ANALOG_COMP_1_vect_num 8 #define ANALOG_COMP_1_vect _VECTOR(8) /* Analog Comparator 2 */ #define ANALOG_COMP_2_vect_num 9 #define ANALOG_COMP_2_vect _VECTOR(9) /* External Interrupt Request 0 */ #define INT0_vect_num 10 #define INT0_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMP_A_vect_num 16 #define TIMER0_COMP_A_vect _VECTOR(16) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) /* ADC Conversion Complete */ #define ADC_vect_num 18 #define ADC_vect _VECTOR(18) /* External Interrupt Request 1 */ #define INT1_vect_num 19 #define INT1_vect _VECTOR(19) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 20 #define SPI_STC_vect _VECTOR(20) /* USART, Rx Complete */ #define USART_RX_vect_num 21 #define USART_RX_vect _VECTOR(21) /* USART Data Register Empty */ #define USART_UDRE_vect_num 22 #define USART_UDRE_vect _VECTOR(22) /* USART, Tx Complete */ #define USART_TX_vect_num 23 #define USART_TX_vect _VECTOR(23) /* External Interrupt Request 2 */ #define INT2_vect_num 24 #define INT2_vect _VECTOR(24) /* Watchdog Timeout Interrupt */ #define WDT_vect_num 25 #define WDT_vect _VECTOR(25) /* EEPROM Ready */ #define EE_READY_vect_num 26 #define EE_READY_vect _VECTOR(26) /* Timer Counter 0 Compare Match B */ #define TIMER0_COMPB_vect_num 27 #define TIMER0_COMPB_vect _VECTOR(27) /* External Interrupt Request 3 */ #define INT3_vect_num 28 #define INT3_vect _VECTOR(28) /* Store Program Memory Read */ #define SPM_READY_vect_num 31 #define SPM_READY_vect _VECTOR(31) #define _VECTORS_SIZE (4 * 32) /* Constants */ #define RAMEND 0x4FF #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF #define SPM_PAGESIZE 128 /* Fuse Information */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_PSCRV (unsigned char)~_BV(4) #define FUSE_PSC0RB (unsigned char)~_BV(5) #define FUSE_PSC1RB (unsigned char)~_BV(6) #define FUSE_PSC2RB (unsigned char)~_BV(7) #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x83 #endif /* _AVR_IO90PWM316_H_ */ avr-libc-1.8.0.orig/include/avr/iom8u2.h0000644000000000000000000005007211732702554014565 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom8u2.h 2245 2011-05-12 22:42:21Z arcanum $ */ /* avr/iom8u2.h - definitions for ATmega8U2 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom8u2.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega8U2_H_ #define _AVR_ATmega8U2_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define OCF1C 3 #define ICF1 5 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define INTF4 4 #define INTF5 5 #define INTF6 6 #define INTF7 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define INT4 4 #define INT5 5 #define INT6 6 #define INT7 7 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLP0 2 #define PLLP1 3 #define PLLP2 4 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define DWDR _SFR_IO8(0x31) #define DWDR0 0 #define DWDR1 1 #define DWDR2 2 #define DWDR3 3 #define DWDR4 4 #define DWDR5 5 #define DWDR6 6 #define DWDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define USBRF 5 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define EIND _SFR_IO8(0x3C) #define EIND0 0 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define WDTCKD _SFR_MEM8(0x62) #define WCLKD0 0 #define WCLKD1 1 #define WDEWIE 2 #define WDEWIF 3 #define REGCR _SFR_MEM8(0x63) #define REGDIS 0 #define PRR0 _SFR_MEM8(0x64) #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRR1 _SFR_MEM8(0x65) #define PRUSART1 0 #define PRUSB 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define EICRB _SFR_MEM8(0x6A) #define ISC40 0 #define ISC41 1 #define ISC50 2 #define ISC51 3 #define ISC60 4 #define ISC61 5 #define ISC70 6 #define ISC71 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define OCIE1C 3 #define ICIE1 5 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1C0 2 #define COM1C1 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1C 5 #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CL0 0 #define OCR1CL1 1 #define OCR1CL2 2 #define OCR1CL3 3 #define OCR1CL4 4 #define OCR1CL5 5 #define OCR1CL6 6 #define OCR1CL7 7 #define OCR1CH _SFR_MEM8(0x8D) #define OCR1CH0 0 #define OCR1CH1 1 #define OCR1CH2 2 #define OCR1CH3 3 #define OCR1CH4 4 #define OCR1CH5 5 #define OCR1CH6 6 #define OCR1CH7 7 #define UCSR1A _SFR_MEM8(0xC8) #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 #define UCSR1B _SFR_MEM8(0xC9) #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 #define UCSR1C _SFR_MEM8(0xCA) #define UCPOL1 0 #define UCSZ10 1 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 #define UCSR1D _SFR_MEM8(0xCB) #define RTSEN 0 #define CTSEN 1 #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1_0 0 #define UBRR1_1 1 #define UBRR1_2 2 #define UBRR1_3 3 #define UBRR1_4 4 #define UBRR1_5 5 #define UBRR1_6 6 #define UBRR1_7 7 #define UBRR1H _SFR_MEM8(0xCD) #define UBRR1_8 0 #define UBRR1_9 1 #define UBRR1_10 2 #define UBRR1_11 3 #define UDR1 _SFR_MEM8(0xCE) #define UDR1_0 0 #define UDR1_1 1 #define UDR1_2 2 #define UDR1_3 3 #define UDR1_4 4 #define UDR1_5 5 #define UDR1_6 6 #define UDR1_7 7 #define CLKSEL0 _SFR_MEM8(0xD0) #define CLKS 0 #define EXTE 2 #define RCE 3 #define EXSUT0 4 #define EXSUT1 5 #define RCSUT0 6 #define RCSUT1 7 #define CLKSEL1 _SFR_MEM8(0xD1) #define EXCKSEL0 0 #define EXCKSEL1 1 #define EXCKSEL2 2 #define EXCKSEL3 3 #define RCCKSEL0 4 #define RCCKSEL1 5 #define RCCKSEL2 6 #define RCCKSEL3 7 #define CLKSTA _SFR_MEM8(0xD2) #define EXTON 0 #define RCON 1 #define USBCON _SFR_MEM8(0xD8) #define FRZCLK 5 #define USBE 7 #define UDCON _SFR_MEM8(0xE0) #define DETACH 0 #define RMWKUP 1 #define RSTCPU 2 #define UDINT _SFR_MEM8(0xE1) #define SUSPI 0 #define SOFI 2 #define EORSTI 3 #define WAKEUPI 4 #define EORSMI 5 #define UPRSMI 6 #define UDIEN _SFR_MEM8(0xE2) #define SUSPE 0 #define SOFE 2 #define EORSTE 3 #define WAKEUPE 4 #define EORSME 5 #define UPRSME 6 #define UDADDR _SFR_MEM8(0xE3) #define UADD0 0 #define UADD1 1 #define UADD2 2 #define UADD3 3 #define UADD4 4 #define UADD5 5 #define UADD6 6 #define ADDEN 7 #define UDFNUM _SFR_MEM16(0xE4) #define UDFNUML _SFR_MEM8(0xE4) #define FNUM0 0 #define FNUM1 1 #define FNUM2 2 #define FNUM3 3 #define FNUM4 4 #define FNUM5 5 #define FNUM6 6 #define FNUM7 7 #define UDFNUMH _SFR_MEM8(0xE5) #define FNUM8 0 #define FNUM9 1 #define FNUM10 2 #define UDMFN _SFR_MEM8(0xE6) #define FNCERR 4 #define UEINTX _SFR_MEM8(0xE8) #define TXINI 0 #define STALLEDI 1 #define RXOUTI 2 #define RXSTPI 3 #define NAKOUTI 4 #define RWAL 5 #define NAKINI 6 #define FIFOCON 7 #define UENUM _SFR_MEM8(0xE9) #define EPNUM0 0 #define EPNUM1 1 #define EPNUM2 2 #define UERST _SFR_MEM8(0xEA) #define EPRST0 0 #define EPRST1 1 #define EPRST2 2 #define EPRST3 3 #define EPRST4 4 #define UECONX _SFR_MEM8(0xEB) #define EPEN 0 #define RSTDT 3 #define STALLRQC 4 #define STALLRQ 5 #define UECFG0X _SFR_MEM8(0xEC) #define EPDIR 0 #define EPTYPE0 6 #define EPTYPE1 7 #define UECFG1X _SFR_MEM8(0xED) #define ALLOC 1 #define EPBK0 2 #define EPBK1 3 #define EPSIZE0 4 #define EPSIZE1 5 #define EPSIZE2 6 #define UESTA0X _SFR_MEM8(0xEE) #define NBUSYBK0 0 #define NBUSYBK1 1 #define DTSEQ0 2 #define DTSEQ1 3 #define UNDERFI 5 #define OVERFI 6 #define CFGOK 7 #define UESTA1X _SFR_MEM8(0xEF) #define CURRBK0 0 #define CURRBK1 1 #define CTRLDIR 2 #define UEIENX _SFR_MEM8(0xF0) #define TXINE 0 #define STALLEDE 1 #define RXOUTE 2 #define RXSTPE 3 #define NAKOUTE 4 #define NAKINE 6 #define FLERRE 7 #define UEDATX _SFR_MEM8(0xF1) #define DAT0 0 #define DAT1 1 #define DAT2 2 #define DAT3 3 #define DAT4 4 #define DAT5 5 #define DAT6 6 #define DAT7 7 #define UEBCLX _SFR_MEM8(0xF2) #define BYCT0 0 #define BYCT1 1 #define BYCT2 2 #define BYCT3 3 #define BYCT4 4 #define BYCT5 5 #define BYCT6 6 #define BYCT7 7 #define UEINT _SFR_MEM8(0xF4) #define EPINT0 0 #define EPINT1 1 #define EPINT2 2 #define EPINT3 3 #define EPINT4 4 #define UPOE _SFR_MEM8(0XFB) #define UPWE1 7 #define UPWE0 6 #define UPDRV1 5 #define UPDRV0 4 #define SCKI 3 #define DATAI 2 #define DPI 1 #define DMI 0 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ #define PCINT0_vect_num 9 #define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 10 #define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */ #define USB_GEN_vect_num 11 #define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */ #define USB_COM_vect_num 12 #define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */ #define WDT_vect_num 13 #define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */ #define TIMER1_CAPT_vect_num 14 #define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ #define TIMER1_COMPA_vect_num 15 #define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ #define TIMER0_COMPA_vect_num 19 #define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 20 #define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 21 #define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 22 #define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */ #define USART1_RX_vect_num 23 #define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */ #define USART1_UDRE_vect_num 24 #define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */ #define USART1_TX_vect_num 25 #define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */ #define ANALOG_COMP_vect_num 26 #define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */ #define EE_READY_vect_num 27 #define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ #define SPM_READY_vect_num 28 #define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */ #define TIMER1_COMPB_vect_num 16 #define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */ #define TIMER1_COMPC_vect_num 17 #define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */ #define TIMER1_OVF_vect_num 18 #define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (29 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (512) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x1FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */ #define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x89 /* Device Pin Definitions */ #endif /* _AVR_ATmega8U2_H_ */ avr-libc-1.8.0.orig/include/avr/ioat94k.h0000644000000000000000000003361311732702554014730 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ioat94k.h 602 2004-11-01 22:23:56Z arcanum $ */ /* avr/ioat94k.h - definitions for AT94K series FPSLIC(tm) */ #ifndef _AVR_IOAT94K_H_ #define _AVR_IOAT94K_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "ioat94k.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* UART1 Baud Rate Register */ #define UBRR1 _SFR_IO8(0x00) /* UART1 Control and Status Registers */ #define UCSR1B _SFR_IO8(0x01) #define UCSR1A _SFR_IO8(0x02) /* UART1 I/O Data Register */ #define UDR1 _SFR_IO8(0x03) /* 0x04 reserved */ /* Input Pins, Port E */ #define PINE _SFR_IO8(0x05) /* Data Direction Register, Port E */ #define DDRE _SFR_IO8(0x06) /* Data Register, Port E */ #define PORTE _SFR_IO8(0x07) /* On Chip Debug Register (reserved) */ #define OCDR _SFR_IO8(0x08) /* UART0 Baud Rate Register */ #define UBRR0 _SFR_IO8(0x09) /* UART0 Control and Status Registers */ #define UCSR0B _SFR_IO8(0x0A) #define UCSR0A _SFR_IO8(0x0B) /* UART0 I/O Data Register */ #define UDR0 _SFR_IO8(0x0C) /* 0x0D..0x0F reserved */ /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* FPGA I/O Select Control Register */ #define FISCR _SFR_IO8(0x13) /* FPGA I/O Select Registers A, B, C, D */ #define FISUA _SFR_IO8(0x14) #define FISUB _SFR_IO8(0x15) #define FISUC _SFR_IO8(0x16) #define FISUD _SFR_IO8(0x17) /* FPGA Cache Logic(R) registers (top secret, under NDA) */ #define FPGAX _SFR_IO8(0x18) #define FPGAY _SFR_IO8(0x19) #define FPGAZ _SFR_IO8(0x1A) #define FPGAD _SFR_IO8(0x1B) /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ /* 2-wire Serial Bit Rate Register */ #define TWBR _SFR_IO8(0x1C) /* 2-wire Serial Status Register */ #define TWSR _SFR_IO8(0x1D) /* 2-wire Serial (Slave) Address Register */ #define TWAR _SFR_IO8(0x1E) /* 2-wire Serial Data Register */ #define TWDR _SFR_IO8(0x1F) /* UART Baud Register High */ #define UBRRH _SFR_IO8(0x20) #define UBRRHI UBRRH /* New name in datasheet (1138F-FPSLI-06/02) */ /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* Timer/Counter2 Output Compare Register */ #define OCR2 _SFR_IO8(0x22) /* Timer/Counter2 (8-bit) */ #define TCNT2 _SFR_IO8(0x23) /* Timer/Counter1 Input Capture Register */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* Asynchronous mode StatuS Register */ #define ASSR _SFR_IO8(0x26) /* Timer/Counter2 Control Register */ #define TCCR2 _SFR_IO8(0x27) /* Timer/Counter1 Output Compare RegisterB */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare RegisterA */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter1 Control Register B */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter1 Control Register A */ #define TCCR1A _SFR_IO8(0x2F) /* Special Function IO Register */ #define SFIOR _SFR_IO8(0x30) /* Timer/Counter0 Output Compare Register */ #define OCR0 _SFR_IO8(0x31) /* Timer/Counter0 (8-bit) */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* 0x34 reserved */ /* MCU Control/Status Register */ #define MCUR _SFR_IO8(0x35) /* 2-wire Serial Control Register */ #define TWCR _SFR_IO8(0x36) /* 0x37 reserved */ /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK Register */ #define TIMSK _SFR_IO8(0x39) /* Software Control Register */ #define SFTCR _SFR_IO8(0x3A) /* External Interrupt Mask/Flag Register */ #define EIMF _SFR_IO8(0x3B) /* 0x3C reserved */ /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ #define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */ #define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */ #define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */ #define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */ #define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */ #define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */ #define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */ #define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */ #define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */ #define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */ #define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */ #define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */ #define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */ #define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */ #define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */ #define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */ #define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */ #define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */ #define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */ #define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */ #define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */ #define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */ #define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */ #define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */ #define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */ #define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */ #define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */ #define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */ #define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */ #define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */ #define SIG_FPGA_INTERRUPT12 _VECTOR(31) /* FPGA_INT12 */ #define SIG_FPGA_INTERRUPT13 _VECTOR(32) /* FPGA_INT13 */ #define SIG_FPGA_INTERRUPT14 _VECTOR(33) /* FPGA_INT14 */ #define SIG_FPGA_INTERRUPT15 _VECTOR(34) /* FPGA_INT15 */ #define SIG_2WIRE_SERIAL _VECTOR(35) /* TWS_INT */ #define _VECTORS_SIZE 144 /* Bit numbers (SFRs alphabetically sorted) */ /* ASSR */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* DDRE */ #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 /* EIMF */ #define INTF3 7 #define INTF2 6 #define INTF1 5 #define INTF0 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 /* FISCR */ #define FIADR 7 #define XFIS1 1 #define XFIS0 0 /* FISUA */ #define FIF3 7 #define FIF2 6 #define FIF1 5 #define FIF0 4 #define FINT3 3 #define FINT2 2 #define FINT1 1 #define FINT0 0 /* FISUB */ #define FIF7 7 #define FIF6 6 #define FIF5 5 #define FIF4 4 #define FINT7 3 #define FINT6 2 #define FINT5 1 #define FINT4 0 /* FISUC */ #define FIF11 7 #define FIF10 6 #define FIF9 5 #define FIF8 4 #define FINT11 3 #define FINT10 2 #define FINT9 1 #define FINT8 0 /* FISUD */ #define FIF15 7 #define FIF14 6 #define FIF13 5 #define FIF12 4 #define FINT15 3 #define FINT14 2 #define FINT13 1 #define FINT12 0 /* MCUR */ #define JTRF 7 #define JTD 6 #define SE 5 #define SM1 4 #define SM0 3 #define PORF 2 #define WDRF 1 #define EXTRF 0 /* OCDR (reserved) */ #define IDRD 7 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* PINE */ #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* PORTE */ /* PE7 = IC1 / INT3 (alternate) PE6 = OC1A / INT2 (alternate) PE5 = OC1B / INT1 (alternate) PE4 = ET11 / INT0 (alternate) PE3 = OC2 / RX1 (alternate) PE2 = / TX1 (alternate) PE1 = OC0 / RX0 (alternate) PE0 = ET0 / TX0 (alternate) */ #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 /* SFIOR */ #define PSR2 1 #define PSR10 0 /* SFTCR */ #define FMXOR 3 #define WDTS 2 #define DBG 1 #define SRST 0 /* TCCR0 */ #define FOC0 7 #define PWM0 6 #define COM01 5 #define COM00 4 #define CTC0 3 #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define PWM11 1 #define PWM10 0 /* TCCR1B */ #define ICNC1 7 #define ICES1 6 #define ICPE 5 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* TCCR2 */ #define FOC2 7 #define PWM2 6 #define COM21 5 #define COM20 4 #define CTC2 3 #define CS22 2 #define CS21 1 #define CS20 0 /* TIFR */ #define TOV1 7 #define OCF1A 6 #define OCF1B 5 #define TOV2 4 #define ICF1 3 #define OCF2 2 #define TOV0 1 #define OCF0 0 /* TIMSK */ #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 #define TOIE2 4 #define TICIE1 3 #define OCIE2 2 #define TOIE0 1 #define OCIE0 0 /* TWAR */ /* #define TWA 1 */ /* TWA is bits 7:1 */ #define TWGCE 0 /* TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 /* TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 /* UBRRHI Bits 11..8 of UART1 are bits 7..4 of UBRRHI. Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */ /* #define UBRRHI1 4 */ /* #define UBRRHI0 0 */ /* UCSR0A */ #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define OR0 3 #define U2X0 1 #define MPCM0 0 /* UCSR0B */ #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define CHR90 2 #define RXB80 1 #define TXB80 0 /* UCSR1A */ #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define OR1 3 #define U2X1 1 #define MPCM1 0 /* UCSR1B */ #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define CHR91 2 #define RXB81 1 #define TXB81 0 /* WDTCR */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Last memory addresses - depending on configuration, it is possible to have 20K-32K of program memory and 4K-16K of data memory (all in the same 36K total of SRAM, loaded from external EEPROM). */ #ifndef RAMEND #define RAMEND 0x0FFF #endif #ifndef XRAMEND #define XRAMEND RAMEND #endif #define E2END 0 #ifndef FLASHEND #define FLASHEND 0x7FFF #endif #endif /* _AVR_IOAT94K_H_ */ avr-libc-1.8.0.orig/include/avr/iom3290.h0000644000000000000000000006043611732702554014551 0ustar /* Copyright (c) 2004 Eric B. Weddington Copyright (c) 2005, 2006, 2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/iom3290.h - definitions for ATmega3290 and ATmega3290P. */ #ifndef _AVR_IOM3290_H_ #define _AVR_IOM3290_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom3290.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define PCIF2 6 #define PCIF3 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define PCIE2 6 #define PCIE3 7 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #if defined(__AVR_ATmega3290P__) #define BODSE 5 #define BODS 6 #endif #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRLCD 4 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x72] */ #define PCMSK3 _SFR_MEM8(0x73) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define PCINT27 3 #define PCINT28 4 #define PCINT29 5 #define PCINT30 6 /* Reserved [0x74..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0XC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7..0xD7] */ #define PINH _SFR_MEM8(0xD8) #define PINH7 7 #define PINH6 6 #define PINH5 5 #define PINH4 4 #define PINH3 3 #define PINH2 2 #define PINH1 1 #define PINH0 0 #define DDRH _SFR_MEM8(0xD9) #define DDH7 7 #define DDH6 6 #define DDH5 5 #define DDH4 4 #define DDH3 3 #define DDH2 2 #define DDH1 1 #define DDH0 0 #define PORTH _SFR_MEM8(0xDA) #define PH7 7 #define PH6 6 #define PH5 5 #define PH4 4 #define PH3 3 #define PH2 2 #define PH1 1 #define PH0 0 #define PINJ _SFR_MEM8(0xDB) #define PINJ6 6 #define PINJ5 5 #define PINJ4 4 #define PINJ3 3 #define PINJ2 2 #define PINJ1 1 #define PINJ0 0 #define DDRJ _SFR_MEM8(0xDC) #define DDJ6 6 #define DDJ5 5 #define DDJ4 4 #define DDJ3 3 #define DDJ2 2 #define DDJ1 1 #define DDJ0 0 #define PORTJ _SFR_MEM8(0xDD) #define PJ6 6 #define PJ5 5 #define PJ4 4 #define PJ3 3 #define PJ2 2 #define PJ1 1 #define PJ0 0 /* Reserved [0xDE..0xE3] */ #define LCDCRA _SFR_MEM8(0XE4) #define LCDBL 0 #if defined(__AVR_ATmega3290P__) #define LCDCCD 1 #define LCDBD 2 #endif #define LCDIE 3 #define LCDIF 4 #define LCDAB 6 #define LCDEN 7 #define LCDCRB _SFR_MEM8(0XE5) #define LCDPM0 0 #define LCDPM1 1 #define LCDPM2 2 #define LCDPM3 3 #define LCDMUX0 4 #define LCDMUX1 5 #define LCD2B 6 #define LCDCS 7 #define LCDFRR _SFR_MEM8(0XE6) #define LCDCD0 0 #define LCDCD1 1 #define LCDCD2 2 #define LCDPS0 4 #define LCDPS1 5 #define LCDPS2 6 #define LCDCCR _SFR_MEM8(0XE7) #define LCDCC0 0 #define LCDCC1 1 #define LCDCC2 2 #define LCDCC3 3 #if defined(__AVR_ATmega3290P__) #define LCDMDT 4 #endif #define LCDDC0 5 #define LCDDC1 6 #define LCDDC2 7 /* Reserved [0xE8..0xEB] */ #define LCDDR00 _SFR_MEM8(0XEC) #define SEG000 0 #define SEG001 1 #define SEG002 2 #define SEG003 3 #define SEG004 4 #define SEG005 5 #define SEG006 6 #define SEG007 7 #define LCDDR01 _SFR_MEM8(0XED) #define SEG008 0 #define SEG009 1 #define SEG010 2 #define SEG011 3 #define SEG012 4 #define SEG013 5 #define SEG014 6 #define SEG015 7 #define LCDDR02 _SFR_MEM8(0XEE) #define SEG016 0 #define SEG017 1 #define SEG018 2 #define SEG019 3 #define SEG020 4 #define SEG021 5 #define SEG022 6 #define SEG023 7 #define LCDDR03 _SFR_MEM8(0XEF) #define SEG024 0 #define SEG025 1 #define SEG026 2 #define SEG027 3 #define SEG028 4 #define SEG029 5 #define SEG030 6 #define SEG031 7 #define LCDDR04 _SFR_MEM8(0XF0) #define SEG032 0 #define SEG033 1 #define SEG034 2 #define SEG035 3 #define SEG036 4 #define SEG037 5 #define SEG038 6 #define SEG039 7 #define LCDDR05 _SFR_MEM8(0XF1) #define SEG100 0 #define SEG101 1 #define SEG102 2 #define SEG103 3 #define SEG104 4 #define SEG105 5 #define SEG106 6 #define SEG107 7 #define LCDDR06 _SFR_MEM8(0XF2) #define SEG108 0 #define SEG109 1 #define SEG110 2 #define SEG111 3 #define SEG112 4 #define SEG113 5 #define SEG114 6 #define SEG115 7 #define LCDDR07 _SFR_MEM8(0XF3) #define SEG116 0 #define SEG117 1 #define SEG118 2 #define SEG119 3 #define SEG120 4 #define SEG121 5 #define SEG122 6 #define SEG123 7 #define LCDDR08 _SFR_MEM8(0XF4) #define SEG124 0 #define SEG125 1 #define SEG126 2 #define SEG127 3 #define SEG128 4 #define SEG129 5 #define SEG130 6 #define SEG131 7 #define LCDDR09 _SFR_MEM8(0XF5) #define SEG132 0 #define SEG133 1 #define SEG134 2 #define SEG135 3 #define SEG136 4 #define SEG137 5 #define SEG138 6 #define SEG139 7 #define LCDDR10 _SFR_MEM8(0XF6) #define SEG200 0 #define SEG201 1 #define SEG202 2 #define SEG203 3 #define SEG204 4 #define SEG205 5 #define SEG206 6 #define SEG207 7 #define LCDDR11 _SFR_MEM8(0XF7) #define SEG208 0 #define SEG209 1 #define SEG210 2 #define SEG211 3 #define SEG212 4 #define SEG213 5 #define SEG214 6 #define SEG215 7 #define LCDDR12 _SFR_MEM8(0XF8) #define SEG216 0 #define SEG217 1 #define SEG218 2 #define SEG219 3 #define SEG220 4 #define SEG221 5 #define SEG222 6 #define SEG223 7 #define LCDDR13 _SFR_MEM8(0XF9) #define SEG224 0 #define SEG225 1 #define SEG226 2 #define SEG227 3 #define SEG228 4 #define SEG229 5 #define SEG230 6 #define SEG231 7 #define LCDDR14 _SFR_MEM8(0XFA) #define SEG232 0 #define SEG233 1 #define SEG234 2 #define SEG235 3 #define SEG236 4 #define SEG237 5 #define SEG238 6 #define SEG239 7 #define LCDDR15 _SFR_MEM8(0XFB) #define SEG300 0 #define SEG301 1 #define SEG302 2 #define SEG303 3 #define SEG304 4 #define SEG305 5 #define SEG306 6 #define SEG307 7 #define LCDDR16 _SFR_MEM8(0XFC) #define SEG308 0 #define SEG309 1 #define SEG310 2 #define SEG311 3 #define SEG312 4 #define SEG313 5 #define SEG314 6 #define SEG315 7 #define LCDDR17 _SFR_MEM8(0XFD) #define SEG316 0 #define SEG217 1 #define SEG318 2 #define SEG319 3 #define SEG320 4 #define SEG321 5 #define SEG322 6 #define SEG323 7 #define LCDDR18 _SFR_MEM8(0XFE) #define SEG324 0 #define SEG325 1 #define SEG326 2 #define SEG327 3 #define SEG328 4 #define SEG329 5 #define SEG330 6 #define SEG331 7 #define LCDDR19 _SFR_MEM8(0XFF) #define SEG332 0 #define SEG333 1 #define SEG334 2 #define SEG335 3 #define SEG336 4 #define SEG337 5 #define SEG338 6 #define SEG339 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART, Rx Complete */ #define USART_RX_vect_num 13 #define USART_RX_vect _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) /* USART Data register Empty */ #define USART_UDRE_vect_num 14 #define USART_UDRE_vect _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* LCD Start of Frame */ #define LCD_vect_num 22 #define LCD_vect _VECTOR(22) #define SIG_LCD _VECTOR(22) /* Pin Change Interrupt Request 2 */ #define PCINT2_vect_num 23 #define PCINT2_vect _VECTOR(23) #define SIG_PIN_CHANGE2 _VECTOR(23) /* Pin Change Interrupt Request 3 */ #define PCINT3_vect_num 24 #define PCINT3_vect _VECTOR(24) #define SIG_PIN_CHANGE3 _VECTOR(24) #define _VECTORS_SIZE 100 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x8FF #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 4 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x04 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #pragma GCC poison SIG_LCD #pragma GCC poison SIG_PIN_CHANGE2 #pragma GCC poison SIG_PIN_CHANGE3 #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM3290_H_ */ avr-libc-1.8.0.orig/include/avr/iom8hva.h0000644000000000000000000000464711732702554015024 0ustar /* Copyright (c) 2007, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom8hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* iom8hva.h - definitions for ATmega8HVA. */ #ifndef _AVR_IOM8HVA_H_ #define _AVR_IOM8HVA_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x2FF #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_SUT0 (unsigned char)~_BV(0) #define FUSE_SUT1 (unsigned char)~_BV(1) #define FUSE_SUT2 (unsigned char)~_BV(2) #define FUSE_SELFPRGEN (unsigned char)~_BV(3) #define FUSE_DWEN (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_EESAVE (unsigned char)~_BV(6) #define FUSE_WDTON (unsigned char)~_BV(7) #define FUSE_DEFAULT (FUSE_SPIEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #endif /* _AVR_IOM8HVA_H_ */ avr-libc-1.8.0.orig/include/avr/io.h0000644000000000000000000003504211732702554014051 0ustar /* Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch Copyright (c) 2007 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io.h 2211 2011-02-14 14:04:25Z aboyapati $ */ /** \file */ /** \defgroup avr_io : AVR device-specific IO definitions \code #include \endcode This header file includes the apropriate IO definitions for the device that has been specified by the -mmcu= compiler command-line switch. This is done by diverting to the appropriate file <avr/ioXXXX.h> which should never be included directly. Some register names common to all AVR devices are defined directly within <avr/common.h>, which is included in <avr/io.h>, but most of the details come from the respective include file. Note that this file always includes the following files: \code #include #include #include #include \endcode See \ref avr_sfr for more details about that header file. Included are definitions of the IO register set and their respective bit values as specified in the Atmel documentation. Note that inconsistencies in naming conventions, so even identical functions sometimes get different names on different devices. Also included are the specific names useable for interrupt function definitions as documented \ref avr_signames "here". Finally, the following macros are defined: - \b RAMEND
The last on-chip RAM address.
- \b XRAMEND
The last possible RAM location that is addressable. This is equal to RAMEND for devices that do not allow for external RAM. For devices that allow external RAM, this will be larger than RAMEND.
- \b E2END
The last EEPROM address.
- \b FLASHEND
The last byte address in the Flash program space.
- \b SPM_PAGESIZE
For devices with bootloader support, the flash pagesize (in bytes) to be used for the \c SPM instruction. - \b E2PAGESIZE
The size of the EEPROM page. */ #ifndef _AVR_IO_H_ #define _AVR_IO_H_ #include #if defined (__AVR_AT94K__) # include #elif defined (__AVR_AT43USB320__) # include #elif defined (__AVR_AT43USB355__) # include #elif defined (__AVR_AT76C711__) # include #elif defined (__AVR_AT86RF401__) # include #elif defined (__AVR_AT90PWM1__) # include #elif defined (__AVR_AT90PWM2__) # include #elif defined (__AVR_AT90PWM2B__) # include #elif defined (__AVR_AT90PWM3__) # include #elif defined (__AVR_AT90PWM3B__) # include #elif defined (__AVR_AT90PWM216__) # include #elif defined (__AVR_AT90PWM316__) # include #elif defined (__AVR_AT90PWM81__) # include #elif defined (__AVR_ATmega8U2__) # include #elif defined (__AVR_ATmega16M1__) # include #elif defined (__AVR_ATmega16U2__) # include #elif defined (__AVR_ATmega16U4__) # include #elif defined (__AVR_ATmega32C1__) # include #elif defined (__AVR_ATmega32M1__) # include #elif defined (__AVR_ATmega32U2__) # include #elif defined (__AVR_ATmega32U4__) # include #elif defined (__AVR_ATmega32U6__) # include #elif defined (__AVR_ATmega64C1__) # include #elif defined (__AVR_ATmega64M1__) # include #elif defined (__AVR_ATmega128__) # include #elif defined (__AVR_ATmega1280__) # include #elif defined (__AVR_ATmega1281__) # include #elif defined (__AVR_ATmega1284P__) # include #elif defined (__AVR_ATmega128RFA1__) # include #elif defined (__AVR_ATmega2560__) # include #elif defined (__AVR_ATmega2561__) # include #elif defined (__AVR_AT90CAN32__) # include #elif defined (__AVR_AT90CAN64__) # include #elif defined (__AVR_AT90CAN128__) # include #elif defined (__AVR_AT90USB82__) # include #elif defined (__AVR_AT90USB162__) # include #elif defined (__AVR_AT90USB646__) # include #elif defined (__AVR_AT90USB647__) # include #elif defined (__AVR_AT90USB1286__) # include #elif defined (__AVR_AT90USB1287__) # include #elif defined (__AVR_ATmega64__) # include #elif defined (__AVR_ATmega640__) # include #elif defined (__AVR_ATmega644__) || defined (__AVR_ATmega644A__) # include #elif defined (__AVR_ATmega644P__) # include #elif defined (__AVR_ATmega644PA__) # include #elif defined (__AVR_ATmega645__) || defined (__AVR_ATmega645A__) || defined (__AVR_ATmega645P__) # include #elif defined (__AVR_ATmega6450__) || defined (__AVR_ATmega6450A__) || defined (__AVR_ATmega6450P__) # include #elif defined (__AVR_ATmega649__) || defined (__AVR_ATmega649A__) # include #elif defined (__AVR_ATmega6490__) || defined (__AVR_ATmega6490A__) || defined (__AVR_ATmega6490P__) # include #elif defined (__AVR_ATmega649P__) # include #elif defined (__AVR_ATmega64HVE__) # include #elif defined (__AVR_ATmega103__) # include #elif defined (__AVR_ATmega32__) # include #elif defined (__AVR_ATmega323__) # include #elif defined (__AVR_ATmega324P__) || defined (__AVR_ATmega324A__) # include #elif defined (__AVR_ATmega324PA__) # include #elif defined (__AVR_ATmega325__) || defined (__AVR_ATmega325A__) # include #elif defined (__AVR_ATmega325P__) # include #elif defined (__AVR_ATmega3250__) || defined (__AVR_ATmega3250A__) # include #elif defined (__AVR_ATmega3250P__) # include #elif defined (__AVR_ATmega328P__) || defined (__AVR_ATmega328__) # include #elif defined (__AVR_ATmega329__) || defined (__AVR_ATmega329A__) # include #elif defined (__AVR_ATmega329P__) || defined (__AVR_ATmega329PA__) # include #elif defined (__AVR_ATmega3290__) || defined (__AVR_ATmega3290A__) # include #elif defined (__AVR_ATmega3290P__) # include #elif defined (__AVR_ATmega32HVB__) # include #elif defined (__AVR_ATmega32HVBREVB__) # include #elif defined (__AVR_ATmega406__) # include #elif defined (__AVR_ATmega16__) # include #elif defined (__AVR_ATmega16A__) # include #elif defined (__AVR_ATmega161__) # include #elif defined (__AVR_ATmega162__) # include #elif defined (__AVR_ATmega163__) # include #elif defined (__AVR_ATmega164P__) || defined (__AVR_ATmega164A__) # include #elif defined (__AVR_ATmega165__) || defined (__AVR_ATmega165A__) # include #elif defined (__AVR_ATmega165P__) # include #elif defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__) # include #elif defined (__AVR_ATmega168P__) # include #elif defined (__AVR_ATmega169__) || defined (__AVR_ATmega169A__) # include #elif defined (__AVR_ATmega169P__) # include #elif defined (__AVR_ATmega169PA__) # include #elif defined (__AVR_ATmega8HVA__) # include #elif defined (__AVR_ATmega16HVA__) # include #elif defined (__AVR_ATmega16HVA2__) # include #elif defined (__AVR_ATmega16HVB__) # include #elif defined (__AVR_ATmega16HVBREVB__) # include #elif defined (__AVR_ATmega8__) # include #elif defined (__AVR_ATmega48__) || defined (__AVR_ATmega48A__) # include #elif defined (__AVR_ATmega48P__) # include #elif defined (__AVR_ATmega88__) || defined (__AVR_ATmega88A__) # include #elif defined (__AVR_ATmega88P__) # include #elif defined (__AVR_ATmega88PA__) # include #elif defined (__AVR_ATmega8515__) # include #elif defined (__AVR_ATmega8535__) # include #elif defined (__AVR_AT90S8535__) # include #elif defined (__AVR_AT90C8534__) # include #elif defined (__AVR_AT90S8515__) # include #elif defined (__AVR_AT90S4434__) # include #elif defined (__AVR_AT90S4433__) # include #elif defined (__AVR_AT90S4414__) # include #elif defined (__AVR_ATtiny22__) # include #elif defined (__AVR_ATtiny26__) # include #elif defined (__AVR_AT90S2343__) # include #elif defined (__AVR_AT90S2333__) # include #elif defined (__AVR_AT90S2323__) # include #elif defined (__AVR_AT90S2313__) # include #elif defined (__AVR_ATtiny4__) # include #elif defined (__AVR_ATtiny5__) # include #elif defined (__AVR_ATtiny9__) # include #elif defined (__AVR_ATtiny10__) # include #elif defined (__AVR_ATtiny20__) # include #elif defined (__AVR_ATtiny40__) # include #elif defined (__AVR_ATtiny2313__) # include #elif defined (__AVR_ATtiny2313A__) # include #elif defined (__AVR_ATtiny13__) # include #elif defined (__AVR_ATtiny13A__) # include #elif defined (__AVR_ATtiny25__) # include #elif defined (__AVR_ATtiny4313__) # include #elif defined (__AVR_ATtiny45__) # include #elif defined (__AVR_ATtiny85__) # include #elif defined (__AVR_ATtiny24__) # include #elif defined (__AVR_ATtiny24A__) # include #elif defined (__AVR_ATtiny44__) # include #elif defined (__AVR_ATtiny44A__) # include #elif defined (__AVR_ATtiny84__) # include #elif defined (__AVR_ATtiny84A__) # include #elif defined (__AVR_ATtiny261__) # include #elif defined (__AVR_ATtiny261A__) # include #elif defined (__AVR_ATtiny461__) # include #elif defined (__AVR_ATtiny461A__) # include #elif defined (__AVR_ATtiny861__) # include #elif defined (__AVR_ATtiny861A__) # include #elif defined (__AVR_ATtiny43U__) # include #elif defined (__AVR_ATtiny48__) # include #elif defined (__AVR_ATtiny88__) # include #elif defined (__AVR_ATtiny87__) # include #elif defined (__AVR_ATtiny167__) # include #elif defined (__AVR_AT90SCR100__) # include #elif defined (__AVR_ATxmega16A4__) # include #elif defined (__AVR_ATxmega16D4__) # include #elif defined (__AVR_ATxmega32A4__) # include #elif defined (__AVR_ATxmega32D4__) # include #elif defined (__AVR_ATxmega64A1__) # include #elif defined (__AVR_ATxmega64A1U__) # include #elif defined (__AVR_ATxmega64A3__) # include #elif defined (__AVR_ATxmega64D3__) # include #elif defined (__AVR_ATxmega128A1__) # include #elif defined (__AVR_ATxmega128A1U__) # include #elif defined (__AVR_ATxmega128A3__) # include #elif defined (__AVR_ATxmega128D3__) # include #elif defined (__AVR_ATxmega192A3__) # include #elif defined (__AVR_ATxmega192D3__) # include #elif defined (__AVR_ATxmega256A3__) # include #elif defined (__AVR_ATxmega256A3B__) # include #elif defined (__AVR_ATxmega256D3__) # include #elif defined (__AVR_ATA6289__) # include /* avr1: the following only supported for assembler programs */ #elif defined (__AVR_ATtiny28__) # include #elif defined (__AVR_AT90S1200__) # include #elif defined (__AVR_ATtiny15__) # include #elif defined (__AVR_ATtiny12__) # include #elif defined (__AVR_ATtiny11__) # include #elif defined (__AVR_M3000__) # include #else # if !defined(__COMPILING_AVR_LIBC__) # warning "device type not defined" # endif #endif #include #include #include /* Include fuse.h after individual IO header files. */ #include /* Include lock.h after individual IO header files. */ #include #endif /* _AVR_IO_H_ */ avr-libc-1.8.0.orig/include/avr/iom169.h0000644000000000000000000005501511732702554014470 0ustar /* Copyright (c) 2002, 2003, 2004, 2005 Juergen Schilling Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom169.h 2231 2011-03-07 05:06:55Z arcanum $ */ /* iom169.h - definitions for ATmega169 */ /* This should be up to date with data sheet version 2514J-AVR-12/03. */ #ifndef _AVR_IOM169_H_ #define _AVR_IOM169_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom169.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Port A */ #define PINA _SFR_IO8(0x00) #define DDRA _SFR_IO8(0x01) #define PORTA _SFR_IO8(0x02) /* Port B */ #define PINB _SFR_IO8(0x03) #define DDRB _SFR_IO8(0x04) #define PORTB _SFR_IO8(0x05) /* Port C */ #define PINC _SFR_IO8(0x06) #define DDRC _SFR_IO8(0x07) #define PORTC _SFR_IO8(0x08) /* Port D */ #define PIND _SFR_IO8(0x09) #define DDRD _SFR_IO8(0x0A) #define PORTD _SFR_IO8(0x0B) /* Port E */ #define PINE _SFR_IO8(0x0C) #define DDRE _SFR_IO8(0x0D) #define PORTE _SFR_IO8(0x0E) /* Port F */ #define PINF _SFR_IO8(0x0F) #define DDRF _SFR_IO8(0x10) #define PORTF _SFR_IO8(0x11) /* Port G */ #define PING _SFR_IO8(0x12) #define DDRG _SFR_IO8(0x13) #define PORTG _SFR_IO8(0x14) /* Timer/Counter 0 interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) /* Timer/Counter 1 interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) /* Timer/Counter 2 interrupt Flag Register */ #define TIFR2 _SFR_IO8(0x17) /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) /* External Interrupt Mask Register */ #define EIMSK _SFR_IO8(0x1D) /* General Purpose I/O Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) /* Timer/Counter Control Register A */ #define TCCR0A _SFR_IO8(0x24) /* Timer/Counter Register */ #define TCNT0 _SFR_IO8(0x26) /* Output Compare Register A */ #define OCR0A _SFR_IO8(0x27) /* General Purpose I/O Register 1 */ #define GPIOR1 _SFR_IO8(0x2A) /* General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x2B) /* SPI Control Register */ #define SPCR _SFR_IO8(0x2C) /* SPI Status Register */ #define SPSR _SFR_IO8(0x2D) /* SPI Data Register */ #define SPDR _SFR_IO8(0x2E) /* Analog Comperator Control and Status Register */ #define ACSR _SFR_IO8(0x30) /* On-chip Debug Register */ #define OCDR _SFR_IO8(0x31) /* Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU Control Rgeister */ #define MCUCR _SFR_IO8(0x35) /* Store Program Memory Control and Status Register */ #define SPMCSR _SFR_IO8(0x37) /* Watchdog Timer Control Register */ #define WDTCR _SFR_MEM8(0x60) /* Clock Prescale Register */ #define CLKPR _SFR_MEM8(0x61) #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRLCD 4 /* Oscillator Calibration Register */ #define OSCCAL _SFR_MEM8(0x66) /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x69) /* Pin Change Mask Register */ #define PCMSK _SFR_MEM16(0x6B) #define PCMSK0 _SFR_MEM8(0x6B) #define PCMSK1 _SFR_MEM8(0x6C) /* Timer/Counter 0 Interrupt Mask Register */ #define TIMSK0 _SFR_MEM8(0x6E) /* Timer/Counter 1 Interrupt Mask Register */ #define TIMSK1 _SFR_MEM8(0x6F) /* Timer/Counter 2 Interrupt Mask Register */ #define TIMSK2 _SFR_MEM8(0x70) /* ADC Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) /* ADC Control and Status Register A */ #define ADCSRA _SFR_MEM8(0x7A) /* ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x7B) /* ADC Multiplex Selection Register */ #define ADMUX _SFR_MEM8(0x7C) /* NOTE: DIDR0 and DIDR1 are swapped in the register summary of the data sheet (2514D-AVR-01/03), but seem to be correct in the discussions of the registers. */ /* Digital Input Disable Register 0 */ #define DIDR0 _SFR_MEM8(0x7E) /* Digital Input Disable Register 1 */ #define DIDR1 _SFR_MEM8(0x7F) /* Timer/Counter1 Control Register A */ #define TCCR1A _SFR_MEM8(0x80) /* Timer/Counter1 Control Register B */ #define TCCR1B _SFR_MEM8(0x81) /* Timer/Counter1 Control Register C */ #define TCCR1C _SFR_MEM8(0x82) /* Timer/Counter1 Register */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Timer/Counter1 Input Capture Register */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Timer/Counter1 Output Compare Registare B */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Timer/Counter2 Control Register A */ #define TCCR2A _SFR_MEM8(0xB0) /* Timer/Counter2 Register */ #define TCNT2 _SFR_MEM8(0xB2) /* Timer/Counter2 Output Compare Register */ #define OCR2A _SFR_MEM8(0xB3) /* Asynchronous Status Register */ #define ASSR _SFR_MEM8(0xB6) /* USI Control Register */ #define USICR _SFR_MEM8(0xB8) /* USI Status Register */ #define USISR _SFR_MEM8(0xB9) /* USI Data Register */ #define USIDR _SFR_MEM8(0xBA) /* USART0 Control and Status Register A */ #define UCSRA _SFR_MEM8(0xC0) /* USART0 Control and Status Register B */ #define UCSRB _SFR_MEM8(0xC1) /* USART0 Control and Status Register C */ #define UCSRC _SFR_MEM8(0xC2) /* USART0 Baud Rate Register */ #define UBRR _SFR_MEM16(0xC4) #define UBRRL _SFR_MEM8(0xC4) #define UBRRH _SFR_MEM8(0xC5) /* USART0 I/O Data Register */ #define UDR _SFR_MEM8(0xC6) /* LCD Control and Status Register A */ #define LCDCRA _SFR_MEM8(0xE4) /* LCD Control and Status Register B */ #define LCDCRB _SFR_MEM8(0xE5) /* LCD Frame Rate Register */ #define LCDFRR _SFR_MEM8(0xE6) /* LCD Contrast Control Register */ #define LCDCCR _SFR_MEM8(0xE7) /* LCD Memory mapping */ #define LCDDR0 _SFR_MEM8(0xEC) #define LCDDR1 _SFR_MEM8(0xED) #define LCDDR2 _SFR_MEM8(0xEE) #define LCDDR3 _SFR_MEM8(0xEF) #define LCDDR5 _SFR_MEM8(0xF1) #define LCDDR6 _SFR_MEM8(0xF2) #define LCDDR7 _SFR_MEM8(0xF3) #define LCDDR8 _SFR_MEM8(0xF4) #define LCDDR10 _SFR_MEM8(0xF6) #define LCDDR11 _SFR_MEM8(0xF7) #define LCDDR12 _SFR_MEM8(0xF8) #define LCDDR13 _SFR_MEM8(0xF9) #define LCDDR15 _SFR_MEM8(0xFB) #define LCDDR16 _SFR_MEM8(0xFC) #define LCDDR17 _SFR_MEM8(0xFD) #define LCDDR18 _SFR_MEM8(0xFE) /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART0, Rx Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) #define SIG_USART_RECV _VECTOR(13) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) #define SIG_USART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define SIG_USART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* LCD Start of Frame */ #define LCD_vect_num 22 #define LCD_vect _VECTOR(22) #define SIG_LCD _VECTOR(22) #define _VECTORS_SIZE 92 /* Bit numbers */ /* PA7 = SEG3 PA6 = SEG2 PA5 = SEG1 PA4 = SEG0 PA3 = COM3 PA2 = COM2 PA1 = COM1 PA0 = COM0 */ /* PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* PB7 = OC2A / PCINT15 PB6 = OC1B / PCINT14 PB5 = OC1A / PCINT13 PB4 = OC0A / PCINT12 PB3 = MISO / PCINT11 PB2 = MOSI / PCINT10 PB1 = SCK / PCINT9 PB0 = SS# / PCINT8 */ /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PC7 = SEG5 PC6 = SEG6 PC5 = SEG7 PC4 = SEG8 PC3 = SEG9 PC2 = SEG10 PC1 = SEG11 PC0 = SEG12 */ /* PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* PD7 = SEG15 PD6 = SEG16 PD5 = SEG17 PD4 = SEG18 PD3 = SEG19 PD2 = SEG20 PD1 = INT0 / SEG21 PD0 = ICP / SEG22 */ /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* PE7 = CLK0 / PCINT7 PE6 = DO / PCINT6 PE5 = DI / SDA / PCINT5 PE4 = USCK / SCL / PCINT4 PE3 = AIN1 / PCINT3 PE2 = XCK / AIN0 / PCINT2 PE1 = TXD / PCINT1 PE0 = RXD / PCINT0 */ /* PORTE */ #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 /* DDRE */ #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 /* PINE */ #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 /* PF7 = ADC7 / TDI PF6 = ADC6 / TDO PF5 = ADC5 / TMS PF4 = ADC4 / TCK PF3 = ADC3 PF2 = ADC2 PF1 = ADC1 PF0 = ADC0 */ /* PORTF */ #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 /* DDRF */ #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 /* PINF */ #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 /* PG5 = RESET# PG4 = T0 / SEG23 PG3 = T1 / SEG24 PG2 = SEG4 PG1 = SEG13 PG0 = SEG14 */ /* PORTG */ #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 /* DDRG */ #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 /* PING */ #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 /* TIFR0 */ #define OCF0A 1 #define TOV0 0 /* TIFR1 */ #define ICF1 5 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 /* TIFR2 */ #define OCF2A 1 #define TOV2 0 /* EIFR */ #define PCIF1 7 #define PCIF0 6 #define INTF0 0 /* EIMSK */ #define PCIE1 7 #define PCIE0 6 #define INT0 0 /* EECR */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* GTCCR */ #define TSM 7 #define PSR2 1 #define PSR10 0 /* TCCR0A */ #define FOC0A 7 #define WGM00 6 #define COM0A1 5 #define COM0A0 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* OCDR */ #define IDRD 7 #define OCD 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 /* SMCR */ #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 /* MCUSR */ #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* MCUCR */ #define JTD 7 #define PUD 4 #define IVSEL 1 #define IVCE 0 /* SPMCSR */ #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* WDTCR */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* CLKPR */ #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 /* EICRA */ #define ISC01 1 #define ISC00 0 /* PCMSK0 */ #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 /* PCMSK1 */ #define PCINT15 7 #define PCINT14 6 #define PCINT13 5 #define PCINT12 4 #define PCINT11 3 #define PCINT10 2 #define PCINT9 1 #define PCINT8 0 /* TIMSK0 */ #define OCIE0A 1 #define TOIE0 0 /* TIMSK1 */ #define ICIE1 5 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 /* TIMSK2 */ #define OCIE2A 1 #define TOIE2 0 /* ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADCSRB */ #define ACME 6 #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* DIDR1 */ #define AIN1D 1 #define AIN0D 0 /* DIDR0 */ #define ADC7D 7 #define ADC6D 6 #define ADC5D 5 #define ADC4D 4 #define ADC3D 3 #define ADC2D 2 #define ADC1D 1 #define ADC0D 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define WGM11 1 #define WGM10 0 /* TCCR1B */ #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* TCCR1C */ #define FOC1A 7 #define FOC1B 6 /* TCCR2A */ #define FOC2A 7 #define WGM20 6 #define COM2A1 5 #define COM2A0 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* ASSR */ #define EXCLK 4 #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* USICR */ #define USISIE 7 #define USIOIE 6 #define USIWM1 5 #define USIWM0 4 #define USICS1 3 #define USICS0 2 #define USICLK 1 #define USITC 0 /* USISR */ #define USISIF 7 #define USIOIF 6 #define USIPF 5 #define USIDC 4 #define USICNT3 3 #define USICNT2 2 #define USICNT1 1 #define USICNT0 0 /* UCSRA */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define UPE 2 #define U2X 1 #define MPCM 0 /* UCSRB */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 /* UCSRC */ #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* LCDCRA */ #define LCDEN 7 #define LCDAB 6 #define LCDIF 4 #define LCDIE 3 #define LCDBD 2 /* Only in Rev. F */ #define LCDCCD 1 /* Only in Rev. F */ #define LCDBL 0 /* LCDCRB */ #define LCDCS 7 #define LCD2B 6 #define LCDMUX1 5 #define LCDMUX0 4 #define LCDPM2 2 #define LCDPM1 1 #define LCDPM0 0 /* LCDFRR */ #define LCDPS2 6 #define LCDPS1 5 #define LCDPS0 4 #define LCDCD2 2 #define LCDCD1 1 #define LCDCD0 0 /* LCDCCR */ #define LCDDC2 7 #define LCDDC1 6 #define LCDDC0 5 #define LCDMDT 4 /* Only in Rev. F */ #define LCDCC3 3 #define LCDCC2 2 #define LCDCC1 1 #define LCDCC0 0 /* LCDDR0-18 */ #define SEG24 0 #define SEG23 7 #define SEG22 6 #define SEG21 5 #define SEG20 4 #define SEG19 3 #define SEG18 2 #define SEG17 1 #define SEG16 0 #define SEG15 7 #define SEG14 6 #define SEG13 5 #define SEG12 4 #define SEG11 3 #define SEG10 2 #define SEG9 1 #define SEG8 0 #define SEG7 7 #define SEG6 6 #define SEG5 5 #define SEG4 4 #define SEG3 3 #define SEG2 2 #define SEG1 1 #define SEG0 0 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x4FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x05 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_USART_RECV #pragma GCC poison SIG_USART_DATA #pragma GCC poison SIG_USART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #pragma GCC poison SIG_LCD #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM169_H_ */ avr-libc-1.8.0.orig/include/avr/iom32hvb.h0000644000000000000000000005145011732702554015074 0ustar /* Copyright (c) 2011 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom32hvb.h 2211 2011-02-14 14:04:25Z aboyapati $ */ /* avr/iom32hvb.h - definitions for ATmega32HVB */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32hvb.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega32HVB_H_ #define _AVR_ATmega32HVB_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 3 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 3 #define OSICSR _SFR_IO8(0x17) #define OSIEN 0 #define OSIST 1 #define OSISEL0 4 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define ICS0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define TCNT0 _SFR_IO16(0x26) #define TCNT0L _SFR_IO8(0x26) #define TCNT0L0 0 #define TCNT0L1 1 #define TCNT0L2 2 #define TCNT0L3 3 #define TCNT0L4 4 #define TCNT0L5 5 #define TCNT0L6 6 #define TCNT0L7 7 #define TCNT0H _SFR_IO8(0x27) #define TCNT0H0 0 #define TCNT0H1 1 #define TCNT0H2 2 #define TCNT0H3 3 #define TCNT0H4 4 #define TCNT0H5 5 #define TCNT0H6 6 #define TCNT0H7 7 #define OCR0A _SFR_IO8(0x28) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0B _SFR_IO8(0x29) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define DWDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BODRF 2 #define WDRF 3 #define OCDRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define CKOE 5 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define LBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRVADC 0 #define PRTIM0 1 #define PRTIM1 2 #define PRSPI 3 #define PRVRM 5 #define PRTWI 6 #define FOSCCAL _SFR_MEM8(0x66) #define FCAL0 0 #define FCAL1 1 #define FCAL2 2 #define FCAL3 3 #define FCAL4 4 #define FCAL5 5 #define FCAL6 6 #define FCAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT4 0 #define PCINT5 1 #define PCINT6 2 #define PCINT7 3 #define PCINT8 4 #define PCINT9 5 #define PCINT10 6 #define PCINT11 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 3 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 3 #define VADC _SFR_MEM16(0x78) #define VADCL _SFR_MEM8(0x78) #define VADC0 0 #define VADC1 1 #define VADC2 2 #define VADC3 3 #define VADC4 4 #define VADC5 5 #define VADC6 6 #define VADC7 7 #define VADCH _SFR_MEM8(0x79) #define VADC8 0 #define VADC9 1 #define VADC10 2 #define VADC11 3 #define VADCSR _SFR_MEM8(0x7A) #define VADCCIE 0 #define VADCCIF 1 #define VADSC 2 #define VADEN 3 #define VADMUX _SFR_MEM8(0x7C) #define VADMUX0 0 #define VADMUX1 1 #define VADMUX2 2 #define VADMUX3 3 #define DIDR0 _SFR_MEM8(0x7E) #define PA0DID 0 #define PA1DID 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define ICS1 3 #define ICES1 4 #define ICNC1 5 #define ICEN1 6 #define TCW1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define OCR1A _SFR_MEM8(0x88) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define OCR1B _SFR_MEM8(0x89) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define TWBCSR _SFR_MEM8(0xBE) #define TWBCIP 0 #define TWBDT0 1 #define TWBDT1 2 #define TWBCIE 6 #define TWBCIF 7 #define ROCR _SFR_MEM8(0xC8) #define ROCWIE 0 #define ROCWIF 1 #define ROCD 4 #define ROCS 7 #define BGCCR _SFR_MEM8(0xD0) #define BGCC0 0 #define BGCC1 1 #define BGCC2 2 #define BGCC3 3 #define BGCC4 4 #define BGCC5 5 #define BGCRR _SFR_MEM8(0xD1) #define BGCR0 0 #define BGCR1 1 #define BGCR2 2 #define BGCR3 3 #define BGCR4 4 #define BGCR5 5 #define BGCR6 6 #define BGCR7 7 #define BGCSR _SFR_MEM8(0xD2) #define BGSCDIE 0 #define BGSCDIF 1 #define BGSCDE 4 #define BGD 5 #define CHGDCSR _SFR_MEM8(0xD4) #define CHGDIE 0 #define CHGDIF 1 #define CHGDISC0 2 #define CHGDISC1 3 #define BATTPVL 4 #define CADAC0 _SFR_MEM8(0xE0) #define CADAC00 0 #define CADAC01 1 #define CADAC02 2 #define CADAC03 3 #define CADAC04 4 #define CADAC05 5 #define CADAC06 6 #define CADAC07 7 #define CADAC1 _SFR_MEM8(0xE1) #define CADAC08 0 #define CADAC09 1 #define CADAC10 2 #define CADAC11 3 #define CADAC12 4 #define CADAC13 5 #define CADAC14 6 #define CADAC15 7 #define CADAC2 _SFR_MEM8(0xE2) #define CADAC16 0 #define CADAC17 1 #define CADAC18 2 #define CADAC19 3 #define CADAC20 4 #define CADAC21 5 #define CADAC22 6 #define CADAC23 7 #define CADAC3 _SFR_MEM8(0xE3) #define CADAC24 0 #define CADAC25 1 #define CADAC26 2 #define CADAC27 3 #define CADAC28 4 #define CADAC29 5 #define CADAC30 6 #define CADAC31 7 #define CADIC _SFR_MEM16(0xE4) #define CADICL _SFR_MEM8(0xE4) #define CADICL0 0 #define CADICL1 1 #define CADICL2 2 #define CADICL3 3 #define CADICL4 4 #define CADICL5 5 #define CADICL6 6 #define CADICL7 7 #define CADICH _SFR_MEM8(0xE5) #define CADICH0 0 #define CADICH1 1 #define CADICH2 2 #define CADICH3 3 #define CADICH4 4 #define CADICH5 5 #define CADICH6 6 #define CADICH7 7 #define CADCSRA _SFR_MEM8(0xE6) #define CADSE 0 #define CADSI0 1 #define CADSI1 2 #define CADAS0 3 #define CADAS1 4 #define CADUB 5 #define CADPOL 6 #define CADEN 7 #define CADCSRB _SFR_MEM8(0xE7) #define CADICIF 0 #define CADRCIF 1 #define CADACIF 2 #define CADICIE 4 #define CADRCIE 5 #define CADACIE 6 #define CADCSRC _SFR_MEM8(0xE8) #define CADVSE 0 #define CADRCC _SFR_MEM8(0xE9) #define CADRCC0 0 #define CADRCC1 1 #define CADRCC2 2 #define CADRCC3 3 #define CADRCC4 4 #define CADRCC5 5 #define CADRCC6 6 #define CADRCC7 7 #define CADRDC _SFR_MEM8(0xEA) #define CADRDC0 0 #define CADRDC1 1 #define CADRDC2 2 #define CADRDC3 3 #define CADRDC4 4 #define CADRDC5 5 #define CADRDC6 6 #define CADRDC7 7 #define FCSR _SFR_MEM8(0xF0) #define CFE 0 #define DFE 1 #define CPS 2 #define DUVRD 3 #define CBCR _SFR_MEM8(0xF1) #define CBE1 0 #define CBE2 1 #define CBE3 2 #define CBE4 3 #define BPIMSK _SFR_MEM8(0xF2) #define CHCIE 0 #define DHCIE 1 #define COCIE 2 #define DOCIE 3 #define SCIE 4 #define BPIFR _SFR_MEM8(0xF3) #define CHCIF 0 #define DHCIF 1 #define COCIF 2 #define DOCIF 3 #define SCIF 4 #define BPSCD _SFR_MEM8(0xF5) #define SCDL0 0 #define SCDL1 1 #define SCDL2 2 #define SCDL3 3 #define SCDL4 4 #define SCDL5 5 #define SCDL6 6 #define SCDL7 7 #define BPDOCD _SFR_MEM8(0xF6) #define DOCDL0 0 #define DOCDL1 1 #define DOCDL2 2 #define DOCDL3 3 #define DOCDL4 4 #define DOCDL5 5 #define DOCDL6 6 #define DOCDL7 7 #define BPCOCD _SFR_MEM8(0xF7) #define COCDL0 0 #define COCDL1 1 #define COCDL2 2 #define COCDL3 3 #define COCDL4 4 #define COCDL5 5 #define COCDL6 6 #define COCDL7 7 #define BPDHCD _SFR_MEM8(0xF8) #define DHCDL0 0 #define DHCDL1 1 #define DHCDL2 2 #define DHCDL3 3 #define DHCDL4 4 #define DHCDL5 5 #define DHCDL6 6 #define DHCDL7 7 #define BPCHCD _SFR_MEM8(0xF9) #define CHCDL0 0 #define CHCDL1 1 #define CHCDL2 2 #define CHCDL3 3 #define CHCDL4 4 #define CHCDL5 5 #define CHCDL6 6 #define CHCDL7 7 #define BPSCTR _SFR_MEM8(0xFA) #define SCPT0 0 #define SCPT1 1 #define SCPT2 2 #define SCPT3 3 #define SCPT4 4 #define SCPT5 5 #define SCPT6 6 #define BPOCTR _SFR_MEM8(0xFB) #define OCPT0 0 #define OCPT1 1 #define OCPT2 2 #define OCPT3 3 #define OCPT4 4 #define OCPT5 5 #define BPHCTR _SFR_MEM8(0xFC) #define HCPT0 0 #define HCPT1 1 #define HCPT2 2 #define HCPT3 3 #define HCPT4 4 #define HCPT5 5 #define BPCR _SFR_MEM8(0xFD) #define CHCD 0 #define DHCD 1 #define COCD 2 #define DOCD 3 #define SCD 4 #define EPID 5 #define BPPLR _SFR_MEM8(0xFE) #define BPPL 0 #define BPPLE 1 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define BPINT_vect_num 1 #define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ #define VREGMON_vect_num 2 #define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ #define INT0_vect_num 3 #define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ #define INT1_vect_num 4 #define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ #define INT2_vect_num 5 #define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ #define INT3_vect_num 6 #define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ #define PCINT0_vect_num 7 #define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ #define PCINT1_vect_num 8 #define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ #define WDT_vect_num 9 #define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ #define BGSCD_vect_num 10 #define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ #define CHDET_vect_num 11 #define CHDET_vect _VECTOR(11) /* Charger Detect */ #define TIMER1_IC_vect_num 12 #define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ #define TIMER0_IC_vect_num 16 #define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ #define TIMER0_COMPA_vect_num 17 #define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ #define TIMER0_COMPB_vect_num 18 #define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ #define TIMER0_OVF_vect_num 19 #define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ #define TWIBUSCD_vect_num 20 #define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ #define TWI_vect_num 21 #define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ #define SPI_STC_vect_num 22 #define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ #define VADC_vect_num 23 #define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ #define CCADC_CONV_vect_num 24 #define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ #define CCADC_REG_CUR_vect_num 25 #define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ #define CCADC_ACC_vect_num 26 #define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ #define EE_READY_vect_num 27 #define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ #define SPM_vect_num 28 #define SPM_vect _VECTOR(28) /* SPM Ready */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (29 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (2048) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (NA) #define XRAMEND (RAMEND) #define E2END (0x3FF) #define E2PAGESIZE (4) #define FLASHEND (0x7FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ #define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ #define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ #define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ #define FUSE_CKDIV (unsigned char)~_BV(4) /* CKDIV Register */ #define HFUSE_DEFAULT (FUSE_CKDIV & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x10 /* Device Pin Definitions */ #define PV2_DDR DDRV #define PV2_PORT PORTV #define PV2_PIN PINV #define PV2_BIT 2 #define PV1_DDR DDRV #define PV1_PORT PORTV #define PV1_PIN PINV #define PV1_BIT 1 #define NV_DDR DDRNV #define NV_PORT PORTNV #define NV_PIN PINNV #define NV_BIT NV #define VFET_DDR DDRVFET #define VFET_PORT PORTVFET #define VFET_PIN PINVFET #define VFET_BIT VFET #define CF1P_DDR DDRCF1P #define CF1P_PORT PORTCF1P #define CF1P_PIN PINCF1P #define CF1P_BIT CF1P #define CF1N_DDR DDRCF1N #define CF1N_PORT PORTCF1N #define CF1N_PIN PINCF1N #define CF1N_BIT CF1N #define CF2P_DDR DDRCF2P #define CF2P_PORT PORTCF2P #define CF2P_PIN PINCF2P #define CF2P_BIT CF2P #define CF2N_DDR DDRCF2N #define CF2N_PORT PORTCF2N #define CF2N_PIN PINCF2N #define CF2N_BIT CF2N #define VREG_DDR DDRVREG #define VREG_PORT PORTVREG #define VREG_PIN PINVREG #define VREG_BIT VREG #define VREF_DDR DDRVREF #define VREF_PORT PORTVREF #define VREF_PIN PINVREF #define VREF_BIT VREF #define VREF_DDR DDRVREFGND #define VREF_PORT PORTVREFGND #define VREF_PIN PINVREFGND #define VREF_BIT VREFGND #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI #define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI #define NI_PIN PINNI #define NI_BIT NI #define PA0_DDR DDRA #define PA0_PORT PORTA #define PA0_PIN PINA #define PA0_BIT 0 #define PA1_DDR DDRA #define PA1_PORT PORTA #define PA1_PIN PINA #define PA1_BIT 1 #define PA2_DDR DDRA #define PA2_PORT PORTA #define PA2_PIN PINA #define PA2_BIT 2 #define PB0_DDR DDRB #define PB0_PORT PORTB #define PB0_PIN PINB #define PB0_BIT 0 #define PB1_DDR DDRB #define PB1_PORT PORTB #define PB1_PIN PINB #define PB1_BIT 1 #define PB2_DDR DDRB #define PB2_PORT PORTB #define PB2_PIN PINB #define PB2_BIT 2 #define PB3_DDR DDRB #define PB3_PORT PORTB #define PB3_PIN PINB #define PB3_BIT 3 #define PC0_DDR DDRC #define PC0_PORT PORTC #define PC0_PIN PINC #define PC0_BIT 0 #define BATT_DDR DDRBATT #define BATT_PORT PORTBATT #define BATT_PIN PINBATT #define BATT_BIT BATT #define OC_DDR DDROC #define OC_PORT PORTOC #define OC_PIN PINOC #define OC_BIT OC #endif /* _AVR_ATmega32HVB_H_ */ avr-libc-1.8.0.orig/include/avr/iotn45.h0000644000000000000000000000615111732702554014563 0ustar /* Copyright (c) 2005, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn45.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iotn45.h - definitions for ATtiny45 */ #ifndef _AVR_IOTN45_H_ #define _AVR_IOTN45_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x60) #define RAMEND 0x15F #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 4 #define FLASHEND 0xFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x06 #endif /* _AVR_IOTN45_H_ */ avr-libc-1.8.0.orig/include/avr/iox128d3.h0000644000000000000000000073020411732702554014725 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox128d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ /* avr/iox128d3.h - definitions for ATxmega128D3 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox128d3.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega128D3_H_ #define _AVR_ATxmega128D3_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ register8_t CTRL; /* Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) #define TWIC_MASTER_DATA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_CTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRLA bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (114 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (139264) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (131072) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x1E000) #define APPTABLE_SECTION_SIZE (8192) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x20000) #define BOOT_SECTION_SIZE (8192) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (16384) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (8192) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x48 #endif /* _AVR_ATxmega128D3_H_ */ avr-libc-1.8.0.orig/include/avr/iom649p.h0000644000000000000000000007106711732702554014660 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom649p.h 2146 2010-06-09 06:38:54Z joerg_wunsch $ */ /* avr/iom649p.h - definitions for ATmega649 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom649p.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega649_H_ #define _AVR_ATmega649_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define PINE3 3 #define PINE4 4 #define PINE5 5 #define PINE6 6 #define PINE7 7 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define DDE3 3 #define DDE4 4 #define DDE5 5 #define DDE6 6 #define DDE7 7 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define PORTE3 3 #define PORTE4 4 #define PORTE5 5 #define PORTE6 6 #define PORTE7 7 #define PINF _SFR_IO8(0x0F) #define PINF0 0 #define PINF1 1 #define PINF2 2 #define PINF3 3 #define PINF4 4 #define PINF5 5 #define PINF6 6 #define PINF7 7 #define DDRF _SFR_IO8(0x10) #define DDF0 0 #define DDF1 1 #define DDF2 2 #define DDF3 3 #define DDF4 4 #define DDF5 5 #define DDF6 6 #define DDF7 7 #define PORTF _SFR_IO8(0x11) #define PORTF0 0 #define PORTF1 1 #define PORTF2 2 #define PORTF3 3 #define PORTF4 4 #define PORTF5 5 #define PORTF6 6 #define PORTF7 7 #define PING _SFR_IO8(0x12) #define PING0 0 #define PING1 1 #define PING2 2 #define PING3 3 #define PING4 4 #define PING5 5 #define DDRG _SFR_IO8(0x13) #define DDG0 0 #define DDG1 1 #define DDG2 2 #define DDG3 3 #define DDG4 4 #define PORTG _SFR_IO8(0x14) #define PORTG0 0 #define PORTG1 1 #define PORTG2 2 #define PORTG3 3 #define PORTG4 4 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define PCIF2 6 #define PCIF3 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define PCIE2 6 #define PCIE3 7 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARL0 0 #define EEARL1 1 #define EEARL2 2 #define EEARL3 3 #define EEARL4 4 #define EEARL5 5 #define EEARL6 6 #define EEARL7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define GTCCR _SFR_IO8(0x23) #define PSR310 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRLCD 4 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2A0 0 #define OCR2A1 1 #define OCR2A2 2 #define OCR2A3 3 #define OCR2A4 4 #define OCR2A5 5 #define OCR2A6 6 #define OCR2A7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0_0 0 #define UBRR0_1 1 #define UBRR0_2 2 #define UBRR0_3 3 #define UBRR0_4 4 #define UBRR0_5 5 #define UBRR0_6 6 #define UBRR0_7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR0_8 0 #define UBRR0_9 1 #define UBRR0_10 2 #define UBRR0_11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR00 0 #define UDR01 1 #define UDR02 2 #define UDR03 3 #define UDR04 4 #define UDR05 5 #define UDR06 6 #define UDR07 7 #define LCDCRA _SFR_MEM8(0xE4) #define LCDBL 0 #define LCDIE 3 #define LCDIF 4 #define LCDAB 6 #define LCDEN 7 #define LCDCRB _SFR_MEM8(0xE5) #define LCDPM0 0 #define LCDPM1 1 #define LCDPM2 2 #define LCDPM3 3 #define LCDMUX0 4 #define LCDMUX1 5 #define LCD2B 6 #define LCDCS 7 #define LCDFRR _SFR_MEM8(0xE6) #define LCDCD0 0 #define LCDCD1 1 #define LCDCD2 2 #define LCDPS0 4 #define LCDPS1 5 #define LCDPS2 6 #define LCDCCR _SFR_MEM8(0xE7) #define LCDCC0 0 #define LCDCC1 1 #define LCDCC2 2 #define LCDCC3 3 #define LCDDC0 5 #define LCDDC1 6 #define LCDDC2 7 #define LCDDR0 _SFR_MEM8(0xEC) #define SEG000 0 #define SEG001 1 #define SEG002 2 #define SEG003 3 #define SEG004 4 #define SEG005 5 #define SEG006 6 #define SEG007 7 #define LCDDR1 _SFR_MEM8(0xED) #define SEG008 0 #define SEG009 1 #define SEG010 2 #define SEG011 3 #define SEG012 4 #define SEG013 5 #define SEG014 6 #define SEG015 7 #define LCDDR2 _SFR_MEM8(0xEE) #define SEG016 0 #define SEG017 1 #define SEG018 2 #define SEG019 3 #define SEG020 4 #define SEG021 5 #define SEG022 6 #define SEG023 7 #define LCDDR3 _SFR_MEM8(0xEF) #define SEG024 0 #define LCDDR4 _SFR_MEM8(0xF0) #define LCDDR5 _SFR_MEM8(0xF1) #define SEG100 0 #define SEG101 1 #define SEG102 2 #define SEG103 3 #define SEG104 4 #define SEG105 5 #define SEG106 6 #define SEG107 7 #define LCDDR6 _SFR_MEM8(0xF2) #define SEG108 0 #define SEG109 1 #define SEG110 2 #define SEG111 3 #define SEG112 4 #define SEG113 5 #define SEG114 6 #define SEG115 7 #define LCDDR7 _SFR_MEM8(0xF3) #define SEG116 0 #define SEG117 1 #define SEG118 2 #define SEG119 3 #define SEG120 4 #define SEG121 5 #define SEG122 6 #define SEG123 7 #define LCDDR8 _SFR_MEM8(0xF4) #define SEG124 0 #define LCDDR9 _SFR_MEM8(0xF5) #define LCDDR10 _SFR_MEM8(0xF6) #define SEG200 0 #define SEG201 1 #define SEG202 2 #define SEG203 3 #define SEG204 4 #define SEG205 5 #define SEG206 6 #define SEG207 7 #define LCDDR11 _SFR_MEM8(0xF7) #define SEG208 0 #define SEG209 1 #define SEG210 2 #define SEG211 3 #define SEG212 4 #define SEG213 5 #define SEG214 6 #define SEG215 7 #define LCDDR12 _SFR_MEM8(0xF8) #define SEG216 0 #define SEG217 1 #define SEG218 2 #define SEG219 3 #define SEG220 4 #define SEG221 5 #define SEG222 6 #define SEG223 7 #define LCDDR13 _SFR_MEM8(0xF9) #define SEG224 0 #define LCDDR14 _SFR_MEM8(0xFA) #define LCDDR15 _SFR_MEM8(0xFB) #define SEG300 0 #define SEG301 1 #define SEG302 2 #define SEG303 3 #define SEG304 4 #define SEG305 5 #define SEG306 6 #define SEG307 7 #define LCDDR16 _SFR_MEM8(0xFC) #define SEG308 0 #define SEG309 1 #define SEG310 2 #define SEG311 3 #define SEG312 4 #define SEG313 5 #define SEG314 6 #define SEG315 7 #define LCDDR17 _SFR_MEM8(0xFD) #define SEG316 0 #define SEG317 1 #define SEG318 2 #define SEG319 3 #define SEG320 4 #define SEG321 5 #define SEG322 6 #define SEG323 7 #define LCDDR18 _SFR_MEM8(0xFE) #define SEG324 0 #define LCDDR19 _SFR_MEM8(0xFF) /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) /* Timer/Counter2 Compare Match */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter Compare Match B */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) /* Timer/Counter0 Compare Match */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) /* SPI Serial Transfer Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) /* USART0, Rx Complete */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) /* USART0 Data register Empty */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) /* USART0, Tx Complete */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) /* USI Start Condition */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) /* USI Overflow */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) /* Analog Comparator */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) /* ADC Conversion Complete */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) /* EEPROM Ready */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) /* Store Program Memory Read */ #define LCD_vect_num 22 #define LCD_vect _VECTOR(22) /* LCD Start of Frame */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (23 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (256) #define RAMSTART (0x100) #define RAMSIZE (4096) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x7FF) #define E2PAGESIZE (8) #define FLASHEND (0xFFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_RESERVED (unsigned char)~_BV(0) /* Reserved fuse bit, do not program */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x0B /* Device Pin Definitions */ #define RXD_DDR DDRE #define RXD_PORT PORTE #define RXD_PIN PINE #define RXD_BIT 0 #define PCINT0_DDR DDRE #define PCINT0_PORT PORTE #define PCINT0_PIN PINE #define PCINT0_BIT 0 #define TXD_DDR DDRE #define TXD_PORT PORTE #define TXD_PIN PINE #define TXD_BIT 1 #define PCINT1_DDR DDRE #define PCINT1_PORT PORTE #define PCINT1_PIN PINE #define PCINT1_BIT 1 #define XCK_DDR DDRE #define XCK_PORT PORTE #define XCK_PIN PINE #define XCK_BIT 2 #define AIN0_DDR DDRE #define AIN0_PORT PORTE #define AIN0_PIN PINE #define AIN0_BIT 2 #define PCINT2_DDR DDRE #define PCINT2_PORT PORTE #define PCINT2_PIN PINE #define PCINT2_BIT 2 #define AIN1_DDR DDRE #define AIN1_PORT PORTE #define AIN1_PIN PINE #define AIN1_BIT 3 #define PCINT3_DDR DDRE #define PCINT3_PORT PORTE #define PCINT3_PIN PINE #define PCINT3_BIT 3 #define USCK_DDR DDRE #define USCK_PORT PORTE #define USCK_PIN PINE #define USCK_BIT 4 #define SCL_DDR DDRE #define SCL_PORT PORTE #define SCL_PIN PINE #define SCL_BIT 4 #define PCINT4_DDR DDRE #define PCINT4_PORT PORTE #define PCINT4_PIN PINE #define PCINT4_BIT 4 #define DI_DDR DDRE #define DI_PORT PORTE #define DI_PIN PINE #define DI_BIT 5 #define SDA_DDR DDRE #define SDA_PORT PORTE #define SDA_PIN PINE #define SDA_BIT 5 #define PCINT5_DDR DDRE #define PCINT5_PORT PORTE #define PCINT5_PIN PINE #define PCINT5_BIT 5 #define DO_DDR DDRE #define DO_PORT PORTE #define DO_PIN PINE #define DO_BIT 6 #define PCINT6_DDR DDRE #define PCINT6_PORT PORTE #define PCINT6_PIN PINE #define PCINT6_BIT 6 #define PCINT7_DDR DDRE #define PCINT7_PORT PORTE #define PCINT7_PIN PINE #define PCINT7_BIT 7 #define SS_DDR DDRB #define SS_PORT PORTB #define SS_PIN PINB #define SS_BIT 0 #define PCINT8_DDR DDRB #define PCINT8_PORT PORTB #define PCINT8_PIN PINB #define PCINT8_BIT 0 #define SCK_DDR DDRB #define SCK_PORT PORTB #define SCK_PIN PINB #define SCK_BIT 1 #define PCINT9_DDR DDRB #define PCINT9_PORT PORTB #define PCINT9_PIN PINB #define PCINT9_BIT 1 #define MOSI_DDR DDRB #define MOSI_PORT PORTB #define MOSI_PIN PINB #define MOSI_BIT 2 #define PCINT10_DDR DDRB #define PCINT10_PORT PORTB #define PCINT10_PIN PINB #define PCINT10_BIT 2 #define MISO_DDR DDRB #define MISO_PORT PORTB #define MISO_PIN PINB #define MISO_BIT 3 #define PCINT11_DDR DDRB #define PCINT11_PORT PORTB #define PCINT11_PIN PINB #define PCINT11_BIT 3 #define OC0_DDR DDRB #define OC0_PORT PORTB #define OC0_PIN PINB #define OC0_BIT 4 #define PCINT12_DDR DDRB #define PCINT12_PORT PORTB #define PCINT12_PIN PINB #define PCINT12_BIT 4 #define OC1A_DDR DDRB #define OC1A_PORT PORTB #define OC1A_PIN PINB #define OC1A_BIT 5 #define PCINT13_DDR DDRB #define PCINT13_PORT PORTB #define PCINT13_PIN PINB #define PCINT13_BIT 5 #define OC1B_DDR DDRB #define OC1B_PORT PORTB #define OC1B_PIN PINB #define OC1B_BIT 6 #define PCINT14_DDR DDRB #define PCINT14_PORT PORTB #define PCINT14_PIN PINB #define PCINT14_BIT 6 #define OC2_DDR DDRB #define OC2_PORT PORTB #define OC2_PIN PINB #define OC2_BIT 7 #define PCINT15_DDR DDRB #define PCINT15_PORT PORTB #define PCINT15_PIN PINB #define PCINT15_BIT 7 #define T1_DDR DDRG #define T1_PORT PORTG #define T1_PIN PING #define T1_BIT 3 #define SEG24_DDR DDRG #define SEG24_PORT PORTG #define SEG24_PIN PING #define SEG24_BIT 3 #define T0_DDR DDRG #define T0_PORT PORTG #define T0_PIN PING #define T0_BIT 4 #define SEG23_DDR DDRG #define SEG23_PORT PORTG #define SEG23_PIN PING #define SEG23_BIT 4 #define SEG22_DDR DDRD #define SEG22_PORT PORTD #define SEG22_PIN PIND #define SEG22_BIT 0 #define SEG21_DDR DDRD #define SEG21_PORT PORTD #define SEG21_PIN PIND #define SEG21_BIT 1 #define SEG20_DDR DDRD #define SEG20_PORT PORTD #define SEG20_PIN PIND #define SEG20_BIT 2 #define SEG19_DDR DDRD #define SEG19_PORT PORTD #define SEG19_PIN PIND #define SEG19_BIT 3 #define SEG18_DDR DDRD #define SEG18_PORT PORTD #define SEG18_PIN PIND #define SEG18_BIT 4 #define SEG17_DDR DDRD #define SEG17_PORT PORTD #define SEG17_PIN PIND #define SEG17_BIT 5 #define SEG16_DDR DDRD #define SEG16_PORT PORTD #define SEG16_PIN PIND #define SEG16_BIT 6 #define SEG15_DDR DDRD #define SEG15_PORT PORTD #define SEG15_PIN PIND #define SEG15_BIT 7 #define SEG14_DDR DDRG #define SEG14_PORT PORTG #define SEG14_PIN PING #define SEG14_BIT 0 #define SEG13_DDR DDRG #define SEG13_PORT PORTG #define SEG13_PIN PING #define SEG13_BIT 1 #define SEG12_DDR DDRC #define SEG12_PORT PORTC #define SEG12_PIN PINC #define SEG12_BIT 0 #define SEG11_DDR DDRC #define SEG11_PORT PORTC #define SEG11_PIN PINC #define SEG11_BIT 1 #define SEG10_DDR DDRC #define SEG10_PORT PORTC #define SEG10_PIN PINC #define SEG10_BIT 2 #define SEG9_DDR DDRC #define SEG9_PORT PORTC #define SEG9_PIN PINC #define SEG9_BIT 3 #define SEG8_DDR DDRC #define SEG8_PORT PORTC #define SEG8_PIN PINC #define SEG8_BIT 4 #define SEG7_DDR DDRC #define SEG7_PORT PORTC #define SEG7_PIN PINC #define SEG7_BIT 5 #define SEG6_DDR DDRC #define SEG6_PORT PORTC #define SEG6_PIN PINC #define SEG6_BIT 6 #define SEG5_DDR DDRC #define SEG5_PORT PORTC #define SEG5_PIN PINC #define SEG5_BIT 7 #define SEG4_DDR DDRG #define SEG4_PORT PORTG #define SEG4_PIN PING #define SEG4_BIT 2 #define SEG3_DDR DDRA #define SEG3_PORT PORTA #define SEG3_PIN PINA #define SEG3_BIT 7 #define SEG2_DDR DDRA #define SEG2_PORT PORTA #define SEG2_PIN PINA #define SEG2_BIT 6 #define SEG1_DDR DDRA #define SEG1_PORT PORTA #define SEG1_PIN PINA #define SEG1_BIT 5 #define SEG0_DDR DDRA #define SEG0_PORT PORTA #define SEG0_PIN PINA #define SEG0_BIT 4 #define COM3_DDR DDRA #define COM3_PORT PORTA #define COM3_PIN PINA #define COM3_BIT 3 #define COM2_DDR DDRA #define COM2_PORT PORTA #define COM2_PIN PINA #define COM2_BIT 2 #define COM1_DDR DDRA #define COM1_PORT PORTA #define COM1_PIN PINA #define COM1_BIT 1 #define COM0_DDR DDRA #define COM0_PORT PORTA #define COM0_PIN PINA #define COM0_BIT 0 #define ADC7_DDR DDRF #define ADC7_PORT PORTF #define ADC7_PIN PINF #define ADC7_BIT 7 #define ADC6_DDR DDRF #define ADC6_PORT PORTF #define ADC6_PIN PINF #define ADC6_BIT 6 #define TD0_DDR DDRF #define TD0_PORT PORTF #define TD0_PIN PINF #define TD0_BIT 6 #define ADC5_DDR DDRF #define ADC5_PORT PORTF #define ADC5_PIN PINF #define ADC5_BIT 5 #define ADC4_DDR DDRF #define ADC4_PORT PORTF #define ADC4_PIN PINF #define ADC4_BIT 4 #define ADC3_DDR DDRF #define ADC3_PORT PORTF #define ADC3_PIN PINF #define ADC3_BIT 3 #define ADC2_DDR DDRF #define ADC2_PORT PORTF #define ADC2_PIN PINF #define ADC2_BIT 2 #define ADC1_DDR DDRF #define ADC1_PORT PORTF #define ADC1_PIN PINF #define ADC1_BIT 1 #define ADC0_DDR DDRF #define ADC0_PORT PORTF #define ADC0_PIN PINF #define ADC0_BIT 0 #endif /* _AVR_ATmega649_H_ */ avr-libc-1.8.0.orig/include/avr/iotn12.h0000644000000000000000000001437211732702554014561 0ustar /* Copyright (c) 2002,2005 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn12.h 2236 2011-03-17 21:53:39Z arcanum $ */ /* avr/iotn12.h - definitions for ATtiny12 */ #ifndef _AVR_IOTN12_H_ #define _AVR_IOTN12_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn12.h" #else # error "Attempt to include more than one file." #endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" #endif /* I/O registers */ /* 0x00..0x07 reserved */ /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* 0x09..0x15 reserved */ /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* 0x19..0x1B reserved */ /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* 0x1F..0x20 reserved */ /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* 0x22..0x30 reserved */ /* Oscillator Calibration Register */ #define OSCCAL _SFR_IO8(0x31) /* Timer/Counter0 (8-bit) */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* 0x36..0x37 reserved */ /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK Register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3C..0x3E reserved */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 0 */ #define IO_PINS_vect_num 2 #define IO_PINS_vect _VECTOR(2) #define SIG_PIN _VECTOR(2) #define SIG_PIN_CHANGE _VECTOR(2) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 3 #define TIMER0_OVF_vect _VECTOR(3) #define SIG_OVERFLOW0 _VECTOR(3) /* EEPROM Ready */ #define EE_RDY_vect_num 4 #define EE_RDY_vect _VECTOR(4) #define SIG_EEPROM_READY _VECTOR(4) /* Analog Comparator */ #define ANA_COMP_vect_num 5 #define ANA_COMP_vect _VECTOR(5) #define SIG_COMPARATOR _VECTOR(5) #define _VECTORS_SIZE 12 /* Bit numbers */ /* GIMSK */ #define INT0 6 #define PCIE 5 /* GIFR */ #define INTF0 6 #define PCIF 5 /* TIMSK */ #define TOIE0 1 /* TIFR */ #define TOV0 1 /* MCUCR */ #define PUD 6 #define SE 5 #define SM 4 #define ISC01 1 #define ISC00 0 /* TCCR0 */ #define CS02 2 #define CS01 1 #define CS00 0 /* WDTCR */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PB5 = RESET# PB4 = XTAL2 PB3 = XTAL1 PB2 = T0 / SCK PB1 = INT0 / AIN1 / MISO PB0 = AIN0 / MOSI */ /* PORTB */ #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* ACSR */ #define ACD 7 #define AINBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIS1 1 #define ACIS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Last memory addresses */ #define RAMEND 0x1F #define XRAMEND 0x0 #define E2END 0x3F #define E2PAGESIZE 2 #define FLASHEND 0x3FF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_RSTDISBL (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN & FUSE_BODLEVEL) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x05 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN #pragma GCC poison SIG_PIN_CHANGE #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOTN12_H_ */ avr-libc-1.8.0.orig/include/avr/iousb1287.h0000644000000000000000000000661311732702554015107 0ustar /* Copyright (c) 2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iousb1287.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/iousb1287.h - definitions for AT90USB1287 */ #ifndef _AVR_AT90USB1287_H_ #define _AVR_AT90USB1287_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x20FF #define XRAMEND 0xFFFF #define E2END 0xFFF #define E2PAGESIZE 8 #define FLASHEND 0x1FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_HWBE (unsigned char)~_BV(3) #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x82 #endif /* _AVR_AT90USB1287_H_ */ avr-libc-1.8.0.orig/include/avr/io2323.h0000644000000000000000000001155611732702554014367 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io2323.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io2323.h - definitions for AT90S2323 */ #ifndef _AVR_IO2323_H_ #define _AVR_IO2323_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io2323.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Timer/Counter0 Overflow */ #define TIMER0_OVF0_vect_num 2 #define TIMER0_OVF0_vect _VECTOR(2) #define SIG_OVERFLOW0 _VECTOR(2) #define _VECTORS_SIZE 6 /* The Register Bit names are represented by their bit number (0-7). */ /* General Interrupt MaSK register */ #define INT0 6 #define INTF0 6 /* General Interrupt Flag Register */ #define TOIE0 1 #define TOV0 1 /* MCU general Control Register */ #define SE 5 #define SM 4 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PB2 = SCK/T0 PB1 = MISO/INT0 PB0 = MOSI */ /* Data Register, Port B */ #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB2 2 #define PINB1 1 #define PINB0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 0 #define FLASHEND 0x07FF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_FSTRT (unsigned char)~_BV(0) #define FUSE_SPIEN (unsigned char)~_BV(5) #define LFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x02 #endif /* _AVR_IO2323_H_ */ /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x02 avr-libc-1.8.0.orig/include/avr/iousb162.h0000644000000000000000000000661711732702554015022 0ustar /* Copyright (c) 2007 Anatoly Sokolov Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iousb162.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/iousb162.h - definitions for AT90USB162 */ #ifndef _AVR_AT90USB162_H_ #define _AVR_AT90USB162_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x2FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_RSTDSBL (unsigned char)~_BV(6) #define FUSE_DWEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_HWBE (unsigned char)~_BV(3) #define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x82 #endif /* _AVR_AT90USB162_H_ */ avr-libc-1.8.0.orig/include/avr/iotn261.h0000644000000000000000000000614211732702554014643 0ustar /* Copyright (c) 2006, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn261.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iotn261.h - definitions for ATtiny261 */ #ifndef _AVR_IOTN261_H_ #define _AVR_IOTN261_H_ 1 #include #define SPM_PAGESIZE 32 #define RAMSTART (0x60) #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 4 #define FLASHEND 0x7FF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x0C #endif /* _AVR_IOTN261_H_ */ avr-libc-1.8.0.orig/include/avr/iom3000.h0000644000000000000000000001746211732702554014537 0ustar /* Copyright (c) 2010, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ /* avr/iom3000.h - definitions for M3000 from Intelligent Motion Systems . */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom3000.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOM3000_H_ #define _AVR_IOM3000_H_ 1 /* Registers and associated bit numbers */ #define IPD _SFR_IO16(0x00) #define IPDL _SFR_IO8(0x00) #define IPDH _SFR_IO8(0x01) #define IPA _SFR_IO16(0x02) #define IPAL _SFR_IO8(0x02) #define IPAH _SFR_IO8(0x03) #define IPCR _SFR_IO8(0x04) #define ADRSLT _SFR_IO16(0x05) #define ADRSLTL _SFR_IO8(0x05) /* Alias. */ #define ADRSLTH _SFR_IO8(0x06) /* Alias. */ #define ADRSLTLO _SFR_IO8(0x05) /* Name according to datasheet. */ #define ADRSLTHI _SFR_IO8(0x06) /* Name according to datasheet. */ #define ADCSR _SFR_IO8(0x07) #define AMUXCTL _SFR_IO8(0x0B) #define MSPCR _SFR_IO8(0x0C) #define USPCR _SFR_IO8(0x0C) #define MSPSR _SFR_IO8(0x0D) #define USPSR _SFR_IO8(0x0D) #define MSPDR _SFR_IO8(0x0E) #define USPDR _SFR_IO8(0x0E) #define WDTCR _SFR_IO8(0x0F) #define USR _SFR_IO8(0x11) #define UCRA _SFR_IO8(0x12) #define UCRB _SFR_IO8(0x13) #define UBRR _SFR_IO8(0x14) #define UBRRL _SFR_IO8(0x14) /* Alias. */ #define UBRRH _SFR_IO8(0x15) /* Alias. */ #define UBRRLO _SFR_IO8(0x14) /* Name according to datasheet. */ #define UBRRHI _SFR_IO8(0x15) /* Name according to datasheet. */ #define GIFR _SFR_IO8(0x16) #define GIMSK _SFR_IO8(0x17) #define DACVAL _SFR_IO16(0x18) #define DACVALL _SFR_IO8(0x18) /* Alias. */ #define DACVALH _SFR_IO8(0x19) /* Alias. */ #define DACVALLO _SFR_IO8(0x18) /* Name according to datasheet. */ #define DACVALHI _SFR_IO8(0x19) /* Name according to datasheet. */ #define BGPPIN _SFR_IO8(0x1A) #define BGPDDR _SFR_IO8(0x1B) #define BGPPORT _SFR_IO8(0x1C) #define AGPPIN _SFR_IO8(0x1D) #define AGPDDR _SFR_IO8(0x1E) #define AGPPORT _SFR_IO8(0x1F) #define EXTCCR1A _SFR_IO8(0x20) #define EXTCCR1B _SFR_IO8(0x21) #define EXTCNT1 _SFR_IO16(0x22) #define EXTCNT1L _SFR_IO8(0x22) #define EXTCNT1H _SFR_IO8(0x23) #define EXOCR1A _SFR_IO16(0x24) #define EXOCR1AL _SFR_IO8(0x24) #define EXOCR1AH _SFR_IO8(0x25) #define EXOCR1B _SFR_IO16(0x26) #define EXOCR1BL _SFR_IO8(0x26) #define EXOCR1BH _SFR_IO8(0x27) #define EXTIFR _SFR_IO8(0x2A) #define EXTIMSK _SFR_IO8(0x2B) #define EXTCNT _SFR_IO8(0x2C) #define EXTCCR0 _SFR_IO8(0x2D) #define CGPPIN _SFR_IO8(0x30) #define CGPDDR _SFR_IO8(0x31) #define CGPPORT _SFR_IO8(0x32) #define MCSR _SFR_IO8(0x33) #define CDIVCAN _SFR_MEM8(0x100) #define CBTR1 _SFR_MEM8(0x101) #define CBTR2 _SFR_MEM8(0x102) #define CBTR3 _SFR_MEM8(0x103) #define CMCR _SFR_MEM8(0x104) #define CRAFEN _SFR_MEM8(0x105) #define CTARR _SFR_MEM8(0x106) #define CIER _SFR_MEM8(0x107) #define CCFLG _SFR_MEM8(0x108) #define CCISR _SFR_MEM8(0x109) #define CIDAH0 _SFR_MEM8(0x10A) #define CIDAH1 _SFR_MEM8(0x10B) #define CEFR _SFR_MEM8(0x10C) #define CRXERR _SFR_MEM8(0x10D) #define CTXERR _SFR_MEM8(0x10E) #define CVER _SFR_MEM8(0x10F) #define CIDAC0R _SFR_MEM32(0x110) #define CIDM0R _SFR_MEM32(0x114) #define CIDAC1R _SFR_MEM32(0x118) #define CIDM1R _SFR_MEM32(0x11C) #define CIDAC2R _SFR_MEM32(0x120) #define CIDM2R _SFR_MEM32(0x124) #define CIDAC3R _SFR_MEM32(0x128) #define CIDM3R _SFR_MEM32(0x12C) #define CIDAC4R _SFR_MEM32(0x130) #define CIDM4R _SFR_MEM32(0x134) #define CIDAC5R _SFR_MEM32(0x138) #define CIDM5R _SFR_MEM32(0x13C) #define CIDAC6R _SFR_MEM32(0x140) #define CIDM6R _SFR_MEM32(0x144) #define CTXB0 ((volatile uint8_t [16])(0x150)) #define CTXB1 ((volatile uint8_t [16])(0x160)) #define CTXB2 ((volatile uint8_t [16])(0x170)) #define CRXB0 ((volatile uint8_t [16])(0x180)) #define CRXB1 ((volatile uint8_t [16])(0x190)) #define PWMMSK _SFR_MEM8(0x200) #define PWMPER _SFR_MEM8(0x201) #define PWMSFRQ _SFR_MEM8(0x202) #define PWMCTL _SFR_MEM8(0x203) #define CURIRUN _SFR_MEM8(0x204) #define CURIRED _SFR_MEM8(0x205) #define CURRDLY _SFR_MEM16(0x206) #define VELLOW1 _SFR_MEM8(0x208) #define VELLOW2 _SFR_MEM8(0x209) #define VELLOW3 _SFR_MEM8(0x20A) #define VELHI1 _SFR_MEM8(0x20B) #define VELHI2 _SFR_MEM8(0x20C) #define VELHI3 _SFR_MEM8(0x20D) #define VELDEC1 _SFR_MEM8(0x20E) #define VELDEC2 _SFR_MEM8(0x20F) #define VELDEC3 _SFR_MEM8(0x210) #define VELACC1 _SFR_MEM8(0x211) #define VELACC2 _SFR_MEM8(0x212) #define VELACC3 _SFR_MEM8(0x213) #define VELCVEL _SFR_MEM8(0x214) /* #define VELCVEL _SFR_MEM8(0x215) #define VELCVEL _SFR_MEM8(0x216) */ #define VELTVEL _SFR_MEM8(0x217) /* #define VELTVEL _SFR_MEM8(0x218) #define VELTVEL _SFR_MEM8(0x219) */ #define VELVGCTL _SFR_MEM8(0x21A) #define VELSTB _SFR_MEM8(0x21B) #define VELIFLG _SFR_MEM8(0x21C) #define VELIMSK _SFR_MEM8(0x21D) #define IDXTRT _SFR_MEM32(0x21E) #define IDXENT _SFR_MEM32(0x222) #define IDXMSDT _SFR_MEM16(0x226) #define IDXPOT _SFR_MEM32(0x228) #define IDXPOS _SFR_MEM32(0x22C) #define IDXENC _SFR_MEM32(0x230) #define IDXCTRL _SFR_MEM8(0x234) #define IDXSTRB _SFR_MEM8(0x235) #define IDXCPTP _SFR_MEM32(0x236) #define IDXIFLG _SFR_MEM8(0x23A) #define IDXIMSK _SFR_MEM8(0x23B) #define SCIO _SFR_MEM8(0x23C) #define SCSW _SFR_MEM8(0x23D) #define SCRF _SFR_MEM32(0x23E) #define IOF _SFR_MEM8(0x242) #define MSELR _SFR_MEM8(0x243) #define STAT _SFR_MEM8(0x244) #define SPWMCTL _SFR_MEM8(0x245) #define SINDAC _SFR_MEM16(0x280) #define SINDACL _SFR_MEM8(0x280) #define SINDACH _SFR_MEM8(0x281) #define COSDAC _SFR_MEM8(0x282) #define COSDACL _SFR_MEM8(0x282) #define COSDACH _SFR_MEM8(0x283) #define GAINDAC _SFR_MEM8(0x284) #define DACCTRL _SFR_MEM8(0x285) #define INTCCR1A _SFR_MEM8(0x800) #define INTCCR1B _SFR_MEM8(0x801) #define INTCNT1 _SFR_MEM16(0x802) #define INTCNT1L _SFR_MEM8(0x802) #define INTCNT1H _SFR_MEM8(0x803) #define INOCR1A _SFR_MEM16(0x804) #define INOCR1AL _SFR_MEM8(0x804) #define INOCR1AH _SFR_MEM8(0x805) #define INOCR1B _SFR_MEM16(0x806) /* Data sheet says 0x807-0x808, but I believe this is wrong due to conflict with INTCNT. */ #define INOCR1BL _SFR_MEM8(0x806) #define INOCR1BH _SFR_MEM8(0x807) #define INTCNT _SFR_MEM8(0x808) #define INTCCR0 _SFR_MEM8(0x809) #define INTIFR _SFR_MEM8(0x80A) #define INTIMSK _SFR_MEM8(0x80B) /* Constants */ #define RAMEND 0xFFF /* Last On-Chip SRAM Location */ #define E2END 0x0 #define E2PAGESIZE 0 #define FLASHEND 0xFFFF #define _VECTORS_SIZE 0 #endif /* _AVR_IOM3000_H_ */ avr-libc-1.8.0.orig/include/avr/iotn4.h0000644000000000000000000002323411732702554014477 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn4.h 2063 2009-11-18 22:06:28Z arcanum $ */ /* avr/iotn4.h - definitions for ATtiny4 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn4.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny4_H_ #define _AVR_ATtiny4_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x00) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x01) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x02) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PUEB _SFR_IO8(0x03) #define PUEB0 0 #define PUEB1 1 #define PUEB2 2 #define PUEB3 3 #define PORTCR _SFR_IO8(0x0C) #define BBMB 1 #define PCMSK _SFR_IO8(0x10) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCIFR _SFR_IO8(0x11) #define PCIF0 0 #define PCICR _SFR_IO8(0x12) #define PCIE0 0 #define EIMSK _SFR_IO8(0x13) #define INT0 0 #define EIFR _SFR_IO8(0x14) #define INTF0 0 #define EICRA _SFR_IO8(0x15) #define ISC00 0 #define ISC01 1 #define DIDR0 _SFR_IO8(0x17) #define AIN0D 0 #define AIN1D 1 #define ACSR _SFR_IO8(0x1F) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACD 7 #define ICR0 _SFR_IO16(0x22) #define ICR0L _SFR_IO8(0x22) #define ICR0_0 0 #define ICR0_1 1 #define ICR0_2 2 #define ICR0_3 3 #define ICR0_4 4 #define ICR0_5 5 #define ICR0_6 6 #define ICR0_7 7 #define ICR0H _SFR_IO8(0x23) #define ICR0_8 0 #define ICR0_9 1 #define ICR0_10 2 #define ICR0_11 3 #define ICR0_12 4 #define ICR0_13 5 #define ICR0_14 6 #define ICR0_15 7 #define OCR0B _SFR_IO16(0x24) #define OCR0BL _SFR_IO8(0x24) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define OCR0BH _SFR_IO8(0x25) #define OCR0B8 0 #define OCR0B9 1 #define OCR0B10 2 #define OCR0B11 3 #define OCR0B12 4 #define OCR0B13 5 #define OCR0B14 6 #define OCR0B15 7 #define OCR0A _SFR_IO16(0x26) #define OCR0AL _SFR_IO8(0x26) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0AH _SFR_IO8(0x27) #define OCR0A8 0 #define OCR0A9 1 #define OCR0A10 2 #define OCR0A11 3 #define OCR0A12 4 #define OCR0A13 5 #define OCR0A14 6 #define OCR0A15 7 #define TCNT0 _SFR_IO16(0x28) #define TCNT0L _SFR_IO8(0x28) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCNT0H _SFR_IO8(0x29) #define TCNT0_8 0 #define TCNT0_9 1 #define TCNT0_10 2 #define TCNT0_11 3 #define TCNT0_12 4 #define TCNT0_13 5 #define TCNT0_14 6 #define TCNT0_15 7 #define TIFR0 _SFR_IO8(0x2A) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 5 #define TIMSK0 _SFR_IO8(0x2B) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 5 #define TCCR0C _SFR_IO8(0x2C) #define FOC0B 6 #define FOC0A 7 #define TCCR0B _SFR_IO8(0x2D) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define WGM03 4 #define ICES0 6 #define ICNC0 7 #define TCCR0A _SFR_IO8(0x2E) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define GTCCR _SFR_IO8(0x2F) #define PSR 0 #define TSM 7 #define WDTCSR _SFR_IO8(0x31) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define NVMCSR _SFR_IO8(0x32) #define NVMBSY 7 #define NVMCMD _SFR_IO8(0x33) #define NVMCMD0 0 #define NVMCMD1 1 #define NVMCMD2 2 #define NVMCMD3 3 #define NVMCMD4 4 #define NVMCMD5 5 #define VLMCSR _SFR_IO8(0x34) #define VLM0 0 #define VLM1 1 #define VLM2 2 #define VLMIE 6 #define VLMF 7 #define PRR _SFR_IO8(0x35) #define PRTIM0 0 #define PRADC 1 #define CLKPSR _SFR_IO8(0x36) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKMSR _SFR_IO8(0x37) #define CLKMS0 0 #define CLKMS1 1 #define OSCCAL _SFR_IO8(0x39) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define SMCR _SFR_IO8(0x3A) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define RSTFLR _SFR_IO8(0x3B) #define PORF 0 #define EXTRF 1 #define WDRF 3 #define CCP _SFR_IO8(0x3C) #define CCP0 0 #define CCP1 1 #define CCP2 2 #define CCP3 3 #define CCP4 4 #define CCP5 5 #define CCP6 6 #define CCP7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define TIM0_CAPT_vect_num 3 #define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ #define TIM0_OVF_vect_num 4 #define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ #define TIM0_COMPA_vect_num 5 #define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ #define TIM0_COMPB_vect_num 6 #define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ #define ANA_COMP_vect_num 7 #define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Watchdog Time-out */ #define VLM_vect_num 9 #define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (10 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (32) #define RAMSTART (0x40) #define RAMSIZE (32) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x0) #define E2PAGESIZE (0) #define FLASHEND (0x1FF) /* Fuses */ #define FUSE_MEMORY_SIZE 0 /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x0A /* Device Pin Definitions */ #define SPDATA_DDR DDRCINT #define SPDATA_PORT PORTCINT #define SPDATA_PIN PINCINT #define SPDATA_BIT INT0 #define OC0A_DDR DDRCINT #define OC0A_PORT PORTCINT #define OC0A_PIN PINCINT #define OC0A_BIT INT0 #define ADC0_DDR DDRCINT #define ADC0_PORT PORTCINT #define ADC0_PIN PINCINT #define ADC0_BIT INT0 #define AIN0_DDR DDRCINT #define AIN0_PORT PORTCINT #define AIN0_PIN PINCINT #define AIN0_BIT INT0 #define PB0_DDR DDRCINT #define PB0_PORT PORTCINT #define PB0_PIN PINCINT #define PB0_BIT INT0 #define SPCLK_DDR DDRCINT #define SPCLK_PORT PORTCINT #define SPCLK_PIN PINCINT #define SPCLK_BIT INT1 #define CLKI_DDR DDRCINT #define CLKI_PORT PORTCINT #define CLKI_PIN PINCINT #define CLKI_BIT INT1 #define ICP0_DDR DDRCINT #define ICP0_PORT PORTCINT #define ICP0_PIN PINCINT #define ICP0_BIT INT1 #define OC0B_DDR DDRCINT #define OC0B_PORT PORTCINT #define OC0B_PIN PINCINT #define OC0B_BIT INT1 #define ADC1_DDR DDRCINT #define ADC1_PORT PORTCINT #define ADC1_PIN PINCINT #define ADC1_BIT INT1 #define AIN1_DDR DDRCINT #define AIN1_PORT PORTCINT #define AIN1_PIN PINCINT #define AIN1_BIT INT1 #define PB1_DDR DDRCINT #define PB1_PORT PORTCINT #define PB1_PIN PINCINT #define PB1_BIT INT1 #define CLKO_DDR DDRT #define CLKO_PORT PORTT #define CLKO_PIN PINT #define CLKO_BIT T0 #define PCINT2_DDR DDRT #define PCINT2_PORT PORTT #define PCINT2_PIN PINT #define PCINT2_BIT T0 #define INT0_DDR DDRT #define INT0_PORT PORTT #define INT0_PIN PINT #define INT0_BIT T0 #define ADC2_DDR DDRT #define ADC2_PORT PORTT #define ADC2_PIN PINT #define ADC2_BIT T0 #define PB2_DDR DDRT #define PB2_PORT PORTT #define PB2_PIN PINT #define PB2_BIT T0 #define PCINT3_DDR DDRRESET #define PCINT3_PORT PORTRESET #define PCINT3_PIN PINRESET #define PCINT3_BIT RESET #define ADC3_DDR DDRRESET #define ADC3_PORT PORTRESET #define ADC3_PIN PINRESET #define ADC3_BIT RESET #define PB3_DDR DDRRESET #define PB3_PORT PORTRESET #define PB3_PIN PINRESET #define PB3_BIT RESET #endif /* _AVR_ATtiny4_H_ */ avr-libc-1.8.0.orig/include/avr/iom323.h0000644000000000000000000003410311732702554014453 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom323.h 2234 2011-03-16 04:32:21Z arcanum $ */ /* avr/iom323.h - definitions for ATmega323 */ #ifndef _AVR_IOM323_H_ #define _AVR_IOM323_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom323.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWAR _SFR_IO8(0x02) #define TWDR _SFR_IO8(0x03) /* ADC */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSR _SFR_IO8(0x06) #define ADMUX _SFR_IO8(0x07) /* analog comparator */ #define ACSR _SFR_IO8(0x08) /* UART */ #define UBRR _SFR_IO8(0x09) #define UBRRL UBRR #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) #define UDR _SFR_IO8(0x0C) /* SPI */ #define SPCR _SFR_IO8(0x0D) #define SPSR _SFR_IO8(0x0E) #define SPDR _SFR_IO8(0x0F) /* Port D */ #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) /* Port C */ #define PINC _SFR_IO8(0x13) #define DDRC _SFR_IO8(0x14) #define PORTC _SFR_IO8(0x15) /* Port B */ #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) /* Port A */ #define PINA _SFR_IO8(0x19) #define DDRA _SFR_IO8(0x1A) #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UBRRH _SFR_IO8(0x20) #define UCSRC UBRRH #define WDTCR _SFR_IO8(0x21) #define ASSR _SFR_IO8(0x22) /* Timer 2 */ #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) /* Timer 1 */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define TCCR1A _SFR_IO8(0x2F) #define SFIOR _SFR_IO8(0x30) #define OSCCAL _SFR_IO8(0x31) /* Timer 0 */ #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define MCUSR _SFR_IO8(0x34) #define MCUCSR MCUSR #define MCUCR _SFR_IO8(0x35) #define TWCR _SFR_IO8(0x36) #define SPMCR _SFR_IO8(0x37) #define TIFR _SFR_IO8(0x38) #define TIMSK _SFR_IO8(0x39) #define GIFR _SFR_IO8(0x3A) #define GIMSK _SFR_IO8(0x3B) #define GICR GIMSK #define OCR0 _SFR_IO8(0x3C) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART, Rx Complete */ #define USART_RXC_vect_num 13 #define USART_RXC_vect _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) /* USART Data Register Empty */ #define USART_UDRE_vect_num 14 #define USART_UDRE_vect _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) /* USART, Tx Complete */ #define USART_TXC_vect_num 15 #define USART_TXC_vect _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) /* ADC Conversion Complete */ #define ADC_vect_num 16 #define ADC_vect _VECTOR(16) #define SIG_ADC _VECTOR(16) /* EEPROM Ready */ #define EE_RDY_vect_num 17 #define EE_RDY_vect _VECTOR(17) #define SIG_EEPROM_READY _VECTOR(17) /* Analog Comparator */ #define ANA_COMP_vect_num 18 #define ANA_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* 2-wire Serial Interface */ #define TWI_vect_num 19 #define TWI_vect _VECTOR(19) #define SIG_2WIRE_SERIAL _VECTOR(19) /* Store Program Memory Ready */ #define SPM_RDY_vect_num 20 #define SPM_RDY_vect _VECTOR(20) #define _VECTORS_SIZE 80 /* Bit numbers */ /* GIMSK */ #define INT1 7 #define INT0 6 #define INT2 5 #define IVSEL 1 #define IVCE 0 /* GIFR */ #define INTF1 7 #define INTF0 6 #define INTF2 5 /* TIMSK */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 /* TIFR */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 /* SPMCR */ #define SPMIE 7 #define ASB 6 /* bit 5 reserved */ #define ASRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWI_TST 1 #define TWIE 0 /* TWAR */ #define TWGCE 0 /* TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 /* bits 2-0 reserved */ /* MCUCR */ /* bit 7 reserved (SM2?) */ #define SE 7 #define SM2 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* MCUCSR */ #define JTD 7 #define ISC2 6 #define EIH 5 #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* SFIOR */ #define RPDD 7 #define RPDC 6 #define RPDB 5 #define RPDA 4 #define ACME 3 #define PUD 2 #define PSR2 1 #define PSR10 0 /* TCCR0 */ #define FOC0 7 #define PWM0 6 #define COM01 5 #define COM00 4 #define CTC0 3 #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR2 */ #define FOC2 7 #define PWM2 6 #define COM21 5 #define COM20 4 #define CTC2 3 #define CS22 2 #define CS21 1 #define CS20 0 /* ASSR */ /* bits 7-4 reserved */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define PWM11 1 #define PWM10 0 /* TCCR1B */ #define ICNC1 7 #define ICES1 6 /* bit 5 reserved */ #define CTC11 4 #define CTC10 3 #define CS12 2 #define CS11 1 #define CS10 0 /* WDTCR */ /* bits 7-5 reserved */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PA7-PA0 = ADC7-ADC0 */ /* PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* PB7 = SCK PB6 = MISO PB5 = MOSI PB4 = SS# PB3 = AIN1 PB2 = AIN0 PB1 = T1 PB0 = T0 */ /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PC7 = TOSC2 PC6 = TOSC1 PC1 = SDA PC0 = SCL */ /* PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* PD7 = OC2 PD6 = ICP PD5 = OC1A PD4 = OC1B PD3 = INT1 PD2 = INT0 PD1 = TXD PD0 = RXD */ /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* PE2 = ALE PE1 = OC1B PE0 = ICP / INT2 */ /* SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UCSRA */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define PE 2 #define U2X 1 #define MPCM 0 /* UCSRB */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* UCSRC */ #define URSEL 7 #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* ACSR */ #define ACD 7 #define AINBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADCSR */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x85F #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 0 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_JTAGEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x01 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_2WIRE_SERIAL #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM323_H_ */ avr-libc-1.8.0.orig/include/avr/iom169pa.h0000644000000000000000000007103611732702554015012 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom169pa.h 2192 2010-11-08 13:53:24Z arcanum $ */ /* avr/iom169pa.h - definitions for ATmega169PA */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom169pa.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega169PA_H_ #define _AVR_ATmega169PA_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define PINE3 3 #define PINE4 4 #define PINE5 5 #define PINE6 6 #define PINE7 7 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define DDE3 3 #define DDE4 4 #define DDE5 5 #define DDE6 6 #define DDE7 7 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define PORTE3 3 #define PORTE4 4 #define PORTE5 5 #define PORTE6 6 #define PORTE7 7 #define PINF _SFR_IO8(0x0F) #define PINF0 0 #define PINF1 1 #define PINF2 2 #define PINF3 3 #define PINF4 4 #define PINF5 5 #define PINF6 6 #define PINF7 7 #define DDRF _SFR_IO8(0x10) #define DDF0 0 #define DDF1 1 #define DDF2 2 #define DDF3 3 #define DDF4 4 #define DDF5 5 #define DDF6 6 #define DDF7 7 #define PORTF _SFR_IO8(0x11) #define PORTF0 0 #define PORTF1 1 #define PORTF2 2 #define PORTF3 3 #define PORTF4 4 #define PORTF5 5 #define PORTF6 6 #define PORTF7 7 #define PING _SFR_IO8(0x12) #define PING0 0 #define PING1 1 #define PING2 2 #define PING3 3 #define PING4 4 #define PING5 5 #define DDRG _SFR_IO8(0x13) #define DDG0 0 #define DDG1 1 #define DDG2 2 #define DDG3 3 #define DDG4 4 #define DDG5 5 #define PORTG _SFR_IO8(0x14) #define PORTG0 0 #define PORTG1 1 #define PORTG2 2 #define PORTG3 3 #define PORTG4 4 #define PORTG5 5 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define GTCCR _SFR_IO8(0x23) #define PSR310 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 #define BODS 6 #define JTD 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRLCD 4 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 #define TCCR2B _SFR_MEM8(0xB1) #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2A0 0 #define OCR2A1 1 #define OCR2A2 2 #define OCR2A3 3 #define OCR2A4 4 #define OCR2A5 5 #define OCR2A6 6 #define OCR2A7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0_0 0 #define UBRR0_1 1 #define UBRR0_2 2 #define UBRR0_3 3 #define UBRR0_4 4 #define UBRR0_5 5 #define UBRR0_6 6 #define UBRR0_7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR0_8 0 #define UBRR0_9 1 #define UBRR0_10 2 #define UBRR0_11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR00 0 #define UDR01 1 #define UDR02 2 #define UDR03 3 #define UDR04 4 #define UDR05 5 #define UDR06 6 #define UDR07 7 #define LCDCRA _SFR_MEM8(0xE4) #define LCDBL 0 #define LCDCCD 1 #define LCDBD 2 #define LCDIE 3 #define LCDIF 4 #define LCDAB 6 #define LCDEN 7 #define LCDCRB _SFR_MEM8(0xE5) #define LCDPM0 0 #define LCDPM1 1 #define LCDPM2 2 #define LCDMUX0 4 #define LCDMUX1 5 #define LCD2B 6 #define LCDCS 7 #define LCDFRR _SFR_MEM8(0xE6) #define LCDCD0 0 #define LCDCD1 1 #define LCDCD2 2 #define LCDPS0 4 #define LCDPS1 5 #define LCDPS2 6 #define LCDCCR _SFR_MEM8(0xE7) #define LCDCC0 0 #define LCDCC1 1 #define LCDCC2 2 #define LCDCC3 3 #define LCDMDT 4 #define LCDDC0 5 #define LCDDC1 6 #define LCDDC2 7 #define LCDDR0 _SFR_MEM8(0xEC) #define SEG000 0 #define SEG001 1 #define SEG002 2 #define SEG003 3 #define SEG004 4 #define SEG005 5 #define SEG006 6 #define SEG007 7 #define LCDDR1 _SFR_MEM8(0xED) #define SEG008 0 #define SEG009 1 #define SEG010 2 #define SEG011 3 #define SEG012 4 #define SEG013 5 #define SEG014 6 #define SEG015 7 #define LCDDR2 _SFR_MEM8(0xEE) #define SEG016 0 #define SEG017 1 #define SEG018 2 #define SEG019 3 #define SEG020 4 #define SEG021 5 #define SEG022 6 #define SEG023 7 #define LCDDR3 _SFR_MEM8(0xEF) #define SEG024 0 #define LCDDR5 _SFR_MEM8(0xF1) #define SEG100 0 #define SEG101 1 #define SEG102 2 #define SEG103 3 #define SEG104 4 #define SEG105 5 #define SEG106 6 #define SEG107 7 #define LCDDR6 _SFR_MEM8(0xF2) #define SEG108 0 #define SEG109 1 #define SEG110 2 #define SEG111 3 #define SEG112 4 #define SEG113 5 #define SEG114 6 #define SEG115 7 #define LCDDR7 _SFR_MEM8(0xF3) #define SEG116 0 #define SEG117 1 #define SEG118 2 #define SEG119 3 #define SEG120 4 #define SEG121 5 #define SEG122 6 #define SEG123 7 #define LCDDR8 _SFR_MEM8(0xF4) #define SEG124 0 #define LCDDR10 _SFR_MEM8(0xF6) #define SEG200 0 #define SEG201 1 #define SEG202 2 #define SEG203 3 #define SEG204 4 #define SEG205 5 #define SEG206 6 #define SEG207 7 #define LCDDR11 _SFR_MEM8(0xF7) #define SEG208 0 #define SEG209 1 #define SEG210 2 #define SEG211 3 #define SEG212 4 #define SEG213 5 #define SEG214 6 #define SEG215 7 #define LCDDR12 _SFR_MEM8(0xF8) #define SEG216 0 #define SEG217 1 #define SEG218 2 #define SEG219 3 #define SEG220 4 #define SEG221 5 #define SEG222 6 #define SEG223 7 #define LCDDR13 _SFR_MEM8(0xF9) #define SEG224 0 #define LCDDR15 _SFR_MEM8(0xFB) #define SEG300 0 #define SEG301 1 #define SEG302 2 #define SEG303 3 #define SEG304 4 #define SEG305 5 #define SEG306 6 #define SEG307 7 #define LCDDR16 _SFR_MEM8(0xFC) #define SEG308 0 #define SEG309 1 #define SEG310 2 #define SEG311 3 #define SEG312 4 #define SEG313 5 #define SEG314 6 #define SEG315 7 #define LCDDR17 _SFR_MEM8(0xFD) #define SEG316 0 #define SEG317 1 #define SEG318 2 #define SEG319 3 #define SEG320 4 #define SEG321 5 #define SEG322 6 #define SEG323 7 #define LCDDR18 _SFR_MEM8(0xFE) #define SEG324 0 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) /* Timer/Counter2 Compare Match */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter Compare Match B */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) /* Timer/Counter0 Compare Match */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) /* SPI Serial Transfer Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) /* USART0, Rx Complete */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) /* USART0 Data register Empty */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) /* USART0, Tx Complete */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) /* USI Start Condition */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) /* USI Overflow */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) /* Analog Comparator */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) /* ADC Conversion Complete */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) /* EEPROM Ready */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) /* Store Program Memory Read */ #define LCD_vect_num 22 #define LCD_vect _VECTOR(22) /* LCD Start of Frame */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (23 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (1024) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x3FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown out detector trigger level */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x05 /* Device Pin Definitions */ #define RXD_DDR DDRE #define RXD_PORT PORTE #define RXD_PIN PINE #define RXD_BIT 0 #define PCINT0_DDR DDRE #define PCINT0_PORT PORTE #define PCINT0_PIN PINE #define PCINT0_BIT 0 #define TXD_DDR DDRE #define TXD_PORT PORTE #define TXD_PIN PINE #define TXD_BIT 1 #define PCINT1_DDR DDRE #define PCINT1_PORT PORTE #define PCINT1_PIN PINE #define PCINT1_BIT 1 #define XCK_DDR DDRE #define XCK_PORT PORTE #define XCK_PIN PINE #define XCK_BIT 2 #define AIN0_DDR DDRE #define AIN0_PORT PORTE #define AIN0_PIN PINE #define AIN0_BIT 2 #define PCINT2_DDR DDRE #define PCINT2_PORT PORTE #define PCINT2_PIN PINE #define PCINT2_BIT 2 #define AIN1_DDR DDRE #define AIN1_PORT PORTE #define AIN1_PIN PINE #define AIN1_BIT 3 #define PCINT3_DDR DDRE #define PCINT3_PORT PORTE #define PCINT3_PIN PINE #define PCINT3_BIT 3 #define USCK_DDR DDRE #define USCK_PORT PORTE #define USCK_PIN PINE #define USCK_BIT 4 #define SCL_DDR DDRE #define SCL_PORT PORTE #define SCL_PIN PINE #define SCL_BIT 4 #define PCINT4_DDR DDRE #define PCINT4_PORT PORTE #define PCINT4_PIN PINE #define PCINT4_BIT 4 #define DI_DDR DDRE #define DI_PORT PORTE #define DI_PIN PINE #define DI_BIT 5 #define SDA_DDR DDRE #define SDA_PORT PORTE #define SDA_PIN PINE #define SDA_BIT 5 #define PCINT5_DDR DDRE #define PCINT5_PORT PORTE #define PCINT5_PIN PINE #define PCINT5_BIT 5 #define DO_DDR DDRE #define DO_PORT PORTE #define DO_PIN PINE #define DO_BIT 6 #define PCINT6_DDR DDRE #define PCINT6_PORT PORTE #define PCINT6_PIN PINE #define PCINT6_BIT 6 #define PCINT7_DDR DDRE #define PCINT7_PORT PORTE #define PCINT7_PIN PINE #define PCINT7_BIT 7 #define SS_DDR DDRB #define SS_PORT PORTB #define SS_PIN PINB #define SS_BIT 0 #define PCINT8_DDR DDRB #define PCINT8_PORT PORTB #define PCINT8_PIN PINB #define PCINT8_BIT 0 #define SCK_DDR DDRB #define SCK_PORT PORTB #define SCK_PIN PINB #define SCK_BIT 1 #define PCINT9_DDR DDRB #define PCINT9_PORT PORTB #define PCINT9_PIN PINB #define PCINT9_BIT 1 #define MOSI_DDR DDRB #define MOSI_PORT PORTB #define MOSI_PIN PINB #define MOSI_BIT 2 #define PCINT10_DDR DDRB #define PCINT10_PORT PORTB #define PCINT10_PIN PINB #define PCINT10_BIT 2 #define MISO_DDR DDRB #define MISO_PORT PORTB #define MISO_PIN PINB #define MISO_BIT 3 #define PCINT11_DDR DDRB #define PCINT11_PORT PORTB #define PCINT11_PIN PINB #define PCINT11_BIT 3 #define OC0_DDR DDRB #define OC0_PORT PORTB #define OC0_PIN PINB #define OC0_BIT 4 #define PCINT12_DDR DDRB #define PCINT12_PORT PORTB #define PCINT12_PIN PINB #define PCINT12_BIT 4 #define OC1A_DDR DDRB #define OC1A_PORT PORTB #define OC1A_PIN PINB #define OC1A_BIT 5 #define PCINT13_DDR DDRB #define PCINT13_PORT PORTB #define PCINT13_PIN PINB #define PCINT13_BIT 5 #define OC1B_DDR DDRB #define OC1B_PORT PORTB #define OC1B_PIN PINB #define OC1B_BIT 6 #define PCINT14_DDR DDRB #define PCINT14_PORT PORTB #define PCINT14_PIN PINB #define PCINT14_BIT 6 #define OC2_DDR DDRB #define OC2_PORT PORTB #define OC2_PIN PINB #define OC2_BIT 7 #define PCINT15_DDR DDRB #define PCINT15_PORT PORTB #define PCINT15_PIN PINB #define PCINT15_BIT 7 #define T1_DDR DDRG #define T1_PORT PORTG #define T1_PIN PING #define T1_BIT 3 #define SEG24_DDR DDRG #define SEG24_PORT PORTG #define SEG24_PIN PING #define SEG24_BIT 3 #define T0_DDR DDRG #define T0_PORT PORTG #define T0_PIN PING #define T0_BIT 4 #define SEG23_DDR DDRG #define SEG23_PORT PORTG #define SEG23_PIN PING #define SEG23_BIT 4 #define SEG22_DDR DDRD #define SEG22_PORT PORTD #define SEG22_PIN PIND #define SEG22_BIT 0 #define SEG21_DDR DDRD #define SEG21_PORT PORTD #define SEG21_PIN PIND #define SEG21_BIT 1 #define SEG20_DDR DDRD #define SEG20_PORT PORTD #define SEG20_PIN PIND #define SEG20_BIT 2 #define SEG19_DDR DDRD #define SEG19_PORT PORTD #define SEG19_PIN PIND #define SEG19_BIT 3 #define SEG18_DDR DDRD #define SEG18_PORT PORTD #define SEG18_PIN PIND #define SEG18_BIT 4 #define SEG17_DDR DDRD #define SEG17_PORT PORTD #define SEG17_PIN PIND #define SEG17_BIT 5 #define SEG16_DDR DDRD #define SEG16_PORT PORTD #define SEG16_PIN PIND #define SEG16_BIT 6 #define SEG15_DDR DDRD #define SEG15_PORT PORTD #define SEG15_PIN PIND #define SEG15_BIT 7 #define SEG14_DDR DDRG #define SEG14_PORT PORTG #define SEG14_PIN PING #define SEG14_BIT 0 #define SEG13_DDR DDRG #define SEG13_PORT PORTG #define SEG13_PIN PING #define SEG13_BIT 1 #define SEG12_DDR DDRC #define SEG12_PORT PORTC #define SEG12_PIN PINC #define SEG12_BIT 0 #define SEG11_DDR DDRC #define SEG11_PORT PORTC #define SEG11_PIN PINC #define SEG11_BIT 1 #define SEG10_DDR DDRC #define SEG10_PORT PORTC #define SEG10_PIN PINC #define SEG10_BIT 2 #define SEG9_DDR DDRC #define SEG9_PORT PORTC #define SEG9_PIN PINC #define SEG9_BIT 3 #define SEG8_DDR DDRC #define SEG8_PORT PORTC #define SEG8_PIN PINC #define SEG8_BIT 4 #define SEG7_DDR DDRC #define SEG7_PORT PORTC #define SEG7_PIN PINC #define SEG7_BIT 5 #define SEG6_DDR DDRC #define SEG6_PORT PORTC #define SEG6_PIN PINC #define SEG6_BIT 6 #define SEG5_DDR DDRC #define SEG5_PORT PORTC #define SEG5_PIN PINC #define SEG5_BIT 7 #define SEG4_DDR DDRG #define SEG4_PORT PORTG #define SEG4_PIN PING #define SEG4_BIT 2 #define SEG3_DDR DDRA #define SEG3_PORT PORTA #define SEG3_PIN PINA #define SEG3_BIT 7 #define SEG2_DDR DDRA #define SEG2_PORT PORTA #define SEG2_PIN PINA #define SEG2_BIT 6 #define SEG1_DDR DDRA #define SEG1_PORT PORTA #define SEG1_PIN PINA #define SEG1_BIT 5 #define SEG0_DDR DDRA #define SEG0_PORT PORTA #define SEG0_PIN PINA #define SEG0_BIT 4 #define COM3_DDR DDRA #define COM3_PORT PORTA #define COM3_PIN PINA #define COM3_BIT 3 #define COM2_DDR DDRA #define COM2_PORT PORTA #define COM2_PIN PINA #define COM2_BIT 2 #define COM1_DDR DDRA #define COM1_PORT PORTA #define COM1_PIN PINA #define COM1_BIT 1 #define COM0_DDR DDRA #define COM0_PORT PORTA #define COM0_PIN PINA #define COM0_BIT 0 #define ADC7_DDR DDRF #define ADC7_PORT PORTF #define ADC7_PIN PINF #define ADC7_BIT 7 #define ADC6_DDR DDRF #define ADC6_PORT PORTF #define ADC6_PIN PINF #define ADC6_BIT 6 #define TD0_DDR DDRF #define TD0_PORT PORTF #define TD0_PIN PINF #define TD0_BIT 6 #define ADC5_DDR DDRF #define ADC5_PORT PORTF #define ADC5_PIN PINF #define ADC5_BIT 5 #define ADC4_DDR DDRF #define ADC4_PORT PORTF #define ADC4_PIN PINF #define ADC4_BIT 4 #define ADC3_DDR DDRF #define ADC3_PORT PORTF #define ADC3_PIN PINF #define ADC3_BIT 3 #define ADC2_DDR DDRF #define ADC2_PORT PORTF #define ADC2_PIN PINF #define ADC2_BIT 2 #define ADC1_DDR DDRF #define ADC1_PORT PORTF #define ADC1_PIN PINF #define ADC1_BIT 1 #define ADC0_DDR DDRF #define ADC0_PORT PORTF #define ADC0_PIN PINF #define ADC0_BIT 0 #endif /* _AVR_ATmega169PA_H_ */ avr-libc-1.8.0.orig/include/avr/iox192a3.h0000644000000000000000000111151711732702554014724 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox192a3.h 2218 2011-02-21 19:43:03Z arcanum $ */ /* avr/iox192a3.h - definitions for ATxmega192A3 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox192a3.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega192A3_H_ #define _AVR_ATxmega192A3_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* JTAG User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t GAINCAL; /* Gain Calibration */ register8_t OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* ADCB - Analog to Digital Converter B */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) #define ADCB_EVCTRL _SFR_MEM8(0x0243) #define ADCB_PRESCALER _SFR_MEM8(0x0244) #define ADCB_INTFLAGS _SFR_MEM8(0x0246) #define ADCB_CAL _SFR_MEM16(0x024C) #define ADCB_CH0RES _SFR_MEM16(0x0250) #define ADCB_CH1RES _SFR_MEM16(0x0252) #define ADCB_CH2RES _SFR_MEM16(0x0254) #define ADCB_CH3RES _SFR_MEM16(0x0256) #define ADCB_CMP _SFR_MEM16(0x0258) #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_GAINCAL _SFR_MEM8(0x0328) #define DACB_OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* TCE1 - Timer/Counter E1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) #define TCE1_CTRLD _SFR_MEM8(0x0A43) #define TCE1_CTRLE _SFR_MEM8(0x0A44) #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) #define TCE1_TEMP _SFR_MEM8(0x0A4F) #define TCE1_CNT _SFR_MEM16(0x0A60) #define TCE1_PER _SFR_MEM16(0x0A66) #define TCE1_CCA _SFR_MEM16(0x0A68) #define TCE1_CCB _SFR_MEM16(0x0A6A) #define TCE1_PERBUF _SFR_MEM16(0x0A76) #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) #define USARTE1_CTRLB _SFR_MEM8(0x0AB4) #define USARTE1_CTRLC _SFR_MEM8(0x0AB5) #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /* HIRESF - High-Resolution Extension F */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) /* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) #define USARTF1_CTRLB _SFR_MEM8(0x0BB4) #define USARTF1_CTRLC _SFR_MEM8(0x0BB5) #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) /* SPIF - Serial Peripheral Interface F */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) #define SPIF_DATA _SFR_MEM8(0x0BC3) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ #define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ #define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ #define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ #define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ #define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ #define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ #define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ #define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ #define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ #define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ #define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ #define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ #define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ #define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ #define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ #define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ #define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ #define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ #define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* ACB interrupt vectors */ #define ACB_AC0_vect_num 36 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ #define ACB_AC1_vect_num 37 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ #define ACB_ACW_vect_num 38 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ /* ADCB interrupt vectors */ #define ADCB_CH0_vect_num 39 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ #define ADCB_CH1_vect_num 40 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ #define ADCB_CH2_vect_num 41 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ #define ADCB_CH3_vect_num 42 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* SPIE interrupt vectors */ #define SPIE_INT_vect_num 57 #define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* USARTE1 interrupt vectors */ #define USARTE1_RXC_vect_num 61 #define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ #define USARTE1_DRE_vect_num 62 #define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ #define USARTE1_TXC_vect_num 63 #define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ /* USARTF0 interrupt vectors */ #define USARTF0_RXC_vect_num 119 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ #define USARTF0_DRE_vect_num 120 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ #define USARTF0_TXC_vect_num 121 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (122 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (204800) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (196608) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x2E000) #define APPTABLE_SECTION_SIZE (8192) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x30000) #define BOOT_SECTION_SIZE (8192) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (16777216) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (16384) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ #define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ #define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ #define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ #define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ #define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ #define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ #define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x44 #endif /* _AVR_ATxmega192A3_H_ */ avr-libc-1.8.0.orig/include/avr/iom165.h0000644000000000000000000004472511732702554014472 0ustar /* Copyright (c) 2004,2005,2006 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom165.h 2231 2011-03-07 05:06:55Z arcanum $ */ /* avr/iom165.h - definitions for ATmega165 */ #ifndef _AVR_IOM165_H_ #define _AVR_IOM165_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom165.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 6 #define PCIF1 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 6 #define PCIE1 7 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCD 7 // The datasheet defines this but IMO it should be OCDR7. #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ /* Combine PCMSK0 and PCMSK1 */ #define PCMSK _SFR_MEM16(0x6B) #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 /* Reserved [0x6D] */ #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSRA _SFR_MEM8(0xC0) #define MPCM 0 #define U2X 1 #define UPE 2 #define DOR 3 #define FE 4 #define UDRE 5 #define TXC 6 #define RXC 7 #define UCSRB _SFR_MEM8(0XC1) #define TXB8 0 #define RXB8 1 #define UCSZ2 2 #define TXEN 3 #define RXEN 4 #define UDRIE 5 #define TXCIE 6 #define RXCIE 7 #define UCSRC _SFR_MEM8(0xC2) #define UCPOL 0 #define UCSZ0 1 #define UCSZ1 2 #define USBS 3 #define UPM0 4 #define UPM1 5 #define UMSEL 6 /* Reserved [0xC3] */ /* Combine UBRRL and UBRRH */ #define UBRR _SFR_MEM16(0xC4) #define UBRRL _SFR_MEM8(0xC4) #define UBRRH _SFR_MEM8(0xC5) #define UDR _SFR_MEM8(0XC6) /* Reserved [0xC7..0xFF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART0, Rx Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) #define USART_RX_vect _VECTOR(13) /* Alias */ #define SIG_UART_RECV _VECTOR(13) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) #define USART_UDRE_vect _VECTOR(14) /* Alias */ #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define USART_TX_vect _VECTOR(15) /* Alias */ #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) #define _VECTORS_SIZE 88 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x4FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x07 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison USART_RX_vect #pragma GCC poison SIG_UART_RECV #pragma GCC poison USART_UDRE_vect #pragma GCC poison SIG_UART_DATA #pragma GCC poison USART_TX_vect #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM165_H_ */ avr-libc-1.8.0.orig/include/avr/version.h.in0000644000000000000000000000741611732702554015540 0ustar /* Copyright (c) 2005, Joerg Wunsch -*- c -*- All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: version.h.in 870 2005-09-12 20:18:12Z joerg_wunsch $ */ /** \defgroup avr_version : avr-libc version macros \code #include \endcode This header file defines macros that contain version numbers and strings describing the current version of avr-libc. The version number itself basically consists of three pieces that are separated by a dot: the major number, the minor number, and the revision number. For development versions (which use an odd minor number), the string representation additionally gets the date code (YYYYMMDD) appended. This file will also be included by \c . That way, portable tests can be implemented using \c that can be used in code that wants to remain backwards-compatible to library versions prior to the date when the library version API had been added, as referenced but undefined C preprocessor macros automatically evaluate to 0. */ #ifndef _AVR_VERSION_H_ #define _AVR_VERSION_H_ /** \ingroup avr_version String literal representation of the current library version. */ #define __AVR_LIBC_VERSION_STRING__ "@AVR_LIBC_VERSION@" /** \ingroup avr_version Numerical representation of the current library version. In the numerical representation, the major number is multiplied by 10000, the minor number by 100, and all three parts are then added. It is intented to provide a monotonically increasing numerical value that can easily be used in numerical checks. */ #define __AVR_LIBC_VERSION__ @AVR_LIBC_VERSION_NUMERIC@UL /** \ingroup avr_version String literal representation of the release date. */ #define __AVR_LIBC_DATE_STRING__ "@AVR_LIBC_RELDATE@" /** \ingroup avr_version Numerical representation of the release date. */ #define __AVR_LIBC_DATE_ @AVR_LIBC_RELDATE@UL /** \ingroup avr_version Library major version number. */ #define __AVR_LIBC_MAJOR__ @AVR_LIBC_MAJOR@ /** \ingroup avr_version Library minor version number. */ #define __AVR_LIBC_MINOR__ @AVR_LIBC_MINOR@ /** \ingroup avr_version Library revision number. */ #define __AVR_LIBC_REVISION__ @AVR_LIBC_REVISION@ #endif /* _AVR_VERSION_H_ */ avr-libc-1.8.0.orig/include/avr/iom16hva2.h0000644000000000000000000004314311732702554015157 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16hva2.h 2192 2010-11-08 13:53:24Z arcanum $ */ /* avr/iom16hva2.h - definitions for ATmega16HVA2 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16hva2.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega16HVA2_H_ #define _AVR_ATmega16HVA2_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 3 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 3 #define OSICSR _SFR_IO8(0x17) #define OSIEN 0 #define OSIST 1 #define OSISEL0 4 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define ICS0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define TCNT0 _SFR_IO16(0x26) #define TCNT0L _SFR_IO8(0x26) #define TCNT0L0 0 #define TCNT0L1 1 #define TCNT0L2 2 #define TCNT0L3 3 #define TCNT0L4 4 #define TCNT0L5 5 #define TCNT0L6 6 #define TCNT0L7 7 #define TCNT0H _SFR_IO8(0x27) #define TCNT0H0 0 #define TCNT0H1 1 #define TCNT0H2 2 #define TCNT0H3 3 #define TCNT0H4 4 #define TCNT0H5 5 #define TCNT0H6 6 #define TCNT0H7 7 #define OCR0A _SFR_IO8(0x28) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0B _SFR_IO8(0x29) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define DWDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BODRF 2 #define WDRF 3 #define OCDRF 4 #define MCUCR _SFR_IO8(0x35) #define PUD 4 #define CKOE 5 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define SIGRD 5 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRVADC 0 #define PRTIM0 1 #define PRTIM1 2 #define PRSPI 3 #define PRVRM 5 #define FOSCCAL _SFR_MEM8(0x66) #define FCAL0 0 #define FCAL1 1 #define FCAL2 2 #define FCAL3 3 #define FCAL4 4 #define FCAL5 5 #define FCAL6 6 #define FCAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 3 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 3 #define VADC _SFR_MEM16(0x78) #define VADCL _SFR_MEM8(0x78) #define VADC0 0 #define VADC1 1 #define VADC2 2 #define VADC3 3 #define VADC4 4 #define VADC5 5 #define VADC6 6 #define VADC7 7 #define VADCH _SFR_MEM8(0x79) #define VADC8 0 #define VADC9 1 #define VADC10 2 #define VADC11 3 #define VADCSR _SFR_MEM8(0x7A) #define VADCCIE 0 #define VADCCIF 1 #define VADSC 2 #define VADEN 3 #define VADMUX _SFR_MEM8(0x7C) #define VADMUX0 0 #define VADMUX1 1 #define VADMUX2 2 #define VADMUX3 3 #define DIDR0 _SFR_MEM8(0x7E) #define PA0DID 0 #define PA1DID 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define ICS1 3 #define ICES1 4 #define ICNC1 5 #define ICEN1 6 #define TCW1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define OCR1A _SFR_MEM8(0x88) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define OCR1B _SFR_MEM8(0x89) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define ROCR _SFR_MEM8(0xC8) #define ROCWIE 0 #define ROCWIF 1 #define ROCS 7 #define BGCCR _SFR_MEM8(0xD0) #define BGCC0 0 #define BGCC1 1 #define BGCC2 2 #define BGCC3 3 #define BGCC4 4 #define BGCC5 5 #define BGD 7 #define BGCRR _SFR_MEM8(0xD1) #define BGCR0 0 #define BGCR1 1 #define BGCR2 2 #define BGCR3 3 #define BGCR4 4 #define BGCR5 5 #define BGCR6 6 #define BGCR7 7 #define CADAC0 _SFR_MEM8(0xE0) #define CADAC00 0 #define CADAC01 1 #define CADAC02 2 #define CADAC03 3 #define CADAC04 4 #define CADAC05 5 #define CADAC06 6 #define CADAC07 7 #define CADAC1 _SFR_MEM8(0xE1) #define CADAC08 0 #define CADAC09 1 #define CADAC10 2 #define CADAC11 3 #define CADAC12 4 #define CADAC13 5 #define CADAC14 6 #define CADAC15 7 #define CADAC2 _SFR_MEM8(0xE2) #define CADAC16 0 #define CADAC17 1 #define CADAC18 2 #define CADAC19 3 #define CADAC20 4 #define CADAC21 5 #define CADAC22 6 #define CADAC23 7 #define CADAC3 _SFR_MEM8(0xE3) #define CADAC24 0 #define CADAC25 1 #define CADAC26 2 #define CADAC27 3 #define CADAC28 4 #define CADAC29 5 #define CADAC30 6 #define CADAC31 7 #define CADCSRA _SFR_MEM8(0xE4) #define CADSE 0 #define CADSI0 1 #define CADSI1 2 #define CADAS0 3 #define CADAS1 4 #define CADUB 5 #define CADPOL 6 #define CADEN 7 #define CADCSRB _SFR_MEM8(0xE5) #define CADICIF 0 #define CADRCIF 1 #define CADACIF 2 #define CADICIE 4 #define CADRCIE 5 #define CADACIE 6 #define CADRC _SFR_MEM8(0xE6) #define CADRC0 0 #define CADRC1 1 #define CADRC2 2 #define CADRC3 3 #define CADRC4 4 #define CADRC5 5 #define CADRC6 6 #define CADRC7 7 #define CADIC _SFR_MEM16(0xE8) #define CADICL _SFR_MEM8(0xE8) #define CADICL0 0 #define CADICL1 1 #define CADICL2 2 #define CADICL3 3 #define CADICL4 4 #define CADICL5 5 #define CADICL6 6 #define CADICL7 7 #define CADICH _SFR_MEM8(0xE9) #define CADICH0 0 #define CADICH1 1 #define CADICH2 2 #define CADICH3 3 #define CADICH4 4 #define CADICH5 5 #define CADICH6 6 #define CADICH7 7 #define FCSR _SFR_MEM8(0xF0) #define CFE 0 #define DFE 1 #define CPS 2 #define DUVRD 3 #define BPIMSK _SFR_MEM8(0xF2) #define CHCIE 0 #define DHCIE 1 #define COCIE 2 #define DOCIE 3 #define SCIE 4 #define BPIFR _SFR_MEM8(0xF3) #define CHCIF 0 #define DHCIF 1 #define COCIF 2 #define DOCIF 3 #define SCIF 4 #define BPSCD _SFR_MEM8(0xF5) #define SCDL0 0 #define SCDL1 1 #define SCDL2 2 #define SCDL3 3 #define SCDL4 4 #define SCDL5 5 #define SCDL6 6 #define SCDL7 7 #define BPDOCD _SFR_MEM8(0xF6) #define DOCDL0 0 #define DOCDL1 1 #define DOCDL2 2 #define DOCDL3 3 #define DOCDL4 4 #define DOCDL5 5 #define DOCDL6 6 #define DOCDL7 7 #define BPCOCD _SFR_MEM8(0xF7) #define COCDL0 0 #define COCDL1 1 #define COCDL2 2 #define COCDL3 3 #define COCDL4 4 #define COCDL5 5 #define COCDL6 6 #define COCDL7 7 #define BPDHCD _SFR_MEM8(0xF8) #define DHCDL0 0 #define DHCDL1 1 #define DHCDL2 2 #define DHCDL3 3 #define DHCDL4 4 #define DHCDL5 5 #define DHCDL6 6 #define DHCDL7 7 #define BPCHCD _SFR_MEM8(0xF9) #define CHCDL0 0 #define CHCDL1 1 #define CHCDL2 2 #define CHCDL3 3 #define CHCDL4 4 #define CHCDL5 5 #define CHCDL6 6 #define CHCDL7 7 #define BPSCTR _SFR_MEM8(0xFA) #define SCPT0 0 #define SCPT1 1 #define SCPT2 2 #define SCPT3 3 #define SCPT4 4 #define SCPT5 5 #define SCPT6 6 #define BPOCTR _SFR_MEM8(0xFB) #define OCPT0 0 #define OCPT1 1 #define OCPT2 2 #define OCPT3 3 #define OCPT4 4 #define OCPT5 5 #define BPHCTR _SFR_MEM8(0xFC) #define HCPT0 0 #define HCPT1 1 #define HCPT2 2 #define HCPT3 3 #define HCPT4 4 #define HCPT5 5 #define BPCR _SFR_MEM8(0xFD) #define CHCD 0 #define DHCD 1 #define COCD 2 #define DOCD 3 #define SCD 4 #define PRMD 7 #define BPPLR _SFR_MEM8(0xFE) #define BPPL 0 #define BPPLE 1 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define BPINT_vect_num 1 #define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ #define VREGMON_vect_num 2 #define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ #define INT0_vect_num 3 #define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ #define INT1_vect_num 4 #define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ #define INT2_vect_num 5 #define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ #define PCINT0_vect_num 6 #define PCINT0_vect _VECTOR(6) /* Pin Change Interrupt Request 0 */ #define WDT_vect_num 7 #define WDT_vect _VECTOR(7) /* Watchdog Timeout Interrupt */ #define TIMER1_IC_vect_num 8 #define TIMER1_IC_vect _VECTOR(8) /* Timer 1 Input capture */ #define TIMER1_COMPA_vect_num 9 #define TIMER1_COMPA_vect _VECTOR(9) /* Timer 1 Compare Match A */ #define TIMER1_COMPB_vect_num 10 #define TIMER1_COMPB_vect _VECTOR(10) /* Timer 1 Compare Match B */ #define TIMER1_OVF_vect_num 11 #define TIMER1_OVF_vect _VECTOR(11) /* Timer 1 overflow */ #define TIMER0_IC_vect_num 12 #define TIMER0_IC_vect _VECTOR(12) /* Timer 0 Input Capture */ #define TIMER0_COMPA_vect_num 13 #define TIMER0_COMPA_vect _VECTOR(13) /* Timer 0 Comapre Match A */ #define TIMER0_COMPB_vect_num 14 #define TIMER0_COMPB_vect _VECTOR(14) /* Timer 0 Compare Match B */ #define TIMER0_OVF_vect_num 15 #define TIMER0_OVF_vect _VECTOR(15) /* Timer 0 Overflow */ #define SPI_STC_vect_num 16 #define SPI_STC_vect _VECTOR(16) /* SPI Serial transfer complete */ #define VADC_vect_num 17 #define VADC_vect _VECTOR(17) /* Voltage ADC Conversion Complete */ #define CCADC_CONV_vect_num 18 #define CCADC_CONV_vect _VECTOR(18) /* Coulomb Counter ADC Conversion Complete */ #define CCADC_REG_CUR_vect_num 19 #define CCADC_REG_CUR_vect _VECTOR(19) /* Coloumb Counter ADC Regular Current */ #define CCADC_ACC_vect_num 20 #define CCADC_ACC_vect _VECTOR(20) /* Coloumb Counter ADC Accumulator */ #define EE_READY_vect_num 21 #define EE_READY_vect _VECTOR(21) /* EEPROM Ready */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (22 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (1024) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (NA) #define XRAMEND (RAMEND) #define E2END (0xFF) #define E2PAGESIZE (4) #define FLASHEND (0x3FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_SUT0 (unsigned char)~_BV(0) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(1) /* Select start-up time */ #define FUSE_SUT2 (unsigned char)~_BV(2) /* Select start-up time */ #define FUSE_SELFPRGEN (unsigned char)~_BV(3) /* Enable self programming */ #define FUSE_DWEN (unsigned char)~_BV(4) /* Enable debugWIRE */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ #define LFUSE_DEFAULT (FUSE_SPIEN) /* High Fuse Byte */ #define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select 0 */ #define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select 1 */ #define FUSE_COMPMODE (unsigned char)~_BV(2) /* Compatibility mode */ #define HFUSE_DEFAULT (FUSE_COMPMODE & FUSE_OSCSEL1) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x0E /* Device Pin Definitions */ #define PV2_DDR DDRV #define PV2_PORT PORTV #define PV2_PIN PINV #define PV2_BIT 2 #define PV1_DDR DDRV #define PV1_PORT PORTV #define PV1_PIN PINV #define PV1_BIT 1 #define NV_DDR DDRNV #define NV_PORT PORTNV #define NV_PIN PINNV #define NV_BIT NV #define VFET_DDR DDRVFET #define VFET_PORT PORTVFET #define VFET_PIN PINVFET #define VFET_BIT VFET #define CF1P_DDR DDRCF1P #define CF1P_PORT PORTCF1P #define CF1P_PIN PINCF1P #define CF1P_BIT CF1P #define CF1N_DDR DDRCF1N #define CF1N_PORT PORTCF1N #define CF1N_PIN PINCF1N #define CF1N_BIT CF1N #define CF2P_DDR DDRCF2P #define CF2P_PORT PORTCF2P #define CF2P_PIN PINCF2P #define CF2P_BIT CF2P #define CF2N_DDR DDRCF2N #define CF2N_PORT PORTCF2N #define CF2N_PIN PINCF2N #define CF2N_BIT CF2N #define VREG_DDR DDRVREG #define VREG_PORT PORTVREG #define VREG_PIN PINVREG #define VREG_BIT VREG #define VREF_DDR DDRVREF #define VREF_PORT PORTVREF #define VREF_PIN PINVREF #define VREF_BIT VREF #define VREFGND_DDR DDRVREFGND #define VREFGND_PORT PORTVREFGND #define VREFGND_PIN PINVREFGND #define VREFGND_BIT VREFGND #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI #define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI #define NI_PIN PINNI #define NI_BIT NI #define PA0_DDR DDRA #define PA0_PORT PORTA #define PA0_PIN PINA #define PA0_BIT 0 #define PA1_DDR DDRA #define PA1_PORT PORTA #define PA1_PIN PINA #define PA1_BIT 1 #define PA2_DDR DDRA #define PA2_PORT PORTA #define PA2_PIN PINA #define PA2_BIT 2 #define PB0_DDR DDRB #define PB0_PORT PORTB #define PB0_PIN PINB #define PB0_BIT 0 #define PB1_DDR DDRB #define PB1_PORT PORTB #define PB1_PIN PINB #define PB1_BIT 1 #define PB2_DDR DDRB #define PB2_PORT PORTB #define PB2_PIN PINB #define PB2_BIT 2 #define PB3_DDR DDRB #define PB3_PORT PORTB #define PB3_PIN PINB #define PB3_BIT 3 #define PC0_DDR DDRC #define PC0_PORT PORTC #define PC0_PIN PINC #define PC0_BIT 0 #define BATT_DDR DDRBATT #define BATT_PORT PORTBATT #define BATT_PIN PINBATT #define BATT_BIT BATT #define OC_DDR DDROC #define OC_PORT PORTOC #define OC_PIN PINOC #define OC_BIT OC #endif /* _AVR_ATmega16HVA2_H_ */ avr-libc-1.8.0.orig/include/avr/iom32m1.h0000644000000000000000000007733611732702554014645 0ustar /* Copyright (c) 2008-2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom32m1.h 2235 2011-03-17 04:13:14Z arcanum $ */ /* avr/iom32m1.h - definitions for ATmega32M1 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32m1.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega32M1_H_ #define _AVR_ATmega32M1_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define GPIOR1 _SFR_IO8(0x19) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x1A) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSRSYNC 0 #define ICPSEL1 6 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLF 2 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define AC0O 0 #define AC1O 1 #define AC2O 2 #define AC3O 3 #define AC0IF 4 #define AC1IF 5 #define AC2IF 6 #define AC3IF 7 #define DWDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPIPS 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRLIN 1 #define PRSPI 2 #define PRTIM0 3 #define PRTIM1 4 #define PRPSC 5 #define PRCAN 6 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6A) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6B) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6C) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define PCMSK3 _SFR_MEM8(0x6D) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define AMP0CSR _SFR_MEM8(0x75) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0TS2 2 #define AMPCMP0 3 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 #define AMP1CSR _SFR_MEM8(0x76) #define AMP1TS0 0 #define AMP1TS1 1 #define AMP1TS2 2 #define AMPCMP1 3 #define AMP1G0 4 #define AMP1G1 5 #define AMP1IS 6 #define AMP1EN 7 #define AMP2CSR _SFR_MEM8(0x77) #define AMP2TS0 0 #define AMP2TS1 1 #define AMP2TS2 2 #define AMPCMP2 3 #define AMP2G0 4 #define AMP2G1 5 #define AMP2IS 6 #define AMP2EN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define AREFEN 5 #define ISRCEN 6 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define AMP0ND 3 #define AMP0PD 4 #define ACMP0D 5 #define AMP2PD 6 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define DACON _SFR_MEM8(0x90) #define DAEN 0 #define DAOE 1 #define DALA 2 #define DATS0 4 #define DATS1 5 #define DATS2 6 #define DAATE 7 #define DAC _SFR_MEM16(0x91) #define DACL _SFR_MEM8(0x91) #define DACL0 0 #define DACL1 1 #define DACL2 2 #define DACL3 3 #define DACL4 4 #define DACL5 5 #define DACL6 6 #define DACL7 7 #define DACH _SFR_MEM8(0x92) #define DACH0 0 #define DACH1 1 #define DACH2 2 #define DACH3 3 #define DACH4 4 #define DACH5 5 #define DACH6 6 #define DACH7 7 #define AC0CON _SFR_MEM8(0x94) #define AC0M0 0 #define AC0M1 1 #define AC0M2 2 #define ACCKSEL 3 #define AC0IS0 4 #define AC0IS1 5 #define AC0IE 6 #define AC0EN 7 #define AC1CON _SFR_MEM8(0x95) #define AC1M0 0 #define AC1M1 1 #define AC1M2 2 #define AC1ICE 3 #define AC1IS0 4 #define AC1IS1 5 #define AC1IE 6 #define AC1EN 7 #define AC2CON _SFR_MEM8(0x96) #define AC2M0 0 #define AC2M1 1 #define AC2M2 2 #define AC2IS0 4 #define AC2IS1 5 #define AC2IE 6 #define AC2EN 7 #define AC3CON _SFR_MEM8(0x97) #define AC3M0 0 #define AC3M1 1 #define AC3M2 2 #define AC3IS0 4 #define AC3IS1 5 #define AC3IE 6 #define AC3EN 7 #define POCR0SA _SFR_MEM16(0xA0) #define POCR0SAL _SFR_MEM8(0xA0) #define POCR0SA_0 0 #define POCR0SA_1 1 #define POCR0SA_2 2 #define POCR0SA_3 3 #define POCR0SA_4 4 #define POCR0SA_5 5 #define POCR0SA_6 6 #define POCR0SA_7 7 #define POCR0SAH _SFR_MEM8(0xA1) #define POCR0SA_8 0 #define POCR0SA_9 1 #define POCR0SA_10 2 #define POCR0SA_11 3 #define POCR0SA_00 2 /* Deprecated */ #define POCR0SA_01 3 /* Deprecated */ #define POCR0RA _SFR_MEM16(0xA2) #define POCR0RAL _SFR_MEM8(0xA2) #define POCR0RA_0 0 #define POCR0RA_1 1 #define POCR0RA_2 2 #define POCR0RA_3 3 #define POCR0RA_4 4 #define POCR0RA_5 5 #define POCR0RA_6 6 #define POCR0RA_7 7 #define POCR0RAH _SFR_MEM8(0xA3) #define POCR0RA_8 0 #define POCR0RA_9 1 #define POCR0RA_10 2 #define POCR0RA_11 3 #define POCR0RA_00 2 /* Deprecated */ #define POCR0RA_01 3 /* Deprecated */ #define POCR0SB _SFR_MEM16(0xA4) #define POCR0SBL _SFR_MEM8(0xA4) #define POCR0SB_0 0 #define POCR0SB_1 1 #define POCR0SB_2 2 #define POCR0SB_3 3 #define POCR0SB_4 4 #define POCR0SB_5 5 #define POCR0SB_6 6 #define POCR0SB_7 7 #define POCR0SBH _SFR_MEM8(0xA5) #define POCR0SB_8 0 #define POCR0SB_9 1 #define POCR0SB_10 2 #define POCR0SB_11 3 #define POCR0SB_00 2 /* Deprecated */ #define POCR0SB_01 3 /* Deprecated */ #define POCR1SA _SFR_MEM16(0xA6) #define POCR1SAL _SFR_MEM8(0xA6) #define POCR1SA_0 0 #define POCR1SA_1 1 #define POCR1SA_2 2 #define POCR1SA_3 3 #define POCR1SA_4 4 #define POCR1SA_5 5 #define POCR1SA_6 6 #define POCR1SA_7 7 #define POCR1SAH _SFR_MEM8(0xA7) #define POCR1SA_8 0 #define POCR1SA_9 1 #define POCR1SA_10 2 #define POCR1SA_11 3 #define POCR1SA_00 2 /* Deprecated */ #define POCR1SA_01 3 /* Deprecated */ #define POCR1RA _SFR_MEM16(0xA8) #define POCR1RAL _SFR_MEM8(0xA8) #define POCR1RA_0 0 #define POCR1RA_1 1 #define POCR1RA_2 2 #define POCR1RA_3 3 #define POCR1RA_4 4 #define POCR1RA_5 5 #define POCR1RA_6 6 #define POCR1RA_7 7 #define POCR1RAH _SFR_MEM8(0xA9) #define POCR1RA_8 0 #define POCR1RA_9 1 #define POCR1RA_10 2 #define POCR1RA_11 3 #define POCR1RA_00 2 /* Deprecated */ #define POCR1SB _SFR_MEM16(0xAA) #define POCR1SBL _SFR_MEM8(0xAA) #define POCR1SB_0 0 #define POCR1SB_1 1 #define POCR1SB_2 2 #define POCR1SB_3 3 #define POCR1SB_4 4 #define POCR1SB_5 5 #define POCR1SB_6 6 #define POCR1SB_7 7 #define POCR1SBH _SFR_MEM8(0xAB) #define POCR1SB_8 0 #define POCR1SB_9 1 #define POCR1SB_10 2 #define POCR1SB_11 3 #define POCR1SB_00 2 /* Deprecated */ #define POCR1SB_01 3 /* Deprecated */ #define POCR2SA _SFR_MEM16(0xAC) #define POCR2SAL _SFR_MEM8(0xAC) #define POCR2SA_0 0 #define POCR2SA_1 1 #define POCR2SA_2 2 #define POCR2SA_3 3 #define POCR2SA_4 4 #define POCR2SA_5 5 #define POCR2SA_6 6 #define POCR2SA_7 7 #define POCR2SAH _SFR_MEM8(0xAD) #define POCR2SA_8 0 #define POCR2SA_9 1 #define POCR2SA_10 2 #define POCR2SA_11 3 #define POCR2SA_00 2 /* Deprecated */ #define POCR2SA_01 3 /* Deprecated */ #define POCR2RA _SFR_MEM16(0xAE) #define POCR2RAL _SFR_MEM8(0xAE) #define POCR2RA_0 0 #define POCR2RA_1 1 #define POCR2RA_2 2 #define POCR2RA_3 3 #define POCR2RA_4 4 #define POCR2RA_5 5 #define POCR2RA_6 6 #define POCR2RA_7 7 #define POCR2RAH _SFR_MEM8(0xAF) #define POCR2RA_8 0 #define POCR2RA_9 1 #define POCR2RA_10 2 #define POCR2RA_11 3 #define POCR2RA_00 2 /* Deprecated */ #define POCR2RA_01 3 /* Deprecated */ #define POCR2SB _SFR_MEM16(0xB0) #define POCR2SBL _SFR_MEM8(0xB0) #define POCR2SB_0 0 #define POCR2SB_1 1 #define POCR2SB_2 2 #define POCR2SB_3 3 #define POCR2SB_4 4 #define POCR2SB_5 5 #define POCR2SB_6 6 #define POCR2SB_7 7 #define POCR2SBH _SFR_MEM8(0xB1) #define POCR2SB_8 0 #define POCR2SB_9 1 #define POCR2SB_10 2 #define POCR2SB_11 3 #define POCR2SB_00 2 /* Deprecated */ #define POCR2SB_01 3 /* Deprecated */ #define POCRxRB _SFR_MEM16(0xB2) /* Deprecated */ #define POCR_RB _SFR_MEM16(0xB2) #define POCRxRBL _SFR_MEM8(0xB2) /* Deprecated */ #define POCR_RBL _SFR_MEM8(0xB2) #define POCR_RB_0 0 #define POCR_RB_1 1 #define POCR_RB_2 2 #define POCR_RB_3 3 #define POCR_RB_4 4 #define POCR_RB_5 5 #define POCR_RB_6 6 #define POCR_RB_7 7 #define POCRxRBH _SFR_MEM8(0xB3) /* Deprecated */ #define POCR_RBH _SFR_MEM8(0xB3) #define POCR_RB_8 0 #define POCR_RB_9 1 #define POCR_RB_10 2 #define POCR_RB_11 3 #define POCR_RB_00 2 /* Deprecated */ #define POCR_RB_01 3 /* Deprecated */ #define PSYNC _SFR_MEM8(0xB4) #define PSYNC00 0 #define PSYNC01 1 #define PSYNC10 2 #define PSYNC11 3 #define PSYNC20 4 #define PSYNC21 5 #define PCNF _SFR_MEM8(0xB5) #define POPA 2 #define POPB 3 #define PMODE 4 #define PULOCK 5 #define POC _SFR_MEM8(0xB6) #define POEN0A 0 #define POEN0B 1 #define POEN1A 2 #define POEN1B 3 #define POEN2A 4 #define POEN2B 5 #define PCTL _SFR_MEM8(0xB7) #define PRUN 0 #define PCCYC 1 #define PCLKSEL 5 #define PPRE0 6 #define PPRE1 7 #define PMIC0 _SFR_MEM8(0xB8) #define PRFM00 0 #define PRFM01 1 #define PRFM02 2 #define PAOC0 3 #define PFLTE0 4 #define PELEV0 5 #define PISEL0 6 #define POVEN0 7 #define PMIC1 _SFR_MEM8(0xB9) #define PRFM10 0 #define PRFM11 1 #define PRFM12 2 #define PAOC1 3 #define PFLTE1 4 #define PELEV1 5 #define PISEL1 6 #define POVEN1 7 #define PMIC2 _SFR_MEM8(0xBA) #define PRFM20 0 #define PRFM21 1 #define PRFM22 2 #define PAOC2 3 #define PFLTE2 4 #define PELEV2 5 #define PISEL2 6 #define POVEN2 7 #define PIM _SFR_MEM8(0xBB) #define PEOPE 0 #define PEVE0 1 #define PEVE1 2 #define PEVE2 3 #define PIFR _SFR_MEM8(0xBC) #define PEOP 0 #define PEV0 1 #define PEV1 2 #define PEV2 3 #define LINCR _SFR_MEM8(0xC8) #define LCMD0 0 #define LCMD1 1 #define LCMD2 2 #define LENA 3 #define LCONF0 4 #define LCONF1 5 #define LIN13 6 #define LSWRES 7 #define LINSIR _SFR_MEM8(0xC9) #define LRXOK 0 #define LTXOK 1 #define LIDOK 2 #define LERR 3 #define LBUSY 4 #define LIDST0 5 #define LIDST1 6 #define LIDST2 7 #define LINENIR _SFR_MEM8(0xCA) #define LENRXOK 0 #define LENTXOK 1 #define LENIDOK 2 #define LENERR 3 #define LINERR _SFR_MEM8(0xCB) #define LBERR 0 #define LCERR 1 #define LPERR 2 #define LSERR 3 #define LFERR 4 #define LOVERR 5 #define LTOERR 6 #define LABORT 7 #define LINBTR _SFR_MEM8(0xCC) #define LBT0 0 #define LBT1 1 #define LBT2 2 #define LBT3 3 #define LBT4 4 #define LBT5 5 #define LDISR 7 #define LINBRR _SFR_MEM16(0xCD) #define LINBRRL _SFR_MEM8(0xCD) #define LDIV0 0 #define LDIV1 1 #define LDIV2 2 #define LDIV3 3 #define LDIV4 4 #define LDIV5 5 #define LDIV6 6 #define LDIV7 7 #define LINBRRH _SFR_MEM8(0xCE) #define LDIV8 0 #define LDIV9 1 #define LDIV10 2 #define LDIV11 3 #define LINDLR _SFR_MEM8(0xCF) #define LRXDL0 0 #define LRXDL1 1 #define LRXDL2 2 #define LRXDL3 3 #define LTXDL0 4 #define LTXDL1 5 #define LTXDL2 6 #define LTXDL3 7 #define LINIDR _SFR_MEM8(0xD0) #define LID0 0 #define LID1 1 #define LID2 2 #define LID3 3 #define LID4 4 #define LID5 5 #define LP0 6 #define LP1 7 #define LINSEL _SFR_MEM8(0xD1) #define LINDX0 0 #define LINDX1 1 #define LINDX2 2 #define LAINC 3 #define LINDAT _SFR_MEM8(0xD2) #define LDATA0 0 #define LDATA1 1 #define LDATA2 2 #define LDATA3 3 #define LDATA4 4 #define LDATA5 5 #define LDATA6 6 #define LDATA7 7 #define CANGCON _SFR_MEM8(0xD8) #define SWRES 0 #define ENASTB 1 #define TEST 2 #define LISTEN 3 #define SYNTTC 4 #define TTC 5 #define OVRQ 6 #define ABRQ 7 #define CANGSTA _SFR_MEM8(0xD9) #define ERRP 0 #define BOFF 1 #define ENFG 2 #define RXBSY 3 #define TXBSY 4 #define OVFG 6 #define CANGIT _SFR_MEM8(0xDA) #define AERG 0 #define FERG 1 #define CERG 2 #define SERG 3 #define BXOK 4 #define OVRTIM 5 #define BOFFIT 6 #define CANIT 7 #define CANGIE _SFR_MEM8(0xDB) #define ENOVRT 0 #define ENERG 1 #define ENBX 2 #define ENERR 3 #define ENTX 4 #define ENRX 5 #define ENBOFF 6 #define ENIT 7 #define CANEN2 _SFR_MEM8(0xDC) #define ENMOB0 0 #define ENMOB1 1 #define ENMOB2 2 #define ENMOB3 3 #define ENMOB4 4 #define ENMOB5 5 #define CANEN1 _SFR_MEM8(0xDD) #define CANIE2 _SFR_MEM8(0xDE) #define IEMOB0 0 #define IEMOB1 1 #define IEMOB2 2 #define IEMOB3 3 #define IEMOB4 4 #define IEMOB5 5 #define CANIE1 _SFR_MEM8(0xDF) /* RegDef: CAN Status Interrupt MOb Register*/ #define CANSIT _SFR_MEM16(0xE0) #define CANSIT2 _SFR_MEM8(0xE0) #define SIT0 0 #define SIT1 1 #define SIT2 2 #define SIT3 3 #define SIT4 4 #define SIT5 5 #define CANSIT1 _SFR_MEM8(0xE1) #define CANBT1 _SFR_MEM8(0xE2) #define BRP0 1 #define BRP1 2 #define BRP2 3 #define BRP3 4 #define BRP4 5 #define BRP5 6 #define CANBT2 _SFR_MEM8(0xE3) #define PRS0 1 #define PRS1 2 #define PRS2 3 #define SJW0 5 #define SJW1 6 #define CANBT3 _SFR_MEM8(0xE4) #define SMP 0 #define PHS10 1 #define PHS11 2 #define PHS12 3 #define PHS20 4 #define PHS21 5 #define PHS22 6 #define CANTCON _SFR_MEM8(0xE5) #define TPRSC0 0 #define TPRSC1 1 #define TPRSC2 2 #define TPRSC3 3 #define TPRSC4 4 #define TPRSC5 5 #define TPRSC6 6 #define TPRSC7 7 #define CANTIM _SFR_MEM16(0xE6) #define CANTIML _SFR_MEM8(0xE6) #define CANTIM0 0 #define CANTIM1 1 #define CANTIM2 2 #define CANTIM3 3 #define CANTIM4 4 #define CANTIM5 5 #define CANTIM6 6 #define CANTIM7 7 #define CANTIMH _SFR_MEM8(0xE7) #define CANTIM8 0 #define CANTIM9 1 #define CANTIM10 2 #define CANTIM11 3 #define CANTIM12 4 #define CANTIM13 5 #define CANTIM14 6 #define CANTIM15 7 #define CANTTC _SFR_MEM16(0xE8) #define CANTTCL _SFR_MEM8(0xE8) #define TIMTCC0 0 #define TIMTCC1 1 #define TIMTCC2 2 #define TIMTCC3 3 #define TIMTCC4 4 #define TIMTCC5 5 #define TIMTCC6 6 #define TIMTCC7 7 #define CANTTCH _SFR_MEM8(0xE9) #define TIMTCC8 0 #define TIMTCC9 1 #define TIMTCC10 2 #define TIMTCC11 3 #define TIMTCC12 4 #define TIMTCC13 5 #define TIMTCC14 6 #define TIMTCC15 7 #define CANTEC _SFR_MEM8(0xEA) #define TEC0 0 #define TEC1 1 #define TEC2 2 #define TEC3 3 #define TEC4 4 #define TEC5 5 #define TEC6 6 #define TEC7 7 #define CANREC _SFR_MEM8(0xEB) #define REC0 0 #define REC1 1 #define REC2 2 #define REC3 3 #define REC4 4 #define REC5 5 #define REC6 6 #define REC7 7 #define CANHPMOB _SFR_MEM8(0xEC) #define CGP0 0 #define CGP1 1 #define CGP2 2 #define CGP3 3 #define HPMOB0 4 #define HPMOB1 5 #define HPMOB2 6 #define HPMOB3 7 #define CANPAGE _SFR_MEM8(0xED) #define INDX0 0 #define INDX1 1 #define INDX2 2 #define AINC 3 #define MOBNB0 4 #define MOBNB1 5 #define MOBNB2 6 #define MOBNB3 7 #define CANSTMOB _SFR_MEM8(0xEE) #define AERR 0 #define FERR 1 #define CERR 2 #define SERR 3 #define BERR 4 #define RXOK 5 #define TXOK 6 #define DLCW 7 #define CANCDMOB _SFR_MEM8(0xEF) #define DLC0 0 #define DLC1 1 #define DLC2 2 #define DLC3 3 #define IDE 4 #define RPLV 5 #define CONMOB0 6 #define CONMOB1 7 /* RegDef: CAN Identifier Tag Registers*/ #define CANIDT _SFR_MEM32(0xF0) #define CANIDT4 _SFR_MEM8(0xF0) #define RB0TAG 0 #define RB1TAG 1 #define RTRTAG 2 #define IDT0 3 #define IDT1 4 #define IDT2 5 #define IDT3 6 #define IDT4 7 #define CANIDT3 _SFR_MEM8(0xF1) #define IDT5 0 #define IDT6 1 #define IDT7 2 #define IDT8 3 #define IDT9 4 #define IDT10 5 #define IDT11 6 #define IDT12 7 #define CANIDT2 _SFR_MEM8(0xF2) #define IDT13 0 #define IDT14 1 #define IDT15 2 #define IDT16 3 #define IDT17 4 #define IDT18 5 #define IDT19 6 #define IDT20 7 #define CANIDT1 _SFR_MEM8(0xF3) #define IDT21 0 #define IDT22 1 #define IDT23 2 #define IDT24 3 #define IDT25 4 #define IDT26 5 #define IDT27 6 #define IDT28 7 /* RegDef: CAN Identifier Mask Registers */ #define CANIDM _SFR_MEM32(0xF4) #define CANIDM4 _SFR_MEM8(0xF4) #define IDEMSK 0 #define RTRMSK 2 #define IDMSK0 3 #define IDMSK1 4 #define IDMSK2 5 #define IDMSK3 6 #define IDMSK4 7 #define CANIDM3 _SFR_MEM8(0xF5) #define IDMSK5 0 #define IDMSK6 1 #define IDMSK7 2 #define IDMSK8 3 #define IDMSK9 4 #define IDMSK10 5 #define IDMSK11 6 #define IDMSK12 7 #define CANIDM2 _SFR_MEM8(0xF6) #define IDMSK13 0 #define IDMSK14 1 #define IDMSK15 2 #define IDMSK16 3 #define IDMSK17 4 #define IDMSK18 5 #define IDMSK19 6 #define IDMSK20 7 #define CANIDM1 _SFR_MEM8(0xF7) #define IDMSK21 0 #define IDMSK22 1 #define IDMSK23 2 #define IDMSK24 3 #define IDMSK25 4 #define IDMSK26 5 #define IDMSK27 6 #define IDMSK28 7 #define CANSTM _SFR_MEM16(0xF8) #define CANSTML _SFR_MEM8(0xF8) #define TIMSTM0 0 #define TIMSTM1 1 #define TIMSTM2 2 #define TIMSTM3 3 #define TIMSTM4 4 #define TIMSTM5 5 #define TIMSTM6 6 #define TIMSTM7 7 #define CANSTMH _SFR_MEM8(0xF9) #define TIMSTM8 0 #define TIMSTM9 1 #define TIMSTM10 2 #define TIMSTM11 3 #define TIMSTM12 4 #define TIMSTM13 5 #define TIMSTM14 6 #define TIMSTM15 7 #define CANMSG _SFR_MEM8(0xFA) #define MSG0 0 #define MSG1 1 #define MSG2 2 #define MSG3 3 #define MSG4 4 #define MSG5 5 #define MSG6 6 #define MSG7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define ANACOMP0_vect_num 1 #define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ #define ANACOMP1_vect_num 2 #define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ #define ANACOMP2_vect_num 3 #define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ #define ANACOMP3_vect_num 4 #define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ #define PSC_FAULT_vect_num 5 #define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ #define PSC_EC_vect_num 6 #define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ #define INT0_vect_num 7 #define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ #define INT1_vect_num 8 #define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ #define INT2_vect_num 9 #define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ #define INT3_vect_num 10 #define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 14 #define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 15 #define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 16 #define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ #define CAN_INT_vect_num 18 #define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ #define CAN_TOVF_vect_num 19 #define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ #define LIN_TC_vect_num 20 #define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ #define LIN_ERR_vect_num 21 #define LIN_ERR_vect _VECTOR(21) /* LIN Error */ #define PCINT0_vect_num 22 #define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 23 #define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 24 #define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ #define PCINT3_vect_num 25 #define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ #define SPI_STC_vect_num 26 #define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ #define ADC_vect_num 27 #define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ #define WDT_vect_num 28 #define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ #define EE_READY_vect_num 29 #define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ #define SPM_READY_vect_num 30 #define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (31 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x0100) #define RAMSIZE (2048) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (0x0) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x3FF) #define E2PAGESIZE (4) #define FLASHEND (0x7FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ #define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ #define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ #define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x84 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison POCR0SA_00 #pragma GCC poison POCR0SA_01 #pragma GCC poison POCR0RA_00 #pragma GCC poison POCR0RA_01 #pragma GCC poison POCR0SB_00 #pragma GCC poison POCR0SB_01 #pragma GCC poison POCR1SA_00 #pragma GCC poison POCR1SA_01 #pragma GCC poison POCR1RA_00 #pragma GCC poison POCR1SB_00 #pragma GCC poison POCR1SB_01 #pragma GCC poison POCR2SA_00 #pragma GCC poison POCR2SA_01 #pragma GCC poison POCR2RA_00 #pragma GCC poison POCR2RA_01 #pragma GCC poison POCR2SB_00 #pragma GCC poison POCR2SB_01 #pragma GCC poison POCRxRB #pragma GCC poison POCRxRBL #pragma GCC poison POCRxRBH #pragma GCC poison POCR_RB_00 #pragma GCC poison POCR_RB_01 #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_ATmega32M1_H_ */ avr-libc-1.8.0.orig/include/avr/iotn48.h0000644000000000000000000003630511732702554014572 0ustar /* Copyright (c) 2007-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn48.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iotn48.h - definitions for ATtiny48 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn48.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOTN48_H_ #define _AVR_IOTN48_H_ 1 /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINA _SFR_IO8(0x0C) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define DDRA _SFR_IO8(0x0D) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define PORTA _SFR_IO8(0x0E) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTCR _SFR_IO8(0x12) #define PUDA 0 #define PUDB 1 #define PUDC 2 #define PUDD 3 #define BBMA 4 #define BBMB 5 #define BBMC 6 #define BBMD 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define CTC0 3 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define PUD 4 #define BODSE 5 #define BODS 6 #define SPMCSR _SFR_IO8(0x37) #define SELFPRGEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define RWWSB 6 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTWI 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK3 _SFR_MEM8(0x6A) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define PCINT27 3 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define TWIHSR _SFR_MEM8(0xBE) /* Deprecated */ #define TWHSR _SFR_MEM8(0xBE) #define TWIHS 0 /* Interrupt Vectors */ /* Interrupt vector 0 is the reset vector. */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) #define PCINT2_vect_num 5 #define PCINT2_vect _VECTOR(5) #define PCINT3_vect_num 6 #define PCINT3_vect _VECTOR(6) #define WDT_vect_num 7 #define WDT_vect _VECTOR(7) #define TIMER1_CAPT_vect_num 8 #define TIMER1_CAPT_vect _VECTOR(8) #define TIMER1_COMPA_vect_num 9 #define TIMER1_COMPA_vect _VECTOR(9) #define TIMER1_COMPB_vect_num 10 #define TIMER1_COMPB_vect _VECTOR(10) #define TIMER1_OVF_vect_num 11 #define TIMER1_OVF_vect _VECTOR(11) #define TIMER0_COMPA_vect_num 12 #define TIMER0_COMPA_vect _VECTOR(12) #define TIMER0_COMPB_vect_num 13 #define TIMER0_COMPB_vect _VECTOR(13) #define TIMER0_OVF_vect_num 14 #define TIMER0_OVF_vect _VECTOR(14) #define SPI_STC_vect_num 15 #define SPI_STC_vect _VECTOR(15) #define ADC_vect_num 16 #define ADC_vect _VECTOR(16) #define EE_READY_vect_num 17 #define EE_READY_vect _VECTOR(17) #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define TWI_vect_num 19 #define TWI_vect _VECTOR(19) #define _VECTORS_SIZE 40 /* Constants */ #define SPM_PAGESIZE 32 #define RAMSTART (0x100) #define RAMEND 0x1FF #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x3F #define E2PAGESIZE 4 #define FLASHEND 0xFFF /* Fuse Information */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x09 #endif /* _AVR_IOTN48_H_ */ avr-libc-1.8.0.orig/include/avr/sleep.h0000644000000000000000000004505511732702554014557 0ustar /* Copyright (c) 2002, 2004 Theodore A. Roth Copyright (c) 2004, 2007, 2008 Eric B. Weddington Copyright (c) 2005, 2006, 2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: sleep.h 2238 2011-05-09 16:44:33Z arcanum $ */ #ifndef _AVR_SLEEP_H_ #define _AVR_SLEEP_H_ 1 #include #include /** \file */ /** \defgroup avr_sleep : Power Management and Sleep Modes \code #include \endcode Use of the \c SLEEP instruction can allow an application to reduce its power comsumption considerably. AVR devices can be put into different sleep modes. Refer to the datasheet for the details relating to the device you are using. There are several macros provided in this header file to actually put the device into sleep mode. The simplest way is to optionally set the desired sleep mode using \c set_sleep_mode() (it usually defaults to idle mode where the CPU is put on sleep but all peripheral clocks are still running), and then call \c sleep_mode(). This macro automatically sets the sleep enable bit, goes to sleep, and clears the sleep enable bit. Example: \code #include ... set_sleep_mode(); sleep_mode(); \endcode Note that unless your purpose is to completely lock the CPU (until a hardware reset), interrupts need to be enabled before going to sleep. As the \c sleep_mode() macro might cause race conditions in some situations, the individual steps of manipulating the sleep enable (SE) bit, and actually issuing the \c SLEEP instruction, are provided in the macros \c sleep_enable(), \c sleep_disable(), and \c sleep_cpu(). This also allows for test-and-sleep scenarios that take care of not missing the interrupt that will awake the device from sleep. Example: \code #include #include ... set_sleep_mode(); cli(); if (some_condition) { sleep_enable(); sei(); sleep_cpu(); sleep_disable(); } sei(); \endcode This sequence ensures an atomic test of \c some_condition with interrupts being disabled. If the condition is met, sleep mode will be prepared, and the \c SLEEP instruction will be scheduled immediately after an \c SEI instruction. As the intruction right after the \c SEI is guaranteed to be executed before an interrupt could trigger, it is sure the device will really be put to sleep. Some devices have the ability to disable the Brown Out Detector (BOD) before going to sleep. This will also reduce power while sleeping. If the specific AVR device has this ability then an additional macro is defined: \c sleep_bod_disable(). This macro generates inlined assembly code that will correctly implement the timed sequence for disabling the BOD before sleeping. However, there is a limited number of cycles after the BOD has been disabled that the device can be put into sleep mode, otherwise the BOD will not truly be disabled. Recommended practice is to disable the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then put the device to sleep (\c sleep_cpu()), like so: \code #include #include ... set_sleep_mode(); cli(); if (some_condition) { sleep_enable(); sleep_bod_disable(); sei(); sleep_cpu(); sleep_disable(); } sei(); \endcode */ /* Define an internal sleep control register and an internal sleep enable bit mask. */ #if defined(SLEEP_CTRL) /* XMEGA devices */ #define _SLEEP_CONTROL_REG SLEEP_CTRL #define _SLEEP_ENABLE_MASK SLEEP_SEN_bm #elif defined(SMCR) #define _SLEEP_CONTROL_REG SMCR #define _SLEEP_ENABLE_MASK _BV(SE) #elif defined(__AVR_AT94K__) #define _SLEEP_CONTROL_REG MCUR #define _SLEEP_ENABLE_MASK _BV(SE) #else #define _SLEEP_CONTROL_REG MCUCR #define _SLEEP_ENABLE_MASK _BV(SE) #endif /* Define set_sleep_mode() and sleep mode values per device. */ #if defined(__AVR_ATmega161__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN 1 #define SLEEP_MODE_PWR_SAVE 2 #define set_sleep_mode(mode) \ do { \ MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \ EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \ } while(0) #elif defined(__AVR_ATmega162__) \ || defined(__AVR_ATmega8515__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN 1 #define SLEEP_MODE_PWR_SAVE 2 #define SLEEP_MODE_ADC 3 #define SLEEP_MODE_STANDBY 4 #define SLEEP_MODE_EXT_STANDBY 5 #define set_sleep_mode(mode) \ do { \ MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \ MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \ EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \ } while(0) #elif defined(__AVR_AT90S2313__) \ || defined(__AVR_AT90S2323__) \ || defined(__AVR_AT90S2333__) \ || defined(__AVR_AT90S2343__) \ || defined(__AVR_AT43USB320__) \ || defined(__AVR_AT43USB355__) \ || defined(__AVR_AT90S4414__) \ || defined(__AVR_AT90S4433__) \ || defined(__AVR_AT90S8515__) \ || defined(__AVR_ATtiny22__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~__BV(SM)) | (mode)); \ } while(0) #elif defined(__AVR_ATtiny167__) \ || defined(__AVR_ATtiny87__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_ADC _BV(SM0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \ } while(0) #elif defined(__AVR_AT90S4434__) \ || defined(__AVR_AT76C711__) \ || defined(__AVR_AT90S8535__) \ || defined(__AVR_ATmega103__) \ || defined(__AVR_ATmega161__) \ || defined(__AVR_ATmega163__) \ || defined(__AVR_ATmega16HVB__) \ || defined(__AVR_ATmega16HVBREVB__) \ || defined(__AVR_ATmega32HVB__) \ || defined(__AVR_ATmega32HVBREVB__) \ || defined(__AVR_ATtiny13__) \ || defined(__AVR_ATtiny13A__) \ || defined(__AVR_ATtiny15__) \ || defined(__AVR_ATtiny24__) \ || defined(__AVR_ATtiny24A__) \ || defined(__AVR_ATtiny44__) \ || defined(__AVR_ATtiny44A__) \ || defined(__AVR_ATtiny84__) \ || defined(__AVR_ATtiny84A__) \ || defined(__AVR_ATtiny25__) \ || defined(__AVR_ATtiny45__) \ || defined(__AVR_ATtiny48__) \ || defined(__AVR_ATtiny85__) \ || defined(__AVR_ATtiny88__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_ADC _BV(SM0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \ } while(0) #elif defined(__AVR_ATtiny2313__) \ || defined(__AVR_ATtiny2313A__) \ || defined(__AVR_ATtiny4313__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN (_BV(SM0) | _BV(SM1)) #define SLEEP_MODE_STANDBY _BV(SM1) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \ } while(0) #elif defined(__AVR_AT94K__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \ } while(0) #elif defined(__AVR_ATtiny26__) \ || defined(__AVR_ATtiny261__) \ || defined(__AVR_ATtiny261A__) \ || defined(__AVR_ATtiny461__) \ || defined(__AVR_ATtiny461A__) \ || defined(__AVR_ATtiny861__) \ || defined(__AVR_ATtiny861A__) \ || defined(__AVR_ATtiny43U__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_ADC _BV(SM0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_STANDBY (_BV(SM0) | _BV(SM1)) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \ } while(0) #elif defined(__AVR_AT90PWM216__) \ || defined(__AVR_AT90PWM316__) \ || defined(__AVR_AT90PWM81__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_ADC _BV(SM0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2)) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \ } while(0) #elif defined(__AVR_AT90CAN128__) \ || defined(__AVR_AT90CAN32__) \ || defined(__AVR_AT90CAN64__) \ || defined(__AVR_AT90PWM1__) \ || defined(__AVR_AT90PWM2__) \ || defined(__AVR_AT90PWM2B__) \ || defined(__AVR_AT90PWM3__) \ || defined(__AVR_AT90PWM3B__) \ || defined(__AVR_AT90USB162__) \ || defined(__AVR_AT90USB82__) \ || defined(__AVR_AT90USB1286__) \ || defined(__AVR_AT90USB1287__) \ || defined(__AVR_AT90USB646__) \ || defined(__AVR_AT90USB647__) \ || defined(__AVR_ATmega128__) \ || defined(__AVR_ATmega1280__) \ || defined(__AVR_ATmega1281__) \ || defined(__AVR_ATmega1284P__) \ || defined(__AVR_ATmega128RFA1__) \ || defined(__AVR_ATmega16__) \ || defined(__AVR_ATmega16A__) \ || defined(__AVR_ATmega162__) \ || defined(__AVR_ATmega164A__) \ || defined(__AVR_ATmega164P__) \ || defined(__AVR_ATmega165__) \ || defined(__AVR_ATmega165A__) \ || defined(__AVR_ATmega165P__) \ || defined(__AVR_ATmega168__) \ || defined(__AVR_ATmega168A__) \ || defined(__AVR_ATmega168P__) \ || defined(__AVR_ATmega169__) \ || defined(__AVR_ATmega169A__) \ || defined(__AVR_ATmega169P__) \ || defined(__AVR_ATmega169PA__) \ || defined(__AVR_ATmega16HVA__) \ || defined(__AVR_ATmega16HVA2__) \ || defined(__AVR_ATmega16M1__) \ || defined(__AVR_ATmega16U2__) \ || defined(__AVR_ATmega16U4__) \ || defined(__AVR_ATmega2560__) \ || defined(__AVR_ATmega2561__) \ || defined(__AVR_ATmega32__) \ || defined(__AVR_ATmega323__) \ || defined(__AVR_ATmega324A__) \ || defined(__AVR_ATmega324P__) \ || defined(__AVR_ATmega324PA__) \ || defined(__AVR_ATmega325__) \ || defined(__AVR_ATmega325A__) \ || defined(__AVR_ATmega3250__) \ || defined(__AVR_ATmega3250A__) \ || defined(__AVR_ATmega328__) \ || defined(__AVR_ATmega328P__) \ || defined(__AVR_ATmega329__) \ || defined(__AVR_ATmega329A__) \ || defined(__AVR_ATmega329P__) \ || defined(__AVR_ATmega329PA__) \ || defined(__AVR_ATmega3290__) \ || defined(__AVR_ATmega3290A__) \ || defined(__AVR_ATmega3290P__) \ || defined(__AVR_ATmega32C1__) \ || defined(__AVR_ATmega32M1__) \ || defined(__AVR_ATmega32U2__) \ || defined(__AVR_ATmega32U4__) \ || defined(__AVR_ATmega32U6__) \ || defined(__AVR_ATmega406__) \ || defined(__AVR_ATmega48__) \ || defined(__AVR_ATmega48A__) \ || defined(__AVR_ATmega48P__) \ || defined(__AVR_ATmega64__) \ || defined(__AVR_ATmega640__) \ || defined(__AVR_ATmega644__) \ || defined(__AVR_ATmega644A__) \ || defined(__AVR_ATmega644P__) \ || defined(__AVR_ATmega644PA__) \ || defined(__AVR_ATmega645__) \ || defined(__AVR_ATmega645A__) \ || defined(__AVR_ATmega645P__) \ || defined(__AVR_ATmega6450__) \ || defined(__AVR_ATmega6450A__) \ || defined(__AVR_ATmega6450P__) \ || defined(__AVR_ATmega649__) \ || defined(__AVR_ATmega649A__) \ || defined(__AVR_ATmega6490__) \ || defined(__AVR_ATmega6490A__) \ || defined(__AVR_ATmega6490P__) \ || defined(__AVR_ATmega649P__) \ || defined(__AVR_ATmega64C1__) \ || defined(__AVR_ATmega64HVE__) \ || defined(__AVR_ATmega64M1__) \ || defined(__AVR_ATmega8__) \ || defined(__AVR_ATmega8515__) \ || defined(__AVR_ATmega8535__) \ || defined(__AVR_ATmega88__) \ || defined(__AVR_ATmega88A__) \ || defined(__AVR_ATmega88P__) \ || defined(__AVR_ATmega88PA__) \ || defined(__AVR_ATmega8HVA__) \ || defined(__AVR_ATmega8U2__) #define SLEEP_MODE_IDLE (0) #define SLEEP_MODE_ADC _BV(SM0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2)) #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2)) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \ } while(0) #elif defined(__AVR_ATxmega16A4__) \ || defined(__AVR_ATxmega16D4__) \ || defined(__AVR_ATxmega32A4__) \ || defined(__AVR_ATxmega32D4__) \ || defined(__AVR_ATxmega64A1__) \ || defined(__AVR_ATxmega64A1U__) \ || defined(__AVR_ATxmega64A3__) \ || defined(__AVR_ATxmega64D3__) \ || defined(__AVR_ATxmega128A1__) \ || defined(__AVR_ATxmega128A1U__) \ || defined(__AVR_ATxmega128A3__) \ || defined(__AVR_ATxmega128D3__) \ || defined(__AVR_ATxmega192A3__) \ || defined(__AVR_ATxmega192D3__) \ || defined(__AVR_ATxmega256A3__) \ || defined(__AVR_ATxmega256D3__) \ || defined(__AVR_ATxmega256A3B__) #define SLEEP_MODE_IDLE (0) #define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm) #define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm) #define SLEEP_MODE_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm) #define SLEEP_MODE_EXT_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \ } while(0) #elif defined(__AVR_AT90SCR100__) #define SLEEP_MODE_IDLE (0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2)) #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2)) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \ } while(0) #elif defined(__AVR_ATA6289__) #define SLEEP_MODE_IDLE (0) #define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0)) #define SLEEP_MODE_PWR_DOWN (_BV(SM1)) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \ } while(0) #elif defined(__AVR_ATtiny4__) \ || defined(__AVR_ATtiny5__) \ || defined(__AVR_ATtiny9__) \ || defined(__AVR_ATtiny10__) \ || defined(__AVR_ATtiny20__) \ || defined(__AVR_ATtiny40__) #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_ADC _BV(SM0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_STANDBY _BV(SM2) #define set_sleep_mode(mode) \ do { \ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \ } while(0) #else #error "No SLEEP mode defined for this device." #endif /** \ingroup avr_sleep Put the device in sleep mode. How the device is brought out of sleep mode depends on the specific mode selected with the set_sleep_mode() function. See the data sheet for your device for more details. */ #if defined(__DOXYGEN__) /** \ingroup avr_sleep Set the SE (sleep enable) bit. */ extern void sleep_enable (void); #else #define sleep_enable() \ do { \ _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK; \ } while(0) #endif #if defined(__DOXYGEN__) /** \ingroup avr_sleep Clear the SE (sleep enable) bit. */ extern void sleep_disable (void); #else #define sleep_disable() \ do { \ _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK); \ } while(0) #endif /** \ingroup avr_sleep Put the device into sleep mode. The SE bit must be set beforehand, and it is recommended to clear it afterwards. */ #if defined(__DOXYGEN__) extern void sleep_cpu (void); #else #define sleep_cpu() \ do { \ __asm__ __volatile__ ( "sleep" "\n\t" :: ); \ } while(0) #endif #if defined(__DOXYGEN__) extern void sleep_mode (void); #else #define sleep_mode() \ do { \ sleep_enable(); \ sleep_cpu(); \ sleep_disable(); \ } while (0) #endif #if defined(__DOXYGEN__) extern void sleep_bod_disable (void); #else #if defined(BODS) && defined(BODSE) #define sleep_bod_disable() \ do { \ uint8_t tempreg; \ __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \ "ori %[tempreg], %[bods_bodse]" "\n\t" \ "out %[mcucr], %[tempreg]" "\n\t" \ "andi %[tempreg], %[not_bodse]" "\n\t" \ "out %[mcucr], %[tempreg]" \ : [tempreg] "=&d" (tempreg) \ : [mcucr] "I" _SFR_IO_ADDR(MCUCR), \ [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \ [not_bodse] "i" (~_BV(BODSE))); \ } while (0) #endif #endif /*@}*/ #endif /* _AVR_SLEEP_H_ */ avr-libc-1.8.0.orig/include/avr/iom32c1.h0000644000000000000000000006303411732702554014621 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom32c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ /* avr/iom32c1.h - definitions for ATmega32C1 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32c1.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega32C1_H_ #define _AVR_ATmega32C1_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define GPIOR1 _SFR_IO8(0x19) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x1A) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSRSYNC 0 #define ICPSEL1 6 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLF 2 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define AC0O 0 #define AC1O 1 #define AC2O 2 #define AC3O 3 #define AC0IF 4 #define AC1IF 5 #define AC2IF 6 #define AC3IF 7 #define DWDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPIPS 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRLIN 1 #define PRSPI 2 #define PRTIM0 3 #define PRTIM1 4 #define PRPSC 5 #define PRCAN 6 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6A) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6B) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6C) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define PCMSK3 _SFR_MEM8(0x6D) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define AMP0CSR _SFR_MEM8(0x75) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0TS2 2 #define AMPCMP0 3 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 #define AMP1CSR _SFR_MEM8(0x76) #define AMP1TS0 0 #define AMP1TS1 1 #define AMP1TS2 2 #define AMPCMP1 3 #define AMP1G0 4 #define AMP1G1 5 #define AMP1IS 6 #define AMP1EN 7 #define AMP2CSR _SFR_MEM8(0x77) #define AMP2TS0 0 #define AMP2TS1 1 #define AMP2TS2 2 #define AMPCMP2 3 #define AMP2G0 4 #define AMP2G1 5 #define AMP2IS 6 #define AMP2EN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define AREFEN 5 #define ISRCEN 6 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define AMP0ND 3 #define AMP0PD 4 #define ACMP0D 5 #define AMP2PD 6 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define DACON _SFR_MEM8(0x90) #define DAEN 0 #define DAOE 1 #define DALA 2 #define DATS0 4 #define DATS1 5 #define DATS2 6 #define DAATE 7 #define DAC _SFR_MEM16(0x91) #define DACL _SFR_MEM8(0x91) #define DACL0 0 #define DACL1 1 #define DACL2 2 #define DACL3 3 #define DACL4 4 #define DACL5 5 #define DACL6 6 #define DACL7 7 #define DACH _SFR_MEM8(0x92) #define DACH0 0 #define DACH1 1 #define DACH2 2 #define DACH3 3 #define DACH4 4 #define DACH5 5 #define DACH6 6 #define DACH7 7 #define AC0CON _SFR_MEM8(0x94) #define AC0M0 0 #define AC0M1 1 #define AC0M2 2 #define ACCKSEL 3 #define AC0IS0 4 #define AC0IS1 5 #define AC0IE 6 #define AC0EN 7 #define AC1CON _SFR_MEM8(0x95) #define AC1M0 0 #define AC1M1 1 #define AC1M2 2 #define AC1ICE 3 #define AC1IS0 4 #define AC1IS1 5 #define AC1IE 6 #define AC1EN 7 #define AC2CON _SFR_MEM8(0x96) #define AC2M0 0 #define AC2M1 1 #define AC2M2 2 #define AC2IS0 4 #define AC2IS1 5 #define AC2IE 6 #define AC2EN 7 #define AC3CON _SFR_MEM8(0x97) #define AC3M0 0 #define AC3M1 1 #define AC3M2 2 #define AC3IS0 4 #define AC3IS1 5 #define AC3IE 6 #define AC3EN 7 #define LINCR _SFR_MEM8(0xC8) #define LCMD0 0 #define LCMD1 1 #define LCMD2 2 #define LENA 3 #define LCONF0 4 #define LCONF1 5 #define LIN13 6 #define LSWRES 7 #define LINSIR _SFR_MEM8(0xC9) #define LRXOK 0 #define LTXOK 1 #define LIDOK 2 #define LERR 3 #define LBUSY 4 #define LIDST0 5 #define LIDST1 6 #define LIDST2 7 #define LINENIR _SFR_MEM8(0xCA) #define LENRXOK 0 #define LENTXOK 1 #define LENIDOK 2 #define LENERR 3 #define LINERR _SFR_MEM8(0xCB) #define LBERR 0 #define LCERR 1 #define LPERR 2 #define LSERR 3 #define LFERR 4 #define LOVERR 5 #define LTOERR 6 #define LABORT 7 #define LINBTR _SFR_MEM8(0xCC) #define LBT0 0 #define LBT1 1 #define LBT2 2 #define LBT3 3 #define LBT4 4 #define LBT5 5 #define LDISR 7 #define LINBRR _SFR_MEM16(0xCD) #define LINBRRL _SFR_MEM8(0xCD) #define LDIV0 0 #define LDIV1 1 #define LDIV2 2 #define LDIV3 3 #define LDIV4 4 #define LDIV5 5 #define LDIV6 6 #define LDIV7 7 #define LINBRRH _SFR_MEM8(0xCE) #define LDIV8 0 #define LDIV9 1 #define LDIV10 2 #define LDIV11 3 #define LINDLR _SFR_MEM8(0xCF) #define LRXDL0 0 #define LRXDL1 1 #define LRXDL2 2 #define LRXDL3 3 #define LTXDL0 4 #define LTXDL1 5 #define LTXDL2 6 #define LTXDL3 7 #define LINIDR _SFR_MEM8(0xD0) #define LID0 0 #define LID1 1 #define LID2 2 #define LID3 3 #define LID4 4 #define LID5 5 #define LP0 6 #define LP1 7 #define LINSEL _SFR_MEM8(0xD1) #define LINDX0 0 #define LINDX1 1 #define LINDX2 2 #define LAINC 3 #define LINDAT _SFR_MEM8(0xD2) #define LDATA0 0 #define LDATA1 1 #define LDATA2 2 #define LDATA3 3 #define LDATA4 4 #define LDATA5 5 #define LDATA6 6 #define LDATA7 7 #define CANGCON _SFR_MEM8(0xD8) #define SWRES 0 #define ENASTB 1 #define TEST 2 #define LISTEN 3 #define SYNTTC 4 #define TTC 5 #define OVRQ 6 #define ABRQ 7 #define CANGSTA _SFR_MEM8(0xD9) #define ERRP 0 #define BOFF 1 #define ENFG 2 #define RXBSY 3 #define TXBSY 4 #define OVFG 6 #define CANGIT _SFR_MEM8(0xDA) #define AERG 0 #define FERG 1 #define CERG 2 #define SERG 3 #define BXOK 4 #define OVRTIM 5 #define BOFFIT 6 #define CANIT 7 #define CANGIE _SFR_MEM8(0xDB) #define ENOVRT 0 #define ENERG 1 #define ENBX 2 #define ENERR 3 #define ENTX 4 #define ENRX 5 #define ENBOFF 6 #define ENIT 7 #define CANEN2 _SFR_MEM8(0xDC) #define ENMOB0 0 #define ENMOB1 1 #define ENMOB2 2 #define ENMOB3 3 #define ENMOB4 4 #define ENMOB5 5 #define CANEN1 _SFR_MEM8(0xDD) #define CANIE2 _SFR_MEM8(0xDE) #define IEMOB0 0 #define IEMOB1 1 #define IEMOB2 2 #define IEMOB3 3 #define IEMOB4 4 #define IEMOB5 5 #define CANIE1 _SFR_MEM8(0xDF) /* RegDef: CAN Status Interrupt MOb Register*/ #define CANSIT _SFR_MEM16(0xE0) #define CANSIT2 _SFR_MEM8(0xE0) #define SIT0 0 #define SIT1 1 #define SIT2 2 #define SIT3 3 #define SIT4 4 #define SIT5 5 #define CANSIT1 _SFR_MEM8(0xE1) #define CANBT1 _SFR_MEM8(0xE2) #define BRP0 1 #define BRP1 2 #define BRP2 3 #define BRP3 4 #define BRP4 5 #define BRP5 6 #define CANBT2 _SFR_MEM8(0xE3) #define PRS0 1 #define PRS1 2 #define PRS2 3 #define SJW0 5 #define SJW1 6 #define CANBT3 _SFR_MEM8(0xE4) #define SMP 0 #define PHS10 1 #define PHS11 2 #define PHS12 3 #define PHS20 4 #define PHS21 5 #define PHS22 6 #define CANTCON _SFR_MEM8(0xE5) #define TPRSC0 0 #define TPRSC1 1 #define TPRSC2 2 #define TPRSC3 3 #define TPRSC4 4 #define TPRSC5 5 #define TPRSC6 6 #define TPRSC7 7 #define CANTIM _SFR_MEM16(0xE6) #define CANTIML _SFR_MEM8(0xE6) #define CANTIM0 0 #define CANTIM1 1 #define CANTIM2 2 #define CANTIM3 3 #define CANTIM4 4 #define CANTIM5 5 #define CANTIM6 6 #define CANTIM7 7 #define CANTIMH _SFR_MEM8(0xE7) #define CANTIM8 0 #define CANTIM9 1 #define CANTIM10 2 #define CANTIM11 3 #define CANTIM12 4 #define CANTIM13 5 #define CANTIM14 6 #define CANTIM15 7 #define CANTTC _SFR_MEM16(0xE8) #define CANTTCL _SFR_MEM8(0xE8) #define TIMTCC0 0 #define TIMTCC1 1 #define TIMTCC2 2 #define TIMTCC3 3 #define TIMTCC4 4 #define TIMTCC5 5 #define TIMTCC6 6 #define TIMTCC7 7 #define CANTTCH _SFR_MEM8(0xE9) #define TIMTCC8 0 #define TIMTCC9 1 #define TIMTCC10 2 #define TIMTCC11 3 #define TIMTCC12 4 #define TIMTCC13 5 #define TIMTCC14 6 #define TIMTCC15 7 #define CANTEC _SFR_MEM8(0xEA) #define TEC0 0 #define TEC1 1 #define TEC2 2 #define TEC3 3 #define TEC4 4 #define TEC5 5 #define TEC6 6 #define TEC7 7 #define CANREC _SFR_MEM8(0xEB) #define REC0 0 #define REC1 1 #define REC2 2 #define REC3 3 #define REC4 4 #define REC5 5 #define REC6 6 #define REC7 7 #define CANHPMOB _SFR_MEM8(0xEC) #define CGP0 0 #define CGP1 1 #define CGP2 2 #define CGP3 3 #define HPMOB0 4 #define HPMOB1 5 #define HPMOB2 6 #define HPMOB3 7 #define CANPAGE _SFR_MEM8(0xED) #define INDX0 0 #define INDX1 1 #define INDX2 2 #define AINC 3 #define MOBNB0 4 #define MOBNB1 5 #define MOBNB2 6 #define MOBNB3 7 #define CANSTMOB _SFR_MEM8(0xEE) #define AERR 0 #define FERR 1 #define CERR 2 #define SERR 3 #define BERR 4 #define RXOK 5 #define TXOK 6 #define DLCW 7 #define CANCDMOB _SFR_MEM8(0xEF) #define DLC0 0 #define DLC1 1 #define DLC2 2 #define DLC3 3 #define IDE 4 #define RPLV 5 #define CONMOB0 6 #define CONMOB1 7 /* RegDef: CAN Identifier Tag Registers*/ #define CANIDT _SFR_MEM32(0xF0) #define CANIDT4 _SFR_MEM8(0xF0) #define RB0TAG 0 #define RB1TAG 1 #define RTRTAG 2 #define IDT0 3 #define IDT1 4 #define IDT2 5 #define IDT3 6 #define IDT4 7 #define CANIDT3 _SFR_MEM8(0xF1) #define IDT5 0 #define IDT6 1 #define IDT7 2 #define IDT8 3 #define IDT9 4 #define IDT10 5 #define IDT11 6 #define IDT12 7 #define CANIDT2 _SFR_MEM8(0xF2) #define IDT13 0 #define IDT14 1 #define IDT15 2 #define IDT16 3 #define IDT17 4 #define IDT18 5 #define IDT19 6 #define IDT20 7 #define CANIDT1 _SFR_MEM8(0xF3) #define IDT21 0 #define IDT22 1 #define IDT23 2 #define IDT24 3 #define IDT25 4 #define IDT26 5 #define IDT27 6 #define IDT28 7 /* RegDef: CAN Identifier Mask Registers */ #define CANIDM _SFR_MEM32(0xF4) #define CANIDM4 _SFR_MEM8(0xF4) #define IDEMSK 0 #define RTRMSK 2 #define IDMSK0 3 #define IDMSK1 4 #define IDMSK2 5 #define IDMSK3 6 #define IDMSK4 7 #define CANIDM3 _SFR_MEM8(0xF5) #define IDMSK5 0 #define IDMSK6 1 #define IDMSK7 2 #define IDMSK8 3 #define IDMSK9 4 #define IDMSK10 5 #define IDMSK11 6 #define IDMSK12 7 #define CANIDM2 _SFR_MEM8(0xF6) #define IDMSK13 0 #define IDMSK14 1 #define IDMSK15 2 #define IDMSK16 3 #define IDMSK17 4 #define IDMSK18 5 #define IDMSK19 6 #define IDMSK20 7 #define CANIDM1 _SFR_MEM8(0xF7) #define IDMSK21 0 #define IDMSK22 1 #define IDMSK23 2 #define IDMSK24 3 #define IDMSK25 4 #define IDMSK26 5 #define IDMSK27 6 #define IDMSK28 7 #define CANSTM _SFR_MEM16(0xF8) #define CANSTML _SFR_MEM8(0xF8) #define TIMSTM0 0 #define TIMSTM1 1 #define TIMSTM2 2 #define TIMSTM3 3 #define TIMSTM4 4 #define TIMSTM5 5 #define TIMSTM6 6 #define TIMSTM7 7 #define CANSTMH _SFR_MEM8(0xF9) #define TIMSTM8 0 #define TIMSTM9 1 #define TIMSTM10 2 #define TIMSTM11 3 #define TIMSTM12 4 #define TIMSTM13 5 #define TIMSTM14 6 #define TIMSTM15 7 #define CANMSG _SFR_MEM8(0xFA) #define MSG0 0 #define MSG1 1 #define MSG2 2 #define MSG3 3 #define MSG4 4 #define MSG5 5 #define MSG6 6 #define MSG7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define ANACOMP0_vect_num 1 #define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ #define ANACOMP1_vect_num 2 #define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ #define ANACOMP2_vect_num 3 #define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ #define ANACOMP3_vect_num 4 #define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ #define PSC_FAULT_vect_num 5 #define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ #define PSC_EC_vect_num 6 #define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ #define INT0_vect_num 7 #define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ #define INT1_vect_num 8 #define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ #define INT2_vect_num 9 #define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ #define INT3_vect_num 10 #define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 14 #define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 15 #define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 16 #define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ #define CAN_INT_vect_num 18 #define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ #define CAN_TOVF_vect_num 19 #define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ #define LIN_TC_vect_num 20 #define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ #define LIN_ERR_vect_num 21 #define LIN_ERR_vect _VECTOR(21) /* LIN Error */ #define PCINT0_vect_num 22 #define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 23 #define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 24 #define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ #define PCINT3_vect_num 25 #define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ #define SPI_STC_vect_num 26 #define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ #define ADC_vect_num 27 #define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ #define WDT_vect_num 28 #define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ #define EE_READY_vect_num 29 #define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ #define SPM_READY_vect_num 30 #define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (31 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x0100) #define RAMSIZE (2048) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (0x0) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x3FF) #define E2PAGESIZE (4) #define FLASHEND (0x7FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ #define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ #define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ #define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x86 #endif /* _AVR_ATmega32C1_H_ */ avr-libc-1.8.0.orig/include/avr/parity.h0000644000000000000000000000335211732702554014751 0ustar /* Copyright (c) 2005 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: parity.h 933 2005-11-05 22:23:16Z joerg_wunsch $ */ #ifndef _AVR_PARITY_H_ #define _AVR_PARITY_H_ #warning "This file has been moved to ." #include #endif /* _AVR_PARITY_H_ */ avr-libc-1.8.0.orig/include/avr/fuse.h0000644000000000000000000002177011732702554014407 0ustar /* Copyright (c) 2007, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fuse.h 2107 2010-03-20 18:00:47Z arcanum $ */ /* avr/fuse.h - Fuse API */ #ifndef _AVR_FUSE_H_ #define _AVR_FUSE_H_ 1 /* This file must be explicitly included by . */ #if !defined(_AVR_IO_H_) #error "You must #include and not by itself." #endif /** \file */ /** \defgroup avr_fuse : Fuse Support \par Introduction The Fuse API allows a user to specify the fuse settings for the specific AVR device they are compiling for. These fuse settings will be placed in a special section in the ELF output file, after linking. Programming tools can take advantage of the fuse information embedded in the ELF file, by extracting this information and determining if the fuses need to be programmed before programming the Flash and EEPROM memories. This also allows a single ELF file to contain all the information needed to program an AVR. To use the Fuse API, include the header file, which in turn automatically includes the individual I/O header file and the file. These other two files provides everything necessary to set the AVR fuses. \par Fuse API Each I/O header file must define the FUSE_MEMORY_SIZE macro which is defined to the number of fuse bytes that exist in the AVR device. A new type, __fuse_t, is defined as a structure. The number of fields in this structure are determined by the number of fuse bytes in the FUSE_MEMORY_SIZE macro. If FUSE_MEMORY_SIZE == 1, there is only a single field: byte, of type unsigned char. If FUSE_MEMORY_SIZE == 2, there are two fields: low, and high, of type unsigned char. If FUSE_MEMORY_SIZE == 3, there are three fields: low, high, and extended, of type unsigned char. If FUSE_MEMORY_SIZE > 3, there is a single field: byte, which is an array of unsigned char with the size of the array being FUSE_MEMORY_SIZE. A convenience macro, FUSEMEM, is defined as a GCC attribute for a custom-named section of ".fuse". A convenience macro, FUSES, is defined that declares a variable, __fuse, of type __fuse_t with the attribute defined by FUSEMEM. This variable allows the end user to easily set the fuse data. \note If a device-specific I/O header file has previously defined FUSEMEM, then FUSEMEM is not redefined. If a device-specific I/O header file has previously defined FUSES, then FUSES is not redefined. Each AVR device I/O header file has a set of defined macros which specify the actual fuse bits available on that device. The AVR fuses have inverted values, logical 1 for an unprogrammed (disabled) bit and logical 0 for a programmed (enabled) bit. The defined macros for each individual fuse bit represent this in their definition by a bit-wise inversion of a mask. For example, the FUSE_EESAVE fuse in the ATmega128 is defined as: \code #define FUSE_EESAVE ~_BV(3) \endcode \note The _BV macro creates a bit mask from a bit number. It is then inverted to represent logical values for a fuse memory byte. To combine the fuse bits macros together to represent a whole fuse byte, use the bitwise AND operator, like so: \code (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN) \endcode Each device I/O header file also defines macros that provide default values for each fuse byte that is available. LFUSE_DEFAULT is defined for a Low Fuse byte. HFUSE_DEFAULT is defined for a High Fuse byte. EFUSE_DEFAULT is defined for an Extended Fuse byte. If FUSE_MEMORY_SIZE > 3, then the I/O header file defines macros that provide default values for each fuse byte like so: FUSE0_DEFAULT FUSE1_DEFAULT FUSE2_DEFAULT FUSE3_DEFAULT FUSE4_DEFAULT .... \par API Usage Example Putting all of this together is easy. Using C99's designated initializers: \code #include FUSES = { .low = LFUSE_DEFAULT, .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), .extended = EFUSE_DEFAULT, }; int main(void) { return 0; } \endcode Or, using the variable directly instead of the FUSES macro, \code #include __fuse_t __fuse __attribute__((section (".fuse"))) = { .low = LFUSE_DEFAULT, .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), .extended = EFUSE_DEFAULT, }; int main(void) { return 0; } \endcode If you are compiling in C++, you cannot use the designated intializers so you must do: \code #include FUSES = { LFUSE_DEFAULT, // .low (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), // .high EFUSE_DEFAULT, // .extended }; int main(void) { return 0; } \endcode However there are a number of caveats that you need to be aware of to use this API properly. Be sure to include to get all of the definitions for the API. The FUSES macro defines a global variable to store the fuse data. This variable is assigned to its own linker section. Assign the desired fuse values immediately in the variable initialization. The .fuse section in the ELF file will get its values from the initial variable assignment ONLY. This means that you can NOT assign values to this variable in functions and the new values will not be put into the ELF .fuse section. The global variable is declared in the FUSES macro has two leading underscores, which means that it is reserved for the "implementation", meaning the library, so it will not conflict with a user-named variable. You must initialize ALL fields in the __fuse_t structure. This is because the fuse bits in all bytes default to a logical 1, meaning unprogrammed. Normal uninitialized data defaults to all locgial zeros. So it is vital that all fuse bytes are initialized, even with default data. If they are not, then the fuse bits may not programmed to the desired settings. Be sure to have the -mmcu=device flag in your compile command line and your linker command line to have the correct device selected and to have the correct I/O header file included when you include . You can print out the contents of the .fuse section in the ELF file by using this command line: \code avr-objdump -s -j .fuse \endcode The section contents shows the address on the left, then the data going from lower address to a higher address, left to right. */ #ifndef __ASSEMBLER__ #ifndef FUSEMEM #define FUSEMEM __attribute__((section (".fuse"))) #endif #if FUSE_MEMORY_SIZE > 3 typedef struct { unsigned char byte[FUSE_MEMORY_SIZE]; } __fuse_t; #elif FUSE_MEMORY_SIZE == 3 typedef struct { unsigned char low; unsigned char high; unsigned char extended; } __fuse_t; #elif FUSE_MEMORY_SIZE == 2 typedef struct { unsigned char low; unsigned char high; } __fuse_t; #elif FUSE_MEMORY_SIZE == 1 typedef struct { unsigned char byte; } __fuse_t; #endif #if !defined(FUSES) #if defined(__AVR_XMEGA__) #define FUSES NVM_FUSES_t __fuse FUSEMEM #else #define FUSES __fuse_t __fuse FUSEMEM #endif #endif #endif /* !__ASSEMBLER__ */ #endif /* _AVR_FUSE_H_ */ avr-libc-1.8.0.orig/include/avr/ioa6289.h0000644000000000000000000004234411732702554014546 0ustar /* Copyright (c) 2008 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ioa6289.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/ioa6289.h - definitions for ATA6289 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "ioa6289.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATA6289_H_ #define _AVR_ATA6289_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define DDRC _SFR_IO8(0x07) #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define CMCR _SFR_IO8(0x0F) #define CMM0 0 #define CMM1 1 #define SRCD 2 #define CMONEN 3 #define CCS 4 #define ECINS 5 #define CMCCE 7 #define CMSR _SFR_IO8(0x10) #define ECF 0 #define T2CRA _SFR_IO8(0x11) #define T2OTM 0 #define T2CTM 1 #define T2CR 2 #define T2CRM 3 #define T2CPRM 4 #define T2ICS 5 #define T2TS 6 #define T2E 7 #define T2CRB _SFR_IO8(0x12) #define T2SCE 0 #define T3CRA _SFR_IO8(0x14) #define T3AC 0 #define T3SCE 1 #define T3CR 2 #define T3TS 6 #define T3E 7 #define VMCSR _SFR_IO8(0x16) #define VMEN 0 #define VMLS0 1 #define VMLS1 2 #define VMLS2 3 #define VMIM 4 #define VMF 5 #define BODPD 6 #define BODLS 7 #define PCIFR _SFR_IO8(0x17) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define LFFR _SFR_IO8(0x18) #define LFWPF 0 #define LFBF 1 #define LFEDF 2 #define LFRF 3 #define SSFR _SFR_IO8(0x19) #define MSENF 0 #define MSENO 1 #define T10IFR _SFR_IO8(0x1A) #define T0F 0 #define T1F 1 #define T2IFR _SFR_IO8(0x1B) #define T2OFF 0 #define T2COF 1 #define T2ICF 2 #define T2RXF 3 #define T2TXF 4 #define T2TCF 5 #define T3IFR _SFR_IO8(0x1C) #define T3OFF 0 #define T3COAF 1 #define T3COBF 2 #define T3ICF 3 #define EIFR _SFR_IO8(0x1D) #define INTF0 0 #define INTF1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define PCICR _SFR_IO8(0x23) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define EIMSK _SFR_IO8(0x24) #define INT0 0 #define INT1 1 #define SVCR _SFR_IO8(0x27) #define SVCS0 0 #define SVCS1 1 #define SVCS2 2 #define SVCS3 3 #define SVCS4 4 #define SCR _SFR_IO8(0x28) #define SMS 0 #define SEN0 1 #define SEN1 2 #define SMEN 3 #define SCCR _SFR_IO8(0x29) #define SRCC0 0 #define SRCC1 1 #define SCCS0 2 #define SCCS1 3 #define SCCS2 4 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define T2MDR _SFR_IO8(0x2F) #define T2MDR0 0 #define T2MDR1 1 #define T2MDR2 2 #define T2MDR3 3 #define T2MDR4 4 #define T2MDR5 5 #define T2MDR6 6 #define T2MDR7 7 #define LFRR _SFR_IO8(0x30) #define LFRR0 0 #define LFRR1 1 #define LFRR2 2 #define LFRR3 3 #define LFRR4 4 #define LFRR5 5 #define LFRR6 6 #define LFCDR _SFR_IO8(0x32) #define LFDO 0 #define LFRST 6 #define LFSCE 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define TSRF 5 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define LFRB _SFR_IO8(0x36) #define LFRB0 0 #define LFRB1 1 #define LFRB2 2 #define LFRB3 3 #define LFRB4 4 #define LFRB5 5 #define LFRB6 6 #define LFRB7 7 #define SPMCSR _SFR_IO8(0x37) #define SELFPRGEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define T1CR _SFR_IO8(0x38) #define T1PS0 0 #define T1PS1 1 #define T1PS2 2 #define T1CS0 3 #define T1CS1 4 #define T1CS2 5 #define T1IE 7 #define T0CR _SFR_IO8(0x39) #define T0PAS0 0 #define T0PAS1 1 #define T0PAS2 2 #define T0IE 3 #define T0PR 4 #define T0PBS0 5 #define T0PBS1 6 #define T0PBS2 7 #define CMIMR _SFR_IO8(0x3B) #define ECIE 0 #define CLKPR _SFR_IO8(0x3C) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLTPS0 3 #define CLTPS1 4 #define CLTPS2 5 #define CLPCE 7 #define WDTCR _SFR_MEM8(0x60) #define WDPS0 0 #define WDPS1 1 #define WDPS2 2 #define WDE 3 #define WDCE 4 #define SIMSK _SFR_MEM8(0x61) #define MSIE 0 #define TSCR _SFR_MEM8(0x64) #define TSSD 0 #define SRCCAL _SFR_MEM8(0x65) #define SCAL0 0 #define SCAL1 1 #define SCAL2 2 #define SCAL3 3 #define SCAL4 4 #define SCAL5 5 #define SCAL6 6 #define SCAL7 7 #define FRCCAL _SFR_MEM8(0x66) #define FCAL0 0 #define FCAL1 1 #define FCAL2 2 #define FCAL3 3 #define FCAL4 4 #define FCAL5 5 #define FCAL6 6 #define FCAL7 7 #define MSVCAL _SFR_MEM8(0x67) #define VRCAL0 0 #define VRCAL1 1 #define VRCAL2 2 #define VRCAL3 3 #define VRCAL4 4 #define VRCAL5 5 #define VRCAL6 6 #define VRCAL7 7 #define BGCAL _SFR_MEM8(0x68) #define BGCAL0 0 #define BGCAL1 1 #define BGCAL2 2 #define BGCAL3 3 #define BGCAL4 4 #define BGCAL5 5 #define BGCAL6 6 #define BGCAL7 7 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK0 _SFR_MEM8(0x6A) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6B) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCMSK2 _SFR_MEM8(0x6C) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define T2ICR _SFR_MEM16(0x6E) #define T2ICRL _SFR_MEM8(0x6E) #define T2ICRL0 0 #define T2ICRL1 1 #define T2ICRL2 2 #define T2ICRL3 3 #define T2ICRL4 4 #define T2ICRL5 5 #define T2ICRL6 6 #define T2ICRL7 7 #define T2ICRH _SFR_MEM8(0x6F) #define T2ICRH0 0 #define T2ICRH1 1 #define T2ICRH2 2 #define T2ICRH3 3 #define T2ICRH4 4 #define T2ICRH5 5 #define T2ICRH6 6 #define T2ICRH7 7 #define T2COR _SFR_MEM16(0x70) #define T2CORL _SFR_MEM8(0x70) #define T2CORL0 0 #define T2CORL1 1 #define T2CORL2 2 #define T2CORL3 3 #define T2CORL4 4 #define T2CORL5 5 #define T2CORL6 6 #define T2CORL7 7 #define T2CORH _SFR_MEM8(0x71) #define T2CORH0 0 #define T2CORH1 1 #define T2CORH2 2 #define T2CORH3 3 #define T2CORH4 4 #define T2CORH5 5 #define T2CORH6 6 #define T2CORH7 7 #define T2MRA _SFR_MEM8(0x72) #define T2CS0 0 #define T2CS1 1 #define T2CS2 2 #define T2CE0 3 #define T2CE1 4 #define T2CNC 5 #define T2TP0 6 #define T2TP1 7 #define T2MRB _SFR_MEM8(0x73) #define T2M0 0 #define T2M1 1 #define T2M2 2 #define T2M3 3 #define T2TOP 4 #define T2CPOL 6 #define T2SSIE 7 #define T2IMR _SFR_MEM8(0x74) #define T2OIM 0 #define T2CIM 1 #define T2CPIM 2 #define T2RXIM 3 #define T2TXIM 4 #define T2TCIM 5 #define T3ICR _SFR_MEM16(0x76) #define T3ICRL _SFR_MEM8(0x76) #define T3ICRL0 0 #define T3ICRL1 1 #define T3ICRL2 2 #define T3ICRL3 3 #define T3ICRL4 4 #define T3ICRL5 5 #define T3ICRL6 6 #define T3ICRL7 7 #define T3ICRH _SFR_MEM8(0x77) #define T3ICRH0 0 #define T3ICRH1 1 #define T3ICRH2 2 #define T3ICRH3 3 #define T3ICRH4 4 #define T3ICRH5 5 #define T3ICRH6 6 #define T3ICRH7 7 #define T3CORA _SFR_MEM16(0x78) #define T3CORAL _SFR_MEM8(0x78) #define T3CORAL0 0 #define T3CORAL1 1 #define T3CORAL2 2 #define T3CORAL3 3 #define T3CORAL4 4 #define T3CORAL5 5 #define T3CORAL6 6 #define T3CORAL7 7 #define T3CORAH _SFR_MEM8(0x79) #define T3CORAH0 0 #define T3CORAH1 1 #define T3CORAH2 2 #define T3CORAH3 3 #define T3CORAH4 4 #define T3CORAH5 5 #define T3CORAH6 6 #define T3CORAH7 7 #define T3CORB _SFR_MEM16(0x7A) #define T3CORBL _SFR_MEM8(0x7A) #define T3CORBL0 0 #define T3CORBL1 1 #define T3CORBL2 2 #define T3CORBL3 3 #define T3CORBL4 4 #define T3CORBL5 5 #define T3CORBL6 6 #define T3CORBL7 7 #define T3CORBH _SFR_MEM8(0x7B) #define T3CORBH0 0 #define T3CORBH1 1 #define T3CORBH2 2 #define T3CORBH3 3 #define T3CORBH4 4 #define T3CORBH5 5 #define T3CORBH6 6 #define T3CORBH7 7 #define T3MRA _SFR_MEM8(0x7C) #define T3CS0 0 #define T3CS1 1 #define T3CS2 2 #define T3CE0 3 #define T3CE1 4 #define T3CNC 5 #define T3ICS0 6 #define T3ICS1 7 #define T3MRB _SFR_MEM8(0x7D) #define T3M0 0 #define T3M1 1 #define T3M2 2 #define T3TOP 4 #define T3CRB _SFR_MEM8(0x7E) #define T3CTMA 0 #define T3SAMA 1 #define T3CRMA 2 #define T3CTMB 3 #define T3SAMB 4 #define T3CRMB 5 #define T3CPRM 6 #define T3IMR _SFR_MEM8(0x7F) #define T3OIM 0 #define T3CAIM 1 #define T3CBIM 2 #define T3CPIM 3 #define LFIMR _SFR_MEM8(0x81) #define LFWIM 0 #define LFBIM 1 #define LFEIM 2 #define LFRCR _SFR_MEM8(0x82) #define LFEN 0 #define LFBM 1 #define LFWM0 2 #define LFWM1 3 #define LFRSS 4 #define LFCS0 5 #define LFCS1 6 #define LFCS2 7 #define LFHCR _SFR_MEM8(0x83) #define LFHCR0 0 #define LFHCR1 1 #define LFHCR2 2 #define LFHCR3 3 #define LFHCR4 4 #define LFHCR5 5 #define LFHCR6 6 #define LFIDC _SFR_MEM16(0x84) #define LFIDCL _SFR_MEM8(0x84) #define LFIDCL_0 0 #define LFIDCL_1 1 #define LFIDCL_2 2 #define LFIDCL_3 3 #define LFIDCL_4 4 #define LFIDCL_5 5 #define LFIDCL_6 6 #define LFIDCL_7 7 #define LFIDCH _SFR_MEM8(0x85) #define LFIDCH_8 0 #define LFIDCH_9 1 #define LFIDCH_10 2 #define LFIDCH_11 3 #define LFIDCH_12 4 #define LFIDCH_13 5 #define LFIDCH_14 6 #define LFIDCH_15 7 #define LFCAL _SFR_MEM16(0x86) #define LFCALL _SFR_MEM8(0x86) #define LFCAL_00 0 #define LFCAL_01 1 #define LFCAL_02 2 #define LFCAL_03 3 #define LFCAL_04 4 #define LFCAL_05 5 #define LFCAL_06 6 #define LFCAL_07 7 #define LFCALH _SFR_MEM8(0x87) #define LFCAL_08 0 #define LFCAL_09 1 #define LFCAL_10 2 #define LFCAL_11 3 #define LFCAL_12 4 #define LFCAL_13 5 #define LFCAL_14 6 #define LFCAL_15 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 5 #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 2 */ #define INTVM_vect_num 6 #define INTVM_vect _VECTOR(6) /* Voltage Monitor Interrupt */ #define SENINT_vect_num 7 #define SENINT_vect _VECTOR(7) /* Sensor Interface Interrupt */ #define INTT0_vect_num 8 #define INTT0_vect _VECTOR(8) /* Timer0 Interval Interrupt */ #define LFWP_vect_num 9 #define LFWP_vect _VECTOR(9) /* LF-Receiver Wake-up Interrupt */ #define T3CAP_vect_num 10 #define T3CAP_vect _VECTOR(10) /* Timer/Counter3 Capture Event */ #define T3COMA_vect_num 11 #define T3COMA_vect _VECTOR(11) /* Timer/Counter3 Compare Match A */ #define T3COMB_vect_num 12 #define T3COMB_vect _VECTOR(12) /* Timer/Counter3 Compare Match B */ #define T3OVF_vect_num 13 #define T3OVF_vect _VECTOR(13) /* Timer/Counter3 Overflow */ #define T2CAP_vect_num 14 #define T2CAP_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ #define T2COM_vect_num 15 #define T2COM_vect _VECTOR(15) /* Timer/Counter2 Compare Match */ #define T2OVF_vect_num 16 #define T2OVF_vect _VECTOR(16) /* Timer/Counter2 Overflow */ #define SPISTC_vect_num 17 #define SPISTC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ #define LFRXB_vect_num 18 #define LFRXB_vect _VECTOR(18) /* LF Receive Buffer Interrupt */ #define INTT1_vect_num 19 #define INTT1_vect _VECTOR(19) /* Timer1 Interval Interrupt */ #define T2RXB_vect_num 20 #define T2RXB_vect _VECTOR(20) /* Timer2 SSI Receive Buffer Interrupt */ #define T2TXB_vect_num 21 #define T2TXB_vect _VECTOR(21) /* Timer2 SSI Transmit Buffer Interrupt */ #define T2TXC_vect_num 22 #define T2TXC_vect _VECTOR(22) /* Timer2 SSI Transmit Complete Interrupt */ #define LFREOB_vect_num 23 #define LFREOB_vect _VECTOR(23) /* LF-Receiver End of Burst Interrupt */ #define EXCM_vect_num 24 #define EXCM_vect _VECTOR(24) /* External Input Clock break down Interrupt */ #define EEREADY_vect_num 25 #define EEREADY_vect _VECTOR(25) /* EEPROM Ready Interrupt */ #define SPM_RDY_vect_num 26 #define SPM_RDY_vect _VECTOR(26) /* Store Program Memory Ready */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (27 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x100) #define RAMSIZE (512) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND RAMEND #define E2END (320 - 1) #define E2PAGESIZE (4) #define FLASHEND (8192 - 1) /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_TSRDI ~_BV(0) /* Disable Temperature shutdown Reset */ #define FUSE_BODEN ~_BV(1) /* Enable Brown-out detection */ #define FUSE_FRCFS ~_BV(2) /* Fast RC-Oscillator Frequency select */ #define FUSE_WDRCON ~_BV(3) /* Enable Watchdog RC-Oscillator */ #define FUSE_SUT0 ~_BV(4) /* Select start-up time */ #define FUSE_SUT1 ~_BV(5) /* Select start-up time */ #define FUSE_CKOUT ~_BV(6) /* Clock output */ #define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN) /* High Fuse Byte */ #define FUSE_BOOTRST ~_BV(0) /* Select reset vector */ #define FUSE_BOOTSZ0 ~_BV(1) /* Boot size select */ #define FUSE_BOOTSZ1 ~_BV(2) /* Boot size select */ #define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON ~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN ~_BV(6) /* debugWIRE Enable */ #define FUSE_EELOCK ~_BV(7) /* Upper EEPROM Locked (disabled) */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x82 #endif /* _AVR_ATA6289_H_ */ avr-libc-1.8.0.orig/include/avr/iom32hvbrevb.h0000755000000000000000000004464511732702554015766 0ustar /* Copyright (c) 2007, 2011 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom32hvbrevb.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/iom32hvbrevb.h - definitions for ATmega32HVB revision B. */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32hvbrevb.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOM32HVBREVB_H_ #define _AVR_IOM32HVBREVB_H_ 1 /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 3 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 3 #define OSICSR _SFR_IO8(0x17) #define OSIEN 0 #define OSIST 1 #define OSISEL0 4 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define ICS0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define TCNT0 _SFR_IO16(0x26) #define TCNT0L _SFR_IO8(0x26) #define TCNT0L0 0 #define TCNT0L1 1 #define TCNT0L2 2 #define TCNT0L3 3 #define TCNT0L4 4 #define TCNT0L5 5 #define TCNT0L6 6 #define TCNT0L7 7 #define TCNT0H _SFR_IO8(0x27) #define TCNT0H0 0 #define TCNT0H1 1 #define TCNT0H2 2 #define TCNT0H3 3 #define TCNT0H4 4 #define TCNT0H5 5 #define TCNT0H6 6 #define TCNT0H7 7 #define OCR0A _SFR_IO8(0x28) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0B _SFR_IO8(0x29) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BODRF 2 #define WDRF 3 #define OCDRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define CKOE 5 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define LBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRVADC 0 #define PRTIM0 1 #define PRTIM1 2 #define PRSPI 3 #define PRVRM 5 #define PRTWI 6 #define FOSCCAL _SFR_MEM8(0x66) #define FCAL0 0 #define FCAL1 1 #define FCAL2 2 #define FCAL3 3 #define FCAL4 4 #define FCAL5 5 #define FCAL6 6 #define FCAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT4 0 #define PCINT5 1 #define PCINT6 2 #define PCINT7 3 #define PCINT8 4 #define PCINT9 5 #define PCINT10 6 #define PCINT11 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 3 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 3 #define VADC _SFR_MEM16(0x78) #define VADCL _SFR_MEM8(0x78) #define VADC0 0 #define VADC1 1 #define VADC2 2 #define VADC3 3 #define VADC4 4 #define VADC5 5 #define VADC6 6 #define VADC7 7 #define VADCH _SFR_MEM8(0x79) #define VADC8 0 #define VADC9 1 #define VADC10 2 #define VADC11 3 #define VADCSR _SFR_MEM8(0x7A) #define VADCCIE 0 #define VADCCIF 1 #define VADSC 2 #define VADEN 3 #define VADMUX _SFR_MEM8(0x7C) #define VADMUX0 0 #define VADMUX1 1 #define VADMUX2 2 #define VADMUX3 3 #define DIDR0 _SFR_MEM8(0x7E) #define PA0DID 0 #define PA1DID 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define ICS1 3 #define ICES1 4 #define ICNC1 5 #define ICEN1 6 #define TCW1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define OCR1A _SFR_MEM8(0x88) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define OCR1B _SFR_MEM8(0x89) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 0 #define TWAM1 1 #define TWAM2 2 #define TWAM3 3 #define TWAM4 4 #define TWAM5 5 #define TWAM6 6 #define TWBCSR _SFR_MEM8(0xBE) #define TWBCIP 0 #define TWBDT0 1 #define TWBDT1 2 #define TWBCIE 6 #define TWBCIF 7 #define ROCR _SFR_MEM8(0xC8) #define ROCWIE 0 #define ROCWIF 1 #define ROCD 4 #define ROCS 7 #define BGCCR _SFR_MEM8(0xD0) #define BGCC0 0 #define BGCC1 1 #define BGCC2 2 #define BGCC3 3 #define BGCC4 4 #define BGCC5 5 #define BGCRR _SFR_MEM8(0xD1) #define BGCR0 0 #define BGCR1 1 #define BGCR2 2 #define BGCR3 3 #define BGCR4 4 #define BGCR5 5 #define BGCR6 6 #define BGCR7 7 #define BGCSR _SFR_MEM8(0xD2) #define BGSCDIE 0 #define BGSCDIF 1 #define BGSCDE 4 #define BGD 5 #define CHGDCSR _SFR_MEM8(0xD4) #define CHGDIE 0 #define CHGDIF 1 #define CHGDISC0 2 #define CHGDISC1 3 #define BATTPVL 4 #define CADAC _SFR_MEM32(0xE0) #define CADAC0 _SFR_MEM8(0xE0) #define CADAC00 0 #define CADAC01 1 #define CADAC02 2 #define CADAC03 3 #define CADAC04 4 #define CADAC05 5 #define CADAC06 6 #define CADAC07 7 #define CADAC1 _SFR_MEM8(0xE1) #define CADAC08 0 #define CADAC09 1 #define CADAC10 2 #define CADAC11 3 #define CADAC12 4 #define CADAC13 5 #define CADAC14 6 #define CADAC15 7 #define CADAC2 _SFR_MEM8(0xE2) #define CADAC16 0 #define CADAC17 1 #define CADAC18 2 #define CADAC19 3 #define CADAC20 4 #define CADAC21 5 #define CADAC22 6 #define CADAC23 7 #define CADAC3 _SFR_MEM8(0xE3) #define CADAC24 0 #define CADAC25 1 #define CADAC26 2 #define CADAC27 3 #define CADAC28 4 #define CADAC29 5 #define CADAC30 6 #define CADAC31 7 #define CADIC _SFR_MEM16(0xE4) #define CADICL _SFR_MEM8(0xE4) #define CADICL0 0 #define CADICL1 1 #define CADICL2 2 #define CADICL3 3 #define CADICL4 4 #define CADICL5 5 #define CADICL6 6 #define CADICL7 7 #define CADICH _SFR_MEM8(0xE5) #define CADICH0 0 #define CADICH1 1 #define CADICH2 2 #define CADICH3 3 #define CADICH4 4 #define CADICH5 5 #define CADICH6 6 #define CADICH7 7 #define CADCSRA _SFR_MEM8(0xE6) #define CADSE 0 #define CADSI0 1 #define CADSI1 2 #define CADAS0 3 #define CADAS1 4 #define CADUB 5 #define CADPOL 6 #define CADEN 7 #define CADCSRB _SFR_MEM8(0xE7) #define CADICIF 0 #define CADRCIF 1 #define CADACIF 2 #define CADICIE 4 #define CADRCIE 5 #define CADACIE 6 #define CADCSRC _SFR_MEM8(0xE8) #define CADVSE 0 #define CADRCC _SFR_MEM8(0xE9) #define CADRCC0 0 #define CADRCC1 1 #define CADRCC2 2 #define CADRCC3 3 #define CADRCC4 4 #define CADRCC5 5 #define CADRCC6 6 #define CADRCC7 7 #define CADRDC _SFR_MEM8(0xEA) #define CADRDC0 0 #define CADRDC1 1 #define CADRDC2 2 #define CADRDC3 3 #define CADRDC4 4 #define CADRDC5 5 #define CADRDC6 6 #define CADRDC7 7 #define FCSR _SFR_MEM8(0xF0) #define CFE 0 #define DFE 1 #define CPS 2 #define DUVRD 3 #define CBCR _SFR_MEM8(0xF1) #define CBE1 0 #define CBE2 1 #define CBE3 2 #define CBE4 3 #define BPIMSK _SFR_MEM8(0xF2) #define CHCIE 0 #define DHCIE 1 #define COCIE 2 #define DOCIE 3 #define SCIE 4 #define BPIFR _SFR_MEM8(0xF3) #define CHCIF 0 #define DHCIF 1 #define COCIF 2 #define DOCIF 3 #define SCIF 4 #define BPSCD _SFR_MEM8(0xF5) #define SCDL0 0 #define SCDL1 1 #define SCDL2 2 #define SCDL3 3 #define SCDL4 4 #define SCDL5 5 #define SCDL6 6 #define SCDL7 7 #define BPDOCD _SFR_MEM8(0xF6) #define DOCDL0 0 #define DOCDL1 1 #define DOCDL2 2 #define DOCDL3 3 #define DOCDL4 4 #define DOCDL5 5 #define DOCDL6 6 #define DOCDL7 7 #define BPCOCD _SFR_MEM8(0xF7) #define COCDL0 0 #define COCDL1 1 #define COCDL2 2 #define COCDL3 3 #define COCDL4 4 #define COCDL5 5 #define COCDL6 6 #define COCDL7 7 #define BPDHCD _SFR_MEM8(0xF8) #define DHCDL0 0 #define DHCDL1 1 #define DHCDL2 2 #define DHCDL3 3 #define DHCDL4 4 #define DHCDL5 5 #define DHCDL6 6 #define DHCDL7 7 #define BPCHCD _SFR_MEM8(0xF9) #define CHCDL0 0 #define CHCDL1 1 #define CHCDL2 2 #define CHCDL3 3 #define CHCDL4 4 #define CHCDL5 5 #define CHCDL6 6 #define CHCDL7 7 #define BPSCTR _SFR_MEM8(0xFA) #define SCPT0 0 #define SCPT1 1 #define SCPT2 2 #define SCPT3 3 #define SCPT4 4 #define SCPT5 5 #define SCPT6 6 #define BPOCTR _SFR_MEM8(0xFB) #define OCPT0 0 #define OCPT1 1 #define OCPT2 2 #define OCPT3 3 #define OCPT4 4 #define OCPT5 5 #define BPHCTR _SFR_MEM8(0xFC) #define HCPT0 0 #define HCPT1 1 #define HCPT2 2 #define HCPT3 3 #define HCPT4 4 #define HCPT5 5 #define BPCR _SFR_MEM8(0xFD) #define CHCD 0 #define DHCD 1 #define COCD 2 #define DOCD 3 #define SCD 4 #define EPID 5 #define BPPLR _SFR_MEM8(0xFE) #define BPPL 0 #define BPPLE 1 /* Interrupt Vectors */ /* Interrupt Vector 0 is the reset vector. */ #define BPINT_vect_num 1 #define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ #define VREGMON_vect_num 2 #define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ #define INT0_vect_num 3 #define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ #define INT1_vect_num 4 #define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ #define INT2_vect_num 5 #define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ #define INT3_vect_num 6 #define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ #define PCINT0_vect_num 7 #define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ #define PCINT1_vect_num 8 #define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ #define WDT_vect_num 9 #define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ #define BGSCD_vect_num 10 #define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ #define CHDET_vect_num 11 #define CHDET_vect _VECTOR(11) /* Charger Detect */ #define TIMER1_IC_vect_num 12 #define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ #define TIMER0_IC_vect_num 16 #define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ #define TIMER0_COMPA_vect_num 17 #define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ #define TIMER0_COMPB_vect_num 18 #define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ #define TIMER0_OVF_vect_num 19 #define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ #define TWIBUSCD_vect_num 20 #define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ #define TWI_vect_num 21 #define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ #define SPI_STC_vect_num 22 #define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ #define VADC_vect_num 23 #define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ #define CCADC_CONV_vect_num 24 #define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ #define CCADC_REG_CUR_vect_num 25 #define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ #define CCADC_ACC_vect_num 26 #define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ #define EE_READY_vect_num 27 #define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ #define SPM_vect_num 28 #define SPM_vect _VECTOR(28) /* SPM Ready */ #define _VECTORS_SIZE (29 * 4) /* Constants */ #define SPM_PAGESIZE 64 #define RAMEND 0x8FF /* Last On-Chip SRAM Location */ #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x3FF #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ #define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ #define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ #define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ #define LFUSE_DEFAULT (FUSE_OSCSEL0 & FUSE_SPIEN) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ #define FUSE_DUVRDINIT (unsigned char)~_BV(4) /* Reset Value of DUVRDRegister */ #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_DUVRDINIT) /* Lock Bits */ #define __LOCK_BITS_EXIST #endif /* _AVR_IOM32HVBREVB_H_ */ avr-libc-1.8.0.orig/include/avr/io76c711.h0000644000000000000000000002370211732702554014622 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io76c711.h 1873 2009-02-11 17:53:39Z arcanum $ */ /* avr/io76c711.h - definitions for AT76C711 */ #ifndef _AVR_IO76C711_H_ #define _AVR_IO76C711_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io76c711.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* 0x00-0x0C reserved */ /* SPI */ #define SPCR _SFR_IO8(0x0D) #define SPSR _SFR_IO8(0x0E) #define SPDR _SFR_IO8(0x0F) /* Port D */ #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) /* Peripheral Enable Register */ #define PERIPHEN _SFR_IO8(0x13) /* Clock Control Register */ #define CLK_CNTR _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Port B */ #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) /* Port A */ #define PINA _SFR_IO8(0x19) #define DDRA _SFR_IO8(0x1A) #define PORTA _SFR_IO8(0x1B) /* 0x1C-0x1F reserved */ #define IRDAMOD _SFR_IO8(0x20) #define WDTCR _SFR_IO8(0x21) /* 0x22-0x25 reserved */ /* Timer 1 */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define TCCR1A _SFR_IO8(0x2F) /* 0x30 reserved */ /* Timer 0 */ #define PRELD _SFR_IO8(0x31) #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define MCUSR _SFR_IO8(0x34) #define MCUCR _SFR_IO8(0x35) #define TIFR _SFR_IO8(0x36) #define TIMSK _SFR_IO8(0x37) /* 0x38 reserved */ #define EIMSK _SFR_IO8(0x39) /* 0x3A-0x3C reserved */ /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ #define SIG_SUSPEND_RESUME _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(2) #define SIG_INPUT_CAPTURE1 _VECTOR(3) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) #define SIG_OUTPUT_COMPARE1B _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(7) #define SIG_SPI _VECTOR(8) #define SIG_TDMAC _VECTOR(9) #define SIG_UART0 _VECTOR(10) #define SIG_RDMAC _VECTOR(11) #define SIG_USB_HW _VECTOR(12) #define SIG_UART1 _VECTOR(13) #define SIG_INTERRUPT1 _VECTOR(14) #define _VECTORS_SIZE 60 /* Bit numbers */ /* EIMSK */ /* bits 7-4 reserved */ #define POL1 3 #define POL0 2 #define INT1 1 #define INT0 0 /* TIMSK */ #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 /* bit 4 reserved */ #define TICIE1 3 /* bit 2 reserved */ #define TOIE0 1 /* bit 0 reserved */ /* TIFR */ #define TOV1 7 #define OCF1A 6 #define OCF1B 5 /* bit 4 reserved */ #define ICF1 3 /* bit 2 reserved */ #define TOV0 1 /* bit 0 reserved */ /* MCUCR */ /* bits 7-6 reserved */ #define SE 5 #define SM1 4 #define SM0 3 /* bits 2-0 reserved */ /* MCUSR */ /* bits 7-2 reserved */ #define EXTRF 1 #define PORF 0 /* TCCR0 */ /* bits 7-6 reserved */ #define COM01 5 #define COM00 4 #define CTC0 3 #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 /* bits 3-0 reserved */ /* TCCR1B */ #define ICNC1 7 #define ICES1 6 /* bits 5-4 reserved */ #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* WDTCR */ /* bits 7-5 reserved */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* IRDAMOD */ /* bits 7-3 reserved */ #define POL 2 #define MODE 1 #define EN 0 /* PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* PB7 = SCK PB6 = MISO PB5 = MOSI PB4 = SS# PB2 = ICP PB1 = T1 PB0 = T0 */ /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PORTC */ /* bits 7-4 reserved */ #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* PD7 = INT1 / OC1B PD6 = INT0 / OC1A PD1 = TXD PD0 = RXD */ /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* CLK_CNTR */ /* bits 7-5 reserved */ #define UOSC 4 #define UCK 3 #define IRCK 2 /* bits 1-0 reserved */ /* PERIPHEN */ /* bits 7-3 reserved */ #define IRDA 2 #define UART 1 #define USB 0 /* SPSR */ #define SPIF 7 #define WCOL 6 /* bits 5-0 reserved */ /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */ /* UART */ #define UART0_BASE 0x2020 #define UART1_BASE 0x2030 /* offsets from the base address */ #define US_RHR 0x00 #define US_THR 0x00 #define US_IER 0x01 #define US_FCR 0x02 #define US_PMR 0x03 #define US_MR 0x04 #define US_CSR 0x05 #define US_CR 0x06 #define US_BL 0x07 #define US_BM 0x08 #define US_RTO 0x09 #define US_TTG 0x0A /* DMA */ #define DMA_BASE 0x2000 /* offsets from the base address */ #define TXTADL 0x01 #define TXPLL 0x03 #define TXPLM 0x04 #define TXTPLL 0x05 #define TXTPLM 0x06 #define RXTADL 0x07 #define RXTADMEN 0x08 #define RSPLL 0x09 #define RXPLM 0x0A #define RXTPLL 0x0B #define RXTPLM 0x0C #define INTCST 0x0D /* XXX DPORG register mentioned on page 20, but undocumented */ /* XXX Program Memory Control Bit mentioned on page 20, but undocumented */ #define PROGRAM_MEMORY_CONTROL_BIT 0x2040 /* USB */ #define USB_BASE 0x1000 /* offsets from the base address */ #define FRM_NUM_H 0x0FD #define FRM_NUM_L 0x0FC #define GLB_STATE 0x0FB #define SPRSR 0x0FA #define SPRSIE 0x0F9 #define UISR 0x0F7 #define UIAR 0x0F5 #define FADDR 0x0F2 #define ENDPPGPG 0x0F1 #define ECR0 0x0EF #define ECR1 0x0EE #define ECR2 0x0ED #define ECR3 0x0EC #define ECR4 0x0EB #define ECR5 0x0EA #define ECR6 0x0E9 #define ECR7 0x0E8 #define CSR0 0x0DF #define CSR1 0x0DE #define CSR2 0x0DD #define CSR3 0x0DC #define CSR4 0x0DB #define CSR5 0x0DA #define CSR6 0x0D9 #define CSR7 0x0D8 #define FDR0 0x0CF #define FDR1 0x0CE #define FDR2 0x0CD #define FDR3 0x0CC #define FDR4 0x0CB #define FDR5 0x0CA #define FDR6 0x0C9 #define FDR7 0x0C8 #define FBYTE_CNT0_L 0x0BF #define FBYTE_CNT1_L 0x0BE #define FBYTE_CNT2_L 0x0BD #define FBYTE_CNT3_L 0x0BC #define FBYTE_CNT4_L 0x0BB #define FBYTE_CNT5_L 0x0BA #define FBYTE_CNT6_L 0x0B9 #define FBYTE_CNT7_L 0x0B8 #define FBYTE_CNT0_H 0x0AF #define FBYTE_CNT1_H 0x0AE #define FBYTE_CNT2_H 0x0AD #define FBYTE_CNT3_H 0x0AC #define FBYTE_CNT4_H 0x0AB #define FBYTE_CNT5_H 0x0AA #define FBYTE_CNT6_H 0x0A9 #define FBYTE_CNT7_H 0x0A8 #define SLP_MD_EN 0x100 #define IRQ_EN 0x101 #define IRQ_STAT 0x102 #define SUSP_WUP 0x103 #define PA_EN 0x104 #define USB_DMA_ADL 0x105 #define USB_DMA_ADH 0x106 #define USB_DMA_PLR 0x107 #define USB_DMA_EAD 0x108 #define USB_DMA_PLT 0x109 #define USB_DMA_EN 0x10A /* Last memory addresses */ #define RAMEND 0x07FF #define XRAMEND RAMEND #define E2END 0 #define FLASHEND 0x3FFF /* AT76C711 data space memory map (ranges not listed are reserved): 0x0000 - 0x001F - AVR registers 0x0020 - 0x005F - AVR I/O space 0x0060 - 0x07FF - AVR data SRAM 0x1000 - 0x1FFF - USB (not all locations used) 0x2000 - 0x201F - DMA controller 0x2020 - 0x202F - UART0 0x2030 - 0x203F - UART1 (IRDA) 0x2040 - the mysterious Program Memory Control bit (???) 0x3000 - 0x37FF - DPRAM 0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other AVR devices did that as well (no need to use LPM!) */ #endif /* _AVR_IO76C711_H_ */ avr-libc-1.8.0.orig/include/avr/iom164.h0000644000000000000000000000656611732702554014472 0ustar /* Copyright (c) 2005, 2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/iom164.h - definitions for ATmega164 */ /* $Id: iom164.h 2115 2010-04-05 23:19:53Z arcanum $ */ #ifndef _AVR_IOM164_H_ #define _AVR_IOM164_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 128 #define RAMSTART (0x100) #define RAMEND 0x04FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature (ATmega164P) */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x0A #endif /* _AVR_IOM164_H_ */ avr-libc-1.8.0.orig/include/avr/iox32d4.h0000644000000000000000000072006511732702554014644 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox32d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox32d4.h - definitions for ATxmega32D4 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox32d4.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega32D4_H_ #define _AVR_ATxmega32D4_H_ 1 /* Ungrouped common registers */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) /* DACB - Digital to Analog Converter B */ /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (91 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (36864) #define PROGMEM_PAGE_SIZE (256) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (32768) #define APP_SECTION_PAGE_SIZE (256) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x7000) #define APPTABLE_SECTION_SIZE (4096) #define APPTABLE_SECTION_PAGE_SIZE (256) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x8000) #define BOOT_SECTION_SIZE (4096) #define BOOT_SECTION_PAGE_SIZE (256) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (12288) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (1024) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (4096) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (1024) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (256) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x42 #endif /* _AVR_ATxmega32D4_H_ */ avr-libc-1.8.0.orig/include/avr/iom32.h0000644000000000000000000003666411732702554014406 0ustar /* Copyright (c) 2002, Steinar Haugen All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom32.h 2233 2011-03-15 15:49:50Z arcanum $ */ /* avr/iom32.h - definitions for ATmega32 */ #ifndef _AVR_IOM32_H_ #define _AVR_IOM32_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWAR _SFR_IO8(0x02) #define TWDR _SFR_IO8(0x03) /* ADC */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSRA _SFR_IO8(0x06) #define ADMUX _SFR_IO8(0x07) /* analog comparator */ #define ACSR _SFR_IO8(0x08) /* USART */ #define UBRRL _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) #define UDR _SFR_IO8(0x0C) /* SPI */ #define SPCR _SFR_IO8(0x0D) #define SPSR _SFR_IO8(0x0E) #define SPDR _SFR_IO8(0x0F) /* Port D */ #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) /* Port C */ #define PINC _SFR_IO8(0x13) #define DDRC _SFR_IO8(0x14) #define PORTC _SFR_IO8(0x15) /* Port B */ #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) /* Port A */ #define PINA _SFR_IO8(0x19) #define DDRA _SFR_IO8(0x1A) #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UBRRH _SFR_IO8(0x20) #define UCSRC UBRRH #define WDTCR _SFR_IO8(0x21) #define ASSR _SFR_IO8(0x22) /* Timer 2 */ #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) /* Timer 1 */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define TCCR1A _SFR_IO8(0x2F) #define SFIOR _SFR_IO8(0x30) #define OSCCAL _SFR_IO8(0x31) #define OCDR OSCCAL /* Timer 0 */ #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define MCUSR _SFR_IO8(0x34) #define MCUCSR MCUSR #define MCUCR _SFR_IO8(0x35) #define TWCR _SFR_IO8(0x36) #define SPMCR _SFR_IO8(0x37) #define TIFR _SFR_IO8(0x38) #define TIMSK _SFR_IO8(0x39) #define GIFR _SFR_IO8(0x3A) #define GIMSK _SFR_IO8(0x3B) #define GICR GIMSK #define OCR0 _SFR_IO8(0x3C) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART, Rx Complete */ #define USART_RXC_vect_num 13 #define USART_RXC_vect _VECTOR(13) #define SIG_USART_RECV _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) /* USART Data Register Empty */ #define USART_UDRE_vect_num 14 #define USART_UDRE_vect _VECTOR(14) #define SIG_USART_DATA _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) /* USART, Tx Complete */ #define USART_TXC_vect_num 15 #define USART_TXC_vect _VECTOR(15) #define SIG_USART_TRANS _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) /* ADC Conversion Complete */ #define ADC_vect_num 16 #define ADC_vect _VECTOR(16) #define SIG_ADC _VECTOR(16) /* EEPROM Ready */ #define EE_RDY_vect_num 17 #define EE_RDY_vect _VECTOR(17) #define SIG_EEPROM_READY _VECTOR(17) /* Analog Comparator */ #define ANA_COMP_vect_num 18 #define ANA_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* 2-wire Serial Interface */ #define TWI_vect_num 19 #define TWI_vect _VECTOR(19) #define SIG_2WIRE_SERIAL _VECTOR(19) /* Store Program Memory Ready */ #define SPM_RDY_vect_num 20 #define SPM_RDY_vect _VECTOR(20) #define SIG_SPM_READY _VECTOR(20) #define _VECTORS_SIZE 84 /* Bit numbers */ /* GICR */ #define INT1 7 #define INT0 6 #define INT2 5 #define IVSEL 1 #define IVCE 0 /* GIFR */ #define INTF1 7 #define INTF0 6 #define INTF2 5 /* TIMSK */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 /* TIFR */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 /* SPMCR */ #define SPMIE 7 #define RWWSB 6 /* bit 5 reserved */ #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 /* bit 1 reserved */ #define TWIE 0 /* TWAR */ #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 /* TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 /* bit 2 reserved */ #define TWPS1 1 #define TWPS0 0 /* MCUCR */ #define SE 7 #define SM2 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* MCUCSR */ #define JTD 7 #define ISC2 6 /* bit 5 reserved */ #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* SFIOR */ #define ADTS2 7 #define ADTS1 6 #define ADTS0 5 /* bit 4 reserved */ #define ACME 3 #define PUD 2 #define PSR2 1 #define PSR10 0 /* TCCR0 */ #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR2 */ #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* ASSR */ /* bits 7-4 reserved */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define WGM11 1 #define WGM10 0 /* TCCR1B */ #define ICNC1 7 #define ICES1 6 /* bit 5 reserved */ #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* WDTCR */ /* bits 7-5 reserved */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PA7-PA0 = ADC7-ADC0 */ /* PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* PB7 = SCK PB6 = MISO PB5 = MOSI PB4 = SS# PB3 = OC0/AIN1 PB2 = INT2/AIN0 PB1 = T1 PB0 = XCK/T0 */ /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PC7 = TOSC2 PC6 = TOSC1 PC1 = SDA PC0 = SCL */ /* PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* PD7 = OC2 PD6 = ICP PD5 = OC1A PD4 = OC1B PD3 = INT1 PD2 = INT0 PD1 = TXD PD0 = RXD */ /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPSR */ #define SPIF 7 #define WCOL 6 /* bits 5-1 reserved */ #define SPI2X 0 /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UCSRA */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define PE 2 #define U2X 1 #define MPCM 0 /* UCSRB */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 /* UCSRC */ #define URSEL 7 #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 128 #define RAMSTART (0x60) #define RAMEND 0x85F #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 4 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x02 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_USART_RECV #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_USART_DATA #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_USART_TRANS #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_2WIRE_SERIAL #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM32_H_ */ avr-libc-1.8.0.orig/include/avr/iotn461.h0000644000000000000000000000616311732702554014650 0ustar /* Copyright (c) 2006, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn461.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iotn461.h - definitions for ATtiny461 */ #ifndef _AVR_IOTN461_H_ #define _AVR_IOTN461_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x60) #define RAMEND 0x15F #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 4 #define FLASHEND 0xFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x08 #endif /* _AVR_IOTN461_H_ */ avr-libc-1.8.0.orig/include/avr/io4433.h0000644000000000000000000002660511732702554014374 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io4433.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io4433.h - definitions for AT90S4433 */ #ifndef _AVR_IO4433_H_ #define _AVR_IO4433_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io4433.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* UART Baud Rate Register high */ #define UBRRH _SFR_IO8(0x03) /* ADC Data register */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and Status Register */ #define ADCSR _SFR_IO8(0x06) /* ADC MUX */ #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART Baud Rate Register */ #define UBRR _SFR_IO8(0x09) /* UART Control/Status Registers */ #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) /* UART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Timer/Counter1 Output Compare Register A */ #define OCR1 _SFR_IO16(0x2A) #define OCR1L _SFR_IO8(0x2A) #define OCR1H _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter Capture Event */ #define TIMER1_CAPT_vect_num 3 #define TIMER1_CAPT_vect _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) /* Timer/Counter1 Compare Match */ #define TIMER1_COMP_vect_num 4 #define TIMER1_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 5 #define TIMER1_OVF_vect _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(5) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 6 #define TIMER0_OVF_vect _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(6) /* Serial Transfer Complete */ #define SPI_STC_vect_num 7 #define SPI_STC_vect _VECTOR(7) #define SIG_SPI _VECTOR(7) /* UART, Rx Complete */ #define UART_RX_vect_num 8 #define UART_RX_vect _VECTOR(8) #define SIG_UART_RECV _VECTOR(8) /* UART Data Register Empty */ #define UART_UDRE_vect_num 9 #define UART_UDRE_vect _VECTOR(9) #define SIG_UART_DATA _VECTOR(9) /* UART, Tx Complete */ #define UART_TX_vect_num 10 #define UART_TX_vect _VECTOR(10) #define SIG_UART_TRANS _VECTOR(10) /* ADC Conversion Complete */ #define ADC_vect_num 11 #define ADC_vect _VECTOR(11) #define SIG_ADC _VECTOR(11) /* EEPROM Ready */ #define EE_RDY_vect_num 12 #define EE_RDY_vect _VECTOR(12) #define SIG_EEPROM_READY _VECTOR(12) /* Analog Comparator */ #define ANA_COMP_vect_num 13 #define ANA_COMP_vect _VECTOR(13) #define SIG_COMPARATOR _VECTOR(13) #define _VECTORS_SIZE 28 /* The Register Bit names are represented by their bit number (0-7). */ /* MCU general Status Register */ #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* General Interrupt MaSK register */ #define INT1 7 #define INT0 6 /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 /* Timer/Counter Interrupt MaSK register */ #define TOIE1 7 #define OCIE1 6 #define TICIE1 3 #define TOIE0 1 /* Timer/Counter Interrupt Flag register */ #define TOV1 7 #define OCF1 6 #define ICF1 3 #define TOV0 1 /* MCU general Control Register */ #define SE 5 #define SM 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 1 Control Register */ #define COM11 7 #define COM10 6 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define MPCM 0 /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define AINBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADC MUX */ #define ACDBG 6 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* ADC Control and Status Register */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* Data Register, Port B */ #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port C */ #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Direction Register, Port C */ #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0xDF /*Last On-Chip SRAM location*/ #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 0 #define FLASHEND 0xFFF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_BODEN (unsigned char)~_BV(3) #define FUSE_BODLEVEL (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define LFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x03 #endif /* _AVR_IO4433_H_ */ avr-libc-1.8.0.orig/include/avr/iom16u4.h0000644000000000000000000006540311732702554014652 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16u4.h 2185 2010-09-22 07:06:35Z aboyapati $ */ /* avr/iom16u4.h - definitions for ATmega16U4 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16u4.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega16U4_H_ #define _AVR_ATmega16U4_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE2 2 #define PINE6 6 #define DDRE _SFR_IO8(0x0D) #define DDE2 2 #define DDE6 6 #define PORTE _SFR_IO8(0x0E) #define PORTE2 2 #define PORTE6 6 #define PINF _SFR_IO8(0x0F) #define PINF0 0 #define PINF1 1 #define PINF4 4 #define PINF5 5 #define PINF6 6 #define PINF7 7 #define DDRF _SFR_IO8(0x10) #define DDF0 0 #define DDF1 1 #define DDF4 4 #define DDF5 5 #define DDF6 6 #define DDF7 7 #define PORTF _SFR_IO8(0x11) #define PORTF0 0 #define PORTF1 1 #define PORTF4 4 #define PORTF5 5 #define PORTF6 6 #define PORTF7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define OCF1C 3 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TIFR3 _SFR_IO8(0x18) #define TOV3 0 #define OCF3A 1 #define OCF3B 2 #define OCF3C 3 #define ICF3 5 #define TIFR4 _SFR_IO8(0x19) #define TOV4 2 #define OCF4B 5 #define OCF4A 6 #define OCF4D 7 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define INTF4 4 #define INTF5 5 #define INTF6 6 #define INTF7 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define INT4 4 #define INT5 5 #define INT6 6 #define INT7 7 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCROA_0 0 #define OCROA_1 1 #define OCROA_2 2 #define OCROA_3 3 #define OCROA_4 4 #define OCROA_5 5 #define OCROA_6 6 #define OCROA_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PINDIV 4 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define PLLFRQ _SFR_IO8(0x32) #define PDIV0 0 #define PDIV1 1 #define PDIV2 2 #define PDIV3 3 #define PLLTM0 4 #define PLLTM1 5 #define PLLUSB 6 #define PINMUX 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define RAMPZ _SFR_IO8(0x3B) #define RAMPZ0 0 #define EIND _SFR_IO8(0x3C) #define EIND0 0 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define PRR1 _SFR_MEM8(0x65) #define PRUSART1 0 #define PRTIM3 3 #define PRUSB 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define RCCTRL _SFR_MEM8(0x67) #define RCFREQ 0 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define EICRB _SFR_MEM8(0x6A) #define ISC40 0 #define ISC41 1 #define ISC50 2 #define ISC51 3 #define ISC60 4 #define ISC61 5 #define ISC70 6 #define ISC71 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define OCIE1C 3 #define ICIE1 5 #define TIMSK3 _SFR_MEM8(0x71) #define TOIE3 0 #define OCIE3A 1 #define OCIE3B 2 #define OCIE3C 3 #define ICIE3 5 #define TIMSK4 _SFR_MEM8(0x72) #define TOIE4 2 #define OCIE4B 5 #define OCIE4A 6 #define OCIE4D 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define MUX5 5 #define ACME 6 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR2 _SFR_MEM8(0x7D) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define ADC11D 3 #define ADC12D 4 #define ADC13D 5 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1C0 2 #define COM1C1 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1C 5 #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CL0 0 #define OCR1CL1 1 #define OCR1CL2 2 #define OCR1CL3 3 #define OCR1CL4 4 #define OCR1CL5 5 #define OCR1CL6 6 #define OCR1CL7 7 #define OCR1CH _SFR_MEM8(0x8D) #define OCR1CH0 0 #define OCR1CH1 1 #define OCR1CH2 2 #define OCR1CH3 3 #define OCR1CH4 4 #define OCR1CH5 5 #define OCR1CH6 6 #define OCR1CH7 7 #define TCCR3A _SFR_MEM8(0x90) #define WGM30 0 #define WGM31 1 #define COM3C0 2 #define COM3C1 3 #define COM3B0 4 #define COM3B1 5 #define COM3A0 6 #define COM3A1 7 #define TCCR3B _SFR_MEM8(0x91) #define CS30 0 #define CS31 1 #define CS32 2 #define WGM32 3 #define WGM33 4 #define ICES3 6 #define ICNC3 7 #define TCCR3C _SFR_MEM8(0x92) #define FOC3C 5 #define FOC3B 6 #define FOC3A 7 #define TCNT3 _SFR_MEM16(0x94) #define TCNT3L _SFR_MEM8(0x94) #define TCNT3L0 0 #define TCNT3L1 1 #define TCNT3L2 2 #define TCNT3L3 3 #define TCNT3L4 4 #define TCNT3L5 5 #define TCNT3L6 6 #define TCNT3L7 7 #define TCNT3H _SFR_MEM8(0x95) #define TCNT3H0 0 #define TCNT3H1 1 #define TCNT3H2 2 #define TCNT3H3 3 #define TCNT3H4 4 #define TCNT3H5 5 #define TCNT3H6 6 #define TCNT3H7 7 #define ICR3 _SFR_MEM16(0x96) #define ICR3L _SFR_MEM8(0x96) #define ICR3L0 0 #define ICR3L1 1 #define ICR3L2 2 #define ICR3L3 3 #define ICR3L4 4 #define ICR3L5 5 #define ICR3L6 6 #define ICR3L7 7 #define ICR3H _SFR_MEM8(0x97) #define ICR3H0 0 #define ICR3H1 1 #define ICR3H2 2 #define ICR3H3 3 #define ICR3H4 4 #define ICR3H5 5 #define ICR3H6 6 #define ICR3H7 7 #define OCR3A _SFR_MEM16(0x98) #define OCR3AL _SFR_MEM8(0x98) #define OCR3AL0 0 #define OCR3AL1 1 #define OCR3AL2 2 #define OCR3AL3 3 #define OCR3AL4 4 #define OCR3AL5 5 #define OCR3AL6 6 #define OCR3AL7 7 #define OCR3AH _SFR_MEM8(0x99) #define OCR3AH0 0 #define OCR3AH1 1 #define OCR3AH2 2 #define OCR3AH3 3 #define OCR3AH4 4 #define OCR3AH5 5 #define OCR3AH6 6 #define OCR3AH7 7 #define OCR3B _SFR_MEM16(0x9A) #define OCR3BL _SFR_MEM8(0x9A) #define OCR3BL0 0 #define OCR3BL1 1 #define OCR3BL2 2 #define OCR3BL3 3 #define OCR3BL4 4 #define OCR3BL5 5 #define OCR3BL6 6 #define OCR3BL7 7 #define OCR3BH _SFR_MEM8(0x9B) #define OCR3BH0 0 #define OCR3BH1 1 #define OCR3BH2 2 #define OCR3BH3 3 #define OCR3BH4 4 #define OCR3BH5 5 #define OCR3BH6 6 #define OCR3BH7 7 #define OCR3C _SFR_MEM16(0x9C) #define OCR3CL _SFR_MEM8(0x9C) #define OCR3CL0 0 #define OCR3CL1 1 #define OCR3CL2 2 #define OCR3CL3 3 #define OCR3CL4 4 #define OCR3CL5 5 #define OCR3CL6 6 #define OCR3CL7 7 #define OCR3CH _SFR_MEM8(0x9D) #define OCR3CH0 0 #define OCR3CH1 1 #define OCR3CH2 2 #define OCR3CH3 3 #define OCR3CH4 4 #define OCR3CH5 5 #define OCR3CH6 6 #define OCR3CH7 7 #define TCNT4 _SFR_MEM8(0xBE) #define TC40 0 #define TC41 1 #define TC42 2 #define TC43 3 #define TC44 4 #define TC45 5 #define TC46 6 #define TC47 7 #define TC4H _SFR_MEM8(0xBF) #define TC48 0 #define TC49 1 #define TC410 2 #define TCCR4A _SFR_MEM8(0xC0) #define PWM4B 0 #define PWM4A 1 #define FOC4B 2 #define FOC4A 3 #define COM4B0 4 #define COM4B1 5 #define COM4A0 6 #define COM4A1 7 #define TCCR4B _SFR_MEM8(0xC1) #define CS40 0 #define CS41 1 #define CS42 2 #define CS43 3 #define DTPS40 4 #define DTPS41 5 #define PSR4 6 #define PWM4X 7 #define TCCR4C _SFR_MEM8(0xC2) #define PWM4D 0 #define FOC4D 1 #define COM4D0 2 #define COM4D1 3 #define COM4B0S 4 #define COM4B1S 5 #define COM4A0S 6 #define COM4A1S 7 #define TCCR4D _SFR_MEM8(0xC3) #define WGM40 0 #define WGM41 1 #define FPF4 2 #define FPAC4 3 #define FPES4 4 #define FPNC4 5 #define FPEN4 6 #define FPIE4 7 #define TCCR4E _SFR_MEM8(0xC4) #define OC4OE0 0 #define OC4OE1 1 #define OC4OE2 2 #define OC4OE3 3 #define OC4OE4 4 #define OC4OE5 5 #define ENHC4 6 #define TLOCK4 7 #define CLKSEL0 _SFR_MEM8(0xC5) #define CLKS 0 #define EXTE 2 #define RCE 3 #define EXSUT0 4 #define EXSUT1 5 #define RCSUT0 6 #define RCSUT1 7 #define CLKSEL1 _SFR_MEM8(0xC6) #define EXCKSEL0 0 #define EXCKSEL1 1 #define EXCKSEL2 2 #define EXCKSEL3 3 #define RCCKSEL0 4 #define RCCKSEL1 5 #define RCCKSEL2 6 #define RCCKSEL3 7 #define CLKSTA _SFR_MEM8(0xC7) #define EXTON 0 #define RCON 1 #define UCSR1A _SFR_MEM8(0xC8) #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 #define UCSR1B _SFR_MEM8(0xC9) #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 #define UCSR1C _SFR_MEM8(0xCA) #define UCPOL1 0 #define UCSZ10 1 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1H _SFR_MEM8(0xCD) #define UDR1 _SFR_MEM8(0xCE) #define UDR1_0 0 #define UDR1_1 1 #define UDR1_2 2 #define UDR1_3 3 #define UDR1_4 4 #define UDR1_5 5 #define UDR1_6 6 #define UDR1_7 7 #define OCR4A _SFR_MEM8(0xCF) #define OCR4A0 0 #define OCR4A1 1 #define OCR4A2 2 #define OCR4A3 3 #define OCR4A4 4 #define OCR4A5 5 #define OCR4A6 6 #define OCR4A7 7 #define OCR4B _SFR_MEM8(0xD0) #define OCR4B0 0 #define OCR4B1 1 #define OCR4B2 2 #define OCR4B3 3 #define OCR4B4 4 #define OCR4B5 5 #define OCR4B6 6 #define OCR4B7 7 #define OCR4C _SFR_MEM8(0xD1) #define OCR4C0 0 #define OCR4C1 1 #define OCR4C2 2 #define OCR4C3 3 #define OCR4C4 4 #define OCR4C5 5 #define OCR4C6 6 #define OCR4C7 7 #define OCR4D _SFR_MEM8(0xD2) #define OCR4D0 0 #define OCR4D1 1 #define OCR4D2 2 #define OCR4D3 3 #define OCR4D4 4 #define OCR4D5 5 #define OCR4D6 6 #define OCR4D7 7 #define DT4 _SFR_MEM8(0xD4) #define DT4L0 0 #define DT4L1 1 #define DT4L2 2 #define DT4L3 3 #define DT4L4 4 #define DT4L5 5 #define DT4L6 6 #define DT4L7 7 #define UHWCON _SFR_MEM8(0xD7) #define UVREGE 0 #define USBCON _SFR_MEM8(0xD8) #define VBUSTE 0 #define OTGPADE 4 #define FRZCLK 5 #define USBE 7 #define USBSTA _SFR_MEM8(0xD9) #define VBUS 0 #define SPEED 3 #define USBINT _SFR_MEM8(0xDA) #define VBUSTI 0 #define UDCON _SFR_MEM8(0xE0) #define DETACH 0 #define RMWKUP 1 #define LSM 2 #define RSTCPU 3 #define UDINT _SFR_MEM8(0xE1) #define SUSPI 0 #define SOFI 2 #define EORSTI 3 #define WAKEUPI 4 #define EORSMI 5 #define UPRSMI 6 #define UDIEN _SFR_MEM8(0xE2) #define SUSPE 0 #define SOFE 2 #define EORSTE 3 #define WAKEUPE 4 #define EORSME 5 #define UPRSME 6 #define UDADDR _SFR_MEM8(0xE3) #define UADD0 0 #define UADD1 1 #define UADD2 2 #define UADD3 3 #define UADD4 4 #define UADD5 5 #define UADD6 6 #define ADDEN 7 #define UDFNUM _SFR_MEM16(0xE4) #define UDFNUML _SFR_MEM8(0xE4) #define FNUM0 0 #define FNUM1 1 #define FNUM2 2 #define FNUM3 3 #define FNUM4 4 #define FNUM5 5 #define FNUM6 6 #define FNUM7 7 #define UDFNUMH _SFR_MEM8(0xE5) #define FNUM8 0 #define FNUM9 1 #define FNUM10 2 #define UDMFN _SFR_MEM8(0xE6) #define FNCERR 4 #define UEINTX _SFR_MEM8(0xE8) #define TXINI 0 #define STALLEDI 1 #define RXOUTI 2 #define RXSTPI 3 #define NAKOUTI 4 #define RWAL 5 #define NAKINI 6 #define FIFOCON 7 #define UENUM _SFR_MEM8(0xE9) #define UENUM_0 0 #define UENUM_1 1 #define UENUM_2 2 #define UERST _SFR_MEM8(0xEA) #define EPRST0 0 #define EPRST1 1 #define EPRST2 2 #define EPRST3 3 #define EPRST4 4 #define EPRST5 5 #define EPRST6 6 #define UECONX _SFR_MEM8(0xEB) #define EPEN 0 #define RSTDT 3 #define STALLRQC 4 #define STALLRQ 5 #define UECFG0X _SFR_MEM8(0xEC) #define EPDIR 0 #define EPTYPE0 6 #define EPTYPE1 7 #define UECFG1X _SFR_MEM8(0xED) #define ALLOC 1 #define EPBK0 2 #define EPBK1 3 #define EPSIZE0 4 #define EPSIZE1 5 #define EPSIZE2 6 #define UESTA0X _SFR_MEM8(0xEE) #define NBUSYBK0 0 #define NBUSYBK1 1 #define DTSEQ0 2 #define DTSEQ1 3 #define UNDERFI 5 #define OVERFI 6 #define CFGOK 7 #define UESTA1X _SFR_MEM8(0xEF) #define CURRBK0 0 #define CURRBK1 1 #define CTRLDIR 2 #define UEIENX _SFR_MEM8(0xF0) #define TXINE 0 #define STALLEDE 1 #define RXOUTE 2 #define RXSTPE 3 #define NAKOUTE 4 #define NAKINE 6 #define FLERRE 7 #define UEDATX _SFR_MEM8(0xF1) #define DAT0 0 #define DAT1 1 #define DAT2 2 #define DAT3 3 #define DAT4 4 #define DAT5 5 #define DAT6 6 #define DAT7 7 #define UEBCLX _SFR_MEM8(0xF2) #define BYCT0 0 #define BYCT1 1 #define BYCT2 2 #define BYCT3 3 #define BYCT4 4 #define BYCT5 5 #define BYCT6 6 #define BYCT7 7 #define UEBCHX _SFR_MEM8(0xF3) #define UEINT _SFR_MEM8(0xF4) #define EPINT0 0 #define EPINT1 1 #define EPINT2 2 #define EPINT3 3 #define EPINT4 4 #define EPINT5 5 #define EPINT6 6 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ #define PCINT0_vect_num 9 #define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ #define USB_GEN_vect_num 10 #define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ #define USB_COM_vect_num 11 #define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ #define TIMER1_CAPT_vect_num 16 #define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 17 #define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 18 #define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPC_vect_num 19 #define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ #define TIMER1_OVF_vect_num 20 #define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 21 #define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 22 #define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 23 #define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 24 #define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ #define USART1_RX_vect_num 25 #define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ #define USART1_UDRE_vect_num 26 #define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ #define USART1_TX_vect_num 27 #define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ #define ANALOG_COMP_vect_num 28 #define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ #define ADC_vect_num 29 #define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ #define EE_READY_vect_num 30 #define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ #define TIMER3_CAPT_vect_num 31 #define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ #define TIMER3_COMPA_vect_num 32 #define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPB_vect_num 33 #define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPC_vect_num 34 #define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ #define TIMER3_OVF_vect_num 35 #define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ #define TWI_vect_num 36 #define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ #define SPM_READY_vect_num 37 #define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ #define TIMER4_COMPA_vect_num 38 #define TIMER4_COMPA_vect _VECTOR(38) /* Timer/Counter4 Compare Match A */ #define TIMER4_COMPB_vect_num 39 #define TIMER4_COMPB_vect _VECTOR(39) /* Timer/Counter4 Compare Match B */ #define TIMER4_COMPD_vect_num 40 #define TIMER4_COMPD_vect _VECTOR(40) /* Timer/Counter4 Compare Match D */ #define TIMER4_OVF_vect_num 41 #define TIMER4_OVF_vect _VECTOR(41) /* Timer/Counter4 Overflow */ #define TIMER4_FPF_vect_num 42 #define TIMER4_FPF_vect _VECTOR(42) /* Timer/Counter4 Fault Protection Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (43 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (1280) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x3FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x88 #endif /* _AVR_ATmega16U4_H_ */ avr-libc-1.8.0.orig/include/avr/iotn84a.h0000755000000000000000000004210011732702554014724 0ustar /* Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ /* avr/iotn84a.h - definitions for ATtiny84A */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn84a.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny84A_H_ #define _AVR_ATtiny84A_H_ 1 /* Registers and associated bit numbers. */ #define PRR _SFR_IO8(0x00) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define DIDR0 _SFR_IO8(0x01) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define ADCSRB _SFR_IO8(0x03) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADLAR 4 #define ACME 6 #define BIN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x05) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define MUX5 5 #define REFS0 6 #define REFS1 7 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define TIFR1 _SFR_IO8(0x0B) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIMSK1 _SFR_IO8(0x0C) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define USICR _SFR_IO8(0x0D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x0E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x0F) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define USIBR _SFR_IO8(0x10) #define USIBR0 0 #define USIBR1 1 #define USIBR2 2 #define USIBR3 3 #define USIBR4 4 #define USIBR5 5 #define USIBR6 6 #define USIBR7 7 #define PCMSK0 _SFR_IO8(0x12) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define GPIOR0 _SFR_IO8(0x13) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x14) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x15) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x18) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x1D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x1F) #define EEAR8 0 #define PCMSK1 _SFR_IO8(0x20) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define WDTCSR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define TCCR1C _SFR_IO8(0x22) #define FOC1B 6 #define FOC1A 7 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define TSM 7 #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_IO8(0x25) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define CLKPR _SFR_IO8(0x26) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define DWDR _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_IO8(0x29) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_IO8(0x2B) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_IO8(0x2D) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define TCCR1B _SFR_IO8(0x2E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x2F) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR0A _SFR_IO8(0x30) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define OSCCAL _SFR_IO8(0x31) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define TCNT0 _SFR_IO8(0x32) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0B _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 #define OCR0A _SFR_IO8(0x36) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR0 _SFR_IO8(0x38) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIMSK0 _SFR_IO8(0x39) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define GIFR _SFR_IO8(0x3A) #define PCIF0 4 #define PCIF1 5 #define INTF0 6 #define GIMSK _SFR_IO8(0x3B) #define PCIE0 4 #define PCIE1 5 #define INT0 6 #define OCR0B _SFR_IO8(0x3C) #define OCR0_0 0 #define OCR0_1 1 #define OCR0_2 2 #define OCR0_3 3 #define OCR0_4 4 #define OCR0_5 5 #define OCR0_6 6 #define OCR0_7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define EXT_INT0_vect_num 1 #define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ #define WATCHDOG_vect_num 4 #define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ #define TIM1_CAPT_vect_num 5 #define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIM1_COMPA_vect_num 6 #define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIM1_COMPB_vect_num 7 #define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIM1_OVF_vect_num 8 #define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIM0_COMPA_vect_num 9 #define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ #define TIM0_COMPB_vect_num 10 #define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ #define TIM0_OVF_vect_num 11 #define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ #define ANA_COMP_vect_num 12 #define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ #define ADC_vect_num 13 #define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ #define EE_RDY_vect_num 14 #define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ #define USI_STR_vect_num 15 #define USI_STR_vect _VECTOR(15) /* USI START */ #define USI_OVF_vect_num 16 #define USI_OVF_vect _VECTOR(16) /* USI Overflow */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (17 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x60) #define RAMSIZE (512) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x1FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x0C /* Device Pin Definitions */ #define ADC4_DDR DDRA #define ADC4_PORT PORTA #define ADC4_PIN PINA #define ADC4_BIT 4 #define USCK_DDR DDRA #define USCK_PORT PORTA #define USCK_PIN PINA #define USCK_BIT 4 #define SCL_DDR DDRA #define SCL_PORT PORTA #define SCL_PIN PINA #define SCL_BIT 4 #define T1_DDR DDRA #define T1_PORT PORTA #define T1_PIN PINA #define T1_BIT 4 #define PCINT4_DDR DDRA #define PCINT4_PORT PORTA #define PCINT4_PIN PINA #define PCINT4_BIT 4 #define ADC3_DDR DDRA #define ADC3_PORT PORTA #define ADC3_PIN PINA #define ADC3_BIT 3 #define T0_DDR DDRA #define T0_PORT PORTA #define T0_PIN PINA #define T0_BIT 3 #define PCINT3_DDR DDRA #define PCINT3_PORT PORTA #define PCINT3_PIN PINA #define PCINT3_BIT 3 #define ADC2_DDR DDRA #define ADC2_PORT PORTA #define ADC2_PIN PINA #define ADC2_BIT 2 #define AIN1_DDR DDRA #define AIN1_PORT PORTA #define AIN1_PIN PINA #define AIN1_BIT 2 #define PCINT2_DDR DDRA #define PCINT2_PORT PORTA #define PCINT2_PIN PINA #define PCINT2_BIT 2 #define ADC1_DDR DDRA #define ADC1_PORT PORTA #define ADC1_PIN PINA #define ADC1_BIT 1 #define AIN0_DDR DDRA #define AIN0_PORT PORTA #define AIN0_PIN PINA #define AIN0_BIT 1 #define PCINT1_DDR DDRA #define PCINT1_PORT PORTA #define PCINT1_PIN PINA #define PCINT1_BIT 1 #define ADC0_DDR DDRA #define ADC0_PORT PORTA #define ADC0_PIN PINA #define ADC0_BIT 0 #define PCINT0_DDR DDRA #define PCINT0_PORT PORTA #define PCINT0_PIN PINA #define PCINT0_BIT 0 #define PCINT8_DDR DDRB #define PCINT8_PORT PORTB #define PCINT8_PIN PINB #define PCINT8_BIT 0 #define PCINT9_DDR DDRB #define PCINT9_PORT PORTB #define PCINT9_PIN PINB #define PCINT9_BIT 1 #define PCINT11_DDR DDRB #define PCINT11_PORT PORTB #define PCINT11_PIN PINB #define PCINT11_BIT 3 #define dW_DDR DDRB #define dW_PORT PORTB #define dW_PIN PINB #define dW_BIT 3 #define PCINT10_DDR DDRB #define PCINT10_PORT PORTB #define PCINT10_PIN PINB #define PCINT10_BIT 2 #define INT0_DDR DDRB #define INT0_PORT PORTB #define INT0_PIN PINB #define INT0_BIT 2 #define OC0A_DDR DDRB #define OC0A_PORT PORTB #define OC0A_PIN PINB #define OC0A_BIT 2 #define CKOUT_DDR DDRB #define CKOUT_PORT PORTB #define CKOUT_PIN PINB #define CKOUT_BIT 2 #define PCINT7_DDR DDRA #define PCINT7_PORT PORTA #define PCINT7_PIN PINA #define PCINT7_BIT 7 #define ICP1_DDR DDRA #define ICP1_PORT PORTA #define ICP1_PIN PINA #define ICP1_BIT 7 #define OC0B_DDR DDRA #define OC0B_PORT PORTA #define OC0B_PIN PINA #define OC0B_BIT 7 #define ADC7_DDR DDRA #define ADC7_PORT PORTA #define ADC7_PIN PINA #define ADC7_BIT 7 #define PCINT6_DDR DDRA #define PCINT6_PORT PORTA #define PCINT6_PIN PINA #define PCINT6_BIT 6 #define OC1A_DDR DDRA #define OC1A_PORT PORTA #define OC1A_PIN PINA #define OC1A_BIT 6 #define DI_DDR DDRA #define DI_PORT PORTA #define DI_PIN PINA #define DI_BIT 6 #define SDA_DDR DDRA #define SDA_PORT PORTA #define SDA_PIN PINA #define SDA_BIT 6 #define MOSI_DDR DDRA #define MOSI_PORT PORTA #define MOSI_PIN PINA #define MOSI_BIT 6 #define ADC6_DDR DDRA #define ADC6_PORT PORTA #define ADC6_PIN PINA #define ADC6_BIT 6 #define ADC5_DDR DDRA #define ADC5_PORT PORTA #define ADC5_PIN PINA #define ADC5_BIT 5 #define DO_DDR DDRA #define DO_PORT PORTA #define DO_PIN PINA #define DO_BIT 5 #define MISO_DDR DDRA #define MISO_PORT PORTA #define MISO_PIN PINA #define MISO_BIT 5 #define OC1B_DDR DDRA #define OC1B_PORT PORTA #define OC1B_PIN PINA #define OC1B_BIT 5 #define PCINT5_DDR DDRA #define PCINT5_PORT PORTA #define PCINT5_PIN PINA #define PCINT5_BIT 5 #endif /* _AVR_ATtiny84A_H_ */ avr-libc-1.8.0.orig/include/avr/iom64hve.h0000644000000000000000000005055611732702554015112 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom64hve.h 2086 2009-12-15 03:24:16Z arcanum $ */ /* avr/iom64hve.h - definitions for ATmega64HVE */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom64hve.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega64HVE_H_ #define _AVR_ATmega64HVE_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 3 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 3 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define ICS0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define TCNT0 _SFR_IO16(0x26) #define TCNT0L _SFR_IO8(0x26) #define TCNT0L0 0 #define TCNT0L1 1 #define TCNT0L2 2 #define TCNT0L3 3 #define TCNT0L4 4 #define TCNT0L5 5 #define TCNT0L6 6 #define TCNT0L7 7 #define TCNT0H _SFR_IO8(0x27) #define TCNT0H0 0 #define TCNT0H1 1 #define TCNT0H2 2 #define TCNT0H3 3 #define TCNT0H4 4 #define TCNT0H5 5 #define TCNT0H6 6 #define TCNT0H7 7 #define OCR0A _SFR_IO8(0x28) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0B _SFR_IO8(0x29) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define TCCR0C _SFR_IO8(0x2F) #define OCDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BODRF 2 #define WDRF 3 #define OCDRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define CKOE 5 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define LBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPCE 7 #define WUTCSR _SFR_MEM8(0x62) #define WUTP0 0 #define WUTP1 1 #define WUTP2 2 #define WUTE 3 #define WUTR 4 #define WUTIE 6 #define WUTIF 7 #define WDTCLR _SFR_MEM8(0x63) #define WDCLE 0 #define WDCL0 1 #define WDCL1 2 #define PRR0 _SFR_MEM8(0x64) #define PRTIM0 0 #define PRTIM1 1 #define PRSPI 2 #define PRLIN 3 #define SOSCCALA _SFR_MEM8(0x66) #define SCALA0 0 #define SCALA1 1 #define SCALA2 2 #define SCALA3 3 #define SCALA4 4 #define SCALA5 5 #define SCALA6 6 #define SCALA7 7 #define SOSCCALB _SFR_MEM8(0x67) #define SCALB0 0 #define SCALB1 1 #define SCALB2 2 #define SCALB3 3 #define SCALB4 4 #define SCALB5 5 #define SCALB6 6 #define SCALB7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT2 0 #define PCINT3 1 #define PCINT4 2 #define PCINT5 3 #define PCINT6 4 #define PCINT7 5 #define PCINT8 6 #define PCINT9 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 3 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 3 #define DIDR0 _SFR_MEM8(0x7E) #define PA0DID 0 #define PA1DID 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define ICS1 3 #define ICES1 4 #define ICNC1 5 #define ICEN1 6 #define TCW1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define TCCR1C _SFR_MEM8(0x82) #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define OCR1A _SFR_MEM8(0x88) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define OCR1B _SFR_MEM8(0x89) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define LINCR _SFR_MEM8(0xC0) #define LCMD0 0 #define LCMD1 1 #define LCMD2 2 #define LENA 3 #define LCONF0 4 #define LCONF1 5 #define LIN13 6 #define LSWRES 7 #define LINSIR _SFR_MEM8(0xC1) #define LRXOK 0 #define LTXOK 1 #define LIDOK 2 #define LERR 3 #define LBUSY 4 #define LIDST0 5 #define LIDST1 6 #define LIDST2 7 #define LINENIR _SFR_MEM8(0xC2) #define LENRXOK 0 #define LENTXOK 1 #define LENIDOK 2 #define LENERR 3 #define LINERR _SFR_MEM8(0xC3) #define LBERR 0 #define LCERR 1 #define LPERR 2 #define LSERR 3 #define LFERR 4 #define LOVERR 5 #define LTOERR 6 #define LABORT 7 #define LINBTR _SFR_MEM8(0xC4) #define LBT0 0 #define LBT1 1 #define LBT2 2 #define LBT3 3 #define LBT4 4 #define LBT5 5 #define LDISR 7 #define LINBRR _SFR_MEM16(0xC5) #define LINBRRL _SFR_MEM8(0xC5) #define LDIV0 0 #define LDIV1 1 #define LDIV2 2 #define LDIV3 3 #define LDIV4 4 #define LDIV5 5 #define LDIV6 6 #define LDIV7 7 #define LINBRRH _SFR_MEM8(0xC6) #define LDIV8 0 #define LDIV9 1 #define LDIV10 2 #define LDIV11 3 #define LINDLR _SFR_MEM8(0xC7) #define LRXDL0 0 #define LRXDL1 1 #define LRXDL2 2 #define LRXDL3 3 #define LTXDL0 4 #define LTXDL1 5 #define LTXDL2 6 #define LTXDL3 7 #define LINIDR _SFR_MEM8(0xC8) #define LID0 0 #define LID1 1 #define LID2 2 #define LID3 3 #define LID4 4 #define LID5 5 #define LP0 6 #define LP1 7 #define LINSEL _SFR_MEM8(0xC9) #define LINDX0 0 #define LINDX1 1 #define LINDX2 2 #define LAINC 3 #define LINDAT _SFR_MEM8(0xCA) #define LDATA0 0 #define LDATA1 1 #define LDATA2 2 #define LDATA3 3 #define LDATA4 4 #define LDATA5 5 #define LDATA6 6 #define LDATA7 7 #define BGCSRA _SFR_MEM8(0xD1) #define BGSC0 0 #define BGSC1 1 #define BGSC2 2 #define BGCRB _SFR_MEM8(0xD2) #define BGCL0 0 #define BGCL1 1 #define BGCL2 2 #define BGCL3 3 #define BGCL4 4 #define BGCL5 5 #define BGCL6 6 #define BGCL7 7 #define BGCRA _SFR_MEM8(0xD3) #define BGCN0 0 #define BGCN1 1 #define BGCN2 2 #define BGCN3 3 #define BGCN4 4 #define BGCN5 5 #define BGCN6 6 #define BGCN7 7 #define BGLR _SFR_MEM8(0xD4) #define BGPL 0 #define BGPLE 1 #define PLLCSR _SFR_MEM8(0xD8) #define PLLCIE 0 #define PLLCIF 1 #define LOCK 4 #define SWEN 5 #define PBOV _SFR_MEM8(0xDC) #define PBOE0 0 #define PBOE3 3 #define PBOVCE 7 #define ADSCSRA _SFR_MEM8(0xE0) #define SCMD0 0 #define SCMD1 1 #define SBSY 2 #define ADSCSRB _SFR_MEM8(0xE1) #define CADICRB 0 #define CADACRB 1 #define CADICPS 2 #define VADICRB 4 #define VADACRB 5 #define VADICPS 6 #define ADCRA _SFR_MEM8(0xE2) #define CKSEL 0 #define ADCMS0 1 #define ADCMS1 2 #define ADPSEL 3 #define ADCRB _SFR_MEM8(0xE3) #define ADADES0 0 #define ADADES1 1 #define ADADES2 2 #define ADIDES0 3 #define ADIDES1 4 #define ADCRC _SFR_MEM8(0xE4) #define CADRCT0 0 #define CADRCT1 1 #define CADRCT2 2 #define CADRCT3 3 #define CADRCM0 4 #define CADRCM1 5 #define CADEN 7 #define ADCRD _SFR_MEM8(0xE5) #define CADDSEL 0 #define CADPDM0 1 #define CADPDM1 2 #define CADG0 3 #define CADG1 4 #define CADG2 5 #define ADCRE _SFR_MEM8(0xE6) #define VADMUX0 0 #define VADMUX1 1 #define VADMUX2 2 #define VADPDM0 3 #define VADPDM1 4 #define VADREFS 5 #define VADEN 7 #define ADIFR _SFR_MEM8(0xE7) #define CADICIF 0 #define CADACIF 1 #define CADRCIF 2 #define VADICIF 4 #define VADACIF 5 #define ADIMR _SFR_MEM8(0xE8) #define CADICIE 0 #define CADACIE 1 #define CADRCIE 2 #define VADICIE 4 #define VADACIE 5 #define CADRCL _SFR_MEM16(0xE9) #define CADRCLL _SFR_MEM8(0xE9) #define CADRCL0 0 #define CADRCL1 1 #define CADRCL2 2 #define CADRCL3 3 #define CADRCL4 4 #define CADRCL5 5 #define CADRCL6 6 #define CADRCL7 7 #define CADRCLH _SFR_MEM8(0xEA) #define CADRCL8 0 #define CADRCL9 1 #define CADRCL10 2 #define CADRCL11 3 #define CADRCL12 4 #define CADRCL13 5 #define CADRCL14 6 #define CADRCL15 7 #define CADIC _SFR_MEM16(0xEB) #define CADICL _SFR_MEM8(0xEB) #define CADIC0 0 #define CADIC1 1 #define CADIC2 2 #define CADIC3 3 #define CADIC4 4 #define CADIC5 5 #define CADIC6 6 #define CADIC7 7 #define CADICH _SFR_MEM8(0xEC) #define CADIC8 0 #define CADIC9 1 #define CADIC10 2 #define CADIC11 3 #define CADIC12 4 #define CADIC13 5 #define CADIC14 6 #define CADIC15 7 #define CADAC0 _SFR_MEM8(0xED) #define CADAC00 0 #define CADAC01 1 #define CADAC02 2 #define CADAC03 3 #define CADAC04 4 #define CADAC05 5 #define CADAC06 6 #define CADAC07 7 #define CADAC1 _SFR_MEM8(0xEE) #define CADAC08 0 #define CADAC09 1 #define CADAC10 2 #define CADAC11 3 #define CADAC12 4 #define CADAC13 5 #define CADAC14 6 #define CADAC15 7 #define CADAC2 _SFR_MEM8(0xEF) #define CADAC16 0 #define CADAC17 1 #define CADAC18 2 #define CADAC19 3 #define CADAC20 4 #define CADAC21 5 #define CADAC22 6 #define CADAC23 7 #define CADAC3 _SFR_MEM8(0xF0) #define CADAC24 0 #define CADAC25 1 #define CADAC26 2 #define CADAC27 3 #define CADAC28 4 #define CADAC29 5 #define CADAC30 6 #define CADAC31 7 #define VADIC _SFR_MEM16(0xF1) #define VADICL _SFR_MEM8(0xF1) #define VADIC0 0 #define VADIC1 1 #define VADIC2 2 #define VADIC3 3 #define VADIC4 4 #define VADIC5 5 #define VADIC6 6 #define VADIC7 7 #define VADICH _SFR_MEM8(0xF2) #define VADIC8 0 #define VADIC9 1 #define VADIC10 2 #define VADIC11 3 #define VADIC12 4 #define VADIC13 5 #define VADIC14 6 #define VADIC15 7 #define VADAC0 _SFR_MEM8(0xF3) #define VADAC00 0 #define VADAC01 1 #define VADAC02 2 #define VADAC03 3 #define VADAC04 4 #define VADAC05 5 #define VADAC06 6 #define VADAC07 7 #define VADAC1 _SFR_MEM8(0xF4) #define VADAC08 0 #define VADAC09 1 #define VADAC10 2 #define VADAC11 3 #define VADAC12 4 #define VADAC13 5 #define VADAC14 6 #define VADAC15 7 #define VADAC2 _SFR_MEM8(0xF5) #define VADAC16 0 #define VADAC17 1 #define VADAC18 2 #define VADAC19 3 #define VADAC20 4 #define VADAC21 5 #define VADAC22 6 #define VADAC23 7 #define VADAC3 _SFR_MEM8(0xF6) #define VADAC24 0 #define VADAC25 1 #define VADAC26 2 #define VADAC27 3 #define VADAC28 4 #define VADAC29 5 #define VADAC30 6 #define VADAC31 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt 0 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt 1 */ #define WDT_vect_num 4 #define WDT_vect _VECTOR(4) /* Watchdog Timeout Interrupt */ #define WAKEUP_vect_num 5 #define WAKEUP_vect _VECTOR(5) /* Wakeup Timer Overflow */ #define TIMER1_IC_vect_num 6 #define TIMER1_IC_vect _VECTOR(6) /* Timer 1 Input capture */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) /* Timer 1 Compare Match A */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) /* Timer 1 Compare Match B */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) /* Timer 1 overflow */ #define TIMER0_IC_vect_num 10 #define TIMER0_IC_vect _VECTOR(10) /* Timer 0 Input Capture */ #define TIMER0_COMPA_vect_num 11 #define TIMER0_COMPA_vect _VECTOR(11) /* Timer 0 Comapre Match A */ #define TIMER0_COMPB_vect_num 12 #define TIMER0_COMPB_vect _VECTOR(12) /* Timer 0 Compare Match B */ #define TIMER0_OVF_vect_num 13 #define TIMER0_OVF_vect _VECTOR(13) /* Timer 0 Overflow */ #define LIN_STATUS_vect_num 14 #define LIN_STATUS_vect _VECTOR(14) /* LIN Status Interrupt */ #define LIN_ERROR_vect_num 15 #define LIN_ERROR_vect _VECTOR(15) /* LIN Error Interrupt */ #define SPI_STC_vect_num 16 #define SPI_STC_vect _VECTOR(16) /* SPI Serial transfer complete */ #define VADC_CONV_vect_num 17 #define VADC_CONV_vect _VECTOR(17) /* Voltage ADC Instantaneous Conversion Complete */ #define VADC_ACC_vect_num 18 #define VADC_ACC_vect _VECTOR(18) /* Voltage ADC Accumulated Conversion Complete */ #define CADC_CONV_vect_num 19 #define CADC_CONV_vect _VECTOR(19) /* C-ADC Instantaneous Conversion Complete */ #define CADC_REG_CUR_vect_num 20 #define CADC_REG_CUR_vect _VECTOR(20) /* C-ADC Regular Current */ #define CADC_ACC_vect_num 21 #define CADC_ACC_vect _VECTOR(21) /* C-ADC Accumulated Conversion Complete */ #define EE_READY_vect_num 22 #define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ #define SPM_vect_num 23 #define SPM_vect _VECTOR(23) /* SPM Ready */ #define PLL_vect_num 24 #define PLL_vect _VECTOR(24) /* PLL Lock Change Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (25 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (4096) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (NA) #define XRAMEND (RAMEND) #define E2END (0x3FF) #define E2PAGESIZE (4) #define FLASHEND (0xFFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ #define FUSE_SUT0 (unsigned char)~_BV(1) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(2) /* Select start-up time */ #define FUSE_CKDIV8 (unsigned char)~_BV(3) /* Divide clock by 8 */ #define FUSE_BODEN (unsigned char)~_BV(4) /* Enable BOD */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ #define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_OSCSEL0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ #define HFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x10 /* Device Pin Definitions */ #define PV2_DDR DDRV #define PV2_PORT PORTV #define PV2_PIN PINV #define PV2_BIT 2 #define PV1_DDR DDRV #define PV1_PORT PORTV #define PV1_PIN PINV #define PV1_BIT 1 #define NV_DDR DDRNV #define NV_PORT PORTNV #define NV_PIN PINNV #define NV_BIT NV #define VFET_DDR DDRVFET #define VFET_PORT PORTVFET #define VFET_PIN PINVFET #define VFET_BIT VFET #define CF1P_DDR DDRCF1P #define CF1P_PORT PORTCF1P #define CF1P_PIN PINCF1P #define CF1P_BIT CF1P #define CF1N_DDR DDRCF1N #define CF1N_PORT PORTCF1N #define CF1N_PIN PINCF1N #define CF1N_BIT CF1N #define CF2P_DDR DDRCF2P #define CF2P_PORT PORTCF2P #define CF2P_PIN PINCF2P #define CF2P_BIT CF2P #define CF2N_DDR DDRCF2N #define CF2N_PORT PORTCF2N #define CF2N_PIN PINCF2N #define CF2N_BIT CF2N #define VREG_DDR DDRVREG #define VREG_PORT PORTVREG #define VREG_PIN PINVREG #define VREG_BIT VREG #define VREF_DDR DDRVREF #define VREF_PORT PORTVREF #define VREF_PIN PINVREF #define VREF_BIT VREF #define VREFGND_DDR DDRVREFGND #define VREFGND_PORT PORTVREFGND #define VREFGND_PIN PINVREFGND #define VREFGND_BIT VREFGND #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI #define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI #define NI_PIN PINNI #define NI_BIT NI #define PA0_DDR DDRA #define PA0_PORT PORTA #define PA0_PIN PINA #define PA0_BIT 0 #define PA1_DDR DDRA #define PA1_PORT PORTA #define PA1_PIN PINA #define PA1_BIT 1 #define PA2_DDR DDRA #define PA2_PORT PORTA #define PA2_PIN PINA #define PA2_BIT 2 #define PB0_DDR DDRB #define PB0_PORT PORTB #define PB0_PIN PINB #define PB0_BIT 0 #define PB1_DDR DDRB #define PB1_PORT PORTB #define PB1_PIN PINB #define PB1_BIT 1 #define PB2_DDR DDRB #define PB2_PORT PORTB #define PB2_PIN PINB #define PB2_BIT 2 #define PB3_DDR DDRB #define PB3_PORT PORTB #define PB3_PIN PINB #define PB3_BIT 3 #define PC0_DDR DDRC #define PC0_PORT PORTC #define PC0_PIN PINC #define PC0_BIT 0 #define BATT_DDR DDRBATT #define BATT_PORT PORTBATT #define BATT_PIN PINBATT #define BATT_BIT BATT #define OC_DDR DDROC #define OC_PORT PORTOC #define OC_PIN PINOC #define OC_BIT OC #endif /* _AVR_ATmega64HVE_H_ */ avr-libc-1.8.0.orig/include/avr/iox256d3.h0000644000000000000000000071371711732702554014741 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox256d3.h 2162 2010-06-11 17:26:12Z arcanum $ */ /* avr/iox256d3.h - definitions for ATxmega256D3 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox256d3.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega256D3_H_ #define _AVR_ATxmega256D3_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */ BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* ACD Temporary Register */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_TEMP _SFR_MEM8(0x0207) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ #define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ #define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_bm 0x01 /* Event Action Select bit mask. */ #define ADC_EVACT_bp 0 /* Event Action Select bit position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRLA bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (114 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (270336) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (262144) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x3E000) #define APPTABLE_SECTION_SIZE (8192) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x40000) #define BOOT_SECTION_SIZE (8192) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (24576) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (4096) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (16384) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (4096) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x98 #define SIGNATURE_2 0x44 #endif /* _AVR_ATxmega256D3_H_ */ avr-libc-1.8.0.orig/include/avr/iotn10.h0000644000000000000000000002437011732702554014556 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn10.h 2063 2009-11-18 22:06:28Z arcanum $ */ /* avr/iotn10.h - definitions for ATtiny10 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn10.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny10_H_ #define _AVR_ATtiny10_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x00) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x01) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x02) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PUEB _SFR_IO8(0x03) #define PUEB0 0 #define PUEB1 1 #define PUEB2 2 #define PUEB3 3 #define PORTCR _SFR_IO8(0x0C) #define BBMB 1 #define PCMSK _SFR_IO8(0x10) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCIFR _SFR_IO8(0x11) #define PCIF0 0 #define PCICR _SFR_IO8(0x12) #define PCIE0 0 #define EIMSK _SFR_IO8(0x13) #define INT0 0 #define EIFR _SFR_IO8(0x14) #define INTF0 0 #define EICRA _SFR_IO8(0x15) #define ISC00 0 #define ISC01 1 #define DIDR0 _SFR_IO8(0x17) #define ADC0D 0 #define AIN0D 0 #define ADC1D 1 #define AIN1D 1 #define ADC2D 2 #define ADC3D 3 #define ADCL _SFR_IO8(0x19) #define ADC0 0 #define ADC1 1 #define ADC2 2 #define ADC3 3 #define ADC4 4 #define ADC5 5 #define ADC6 6 #define ADC7 7 #define ADMUX _SFR_IO8(0x1B) #define MUX0 0 #define MUX1 1 #define ADCSRB _SFR_IO8(0x1C) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADCSRA _SFR_IO8(0x1D) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ACSR _SFR_IO8(0x1F) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACD 7 #define ICR0 _SFR_IO16(0x22) #define ICR0L _SFR_IO8(0x22) #define ICR0_0 0 #define ICR0_1 1 #define ICR0_2 2 #define ICR0_3 3 #define ICR0_4 4 #define ICR0_5 5 #define ICR0_6 6 #define ICR0_7 7 #define ICR0H _SFR_IO8(0x23) #define ICR0_8 0 #define ICR0_9 1 #define ICR0_10 2 #define ICR0_11 3 #define ICR0_12 4 #define ICR0_13 5 #define ICR0_14 6 #define ICR0_15 7 #define OCR0B _SFR_IO16(0x24) #define OCR0BL _SFR_IO8(0x24) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define OCR0BH _SFR_IO8(0x25) #define OCR0B8 0 #define OCR0B9 1 #define OCR0B10 2 #define OCR0B11 3 #define OCR0B12 4 #define OCR0B13 5 #define OCR0B14 6 #define OCR0B15 7 #define OCR0A _SFR_IO16(0x26) #define OCR0AL _SFR_IO8(0x26) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0AH _SFR_IO8(0x27) #define OCR0A8 0 #define OCR0A9 1 #define OCR0A10 2 #define OCR0A11 3 #define OCR0A12 4 #define OCR0A13 5 #define OCR0A14 6 #define OCR0A15 7 #define TCNT0 _SFR_IO16(0x28) #define TCNT0L _SFR_IO8(0x28) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCNT0H _SFR_IO8(0x29) #define TCNT0_8 0 #define TCNT0_9 1 #define TCNT0_10 2 #define TCNT0_11 3 #define TCNT0_12 4 #define TCNT0_13 5 #define TCNT0_14 6 #define TCNT0_15 7 #define TIFR0 _SFR_IO8(0x2A) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 5 #define TIMSK0 _SFR_IO8(0x2B) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 5 #define TCCR0C _SFR_IO8(0x2C) #define FOC0B 6 #define FOC0A 7 #define TCCR0B _SFR_IO8(0x2D) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define WGM03 4 #define ICES0 6 #define ICNC0 7 #define TCCR0A _SFR_IO8(0x2E) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define GTCCR _SFR_IO8(0x2F) #define PSR 0 #define TSM 7 #define WDTCSR _SFR_IO8(0x31) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define NVMCSR _SFR_IO8(0x32) #define NVMBSY 7 #define NVMCMD _SFR_IO8(0x33) #define NVMCMD0 0 #define NVMCMD1 1 #define NVMCMD2 2 #define NVMCMD3 3 #define NVMCMD4 4 #define NVMCMD5 5 #define VLMCSR _SFR_IO8(0x34) #define VLM0 0 #define VLM1 1 #define VLM2 2 #define VLMIE 6 #define VLMF 7 #define PRR _SFR_IO8(0x35) #define PRTIM0 0 #define PRADC 1 #define CLKPSR _SFR_IO8(0x36) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKMSR _SFR_IO8(0x37) #define CLKMS0 0 #define CLKMS1 1 #define OSCCAL _SFR_IO8(0x39) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define SMCR _SFR_IO8(0x3A) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define RSTFLR _SFR_IO8(0x3B) #define PORF 0 #define EXTRF 1 #define WDRF 3 #define CCP _SFR_IO8(0x3C) #define CCP0 0 #define CCP1 1 #define CCP2 2 #define CCP3 3 #define CCP4 4 #define CCP5 5 #define CCP6 6 #define CCP7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define TIM0_CAPT_vect_num 3 #define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ #define TIM0_OVF_vect_num 4 #define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ #define TIM0_COMPA_vect_num 5 #define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ #define TIM0_COMPB_vect_num 6 #define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ #define ANA_COMP_vect_num 7 #define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Watchdog Time-out */ #define VLM_vect_num 9 #define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ #define ADC_vect_num 10 #define ADC_vect _VECTOR(10) /* ADC Conversion Complete */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (11 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (32) #define RAMSTART (0x40) #define RAMSIZE (32) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x0) #define E2PAGESIZE (0) #define FLASHEND (0x3FF) /* Fuses */ #define FUSE_MEMORY_SIZE 0 /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x03 /* Device Pin Definitions */ #define SPDATA_DDR DDRCINT #define SPDATA_PORT PORTCINT #define SPDATA_PIN PINCINT #define SPDATA_BIT INT0 #define OC0A_DDR DDRCINT #define OC0A_PORT PORTCINT #define OC0A_PIN PINCINT #define OC0A_BIT INT0 #define ADC0_DDR DDRCINT #define ADC0_PORT PORTCINT #define ADC0_PIN PINCINT #define ADC0_BIT INT0 #define AIN0_DDR DDRCINT #define AIN0_PORT PORTCINT #define AIN0_PIN PINCINT #define AIN0_BIT INT0 #define PB0_DDR DDRCINT #define PB0_PORT PORTCINT #define PB0_PIN PINCINT #define PB0_BIT INT0 #define SPCLK_DDR DDRCINT #define SPCLK_PORT PORTCINT #define SPCLK_PIN PINCINT #define SPCLK_BIT INT1 #define CLKI_DDR DDRCINT #define CLKI_PORT PORTCINT #define CLKI_PIN PINCINT #define CLKI_BIT INT1 #define ICP0_DDR DDRCINT #define ICP0_PORT PORTCINT #define ICP0_PIN PINCINT #define ICP0_BIT INT1 #define OC0B_DDR DDRCINT #define OC0B_PORT PORTCINT #define OC0B_PIN PINCINT #define OC0B_BIT INT1 #define ADC1_DDR DDRCINT #define ADC1_PORT PORTCINT #define ADC1_PIN PINCINT #define ADC1_BIT INT1 #define AIN1_DDR DDRCINT #define AIN1_PORT PORTCINT #define AIN1_PIN PINCINT #define AIN1_BIT INT1 #define PB1_DDR DDRCINT #define PB1_PORT PORTCINT #define PB1_PIN PINCINT #define PB1_BIT INT1 #define CLKO_DDR DDRT #define CLKO_PORT PORTT #define CLKO_PIN PINT #define CLKO_BIT T0 #define PCINT2_DDR DDRT #define PCINT2_PORT PORTT #define PCINT2_PIN PINT #define PCINT2_BIT T0 #define INT0_DDR DDRT #define INT0_PORT PORTT #define INT0_PIN PINT #define INT0_BIT T0 #define ADC2_DDR DDRT #define ADC2_PORT PORTT #define ADC2_PIN PINT #define ADC2_BIT T0 #define PB2_DDR DDRT #define PB2_PORT PORTT #define PB2_PIN PINT #define PB2_BIT T0 #define PCINT3_DDR DDRRESET #define PCINT3_PORT PORTRESET #define PCINT3_PIN PINRESET #define PCINT3_BIT RESET #define ADC3_DDR DDRRESET #define ADC3_PORT PORTRESET #define ADC3_PIN PINRESET #define ADC3_BIT RESET #define PB3_DDR DDRRESET #define PB3_PORT PORTRESET #define PB3_PIN PINRESET #define PB3_BIT RESET #endif /* _AVR_ATtiny10_H_ */ avr-libc-1.8.0.orig/include/avr/iom88pa.h0000644000000000000000000005716111732702554014735 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom88pa.h 2035 2009-11-02 02:44:17Z arcanum $ */ /* avr/iom88pa.h - definitions for ATmega88PA */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom88pa.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega88PA_H_ #define _AVR_ATmega88PA_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 #define BODS 6 #define SPMCSR _SFR_IO8(0x37) #define SELFPRGEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2A_0 0 #define OCR2A_1 1 #define OCR2A_2 2 #define OCR2A_3 3 #define OCR2A_4 4 #define OCR2A_5 5 #define OCR2A_6 6 #define OCR2A_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2B_0 0 #define OCR2B_1 1 #define OCR2B_2 2 #define OCR2B_3 3 #define OCR2B_4 4 #define OCR2B_5 5 #define OCR2B_6 6 #define OCR2B_7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL01 7 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define _UBRR0 0 #define _UBRR1 1 #define UBRR2 2 #define UBRR3 3 #define UBRR4 4 #define UBRR5 5 #define UBRR6 6 #define UBRR7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR8 0 #define UBRR9 1 #define UBRR10 2 #define UBRR11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR0_0 0 #define UDR0_1 1 #define UDR0_2 2 #define UDR0_3 3 #define UDR0_4 4 #define UDR0_5 5 #define UDR0_6 6 #define UDR0_7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ #define PCINT2_vect_num 5 #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ #define WDT_vect_num 6 #define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 7 #define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 8 #define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ #define TIMER2_OVF_vect_num 9 #define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 10 #define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 11 #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 12 #define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ #define TIMER0_OVF_vect_num 16 #define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ #define SPI_STC_vect_num 17 #define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ #define USART_RX_vect_num 18 #define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ #define USART_UDRE_vect_num 19 #define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ #define USART_TX_vect_num 20 #define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ #define ADC_vect_num 21 #define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ #define EE_READY_vect_num 22 #define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ #define TWI_vect_num 24 #define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ #define SPM_Ready_vect_num 25 #define SPM_Ready_vect _VECTOR(25) /* Store Program Memory Read */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (26 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x100) #define RAMSIZE (1024) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x1FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select reset vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select boot size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select boot size */ #define EFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x0F /* Device Pin Definitions */ #define PCINT19_DDR DDRD #define PCINT19_PORT PORTD #define PCINT19_PIN PIND #define PCINT19_BIT 3 #define OC2B_DDR DDRD #define OC2B_PORT PORTD #define OC2B_PIN PIND #define OC2B_BIT 3 #define INT1_DDR DDRD #define INT1_PORT PORTD #define INT1_PIN PIND #define INT1_BIT 3 #define XCK_DDR DDRD #define XCK_PORT PORTD #define XCK_PIN PIND #define XCK_BIT 4 #define T0_DDR DDRD #define T0_PORT PORTD #define T0_PIN PIND #define T0_BIT 4 #define PCINT20_DDR DDRD #define PCINT20_PORT PORTD #define PCINT20_PIN PIND #define PCINT20_BIT 4 #define PCINT6_DDR DDRB #define PCINT6_PORT PORTB #define PCINT6_PIN PINB #define PCINT6_BIT 6 #define PCINT7_DDR DDRB #define PCINT7_PORT PORTB #define PCINT7_PIN PINB #define PCINT7_BIT 7 #define T1_DDR DDRD #define T1_PORT PORTD #define T1_PIN PIND #define T1_BIT 5 #define OC0B_DDR DDRD #define OC0B_PORT PORTD #define OC0B_PIN PIND #define OC0B_BIT 5 #define PCINT21_DDR DDRD #define PCINT21_PORT PORTD #define PCINT21_PIN PIND #define PCINT21_BIT 5 #define AIN0_DDR DDRD #define AIN0_PORT PORTD #define AIN0_PIN PIND #define AIN0_BIT 6 #define OC0A_DDR DDRD #define OC0A_PORT PORTD #define OC0A_PIN PIND #define OC0A_BIT 6 #define PCINT22_DDR DDRD #define PCINT22_PORT PORTD #define PCINT22_PIN PIND #define PCINT22_BIT 6 #define AIN1_DDR DDRD #define AIN1_PORT PORTD #define AIN1_PIN PIND #define AIN1_BIT 7 #define PCINT23_DDR DDRD #define PCINT23_PORT PORTD #define PCINT23_PIN PIND #define PCINT23_BIT 7 #define ICP1_DDR DDRB #define ICP1_PORT PORTB #define ICP1_PIN PINB #define ICP1_BIT 0 #define CLKO_DDR DDRB #define CLKO_PORT PORTB #define CLKO_PIN PINB #define CLKO_BIT 0 #define PCINT0_DDR DDRB #define PCINT0_PORT PORTB #define PCINT0_PIN PINB #define PCINT0_BIT 0 #define OC1A_DDR DDRB #define OC1A_PORT PORTB #define OC1A_PIN PINB #define OC1A_BIT 1 #define PCINT1_DDR DDRB #define PCINT1_PORT PORTB #define PCINT1_PIN PINB #define PCINT1_BIT 1 #define SS_DDR DDRB #define SS_PORT PORTB #define SS_PIN PINB #define SS_BIT 2 #define OC1B_DDR DDRB #define OC1B_PORT PORTB #define OC1B_PIN PINB #define OC1B_BIT 2 #define PCINT2_DDR DDRB #define PCINT2_PORT PORTB #define PCINT2_PIN PINB #define PCINT2_BIT 2 #define MOSI_DDR DDRB #define MOSI_PORT PORTB #define MOSI_PIN PINB #define MOSI_BIT 3 #define OC2A_DDR DDRB #define OC2A_PORT PORTB #define OC2A_PIN PINB #define OC2A_BIT 3 #define PCINT3_DDR DDRB #define PCINT3_PORT PORTB #define PCINT3_PIN PINB #define PCINT3_BIT 3 #define MISO_DDR DDRB #define MISO_PORT PORTB #define MISO_PIN PINB #define MISO_BIT 4 #define PCINT4_DDR DDRB #define PCINT4_PORT PORTB #define PCINT4_PIN PINB #define PCINT4_BIT 4 #define SCK_DDR DDRB #define SCK_PORT PORTB #define SCK_PIN PINB #define SCK_BIT 5 #define PCINT5_DDR DDRB #define PCINT5_PORT PORTB #define PCINT5_PIN PINB #define PCINT5_BIT 5 #define ADC6_DDR DDRADC #define ADC6_PORT PORTADC #define ADC6_PIN PINADC #define ADC6_BIT ADC6 #define ADC7_DDR DDRADC #define ADC7_PORT PORTADC #define ADC7_PIN PINADC #define ADC7_BIT ADC7 #define ADC0_DDR DDRC #define ADC0_PORT PORTC #define ADC0_PIN PINC #define ADC0_BIT 0 #define PCINT8_DDR DDRC #define PCINT8_PORT PORTC #define PCINT8_PIN PINC #define PCINT8_BIT 0 #define ADC1_DDR DDRC #define ADC1_PORT PORTC #define ADC1_PIN PINC #define ADC1_BIT 1 #define PCINT9_DDR DDRC #define PCINT9_PORT PORTC #define PCINT9_PIN PINC #define PCINT9_BIT 1 #define ADC2_DDR DDRC #define ADC2_PORT PORTC #define ADC2_PIN PINC #define ADC2_BIT 2 #define PCINT10_DDR DDRC #define PCINT10_PORT PORTC #define PCINT10_PIN PINC #define PCINT10_BIT 2 #define ADC3_DDR DDRC #define ADC3_PORT PORTC #define ADC3_PIN PINC #define ADC3_BIT 3 #define PCINT11_DDR DDRC #define PCINT11_PORT PORTC #define PCINT11_PIN PINC #define PCINT11_BIT 3 #define ADC4_DDR DDRC #define ADC4_PORT PORTC #define ADC4_PIN PINC #define ADC4_BIT 4 #define SDA_DDR DDRC #define SDA_PORT PORTC #define SDA_PIN PINC #define SDA_BIT 4 #define PCINT12_DDR DDRC #define PCINT12_PORT PORTC #define PCINT12_PIN PINC #define PCINT12_BIT 4 #define ADC5_DDR DDRC #define ADC5_PORT PORTC #define ADC5_PIN PINC #define ADC5_BIT 5 #define SCL_DDR DDRC #define SCL_PORT PORTC #define SCL_PIN PINC #define SCL_BIT 5 #define PCINT13_DDR DDRC #define PCINT13_PORT PORTC #define PCINT13_PIN PINC #define PCINT13_BIT 5 #define PCINT14_DDR DDRC #define PCINT14_PORT PORTC #define PCINT14_PIN PINC #define PCINT14_BIT 6 #define RXD_DDR DDRD #define RXD_PORT PORTD #define RXD_PIN PIND #define RXD_BIT 0 #define PCINT16_DDR DDRD #define PCINT16_PORT PORTD #define PCINT16_PIN PIND #define PCINT16_BIT 0 #define TXD_DDR DDRD #define TXD_PORT PORTD #define TXD_PIN PIND #define TXD_BIT 1 #define PCINT17_DDR DDRD #define PCINT17_PORT PORTD #define PCINT17_PIN PIND #define PCINT17_BIT 1 #define INT0_DDR DDRD #define INT0_PORT PORTD #define INT0_PIN PIND #define INT0_BIT 2 #define PCINT18_DDR DDRD #define PCINT18_PORT PORTD #define PCINT18_PIN PIND #define PCINT18_BIT 2 #endif /* _AVR_ATmega88PA_H_ */ avr-libc-1.8.0.orig/include/avr/lock.h0000644000000000000000000002046411732702554014374 0ustar /* Copyright (c) 2007, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: lock.h 1692 2008-04-29 18:07:36Z arcanum $ */ /* avr/lock.h - Lock Bits API */ #ifndef _AVR_LOCK_H_ #define _AVR_LOCK_H_ 1 /** \file */ /** \defgroup avr_lock : Lockbit Support \par Introduction The Lockbit API allows a user to specify the lockbit settings for the specific AVR device they are compiling for. These lockbit settings will be placed in a special section in the ELF output file, after linking. Programming tools can take advantage of the lockbit information embedded in the ELF file, by extracting this information and determining if the lockbits need to be programmed after programming the Flash and EEPROM memories. This also allows a single ELF file to contain all the information needed to program an AVR. To use the Lockbit API, include the header file, which in turn automatically includes the individual I/O header file and the file. These other two files provides everything necessary to set the AVR lockbits. \par Lockbit API Each I/O header file may define up to 3 macros that controls what kinds of lockbits are available to the user. If __LOCK_BITS_EXIST is defined, then two lock bits are available to the user and 3 mode settings are defined for these two bits. If __BOOT_LOCK_BITS_0_EXIST is defined, then the two BLB0 lock bits are available to the user and 4 mode settings are defined for these two bits. If __BOOT_LOCK_BITS_1_EXIST is defined, then the two BLB1 lock bits are available to the user and 4 mode settings are defined for these two bits. If __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST is defined then two lock bits are available to set the locking mode for the Application Table Section (which is used in the XMEGA family). If __BOOT_LOCK_APPLICATION_BITS_EXIST is defined then two lock bits are available to set the locking mode for the Application Section (which is used in the XMEGA family). If __BOOT_LOCK_BOOT_BITS_EXIST is defined then two lock bits are available to set the locking mode for the Boot Loader Section (which is used in the XMEGA family). The AVR lockbit modes have inverted values, logical 1 for an unprogrammed (disabled) bit and logical 0 for a programmed (enabled) bit. The defined macros for each individual lock bit represent this in their definition by a bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined as: \code #define LB_MODE_3 (0xFC) ` \endcode To combine the lockbit mode macros together to represent a whole byte, use the bitwise AND operator, like so: \code (LB_MODE_3 & BLB0_MODE_2) \endcode also defines a macro that provides a default lockbit value: LOCKBITS_DEFAULT which is defined to be 0xFF. See the AVR device specific datasheet for more details about these lock bits and the available mode settings. A convenience macro, LOCKMEM, is defined as a GCC attribute for a custom-named section of ".lock". A convenience macro, LOCKBITS, is defined that declares a variable, __lock, of type unsigned char with the attribute defined by LOCKMEM. This variable allows the end user to easily set the lockbit data. \note If a device-specific I/O header file has previously defined LOCKMEM, then LOCKMEM is not redefined. If a device-specific I/O header file has previously defined LOCKBITS, then LOCKBITS is not redefined. LOCKBITS is currently known to be defined in the I/O header files for the XMEGA devices. \par API Usage Example Putting all of this together is easy: \code #include LOCKBITS = (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4); int main(void) { return 0; } \endcode Or: \code #include unsigned char __lock __attribute__((section (".lock"))) = (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4); int main(void) { return 0; } \endcode However there are a number of caveats that you need to be aware of to use this API properly. Be sure to include to get all of the definitions for the API. The LOCKBITS macro defines a global variable to store the lockbit data. This variable is assigned to its own linker section. Assign the desired lockbit values immediately in the variable initialization. The .lock section in the ELF file will get its values from the initial variable assignment ONLY. This means that you can NOT assign values to this variable in functions and the new values will not be put into the ELF .lock section. The global variable is declared in the LOCKBITS macro has two leading underscores, which means that it is reserved for the "implementation", meaning the library, so it will not conflict with a user-named variable. You must initialize the lockbit variable to some meaningful value, even if it is the default value. This is because the lockbits default to a logical 1, meaning unprogrammed. Normal uninitialized data defaults to all locgial zeros. So it is vital that all lockbits are initialized, even with default data. If they are not, then the lockbits may not programmed to the desired settings and can possibly put your device into an unrecoverable state. Be sure to have the -mmcu=device flag in your compile command line and your linker command line to have the correct device selected and to have the correct I/O header file included when you include . You can print out the contents of the .lock section in the ELF file by using this command line: \code avr-objdump -s -j .lock \endcode */ #ifndef __ASSEMBLER__ #ifndef LOCKMEM #define LOCKMEM __attribute__((section (".lock"))) #endif #ifndef LOCKBITS #define LOCKBITS unsigned char __lock LOCKMEM #endif #endif /* !__ASSEMBLER */ /* Lock Bit Modes */ #if defined(__LOCK_BITS_EXIST) #define LB_MODE_1 (0xFF) #define LB_MODE_2 (0xFE) #define LB_MODE_3 (0xFC) #endif #if defined(__BOOT_LOCK_BITS_0_EXIST) #define BLB0_MODE_1 (0xFF) #define BLB0_MODE_2 (0xFB) #define BLB0_MODE_3 (0xF3) #define BLB0_MODE_4 (0xF7) #endif #if defined(__BOOT_LOCK_BITS_1_EXIST) #define BLB1_MODE_1 (0xFF) #define BLB1_MODE_2 (0xEF) #define BLB1_MODE_3 (0xCF) #define BLB1_MODE_4 (0xDF) #endif #if defined(__BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST) #define BLBAT0 ~_BV(2) #define BLBAT1 ~_BV(3) #endif #if defined(__BOOT_LOCK_APPLICATION_BITS_EXIST) #define BLBA0 ~_BV(4) #define BLBA1 ~_BV(5) #endif #if defined(__BOOT_LOCK_BOOT_BITS_EXIST) #define BLBB0 ~_BV(6) #define BLBB1 ~_BV(7) #endif #define LOCKBITS_DEFAULT (0xFF) #endif /* _AVR_LOCK_H_ */ avr-libc-1.8.0.orig/include/avr/io2313.h0000644000000000000000000002167611732702554014372 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io2313.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io2313.h - definitions for AT90S2313 */ #ifndef _AVR_IO2313_H_ #define _AVR_IO2313_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io2313.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART Baud Rate Register */ #define UBRR _SFR_IO8(0x09) /* UART Control Register */ #define UCR _SFR_IO8(0x0A) /* UART Status Register */ #define USR _SFR_IO8(0x0B) /* UART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* Output Compare Register 1 */ #define OCR1 _SFR_IO16(0x2A) #define OCR1L _SFR_IO8(0x2A) #define OCR1H _SFR_IO8(0x2B) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3C..0x3D SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT1_vect_num 3 #define TIMER1_CAPT1_vect _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) /* Timer/Counter1 Compare Match */ #define TIMER1_COMP1_vect_num 4 #define TIMER1_COMP1_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) /* Timer/Counter1 Overflow */ #define TIMER1_OVF1_vect_num 5 #define TIMER1_OVF1_vect _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(5) /* Timer/Counter0 Overflow */ #define TIMER0_OVF0_vect_num 6 #define TIMER0_OVF0_vect _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(6) /* UART, Rx Complete */ #define UART_RX_vect_num 7 #define UART_RX_vect _VECTOR(7) #define SIG_UART_RECV _VECTOR(7) /* UART Data Register Empty */ #define UART_UDRE_vect_num 8 #define UART_UDRE_vect _VECTOR(8) #define SIG_UART_DATA _VECTOR(8) /* UART, Tx Complete */ #define UART_TX_vect_num 9 #define UART_TX_vect _VECTOR(9) #define SIG_UART_TRANS _VECTOR(9) /* Analog Comparator */ #define ANA_COMP_vect_num 10 #define ANA_COMP_vect _VECTOR(10) #define SIG_COMPARATOR _VECTOR(10) #define _VECTORS_SIZE 22 /* * The Register Bit names are represented by their bit number (0-7). */ /* General Interrupt MaSK register */ #define INT1 7 #define INT0 6 /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 /* Timer/Counter Interrupt MaSK register */ #define TOIE1 7 #define OCIE1A 6 #define TICIE 3 /* old name */ #define TICIE1 3 #define TOIE0 1 /* Timer/Counter Interrupt Flag register */ #define TOV1 7 #define OCF1A 6 #define ICF1 3 #define TOV0 1 /* MCU general Control Register */ #define SE 5 #define SM 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* EEPROM Control Register */ #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port D */ #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 0 #define FLASHEND 0x07FF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_FSTRT (unsigned char)~_BV(0) #define FUSE_SPIEN (unsigned char)~_BV(5) #define LFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x01 #endif /* _AVR_IO2313_H_ */ avr-libc-1.8.0.orig/include/avr/iom88.h0000644000000000000000000000727311732702554014413 0ustar /* Copyright (c) 2004, Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom88.h 2115 2010-04-05 23:19:53Z arcanum $ */ #ifndef _AVR_IOM88_H_ #define _AVR_IOM88_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x100) #define RAMEND 0x4FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x0A #endif /* _AVR_IOM88_H_ */ avr-libc-1.8.0.orig/include/avr/iotn20.h0000644000000000000000000003605211732702554014557 0ustar /* Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ /* avr/iotn20.h - definitions for ATtiny20 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn20.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny20_H_ #define _AVR_ATtiny20_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PUEA _SFR_IO8(0x03) #define PUEA0 0 #define PUEA1 1 #define PUEA2 2 #define PUEA3 3 #define PUEA4 4 #define PUEA5 5 #define PUEA6 6 #define PUEA7 7 #define PINB _SFR_IO8(0x04) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x05) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x06) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PUEB _SFR_IO8(0x07) #define PUEB0 0 #define PUEB1 1 #define PUEB2 2 #define PUEB3 3 #define PORTCR _SFR_IO8(0x08) #define BBMA 0 #define BBMB 1 #define PCMSK0 _SFR_IO8(0x09) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_IO8(0x0A) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define GIFR _SFR_IO8(0x0B) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define GIMSK _SFR_IO8(0x0C) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define DIDR0 _SFR_IO8(0x0D) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x0E) #endif #define ADCW _SFR_IO16(0x0E) #define ADCL _SFR_IO8(0x0E) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x0F) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADMUX _SFR_IO8(0x10) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define REFS 6 #define ADCSRB _SFR_IO8(0x11) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADLAR 3 #define ADCSRA _SFR_IO8(0x12) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ACSRB _SFR_IO8(0x13) #define ACME 2 #define HLEV 6 #define HSEL 7 #define ACSRA _SFR_IO8(0x14) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCR0B _SFR_IO8(0x15) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define OCR0A _SFR_IO8(0x16) #define OCR0_0 0 #define OCR0_1 1 #define OCR0_2 2 #define OCR0_3 3 #define OCR0_4 4 #define OCR0_5 5 #define OCR0_6 6 #define OCR0_7 7 #define TCNT0 _SFR_IO8(0x17) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0B _SFR_IO8(0x18) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCCR0A _SFR_IO8(0x19) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define ICR1 _SFR_IO16(0x1A) #define ICR1L _SFR_IO8(0x1A) #define ICR1_0 0 #define ICR1_1 1 #define ICR1_2 2 #define ICR1_3 3 #define ICR1_4 4 #define ICR1_5 5 #define ICR1_6 6 #define ICR1_7 7 #define ICR1H _SFR_IO8(0x1B) #define ICR1_8 0 #define ICR1_9 1 #define ICR1_10 2 #define ICR1_11 3 #define ICR1_12 4 #define ICR1_13 5 #define ICR1_14 6 #define ICR1_15 7 #define OCR1B _SFR_IO16(0x1C) #define OCR1BL _SFR_IO8(0x1C) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define OCR1BH _SFR_IO8(0x1D) #define OCR1B8 0 #define OCR1B9 1 #define OCR1B10 2 #define OCR1B11 3 #define OCR1B12 4 #define OCR1B13 5 #define OCR1B14 6 #define OCR1B15 7 #define OCR1A _SFR_IO16(0x1E) #define OCR1AL _SFR_IO8(0x1E) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define OCR1AH _SFR_IO8(0x1F) #define OCR1A8 0 #define OCR1A9 1 #define OCR1A10 2 #define OCR1A11 3 #define OCR1A12 4 #define OCR1A13 5 #define OCR1A14 6 #define OCR1A15 7 #define TCNT1 _SFR_IO16(0x20) #define TCNT1L _SFR_IO8(0x20) #define TCNT1_0 0 #define TCNT1_1 1 #define TCNT1_2 2 #define TCNT1_3 3 #define TCNT1_4 4 #define TCNT1_5 5 #define TCNT1_6 6 #define TCNT1_7 7 #define TCNT1H _SFR_IO8(0x21) #define TCNT1_8 0 #define TCNT1_9 1 #define TCNT1_10 2 #define TCNT1_11 3 #define TCNT1_12 4 #define TCNT1_13 5 #define TCNT1_14 6 #define TCNT1_15 7 #define TCCR1C _SFR_IO8(0x22) #define FOC1B 6 #define FOC1A 7 #define TCCR1B _SFR_IO8(0x23) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1A _SFR_IO8(0x24) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TIFR _SFR_IO8(0x25) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TOV1 3 #define OCF1A 4 #define OCF1B 5 #define ICF1 7 #define TIMSK _SFR_IO8(0x26) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TOIE1 3 #define OCIE1A 4 #define OCIE1B 5 #define ICIE1 7 #define GTCCR _SFR_IO8(0x27) #define PSR 0 #define TSM 7 #define TWSD _SFR_IO8(0x28) #define TWSD0 0 #define TWSD1 1 #define TWSD2 2 #define TWSD3 3 #define TWSD4 4 #define TWSD5 5 #define TWSD6 6 #define TWSD7 7 #define TWSAM _SFR_IO8(0x29) #define TWAE 0 #define TWSAM1 1 #define TWSAM2 2 #define TWSAM3 3 #define TWSAM4 4 #define TWSAM5 5 #define TWSAM6 6 #define TWSAM7 7 #define TWSA _SFR_IO8(0x2A) #define TWSA0 0 #define TWSA1 1 #define TWSA2 2 #define TWSA3 3 #define TWSA4 4 #define TWSA5 5 #define TWSA6 6 #define TWSA7 7 #define TWSSRA _SFR_IO8(0x2B) #define TWAS 0 #define TWDIR 1 #define TWBE 2 #define TWC 3 #define TWRA 4 #define TWCH 5 #define TWASIF 6 #define TWDIF 7 #define TWSCRB _SFR_IO8(0x2C) #define TWCMD0 0 #define TWCMD1 1 #define TWAA 2 #define TWSCRA _SFR_IO8(0x2D) #define TWSME 0 #define TWPME 1 #define TWSIE 2 #define TWEN 3 #define TWASIE 4 #define TWDIE 5 #define TWSHE 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define SPSR _SFR_IO8(0x2F) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPCR _SFR_IO8(0x30) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define WDTCSR _SFR_IO8(0x31) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define NVMCSR _SFR_IO8(0x32) #define NVMBSY 7 #define NVMCMD _SFR_IO8(0x33) #define NVMCMD0 0 #define NVMCMD1 1 #define NVMCMD2 2 #define NVMCMD3 3 #define NVMCMD4 4 #define NVMCMD5 5 #define QTCSR _SFR_IO8(0x34) #define PRR _SFR_IO8(0x35) #define PRADC 0 #define PRTIM0 1 #define PRTIM1 2 #define PRSPI 3 #define PRTWI 4 #define CLKPSR _SFR_IO8(0x36) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKMSR _SFR_IO8(0x37) #define CLKMS0 0 #define CLKMS1 1 #define OSCCAL _SFR_IO8(0x39) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define MCUCR _SFR_IO8(0x3A) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define BODS 4 #define ISC00 6 #define ISC01 7 #define RSTFLR _SFR_IO8(0x3B) #define PORF 0 #define EXTRF 1 #define WDRF 3 #define CCP _SFR_IO8(0x3C) #define CCP0 0 #define CCP1 1 #define CCP2 2 #define CCP3 3 #define CCP4 4 #define CCP5 5 #define CCP6 6 #define CCP7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ #define WDT_vect_num 4 #define WDT_vect _VECTOR(4) /* Watchdog Time-out */ #define TIM1_CAPT_vect_num 5 #define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Input Capture */ #define TIM1_COMPA_vect_num 6 #define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIM1_COMPB_vect_num 7 #define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIM1_OVF_vect_num 8 #define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIM0_COMPA_vect_num 9 #define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ #define TIM0_COMPB_vect_num 10 #define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ #define TIM0_OVF_vect_num 11 #define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ #define ANA_COMP_vect_num 12 #define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ #define ADC_ADC_vect_num 13 #define ADC_ADC_vect _VECTOR(13) /* Conversion Complete */ #define TWI_SLAVE_vect_num 14 #define TWI_SLAVE_vect _VECTOR(14) /* Two-Wire Interface */ #define SPI_vect_num 15 #define SPI_vect _VECTOR(15) /* Serial Peripheral Interface */ #define QTRIP_vect_num 16 #define QTRIP_vect _VECTOR(16) /* Touch Sensing */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (17 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x40) #define RAMSIZE (128) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x0) #define E2PAGESIZE (0) #define FLASHEND (0x7FF) /* Fuses */ #define FUSE_MEMORY_SIZE 0 /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x0F /* Device Pin Definitions */ #define ADC4_DDR DDRCINT #define ADC4_PORT PORTCINT #define ADC4_PIN PINCINT #define ADC4_BIT INT4 #define ADC3_DDR DDRCINT #define ADC3_PORT PORTCINT #define ADC3_PIN PINCINT #define ADC3_BIT INT3 #define AIN1_DDR DDRCINT #define AIN1_PORT PORTCINT #define AIN1_PIN PINCINT #define AIN1_BIT INT2 #define ADC2_DDR DDRCINT #define ADC2_PORT PORTCINT #define ADC2_PIN PINCINT #define ADC2_BIT INT2 #define AIN0_DDR DDRCINT #define AIN0_PORT PORTCINT #define AIN0_PIN PINCINT #define AIN0_BIT INT1 #define ADC1_DDR DDRCINT #define ADC1_PORT PORTCINT #define ADC1_PIN PINCINT #define ADC1_BIT INT1 #define ADC0_DDR DDRCINT #define ADC0_PORT PORTCINT #define ADC0_PIN PINCINT #define ADC0_BIT INT0 #define T0_DDR DDRCLKI #define T0_PORT PORTCLKI #define T0_PIN PINCLKI #define T0_BIT CLKI #define TPICLK_DDR DDRCLKI #define TPICLK_PORT PORTCLKI #define TPICLK_PIN PINCLKI #define TPICLK_BIT CLKI #define PCINT8_DDR DDRCLKI #define PCINT8_PORT PORTCLKI #define PCINT8_PIN PINCLKI #define PCINT8_BIT CLKI #define SDA_DDR DDROC1A #define SDA_PORT PORTOC1A #define SDA_PIN PINOC1A #define SDA_BIT OC1A #define MOSI_DDR DDROC1A #define MOSI_PORT PORTOC1A #define MOSI_PIN PINOC1A #define MOSI_BIT OC1A #define TPIDATA_DDR DDROC1A #define TPIDATA_PORT PORTOC1A #define TPIDATA_PIN PINOC1A #define TPIDATA_BIT OC1A #define PCINT9_DDR DDROC1A #define PCINT9_PORT PORTOC1A #define PCINT9_PIN PINOC1A #define PCINT9_BIT OC1A #define PCINT11_DDR DDRRESET #define PCINT11_PORT PORTRESET #define PCINT11_PIN PINRESET #define PCINT11_BIT RESET #define OC0A_DDR DDRCKOUT #define OC0A_PORT PORTCKOUT #define OC0A_PIN PINCKOUT #define OC0A_BIT CKOUT #define OC1B_DDR DDRCKOUT #define OC1B_PORT PORTCKOUT #define OC1B_PIN PINCKOUT #define OC1B_BIT CKOUT #define MISO_DDR DDRCKOUT #define MISO_PORT PORTCKOUT #define MISO_PIN PINCKOUT #define MISO_BIT CKOUT #define INT0_DDR DDRCKOUT #define INT0_PORT PORTCKOUT #define INT0_PIN PINCKOUT #define INT0_BIT CKOUT #define PCINT10_DDR DDRCKOUT #define PCINT10_PORT PORTCKOUT #define PCINT10_PIN PINCKOUT #define PCINT10_BIT CKOUT #define OC0B_DDR DDR(ADC #define OC0B_PORT PORT(ADC #define OC0B_PIN PIN(ADC #define OC0B_BIT (ADC7 #define ICP1_DDR DDR(ADC #define ICP1_PORT PORT(ADC #define ICP1_PIN PIN(ADC #define ICP1_BIT (ADC7 #define T1_DDR DDR(ADC #define T1_PORT PORT(ADC #define T1_PIN PIN(ADC #define T1_BIT (ADC7 #define SCL_DDR DDR(ADC #define SCL_PORT PORT(ADC #define SCL_PIN PIN(ADC #define SCL_BIT (ADC7 #define SCK_DDR DDR(ADC #define SCK_PORT PORT(ADC #define SCK_PIN PIN(ADC #define SCK_BIT (ADC7 #define PCINT7_DDR DDR(ADC #define PCINT7_PORT PORT(ADC #define PCINT7_PIN PIN(ADC #define PCINT7_BIT (ADC7 #define SS_DDR DDRADC #define SS_PORT PORTADC #define SS_PIN PINADC #define SS_BIT ADC6 #define PCINT6_DDR DDRADC #define PCINT6_PORT PORTADC #define PCINT6_PIN PINADC #define PCINT6_BIT ADC6 #define PCINT5_DDR DDRADC #define PCINT5_PORT PORTADC #define PCINT5_PIN PINADC #define PCINT5_BIT ADC5 #endif /* _AVR_ATtiny20_H_ */ avr-libc-1.8.0.orig/include/avr/iotnx5.h0000644000000000000000000002301311732702554014663 0ustar /* Copyright (c) 2005,2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotnx5.h 2269 2011-12-29 08:07:25Z joerg_wunsch $ */ /* avr/iotnx5.h - definitions for ATtiny25, ATtiny45 and ATtiny85 */ #ifndef _AVR_IOTNX5_H_ #define _AVR_IOTNX5_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotnx5.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Reserved [0x00..0x02] */ #define ADCSRB _SFR_IO8 (0x03) #define BIN 7 #define ACME 6 #define IPR 5 #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSRA _SFR_IO8 (0x06) #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 #define ADMUX _SFR_IO8(0x07) #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define REFS2 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 #define ACSR _SFR_IO8(0x08) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIS1 1 #define ACIS0 0 /* Reserved [0x09..0x0C] */ #define USICR _SFR_IO8(0x0D) #define USISIE 7 #define USIOIE 6 #define USIWM1 5 #define USIWM0 4 #define USICS1 3 #define USICS0 2 #define USICLK 1 #define USITC 0 #define USISR _SFR_IO8(0x0E) #define USISIF 7 #define USIOIF 6 #define USIPF 5 #define USIDC 4 #define USICNT3 3 #define USICNT2 2 #define USICNT1 1 #define USICNT0 0 #define USIDR _SFR_IO8(0x0F) #define USIBR _SFR_IO8(0x10) #define GPIOR0 _SFR_IO8(0x11) #define GPIOR1 _SFR_IO8(0x12) #define GPIOR2 _SFR_IO8(0x13) #define DIDR0 _SFR_IO8(0x14) #define ADC0D 5 #define ADC2D 4 #define ADC3D 3 #define ADC1D 2 #define AIN1D 1 #define AIN0D 0 #define PCMSK _SFR_IO8(0x15) #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 #define PINB _SFR_IO8(0x16) #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x17) #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x18) #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Reserved [0x19..0x1B] */ /* EEPROM Control Register EECR */ #define EECR _SFR_IO8(0x1C) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define PRR _SFR_IO8(0x20) #define PRTIM1 3 #define PRTIM0 2 #define PRUSI 1 #define PRADC 0 #define WDTCR _SFR_IO8(0x21) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 #define DWDR _SFR_IO8(0x22) #define DTPS1 _SFR_IO8(0x23) #define DTPS11 1 #define DTPS10 0 #define DT1B _SFR_IO8(0x24) #define DT1BH3 7 #define DT1BH2 6 #define DT1BH1 5 #define DT1BH0 4 #define DT1BL3 3 #define DT1BL2 2 #define DT1BL1 1 #define DT1BL0 0 #define DT1A _SFR_IO8(0x25) #define DT1AH3 7 #define DT1AH2 6 #define DT1AH1 5 #define DT1AH0 4 #define DT1AL3 3 #define DT1AL2 2 #define DT1AL1 1 #define DT1AL0 0 #define CLKPR _SFR_IO8(0x26) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 #define PLLCSR _SFR_IO8(0x27) #define LSM 7 #define PCKE 2 #define PLLE 1 #define PLOCK 0 #define OCR0B _SFR_IO8(0x28) #define OCR0A _SFR_IO8(0x29) #define TCCR0A _SFR_IO8(0x2A) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 #define OCR1B _SFR_IO8(0x2B) #define GTCCR _SFR_IO8(0x2C) #define TSM 7 #define PWM1B 6 #define COM1B1 5 #define COM1B0 4 #define FOC1B 3 #define FOC1A 2 #define PSR1 1 #define PSR0 0 #define OCR1C _SFR_IO8(0x2D) #define OCR1A _SFR_IO8(0x2E) #define TCNT1 _SFR_IO8(0x2F) #define TCCR1 _SFR_IO8(0x30) #define CTC1 7 #define PWM1A 6 #define COM1A1 5 #define COM1A0 4 #define CS13 3 #define CS12 2 #define CS11 1 #define CS10 0 #define OSCCAL _SFR_IO8(0x31) #define TCNT0 _SFR_IO8(0x32) #define TCCR0B _SFR_IO8(0x33) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 #define MCUSR _SFR_IO8(0x34) #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 #define MCUCR _SFR_IO8(0x35) #define BODS 7 #define PUD 6 #define SE 5 #define SM1 4 #define SM0 3 #define BODSE 2 #define ISC01 1 #define ISC00 0 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define RSIG 5 #define CTPB 4 #define RFLB 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 #define TIFR _SFR_IO8(0x38) #define OCF1A 6 #define OCF1B 5 #define OCF0A 4 #define OCF0B 3 #define TOV1 2 #define TOV0 1 #define TIMSK _SFR_IO8(0x39) #define OCIE1A 6 #define OCIE1B 5 #define OCIE0A 4 #define OCIE0B 3 #define TOIE1 2 #define TOIE0 1 #define GIFR _SFR_IO8(0x3A) #define INTF0 6 #define PCIF 5 #define GIMSK _SFR_IO8(0x3B) #define INT0 6 #define PCIE 5 /* Reserved [0x3C] */ /* 0x3D..0x3E SP [defined in ] */ /* 0x3F SREG [defined in ] */ ///--- /* Interrupt vectors */ /* Interrupt vector 0 is the reset vector. */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE _VECTOR(2) /* Timer/Counter1 Compare Match 1A */ #define TIM1_COMPA_vect_num 3 #define TIM1_COMPA_vect _VECTOR(3) #define TIMER1_COMPA_vect_num 3 #define TIMER1_COMPA_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE1A _VECTOR(3) /* Timer/Counter1 Overflow */ #define TIM1_OVF_vect_num 4 #define TIM1_OVF_vect _VECTOR(4) #define TIMER1_OVF_vect_num 4 #define TIMER1_OVF_vect _VECTOR(4) #define SIG_OVERFLOW1 _VECTOR(4) /* Timer/Counter0 Overflow */ #define TIM0_OVF_vect_num 5 #define TIM0_OVF_vect _VECTOR(5) #define TIMER0_OVF_vect_num 5 #define TIMER0_OVF_vect _VECTOR(5) #define SIG_OVERFLOW0 _VECTOR(5) /* EEPROM Ready */ #define EE_RDY_vect_num 6 #define EE_RDY_vect _VECTOR(6) #define SIG_EEPROM_READY _VECTOR(6) /* Analog comparator */ #define ANA_COMP_vect_num 7 #define ANA_COMP_vect _VECTOR(7) #define SIG_COMPARATOR _VECTOR(7) /* ADC Conversion ready */ #define ADC_vect_num 8 #define ADC_vect _VECTOR(8) #define SIG_ADC _VECTOR(8) /* Timer/Counter1 Compare Match B */ #define TIM1_COMPB_vect_num 9 #define TIM1_COMPB_vect _VECTOR(9) #define TIMER1_COMPB_vect_num 9 #define TIMER1_COMPB_vect _VECTOR(9) #define SIG_OUTPUT_COMPARE1B _VECTOR(9) /* Timer/Counter0 Compare Match A */ #define TIM0_COMPA_vect_num 10 #define TIM0_COMPA_vect _VECTOR(10) #define TIMER0_COMPA_vect_num 10 #define TIMER0_COMPA_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0A _VECTOR(10) /* Timer/Counter0 Compare Match B */ #define TIM0_COMPB_vect_num 11 #define TIM0_COMPB_vect _VECTOR(11) #define TIMER0_COMPB_vect_num 11 #define TIMER0_COMPB_vect _VECTOR(11) #define SIG_OUTPUT_COMPARE0B _VECTOR(11) /* Watchdog Time-out */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) #define SIG_WATCHDOG_TIMEOUT _VECTOR(12) /* USI START */ #define USI_START_vect_num 13 #define USI_START_vect _VECTOR(13) #define SIG_USI_START _VECTOR(13) /* USI Overflow */ #define USI_OVF_vect_num 14 #define USI_OVF_vect _VECTOR(14) #define SIG_USI_OVERFLOW _VECTOR(14) #define _VECTORS_SIZE 30 #endif /* _AVR_IOTNX5_H_ */ avr-libc-1.8.0.orig/include/avr/iom324.h0000644000000000000000000000656611732702554014470 0ustar /* Copyright (c) 2005, 2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/iom324.h - definitions for ATmega324 */ /* $Id: iom324.h 2115 2010-04-05 23:19:53Z arcanum $ */ #ifndef _AVR_IOM324_H_ #define _AVR_IOM324_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 128 #define RAMSTART (0x100) #define RAMEND 0x08FF #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 4 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature (ATmega324P) */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x08 #endif /* _AVR_IOM324_H_ */ avr-libc-1.8.0.orig/include/avr/iom644.h0000644000000000000000000000651511732702554014467 0ustar /* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/iom644.h - definitions for ATmega644 */ /* $Id: iom644.h 2115 2010-04-05 23:19:53Z arcanum $ */ #ifndef _AVR_IOM644_H_ #define _AVR_IOM644_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMSTART (0x100) #define RAMEND 0x10FF #define XRAMEND RAMEND #define E2END 0x7FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x09 #endif /* _AVR_IOM644_H_ */ avr-libc-1.8.0.orig/include/avr/io90pwmx.h0000644000000000000000000012607711732702554015147 0ustar /* Copyright (c) 2005, Andrey Pashchenko All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io90pwmx.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwmx.h - definitions for AT90PWM2(B) and AT90PWM3(B) */ #ifndef _AVR_IO90PWMX_H_ #define _AVR_IO90PWMX_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io90pwmX.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Port B Input Pins Address */ #define PINB _SFR_IO8(0x03) /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Port B Data Direction Register */ #define DDRB _SFR_IO8(0x04) /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Port B Data Register */ #define PORTB _SFR_IO8(0x05) /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Port C Input Pins Address */ #define PINC _SFR_IO8(0x06) /* PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Port C Data Direction Register */ #define DDRC _SFR_IO8(0x07) /* DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Port C Data Register */ #define PORTC _SFR_IO8(0x08) /* PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Port D Input Pins Address */ #define PIND _SFR_IO8(0x09) /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Port D Data Direction Register */ #define DDRD _SFR_IO8(0x0A) /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Port D Data Register */ #define PORTD _SFR_IO8(0x0B) /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Port E Input Pins Address */ #define PINE _SFR_IO8(0x0C) /* PINE */ #define PINE2 2 #define PINE1 1 #define PINE0 0 /* Port E Data Direction Register */ #define DDRE _SFR_IO8(0x0D) /* DDRE */ #define DDE2 2 #define DDE1 1 #define DDE0 0 /* Port E Data Register */ #define PORTE _SFR_IO8(0x0E) /* PORTE */ #define PE2 2 #define PE1 1 #define PE0 0 /* Timer/Counter 0 Interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) /* TIFR0 */ #define OCF0B 2 /* Output Compare Flag 0B */ #define OCF0A 1 /* Output Compare Flag 0A */ #define TOV0 0 /* Overflow Flag */ /* Timer/Counter1 Interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) /* TIFR1 */ #define ICF1 5 /* Input Capture Flag 1 */ #define OCF1B 2 /* Output Compare Flag 1B*/ #define OCF1A 1 /* Output Compare Flag 1A*/ #define TOV1 0 /* Overflow Flag */ /* General Purpose I/O Register 1 */ #define GPIOR1 _SFR_IO8(0x19) /* GPIOR1 */ #define GPIOR17 7 #define GPIOR16 6 #define GPIOR15 5 #define GPIOR14 4 #define GPIOR13 3 #define GPIOR12 2 #define GPIOR11 1 #define GPIOR10 0 /* General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x1A) /* GPIOR2 */ #define GPIOR27 7 #define GPIOR26 6 #define GPIOR25 5 #define GPIOR24 4 #define GPIOR23 3 #define GPIOR22 2 #define GPIOR21 1 #define GPIOR20 0 /* General Purpose I/O Register 3 */ #define GPIOR3 _SFR_IO8(0x1B) /* GPIOR3 */ #define GPIOR37 7 #define GPIOR36 6 #define GPIOR35 5 #define GPIOR34 4 #define GPIOR33 3 #define GPIOR32 2 #define GPIOR31 1 #define GPIOR30 0 /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) /* EIFR */ #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 /* External Interrupt Mask Register */ #define EIMSK _SFR_IO8(0x1D) /* EIMSK */ #define INT3 3 /* External Interrupt Request 3 Enable */ #define INT2 2 /* External Interrupt Request 2 Enable */ #define INT1 1 /* External Interrupt Request 1 Enable */ #define INT0 0 /* External Interrupt Request 0 Enable */ /* General Purpose I/O Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) /* GPIOR0 */ #define GPIOR07 7 #define GPIOR06 6 #define GPIOR05 5 #define GPIOR04 4 #define GPIOR03 3 #define GPIOR02 2 #define GPIOR01 1 #define GPIOR00 0 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1F) /* EECR */ #define EERIE 3 /* EEPROM Ready Interrupt Enable */ #define EEMWE 2 /* EEPROM Master Write Enable */ #define EEWE 1 /* EEPROM Write Enable */ #define EERE 0 /* EEPROM Read Enable */ /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x20) /* EEDR */ #define EEDR7 7 #define EEDR6 6 #define EEDR5 5 #define EEDR4 4 #define EEDR3 3 #define EEDR2 2 #define EEDR1 1 #define EEDR0 0 /* The EEPROM Address Registers */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0x22) /* EEARH */ #define EEAR11 3 #define EEAR10 2 #define EEAR9 1 #define EEAR8 0 /* EEARL */ #define EEAR7 7 #define EEAR6 6 #define EEAR5 5 #define EEAR4 4 #define EEAR3 3 #define EEAR2 2 #define EEAR1 1 #define EEAR0 0 /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) /* GTCCR */ #define TSM 7 /* Timer/Counter Synchronization Mode */ #define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ #define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ /* Timer/Counter Control Register A */ #define TCCR0A _SFR_IO8(0x24) /* TCCR0A */ #define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ #define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ #define COM0B1 5 /* Compare Output Mode, Fast PWm */ #define COM0B0 4 /* Compare Output Mode, Fast PWm */ #define WGM01 1 /* Waveform Generation Mode */ #define WGM00 0 /* Waveform Generation Mode */ /* Timer/Counter Control Register B */ #define TCCR0B _SFR_IO8(0x25) /* TCCR0B */ #define FOC0A 7 /* Force Output Compare A */ #define FOC0B 6 /* Force Output Compare B */ #define WGM02 3 /* Waveform Generation Mode */ #define CS02 2 /* Clock Select */ #define CS01 1 /* Clock Select */ #define CS00 0 /* Clock Select */ /* Timer/Counter0 Register */ #define TCNT0 _SFR_IO8(0x26) /* TCNT0 */ #define TCNT07 7 #define TCNT06 6 #define TCNT05 5 #define TCNT04 4 #define TCNT03 3 #define TCNT02 2 #define TCNT01 1 #define TCNT00 0 /* Timer/Counter0 Output Compare Register A */ #define OCR0A _SFR_IO8(0x27) /* OCR0A */ #define OCR0A7 7 #define OCR0A6 6 #define OCR0A5 5 #define OCR0A4 4 #define OCR0A3 3 #define OCR0A2 2 #define OCR0A1 1 #define OCR0A0 0 /* Timer/Counter0 Output Compare Register B */ #define OCR0B _SFR_IO8(0x28) /* OCR0B */ #define OCR0B7 7 #define OCR0B6 6 #define OCR0B5 5 #define OCR0B4 4 #define OCR0B3 3 #define OCR0B2 2 #define OCR0B1 1 #define OCR0B0 0 /* PLL Control and Status Register */ #define PLLCSR _SFR_IO8(0x29) /* PLLCSR */ #define PCKE 2 /* PCK Enable */ /* Bit 2 has been renamed in later versions of the datasheet. */ #define PLLF 2 /* PLL Factor */ #define PLLE 1 /* PLL Enable */ #define PLOCK 0 /* PLL Lock Detector */ /* SPI Control Register */ #define SPCR _SFR_IO8(0x2C) /* SPCR */ #define SPIE 7 /* SPI Interrupt Enable */ #define SPE 6 /* SPI Enable */ #define DORD 5 /* Data Order */ #define MSTR 4 /* Master/Slave Select */ #define CPOL 3 /* Clock polarity */ #define CPHA 2 /* Clock Phase */ #define SPR1 1 /* SPI Clock Rate Select 1 */ #define SPR0 0 /* SPI Clock Rate Select 0 */ /* SPI Status Register */ #define SPSR _SFR_IO8(0x2D) /* SPSR */ #define SPIF 7 /* SPI Interrupt Flag */ #define WCOL 6 /* Write Collision Flag */ #define SPI2X 0 /* Double SPI Speed Bit */ /* SPI Data Register */ #define SPDR _SFR_IO8(0x2E) /* SPDR */ #define SPD7 7 #define SPD6 6 #define SPD5 5 #define SPD4 4 #define SPD3 3 #define SPD2 2 #define SPD1 1 #define SPD0 0 /* Analog Comparator Status Register */ #define ACSR _SFR_IO8(0x30) /* ACSR */ #define ACCKDIV 7 /* Analog Comparator Clock Divider */ #define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ #define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ #define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ #define AC2O 2 /* Analog Comparator 2 Output Bit */ #define AC1O 1 /* Analog Comparator 1 Output Bit */ #define AC0O 0 /* Analog Comparator 0 Output Bit */ /* Monitor Data Register */ #define MONDR _SFR_IO8(0x31) /* Monitor Stop Mode Control Register */ #define MSMCR _SFR_IO8(0x32) /* Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) /* SMCR */ #define SM2 3 /* Sleep Mode Select bit2 */ #define SM1 2 /* Sleep Mode Select bit1 */ #define SM0 1 /* Sleep Mode Select bit0 */ #define SE 0 /* Sleep Enable */ /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCUSR */ #define WDRF 3 /* Watchdog Reset Flag */ #define BORF 2 /* Brown-out Reset Flag */ #define EXTRF 1 /* External Reset Flag */ #define PORF 0 /* Power-on reset flag */ /* MCU Control Register */ #define MCUCR _SFR_IO8(0x35) /* MCUCR */ #define SPIPS 7 /* SPI Pin Select */ #define PUD 4 /* Pull-up disable */ #define IVSEL 1 /* Interrupt Vector Select */ #define IVCE 0 /* Interrupt Vector Change Enable */ /* Store Program Memory Control Register */ #define SPMCSR _SFR_IO8(0x37) /* SPMCSR */ #define SPMIE 7 /* SPM Interrupt Enable */ #define RWWSB 6 /* Read While Write Section Busy */ #define RWWSRE 4 /* Read While Write section read enable */ #define BLBSET 3 /* Boot Lock Bit Set */ #define PGWRT 2 /* Page Write */ #define PGERS 1 /* Page Erase */ #define SPMEN 0 /* Store Program Memory Enable */ /* 0x3D..0x3E SP [defined in ] */ /* 0x3F SREG [defined in ] */ /* Watchdog Timer Control Register */ #define WDTCSR _SFR_MEM8(0x60) /* WDTCSR */ #define WDIF 7 /* Watchdog Timeout Interrupt Flag */ #define WDIE 6 /* Watchdog Timeout Interrupt Enable */ #define WDP3 5 /* Watchdog Timer Prescaler bit3 */ #define WDCE 4 /* Watchdog Change Enable */ #define WDE 3 /* Watchdog Enable */ #define WDP2 2 /* Watchdog Timer Prescaler bit2 */ #define WDP1 1 /* Watchdog Timer Prescaler bit1 */ #define WDP0 0 /* Watchdog Timer Prescaler bit0 */ /* Clock Prescaler Register */ #define CLKPR _SFR_MEM8(0x61) /* CLKPR */ #define CLKPCE 7 /* Clock Prescaler Change Enable */ #define CLKPS3 3 /* Clock Prescaler Select bit3 */ #define CLKPS2 2 /* Clock Prescaler Select bit2 */ #define CLKPS1 1 /* Clock Prescaler Select bit1 */ #define CLKPS0 0 /* Clock Prescaler Select bit0 */ /* Power Reduction Register */ #define PRR _SFR_MEM8(0x64) /* PRR */ #define PRPSC2 7 /* Power Reduction PSC2 */ #define PRPSC1 6 /* Power Reduction PSC1 */ #define PRPSC0 5 /* Power Reduction PSC0 */ #define PRTIM1 4 /* Power Reduction Timer/Counter1 */ #define PRTIM0 3 /* Power Reduction Timer/Counter0 */ #define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ #define PRUSART 1 /* Power Reduction USART */ #define PRADC 0 /* Power Reduction ADC */ /* Oscillator Calibration Value */ #define OSCCAL _SFR_MEM8(0x66) /* OSCCAL */ #define CAL6 6 #define CAL5 5 #define CAL4 4 #define CAL3 3 #define CAL2 2 #define CAL1 1 #define CAL0 0 /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x69) /* EICRA */ #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter0 Interrupt Mask Register */ #define TIMSK0 _SFR_MEM8(0x6E) /* TIMSK0 */ #define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ #define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ #define TOIE0 0 /* Overflow Interrupt Enable */ /* Timer/Counter1 Interrupt Mask Register */ #define TIMSK1 _SFR_MEM8(0x6F) /* TIMSK1 */ #define ICIE1 5 /* Input Capture Interrupt Enable */ #define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ #define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ #define TOIE1 0 /* Overflow Interrupt Enable */ /* Amplifier 0 Control and Status register */ #define AMP0CSR _SFR_MEM8(0x76) #define AMP0EN 7 #define AMP0IS 6 #define AMP0G1 5 #define AMP0G0 4 #define AMP0TS1 1 #define AMP0TS0 0 /* Amplifier 1 Control and Status register */ #define AMP1CSR _SFR_MEM8(0x77) #define AMP1EN 7 #define AMP1IS 6 #define AMP1G1 5 #define AMP1G0 4 #define AMP1TS1 1 #define AMP1TS0 0 /* ADC Result Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) /* ADC Control and Status Register A */ #define ADCSRA _SFR_MEM8(0x7A) /* ADCSRA */ #define ADEN 7 /* ADC Enable */ #define ADSC 6 /* ADC Start Conversion */ #define ADATE 5 /* ADC Auto Trigger Enable */ #define ADIF 4 /* ADC Interrupt Flag */ #define ADIE 3 /* ADC Interrupt Enable */ #define ADPS2 2 /* ADC Prescaler Select bit2 */ #define ADPS1 1 /* ADC Prescaler Select bit1 */ #define ADPS0 0 /* ADC Prescaler Select bit0 */ /* ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x7B) /* ADCSRB */ #define ADHSM 7 /* ADC High Speed Mode */ #define ADASCR 4 #define ADTS3 3 /* ADC Auto Trigger Source 3 */ #define ADTS2 2 /* ADC Auto Trigger Source 2 */ #define ADTS1 1 /* ADC Auto Trigger Source 1 */ #define ADTS0 0 /* ADC Auto Trigger Source 0 */ /* ADC multiplexer Selection Register */ #define ADMUX _SFR_MEM8(0x7C) /* ADMUX */ #define REFS1 7 /* Reference Selection bit1 */ #define REFS0 6 /* Reference Selection bit0 */ #define ADLAR 5 /* Left Adjust Result */ #define MUX3 3 /* Analog Channel and Gain Selection bit3 */ #define MUX2 2 /* Analog Channel and Gain Selection bit2 */ #define MUX1 1 /* Analog Channel and Gain Selection bit1 */ #define MUX0 0 /* Analog Channel and Gain Selection bit0 */ /* Digital Input Disable Register 0 */ #define DIDR0 _SFR_MEM8(0x7E) /* DIDR0 */ #define ADC7D 7 /* ADC7 Digital input Disable */ #define ADC6D 6 /* ADC6 Digital input Disable */ #define ADC5D 5 /* ADC5 Digital input Disable */ #define ADC4D 4 /* ADC4 Digital input Disable */ #define ADC3D 3 /* ADC3 Digital input Disable */ #define ADC2D 2 /* ADC2 Digital input Disable */ #define ADC1D 1 /* ADC1 Digital input Disable */ #define ADC0D 0 /* ADC0 Digital input Disable */ /* Digital Input Disable Register 1 */ #define DIDR1 _SFR_MEM8(0x7F) /* DIDR1 */ #define ACMP0D 5 #define AMP0PD 4 #define AMP0ND 3 #define ADC10D 2 /* ADC10 Digital input Disable */ #define ADC9D 1 /* ADC9 Digital input Disable */ #define ADC8D 0 /* ADC8 Digital input Disable */ /* Timer/Counter1 Control Register A */ #define TCCR1A _SFR_MEM8(0x80) /* TCCR1A */ #define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ #define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ #define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ #define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ #define WGM11 1 /* Waveform Generation Mode */ #define WGM10 0 /* Waveform Generation Mode */ /* Timer/Counter1 Control Register B */ #define TCCR1B _SFR_MEM8(0x81) /* TCCR1B */ #define ICNC1 7 /* Input Capture 1 Noise Canceler */ #define ICES1 6 /* Input Capture 1 Edge Select */ #define WGM13 4 /* Waveform Generation Mode */ #define WGM12 3 /* Waveform Generation Mode */ #define CS12 2 /* Prescaler source of Timer/Counter 1 */ #define CS11 1 /* Prescaler source of Timer/Counter 1 */ #define CS10 0 /* Prescaler source of Timer/Counter 1 */ /* Timer/Counter1 Control Register C */ #define TCCR1C _SFR_MEM8(0x82) /* TCCR1C */ #define FOC1A 7 /* Force Output Compare for Channel A */ #define FOC1B 6 /* Force Output Compare for Channel B */ /* Timer/Counter1 */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* TCNT1H */ #define TCNT115 7 #define TCNT114 6 #define TCNT113 5 #define TCNT112 4 #define TCNT111 3 #define TCNT110 2 #define TCNT19 1 #define TCNT18 0 /* TCNT1L */ #define TCNT17 7 #define TCNT16 6 #define TCNT15 5 #define TCNT14 4 #define TCNT13 3 #define TCNT12 2 #define TCNT11 1 #define TCNT10 0 /* Input Capture Register 1 */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* ICR1H */ #define ICR115 7 #define ICR114 6 #define ICR113 5 #define ICR112 4 #define ICR111 3 #define ICR110 2 #define ICR19 1 #define ICR18 0 /* ICR1L */ #define ICR17 7 #define ICR16 6 #define ICR15 5 #define ICR14 4 #define ICR13 3 #define ICR12 2 #define ICR11 1 #define ICR10 0 /* Output Compare Register 1 A */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* OCR1AH */ #define OCR1A15 7 #define OCR1A14 6 #define OCR1A13 5 #define OCR1A12 4 #define OCR1A11 3 #define OCR1A10 2 #define OCR1A9 1 #define OCR1A8 0 /* OCR1AL */ #define OCR1A7 7 #define OCR1A6 6 #define OCR1A5 5 #define OCR1A4 4 #define OCR1A3 3 #define OCR1A2 2 #define OCR1A1 1 #define OCR1A0 0 /* Output Compare Register 1 B */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* OCR1BH */ #define OCR1B15 7 #define OCR1B14 6 #define OCR1B13 5 #define OCR1B12 4 #define OCR1B11 3 #define OCR1B10 2 #define OCR1B9 1 #define OCR1B8 0 /* OCR1BL */ #define OCR1B7 7 #define OCR1B6 6 #define OCR1B5 5 #define OCR1B4 4 #define OCR1B3 3 #define OCR1B2 2 #define OCR1B1 1 #define OCR1B0 0 /* PSC0 Interrupt Flag Register */ #define PIFR0 _SFR_MEM8(0xA0) /* PIFR0 */ #define POAC0B 7 /* PSC0 Output B Activity */ #define POAC0A 6 /* PSC0 Output A Activity */ #define PSEI0 5 /* PSC0 Synchro Error Interrupt */ #define PEV0B 4 /* PSC0 External Event B Interrupt */ #define PEV0A 3 /* PSC0 External Event A Interrupt */ #define PRN01 2 /* PSC0 Ramp Number bit1 */ #define PRN00 1 /* PSC0 Ramp Number bit0 */ #define PEOP0 0 /* End Of PSC0 Interrupt */ /* PSC0 Interrupt Mask Register */ #define PIM0 _SFR_MEM8(0xA1) /* PIM0 */ #define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ #define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ #define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ #define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ /* PSC1 Interrupt Flag Register */ #define PIFR1 _SFR_MEM8(0xA2) /* PIFR1 */ #define POAC1B 7 /* PSC1 Output B Activity */ #define POAC1A 6 /* PSC1 Output A Activity */ #define PSEI1 5 /* PSC1 Synchro Error Interrupt */ #define PEV1B 4 /* PSC1 External Event B Interrupt */ #define PEV1A 3 /* PSC1 External Event A Interrupt */ #define PRN11 2 /* PSC1 Ramp Number bit1 */ #define PRN10 1 /* PSC1 Ramp Number bit0 */ #define PEOP1 0 /* End Of PSC1 Interrupt */ /* PSC1 Interrupt Mask Register */ #define PIM1 _SFR_MEM8(0xA3) /* PIM1 */ #define PSEIE1 5 /* PSC1 Synchro Error Interrupt Enable */ #define PEVE1B 4 /* PSC1 External Event B Interrupt Enable */ #define PEVE1A 3 /* PSC1 External Event A Interrupt Enable */ #define PEOPE1 0 /* PSC1 End Of Cycle Interrupt Enable */ /* PSC2 Interrupt Flag Register */ #define PIFR2 _SFR_MEM8(0xA4) /* PIFR2 */ #define POAC2B 7 /* PSC2 Output B Activity */ #define POAC2A 6 /* PSC2 Output A Activity */ #define PSEI2 5 /* PSC2 Synchro Error Interrupt */ #define PEV2B 4 /* PSC2 External Event B Interrupt */ #define PEV2A 3 /* PSC2 External Event A Interrupt */ #define PRN21 2 /* PSC2 Ramp Number bit1 */ #define PRN20 1 /* PSC2 Ramp Number bit0 */ #define PEOP2 0 /* End Of PSC2 Interrupt */ /* PSC2 Interrupt Mask Register */ #define PIM2 _SFR_MEM8(0xA5) /* PIM2 */ #define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ #define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ #define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ #define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ /* Digital to Analog Conversion Control Register */ #define DACON _SFR_MEM8(0xAA) /* DACON */ #define DAATE 7 /* DAC Auto Trigger Enable bit */ #define DATS2 6 /* DAC Trigger Selection bit2 */ #define DATS1 5 /* DAC Trigger Selection bit1 */ #define DATS0 4 /* DAC Trigger Selection bit0 */ #define DALA 2 /* Digital to Analog Left Adjust */ #define DAOE 1 /* Digital to Analog Output Enable bit */ #define DAEN 0 /* Digital to Analog Enable bit */ /* Digital to Analog Converter input Register */ #define DAC _SFR_MEM16(0xAB) #define DACL _SFR_MEM8(0xAB) #define DACH _SFR_MEM8(0xAC) /* Analog Comparator 0 Control Register */ #define AC0CON _SFR_MEM8(0xAD) /* AC0CON */ #define AC0EN 7 /* Analog Comparator 0 Enable Bit */ #define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ #define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ #define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ #define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ #define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ #define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ /* Analog Comparator 1 Control Register */ #define AC1CON _SFR_MEM8(0xAE) /* AC1CON */ #define AC1EN 7 /* Analog Comparator 1 Enable Bit */ #define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */ #define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */ #define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */ #define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */ #define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */ #define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */ #define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */ /* Analog Comparator 2 Control Register */ #define AC2CON _SFR_MEM8(0xAF) /* AC2CON */ #define AC2EN 7 /* Analog Comparator 2 Enable Bit */ #define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ #define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ #define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ #define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ #define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ #define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ /* USART Control and Status Register A */ #define UCSRA _SFR_MEM8(0xC0) /* UCSRA */ #define RXC 7 /* USART Receive Complete */ #define TXC 6 /* USART Transmit Complete */ #define UDRE 5 /* USART Data Register Empty */ #define FE 4 /* Frame Error */ #define DOR 3 /* Data OverRun */ #define UPE 2 /* USART Parity Error */ #define U2X 1 /* Double the USART Transmission Speed */ #define MPCM 0 /* Multi-processor Communication Mode */ /* USART Control and Status Register B */ #define UCSRB _SFR_MEM8(0xC1) /* UCSRB */ #define RXCIE 7 /* RX Complete Interrupt Enable */ #define TXCIE 6 /* TX Complete Interrupt Enable */ #define UDRIE 5 /* USART Data Register Empty Interrupt Enable */ #define RXEN 4 /* Receiver Enable */ #define TXEN 3 /* Transmitter Enable */ #define UCSZ2 2 /* Character Size */ #define RXB8 1 /* Receive Data Bit 8 */ #define TXB8 0 /* Transmit Data Bit 8 */ /* USART Control and Status Register C */ #define UCSRC _SFR_MEM8(0xC2) /* UCSRC */ #define UMSEL 6 /* USART Mode Select */ #define UPM1 5 /* Parity Mode bit1 */ #define UPM0 4 /* Parity Mode bit0 */ #define USBS 3 /* Stop Bit Select */ #define UCSZ1 2 /* Character Size bit1 */ #define UCSZ0 1 /* Character Size bit0 */ #define UCPOL 0 /* Clock Polarity */ /* USART Baud Rate Register */ #define UBRR _SFR_MEM16(0xC4) #define UBRRL _SFR_MEM8(0xC4) #define UBRRH _SFR_MEM8(0xC5) /* USART I/O Data Register */ #define UDR _SFR_MEM8(0xC6) /* EUSART Control and Status Register A */ #define EUCSRA _SFR_MEM8(0xC8) /* EUCSRA */ #define UTxS3 7 /* EUSART Transmit Character Size bit3 */ #define UTxS2 6 /* EUSART Transmit Character Size bit2 */ #define UTxS1 5 /* EUSART Transmit Character Size bit1 */ #define UTxS0 4 /* EUSART Transmit Character Size bit0 */ #define URxS3 3 /* EUSART Receive Character Size bit3 */ #define URxS2 2 /* EUSART Receive Character Size bit2 */ #define URxS1 1 /* EUSART Receive Character Size bit1 */ #define URxS0 0 /* EUSART Receive Character Size bit0 */ /* EUSART Control and Status Register B */ #define EUCSRB _SFR_MEM8(0xC9) /* EUCSRB */ #define EUSART 4 /* EUSART Enable Bit */ #define EUSBS 3 /* EUSBS Enable Bit */ #define EMCH 1 /* Manchester mode */ #define BODR 0 /* Bit Order */ /* EUSART Control and Status Register C */ #define EUCSRC _SFR_MEM8(0xCA) /* EUCSRC */ #define FEM 3 /* Frame Error Manchester */ #define F1617 2 #define STP1 1 /* Stop bits values bit1 */ #define STP0 0 /* Stop bits values bit0 */ /* Manchester receiver Baud Rate Registers */ #define MUBRR _SFR_MEM16(0xCC) #define MUBRRL _SFR_MEM8(0xCC) #define MUBRRH _SFR_MEM8(0xCD) /* EUSART I/O Data Register */ #define EUDR _SFR_MEM8(0xCE) /* PSC 0 Synchro and Output Configuration */ #define PSOC0 _SFR_MEM8(0xD0) /* PSOC0 */ #define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ #define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ #define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ #define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ /* Output Compare SA Registers */ #define OCR0SA _SFR_MEM16(0xD2) #define OCR0SAL _SFR_MEM8(0xD2) #define OCR0SAH _SFR_MEM8(0xD3) /* Output Compare RA Registers */ #define OCR0RA _SFR_MEM16(0xD4) #define OCR0RAL _SFR_MEM8(0xD4) #define OCR0RAH _SFR_MEM8(0xD5) /* Output Compare SB Registers */ #define OCR0SB _SFR_MEM16(0xD6) #define OCR0SBL _SFR_MEM8(0xD6) #define OCR0SBH _SFR_MEM8(0xD7) /* Output Compare RB Registers */ #define OCR0RB _SFR_MEM16(0xD8) #define OCR0RBL _SFR_MEM8(0xD8) #define OCR0RBH _SFR_MEM8(0xD9) /* PSC 0 Configuration Register */ #define PCNF0 _SFR_MEM8(0xDA) /* PCNF0 */ #define PFIFTY0 7 /* PSC 0 Fifty */ #define PALOCK0 6 /* PSC 0 Autolock */ #define PLOCK0 5 /* PSC 0 Lock */ #define PMODE01 4 /* PSC 0 Mode bit1 */ #define PMODE00 3 /* PSC 0 Mode bit0 */ #define POP0 2 /* PSC 0 Output Polarity */ #define PCLKSEL0 1 /* PSC 0 Input Clock Select */ /* PSC 0 Control Register */ #define PCTL0 _SFR_MEM8(0xDB) /* PCTL0 */ #define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ #define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ #define PBFM0 5 /* Balance Flank Width Modulation */ #define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ #define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ #define PARUN0 2 /* PSC 0 Autorun */ #define PCCYC0 1 /* PSC 0 Complete Cycle */ #define PRUN0 0 /* PSC 0 Run */ /* PSC 0 Input A Control Register */ #define PFRC0A _SFR_MEM8(0xDC) /* PFRC0A */ #define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ #define PISEL0A 6 /* PSC 0 Input Select for Part A */ #define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ #define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ #define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ #define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ #define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ #define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ /* PSC 0 Input B Control Register */ #define PFRC0B _SFR_MEM8(0xDD) /* PFRC0B */ #define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ #define PISEL0B 6 /* PSC 0 Input Select for Part B */ #define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ #define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ #define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ #define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ #define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ #define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ /* PSC 0 Input Capture Registers */ #define PICR0 _SFR_MEM16(0xDE) #define PICR0L _SFR_MEM8(0xDE) #define PICR0H _SFR_MEM8(0xDF) #define PCST0 7 /* PSC Capture Software Trig bit */ /* not implemented on AT90PWM2/AT90PWM3 */ /* PSC 1 Synchro and Output Configuration */ #define PSOC1 _SFR_MEM8(0xE0) /* PSOC1 */ #define PSYNC11 5 /* Synchronization Out for ADC Selection bit1 */ #define PSYNC10 4 /* Synchronization Out for ADC Selection bit0 */ #define POEN1B 2 /* PSC 1 OUT Part B Output Enable */ #define POEN1A 0 /* PSC 1 OUT Part A Output Enable */ /* Output Compare SA Registers */ #define OCR1SA _SFR_MEM16(0xE2) #define OCR1SAL _SFR_MEM8(0xE2) #define OCR1SAH _SFR_MEM8(0xE3) /* Output Compare RA Registers */ #define OCR1RA _SFR_MEM16(0xE4) #define OCR1RAL _SFR_MEM8(0xE4) #define OCR1RAH _SFR_MEM8(0xE5) /* Output Compare SB Registers */ #define OCR1SB _SFR_MEM16(0xE6) #define OCR1SBL _SFR_MEM8(0xE6) #define OCR1SBH _SFR_MEM8(0xE7) /* Output Compare RB Registers */ #define OCR1RB _SFR_MEM16(0xE8) #define OCR1RBL _SFR_MEM8(0xE8) #define OCR1RBH _SFR_MEM8(0xE9) /* PSC 1 Configuration Register */ #define PCNF1 _SFR_MEM8(0xEA) /* PCNF1 */ #define PFIFTY1 7 /* PSC 1 Fifty */ #define PALOCK1 6 /* PSC 1 Autolock */ #define PLOCK1 5 /* PSC 1 Lock */ #define PMODE11 4 /* PSC 1 Mode bit1 */ #define PMODE10 3 /* PSC 1 Mode bit0 */ #define POP1 2 /* PSC 1 Output Polarity */ #define PCLKSEL1 1 /* PSC 1 Input Clock Select */ /* PSC 1 Control Register */ #define PCTL1 _SFR_MEM8(0xEB) /* PCTL1 */ #define PPRE11 7 /* PSC 1 Prescaler Select bit1 */ #define PPRE10 6 /* PSC 1 Prescaler Select bit0 */ #define PBFM1 5 /* Balance Flank Width Modulation */ #define PAOC1B 4 /* PSC 1 Asynchronous Output Control B */ #define PAOC1A 3 /* PSC 1 Asynchronous Output Control A */ #define PARUN1 2 /* PSC 1 Autorun */ #define PCCYC1 1 /* PSC 1 Complete Cycle */ #define PRUN1 0 /* PSC 1 Run */ /* PSC 1 Input A Control Register */ #define PFRC1A _SFR_MEM8(0xEC) /* PFRC1A */ #define PCAE1A 7 /* PSC 1 Capture Enable Input Part A */ #define PISEL1A 6 /* PSC 1 Input Select for Part A */ #define PELEV1A 5 /* PSC 1 Edge Level Selector of Input Part A */ #define PFLTE1A 4 /* PSC 1 Filter Enable on Input Part A */ #define PRFM1A3 3 /* PSC 1 Fault Mode bit3 */ #define PRFM1A2 2 /* PSC 1 Fault Mode bit2 */ #define PRFM1A1 1 /* PSC 1 Fault Mode bit1 */ #define PRFM1A0 0 /* PSC 1 Fault Mode bit0 */ /* PSC 1 Input B Control Register */ #define PFRC1B _SFR_MEM8(0xED) /* PFRC1B */ #define PCAE1B 7 /* PSC 1 Capture Enable Input Part B */ #define PISEL1B 6 /* PSC 1 Input Select for Part B */ #define PELEV1B 5 /* PSC 1 Edge Level Selector of Input Part B */ #define PFLTE1B 4 /* PSC 1 Filter Enable on Input Part B */ #define PRFM1B3 3 /* PSC 1 Fault Mode bit3 */ #define PRFM1B2 2 /* PSC 1 Fault Mode bit2 */ #define PRFM1B1 1 /* PSC 1 Fault Mode bit1 */ #define PRFM1B0 0 /* PSC 1 Fault Mode bit0 */ /* PSC 1 Input Capture Registers */ #define PICR1 _SFR_MEM16(0xEE) #define PICR1L _SFR_MEM8(0xEE) #define PICR1H _SFR_MEM8(0xEF) #define PCST1 7 /* PSC Capture Software Trig bit */ /* not implemented on AT90PWM2/AT90PWM3 */ /* PSC 2 Synchro and Output Configuration */ #define PSOC2 _SFR_MEM8(0xF0) /* PSOC2 */ #define POS23 7 /* PSCOUT23 Selection */ #define POS22 6 /* PSCOUT22 Selection */ #define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ #define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ #define POEN2D 3 /* PSCOUT23 Output Enable */ #define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ #define POEN2C 1 /* PSCOUT22 Output Enable */ #define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ /* PSC 2 Output Matrix */ #define POM2 _SFR_MEM8(0xF1) /* POM2 */ #define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ #define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ #define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ #define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ #define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ #define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ #define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ #define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ /* Output Compare SA Registers */ #define OCR2SA _SFR_MEM16(0xF2) #define OCR2SAL _SFR_MEM8(0xF2) #define OCR2SAH _SFR_MEM8(0xF3) /* Output Compare RA Registers */ #define OCR2RA _SFR_MEM16(0xF4) #define OCR2RAL _SFR_MEM8(0xF4) #define OCR2RAH _SFR_MEM8(0xF5) /* Output Compare SB Registers */ #define OCR2SB _SFR_MEM16(0xF6) #define OCR2SBL _SFR_MEM8(0xF6) #define OCR2SBH _SFR_MEM8(0xF7) /* Output Compare RB Registers */ #define OCR2RB _SFR_MEM16(0xF8) #define OCR2RBL _SFR_MEM8(0xF8) #define OCR2RBH _SFR_MEM8(0xF9) /* PSC 2 Configuration Register */ #define PCNF2 _SFR_MEM8(0xFA) /* PCNF2 */ #define PFIFTY2 7 /* PSC 2 Fifty */ #define PALOCK2 6 /* PSC 2 Autolock */ #define PLOCK2 5 /* PSC 2 Lock */ #define PMODE21 4 /* PSC 2 Mode bit1 */ #define PMODE20 3 /* PSC 2 Mode bit0 */ #define POP2 2 /* PSC 2 Output Polarity */ #define PCLKSEL2 1 /* PSC 2 Input Clock Select */ #define POME2 0 /* PSC 2 Output Matrix Enable */ /* PSC 2 Control Register */ #define PCTL2 _SFR_MEM8(0xFB) /* PCTL2 */ #define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ #define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ #define PBFM2 5 /* Balance Flank Width Modulation */ #define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ #define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ #define PARUN2 2 /* PSC 2 Autorun */ #define PCCYC2 1 /* PSC 2 Complete Cycle */ #define PRUN2 0 /* PSC 2 Run */ /* PSC 2 Input A Control Register */ #define PFRC2A _SFR_MEM8(0xFC) /* PFRC2A */ #define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ #define PISEL2A 6 /* PSC 2 Input Select for Part A */ #define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ #define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ #define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ #define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ #define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ #define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ /* PSC 2 Input B Control Register */ #define PFRC2B _SFR_MEM8(0xFD) /* PFRC2B */ #define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ #define PISEL2B 6 /* PSC 2 Input Select for Part B */ #define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ #define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ #define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ #define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ #define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ #define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ /* PSC 2 Input Capture Registers */ #define PICR2 _SFR_MEM16(0xFE) #define PICR2L _SFR_MEM8(0xFE) #define PICR2H _SFR_MEM8(0xFF) #define PCST2 7 /* PSC Capture Software Trig bit */ /* not implemented on AT90PWM2/AT90PWM3 */ /* Interrupt vectors */ /* PSC2 Capture Event */ #define PSC2_CAPT_vect_num 1 #define PSC2_CAPT_vect _VECTOR(1) #define SIG_PSC2_CAPTURE _VECTOR(1) /* PSC2 End Cycle */ #define PSC2_EC_vect_num 2 #define PSC2_EC_vect _VECTOR(2) #define SIG_PSC2_END_CYCLE _VECTOR(2) /* PSC1 Capture Event */ #define PSC1_CAPT_vect_num 3 #define PSC1_CAPT_vect _VECTOR(3) #define SIG_PSC1_CAPTURE _VECTOR(3) /* PSC1 End Cycle */ #define PSC1_EC_vect_num 4 #define PSC1_EC_vect _VECTOR(4) #define SIG_PSC1_END_CYCLE _VECTOR(4) /* PSC0 Capture Event */ #define PSC0_CAPT_vect_num 5 #define PSC0_CAPT_vect _VECTOR(5) #define SIG_PSC0_CAPTURE _VECTOR(5) /* PSC0 End Cycle */ #define PSC0_EC_vect_num 6 #define PSC0_EC_vect _VECTOR(6) #define SIG_PSC0_END_CYCLE _VECTOR(6) /* Analog Comparator 0 */ #define ANALOG_COMP_0_vect_num 7 #define ANALOG_COMP_0_vect _VECTOR(7) #define SIG_COMPARATOR0 _VECTOR(7) /* Analog Comparator 1 */ #define ANALOG_COMP_1_vect_num 8 #define ANALOG_COMP_1_vect _VECTOR(8) #define SIG_COMPARATOR1 _VECTOR(8) /* Analog Comparator 2 */ #define ANALOG_COMP_2_vect_num 9 #define ANALOG_COMP_2_vect _VECTOR(9) #define SIG_COMPARATOR2 _VECTOR(9) /* External Interrupt Request 0 */ #define INT0_vect_num 10 #define INT0_vect _VECTOR(10) #define SIG_INTERRUPT0 _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) #define SIG_INPUT_CAPTURE1 _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num _VECTOR(12) #define TIMER1_COMPA_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1A _VECTOR(12) #define SIG_OUTPUT_COMPARE1_A _VECTOR(12) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1B _VECTOR(13) #define SIG_OUTPUT_COMPARE1_B _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) #define SIG_OVERFLOW1 _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMP_A_vect_num 16 #define TIMER0_COMP_A_vect _VECTOR(16) #define SIG_OUTPUT_COMPARE0A _VECTOR(16) #define SIG_OUTPUT_COMPARE0_A _VECTOR(16) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) #define SIG_OVERFLOW0 _VECTOR(17) /* ADC Conversion Complete */ #define ADC_vect_num 18 #define ADC_vect _VECTOR(18) #define SIG_ADC _VECTOR(18) /* External Interrupt Request 1 */ #define INT1_vect_num 19 #define INT1_vect _VECTOR(19) #define SIG_INTERRUPT1 _VECTOR(19) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 20 #define SPI_STC_vect _VECTOR(20) #define SIG_SPI _VECTOR(20) /* USART, Rx Complete */ #define USART_RX_vect_num 21 #define USART_RX_vect _VECTOR(21) #define SIG_USART_RECV _VECTOR(21) #define SIG_UART_RECV _VECTOR(21) /* USART Data Register Empty */ #define USART_UDRE_vect_num 22 #define USART_UDRE_vect _VECTOR(22) #define SIG_USART_DATA _VECTOR(22) #define SIG_UART_DATA _VECTOR(22) /* USART, Tx Complete */ #define USART_TX_vect_num 23 #define USART_TX_vect _VECTOR(23) #define SIG_USART_TRANS _VECTOR(23) #define SIG_UART_TRANS _VECTOR(23) /* External Interrupt Request 2 */ #define INT2_vect_num 24 #define INT2_vect _VECTOR(24) #define SIG_INTERRUPT2 _VECTOR(24) /* Watchdog Timeout Interrupt */ #define WDT_vect_num 25 #define WDT_vect _VECTOR(25) #define SIG_WDT _VECTOR(25) #define SIG_WATCHDOG_TIMEOUT _VECTOR(25) /* EEPROM Ready */ #define EE_READY_vect_num 26 #define EE_READY_vect _VECTOR(26) #define SIG_EEPROM_READY _VECTOR(26) /* Timer Counter 0 Compare Match B */ #define TIMER0_COMPB_vect_num 27 #define TIMER0_COMPB_vect _VECTOR(27) #define SIG_OUTPUT_COMPARE0B _VECTOR(27) #define SIG_OUTPUT_COMPARE0_B _VECTOR(27) /* External Interrupt Request 3 */ #define INT3_vect_num 28 #define INT3_vect _VECTOR(28) #define SIG_INTERRUPT3 _VECTOR(28) /* Store Program Memory Read */ #define SPM_READY_vect_num 31 #define SPM_READY_vect _VECTOR(31) #define SIG_SPM_READY _VECTOR(31) #define _VECTORS_SIZE 64 /* Constants */ #define SPM_PAGESIZE 64 #define RAMEND 0x02FF #define XRAMEND RAMEND #define E2END 0x01FF #define E2PAGESIZE 4 #define FLASHEND 0x0FFF /* Fuse Information */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_PSCRV (unsigned char)~_BV(4) #define FUSE_PSC0RB (unsigned char)~_BV(5) #define FUSE_PSC1RB (unsigned char)~_BV(6) #define FUSE_PSC2RB (unsigned char)~_BV(7) #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST #endif /* _AVR_IO90PWMX_H_ */ avr-libc-1.8.0.orig/include/avr/portpins.h0000644000000000000000000003311511732702554015317 0ustar /* Copyright (c) 2003 Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: portpins.h 1936 2009-03-19 22:19:26Z arcanum $ */ #ifndef _AVR_PORTPINS_H_ #define _AVR_PORTPINS_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif /* Define Generic PORTn, DDn, and PINn values. */ /* Port Data Register (generic) */ #define PORT7 7 #define PORT6 6 #define PORT5 5 #define PORT4 4 #define PORT3 3 #define PORT2 2 #define PORT1 1 #define PORT0 0 /* Port Data Direction Register (generic) */ #define DD7 7 #define DD6 6 #define DD5 5 #define DD4 4 #define DD3 3 #define DD2 2 #define DD1 1 #define DD0 0 /* Port Input Pins (generic) */ #define PIN7 7 #define PIN6 6 #define PIN5 5 #define PIN4 4 #define PIN3 3 #define PIN2 2 #define PIN1 1 #define PIN0 0 /* Define PORTxn an Pxn values for all possible port pins if not defined already by io.h. */ /* PORT A */ #if defined(PA0) && !defined(PORTA0) # define PORTA0 PA0 #elif defined(PORTA0) && !defined(PA0) # define PA0 PORTA0 #endif #if defined(PA1) && !defined(PORTA1) # define PORTA1 PA1 #elif defined(PORTA1) && !defined(PA1) # define PA1 PORTA1 #endif #if defined(PA2) && !defined(PORTA2) # define PORTA2 PA2 #elif defined(PORTA2) && !defined(PA2) # define PA2 PORTA2 #endif #if defined(PA3) && !defined(PORTA3) # define PORTA3 PA3 #elif defined(PORTA3) && !defined(PA3) # define PA3 PORTA3 #endif #if defined(PA4) && !defined(PORTA4) # define PORTA4 PA4 #elif defined(PORTA4) && !defined(PA4) # define PA4 PORTA4 #endif #if defined(PA5) && !defined(PORTA5) # define PORTA5 PA5 #elif defined(PORTA5) && !defined(PA5) # define PA5 PORTA5 #endif #if defined(PA6) && !defined(PORTA6) # define PORTA6 PA6 #elif defined(PORTA6) && !defined(PA6) # define PA6 PORTA6 #endif #if defined(PA7) && !defined(PORTA7) # define PORTA7 PA7 #elif defined(PORTA7) && !defined(PA7) # define PA7 PORTA7 #endif /* PORT B */ #if defined(PB0) && !defined(PORTB0) # define PORTB0 PB0 #elif defined(PORTB0) && !defined(PB0) # define PB0 PORTB0 #endif #if defined(PB1) && !defined(PORTB1) # define PORTB1 PB1 #elif defined(PORTB1) && !defined(PB1) # define PB1 PORTB1 #endif #if defined(PB2) && !defined(PORTB2) # define PORTB2 PB2 #elif defined(PORTB2) && !defined(PB2) # define PB2 PORTB2 #endif #if defined(PB3) && !defined(PORTB3) # define PORTB3 PB3 #elif defined(PORTB3) && !defined(PB3) # define PB3 PORTB3 #endif #if defined(PB4) && !defined(PORTB4) # define PORTB4 PB4 #elif defined(PORTB4) && !defined(PB4) # define PB4 PORTB4 #endif #if defined(PB5) && !defined(PORTB5) # define PORTB5 PB5 #elif defined(PORTB5) && !defined(PB5) # define PB5 PORTB5 #endif #if defined(PB6) && !defined(PORTB6) # define PORTB6 PB6 #elif defined(PORTB6) && !defined(PB6) # define PB6 PORTB6 #endif #if defined(PB7) && !defined(PORTB7) # define PORTB7 PB7 #elif defined(PORTB7) && !defined(PB7) # define PB7 PORTB7 #endif /* PORT C */ #if defined(PC0) && !defined(PORTC0) # define PORTC0 PC0 #elif defined(PORTC0) && !defined(PC0) # define PC0 PORTC0 #endif #if defined(PC1) && !defined(PORTC1) # define PORTC1 PC1 #elif defined(PORTC1) && !defined(PC1) # define PC1 PORTC1 #endif #if defined(PC2) && !defined(PORTC2) # define PORTC2 PC2 #elif defined(PORTC2) && !defined(PC2) # define PC2 PORTC2 #endif #if defined(PC3) && !defined(PORTC3) # define PORTC3 PC3 #elif defined(PORTC3) && !defined(PC3) # define PC3 PORTC3 #endif #if defined(PC4) && !defined(PORTC4) # define PORTC4 PC4 #elif defined(PORTC4) && !defined(PC4) # define PC4 PORTC4 #endif #if defined(PC5) && !defined(PORTC5) # define PORTC5 PC5 #elif defined(PORTC5) && !defined(PC5) # define PC5 PORTC5 #endif #if defined(PC6) && !defined(PORTC6) # define PORTC6 PC6 #elif defined(PORTC6) && !defined(PC6) # define PC6 PORTC6 #endif #if defined(PC7) && !defined(PORTC7) # define PORTC7 PC7 #elif defined(PORTC7) && !defined(PC7) # define PC7 PORTC7 #endif /* PORT D */ #if defined(PD0) && !defined(PORTD0) # define PORTD0 PD0 #elif defined(PORTD0) && !defined(PD0) # define PD0 PORTD0 #endif #if defined(PD1) && !defined(PORTD1) # define PORTD1 PD1 #elif defined(PORTD1) && !defined(PD1) # define PD1 PORTD1 #endif #if defined(PD2) && !defined(PORTD2) # define PORTD2 PD2 #elif defined(PORTD2) && !defined(PD2) # define PD2 PORTD2 #endif #if defined(PD3) && !defined(PORTD3) # define PORTD3 PD3 #elif defined(PORTD3) && !defined(PD3) # define PD3 PORTD3 #endif #if defined(PD4) && !defined(PORTD4) # define PORTD4 PD4 #elif defined(PORTD4) && !defined(PD4) # define PD4 PORTD4 #endif #if defined(PD5) && !defined(PORTD5) # define PORTD5 PD5 #elif defined(PORTD5) && !defined(PD5) # define PD5 PORTD5 #endif #if defined(PD6) && !defined(PORTD6) # define PORTD6 PD6 #elif defined(PORTD6) && !defined(PD6) # define PD6 PORTD6 #endif #if defined(PD7) && !defined(PORTD7) # define PORTD7 PD7 #elif defined(PORTD7) && !defined(PD7) # define PD7 PORTD7 #endif /* PORT E */ #if defined(PE0) && !defined(PORTE0) # define PORTE0 PE0 #elif defined(PORTE0) && !defined(PE0) # define PE0 PORTE0 #endif #if defined(PE1) && !defined(PORTE1) # define PORTE1 PE1 #elif defined(PORTE1) && !defined(PE1) # define PE1 PORTE1 #endif #if defined(PE2) && !defined(PORTE2) # define PORTE2 PE2 #elif defined(PORTE2) && !defined(PE2) # define PE2 PORTE2 #endif #if defined(PE3) && !defined(PORTE3) # define PORTE3 PE3 #elif defined(PORTE3) && !defined(PE3) # define PE3 PORTE3 #endif #if defined(PE4) && !defined(PORTE4) # define PORTE4 PE4 #elif defined(PORTE4) && !defined(PE4) # define PE4 PORTE4 #endif #if defined(PE5) && !defined(PORTE5) # define PORTE5 PE5 #elif defined(PORTE5) && !defined(PE5) # define PE5 PORTE5 #endif #if defined(PE6) && !defined(PORTE6) # define PORTE6 PE6 #elif defined(PORTE6) && !defined(PE6) # define PE6 PORTE6 #endif #if defined(PE7) && !defined(PORTE7) # define PORTE7 PE7 #elif defined(PORTE7) && !defined(PE7) # define PE7 PORTE7 #endif /* PORT F */ #if defined(PF0) && !defined(PORTF0) # define PORTF0 PF0 #elif defined(PORTF0) && !defined(PF0) # define PF0 PORTF0 #endif #if defined(PF1) && !defined(PORTF1) # define PORTF1 PF1 #elif defined(PORTF1) && !defined(PF1) # define PF1 PORTF1 #endif #if defined(PF2) && !defined(PORTF2) # define PORTF2 PF2 #elif defined(PORTF2) && !defined(PF2) # define PF2 PORTF2 #endif #if defined(PF3) && !defined(PORTF3) # define PORTF3 PF3 #elif defined(PORTF3) && !defined(PF3) # define PF3 PORTF3 #endif #if defined(PF4) && !defined(PORTF4) # define PORTF4 PF4 #elif defined(PORTF4) && !defined(PF4) # define PF4 PORTF4 #endif #if defined(PF5) && !defined(PORTF5) # define PORTF5 PF5 #elif defined(PORTF5) && !defined(PF5) # define PF5 PORTF5 #endif #if defined(PF6) && !defined(PORTF6) # define PORTF6 PF6 #elif defined(PORTF6) && !defined(PF6) # define PF6 PORTF6 #endif #if defined(PF7) && !defined(PORTF7) # define PORTF7 PF7 #elif defined(PORTF7) && !defined(PF7) # define PF7 PORTF7 #endif /* PORT G */ #if defined(PG0) && !defined(PORTG0) # define PORTG0 PG0 #elif defined(PORTG0) && !defined(PG0) # define PG0 PORTG0 #endif #if defined(PG1) && !defined(PORTG1) # define PORTG1 PG1 #elif defined(PORTG1) && !defined(PG1) # define PG1 PORTG1 #endif #if defined(PG2) && !defined(PORTG2) # define PORTG2 PG2 #elif defined(PORTG2) && !defined(PG2) # define PG2 PORTG2 #endif #if defined(PG3) && !defined(PORTG3) # define PORTG3 PG3 #elif defined(PORTG3) && !defined(PG3) # define PG3 PORTG3 #endif #if defined(PG4) && !defined(PORTG4) # define PORTG4 PG4 #elif defined(PORTG4) && !defined(PG4) # define PG4 PORTG4 #endif #if defined(PG5) && !defined(PORTG5) # define PORTG5 PG5 #elif defined(PORTG5) && !defined(PG5) # define PG5 PORTG5 #endif #if defined(PG6) && !defined(PORTG6) # define PORTG6 PG6 #elif defined(PORTG6) && !defined(PG6) # define PG6 PORTG6 #endif #if defined(PG7) && !defined(PORTG7) # define PORTG7 PG7 #elif defined(PORTG7) && !defined(PG7) # define PG7 PORTG7 #endif /* PORT H */ #if defined(PH0) && !defined(PORTH0) # define PORTH0 PH0 #elif defined(PORTH0) && !defined(PH0) # define PH0 PORTH0 #endif #if defined(PH1) && !defined(PORTH1) # define PORTH1 PH1 #elif defined(PORTH1) && !defined(PH1) # define PH1 PORTH1 #endif #if defined(PH2) && !defined(PORTH2) # define PORTH2 PH2 #elif defined(PORTH2) && !defined(PH2) # define PH2 PORTH2 #endif #if defined(PH3) && !defined(PORTH3) # define PORTH3 PH3 #elif defined(PORTH3) && !defined(PH3) # define PH3 PORTH3 #endif #if defined(PH4) && !defined(PORTH4) # define PORTH4 PH4 #elif defined(PORTH4) && !defined(PH4) # define PH4 PORTH4 #endif #if defined(PH5) && !defined(PORTH5) # define PORTH5 PH5 #elif defined(PORTH5) && !defined(PH5) # define PH5 PORTH5 #endif #if defined(PH6) && !defined(PORTH6) # define PORTH6 PH6 #elif defined(PORTH6) && !defined(PH6) # define PH6 PORTH6 #endif #if defined(PH7) && !defined(PORTH7) # define PORTH7 PH7 #elif defined(PORTH7) && !defined(PH7) # define PH7 PORTH7 #endif /* PORT J */ #if defined(PJ0) && !defined(PORTJ0) # define PORTJ0 PJ0 #elif defined(PORTJ0) && !defined(PJ0) # define PJ0 PORTJ0 #endif #if defined(PJ1) && !defined(PORTJ1) # define PORTJ1 PJ1 #elif defined(PORTJ1) && !defined(PJ1) # define PJ1 PORTJ1 #endif #if defined(PJ2) && !defined(PORTJ2) # define PORTJ2 PJ2 #elif defined(PORTJ2) && !defined(PJ2) # define PJ2 PORTJ2 #endif #if defined(PJ3) && !defined(PORTJ3) # define PORTJ3 PJ3 #elif defined(PORTJ3) && !defined(PJ3) # define PJ3 PORTJ3 #endif #if defined(PJ4) && !defined(PORTJ4) # define PORTJ4 PJ4 #elif defined(PORTJ4) && !defined(PJ4) # define PJ4 PORTJ4 #endif #if defined(PJ5) && !defined(PORTJ5) # define PORTJ5 PJ5 #elif defined(PORTJ5) && !defined(PJ5) # define PJ5 PORTJ5 #endif #if defined(PJ6) && !defined(PORTJ6) # define PORTJ6 PJ6 #elif defined(PORTJ6) && !defined(PJ6) # define PJ6 PORTJ6 #endif #if defined(PJ7) && !defined(PORTJ7) # define PORTJ7 PJ7 #elif defined(PORTJ7) && !defined(PJ7) # define PJ7 PORTJ7 #endif /* PORT K */ #if defined(PK0) && !defined(PORTK0) # define PORTK0 PK0 #elif defined(PORTK0) && !defined(PK0) # define PK0 PORTK0 #endif #if defined(PK1) && !defined(PORTK1) # define PORTK1 PK1 #elif defined(PORTK1) && !defined(PK1) # define PK1 PORTK1 #endif #if defined(PK2) && !defined(PORTK2) # define PORTK2 PK2 #elif defined(PORTK2) && !defined(PK2) # define PK2 PORTK2 #endif #if defined(PK3) && !defined(PORTK3) # define PORTK3 PK3 #elif defined(PORTK3) && !defined(PK3) # define PK3 PORTK3 #endif #if defined(PK4) && !defined(PORTK4) # define PORTK4 PK4 #elif defined(PORTK4) && !defined(PK4) # define PK4 PORTK4 #endif #if defined(PK5) && !defined(PORTK5) # define PORTK5 PK5 #elif defined(PORTK5) && !defined(PK5) # define PK5 PORTK5 #endif #if defined(PK6) && !defined(PORTK6) # define PORTK6 PK6 #elif defined(PORTK6) && !defined(PK6) # define PK6 PORTK6 #endif #if defined(PK7) && !defined(PORTK7) # define PORTK7 PK7 #elif defined(PORTK7) && !defined(PK7) # define PK7 PORTK7 #endif /* PORT L */ #if defined(PL0) && !defined(PORTL0) # define PORTL0 PL0 #elif defined(PORTL0) && !defined(PL0) # define PL0 PORTL0 #endif #if defined(PL1) && !defined(PORTL1) # define PORTL1 PL1 #elif defined(PORTL1) && !defined(PL1) # define PL1 PORTL1 #endif #if defined(PL2) && !defined(PORTL2) # define PORTL2 PL2 #elif defined(PORTL2) && !defined(PL2) # define PL2 PORTL2 #endif #if defined(PL3) && !defined(PORTL3) # define PORTL3 PL3 #elif defined(PORTL3) && !defined(PL3) # define PL3 PORTL3 #endif #if defined(PL4) && !defined(PORTL4) # define PORTL4 PL4 #elif defined(PORTL4) && !defined(PL4) # define PL4 PORTL4 #endif #if defined(PL5) && !defined(PORTL5) # define PORTL5 PL5 #elif defined(PORTL5) && !defined(PL5) # define PL5 PORTL5 #endif #if defined(PL6) && !defined(PORTL6) # define PORTL6 PL6 #elif defined(PORTL6) && !defined(PL6) # define PL6 PORTL6 #endif #if defined(PL7) && !defined(PORTL7) # define PORTL7 PL7 #elif defined(PORTL7) && !defined(PL7) # define PL7 PORTL7 #endif #endif /* _AVR_PORTPINS_H_ */ avr-libc-1.8.0.orig/include/avr/iox64a1u.h0000644000000000000000000117477511732702554015044 0ustar /* Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ /* avr/iox64a1u.h - definitions for ATxmega64A1U */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox64a1u.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega64A1U_H_ #define _AVR_ATxmega64A1U_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- VPORT - Virtual Ports -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ register8_t USBCTRL; /* USB Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ } CLK_RTCSRC_t; /* USB Prescaler Division Factor */ typedef enum CLK_USBPSDIV_enum { CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ } CLK_USBPSDIV_t; /* USB Clock Source */ typedef enum CLK_USBSRC_enum { CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ } CLK_USBSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* 32 MHz Calibration Reference */ typedef enum OSC_RC32MCREF_enum { OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ } OSC_RC32MCREF_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t ANAINIT; /* Analog Startup Delay */ register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- PORTCFG - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* Virtual Port Mapping */ typedef enum PORTCFG_VP02MAP_enum { PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP02MAP_t; /* Virtual Port Mapping */ typedef enum PORTCFG_VP13MAP_enum { PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP13MAP_t; /* System Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Peripheral Clock Output Select */ typedef enum PORTCFG_CLKOUTSEL_enum { PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ } PORTCFG_CLKOUTSEL_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* -------------------------------------------------------------------------- CRC - Cyclic Redundancy Checker -------------------------------------------------------------------------- */ /* Cyclic Redundancy Checker */ typedef struct CRC_struct { register8_t CTRL; /* CRC Control Register */ register8_t STATUS; /* CRC Status Register */ register8_t DATAIN; /* CRC Data Input */ register8_t CHECKSUM0; /* CRC Checksum byte 0 */ register8_t CHECKSUM1; /* CRC Checksum byte 1 */ register8_t CHECKSUM2; /* CRC Checksum byte 2 */ register8_t CHECKSUM3; /* CRC Checksum byte 3 */ } CRC_t; /* CRC Reset */ typedef enum CRC_RESET_enum { CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ } CRC_RESET_t; /* CRC Input Source */ typedef enum CRC_SOURCE_enum { CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ } CRC_SOURCE_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Current Limitation Mode */ typedef enum ADC_CURRENT_enum { ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */ ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */ ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */ ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */ } ADC_CURRENT_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t CH0GAINCAL; /* Gain Calibration */ register8_t CH0OFFSETCAL; /* Offset Calibration */ register8_t CH1GAINCAL; /* Gain Calibration */ register8_t CH1OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Analog Comparator 0 Control */ register8_t AC1CTRL; /* Analog Comparator 1 Control */ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- USB - USB Module -------------------------------------------------------------------------- */ /* USB Endpoint */ typedef struct USB_EP_struct { register8_t STATUS; /* Endpoint Status */ register8_t CTRL; /* Endpoint Control */ register8_t CNTL; /* USB Endpoint Counter Low Byte */ register8_t CNTH; /* USB Endpoint Counter High Byte */ register8_t DATAPTRL; /* Data Pointer Low Byte */ register8_t DATAPTRH; /* Data Pointer High Byte */ register8_t AUXDATAL; /* Auxiliary Data Low Byte */ register8_t AUXDATAH; /* Auxiliary Data High Byte */ } USB_EP_t; /* -------------------------------------------------------------------------- USB - USB Module -------------------------------------------------------------------------- */ /* USB Endpoint table */ typedef struct USB_EP_TABLE_struct { USB_EP_t EP0OUT; /* USB Endpoint 0 Output */ USB_EP_t EP0IN; /* USB Endpoint 0 Input */ USB_EP_t EP1OUT; /* USB Endpoint 1 Output */ USB_EP_t EP1IN; /* USB Endpoint 1 Input */ USB_EP_t EP2OUT; /* USB Endpoint 2 Output */ USB_EP_t EP2IN; /* USB Endpoint 2 Input */ USB_EP_t EP3OUT; /* USB Endpoint 3 Output */ USB_EP_t EP3IN; /* USB Endpoint 3 Input */ USB_EP_t EP4OUT; /* USB Endpoint 4 Output */ USB_EP_t EP4IN; /* USB Endpoint 4 Input */ USB_EP_t EP5OUT; /* USB Endpoint 5 Output */ USB_EP_t EP5IN; /* USB Endpoint 5 Input */ USB_EP_t EP6OUT; /* USB Endpoint 6 Output */ USB_EP_t EP6IN; /* USB Endpoint 6 Input */ USB_EP_t EP7OUT; /* USB Endpoint 7 Output */ USB_EP_t EP7IN; /* USB Endpoint 7 Input */ USB_EP_t EP8OUT; /* USB Endpoint 8 Output */ USB_EP_t EP8IN; /* USB Endpoint 8 Input */ USB_EP_t EP9OUT; /* USB Endpoint 9 Output */ USB_EP_t EP9IN; /* USB Endpoint 9 Input */ USB_EP_t EP10OUT; /* USB Endpoint 10 Output */ USB_EP_t EP10IN; /* USB Endpoint 10 Input */ USB_EP_t EP11OUT; /* USB Endpoint 11 Output */ USB_EP_t EP11IN; /* USB Endpoint 11 Input */ USB_EP_t EP12OUT; /* USB Endpoint 12 Output */ USB_EP_t EP12IN; /* USB Endpoint 12 Input */ USB_EP_t EP13OUT; /* USB Endpoint 13 Output */ USB_EP_t EP13IN; /* USB Endpoint 13 Input */ USB_EP_t EP14OUT; /* USB Endpoint 14 Output */ USB_EP_t EP14IN; /* USB Endpoint 14 Input */ USB_EP_t EP15OUT; /* USB Endpoint 15 Output */ USB_EP_t EP15IN; /* USB Endpoint 15 Input */ register8_t FRAMENUML; /* Frame Number Low Byte */ register8_t FRAMENUMH; /* Frame Number High Byte */ } USB_EP_TABLE_t; /* -------------------------------------------------------------------------- USB - USB Module -------------------------------------------------------------------------- */ /* USB Module */ typedef struct USB_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t FIFOWP; /* FIFO Write Pointer Register */ register8_t FIFORP; /* FIFO Read Pointer Register */ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t reserved_0x20; register8_t reserved_0x21; register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t CAL0; /* Calibration Byte 0 */ register8_t CAL1; /* Calibration Byte 1 */ } USB_t; /* USB Endpoint Type */ typedef enum USB_EP_TYPE_enum { USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ } USB_EP_TYPE_t; /* USB Endpoint Buffer Size */ typedef enum USB_EP_SIZE_enum { USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ USB_EP_SIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ USB_EP_SIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ USB_EP_SIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ USB_EP_SIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ USB_EP_SIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ } USB_EP_SIZE_t; /* Interrupt level */ typedef enum USB_INTLVL_enum { USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ USB_INTLVL_LO_gc = (0x01<<0), /* Low Level */ USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ USB_INTLVL_HI_gc = (0x03<<0), /* High Level */ } USB_INTLVL_t; /* -------------------------------------------------------------------------- PORT - I/O Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* -------------------------------------------------------------------------- AWEX - Timer/Counter Advanced Waveform Extension -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* -------------------------------------------------------------------------- HIRES - Timer/Counter High-Resolution Extension -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- PRESC - Prescaler -------------------------------------------------------------------------- */ /* Prescaler */ typedef struct PRESC_struct { register8_t PRESCALER; /* Control Register */ } PRESC_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define CRC (*(CRC_t *) 0x00D0) /* CRC Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ #define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ #define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus Module */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTH (*(PORT_t *) 0x06E0) /* Port H */ #define PORTJ (*(PORT_t *) 0x0700) /* Port J */ #define PORTK (*(PORT_t *) 0x0720) /* Port K */ #define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) #define CLK_USBCTRL _SFR_MEM8(0x0044) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x005F) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_ANAINIT _SFR_MEM8(0x0097) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* CRC - CRC Module */ #define CRC_CTRL _SFR_MEM8(0x00D0) #define CRC_STATUS _SFR_MEM8(0x00D1) #define CRC_DATAIN _SFR_MEM8(0x00D3) #define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) #define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) #define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) #define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_TEMP _SFR_MEM8(0x0207) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* ADCB - Analog to Digital Converter B */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) #define ADCB_EVCTRL _SFR_MEM8(0x0243) #define ADCB_PRESCALER _SFR_MEM8(0x0244) #define ADCB_INTFLAGS _SFR_MEM8(0x0246) #define ADCB_TEMP _SFR_MEM8(0x0247) #define ADCB_CAL _SFR_MEM16(0x024C) #define ADCB_CH0RES _SFR_MEM16(0x0250) #define ADCB_CH1RES _SFR_MEM16(0x0252) #define ADCB_CH2RES _SFR_MEM16(0x0254) #define ADCB_CH3RES _SFR_MEM16(0x0256) #define ADCB_CMP _SFR_MEM16(0x0258) #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) /* DACA - Digital to Analog Converter A */ #define DACA_CTRLA _SFR_MEM8(0x0300) #define DACA_CTRLB _SFR_MEM8(0x0301) #define DACA_CTRLC _SFR_MEM8(0x0302) #define DACA_EVCTRL _SFR_MEM8(0x0303) #define DACA_TIMCTRL _SFR_MEM8(0x0304) #define DACA_STATUS _SFR_MEM8(0x0305) #define DACA_CH0GAINCAL _SFR_MEM8(0x0308) #define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) #define DACA_CH1GAINCAL _SFR_MEM8(0x030A) #define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) #define DACA_CH0DATA _SFR_MEM16(0x0318) #define DACA_CH1DATA _SFR_MEM16(0x031A) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_CH0GAINCAL _SFR_MEM8(0x0328) #define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH1GAINCAL _SFR_MEM8(0x032A) #define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* EBI - External Bus Interface */ #define EBI_CTRL _SFR_MEM8(0x0440) #define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) #define EBI_REFRESH _SFR_MEM16(0x0444) #define EBI_INITDLY _SFR_MEM16(0x0446) #define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) #define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) #define EBI_CS0_CTRLA _SFR_MEM8(0x0450) #define EBI_CS0_CTRLB _SFR_MEM8(0x0451) #define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) #define EBI_CS1_CTRLA _SFR_MEM8(0x0454) #define EBI_CS1_CTRLB _SFR_MEM8(0x0455) #define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) #define EBI_CS2_CTRLA _SFR_MEM8(0x0458) #define EBI_CS2_CTRLB _SFR_MEM8(0x0459) #define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) #define EBI_CS3_CTRLA _SFR_MEM8(0x045C) #define EBI_CS3_CTRLB _SFR_MEM8(0x045D) #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWID - Two-Wire Interface D */ #define TWID_CTRL _SFR_MEM8(0x0490) #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) #define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) #define TWID_MASTER_STATUS _SFR_MEM8(0x0494) #define TWID_MASTER_BAUD _SFR_MEM8(0x0495) #define TWID_MASTER_ADDR _SFR_MEM8(0x0496) #define TWID_MASTER_DATA _SFR_MEM8(0x0497) #define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) #define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) #define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) #define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) #define TWID_SLAVE_DATA _SFR_MEM8(0x049C) #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* TWIF - Two-Wire Interface F */ #define TWIF_CTRL _SFR_MEM8(0x04B0) #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) #define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) #define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) #define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) #define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) #define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) #define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) #define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) #define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) #define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) /* USB - Universal Serial Bus Module */ #define USB_CTRLA _SFR_MEM8(0x04C0) #define USB_CTRLB _SFR_MEM8(0x04C1) #define USB_STATUS _SFR_MEM8(0x04C2) #define USB_ADDR _SFR_MEM8(0x04C3) #define USB_FIFOWP _SFR_MEM8(0x04C4) #define USB_FIFORP _SFR_MEM8(0x04C5) #define USB_EPPTR _SFR_MEM16(0x04C6) #define USB_INTCTRLA _SFR_MEM8(0x04C8) #define USB_INTCTRLB _SFR_MEM8(0x04C9) #define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) #define USB_INTFLAGSASET _SFR_MEM8(0x04CB) #define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) #define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) #define USB_CAL0 _SFR_MEM8(0x04FA) #define USB_CAL1 _SFR_MEM8(0x04FB) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTH - Port H */ #define PORTH_DIR _SFR_MEM8(0x06E0) #define PORTH_DIRSET _SFR_MEM8(0x06E1) #define PORTH_DIRCLR _SFR_MEM8(0x06E2) #define PORTH_DIRTGL _SFR_MEM8(0x06E3) #define PORTH_OUT _SFR_MEM8(0x06E4) #define PORTH_OUTSET _SFR_MEM8(0x06E5) #define PORTH_OUTCLR _SFR_MEM8(0x06E6) #define PORTH_OUTTGL _SFR_MEM8(0x06E7) #define PORTH_IN _SFR_MEM8(0x06E8) #define PORTH_INTCTRL _SFR_MEM8(0x06E9) #define PORTH_INT0MASK _SFR_MEM8(0x06EA) #define PORTH_INT1MASK _SFR_MEM8(0x06EB) #define PORTH_INTFLAGS _SFR_MEM8(0x06EC) #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) #define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) #define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) #define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) /* PORTJ - Port J */ #define PORTJ_DIR _SFR_MEM8(0x0700) #define PORTJ_DIRSET _SFR_MEM8(0x0701) #define PORTJ_DIRCLR _SFR_MEM8(0x0702) #define PORTJ_DIRTGL _SFR_MEM8(0x0703) #define PORTJ_OUT _SFR_MEM8(0x0704) #define PORTJ_OUTSET _SFR_MEM8(0x0705) #define PORTJ_OUTCLR _SFR_MEM8(0x0706) #define PORTJ_OUTTGL _SFR_MEM8(0x0707) #define PORTJ_IN _SFR_MEM8(0x0708) #define PORTJ_INTCTRL _SFR_MEM8(0x0709) #define PORTJ_INT0MASK _SFR_MEM8(0x070A) #define PORTJ_INT1MASK _SFR_MEM8(0x070B) #define PORTJ_INTFLAGS _SFR_MEM8(0x070C) #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) #define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) #define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) #define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) /* PORTK - Port K */ #define PORTK_DIR _SFR_MEM8(0x0720) #define PORTK_DIRSET _SFR_MEM8(0x0721) #define PORTK_DIRCLR _SFR_MEM8(0x0722) #define PORTK_DIRTGL _SFR_MEM8(0x0723) #define PORTK_OUT _SFR_MEM8(0x0724) #define PORTK_OUTSET _SFR_MEM8(0x0725) #define PORTK_OUTCLR _SFR_MEM8(0x0726) #define PORTK_OUTTGL _SFR_MEM8(0x0727) #define PORTK_IN _SFR_MEM8(0x0728) #define PORTK_INTCTRL _SFR_MEM8(0x0729) #define PORTK_INT0MASK _SFR_MEM8(0x072A) #define PORTK_INT1MASK _SFR_MEM8(0x072B) #define PORTK_INTFLAGS _SFR_MEM8(0x072C) #define PORTK_PIN0CTRL _SFR_MEM8(0x0730) #define PORTK_PIN1CTRL _SFR_MEM8(0x0731) #define PORTK_PIN2CTRL _SFR_MEM8(0x0732) #define PORTK_PIN3CTRL _SFR_MEM8(0x0733) #define PORTK_PIN4CTRL _SFR_MEM8(0x0734) #define PORTK_PIN5CTRL _SFR_MEM8(0x0735) #define PORTK_PIN6CTRL _SFR_MEM8(0x0736) #define PORTK_PIN7CTRL _SFR_MEM8(0x0737) /* PORTQ - Port Q */ #define PORTQ_DIR _SFR_MEM8(0x07C0) #define PORTQ_DIRSET _SFR_MEM8(0x07C1) #define PORTQ_DIRCLR _SFR_MEM8(0x07C2) #define PORTQ_DIRTGL _SFR_MEM8(0x07C3) #define PORTQ_OUT _SFR_MEM8(0x07C4) #define PORTQ_OUTSET _SFR_MEM8(0x07C5) #define PORTQ_OUTCLR _SFR_MEM8(0x07C6) #define PORTQ_OUTTGL _SFR_MEM8(0x07C7) #define PORTQ_IN _SFR_MEM8(0x07C8) #define PORTQ_INTCTRL _SFR_MEM8(0x07C9) #define PORTQ_INT0MASK _SFR_MEM8(0x07CA) #define PORTQ_INT1MASK _SFR_MEM8(0x07CB) #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) #define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) #define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) #define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* TCE1 - Timer/Counter E1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) #define TCE1_CTRLD _SFR_MEM8(0x0A43) #define TCE1_CTRLE _SFR_MEM8(0x0A44) #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) #define TCE1_TEMP _SFR_MEM8(0x0A4F) #define TCE1_CNT _SFR_MEM16(0x0A60) #define TCE1_PER _SFR_MEM16(0x0A66) #define TCE1_CCA _SFR_MEM16(0x0A68) #define TCE1_CCB _SFR_MEM16(0x0A6A) #define TCE1_PERBUF _SFR_MEM16(0x0A76) #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) #define USARTE1_CTRLB _SFR_MEM8(0x0AB4) #define USARTE1_CTRLC _SFR_MEM8(0x0AB5) #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /* TCF1 - Timer/Counter F1 */ #define TCF1_CTRLA _SFR_MEM8(0x0B40) #define TCF1_CTRLB _SFR_MEM8(0x0B41) #define TCF1_CTRLC _SFR_MEM8(0x0B42) #define TCF1_CTRLD _SFR_MEM8(0x0B43) #define TCF1_CTRLE _SFR_MEM8(0x0B44) #define TCF1_INTCTRLA _SFR_MEM8(0x0B46) #define TCF1_INTCTRLB _SFR_MEM8(0x0B47) #define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) #define TCF1_CTRLFSET _SFR_MEM8(0x0B49) #define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) #define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) #define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) #define TCF1_TEMP _SFR_MEM8(0x0B4F) #define TCF1_CNT _SFR_MEM16(0x0B60) #define TCF1_PER _SFR_MEM16(0x0B66) #define TCF1_CCA _SFR_MEM16(0x0B68) #define TCF1_CCB _SFR_MEM16(0x0B6A) #define TCF1_PERBUF _SFR_MEM16(0x0B76) #define TCF1_CCABUF _SFR_MEM16(0x0B78) #define TCF1_CCBBUF _SFR_MEM16(0x0B7A) /* HIRESF - High-Resolution Extension F */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) /* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) #define USARTF1_CTRLB _SFR_MEM8(0x0BB4) #define USARTF1_CTRLC _SFR_MEM8(0x0BB5) #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) /* SPIF - Serial Peripheral Interface F */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) #define SPIF_DATA _SFR_MEM8(0x0BC3) /*================== Bitfield Definitions ================== */ /* VPORT - Virtual Ports */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ /* CLK.USBCTRL bit masks and bit positions */ #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ #define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ #define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ #define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ #define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ #define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ #define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ #define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ #define CLK_USBSRC_gp 1 /* Clock Source group position. */ #define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_USBEN_bm 0x01 /* Clock Source Enable bit mask. */ #define CLK_USBEN_bp 0 /* Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_USB_bm 0x40 /* USB bit mask. */ #define PR_USB_bp 6 /* USB bit position. */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ #define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ #define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ #define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_gm 0x06 /* 32 MHz Calibration Reference group mask. */ #define OSC_RC32MCREF_gp 1 /* 32 MHz Calibration Reference group position. */ #define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz Calibration Reference bit 0 mask. */ #define OSC_RC32MCREF0_bp 1 /* 32 MHz Calibration Reference bit 0 position. */ #define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz Calibration Reference bit 1 mask. */ #define OSC_RC32MCREF1_bp 2 /* 32 MHz Calibration Reference bit 1 position. */ #define OSC_RC2MCREF_bm 0x01 /* 2 MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2 MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.ANAINIT bit masks and bit positions */ #define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port A group mask. */ #define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port A group position. */ #define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port A bit 0 mask. */ #define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port A bit 0 position. */ #define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port A bit 1 mask. */ #define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port A bit 1 position. */ #define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port B group mask. */ #define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port B group position. */ #define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port B bit 0 mask. */ #define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port B bit 0 position. */ #define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port B bit 1 mask. */ #define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port B bit 1 position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* PORTCFG - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ #define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ #define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ #define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ #define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ #define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ #define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ #define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ #define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* CRC - Cyclic Redundancy Checker */ /* CRC.CTRL bit masks and bit positions */ #define CRC_RESET_gm 0xC0 /* CRC Reset group mask. */ #define CRC_RESET_gp 6 /* CRC Reset group position. */ #define CRC_RESET0_bm (1<<6) /* CRC Reset bit 0 mask. */ #define CRC_RESET0_bp 6 /* CRC Reset bit 0 position. */ #define CRC_RESET1_bm (1<<7) /* CRC Reset bit 1 mask. */ #define CRC_RESET1_bp 7 /* CRC Reset bit 1 position. */ #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ #define CRC_SOURCE_gm 0x0F /* CRC Input Source group mask. */ #define CRC_SOURCE_gp 0 /* CRC Input Source group position. */ #define CRC_SOURCE0_bm (1<<0) /* CRC Input Source bit 0 mask. */ #define CRC_SOURCE0_bp 0 /* CRC Input Source bit 0 position. */ #define CRC_SOURCE1_bm (1<<1) /* CRC Input Source bit 1 mask. */ #define CRC_SOURCE1_bp 1 /* CRC Input Source bit 1 position. */ #define CRC_SOURCE2_bm (1<<2) /* CRC Input Source bit 2 mask. */ #define CRC_SOURCE2_bp 2 /* CRC Input Source bit 2 position. */ #define CRC_SOURCE3_bm (1<<3) /* CRC Input Source bit 3 mask. */ #define CRC_SOURCE3_bp 3 /* CRC Input Source bit 3 position. */ /* CRC.STATUS bit masks and bit positions */ #define CRC_ZERO_bm 0x02 /* Zero CRC detection bit mask. */ #define CRC_ZERO_bp 1 /* Zero CRC detection bit position. */ #define CRC_BUSY_bm 0x01 /* Enable bit mask. */ #define CRC_BUSY_bp 0 /* Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0x7F /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ #define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ #define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ #define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ #define ADC_CURRENT_gm 0x60 /* Current Limitation group mask. */ #define ADC_CURRENT_gp 5 /* Current Limitation group position. */ #define ADC_CURRENT0_bm (1<<5) /* Current Limitation bit 0 mask. */ #define ADC_CURRENT0_bp 5 /* Current Limitation bit 0 position. */ #define ADC_CURRENT1_bm (1<<6) /* Current Limitation bit 1 mask. */ #define ADC_CURRENT1_bp 6 /* Current Limitation bit 1 position. */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ #define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ #define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* DAC.CH0GAINCAL bit masks and bit positions */ #define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ #define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ #define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ #define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ #define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ #define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ #define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ #define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ #define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ #define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ #define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ #define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ #define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ #define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ #define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ #define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ /* DAC.CH0OFFSETCAL bit masks and bit positions */ #define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ #define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ #define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ #define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ #define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ #define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ #define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ #define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ #define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ #define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ #define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ #define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ #define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ #define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ #define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ #define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ /* DAC.CH1GAINCAL bit masks and bit positions */ #define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ #define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ #define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ #define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ #define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ #define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ #define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ #define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ #define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ #define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ #define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ #define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ #define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ #define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ #define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ #define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ /* DAC.CH1OFFSETCAL bit masks and bit positions */ #define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ #define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ #define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ #define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ #define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ #define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ #define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ #define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ #define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ #define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ #define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ #define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ #define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ #define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ #define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ #define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* USB - USB Module */ /* USB_EP.STATUS bit masks and bit positions */ #define USB_EP_STALL_bm 0x80 /* Endpoint Stall Flag bit mask. */ #define USB_EP_STALL_bp 7 /* Endpoint Stall Flag bit position. */ #define USB_EP_CRC_bm 0x80 /* CRC Error Flag for Isochronous Out Endpoints bit mask. */ #define USB_EP_CRC_bp 7 /* CRC Error Flag for Isochronous Out Endpoints bit position. */ #define USB_EP_UNF_bm 0x40 /* Underflow Enpoint Flag for Input Endpoints bit mask. */ #define USB_EP_UNF_bp 6 /* Underflow Enpoint Flag for Input Endpoints bit position. */ #define USB_EP_OVF_bm 0x40 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */ #define USB_EP_OVF_bp 6 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */ #define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete Flag bit mask. */ #define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete Flag bit position. */ #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ #define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ #define USB_EP_BANK_bp 3 /* Bank Select bit position. */ #define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ #define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ #define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ #define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ /* USB_EP.CTRL bit masks and bit positions */ #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ #define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ #define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ #define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ #define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ #define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ #define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ #define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ #define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ /* USB_EP_STALL_bm Predefined. */ /* USB_EP_STALL_bp Predefined. */ #define USB_EP_SIZE_gm 0x07 /* Data Buffer Size group mask. */ #define USB_EP_SIZE_gp 0 /* Data Buffer Size group position. */ #define USB_EP_SIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ #define USB_EP_SIZE0_bp 0 /* Data Buffer Size bit 0 position. */ #define USB_EP_SIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ #define USB_EP_SIZE1_bp 1 /* Data Buffer Size bit 1 position. */ #define USB_EP_SIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ #define USB_EP_SIZE2_bp 2 /* Data Buffer Size bit 2 position. */ /* USB_EP.CNTH bit masks and bit positions */ #define USB_EP_ZLP_bm 0x80 /* Zero Length Packet bit mask. */ #define USB_EP_ZLP_bp 7 /* Zero Length Packet bit position. */ #define USB_EP_CNT_gm 0x03 /* Endpoint Byte Counter group mask. */ #define USB_EP_CNT_gp 0 /* Endpoint Byte Counter group position. */ #define USB_EP_CNT0_bm (1<<0) /* Endpoint Byte Counter bit 0 mask. */ #define USB_EP_CNT0_bp 0 /* Endpoint Byte Counter bit 0 position. */ #define USB_EP_CNT1_bm (1<<1) /* Endpoint Byte Counter bit 1 mask. */ #define USB_EP_CNT1_bp 1 /* Endpoint Byte Counter bit 1 position. */ /* USB.CTRLA bit masks and bit positions */ #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ #define USB_ENABLE_bp 7 /* USB Enable bit position. */ #define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ #define USB_SPEED_bp 6 /* Speed Select bit position. */ #define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ #define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ #define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ #define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ #define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ #define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ #define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ #define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ #define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ #define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ #define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ #define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ /* USB.CTRLB bit masks and bit positions */ #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ #define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ #define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ #define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ #define USB_GNACK_bp 1 /* Global NACK bit position. */ #define USB_ATTACH_bm 0x01 /* Attach bit mask. */ #define USB_ATTACH_bp 0 /* Attach bit position. */ /* USB.STATUS bit masks and bit positions */ #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ #define USB_URESUME_bp 3 /* Upstream Resume bit position. */ #define USB_RESUME_bm 0x04 /* Resume bit mask. */ #define USB_RESUME_bp 2 /* Resume bit position. */ #define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ #define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ #define USB_BUSRST_bp 0 /* Bus Reset bit position. */ /* USB.ADDR bit masks and bit positions */ #define USB_ADDR_gm 0x7F /* Device Address group mask. */ #define USB_ADDR_gp 0 /* Device Address group position. */ #define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ #define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ #define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ #define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ #define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ #define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ #define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ #define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ #define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ #define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ #define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ #define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ /* USB.FIFOWP bit masks and bit positions */ #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ #define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ #define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ #define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ #define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ #define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ #define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ #define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ #define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ /* USB.FIFORP bit masks and bit positions */ #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ #define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ #define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ #define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ #define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ #define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ #define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ #define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ #define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ /* USB.INTCTRLA bit masks and bit positions */ #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ #define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ #define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ #define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ #define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ #define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ #define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ #define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define USB_INTLVL_gp 0 /* Interrupt Level group position. */ #define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* USB.INTCTRLB bit masks and bit positions */ #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ /* USB.INTFLAGSACLR bit masks and bit positions */ #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ #define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ #define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ #define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ #define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ #define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ #define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ #define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ #define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ #define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ #define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ #define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ #define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ /* USB.INTFLAGSASET bit masks and bit positions */ /* USB_SOFIF_bm Predefined. */ /* USB_SOFIF_bp Predefined. */ /* USB_SUSPENDIF_bm Predefined. */ /* USB_SUSPENDIF_bp Predefined. */ /* USB_RESUMEIF_bm Predefined. */ /* USB_RESUMEIF_bp Predefined. */ /* USB_RSTIF_bm Predefined. */ /* USB_RSTIF_bp Predefined. */ /* USB_CRCIF_bm Predefined. */ /* USB_CRCIF_bp Predefined. */ /* USB_UNFIF_bm Predefined. */ /* USB_UNFIF_bp Predefined. */ /* USB_OVFIF_bm Predefined. */ /* USB_OVFIF_bp Predefined. */ /* USB_STALLIF_bm Predefined. */ /* USB_STALLIF_bp Predefined. */ /* USB.INTFLAGSBCLR bit masks and bit positions */ #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ #define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ /* USB.INTFLAGSBSET bit masks and bit positions */ /* USB_TRNIF_bm Predefined. */ /* USB_TRNIF_bp Predefined. */ /* USB_SETUPIF_bm Predefined. */ /* USB_SETUPIF_bp Predefined. */ /* PORT - I/O Port Configuration */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX - Timer/Counter Advanced Waveform Extension */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES - Timer/Counter High-Resolution Extension */ /* HIRES.CTRLA bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* PRESC - Prescaler */ /* PRESC.PRESCALER bit masks and bit positions */ #define PRESC_RESET_bm 0x01 /* Reset bit mask. */ #define PRESC_RESET_bp 0 /* Reset bit position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_OSCF_vect_num 1 #define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_SPM_vect_num 32 #define NVM_SPM_vect _VECTOR(32) /* SPM Interrupt */ #define NVM_EE_vect_num 33 #define NVM_EE_vect _VECTOR(33) /* EE Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* ACB interrupt vectors */ #define ACB_AC0_vect_num 36 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ #define ACB_AC1_vect_num 37 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ #define ACB_ACW_vect_num 38 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ /* ADCB interrupt vectors */ #define ADCB_CH0_vect_num 39 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ #define ADCB_CH1_vect_num 40 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ #define ADCB_CH2_vect_num 41 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ #define ADCB_CH3_vect_num 42 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* SPIE interrupt vectors */ #define SPIE_INT_vect_num 57 #define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* USARTE1 interrupt vectors */ #define USARTE1_RXC_vect_num 61 #define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ #define USARTE1_DRE_vect_num 62 #define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ #define USARTE1_TXC_vect_num 63 #define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TWID interrupt vectors */ #define TWID_TWIS_vect_num 75 #define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ #define TWID_TWIM_vect_num 76 #define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ /* PORTQ interrupt vectors */ #define PORTQ_INT0_vect_num 94 #define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ #define PORTQ_INT1_vect_num 95 #define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ /* PORTH interrupt vectors */ #define PORTH_INT0_vect_num 96 #define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ #define PORTH_INT1_vect_num 97 #define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ /* PORTJ interrupt vectors */ #define PORTJ_INT0_vect_num 98 #define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ #define PORTJ_INT1_vect_num 99 #define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ /* PORTK interrupt vectors */ #define PORTK_INT0_vect_num 100 #define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ #define PORTK_INT1_vect_num 101 #define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TWIF interrupt vectors */ #define TWIF_TWIS_vect_num 106 #define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ #define TWIF_TWIM_vect_num 107 #define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ /* TCF1 interrupt vectors */ #define TCF1_OVF_vect_num 114 #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ #define TCF1_ERR_vect_num 115 #define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ #define TCF1_CCA_vect_num 116 #define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ #define TCF1_CCB_vect_num 117 #define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ /* SPIF interrupt vectors */ #define SPIF_INT_vect_num 118 #define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ /* USARTF0 interrupt vectors */ #define USARTF0_RXC_vect_num 119 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ #define USARTF0_DRE_vect_num 120 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ #define USARTF0_TXC_vect_num 121 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ /* USARTF1 interrupt vectors */ #define USARTF1_RXC_vect_num 122 #define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ #define USARTF1_DRE_vect_num 123 #define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ #define USARTF1_TXC_vect_num 124 #define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ /* USB interrupt vectors */ #define USB_BUSEVENT_vect_num 125 #define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts and crc, underflow, overflow and stall error interrupts */ #define USB_TRNCOMPL_vect_num 127 #define USB_TRNCOMPL_vect _VECTOR(127) /* Transaction complete interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (128 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x00000) #define PROGMEM_SIZE (69632) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x00000) #define APP_SECTION_SIZE (65536) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x1E000) #define APPTABLE_SECTION_SIZE (4096) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x20000) #define BOOT_SECTION_SIZE (4096) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (16777216) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (4096) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EXTERNAL_SRAM_START (0x4000) #define EXTERNAL_SRAM_SIZE (16760832) #define EXTERNAL_SRAM_PAGE_SIZE (0) #define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND EXTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 0 /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x4E #endif /* _AVR_ATxmega64A1U_H_ */ avr-libc-1.8.0.orig/include/avr/iomxxhva.h0000644000000000000000000002620211732702554015303 0ustar /* Copyright (c) 2007, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iomxxhva.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* iomxxhva.h - definitions for ATmega8HVA and ATmega16HVA. */ #ifndef _AVR_IOMXXHVA_H_ #define _AVR_IOMXXHVA_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iomxxhva.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0X00) #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0X03) #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC0 0 /* Reserved [0x7] */ #define PORTC _SFR_IO8(0x08) #define PC0 0 /* Reserved [0x9..0x14] */ #define TIFR0 _SFR_IO8(0x15) #define ICF0 3 #define OCF0B 2 #define OCF0A 1 #define TOV0 0 #define TIFR1 _SFR_IO8(0x16) #define ICF1 3 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 #define OSICSR _SFR_IO8(0x17) #define OSISEL0 4 #define OSIST 1 #define OSIEN 0 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF2 2 #define INTF1 1 #define INTF0 0 #define EIMSK _SFR_IO8(0x1D) #define INT2 2 #define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 #define EEDR _SFR_IO8(0x20) #define EEAR _SFR_IO8(0x21) #define EEARL _SFR_IO8(0x21) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* Reserved [0x22] */ #define GTCCR _SFR_IO8(0x23) #define TSM 7 #define PSRSYNC 0 #define TCCR0A _SFR_IO8(0x24) #define TCW0 7 #define ICEN0 6 #define ICNC0 5 #define ICES0 4 #define ICS0 3 #define WGM00 0 #define TCCR0B _SFR_IO8(0x25) #define CS02 2 #define CS01 1 #define CS00 0 #define TCNT0 _SFR_IO16(0X26) #define TCNT0L _SFR_IO8(0X26) #define TCNT0H _SFR_IO8(0X27) #define OCR0A _SFR_IO8(0x28) #define OCR0B _SFR_IO8(0X29) #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 #define SPSR _SFR_IO8(0x2D) #define SPIF 7 #define WCOL 6 #define SPI2X 0 #define SPDR _SFR_IO8(0x2E) /* Reserved [0x2F..0x30] */ #define DWDR _SFR_IO8(0x31) #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 #define MCUSR _SFR_IO8(0x34) #define OCDRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 #define MCUCR _SFR_IO8(0x35) #define CKOE 5 #define PUD 4 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SIGRD 5 #define CTPB 4 #define RFLB 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCSR _SFR_MEM8(0x60) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 #define CLKPR _SFR_MEM8(0x61) #define CLKPCE 7 #define CLKPS1 1 #define CLKPS0 0 /* Reserved [0x62..0x63] */ #define PRR0 _SFR_MEM8(0x64) #define PRVRM 5 #define PRSPI 3 #define PRTIM1 2 #define PRTIM0 1 #define PRVADC 0 /* Reserved [0x65] */ #define FOSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Reserved [0x6A..0x6D] */ #define TIMSK0 _SFR_MEM8(0x6E) #define ICIE0 3 #define OCIE0B 2 #define OCIE0A 1 #define TOIE0 0 #define TIMSK1 _SFR_MEM8(0x6F) #define ICIE1 3 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 /* Reserved [0x70..0x77] */ #define VADC _SFR_MEM16(0x78) #define VADCL _SFR_MEM8(0x78) #define VADCH _SFR_MEM8(0x79) #define VADCSR _SFR_MEM8(0x7A) #define VADEN 3 #define VADSC 2 #define VADCCIF 1 #define VADCCIE 0 /* Reserved [0x7B] */ #define VADMUX _SFR_MEM8(0x7C) #define VADMUX3 3 #define VADMUX2 2 #define VADMUX1 1 #define VADMUX0 0 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define PA1DID 1 #define PA0DID 0 /* Reserved [0x7F] */ #define TCCR1A _SFR_MEM8(0x80) #define TCW1 7 #define ICEN1 6 #define ICNC1 5 #define ICES1 4 #define ICS1 3 #define WGM10 0 #define TCCR1B _SFR_MEM8(0x81) #define CS12 2 #define CS11 1 #define CS10 0 /* Reserved [0x82..0x83] */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Reserved [0x86..0x87] */ #define OCR1A _SFR_MEM8(0x88) #define OCR1B _SFR_MEM8(0x89) /* Reserved [0x8A..0xC7] */ #define ROCR _SFR_MEM8(0xC8) #define ROCS 7 #define ROCWIF 1 #define ROCWIE 0 /* Reserved [0xC9..0xCF] */ #define BGCCR _SFR_MEM8(0xD0) #define BGD 7 #define BGCC5 5 #define BGCC4 4 #define BGCC3 3 #define BGCC2 2 #define BGCC1 1 #define BGCC0 0 #define BGCRR _SFR_MEM8(0xD1) #define BGCR7 7 #define BGCR6 6 #define BGCR5 5 #define BGCR4 4 #define BGCR3 3 #define BGCR2 2 #define BGCR1 1 #define BGCR0 0 /* Reserved [0xD2..0xDF] */ /* CC-ADC Accumulate Current */ /* TODO: Add _SFR_MEM32 */ /* #define CADAC _SFR_MEM32(0xE0) */ #define CADAC0 _SFR_MEM8(0xE0) #define CADAC1 _SFR_MEM8(0xE1) #define CADAC2 _SFR_MEM8(0xE2) #define CADAC3 _SFR_MEM8(0xE3) #define CADCSRA _SFR_MEM8(0xE4) #define CADEN 7 #define CADPOL 6 #define CADUB 5 #define CADAS1 4 #define CADAS0 3 #define CADSI1 2 #define CADSI0 1 #define CADSE 0 #define CADCSRB _SFR_MEM8(0xE5) #define CADACIE 6 #define CADRCIE 5 #define CADICIE 4 #define CADACIF 2 #define CADRCIF 1 #define CADICIF 0 #define CADRC _SFR_MEM8(0xE6) /* Reserved [0xE7] */ #define CADIC _SFR_MEM16(0xE8) #define CADICL _SFR_MEM8(0xE8) #define CADICH _SFR_MEM8(0xE9) /* Reserved [0xEA..0xEF] */ #define FCSR _SFR_MEM8(0xF0) #define DUVRD 3 #define CPS 2 #define DFE 1 #define CFE 0 /* Reserved [0xF1] */ #define BPIMSK _SFR_MEM8(0xF2) #define SCIE 4 #define DOCIE 3 #define COCIE 2 #define DHCIE 1 #define CHCIE 0 #define BPIFR _SFR_MEM8(0xF3) #define SCIF 4 #define DOCIF 3 #define COCIF 2 #define DHCIF 1 #define CHCIF 0 /* Reserved [0xF4] */ #define BPSCD _SFR_MEM8(0xF5) #define BPDOCD _SFR_MEM8(0xF6) #define BPCOCD _SFR_MEM8(0xF7) #define BPDHCD _SFR_MEM8(0xF8) #define BPCHCD _SFR_MEM8(0xF9) #define BPSCTR _SFR_MEM8(0xFA) #define BPOCTR _SFR_MEM8(0xFB) #define BPHCTR _SFR_MEM8(0xFC) #define BPCR _SFR_MEM8(0xFD) #define SCD 4 #define DOCD 3 #define COCD 2 #define DHCD 1 #define CHCD 0 #define BPPLR _SFR_MEM8(0xFE) #define BPPLE 1 #define BPPL 0 /* Reserved [0xFF] */ /* Interrupt vectors */ /* Battery Protection Interrupt */ #define BPINT_vect_num 1 #define BPINT_vect _VECTOR(1) /* Voltage Regulator Monitor Interrupt */ #define VREGMON_vect_num 2 #define VREGMON_vect _VECTOR(2) /* External Interrupt Request 0 */ #define INT0_vect_num 3 #define INT0_vect _VECTOR(3) /* External Interrupt Request 1 */ #define INT1_vect_num 4 #define INT1_vect _VECTOR(4) /* External Interrupt Request 2 */ #define INT2_vect_num 5 #define INT2_vect _VECTOR(5) /* Watchdog Timeout Interrupt */ #define WDT_vect_num 6 #define WDT_vect _VECTOR(6) /* Timer/Counter 1 Input Capture */ #define TIMER1_IC_vect_num 7 #define TIMER1_IC_vect _VECTOR(7) /* Timer/Counter 1 Compare A Match */ #define TIMER1_COMPA_vect_num 8 #define TIMER1_COMPA_vect _VECTOR(8) /* Timer/Counter 1 Compare B Match */ #define TIMER1_COMPB_vect_num 9 #define TIMER1_COMPB_vect _VECTOR(9) /* Timer/Counter 1 Overflow */ #define TIMER1_OVF_vect_num 10 #define TIMER1_OVF_vect _VECTOR(10) /* Timer/Counter 0 Input Capture */ #define TIMER0_IC_vect_num 11 #define TIMER0_IC_vect _VECTOR(11) /* Timer/Counter0 Compare A Match */ #define TIMER0_COMPA_vect_num 12 #define TIMER0_COMPA_vect _VECTOR(12) /* Timer/Counter0 Compare B Match */ #define TIMER0_COMPB_vect_num 13 #define TIMER0_COMPB_vect _VECTOR(13) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 14 #define TIMER0_OVF_vect _VECTOR(14) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 15 #define SPI_STC_vect _VECTOR(15) /* Voltage ADC Conversion Complete */ #define VADC_vect_num 16 #define VADC_vect _VECTOR(16) /* Coulomb Counter ADC Conversion Complete */ #define CCADC_CONV_vect_num 17 #define CCADC_CONV_vect _VECTOR(17) /* Coloumb Counter ADC Regular Current */ #define CCADC_REG_CUR_vect_num 18 #define CCADC_REG_CUR_vect _VECTOR(18) /* Coloumb Counter ADC Accumulator */ #define CCADC_ACC_vect_num 19 #define CCADC_ACC_vect _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #if defined (__AVR_ATmega16HVA__) # define _VECTORS_SIZE 84 #else # define _VECTORS_SIZE 42 #endif #endif /* _AVR_IOMXXHVA_H_ */ avr-libc-1.8.0.orig/include/avr/iousbxx2.h0000644000000000000000000003773711732702554015242 0ustar /* Copyright (c) 2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iousbxx2.h 2246 2011-05-14 20:02:02Z joerg_wunsch $ */ /* iousbxx2.h - definitions for AT90USB82 and AT90USB162. */ #ifndef _AVR_IOUSBXX2_H_ #define _AVR_IOUSBXX2_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iousbxx2.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ /* Reserved [0x00..0x02] */ #define PINB _SFR_IO8(0X03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Reserved [0xC..0x14] */ #define TIFR0 _SFR_IO8(0x15) #define OCF0B 2 #define OCF0A 1 #define TOV0 0 #define TIFR1 _SFR_IO8(0x16) #define ICF1 5 #define OCF1C 3 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 /* Reserved [0x17..0x1A] */ #define PCIFR _SFR_IO8(0x1B) #define PCIF1 1 #define PCIF0 0 #define EIFR _SFR_IO8(0x1C) #define INTF7 7 #define INTF6 6 #define INTF5 5 #define INTF4 4 #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 #define EIMSK _SFR_IO8(0x1D) #define INT7 7 #define INT6 6 #define INT5 5 #define INT4 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 #define EEDR _SFR_IO8(0x20) #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0x22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define TSM 7 #define PSRASY 1 #define PSRSYNC 0 #define TCCR0A _SFR_IO8(0x24) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 #define TCCR0B _SFR_IO8(0x25) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0x27) #define OCR0B _SFR_IO8(0X28) #define PLLCSR _SFR_IO8(0x29) #define PLLP2 4 #define PLLP1 3 #define PLLP0 2 #define PLLE 1 #define PLOCK 0 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 #define SPSR _SFR_IO8(0x2D) #define SPIF 7 #define WCOL 6 #define SPI2X 0 #define SPDR _SFR_IO8(0x2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 #define DWDR _SFR_IO8(0x31) #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 #define MCUSR _SFR_IO8(0x34) #define USBRF 5 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 #define MCUCR _SFR_IO8(0x35) #define PUD 4 #define IVSEL 1 #define IVCE 0 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMIE 7 #define RWWSB 6 #define SIGRD 5 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCSR _SFR_MEM8(0x60) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 #define CLKPR _SFR_MEM8(0x61) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 #define WDTCKD _SFR_MEM8(0x62) #define WDEWIF 3 #define WDEWIE 2 #define WCLKD1 1 #define WCLKD0 0 #define REGCR _SFR_MEM8(0x63) #define REGDIS 0 #define PRR0 _SFR_MEM8(0x64) #define PRTIM0 5 #define PRTIM1 3 #define PRSPI 2 #define PRR1 _SFR_MEM8(0x65) #define PRUSB 7 #define PRUSART1 0 #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67] */ #define PCICR _SFR_MEM8(0x68) #define PCIE1 1 #define PCIE0 0 #define EICRA _SFR_MEM8(0x69) #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 #define EICRB _SFR_MEM8(0x6A) #define ISC71 7 #define ISC70 6 #define ISC61 5 #define ISC60 4 #define ISC51 3 #define ISC50 2 #define ISC41 1 #define ISC40 0 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT12 4 #define PCINT11 3 #define PCINT10 2 #define PCINT9 1 #define PCINT8 0 /* Reserved [0x6D] */ #define TIMSK0 _SFR_MEM8(0x6E) #define OCIE0B 2 #define OCIE0A 1 #define TOIE0 0 #define TIMSK1 _SFR_MEM8(0x6F) #define ICIE1 5 #define OCIE1C 3 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 /* Reserved [0x70..0x7F] */ #define TCCR1A _SFR_MEM8(0x80) #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define COM1C1 3 #define COM1C0 2 #define WGM11 1 #define WGM10 0 #define TCCR1B _SFR_MEM8(0x81) #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 #define TCCR1C _SFR_MEM8(0x82) #define FOC1A 7 #define FOC1B 6 #define FOC1C 5 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Combine OCR1CL and OCR1CH */ #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CH _SFR_MEM8(0x8D) /* Reserved [0x8E..0xC7] */ #define UCSR1A _SFR_MEM8(0xC8) #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 #define UCSR1B _SFR_MEM8(0XC9) #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 #define UCSR1C _SFR_MEM8(0xCA) #define UMSEL11 7 #define UMSEL10 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPOL1 0 #define UCSR1D _SFR_MEM8(0xCB) #define CTSEN 1 #define RTSEN 0 /* Combine UBRR1L and UBRR1H */ #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1H _SFR_MEM8(0xCD) #define UDR1 _SFR_MEM8(0XCE) /* Reserved [0xCF] */ #define CKSEL0 _SFR_MEM8(0XD0) /* old name; up to AVR Studio v 4.13 */ #define CLKSEL0 _SFR_MEM8(0XD0) /* since AVR Studio v 4.14 */ #define RCSUT1 7 #define RCSUT0 6 #define EXSUT1 5 #define EXSUT0 4 #define RCE 3 #define EXTE 2 #define CLKS 0 #define CKSEL1 _SFR_MEM8(0XD1) /* old name */ #define CLKSEL1 _SFR_MEM8(0XD1) #define RCCKSEL3 7 #define RCCKSEL2 6 #define RCCKSEL1 5 #define RCCKSEL0 4 #define EXCKSEL3 3 #define EXCKSEL2 2 #define EXCKSEL1 1 #define EXCKSEL0 0 #define CKSTA _SFR_MEM8(0XD2) /* old name */ #define CLKSTA _SFR_MEM8(0XD2) #define RCON 1 #define EXTON 0 /* Reserved [0xD3..0xD7] */ #define USBCON _SFR_MEM8(0XD8) #define USBE 7 #define FRZCLK 5 /* Reserved [0xD9..0xDA] */ /* Combine UDPADDL and UDPADDH */ #define UDPADD _SFR_MEM16(0xDB) #define UDPADDL _SFR_MEM8(0xDB) #define UDPADDH _SFR_MEM8(0xDC) #define DPACC 7 /* Reserved [0xDD..0xDF] */ #define UDCON _SFR_MEM8(0XE0) #define RSTCPU 2 #define RMWKUP 1 #define DETACH 0 #define UDINT _SFR_MEM8(0XE1) #define UPRSMI 6 #define EORSMI 5 #define WAKEUPI 4 #define EORSTI 3 #define SOFI 2 #define SUSPI 0 #define UDIEN _SFR_MEM8(0XE2) #define UPRSME 6 #define EORSME 5 #define WAKEUPE 4 #define EORSTE 3 #define SOFE 2 #define SUSPE 0 #define UDADDR _SFR_MEM8(0XE3) #define ADDEN 7 /* Combine UDFNUML and UDFNUMH */ #define UDFNUM _SFR_MEM16(0xE4) #define UDFNUML _SFR_MEM8(0xE4) #define UDFNUMH _SFR_MEM8(0xE5) #define UDMFN _SFR_MEM8(0XE6) #define FNCERR 4 /* Reserved [0xE7] */ #define UEINTX _SFR_MEM8(0XE8) #define FIFOCON 7 #define NAKINI 6 #define RWAL 5 #define NAKOUTI 4 #define RXSTPI 3 #define RXOUTI 2 #define STALLEDI 1 #define TXINI 0 #define UENUM _SFR_MEM8(0XE9) #define EPNUM2 2 #define EPNUM1 1 #define EPNUM0 0 #define UERST _SFR_MEM8(0XEA) #define EPRST4 4 #define EPRST3 3 #define EPRST2 2 #define EPRST1 1 #define EPRST0 0 #define UECONX _SFR_MEM8(0XEB) #define STALLRQ 5 #define STALLRQC 4 #define RSTDT 3 #define EPEN 0 #define UECFG0X _SFR_MEM8(0XEC) #define EPTYPE1 7 #define EPTYPE0 6 #define EPDIR 0 #define UECFG1X _SFR_MEM8(0XED) #define EPSIZE2 6 #define EPSIZE1 5 #define EPSIZE0 4 #define EPBK1 3 #define EPBK0 2 #define ALLOC 1 #define UESTA0X _SFR_MEM8(0XEE) #define CFGOK 7 #define OVERFI 6 #define UNDERFI 5 #define DTSEQ1 3 #define DTSEQ0 2 #define NBUSYBK1 1 #define NBUSYBK0 0 #define UESTA1X _SFR_MEM8(0XEF) #define CTRLDIR 2 #define CURRBK1 1 #define CURRBK0 0 #define UEIENX _SFR_MEM8(0XF0) #define FLERRE 7 #define NAKINE 6 #define NAKOUTE 4 #define RXSTPE 3 #define RXOUTE 2 #define STALLEDE 1 #define TXINE 0 #define UEDATX _SFR_MEM8(0XF1) #define UEBCLX _SFR_MEM8(0xF2) /* Reserved [0xF3] */ #define UEINT _SFR_MEM8(0XF4) #define EPINT4 4 #define EPINT3 3 #define EPINT2 2 #define EPINT1 1 #define EPINT0 0 /* Reserved [0xF5..0xF9] */ #define PS2CON _SFR_MEM8(0XFA) #define PS2EN 0 #define UPOE _SFR_MEM8(0XFB) #define UPWE1 7 #define UPWE0 6 #define UPDRV1 5 #define UPDRV0 4 #define SCKI 3 #define DATAI 2 #define DPI 1 #define DMI 0 /* Reserved [0xFC..0xFF] */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 3 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) /* External Interrupt Request 4 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) /* External Interrupt Request 5 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) /* External Interrupt Request 6 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) /* External Interrupt Request 7 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 9 #define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 10 #define PCINT1_vect _VECTOR(10) /* USB General Interrupt Request */ #define USB_GEN_vect_num 11 #define USB_GEN_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ #define USB_COM_vect_num 12 #define USB_COM_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ #define WDT_vect_num 13 #define WDT_vect _VECTOR(13) /* Timer/Counter2 Capture Event */ #define TIMER1_CAPT_vect_num 14 #define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Compare Match B */ #define TIMER1_COMPA_vect_num 15 #define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ #define TIMER1_COMPB_vect_num 16 #define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match C */ #define TIMER1_COMPC_vect_num 17 #define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 18 #define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPA_vect_num 19 #define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match B */ #define TIMER0_COMPB_vect_num 20 #define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 21 #define TIMER0_OVF_vect _VECTOR(21) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 22 #define SPI_STC_vect _VECTOR(22) /* USART1, Rx Complete */ #define USART1_RX_vect_num 23 #define USART1_RX_vect _VECTOR(23) /* USART1 Data register Empty */ #define USART1_UDRE_vect_num 24 #define USART1_UDRE_vect _VECTOR(24) /* USART1, Tx Complete */ #define USART1_TX_vect_num 25 #define USART1_TX_vect _VECTOR(25) /* Analog Comparator */ #define ANALOG_COMP_vect_num 26 #define ANALOG_COMP_vect _VECTOR(26) /* EEPROM Ready */ #define EE_READY_vect_num 27 #define EE_READY_vect _VECTOR(27) /* Store Program Memory Read */ #define SPM_READY_vect_num 28 #define SPM_READY_vect _VECTOR(28) #define _VECTORS_SIZE 116 #endif /* _AVR_IOUSBXX2_H_ */ avr-libc-1.8.0.orig/include/avr/io43u35x.h0000644000000000000000000002503411732702554014745 0ustar /* Copyright (c) 2003,2005 Keith Gudger All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io43u35x.h 1873 2009-02-11 17:53:39Z arcanum $ */ /* avr/io43u35x.h - definitions for AT43USB35x */ #ifndef _AVR_IO43U35X_H_ #define _AVR_IO43U35X_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io43u35x.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* ADC Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x02) #endif #define ADCW _SFR_IO16(0x02) #define ADCL _SFR_IO8(0x02) #define ADCH _SFR_IO8(0x03) /* ADC Control and status register */ #define ADCSR _SFR_IO8(0x07) /* ADC Multiplexer select */ #define ADMUX _SFR_IO8(0x08) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* Input Pins, Port F */ #define PINF _SFR_IO8(0x04) /* Data Direction Register, Port F */ #define DDRF _SFR_IO8(0x05) /* Data Register, Port F */ #define PORTF _SFR_IO8(0x06) /* Input Pins, Port E */ #define PINE _SFR_IO8(0x01) /* Data Direction Register, Port E */ #define DDRE _SFR_IO8(0x02) /* Data Register, Port E */ #define PORTE _SFR_IO8(0x03) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* 0x1C..0x1F reserved */ /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Control Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt Mask register */ #define GIMSK _SFR_IO8(0x3B) /* Interrupt vectors */ #define SIG_INTERRUPT0 _VECTOR(1) /* suspend/resume */ #define SIG_INTERRUPT1 _VECTOR(2) #define SIG_TIMER1_CAPT1 _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) #define SIG_OUTPUT_COMPARE1B _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(7) #define SIG_SPI _VECTOR(8) /* 9, 10: reserved */ #define SIG_ADC _VECTOR(11) #define SIG_USB_INT _VECTOR(12) #define _VECTORS_SIZE 52 /* The Register Bit names are represented by their bit number (0-7). */ /* Timer/Counter Interrupt MaSK register */ #define TICIE1 3 #define OCIE1A 6 #define OCIE1B 5 #define TOIE1 7 #define TOIE0 1 /* Timer/Counter Interrupt Flag Register */ #define ICF1 3 #define OCF1A 6 #define OCF1B 5 #define TOV1 7 #define TOV0 1 /* MCU general Control Register */ #define SE 5 #define SM 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Data Register, Port A */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Data Direction Register, Port A */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Input Pins, Port A */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Direction Register, Port C */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port C */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Data Register, Port F */ #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 /* Data Direction Register, Port F */ #define DDF3 3 #define DDF2 2 #define DDF1 1 /* Input Pins, Port F */ #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* ADC Multiplexer select */ #define MUX2 2 #define MUX1 1 #define MUX0 0 /* ADC Control and Status Register */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* Constants */ #define RAMEND 0x045F /*Last On-Chip SRAM Location*/ #define XRAMEND RAMEND #define E2END 0x0000 #define FLASHEND 0x5FFF #endif /* _AVR_43USB355_H_ */ avr-libc-1.8.0.orig/include/avr/io2333.h0000644000000000000000000002554711732702554014375 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io2333.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io2333.h - definitions for AT90S2333 */ #ifndef _AVR_IO2333_H_ #define _AVR_IO2333_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io2333.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* UART Baud Rate Register high */ #define UBRRH _SFR_IO8(0x03) /* ADC Data register */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and Status Register */ #define ADCSR _SFR_IO8(0x06) /* ADC MUX */ #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART Baud Rate Register */ #define UBRR _SFR_IO8(0x09) /* UART Control/Status Registers */ #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) /* UART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Timer/Counter1 Output Compare Register A */ #define OCR1 _SFR_IO16(0x2A) #define OCR1L _SFR_IO8(0x2A) #define OCR1H _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter Capture Event */ #define TIMER1_CAPT_vect_num 3 #define TIMER1_CAPT_vect _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) /* Timer/Counter1 Compare Match */ #define TIMER1_COMP_vect_num 4 #define TIMER1_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 5 #define TIMER1_OVF_vect _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(5) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 6 #define TIMER0_OVF_vect _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(6) /* Serial Transfer Complete */ #define SPI_STC_vect_num 7 #define SPI_STC_vect _VECTOR(7) #define SIG_SPI _VECTOR(7) /* UART, Rx Complete */ #define UART_RX_vect_num 8 #define UART_RX_vect _VECTOR(8) #define SIG_UART_RECV _VECTOR(8) /* UART Data Register Empty */ #define UART_UDRE_vect_num 9 #define UART_UDRE_vect _VECTOR(9) #define SIG_UART_DATA _VECTOR(9) /* UART, Tx Complete */ #define UART_TX_vect_num 10 #define UART_TX_vect _VECTOR(10) #define SIG_UART_TRANS _VECTOR(10) /* ADC Conversion Complete */ #define ADC_vect_num 11 #define ADC_vect _VECTOR(11) #define SIG_ADC _VECTOR(11) /* EEPROM Ready */ #define EE_RDY_vect_num 12 #define EE_RDY_vect _VECTOR(12) #define SIG_EEPROM_READY _VECTOR(12) /* Analog Comparator */ #define ANA_COMP_vect_num 13 #define ANA_COMP_vect _VECTOR(13) #define SIG_COMPARATOR _VECTOR(13) #define _VECTORS_SIZE 28 /* The Register Bit names are represented by their bit number (0-7). */ /* MCU general Status Register */ #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* General Interrupt MaSK register */ #define INT1 7 #define INT0 6 /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 /* Timer/Counter Interrupt MaSK register */ #define TOIE1 7 #define OCIE1 6 #define TICIE1 3 #define TOIE0 1 /* Timer/Counter Interrupt Flag register */ #define TOV1 7 #define OCF1 6 #define ICF1 3 #define TOV0 1 /* MCU general Control Register */ #define SE 5 #define SM 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 1 Control Register */ #define COM11 7 #define COM10 6 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define MPCM 0 /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define AINBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADC MUX */ #define ACDBG 6 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* ADC Control and Status Register */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* Data Register, Port B */ #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port C */ #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Direction Register, Port C */ #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0xDF /*Last On-Chip SRAM location*/ #define XRAMEND RAMEND #define E2END 0x7F #define FLASHEND 0x7FF #endif /* _AVR_IO2333_H_ */ avr-libc-1.8.0.orig/include/avr/iom103.h0000644000000000000000000004416711732702554014462 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom103.h 2227 2011-03-04 19:35:10Z arcanum $ */ /* avr/iom103.h - definitions for ATmega103 */ #ifndef _AVR_IOM103_H_ #define _AVR_IOM103_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom103.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Input Pins, Port F */ #define PINF _SFR_IO8(0x00) /* Input Pins, Port E */ #define PINE _SFR_IO8(0x01) /* Data Direction Register, Port E */ #define DDRE _SFR_IO8(0x02) /* Data Register, Port E */ #define PORTE _SFR_IO8(0x03) /* ADC Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and status register */ #define ADCSR _SFR_IO8(0x06) /* ADC Multiplexer select */ #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART Baud Rate Register */ #define UBRR _SFR_IO8(0x09) /* UART Control Register */ #define UCR _SFR_IO8(0x0A) /* UART Status Register */ #define USR _SFR_IO8(0x0B) /* UART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* Timer2 Output Compare Register */ #define OCR2 _SFR_IO8(0x23) /* Timer/Counter 2 */ #define TCNT2 _SFR_IO8(0x24) /* Timer/Counter 2 Control register */ #define TCCR2 _SFR_IO8(0x25) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 Asynchronous Control & Status Register */ #define ASSR _SFR_IO8(0x30) /* Output Compare Register 0 */ #define OCR0 _SFR_IO8(0x31) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x36) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x37) /* Èxternal Interrupt Flag Register */ #define EIFR _SFR_IO8(0x38) /* External Interrupt MaSK register */ #define EIMSK _SFR_IO8(0x39) /* External Interrupt Control Register */ #define EICR _SFR_IO8(0x3A) /* RAM Page Z select register */ #define RAMPZ _SFR_IO8(0x3B) /* XDIV Divide control register */ #define XDIV _SFR_IO8(0x3C) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* External Interrupt 3 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) #define SIG_INTERRUPT3 _VECTOR(4) /* External Interrupt 4 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) #define SIG_INTERRUPT4 _VECTOR(5) /* External Interrupt 5 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) #define SIG_INTERRUPT5 _VECTOR(6) /* External Interrupt 6 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) #define SIG_INTERRUPT6 _VECTOR(7) /* External Interrupt 7 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) #define SIG_INTERRUPT7 _VECTOR(8) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 9 #define TIMER2_COMP_vect _VECTOR(9) #define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 10 #define TIMER2_OVF_vect _VECTOR(10) #define SIG_OVERFLOW2 _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) #define SIG_INPUT_CAPTURE1 _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 14 #define TIMER1_OVF_vect _VECTOR(14) #define SIG_OVERFLOW1 _VECTOR(14) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 15 #define TIMER0_COMP_vect _VECTOR(15) #define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 16 #define TIMER0_OVF_vect _VECTOR(16) #define SIG_OVERFLOW0 _VECTOR(16) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 17 #define SPI_STC_vect _VECTOR(17) #define SIG_SPI _VECTOR(17) /* UART, Rx Complete */ #define UART_RX_vect_num 18 #define UART_RX_vect _VECTOR(18) #define SIG_UART_RECV _VECTOR(18) /* UART Data Register Empty */ #define UART_UDRE_vect_num 19 #define UART_UDRE_vect _VECTOR(19) #define SIG_UART_DATA _VECTOR(19) /* UART, Tx Complete */ #define UART_TX_vect_num 20 #define UART_TX_vect _VECTOR(20) #define SIG_UART_TRANS _VECTOR(20) /* ADC Conversion Complete */ #define ADC_vect_num 21 #define ADC_vect _VECTOR(21) #define SIG_ADC _VECTOR(21) /* EEPROM Ready */ #define EE_READY_vect_num 22 #define EE_READY_vect _VECTOR(22) #define SIG_EEPROM_READY _VECTOR(22) /* Analog Comparator */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) #define SIG_COMPARATOR _VECTOR(23) #define _VECTORS_SIZE 96 /* The Register Bit names are represented by their bit number (0-7). */ /* XDIV Divide control register*/ #define XDIVEN 7 #define XDIV6 6 #define XDIV5 5 #define XDIV4 4 #define XDIV3 3 #define XDIV2 2 #define XDIV1 1 #define XDIV0 0 /* RAM Page Z select register */ #define RAMPZ0 0 /* External Interrupt Control Register */ #define ISC71 7 #define ISC70 6 #define ISC61 5 #define ISC60 4 #define ISC51 3 #define ISC50 2 #define ISC41 1 #define ISC40 0 /* External Interrupt MaSK register */ #define INT7 7 #define INT6 6 #define INT5 5 #define INT4 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 /* Èxternal Interrupt Flag Register */ #define INTF7 7 #define INTF6 6 #define INTF5 5 #define INTF4 4 /* Timer/Counter Interrupt MaSK register */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 /* Timer/Counter Interrupt Flag Register */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 /* MCU general Control Register */ #define SRE 7 #define SRW 6 #define SE 5 #define SM1 4 #define SM0 3 /* MCU Status Register */ #define EXTRF 1 #define PORF 0 /* Timer/Counter 0 Control Register */ #define PWM0 6 #define COM01 5 #define COM00 4 #define CTC0 3 #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 0 Asynchronous Control & Status Register */ #define AS0 3 #define TCN0UB 2 #define OCR0UB 1 #define TCR0UB 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Timer/Counter 2 Control register */ #define PWM2 6 #define COM21 5 #define COM20 4 #define CTC2 3 #define CS22 2 #define CS21 1 #define CS20 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Data Register, Port A */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Data Direction Register, Port A */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Input Pins, Port A */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port C */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Data Register, Port E */ #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 /* Data Direction Register, Port E */ #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 /* Input Pins, Port E */ #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 /* Input Pins, Port F */ #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADC Control and status register */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADC Multiplexer select */ #define MUX2 2 #define MUX1 1 #define MUX0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0x0FFF /*Last On-Chip SRAM Location*/ #define XRAMEND 0xFFFF #define E2END 0x0FFF #define E2PAGESIZE 0 #define FLASHEND 0x1FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ #define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ #define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x01 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_INTERRUPT3 #pragma GCC poison SIG_INTERRUPT4 #pragma GCC poison SIG_INTERRUPT5 #pragma GCC poison SIG_INTERRUPT6 #pragma GCC poison SIG_INTERRUPT7 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM103_H_ */ avr-libc-1.8.0.orig/include/avr/power.h0000644000000000000000000017717011732702554014607 0ustar /* Copyright (c) 2006, 2007, 2008 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: power.h 2254 2011-09-26 15:06:50Z arcanum $ */ #ifndef _AVR_POWER_H_ #define _AVR_POWER_H_ 1 #include #include /** \file */ /** \defgroup avr_power : Power Reduction Management \code #include \endcode Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that allow you to reduce power consumption by disabling or enabling various on-board peripherals as needed. There are many macros in this header file that provide an easy interface to enable or disable on-board peripherals to reduce power. See the table below. \note Not all AVR devices have a Power Reduction Register (for example the ATmega128). On those devices without a Power Reduction Register, these macros are not available. \note Not all AVR devices contain the same peripherals (for example, the LCD interface), or they will be named differently (for example, USART and USART0). Please consult your device's datasheet, or the header file, to find out which macros are applicable to your device. */ /** \addtogroup avr_power \anchor avr_powermacros
Power Macro Description Applicable for device
power_adc_enable() Enable the Analog to Digital Converter module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
power_adc_disable() Disable the Analog to Digital Converter module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
power_lcd_enable() Enable the LCD module. ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490
power_lcd_disable(). Disable the LCD module. ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490
power_pscr_enable() Enable the Reduced Power Stage Controller module. AT90PWM81
power_pscr_disable() Disable the Reduced Power Stage Controller module. AT90PWM81
power_psc0_enable() Enable the Power Stage Controller 0 module. AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B
power_psc0_disable() Disable the Power Stage Controller 0 module. AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B
power_psc1_enable() Enable the Power Stage Controller 1 module. AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B
power_psc1_disable() Disable the Power Stage Controller 1 module. AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B
power_psc2_enable() Enable the Power Stage Controller 2 module. AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM81
power_psc2_disable() Disable the Power Stage Controller 2 module. AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM81
power_spi_enable() Enable the Serial Peripheral Interface module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168
power_spi_disable() Disable the Serial Peripheral Interface module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168
power_timer0_enable() Enable the Timer 0 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM216, AT90PWM316, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
power_timer0_disable() Disable the Timer 0 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
power_timer1_enable() Enable the Timer 1 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
power_timer1_disable() Disable the Timer 1 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
power_timer2_enable() Enable the Timer 2 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168
power_timer2_disable() Disable the Timer 2 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168
power_timer3_enable() Enable the Timer 3 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287
power_timer3_disable() Disable the Timer 3 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287
power_timer4_enable() Enable the Timer 4 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561
power_timer4_disable() Disable the Timer 4 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561
power_timer5_enable() Enable the Timer 5 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561
power_timer5_disable() Disable the Timer 5 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561
power_twi_enable() Enable the Two Wire Interface module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168
power_twi_disable() Disable the Two Wire Interface module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168
power_usart_enable() Enable the USART module. AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B
power_usart_disable() Disable the USART module. AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B
power_usart0_enable() Enable the USART 0 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168
power_usart0_disable() Disable the USART 0 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega3250A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168
power_usart1_enable() Enable the USART 1 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644
power_usart1_disable() Disable the USART 1 module. ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644
power_usart2_enable() Enable the USART 2 module. ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
power_usart2_disable() Disable the USART 2 module. ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
power_usart3_enable() Enable the USART 3 module. ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
power_usart3_disable() Disable the USART 3 module. ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
power_usb_enable() Enable the USB module. AT90USB646, AT90USB647, AT90USB1286, AT90USB1287
power_usb_disable() Disable the USB module. AT90USB646, AT90USB647, AT90USB1286, AT90USB1287
power_usi_enable() Enable the Universal Serial Interface module. ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
power_usi_disable() Disable the Universal Serial Interface module. ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
power_vadc_enable() Enable the Voltage ADC module. ATmega406
power_vadc_disable() Disable the Voltage ADC module. ATmega406
power_all_enable() Enable all modules. ATxmega6A4, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmegaA1, ATxmegaA1U, ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmegaA3B, ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3, ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega325A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
power_all_disable() Disable all modules. ATxmega6A4, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmegaA1, ATxmegaA1U, ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmegaA3B, ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3,ATxmega192D3, ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega325A, ATmega3250, ATmega325A, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega329A, ATmega3290, ATmega3290A, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861
@} */ // Xmega A series has AES, EBI and DMA bits // Include any other device on need basis #if defined(__AVR_ATxmega16A4__) \ || defined(__AVR_ATxmega32A4__) \ || defined(__AVR_ATxmega64A1__) \ || defined(__AVR_ATxmega64A1U__) \ || defined(__AVR_ATxmega64A3__) \ || defined(__AVR_ATxmega128A1__) \ || defined(__AVR_ATxmega128A1U__) \ || defined(__AVR_ATxmega128A3__) \ || defined(__AVR_ATxmega192A3__) \ || defined(__AVR_ATxmega256A3__) \ || defined(__AVR_ATxmega256A3B__) #define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm)) #define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm) #define power_ebi_enable() (PR_PRGEN &= (uint8_t)~(PR_EBI_bm)) #define power_ebi_disable() (PR_PRGEN |= (uint8_t)PR_EBI_bm) #define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm)) #define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm) #define power_daca_enable() (PR_PRPA &= (uint8_t)~(PR_DAC_bm)) #define power_daca_disable() (PR_PRPA |= (uint8_t)PR_DAC_bm) #define power_dacb_enable() (PR_PRPB &= (uint8_t)~(PR_DAC_bm)) #define power_dacb_disable() (PR_PRPB |= (uint8_t)PR_DAC_bm) #define power_usartc1_enable() (PR_PRPC &= (uint8_t)~(PR_USART1_bm)) #define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm) #define power_usartd1_enable() (PR_PRPD &= (uint8_t)~(PR_USART1_bm)) #define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm) #define power_usarte1_enable() (PR_PRPE &= (uint8_t)~(PR_USART1_bm)) #define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm) #define power_usartf1_enable() (PR_PRPF &= (uint8_t)~(PR_USART1_bm)) #define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm) #define power_all_enable() \ do { \ PR_PRGEN &= (uint8_t)~(PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \ PR_PRPA &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \ PR_PRPB &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \ PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPD &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPF &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ } while(0) #define power_all_disable() \ do { \ PR_PRGEN|= (uint8_t)(PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \ PR_PRPA |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \ PR_PRPB |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \ PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPD |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPF |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ } while(0) #endif #if defined(__AVR_ATxmega16A4__) \ || defined(__AVR_ATxmega16D4__) \ || defined(__AVR_ATxmega32A4__) \ || defined(__AVR_ATxmega32D4__) \ || defined(__AVR_ATxmega64A1__) \ || defined(__AVR_ATxmega64A1U__) \ || defined(__AVR_ATxmega64A3__) \ || defined(__AVR_ATxmega64D3__) \ || defined(__AVR_ATxmega128A1__) \ || defined(__AVR_ATxmega128A1U__) \ || defined(__AVR_ATxmega128A3__) \ || defined(__AVR_ATxmega128D3__) \ || defined(__AVR_ATxmega192A3__) \ || defined(__AVR_ATxmega192D3__) \ || defined(__AVR_ATxmega256A3__) \ || defined(__AVR_ATxmega256A3B__) #define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm)) #define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm) #define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm)) #define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm) #define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm)) #define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm) #define power_adcb_enable() (PR_PRPB &= (uint8_t)~(PR_ADC_bm)) #define power_adcb_disable() (PR_PRPB |= (uint8_t)PR_ADC_bm) #define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm)) #define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm) #define power_acb_enable() (PR_PRPB &= (uint8_t)~(PR_AC_bm)) #define power_acb_disable() (PR_PRPB |= (uint8_t)PR_AC_bm) #define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm)) #define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm) #define power_twid_enable() (PR_PRPD &= (uint8_t)~(PR_TWI_bm)) #define power_twid_disable() (PR_PRPD |= (uint8_t)PR_TWI_bm) #define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm)) #define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm) #define power_twif_enable() (PR_PRPF &= (uint8_t)~(PR_TWI_bm)) #define power_twif_disable() (PR_PRPF |= (uint8_t)PR_TWI_bm) #define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm)) #define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm) #define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm)) #define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm) #define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm)) #define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm) #define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm)) #define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm) #define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm)) #define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm) #define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm)) #define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm) #define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm)) #define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm) #define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm)) #define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm) #define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm)) #define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm) #define power_hiresd_enable() (PR_PRPD &= (uint8_t)~(PR_HIRES_bm)) #define power_hiresd_disable() (PR_PRPD |= (uint8_t)PR_HIRES_bm) #define power_hirese_enable() (PR_PRPE &= (uint8_t)~(PR_HIRES_bm)) #define power_hirese_disable() (PR_PRPE |= (uint8_t)PR_HIRES_bm) #define power_hiresf_enable() (PR_PRPF &= (uint8_t)~(PR_HIRES_bm)) #define power_hiresf_disable() (PR_PRPF |= (uint8_t)PR_HIRES_bm) #define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm)) #define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm) #define power_tc1d_enable() (PR_PRPD &= (uint8_t)~(PR_TC1_bm)) #define power_tc1d_disable() (PR_PRPD |= (uint8_t)PR_TC1_bm) #define power_tc1e_enable() (PR_PRPE &= (uint8_t)~(PR_TC1_bm)) #define power_tc1e_disable() (PR_PRPE |= (uint8_t)PR_TC1_bm) #define power_tc1f_enable() (PR_PRPF &= (uint8_t)~(PR_TC1_bm)) #define power_tc1f_disable() (PR_PRPF |= (uint8_t)PR_TC1_bm) #define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm)) #define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm) #define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm)) #define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm) #define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm)) #define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm) #define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm)) #define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm) #endif #if defined(__AVR_ATxmega16D4__) \ || defined(__AVR_ATxmega32D4__) \ || defined(__AVR_ATxmega64D3__) \ || defined(__AVR_ATxmega128D3__) \ || defined(__AVR_ATxmega192D3__) #define power_all_enable() \ do { \ PR_PRGEN &= (uint8_t)~(PR_RTC_bm|PR_EVSYS_bm); \ PR_PRPA &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \ PR_PRPB &= (uint8_t)~(PR_ADC_bm|PR_AC_bm); \ PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPD &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPF &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ } while(0) #define power_all_disable() \ do { \ PR_PRGEN|= (uint8_t)(PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \ PR_PRPA |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \ PR_PRPB |= (uint8_t)(PR_ADC_bm|PR_AC_bm); \ PR_PRPC |= (uint8_t)(PR_TWI_bm|R_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPD |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ PR_PRPF |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \ } while(0) #elif defined(__AVR_ATmega640__) \ || defined(__AVR_ATmega1280__) \ || defined(__AVR_ATmega1281__) \ || defined(__AVR_ATmega2560__) \ || defined(__AVR_ATmega2561__) #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC)) #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC)) #define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI)) #define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI)) #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI)) #define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI)) #define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0)) #define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0)) #define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1)) #define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1)) #define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2)) #define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2)) #define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3)) #define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3)) #define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRTIM4)) #define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRTIM4)) #define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRTIM5)) #define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRTIM5)) #define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0)) #define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0)) #define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1)) #define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1)) #define power_usart2_enable() (PRR1 &= (uint8_t)~(1 << PRUSART2)) #define power_usart2_disable() (PRR1 |= (uint8_t)(1 << PRUSART2)) #define power_usart3_enable() (PRR1 &= (uint8_t)~(1 << PRUSART3)) #define power_usart3_disable() (PRR1 |= (uint8_t)(1 << PRUSART3)) #define power_all_enable() \ do{ \ PRR0 &= (uint8_t)~((1<, never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn28.h" #else # error "Attempt to include more than one file." #endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" #endif /* I/O registers */ #define OSCCAL _SFR_IO8(0x00) #define WDTCR _SFR_IO8(0x01) #define MODCR _SFR_IO8(0x02) #define TCNT0 _SFR_IO8(0x03) #define TCCR0 _SFR_IO8(0x04) #define IFR _SFR_IO8(0x05) #define ICR _SFR_IO8(0x06) #define MCUCS _SFR_IO8(0x07) #define ACSR _SFR_IO8(0x08) /* 0x09..0x0F reserved */ #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) /* 0x13..0x15 reserved */ #define PINB _SFR_IO8(0x16) /* 0x17..0x18 reserved */ #define PINA _SFR_IO8(0x19) #define PACR _SFR_IO8(0x1A) #define PORTA _SFR_IO8(0x1B) /* 0x1C..0x3E reserved */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Low-level Input on Port B */ #define LOWLEVEL_IO_PINS_vect_num 3 #define LOWLEVEL_IO_PINS_vect _VECTOR(3) #define SIG_PIN _VECTOR(3) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 4 #define TIMER0_OVF_vect _VECTOR(4) #define SIG_OVERFLOW0 _VECTOR(4) /* Analog Comparator */ #define ANA_COMP_vect_num 5 #define ANA_COMP_vect _VECTOR(5) #define SIG_COMPARATOR _VECTOR(5) #define _VECTORS_SIZE 12 /* Bit numbers */ /* ICR */ #define INT1 7 #define INT0 6 #define LLIE 5 #define TOIE0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 /* IFR */ #define INTF1 7 #define INTF0 6 #define TOV0 4 /* MCUCS */ #define PLUPB 7 #define SE 5 #define SM 4 #define WDRF 3 #define EXTRF 1 #define PORF 0 /* TCCR0 */ #define FOV0 7 #define OOM01 4 #define OOM00 3 #define CS02 2 #define CS01 1 #define CS00 0 /* MODCR */ #define ONTIM4 7 #define ONTIM3 6 #define ONTIM2 5 #define ONTIM1 4 #define ONTIM0 3 #define MCONF2 2 #define MCONF1 1 #define MCONF0 0 /* WDTCR */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PA2 = IR */ /* PORTA */ #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* PACR */ #define DDA3 3 #define PA2HC 2 #define DDA1 1 #define DDA0 0 /* PINA */ #define PINA3 3 #define PINA1 1 #define PINA0 0 /* PB4 = INT1 PB3 = INT0 PB2 = T0 PB1 = AIN1 PB0 = AIN0 */ /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* ACSR */ #define ACD 7 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIS1 1 #define ACIS0 0 /* Last memory addresses */ #define RAMEND 0x1F #define XRAMEND 0x0 #define E2END 0x0 #define E2PAGESIZE 0 #define FLASHEND 0x7FF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_INTCAP (unsigned char)~_BV(4) #define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x07 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_PIN #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_COMPARATOR #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOTN28_H_ */ avr-libc-1.8.0.orig/include/avr/iotn87.h0000644000000000000000000004166211732702554014577 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn87.h 2181 2010-08-23 03:46:23Z arcanum $ */ /* avr/iotn87.h - definitions for ATtiny87 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn87.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny87_H_ #define _AVR_ATtiny87_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PORTCR _SFR_IO8(0x12) #define PUDA 0 #define PUDB 2 #define BBMA 4 #define BBMB 5 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define GTCCR _SFR_IO8(0x23) #define PSR1 0 #define PSR0 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x25) #define WGM00 0 #define WGM01 1 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x26) #define CS00 0 #define CS01 1 #define CS02 2 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x27) #define TCNT00 0 #define TCNT01 1 #define TCNT02 2 #define TCNT03 3 #define TCNT04 4 #define TCNT05 5 #define TCNT06 6 #define TCNT07 7 #define OCR0A _SFR_IO8(0x28) #define OCR00 0 #define OCR01 1 #define OCR02 2 #define OCR03 3 #define OCR04 4 #define OCR05 5 #define OCR06 6 #define OCR07 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACIRS 6 #define ACD 7 #define DWDR _SFR_IO8(0x31) #define DWDR0 0 #define DWDR1 1 #define DWDR2 2 #define DWDR3 3 #define DWDR4 4 #define DWDR5 5 #define DWDR6 6 #define DWDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define PUD 4 #define BODSE 5 #define BODS 6 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define SIGRD 5 #define RWWSB 6 #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define CLKCSR _SFR_MEM8(0x62) #define CLKC0 0 #define CLKC1 1 #define CLKC2 2 #define CLKC3 3 #define CLKRDY 4 #define CLKCCE 7 #define CLKSELR _SFR_MEM8(0x63) #define CSEL0 0 #define CSEL1 1 #define CSEL2 2 #define CSEL3 3 #define CSUT0 4 #define CSUT1 5 #define COUT 6 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define PRSPI 4 #define PRLIN 5 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define AMISCR _SFR_MEM8(0x77) #define ISRCEN 0 #define XREFEN 1 #define AREFEN 2 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACIR0 4 #define ACIR1 5 #define ACME 6 #define BIN 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCCR1D _SFR_MEM8(0x83) #define OC1AU 0 #define OC1AV 1 #define OC1AW 2 #define OC1AX 3 #define OC1BU 4 #define OC1BV 5 #define OC1BW 6 #define OC1BX 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR0BUB 0 #define TCR0AUB 1 #define OCR0AUB 3 #define TCN0UB 4 #define AS0 5 #define EXCLK 6 #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define USIBR _SFR_MEM8(0xBB) #define USIBR0 0 #define USIBR1 1 #define USIBR2 2 #define USIBR3 3 #define USIBR4 4 #define USIBR5 5 #define USIBR6 6 #define USIBR7 7 #define USIPP _SFR_MEM8(0xBC) #define USIPOS 0 #define LINCR _SFR_MEM8(0xC8) #define LCMD0 0 #define LCMD1 1 #define LCMD2 2 #define LENA 3 #define LCONF0 4 #define LCONF1 5 #define LIN13 6 #define LSWRES 7 #define LINSIR _SFR_MEM8(0xC9) #define LRXOK 0 #define LTXOK 1 #define LIDOK 2 #define LERR 3 #define LBUSY 4 #define LIDST0 5 #define LIDST1 6 #define LIDST2 7 #define LINENIR _SFR_MEM8(0xCA) #define LENRXOK 0 #define LENTXOK 1 #define LENIDOK 2 #define LENERR 3 #define LINERR _SFR_MEM8(0xCB) #define LBERR 0 #define LCERR 1 #define LPERR 2 #define LSERR 3 #define LFERR 4 #define LOVERR 5 #define LTOERR 6 #define LABORT 7 #define LINBTR _SFR_MEM8(0xCC) #define LBT0 0 #define LBT1 1 #define LBT2 2 #define LBT3 3 #define LBT4 4 #define LBT5 5 #define LDISR 7 #define LINBRR _SFR_MEM16(0xCD) #define LINBRRL _SFR_MEM8(0xCD) #define LDIV0 0 #define LDIV1 1 #define LDIV2 2 #define LDIV3 3 #define LDIV4 4 #define LDIV5 5 #define LDIV6 6 #define LDIV7 7 #define LINBRRH _SFR_MEM8(0xCE) #define LDIV8 0 #define LDIV9 1 #define LDIV10 2 #define LDIV11 3 #define LINDLR _SFR_MEM8(0xCF) #define LRXDL0 0 #define LRXDL1 1 #define LRXDL2 2 #define LRXDL3 3 #define LTXDL0 4 #define LTXDL1 5 #define LTXDL2 6 #define LTXDL3 7 #define LINIDR _SFR_MEM8(0xD0) #define LID0 0 #define LID1 1 #define LID2 2 #define LID3 3 #define LID4 4 #define LID5 5 #define LP0 6 #define LP1 7 #define LINSEL _SFR_MEM8(0xD1) #define LINDX0 0 #define LINDX1 1 #define LINDX2 2 #define LAINC 3 #define LINDAT _SFR_MEM8(0xD2) #define LDATA0 0 #define LDATA1 1 #define LDATA2 2 #define LDATA3 3 #define LDATA4 4 #define LDATA5 5 #define LDATA6 6 #define LDATA7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define USI_OVF_vect_num 19 #define USI_OVF_vect _VECTOR(19) /* USI Overflow */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ #define WDT_vect_num 5 #define WDT_vect _VECTOR(5) /* Watchdog Time-Out Interrupt */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match 1A */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter1 Compare Match 1B */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 10 #define TIMER0_COMPA_vect _VECTOR(10) /* Timer/Counter0 Compare Match 0A */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ #define LIN_TC_vect_num 12 #define LIN_TC_vect _VECTOR(12) /* LIN Transfer Complete */ #define LIN_ERR_vect_num 13 #define LIN_ERR_vect _VECTOR(13) /* LIN Error */ #define SPI_STC_vect_num 14 #define SPI_STC_vect _VECTOR(14) /* SPI Serial Transfer Complete */ #define ADC_vect_num 15 #define ADC_vect _VECTOR(15) /* ADC Conversion Complete */ #define EE_RDY_vect_num 16 #define EE_RDY_vect _VECTOR(16) /* EEPROM Ready */ #define ANA_COMP_vect_num 17 #define ANA_COMP_vect _VECTOR(17) /* Analog Comparator */ #define USI_START_vect_num 18 #define USI_START_vect _VECTOR(18) /* USI Start */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (20 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x0100) #define RAMSIZE (512) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x1FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always ON */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x87 #endif /* _AVR_ATtiny87_H_ */ avr-libc-1.8.0.orig/include/avr/iom644p.h0000644000000000000000000000652311732702554014646 0ustar /* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/iom644p.h - definitions for ATmega644P */ /* $Id: iom644p.h 2115 2010-04-05 23:19:53Z arcanum $ */ #ifndef _AVR_IOM644P_H_ #define _AVR_IOM644P_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMSTART (0x100) #define RAMEND 0x10FF #define XRAMEND RAMEND #define E2END 0x7FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x0A #endif /* _AVR_IOM644P_H_ */ avr-libc-1.8.0.orig/include/avr/iotn25.h0000644000000000000000000000613111732702554014557 0ustar /* Copyright (c) 2005, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn25.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iotn25.h - definitions for ATtiny25 */ #ifndef _AVR_IOTN25_H_ #define _AVR_IOTN25_H_ 1 #include #define SPM_PAGESIZE 32 #define RAMSTART (0x60) #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 4 #define FLASHEND 0x7FF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x08 #endif /* _AVR_IOTN25_H_ */ avr-libc-1.8.0.orig/include/avr/io86r401.h0000644000000000000000000001670311732702554014641 0ustar /* Copyright (c) 2002, Colin O'Flynn All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/io86r401.h - definitions for AT86RF401 */ #ifndef _AVR_IO86RF401_H_ #define _AVR_IO86RF401_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io86r401.h" #else # error "Attempt to include more than one file." #endif #include /* Status REGister */ #define SREG _SFR_IO8(0x3F) /* Stack Pointer */ #define SP _SFR_IO16(0x3D) #define SPH _SFR_IO8(0x3E) #define SPL _SFR_IO8(0x3D) /*Battery low configeration register */ #define BL_CONFIG _SFR_IO8(0x35) /*Button detect register*/ #define B_DET _SFR_IO8(0x34) /*AVR Configeration register*/ #define AVR_CONFIG _SFR_IO8(0x33) /* I/O registers */ /*Data in register */ #define IO_DATIN _SFR_IO8(0x32) /*Data out register */ #define IO_DATOUT _SFR_IO8(0x31) /*IO Enable register */ #define IO_ENAB _SFR_IO8(0x30) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x22) /* Bit Timer Control Register */ #define BTCR _SFR_IO8(0x21) #define BTCNT _SFR_IO8(0x20) /* NOTE: EEPROM name's changed to have D in front on them, per datasheet, but you may want to remove the leading D. */ /* EEPROM Control Register */ /* EEPROM Address Register */ #define DEEAR _SFR_IO8(0x1E) #define DEEARL _SFR_IO8(0x1E) /* EEPROM Data Register */ #define DEEDR _SFR_IO8(0x1D) /* EEPROM Control Register */ #define DEECR _SFR_IO8(0x1C) /* Lock Detector Configuration Register 2 */ #define LOCKDET2 _SFR_IO8(0x17) /* VCO Tuning Register*/ #define VCOTUNE _SFR_IO8(0x16) /* Power Attenuation Control Register */ #define PWR_ATTEN _SFR_IO8(0x14) /* Transmitter Control Register */ #define TX_CNTL _SFR_IO8(0x12) /* Lock Detector Configuration Register 1 */ #define LOCKDET1 _SFR_IO8(0x10) /* Interrupt vectors */ /* Transmission Done, Bit Timer Flag 2 Interrupt */ #define TXDONE_vect_num 1 #define TXDONE_vect _VECTOR(1) #define SIG_TXDONE _VECTOR(1) /* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */ #define TXEMPTY_vect_num 2 #define TXEMPTY_vect _VECTOR(2) #define SIG_TXBE _VECTOR(2) #define _VECTORS_SIZE 12 /* * The Register Bit names are represented by their bit number (0-7). */ /* Lock Detector Configuration Register 1 - LOCKDET1 */ #define UPOK 4 #define ENKO 3 #define BOD 2 #define CS1 1 #define CS0 0 /* Transmit Control Register - TX_CNTL */ #define TXE 5 #define TXK 4 #define LOC 2 /* Power Attenuation Control Register - PWR_ATTEN */ #define PCC2 5 #define PCC1 4 #define PCC0 3 #define PCF2 2 #define PCF1 1 #define PCF0 0 /* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/ #define VCOVDET1 7 #define VCOVDET0 6 #define VCOTUNE4 4 #define VCOTUNE3 3 #define VCOTUNE2 2 #define VCOTUNE1 1 #define VCOTUNE0 0 /* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/ #define EUD 7 #define LAT 6 #define ULC2 5 #define ULC1 4 #define ULC0 3 #define LC2 2 #define LC1 1 #define LC0 0 /* Data EEPROM Control Register - DEECR */ #define BSY 3 #define EEU 2 #define EEL 1 #define EER 0 /* Data EEPROM Data Register - DEEDR */ #define ED7 7 #define ED6 6 #define ED5 5 #define ED4 4 #define ED3 3 #define ED2 2 #define ED1 1 #define ED0 0 /* Data EEPROM Address Register - DEEAR */ #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define BA2 2 /* B is not a typo! */ #define BA1 1 #define BA0 0 /* Bit Timer Count Register - BTCNT */ #define C7 7 #define C6 6 #define C5 5 #define C4 4 #define C3 3 #define C2 2 #define C1 1 #define C0 0 /* Bit Timer Control Register - BTCR */ #define C9 7 #define C8 6 #define M1 5 #define M0 4 #define IE 3 #define F2 2 #define DATA 1 #define F0 0 /* Watchdog Timer Control Register - WDTCR */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* I/O Enable Register - IO_ENAB */ #define BOHYST 6 #define IOE5 5 #define IOE4 4 #define IOE3 3 #define IOE2 2 #define IOE1 1 #define IOE0 0 /* Note: No PORTB or whatever, this is the equivalent. */ /* I/O Data Out Register - IO_DATOUT */ #define IOO5 5 #define IOO4 4 #define IOO3 3 #define IOO2 2 #define IOO1 1 #define IOO0 0 /* Note: No PINB or whatever, this is the equivalent. */ /* I/O Data In Register - IO_DATIN */ #define IOI5 5 #define IOI4 4 #define IOI3 3 #define IOI2 2 #define IOI1 1 #define IOI0 0 /* AVR Configuration Register - AVR_CONFIG */ #define ACS1 6 #define ACS0 5 #define TM 4 #define BD 3 #define BLI 2 #define SLEEP 1 #define BBM 0 /* Button Detect Register - B_DET */ #define BD5 5 #define BD4 4 #define BD3 3 #define BD2 2 #define BD1 1 #define BD0 0 /* Battery Low Configuration Register - BL_CONFIG */ #define BL 7 #define BLV 6 #define BL5 5 #define BL4 4 #define BL3 3 #define BL2 2 #define BL1 1 #define BL0 0 /* Pointer definition */ #define XL r26 #define XH r27 #define YL r28 #define YH r29 #define ZL r30 #define ZH r31 /* Constants */ #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 0 #define FLASHEND 0x07FF /* Fuses */ #define FUSE_MEMORY_SIZE 0 /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x81 #endif /* _AVR_IO86RF401_H_ */ avr-libc-1.8.0.orig/include/avr/iom8515.h0000644000000000000000000004275711732702554014564 0ustar /* Copyright (c) 2002, Steinar Haugen All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom8515.h 2235 2011-03-17 04:13:14Z arcanum $ */ /* avr/iom8515.h - definitions for ATmega8515 */ #ifndef _AVR_IOM8515_H_ #define _AVR_IOM8515_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom8515.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Oscillator Calibration Register */ #define OSCCAL _SFR_IO8(0x04) /* Input Pins, Port E */ #define PINE _SFR_IO8(0x05) /* Data Direction Register, Port E */ #define DDRE _SFR_IO8(0x06) /* Data Register, Port E */ #define PORTE _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* USART Baud Rate Register */ #define UBRRL _SFR_IO8(0x09) /* USART Control and Status Register B */ #define UCSRB _SFR_IO8(0x0A) /* USART Control and Status Register A */ #define UCSRA _SFR_IO8(0x0B) /* USART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* USART Baud Rate Register HI */ /* USART Control and Status Register C */ #define UBRRH _SFR_IO8(0x20) #define UCSRC UBRRH /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Special Function IO Register */ #define SFIOR _SFR_IO8(0x30) /* Timer/Counter 0 Output Compare Register */ #define OCR0 _SFR_IO8(0x31) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU Control and Status Register */ #define MCUCSR _SFR_IO8(0x34) /* MCU Control Register */ #define MCUCR _SFR_IO8(0x35) /* Extended MCU Control Register */ #define EMCUCR _SFR_IO8(0x36) /* Store Program Memory Control Register */ #define SPMCR _SFR_IO8(0x37) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt Control Register */ #define GICR _SFR_IO8(0x3B) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 3 #define TIMER1_CAPT_vect _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 4 #define TIMER1_COMPA_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) /* Timer/Counter1 Compare MatchB */ #define TIMER1_COMPB_vect_num 5 #define TIMER1_COMPB_vect _VECTOR(5) #define SIG_OUTPUT_COMPARE1B _VECTOR(5) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 6 #define TIMER1_OVF_vect _VECTOR(6) #define SIG_OVERFLOW1 _VECTOR(6) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 7 #define TIMER0_OVF_vect _VECTOR(7) #define SIG_OVERFLOW0 _VECTOR(7) /* Serial Transfer Complete */ #define SPI_STC_vect_num 8 #define SPI_STC_vect _VECTOR(8) #define SIG_SPI _VECTOR(8) /* UART, Rx Complete */ #define USART_RX_vect_num 9 #define USART_RX_vect _VECTOR(9) #define UART_RX_vect _VECTOR(9) /* For compatability only */ #define SIG_UART_RECV _VECTOR(9) /* For compatability only */ /* UART Data Register Empty */ #define USART_UDRE_vect_num 10 #define USART_UDRE_vect _VECTOR(10) #define UART_UDRE_vect _VECTOR(10) /* For compatability only */ #define SIG_UART_DATA _VECTOR(10) /* For compatability only */ /* UART, Tx Complete */ #define USART_TX_vect_num 11 #define USART_TX_vect _VECTOR(11) #define UART_TX_vect _VECTOR(11) /* For compatability only */ #define SIG_UART_TRANS _VECTOR(11) /* For compatability only */ /* Analog Comparator */ #define ANA_COMP_vect_num 12 #define ANA_COMP_vect _VECTOR(12) #define SIG_COMPARATOR _VECTOR(12) /* External Interrupt Request 2 */ #define INT2_vect_num 13 #define INT2_vect _VECTOR(13) #define SIG_INTERRUPT2 _VECTOR(13) /* Timer 0 Compare Match */ #define TIMER0_COMP_vect_num 14 #define TIMER0_COMP_vect _VECTOR(14) #define SIG_OUTPUT_COMPARE0 _VECTOR(14) /* EEPROM Ready */ #define EE_RDY_vect_num 15 #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) /* Store Program Memory Ready */ #define SPM_RDY_vect_num 16 #define SPM_RDY_vect _VECTOR(16) #define SIG_SPM_READY _VECTOR(16) #define _VECTORS_SIZE 34 /* The Register Bit names are represented by their bit number (0-7). */ /* General Interrupt Control Register */ #define INT1 7 #define INT0 6 #define INT2 5 #define IVSEL 1 #define IVCE 0 /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 #define INTF2 5 /* Timer/Counter Interrupt MaSK Register */ #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 #define TICIE1 3 #define TOIE0 1 #define OCIE0 0 /* Timer/Counter Interrupt Flag Register */ #define TOV1 7 #define OCF1A 6 #define OCF1B 5 #define ICF1 3 #define TOV0 1 #define OCF0 0 /* Store Program Memory Control Register */ #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* Extended MCU Control Register */ #define SM0 7 #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW01 3 #define SRW00 2 #define SRW11 1 #define ISC2 0 /* MCU Control Register */ #define SRE 7 #define SRW10 6 #define SE 5 #define SM1 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* MCU Control and Status Register */ #define SM2 5 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* Timer/Counter 0 Control Register */ #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* Special Function IO Register */ #define XMBK 6 #define XMM2 5 #define XMM1 4 #define XMM0 3 #define PUD 2 #define PSR10 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define WGM11 1 #define WGM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Watchdog Timer Control Register */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* USART Control and Status Register C */ #define URSEL 7 #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* Data Register, Port A */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Data Direction Register, Port A */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Input Pins, Port A */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port C */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Direction Register, Port C */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* USART Control and Status Register A */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define PE 2 #define U2X 1 #define MPCM 0 /* USART Control and Status Register B */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* Data Register, Port E */ #define PE2 2 #define PE1 1 #define PE0 0 /* Data Direction Register, Port E */ #define DDE2 2 #define DDE1 1 #define DDE0 0 /* Input Pins, Port E */ #define PINE2 2 #define PINE1 1 #define PINE0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x60) #define RAMEND 0x25F /* Last On-Chip SRAM Location */ #define XRAMEND 0xFFFF #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_WDTON (unsigned char)~_BV(6) #define FUSE_S8515C (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x06 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison UART_RX_vect #pragma GCC poison SIG_UART_RECV #pragma GCC poison UART_UDRE_vect #pragma GCC poison SIG_UART_DATA #pragma GCC poison UART_TX_vect #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM8515_H_ */ avr-libc-1.8.0.orig/include/avr/iom161.h0000644000000000000000000003425411732702554014462 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom161.h 2229 2011-03-05 17:00:18Z arcanum $ */ /* avr/iom161.h - definitions for ATmega161 */ #ifndef _AVR_IOM161_H_ #define _AVR_IOM161_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom161.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* UART1 Baud Rate Register */ #define UBRR1 _SFR_IO8(0x00) /* UART1 Control and Status Registers */ #define UCSR1B _SFR_IO8(0x01) #define UCSR1A _SFR_IO8(0x02) /* UART1 I/O Data Register */ #define UDR1 _SFR_IO8(0x03) /* 0x04 reserved */ /* Input Pins, Port E */ #define PINE _SFR_IO8(0x05) /* Data Direction Register, Port E */ #define DDRE _SFR_IO8(0x06) /* Data Register, Port E */ #define PORTE _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART0 Baud Rate Register */ #define UBRR0 _SFR_IO8(0x09) /* UART0 Control and Status Registers */ #define UCSR0B _SFR_IO8(0x0A) #define UCSR0A _SFR_IO8(0x0B) /* UART0 I/O Data Register */ #define UDR0 _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* UART Baud Register HIgh */ #define UBRRH _SFR_IO8(0x20) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* Timer/Counter2 Output Compare Register */ #define OCR2 _SFR_IO8(0x22) /* Timer/Counter2 (8-bit) */ #define TCNT2 _SFR_IO8(0x23) /* Timer/Counter1 Input Capture Register */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* ASynchronous mode Status Register */ #define ASSR _SFR_IO8(0x26) /* Timer/Counter2 Control Register */ #define TCCR2 _SFR_IO8(0x27) /* Timer/Counter1 Output Compare RegisterB */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare RegisterA */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter1 Control Register B */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter1 Control Register A */ #define TCCR1A _SFR_IO8(0x2F) /* Special Function IO Register */ #define SFIOR _SFR_IO8(0x30) /* Timer/Counter0 Output Compare Register */ #define OCR0 _SFR_IO8(0x31) /* Timer/Counter0 (8-bit) */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Extended MCU general Control Register */ #define EMCUCR _SFR_IO8(0x36) /* Store Program Memory Control Register */ #define SPMCR _SFR_IO8(0x37) /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK Register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3C reserved */ /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* UART0, Rx Complete */ #define UART0_RX_vect_num 13 #define UART0_RX_vect _VECTOR(13) #define SIG_UART0_RECV _VECTOR(13) /* UART1, Rx Complete */ #define UART1_RX_vect_num 14 #define UART1_RX_vect _VECTOR(14) #define SIG_UART1_RECV _VECTOR(14) /* UART0 Data Register Empty */ #define UART0_UDRE_vect_num 15 #define UART0_UDRE_vect _VECTOR(15) #define SIG_UART0_DATA _VECTOR(15) /* UART1 Data Register Empty */ #define UART1_UDRE_vect_num 16 #define UART1_UDRE_vect _VECTOR(16) #define SIG_UART1_DATA _VECTOR(16) /* UART0, Tx Complete */ #define UART0_TX_vect_num 17 #define UART0_TX_vect _VECTOR(17) #define SIG_UART0_TRANS _VECTOR(17) /* UART1, Tx Complete */ #define UART1_TX_vect_num 18 #define UART1_TX_vect _VECTOR(18) #define SIG_UART1_TRANS _VECTOR(18) /* EEPROM Ready */ #define EE_RDY_vect_num 19 #define EE_RDY_vect _VECTOR(19) #define SIG_EEPROM_READY _VECTOR(19) /* Analog Comparator */ #define ANA_COMP_vect_num 20 #define ANA_COMP_vect _VECTOR(20) #define SIG_COMPARATOR _VECTOR(20) #define _VECTORS_SIZE 84 /* Bit numbers */ /* GIMSK */ #define INT1 7 #define INT0 6 #define INT2 5 /* GIFR */ #define INTF1 7 #define INTF0 6 #define INTF2 5 /* TIMSK */ #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 #define TOIE2 4 #define TICIE1 3 #define OCIE2 2 #define TOIE0 1 #define OCIE0 0 /* TIFR */ #define TOV1 7 #define OCF1A 6 #define OCF1B 5 #define TOV2 4 #define ICF1 3 #define OCF2 2 #define TOV0 1 #define OCF0 0 /* MCUCR */ #define SRE 7 #define SRW10 6 #define SE 5 #define SM1 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* EMCUCR */ #define SM0 7 #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW01 3 #define SRW00 2 #define SRW11 1 #define ISC2 0 /* SPMCR */ #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* SFIOR */ #define PSR2 1 #define PSR10 0 /* TCCR0 */ #define FOC0 7 #define PWM0 6 #define COM01 5 #define COM00 4 #define CTC0 3 #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR2 */ #define FOC2 7 #define PWM2 6 #define COM21 5 #define COM20 4 #define CTC2 3 #define CS22 2 #define CS21 1 #define CS20 0 /* ASSR */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define PWM11 1 #define PWM10 0 /* TCCR1B */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* WDTCR */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* PB7 = SCK PB6 = MISO PB5 = MOSI PB4 = SS# PB3 = TXD1 / AIN1 PB2 = RXD1 / AIN0 PB1 = OC2 / T1 PB0 = OC0 / T0 */ /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* PD7 = RD# PD6 = WR# PD5 = TOSC2 / OC1A PD4 = TOSC1 PD3 = INT1 PD2 = INT0 PD1 = TXD0 PD0 = RXD0 */ /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* PE2 = ALE PE1 = OC1B PE0 = ICP / INT2 */ /* PORTE */ #define PE2 2 #define PE1 1 #define PE0 0 /* DDRE */ #define DDE2 2 #define DDE1 1 #define DDE0 0 /* PINE */ #define PINE2 2 #define PINE1 1 #define PINE0 0 /* SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UCSR0A, UCSR1A */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define U2X 1 #define MPCM 0 /* UCSR0B, UCSR1B */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* ACSR */ #define ACD 7 #define AINBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x45F #define XRAMEND 0xFFFF #define E2END 0x1FF #define E2PAGESIZE 0 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_SUT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_BOOTRST (unsigned char)~_BV(6) #define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x01 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART0_RECV #pragma GCC poison SIG_UART1_RECV #pragma GCC poison SIG_UART0_DATA #pragma GCC poison SIG_UART1_DATA #pragma GCC poison SIG_UART0_TRANS #pragma GCC poison SIG_UART1_TRANS #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM161_H_ */ avr-libc-1.8.0.orig/include/avr/iox192d3.h0000644000000000000000000073020411732702554014726 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox192d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ /* avr/iox192d3.h - definitions for ATxmega192D3 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox192d3.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega192D3_H_ #define _AVR_ATxmega192D3_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */ BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) #define TWIC_MASTER_DATA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRLA bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (114 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (204800) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (196608) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x2E000) #define APPTABLE_SECTION_SIZE (8192) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x30000) #define BOOT_SECTION_SIZE (8192) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (24576) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (16384) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x49 #endif /* _AVR_ATxmega192D3_H_ */ avr-libc-1.8.0.orig/include/avr/iotnx4.h0000644000000000000000000002462611732702554014675 0ustar /* Copyright (c) 2005,2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotnx4.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iotnx4.h - definitions for ATtiny24, ATtiny44 and ATtiny84 */ #ifndef _AVR_IOTNX4_H_ #define _AVR_IOTNX4_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotnx4.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ #define PRR _SFR_IO8 (0x00) #define PRTIM1 3 #define PRTIM0 2 #define PRUSI 1 #define PRADC 0 #define DIDR0 _SFR_IO8(0x01) #define ADC7D 7 #define ADC6D 6 #define ADC5D 5 #define ADC4D 4 #define ADC3D 3 #define ADC2D 2 #define ADC1D 1 #define ADC0D 0 /* Reserved [0x02] */ #define ADCSRB _SFR_IO8 (0x03) #define BIN 7 #define ACME 6 #define ADLAR 4 #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSRA _SFR_IO8 (0x06) #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 #define ADMUX _SFR_IO8(0x07) #define REFS1 7 #define REFS0 6 #define MUX5 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 #define ACSR _SFR_IO8(0x08) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* Reserved [0x09..0x0A] */ #define TIFR1 _SFR_IO8(0x0B) #define ICF1 5 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 #define TIMSK1 _SFR_IO8(0x0C) #define ICIE1 5 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 #define USICR _SFR_IO8(0x0D) #define USISIE 7 #define USIOIE 6 #define USIWM1 5 #define USIWM0 4 #define USICS1 3 #define USICS0 2 #define USICLK 1 #define USITC 0 #define USISR _SFR_IO8(0x0E) #define USISIF 7 #define USIOIF 6 #define USIPF 5 #define USIDC 4 #define USICNT3 3 #define USICNT2 2 #define USICNT1 1 #define USICNT0 0 #define USIDR _SFR_IO8(0x0F) #define USIBR _SFR_IO8(0x10) /* Reserved [0x11] */ #define PCMSK0 _SFR_IO8(0x12) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 #define GPIOR0 _SFR_IO8(0x13) #define GPIOR1 _SFR_IO8(0x14) #define GPIOR2 _SFR_IO8(0x15) #define PINB _SFR_IO8(0x16) #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x17) #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x18) #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINA _SFR_IO8(0x19) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x1A) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x1B) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* EEPROM Control Register EECR */ #define EECR _SFR_IO8(0x1C) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define PCMSK1 _SFR_IO8(0x20) #define PCINT11 3 #define PCINT10 2 #define PCINT9 1 #define PCINT8 0 #define WDTCSR _SFR_IO8(0x21) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 #define TCCR1C _SFR_IO8(0x22) #define FOC1A 7 #define FOC1B 6 #define GTCCR _SFR_IO8(0x23) #define TSM 7 #define PSR10 0 #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) #define CLKPR _SFR_IO8(0x26) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 #define DWDR _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* keep misspelled names from avr-libc 1.4.[0..1] for compatibility */ #define OCRB1 _SFR_IO16(0x28) #define OCRB1L _SFR_IO8(0x28) #define OCRB1H _SFR_IO8(0x29) #define OCRA1 _SFR_IO16(0x2A) #define OCRA1L _SFR_IO8(0x2A) #define OCRA1H _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 #define TCCR1A _SFR_IO8(0x2F) #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define WGM11 1 #define WGM10 0 #define TCCR0A _SFR_IO8(0x30) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 #define OSCCAL _SFR_IO8(0x31) #define TCNT0 _SFR_IO8(0x32) #define TCCR0B _SFR_IO8(0x33) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 #define MCUSR _SFR_IO8(0x34) #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 #define MCUCR _SFR_IO8(0x35) #define BODS 7 #define PUD 6 #define SE 5 #define SM1 4 #define SM0 3 #define BODSE 2 #define ISC01 1 #define ISC00 0 #define OCR0A _SFR_IO8(0x36) #define SPMCSR _SFR_IO8(0x37) #define RSIG 5 #define CTPB 4 #define RFLB 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 #define TIFR0 _SFR_IO8(0x38) #define OCF0B 2 #define OCF0A 1 #define TOV0 0 #define TIMSK0 _SFR_IO8(0x39) #define OCIE0B 2 #define OCIE0A 1 #define TOIE0 0 #define GIFR _SFR_IO8(0x3A) #define INTF0 6 #define PCIF1 5 #define PCIF0 4 #define GIMSK _SFR_IO8(0x3B) #define INT0 6 #define PCIE1 5 #define PCIE0 4 #define OCR0B _SFR_IO8(0x3C) /* 0x3D..0x3E SP [defined in ] */ /* 0x3F SREG [defined in ] */ ///--- /* Interrupt vectors */ /* Interrupt vector 0 is the reset vector. */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define EXT_INT0_vect_num 1 #define EXT_INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Watchdog Time-out */ #define WDT_vect_num 4 #define WDT_vect _VECTOR(4) #define WATCHDOG_vect_num 4 #define WATCHDOG_vect _VECTOR(4) #define SIG_WATCHDOG_TIMEOUT _VECTOR(4) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 5 #define TIMER1_CAPT_vect _VECTOR(5) #define TIM1_CAPT_vect_num 5 #define TIM1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) /* Timer/Counter1 Compare Match A */ #define TIM1_COMPA_vect_num 6 #define TIM1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) /* Timer/Counter1 Compare Match B */ #define TIM1_COMPB_vect_num 7 #define TIM1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) /* Timer/Counter1 Overflow */ #define TIM1_OVF_vect_num 8 #define TIM1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) /* Timer/Counter0 Compare Match A */ #define TIM0_COMPA_vect_num 9 #define TIM0_COMPA_vect _VECTOR(9) #define SIG_OUTPUT_COMPARE0A _VECTOR(9) /* Timer/Counter0 Compare Match B */ #define TIM0_COMPB_vect_num 10 #define TIM0_COMPB_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0B _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIM0_OVF_vect_num 11 #define TIM0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* Analog Comparator */ #define ANA_COMP_vect_num 12 #define ANA_COMP_vect _VECTOR(12) #define SIG_COMPARATOR _VECTOR(12) /* ADC Conversion Complete */ #define ADC_vect_num 13 #define ADC_vect _VECTOR(13) #define SIG_ADC _VECTOR(13) /* EEPROM Ready */ #define EE_RDY_vect_num 14 #define EE_RDY_vect _VECTOR(14) #define SIG_EEPROM_READY _VECTOR(14) /* USI START */ #define USI_START_vect_num 15 #define USI_START_vect _VECTOR(15) #define USI_STR_vect_num 15 #define USI_STR_vect _VECTOR(15) #define SIG_USI_START _VECTOR(15) /* USI Overflow */ #define USI_OVF_vect_num 16 #define USI_OVF_vect _VECTOR(16) #define SIG_USI_OVERFLOW _VECTOR(16) #define _VECTORS_SIZE 34 #endif /* _AVR_IOTNX4_H_ */ avr-libc-1.8.0.orig/include/avr/iom6450.h0000644000000000000000000005016011732702554014543 0ustar /* Copyright (c) 2004,2005,2006 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom6450.h 2235 2011-03-17 04:13:14Z arcanum $ */ /* avr/iom6450.h - definitions for ATmega6450 */ #ifndef _AVR_IOM6450_H_ #define _AVR_IOM6450_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom6450.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define PCIF2 6 #define PCIF3 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define PCIE2 6 #define PCIE3 7 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x72] */ #define PCMSK3 _SFR_MEM8(0x73) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define PCINT27 3 #define PCINT28 4 #define PCINT29 5 #define PCINT30 6 /* Reserved [0x74..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0XC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7..0xD7] */ #define PINH _SFR_MEM8(0xD8) #define PINH7 7 #define PINH6 6 #define PINH5 5 #define PINH4 4 #define PINH3 3 #define PINH2 2 #define PINH1 1 #define PINH0 0 #define DDRH _SFR_MEM8(0xD9) #define DDH7 7 #define DDH6 6 #define DDH5 5 #define DDH4 4 #define DDH3 3 #define DDH2 2 #define DDH1 1 #define DDH0 0 #define PORTH _SFR_MEM8(0xDA) #define PH7 7 #define PH6 6 #define PH5 5 #define PH4 4 #define PH3 3 #define PH2 2 #define PH1 1 #define PH0 0 #define PINJ _SFR_MEM8(0xDB) #define PINJ6 6 #define PINJ5 5 #define PINJ4 4 #define PINJ3 3 #define PINJ2 2 #define PINJ1 1 #define PINJ0 0 #define DDRJ _SFR_MEM8(0xDC) #define DDJ6 6 #define DDJ5 5 #define DDJ4 4 #define DDJ3 3 #define DDJ2 2 #define DDJ1 1 #define DDJ0 0 #define PORTJ _SFR_MEM8(0xDD) #define PJ6 6 #define PJ5 5 #define PJ4 4 #define PJ3 3 #define PJ2 2 #define PJ1 1 #define PJ0 0 /* Reserved [0xDE..0xFF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART, Rx Complete */ #define USART_RX_vect_num 13 #define USART_RX_vect _VECTOR(13) #define USART0_RX_vect _VECTOR(13) /* Alias */ #define SIG_UART_RECV _VECTOR(13) /* USART Data register Empty */ #define USART_UDRE_vect_num 14 #define USART_UDRE_vect _VECTOR(14) #define USART0_UDRE_vect _VECTOR(14) /* Alias */ #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define USART_TX_vect _VECTOR(15) /* Alias */ #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* Pin Change Interrupt Request 2 */ #define PCINT2_vect_num 23 #define PCINT2_vect _VECTOR(23) #define SIG_PIN_CHANGE2 _VECTOR(23) /* Pin Change Interrupt Request 3 */ #define PCINT3_vect_num 24 #define PCINT3_vect _VECTOR(24) #define SIG_PIN_CHANGE3 _VECTOR(24) #define _VECTORS_SIZE 100 /* Constants */ #define SPM_PAGESIZE 256 #define RAMSTART (0x100) #define RAMEND 0x10FF #define XRAMEND RAMEND #define E2END 0x7FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x06 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison USART0_RX_vect #pragma GCC poison SIG_UART_RECV #pragma GCC poison USART0_UDRE_vect #pragma GCC poison SIG_UART_DATA #pragma GCC poison USART_TX_vect #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #pragma GCC poison SIG_PIN_CHANGE2 #pragma GCC poison SIG_PIN_CHANGE3 #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM6450_H_ */ avr-libc-1.8.0.orig/include/avr/common.h0000644000000000000000000001736211732702554014737 0ustar /* Copyright (c) 2007 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: common.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ #ifndef _AVR_COMMON_H #define _AVR_COMMON_H #include /* This purpose of this header is to define registers that have not been previously defined in the individual device IO header files, and to define other symbols that are common across AVR device families. This file is designed to be included in after the individual device IO header files, and after */ /*------------ Registers Not Previously Defined ------------*/ /* These are registers that are not previously defined in the individual IO header files, OR they are defined here because they are used in parts of avr-libc even if a device is not selected but a general architecture has been selected. */ /* Stack pointer register. AVR architecture 1 has no RAM, thus no stack pointer. All other architectures do have a stack pointer. Some devices have only less than 256 bytes of possible RAM locations (128 Bytes of SRAM and no option for external RAM), thus SPH is officially "reserved" for them. */ #if __AVR_ARCH__ >= 100 # ifndef SPL # define SPL _SFR_MEM8(0x3D) # endif # ifndef SPH # define SPH _SFR_MEM8(0x3E) # endif # ifndef SP # define SP _SFR_MEM16(0x3D) # endif #elif __AVR_ARCH__ != 1 # ifndef SPL # define SPL _SFR_IO8(0x3D) # endif # if XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) # ifndef SP # define SP _SFR_IO8(0x3D) # endif # else # ifndef SP # define SP _SFR_IO16(0x3D) # endif # ifndef SPH # define SPH _SFR_IO8(0x3E) # endif # endif /* XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) */ #endif /* __AVR_ARCH__ != 1 */ /* Status Register */ #ifndef SREG # if __AVR_ARCH__ >= 100 # define SREG _SFR_MEM8(0x3F) # else # define SREG _SFR_IO8(0x3F) # endif #endif /* SREG bit definitions */ #ifndef SREG_C # define SREG_C (0) #endif #ifndef SREG_Z # define SREG_Z (1) #endif #ifndef SREG_N # define SREG_N (2) #endif #ifndef SREG_V # define SREG_V (3) #endif #ifndef SREG_S # define SREG_S (4) #endif #ifndef SREG_H # define SREG_H (5) #endif #ifndef SREG_T # define SREG_T (6) #endif #ifndef SREG_I # define SREG_I (7) #endif #if defined(__COMPILING_AVR_LIBC__) /* AVR 6 Architecture */ # if __AVR_ARCH__ == 6 # ifndef EIND # define EIND _SFR_IO8(0X3C) # endif /* XMEGA Architectures */ # elif __AVR_ARCH__ >= 100 # ifndef EIND # define EIND _SFR_MEM8(0x3C) # endif # endif /* Only few devices come without EEPROM. In order to assemble the EEPROM library components without defining a specific device, we keep the EEPROM-related definitions here. */ /* EEPROM Control Register */ # ifndef EECR # define EECR _SFR_IO8(0x1C) # endif /* EEPROM Data Register */ # ifndef EEDR # define EEDR _SFR_IO8(0x1D) # endif /* EEPROM Address Register */ # ifndef EEAR # define EEAR _SFR_IO16(0x1E) # endif # ifndef EEARL # define EEARL _SFR_IO8(0x1E) # endif # ifndef EEARH # define EEARH _SFR_IO8(0x1F) # endif /* EEPROM Control Register bits */ # ifndef EERE # define EERE (0) # endif # ifndef EEWE # define EEWE (1) # endif # ifndef EEMWE # define EEMWE (2) # endif # ifndef EERIE # define EERIE (3) # endif #endif /* __COMPILING_AVR_LIBC__ */ /*------------ Common Symbols ------------*/ /* Generic definitions for registers that are common across multiple AVR devices and families. */ /* Pointer registers definitions */ #if __AVR_ARCH__ != 1 /* avr1 does not have X and Y pointers */ # define XL r26 # define XH r27 # define YL r28 # define YH r29 #endif /* #if __AVR_ARCH__ != 1 */ #define ZL r30 #define ZH r31 /* Status Register */ #if defined(SREG) # define AVR_STATUS_REG SREG # if __AVR_ARCH__ >= 100 # define AVR_STATUS_ADDR _SFR_MEM_ADDR(SREG) # else # define AVR_STATUS_ADDR _SFR_IO_ADDR(SREG) # endif #endif /* Stack Pointer (combined) Register */ #if defined(SP) # define AVR_STACK_POINTER_REG SP # if __AVR_ARCH__ >= 100 # define AVR_STACK_POINTER_ADDR _SFR_MEM_ADDR(SP) # else # define AVR_STACK_POINTER_ADDR _SFR_IO_ADDR(SP) # endif #endif /* Stack Pointer High Register */ #if defined(SPH) # define _HAVE_AVR_STACK_POINTER_HI 1 # define AVR_STACK_POINTER_HI_REG SPH # if __AVR_ARCH__ >= 100 # define AVR_STACK_POINTER_HI_ADDR _SFR_MEM_ADDR(SPH) # else # define AVR_STACK_POINTER_HI_ADDR _SFR_IO_ADDR(SPH) # endif #endif /* Stack Pointer Low Register */ #if defined(SPL) # define AVR_STACK_POINTER_LO_REG SPL # if __AVR_ARCH__ >= 100 # define AVR_STACK_POINTER_LO_ADDR _SFR_MEM_ADDR(SPL) # else # define AVR_STACK_POINTER_LO_ADDR _SFR_IO_ADDR(SPL) # endif #endif /* RAMPD Register */ #if defined(RAMPD) # define AVR_RAMPD_REG RAMPD # if __AVR_ARCH__ >= 100 # define AVR_RAMPD_ADDR _SFR_MEM_ADDR(RAMPD) # else # define AVR_RAMPD_ADDR _SFR_IO_ADDR(RAMPD) # endif #endif /* RAMPX Register */ #if defined(RAMPX) # define AVR_RAMPX_REG RAMPX # if __AVR_ARCH__ >= 100 # define AVR_RAMPX_ADDR _SFR_MEM_ADDR(RAMPX) # else # define AVR_RAMPX_ADDR _SFR_IO_ADDR(RAMPX) # endif #endif /* RAMPY Register */ #if defined(RAMPY) # define AVR_RAMPY_REG RAMPY # if __AVR_ARCH__ >= 100 # define AVR_RAMPY_ADDR _SFR_MEM_ADDR(RAMPY) # else # define AVR_RAMPY_ADDR _SFR_IO_ADDR(RAMPY) # endif #endif /* RAMPZ Register */ #if defined(RAMPZ) # define AVR_RAMPZ_REG RAMPZ # if __AVR_ARCH__ >= 100 # define AVR_RAMPZ_ADDR _SFR_MEM_ADDR(RAMPZ) # else # define AVR_RAMPZ_ADDR _SFR_IO_ADDR(RAMPZ) # endif #endif /* Extended Indirect Register */ #if defined(EIND) # define AVR_EXTENDED_INDIRECT_REG EIND # if __AVR_ARCH__ >= 100 # define AVR_EXTENDED_INDIRECT_ADDR _SFR_MEM_ADDR(EIND) # else # define AVR_EXTENDED_INDIRECT_ADDR _SFR_IO_ADDR(EIND) # endif #endif /*------------ Workaround to old compilers (4.1.2 and earlier) ------------*/ #ifndef __AVR_HAVE_MOVW__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_MOVW__ 1 # endif #endif #ifndef __AVR_HAVE_LPMX__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_LPMX__ 1 # endif #endif #ifndef __AVR_HAVE_MUL__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_MUL__ 1 # endif #endif #endif /* _AVR_COMMON_H */ avr-libc-1.8.0.orig/include/avr/iom163.h0000644000000000000000000003205011732702554014454 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom163.h 2231 2011-03-07 05:06:55Z arcanum $ */ /* avr/iom163.h - definitions for ATmega163 */ #ifndef _AVR_IOM163_H_ #define _AVR_IOM163_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom163.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWAR _SFR_IO8(0x02) #define TWDR _SFR_IO8(0x03) /* ADC */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSR _SFR_IO8(0x06) #define ADMUX _SFR_IO8(0x07) /* analog comparator */ #define ACSR _SFR_IO8(0x08) /* UART */ #define UBRR _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) #define UDR _SFR_IO8(0x0C) /* SPI */ #define SPCR _SFR_IO8(0x0D) #define SPSR _SFR_IO8(0x0E) #define SPDR _SFR_IO8(0x0F) /* Port D */ #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) /* Port C */ #define PINC _SFR_IO8(0x13) #define DDRC _SFR_IO8(0x14) #define PORTC _SFR_IO8(0x15) /* Port B */ #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) /* Port A */ #define PINA _SFR_IO8(0x19) #define DDRA _SFR_IO8(0x1A) #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UBRRHI _SFR_IO8(0x20) #define WDTCR _SFR_IO8(0x21) #define ASSR _SFR_IO8(0x22) /* Timer 2 */ #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) /* Timer 1 */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define TCCR1A _SFR_IO8(0x2F) #define SFIOR _SFR_IO8(0x30) #define OSCCAL _SFR_IO8(0x31) /* Timer 0 */ #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define MCUSR _SFR_IO8(0x34) #define MCUCR _SFR_IO8(0x35) #define TWCR _SFR_IO8(0x36) #define SPMCR _SFR_IO8(0x37) #define TIFR _SFR_IO8(0x38) #define TIMSK _SFR_IO8(0x39) #define GIFR _SFR_IO8(0x3A) #define GIMSK _SFR_IO8(0x3B) /* 0x3C reserved */ /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 3 #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 4 #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 5 #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 6 #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 7 #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 8 #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 9 #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 10 #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) /* UART, RX Complete */ #define UART_RX_vect_num 11 #define UART_RX_vect _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) /* UART Data Register Empty */ #define UART_UDRE_vect_num 12 #define UART_UDRE_vect _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) /* UART, TX Complete */ #define UART_TX_vect_num 13 #define UART_TX_vect _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) /* ADC Conversion Complete */ #define ADC_vect_num 14 #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) /* EEPROM Ready */ #define EE_RDY_vect_num 15 #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) /* Analog Comparator */ #define ANA_COMP_vect_num 16 #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) /* 2-Wire Serial Interface */ #define TWI_vect_num 17 #define TWI_vect _VECTOR(17) #define SIG_2WIRE_SERIAL _VECTOR(17) #define _VECTORS_SIZE 72 /* Bit numbers */ /* GIMSK */ #define INT1 7 #define INT0 6 /* bit 5 reserved, undefined */ /* bits 4-0 reserved */ /* GIFR */ #define INTF1 7 #define INTF0 6 /* bits 5-0 reserved */ /* TIMSK */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 /* bit 1 reserved */ #define TOIE0 0 /* TIFR */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 /* bit 1 reserved, undefined */ #define TOV0 0 /* SPMCR */ /* bit 7 reserved */ #define ASB 6 /* bit 5 reserved */ #define ASRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 /* bit 1 reserved */ #define TWIE 0 /* TWAR */ #define TWGCE 0 /* TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 /* bits 2-0 reserved */ /* MCUCR */ /* bit 7 reserved */ #define SE 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* MCUSR */ /* bits 7-4 reserved */ #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* SFIOR */ /* bits 7-4 reserved */ #define ACME 3 #define PUD 2 #define PSR2 1 #define PSR10 0 /* TCCR0 */ /* bits 7-3 reserved */ #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR2 */ #define FOC2 7 #define PWM2 6 #define COM21 5 #define COM20 4 #define CTC2 3 #define CS22 2 #define CS21 1 #define CS20 0 /* ASSR */ /* bits 7-4 reserved */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define PWM11 1 #define PWM10 0 /* TCCR1B */ #define ICNC1 7 #define ICES1 6 /* bits 5-4 reserved */ #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* WDTCR */ /* bits 7-5 reserved */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PA7-PA0 = ADC7-ADC0 */ /* PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* PB7 = SCK PB6 = MISO PB5 = MOSI PB4 = SS# PB3 = AIN1 PB2 = AIN0 PB1 = T1 PB0 = T0 */ /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PC7 = TOSC2 PC6 = TOSC1 PC1 = SDA PC0 = SCL */ /* PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* PD7 = OC2 PD6 = ICP PD5 = OC1A PD4 = OC1B PD3 = INT1 PD2 = INT0 PD1 = TXD PD0 = RXD */ /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPSR */ #define SPIF 7 #define WCOL 6 /* bits 5-1 reserved */ #define SPI2X 0 /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UCSRA */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 /* bit 2 reserved */ #define U2X 1 #define MPCM 0 /* UCSRB */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* ACSR */ #define ACD 7 #define AINBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADCSR */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x45F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 0 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define HFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x02 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_2WIRE_SERIAL #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM163_H_ */ avr-libc-1.8.0.orig/include/avr/delay.h0000644000000000000000000000334411732702554014540 0ustar /* Copyright (c) 2005 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: delay.h 933 2005-11-05 22:23:16Z joerg_wunsch $ */ #ifndef _AVR_DELAY_H_ #define _AVR_DELAY_H_ #warning "This file has been moved to ." #include #endif /* _AVR_DELAY_H_ */ avr-libc-1.8.0.orig/include/avr/iom2561.h0000644000000000000000000000642111732702554014543 0ustar /* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id */ /* avr/iom2561.h - definitions for ATmega2561 */ #ifndef _AVR_IOM2561_H_ #define _AVR_IOM2561_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x21FF #define XRAMEND 0xFFFF #define E2END 0xFFF #define E2PAGESIZE 8 #define FLASHEND 0x3FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x98 #define SIGNATURE_2 0x02 #endif /* _AVR_IOM2561_H_ */ avr-libc-1.8.0.orig/include/avr/iom48.h0000644000000000000000000000701611732702554014402 0ustar /* Copyright (c) 2004, Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom48.h 2115 2010-04-05 23:19:53Z arcanum $ */ #ifndef _AVR_IOM48_H_ #define _AVR_IOM48_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x100) #define RAMEND 0x2FF #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 4 #define FLASHEND 0xFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x05 #endif /* _AVR_IOM48_H_ */ avr-libc-1.8.0.orig/include/avr/iotn24.h0000644000000000000000000000613411732702554014561 0ustar /* Copyright (c) 2005, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn24.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iotn24.h - definitions for ATtiny24 */ #ifndef _AVR_IOTN24_H_ #define _AVR_IOTN24_H_ 1 #include #define SPM_PAGESIZE 32 #define RAMSTART (0x60) #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 4 #define FLASHEND 0x7FF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x0B #endif /* _AVR_IOTN24_H_ */ avr-libc-1.8.0.orig/include/avr/iox128a3.h0000644000000000000000000111151311732702554014717 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox128a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox128a3.h - definitions for ATxmega128A3 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox128a3.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega128A3_H_ #define _AVR_ATxmega128A3_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* JTAG User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t GAINCAL; /* Gain Calibration */ register8_t OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* ADCB - Analog to Digital Converter B */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) #define ADCB_EVCTRL _SFR_MEM8(0x0243) #define ADCB_PRESCALER _SFR_MEM8(0x0244) #define ADCB_INTFLAGS _SFR_MEM8(0x0246) #define ADCB_CAL _SFR_MEM16(0x024C) #define ADCB_CH0RES _SFR_MEM16(0x0250) #define ADCB_CH1RES _SFR_MEM16(0x0252) #define ADCB_CH2RES _SFR_MEM16(0x0254) #define ADCB_CH3RES _SFR_MEM16(0x0256) #define ADCB_CMP _SFR_MEM16(0x0258) #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_GAINCAL _SFR_MEM8(0x0328) #define DACB_OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* TCE1 - Timer/Counter E1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) #define TCE1_CTRLD _SFR_MEM8(0x0A43) #define TCE1_CTRLE _SFR_MEM8(0x0A44) #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) #define TCE1_TEMP _SFR_MEM8(0x0A4F) #define TCE1_CNT _SFR_MEM16(0x0A60) #define TCE1_PER _SFR_MEM16(0x0A66) #define TCE1_CCA _SFR_MEM16(0x0A68) #define TCE1_CCB _SFR_MEM16(0x0A6A) #define TCE1_PERBUF _SFR_MEM16(0x0A76) #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) #define USARTE1_CTRLB _SFR_MEM8(0x0AB4) #define USARTE1_CTRLC _SFR_MEM8(0x0AB5) #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /* HIRESF - High-Resolution Extension F */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) /* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) #define USARTF1_CTRLB _SFR_MEM8(0x0BB4) #define USARTF1_CTRLC _SFR_MEM8(0x0BB5) #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) /* SPIF - Serial Peripheral Interface F */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) #define SPIF_DATA _SFR_MEM8(0x0BC3) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ #define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ #define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ #define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ #define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ #define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ #define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ #define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ #define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ #define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ #define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ #define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ #define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ #define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ #define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ #define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ #define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ #define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ #define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ #define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* ACB interrupt vectors */ #define ACB_AC0_vect_num 36 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ #define ACB_AC1_vect_num 37 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ #define ACB_ACW_vect_num 38 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ /* ADCB interrupt vectors */ #define ADCB_CH0_vect_num 39 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ #define ADCB_CH1_vect_num 40 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ #define ADCB_CH2_vect_num 41 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ #define ADCB_CH3_vect_num 42 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* SPIE interrupt vectors */ #define SPIE_INT_vect_num 57 #define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* USARTE1 interrupt vectors */ #define USARTE1_RXC_vect_num 61 #define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ #define USARTE1_DRE_vect_num 62 #define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ #define USARTE1_TXC_vect_num 63 #define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ /* USARTF0 interrupt vectors */ #define USARTF0_RXC_vect_num 119 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ #define USARTF0_DRE_vect_num 120 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ #define USARTF0_TXC_vect_num 121 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (122 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (139264) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (131072) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x1E000) #define APPTABLE_SECTION_SIZE (8192) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x20000) #define BOOT_SECTION_SIZE (8192) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (16384) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (8192) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ #define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ #define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ #define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ #define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ #define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ #define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ #define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x42 #endif /* _AVR_ATxmega128A3_H_ */ avr-libc-1.8.0.orig/include/avr/iom169p.h0000644000000000000000000005420511732702554014650 0ustar /* Copyright (c) 2002, 2003, 2004, 2005, 2006 Juergen Schilling Eric B. Weddington Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom169p.h 2231 2011-03-07 05:06:55Z arcanum $ */ /* iom169p.h - definitions for ATmega169P */ #ifndef _AVR_IOM169P_H_ #define _AVR_IOM169P_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom169p.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Port A */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Port B */ #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Port C */ #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Port D */ #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Port E */ #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 /* Port F */ #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 /* Port G */ #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 /* Timer/Counter 0 interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) #define OCF0A 1 #define TOV0 0 /* Timer/Counter 1 interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) #define ICF1 5 #define OCF1B 2 #define OCF1A 1 #define TOV1 0 /* Timer/Counter 2 interrupt Flag Register */ #define TIFR2 _SFR_IO8(0x17) #define OCF2A 1 #define TOV2 0 /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) #define PCIF1 7 #define PCIF0 6 #define INTF0 0 /* External Interrupt Mask Register */ #define EIMSK _SFR_IO8(0x1D) #define PCIE1 7 #define PCIE0 6 #define INT0 0 /* General Purpose I/O Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) #define TSM 7 #define PSR2 1 #define PSR10 0 /* Timer/Counter Control Register A */ #define TCCR0A _SFR_IO8(0x24) #define FOC0A 7 #define WGM00 6 #define COM0A1 5 #define COM0A0 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter Register */ #define TCNT0 _SFR_IO8(0x26) /* Output Compare Register A */ #define OCR0A _SFR_IO8(0x27) /* General Purpose I/O Register 1 */ #define GPIOR1 _SFR_IO8(0x2A) /* General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x2B) /* SPI Control Register */ #define SPCR _SFR_IO8(0x2C) #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* SPI Status Register */ #define SPSR _SFR_IO8(0x2D) #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPI Data Register */ #define SPDR _SFR_IO8(0x2E) /* Analog Comperator Control and Status Register */ #define ACSR _SFR_IO8(0x30) #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* On-chip Debug Register */ #define OCDR _SFR_IO8(0x31) #define IDRD 7 #define OCDR7 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 /* Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* MCU Control Rgeister */ #define MCUCR _SFR_IO8(0x35) #define JTD 7 #define PUD 4 #define IVSEL 1 #define IVCE 0 /* Store Program Memory Control and Status Register */ #define SPMCSR _SFR_IO8(0x37) #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* Watchdog Timer Control Register */ #define WDTCR _SFR_MEM8(0x60) #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Clock Prescale Register */ #define CLKPR _SFR_MEM8(0x61) #define CLKPCE 7 #define CLKPS3 3 #define CLKPS2 2 #define CLKPS1 1 #define CLKPS0 0 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRLCD 4 /* Oscillator Calibration Register */ #define OSCCAL _SFR_MEM8(0x66) /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x69) #define ISC01 1 #define ISC00 0 /* Pin Change Mask Register */ #define PCMSK _SFR_MEM16(0x6B) #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT15 7 #define PCINT14 6 #define PCINT13 5 #define PCINT12 4 #define PCINT11 3 #define PCINT10 2 #define PCINT9 1 #define PCINT8 0 /* Timer/Counter 0 Interrupt Mask Register */ #define TIMSK0 _SFR_MEM8(0x6E) #define OCIE0A 1 #define TOIE0 0 /* Timer/Counter 1 Interrupt Mask Register */ #define TIMSK1 _SFR_MEM8(0x6F) #define ICIE1 5 #define OCIE1B 2 #define OCIE1A 1 #define TOIE1 0 /* Timer/Counter 2 Interrupt Mask Register */ #define TIMSK2 _SFR_MEM8(0x70) #define OCIE2A 1 #define TOIE2 0 /* ADC Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) /* ADC Control and Status Register A */ #define ADCSRA _SFR_MEM8(0x7A) #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x7B) #define ACME 6 #define ADTS2 2 #define ADTS1 1 #define ADTS0 0 /* ADC Multiplex Selection Register */ #define ADMUX _SFR_MEM8(0x7C) /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* Digital Input Disable Register 0 */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC7D 7 #define ADC6D 6 #define ADC5D 5 #define ADC4D 4 #define ADC3D 3 #define ADC2D 2 #define ADC1D 1 #define ADC0D 0 /* Digital Input Disable Register 1 */ #define DIDR1 _SFR_MEM8(0x7F) #define AIN1D 1 #define AIN0D 0 /* Timer/Counter1 Control Register A */ #define TCCR1A _SFR_MEM8(0x80) #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define WGM11 1 #define WGM10 0 /* Timer/Counter1 Control Register B */ #define TCCR1B _SFR_MEM8(0x81) #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Timer/Counter1 Control Register C */ #define TCCR1C _SFR_MEM8(0x82) #define FOC1A 7 #define FOC1B 6 /* Timer/Counter1 Register */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Timer/Counter1 Input Capture Register */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Timer/Counter1 Output Compare Registare B */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Timer/Counter2 Control Register A */ #define TCCR2A _SFR_MEM8(0xB0) #define FOC2A 7 #define WGM20 6 #define COM2A1 5 #define COM2A0 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* Timer/Counter2 Register */ #define TCNT2 _SFR_MEM8(0xB2) /* Timer/Counter2 Output Compare Register */ #define OCR2A _SFR_MEM8(0xB3) /* Asynchronous Status Register */ #define ASSR _SFR_MEM8(0xB6) #define EXCLK 4 #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* USI Control Register */ #define USICR _SFR_MEM8(0xB8) #define USISIE 7 #define USIOIE 6 #define USIWM1 5 #define USIWM0 4 #define USICS1 3 #define USICS0 2 #define USICLK 1 #define USITC 0 /* USI Status Register */ #define USISR _SFR_MEM8(0xB9) #define USISIF 7 #define USIOIF 6 #define USIPF 5 #define USIDC 4 #define USICNT3 3 #define USICNT2 2 #define USICNT1 1 #define USICNT0 0 /* USI Data Register */ #define USIDR _SFR_MEM8(0xBA) /* USART0 Control and Status Register A */ #define UCSR0A _SFR_MEM8(0xC0) #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 /* USART0 Control and Status Register B */ #define UCSR0B _SFR_MEM8(0xC1) #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 /* USART0 Control and Status Register C */ #define UCSR0C _SFR_MEM8(0xC2) #define UMSEL0 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UCSZ00 1 #define UCPOL0 0 /* USART0 Baud Rate Register */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) /* USART0 I/O Data Register */ #define UDR0 _SFR_MEM8(0xC6) /* LCD Control and Status Register A */ #define LCDCRA _SFR_MEM8(0xE4) #define LCDEN 7 #define LCDAB 6 #define LCDIF 4 #define LCDIE 3 #define LCDBD 2 #define LCDCCD 1 #define LCDBL 0 /* LCD Control and Status Register B */ #define LCDCRB _SFR_MEM8(0xE5) #define LCDCS 7 #define LCD2B 6 #define LCDMUX1 5 #define LCDMUX0 4 #define LCDPM2 2 #define LCDPM1 1 #define LCDPM0 0 /* LCD Frame Rate Register */ #define LCDFRR _SFR_MEM8(0xE6) #define LCDPS2 6 #define LCDPS1 5 #define LCDPS0 4 #define LCDCD2 2 #define LCDCD1 1 #define LCDCD0 0 /* LCD Contrast Control Register */ #define LCDCCR _SFR_MEM8(0xE7) #define LCDDC2 7 #define LCDDC1 6 #define LCDDC0 5 #define LCDMDT 4 #define LCDCC3 3 #define LCDCC2 2 #define LCDCC1 1 #define LCDCC0 0 /* LCD Memory mapping */ #define LCDDR0 _SFR_MEM8(0xEC) #define SEG007 7 #define SEG006 6 #define SEG005 5 #define SEG004 4 #define SEG003 3 #define SEG002 2 #define SEG001 1 #define SEG000 0 #define LCDDR1 _SFR_MEM8(0xED) #define SEG015 7 #define SEG014 6 #define SEG013 5 #define SEG012 4 #define SEG011 3 #define SEG010 2 #define SEG009 1 #define SEG008 0 #define LCDDR2 _SFR_MEM8(0xEE) #define SEG023 7 #define SEG022 6 #define SEG021 5 #define SEG020 4 #define SEG019 3 #define SEG018 2 #define SEG017 1 #define SEG016 0 #define LCDDR3 _SFR_MEM8(0xEF) #define SEG024 0 #define LCDDR5 _SFR_MEM8(0xF1) #define SEG107 7 #define SEG106 6 #define SEG105 5 #define SEG104 4 #define SEG103 3 #define SEG102 2 #define SEG101 1 #define SEG100 0 #define LCDDR6 _SFR_MEM8(0xF2) #define SEG115 7 #define SEG114 6 #define SEG113 5 #define SEG112 4 #define SEG111 3 #define SEG110 2 #define SEG109 1 #define SEG108 0 #define LCDDR7 _SFR_MEM8(0xF3) #define SEG123 7 #define SEG122 6 #define SEG121 5 #define SEG120 4 #define SEG119 3 #define SEG118 2 #define SEG117 1 #define SEG116 0 #define LCDDR8 _SFR_MEM8(0xF4) #define SEG124 0 #define LCDDR10 _SFR_MEM8(0xF6) #define SEG207 7 #define SEG206 6 #define SEG205 5 #define SEG204 4 #define SEG203 3 #define SEG202 2 #define SEG201 1 #define SEG200 0 #define LCDDR11 _SFR_MEM8(0xF7) #define SEG215 7 #define SEG214 6 #define SEG213 5 #define SEG212 4 #define SEG211 3 #define SEG210 2 #define SEG209 1 #define SEG208 0 #define LCDDR12 _SFR_MEM8(0xF8) #define SEG223 7 #define SEG222 6 #define SEG221 5 #define SEG220 4 #define SEG219 3 #define SEG218 2 #define SEG217 1 #define SEG216 0 #define LCDDR13 _SFR_MEM8(0xF9) #define SEG224 0 #define LCDDR15 _SFR_MEM8(0xFB) #define SEG307 7 #define SEG306 6 #define SEG305 5 #define SEG304 4 #define SEG303 3 #define SEG302 2 #define SEG301 1 #define SEG300 0 #define LCDDR16 _SFR_MEM8(0xFC) #define SEG315 7 #define SEG314 6 #define SEG313 5 #define SEG312 4 #define SEG311 3 #define SEG310 2 #define SEG309 1 #define SEG308 0 #define LCDDR17 _SFR_MEM8(0xFD) #define SEG323 7 #define SEG322 6 #define SEG321 5 #define SEG320 4 #define SEG319 3 #define SEG318 2 #define SEG317 1 #define SEG316 0 #define LCDDR18 _SFR_MEM8(0xFE) #define SEG324 0 /* LCDDR0-18 */ #define SEG24 0 #define SEG23 7 #define SEG22 6 #define SEG21 5 #define SEG20 4 #define SEG19 3 #define SEG18 2 #define SEG17 1 #define SEG16 0 #define SEG15 7 #define SEG14 6 #define SEG13 5 #define SEG12 4 #define SEG11 3 #define SEG10 2 #define SEG9 1 #define SEG8 0 #define SEG7 7 #define SEG6 6 #define SEG5 5 #define SEG4 4 #define SEG3 3 #define SEG2 2 #define SEG1 1 #define SEG0 0 /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART0, Rx Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) #define SIG_USART_RECV _VECTOR(13) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) #define SIG_USART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define SIG_USART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* LCD Start of Frame */ #define LCD_vect_num 22 #define LCD_vect _VECTOR(22) #define SIG_LCD _VECTOR(22) #define _VECTORS_SIZE 92 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x4FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x05 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_USART_RECV #pragma GCC poison SIG_USART_DATA #pragma GCC poison SIG_USART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #pragma GCC poison SIG_LCD #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM169P_H_ */ avr-libc-1.8.0.orig/include/avr/iom1284p.h0000644000000000000000000005653611732702554014740 0ustar /* Copyright (c) 2007 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom1284p.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iom1284p.h - definitions for ATmega1284P. */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom1284p.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOM1284P_H_ #define _AVR_IOM1284P_H_ 1 /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define TIFR3 _SFR_IO8(0x18) #define TOV3 0 #define OCF3A 1 #define OCF3B 2 #define ICF3 5 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 #define BODS 6 #define JTD 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define RAMPZ _SFR_IO8(0x3B) #define RAMPZ0 0 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRUSART1 4 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define PRR1 _SFR_MEM8(0x65) #define PRTIM3 0 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #define TIMSK3 _SFR_MEM8(0x71) #define TOIE3 0 #define OCIE3A 1 #define OCIE3B 2 #define ICIE3 5 #define PCMSK3 _SFR_MEM8(0x73) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define PCINT27 3 #define PCINT28 4 #define PCINT29 5 #define PCINT30 6 #define PCINT31 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define TCCR3A _SFR_MEM8(0x90) #define WGM30 0 #define WGM31 1 #define COM3B0 4 #define COM3B1 5 #define COM3A0 6 #define COM3A1 7 #define TCCR3B _SFR_MEM8(0x91) #define CS30 0 #define CS31 1 #define CS32 2 #define WGM32 3 #define WGM33 4 #define ICES3 6 #define ICNC3 7 #define TCCR3C _SFR_MEM8(0x92) #define FOC3B 6 #define FOC3A 7 #define TCNT3 _SFR_MEM16(0x94) #define TCNT3L _SFR_MEM8(0x94) #define TCNT3L0 0 #define TCNT3L1 1 #define TCNT3L2 2 #define TCNT3L3 3 #define TCNT3L4 4 #define TCNT3L5 5 #define TCNT3L6 6 #define TCNT3L7 7 #define TCNT3H _SFR_MEM8(0x95) #define TCNT3H0 0 #define TCNT3H1 1 #define TCNT3H2 2 #define TCNT3H3 3 #define TCNT3H4 4 #define TCNT3H5 5 #define TCNT3H6 6 #define TCNT3H7 7 #define ICR3 _SFR_MEM16(0x96) #define ICR3L _SFR_MEM8(0x96) #define ICR3L0 0 #define ICR3L1 1 #define ICR3L2 2 #define ICR3L3 3 #define ICR3L4 4 #define ICR3L5 5 #define ICR3L6 6 #define ICR3L7 7 #define ICR3H _SFR_MEM8(0x97) #define ICR3H0 0 #define ICR3H1 1 #define ICR3H2 2 #define ICR3H3 3 #define ICR3H4 4 #define ICR3H5 5 #define ICR3H6 6 #define ICR3H7 7 #define OCR3A _SFR_MEM16(0x98) #define OCR3AL _SFR_MEM8(0x98) #define OCR3AL0 0 #define OCR3AL1 1 #define OCR3AL2 2 #define OCR3AL3 3 #define OCR3AL4 4 #define OCR3AL5 5 #define OCR3AL6 6 #define OCR3AL7 7 #define OCR3AH _SFR_MEM8(0x99) #define OCR3AH0 0 #define OCR3AH1 1 #define OCR3AH2 2 #define OCR3AH3 3 #define OCR3AH4 4 #define OCR3AH5 5 #define OCR3AH6 6 #define OCR3AH7 7 #define OCR3B _SFR_MEM16(0x9A) #define OCR3BL _SFR_MEM8(0x9A) #define OCR3AL0 0 #define OCR3AL1 1 #define OCR3AL2 2 #define OCR3AL3 3 #define OCR3AL4 4 #define OCR3AL5 5 #define OCR3AL6 6 #define OCR3AL7 7 #define OCR3BH _SFR_MEM8(0x9B) #define OCR3AH0 0 #define OCR3AH1 1 #define OCR3AH2 2 #define OCR3AH3 3 #define OCR3AH4 4 #define OCR3AH5 5 #define OCR3AH6 6 #define OCR3AH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL01 7 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0_0 0 #define UBRR0_1 1 #define UBRR0_2 2 #define UBRR0_3 3 #define UBRR0_4 4 #define UBRR0_5 5 #define UBRR0_6 6 #define UBRR0_7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR0_8 0 #define UBRR0_9 1 #define UBRR0_10 2 #define UBRR0_11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR0_0 0 #define UDR0_1 1 #define UDR0_2 2 #define UDR0_3 3 #define UDR0_4 4 #define UDR0_5 5 #define UDR0_6 6 #define UDR0_7 7 #define UCSR1A _SFR_MEM8(0xC8) #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 #define UCSR1B _SFR_MEM8(0xC9) #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 #define UCSR1C _SFR_MEM8(0xCA) #define UCPOL1 0 #define UCSZ10 1 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1_0 0 #define UBRR1_1 1 #define UBRR1_2 2 #define UBRR1_3 3 #define UBRR1_4 4 #define UBRR1_5 5 #define UBRR1_6 6 #define UBRR1_7 7 #define UBRR1H _SFR_MEM8(0xCD) #define UBRR1_8 0 #define UBRR1_9 1 #define UBRR1_10 2 #define UBRR1_11 3 #define UDR1 _SFR_MEM8(0xCE) #define UDR1_0 0 #define UDR1_1 1 #define UDR1_2 2 #define UDR1_3 3 #define UDR1_4 4 #define UDR1_5 5 #define UDR1_6 6 #define UDR1_7 7 /* Interrupt Vectors */ /* Interrupt Vector 0 is the reset vector. */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define PCINT0_vect_num 4 #define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 5 #define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 6 #define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */ #define PCINT3_vect_num 7 #define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 9 #define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 10 #define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ #define TIMER2_OVF_vect_num 11 #define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 12 #define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 16 #define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 17 #define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 18 #define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 19 #define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ #define USART0_RX_vect_num 20 #define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ #define USART0_UDRE_vect_num 21 #define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ #define USART0_TX_vect_num 22 #define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ #define ADC_vect_num 24 #define ADC_vect _VECTOR(24) /* ADC Conversion Complete */ #define EE_READY_vect_num 25 #define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ #define TWI_vect_num 26 #define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ #define SPM_READY_vect_num 27 #define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ #define USART1_RX_vect_num 28 #define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */ #define USART1_UDRE_vect_num 29 #define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */ #define USART1_TX_vect_num 30 #define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */ #define TIMER3_CAPT_vect_num 31 #define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ #define TIMER3_COMPA_vect_num 32 #define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPB_vect_num 33 #define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ #define TIMER3_OVF_vect_num 34 #define TIMER3_OVF_vect _VECTOR(34) /* Timer/Counter3 Overflow */ #define _VECTORS_SIZE (35 * 4) /* Constants */ #define SPM_PAGESIZE 256 #define RAMSTART (0x100) #define RAMEND 0x40FF /* Last On-Chip SRAM Location */ #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0xFFF #define E2PAGESIZE 8 #define FLASHEND 0x1FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x05 #endif /* _AVR_IOM1284P_H_ */ avr-libc-1.8.0.orig/include/avr/io8515.h0000644000000000000000000003017611732702554014377 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io8515.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io8515.h - definitions for AT90S8515 */ #ifndef _AVR_IO8515_H_ #define _AVR_IO8515_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io8515.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART Baud Rate Register */ #define UBRR _SFR_IO8(0x09) /* UART Control Register */ #define UCR _SFR_IO8(0x0A) /* UART Status Register */ #define USR _SFR_IO8(0x0B) /* UART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter Capture Event */ #define TIMER1_CAPT_vect_num 3 #define TIMER1_CAPT_vect _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 4 #define TIMER1_COMPA_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) /* Timer/Counter1 Compare MatchB */ #define TIMER1_COMPB_vect_num 5 #define TIMER1_COMPB_vect _VECTOR(5) #define SIG_OUTPUT_COMPARE1B _VECTOR(5) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 6 #define TIMER1_OVF_vect _VECTOR(6) #define SIG_OVERFLOW1 _VECTOR(6) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 7 #define TIMER0_OVF_vect _VECTOR(7) #define SIG_OVERFLOW0 _VECTOR(7) /* Serial Transfer Complete */ #define SPI_STC_vect_num 8 #define SPI_STC_vect _VECTOR(8) #define SIG_SPI _VECTOR(8) /* UART, Rx Complete */ #define UART_RX_vect_num 9 #define UART_RX_vect _VECTOR(9) #define SIG_UART_RECV _VECTOR(9) /* UART Data Register Empty */ #define UART_UDRE_vect_num 10 #define UART_UDRE_vect _VECTOR(10) #define SIG_UART_DATA _VECTOR(10) /* UART, Tx Complete */ #define UART_TX_vect_num 11 #define UART_TX_vect _VECTOR(11) #define SIG_UART_TRANS _VECTOR(11) /* Analog Comparator */ #define ANA_COMP_vect_num 12 #define ANA_COMP_vect _VECTOR(12) #define SIG_COMPARATOR _VECTOR(12) #define _VECTORS_SIZE 26 /* The Register Bit names are represented by their bit number (0-7). */ /* General Interrupt MaSK register */ #define INT1 7 #define INT0 6 /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 /* Timer/Counter Interrupt MaSK register */ #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 #define TICIE1 3 #define TOIE0 1 /* Timer/Counter Interrupt Flag register */ #define TOV1 7 #define OCF1A 6 #define OCF1B 5 #define ICF1 3 #define TOV0 1 /* MCU general Control Register */ #define SRE 7 #define SRW 6 #define SE 5 #define SM 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Data Register, Port A */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Data Direction Register, Port A */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Input Pins, Port A */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port C */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Direction Register, Port C */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0x25F /* Last On-Chip SRAM Location */ #define XRAMEND 0xFFFF #define E2END 0x1FF #define E2PAGESIZE 0 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ #define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ #define LFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x01 #endif /* _AVR_IO8515_H_ */ avr-libc-1.8.0.orig/include/avr/iom128rfa1.h0000644000000000000000000051700711732702554015241 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom128rfa1.h 2009 2009-07-01 14:57:41Z joerg_wunsch $ */ /* avr/iom128rfa1.h - definitions for ATmega128RFA1 */ #ifndef _AVR_IOM128RFA1_H_ #define _AVR_IOM128RFA1_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom128rfa1.h" #else # error "Attempt to include more than one file." #endif #include #ifndef __ASSEMBLER__ # define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) # define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) # define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) #endif /* __ASSEMBLER__ */ /* * USAGE: * * simple register assignment: * TIFR1 = 0x17 * subregister assignment: * TIFR1_struct.ocf1a = 1 * (subregister names are converted to small letters) */ /* Port A Input Pins Address */ #define PINA _SFR_IO8(0x00) /* PINA */ #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 /* Port A Data Direction Register */ #define DDRA _SFR_IO8(0x01) /* DDRA */ #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 /* Port A Data Register */ #define PORTA _SFR_IO8(0x02) /* PORTA */ #define PORTA0 0 #define PA0 0 #define PORTA1 1 #define PA1 1 #define PORTA2 2 #define PA2 2 #define PORTA3 3 #define PA3 3 #define PORTA4 4 #define PA4 4 #define PORTA5 5 #define PA5 5 #define PORTA6 6 #define PA6 6 #define PORTA7 7 #define PA7 7 /* Port B Input Pins Address */ #define PINB _SFR_IO8(0x03) /* PINB */ #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 /* Port B Data Direction Register */ #define DDRB _SFR_IO8(0x04) /* DDRB */ #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 /* Port B Data Register */ #define PORTB _SFR_IO8(0x05) /* PORTB */ #define PORTB0 0 #define PB0 0 #define PORTB1 1 #define PB1 1 #define PORTB2 2 #define PB2 2 #define PORTB3 3 #define PB3 3 #define PORTB4 4 #define PB4 4 #define PORTB5 5 #define PB5 5 #define PORTB6 6 #define PB6 6 #define PORTB7 7 #define PB7 7 /* Port C Input Pins Address */ #define PINC _SFR_IO8(0x06) /* PINC */ #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 /* Port C Data Direction Register */ #define DDRC _SFR_IO8(0x07) /* DDRC */ #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 /* Port C Data Register */ #define PORTC _SFR_IO8(0x08) /* PORTC */ #define PORTC0 0 #define PC0 0 #define PORTC1 1 #define PC1 1 #define PORTC2 2 #define PC2 2 #define PORTC3 3 #define PC3 3 #define PORTC4 4 #define PC4 4 #define PORTC5 5 #define PC5 5 #define PORTC6 6 #define PC6 6 #define PORTC7 7 #define PC7 7 /* Port D Input Pins Address */ #define PIND _SFR_IO8(0x09) /* PIND */ #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 /* Port D Data Direction Register */ #define DDRD _SFR_IO8(0x0A) /* DDRD */ #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 /* Port D Data Register */ #define PORTD _SFR_IO8(0x0B) /* PORTD */ #define PORTD0 0 #define PD0 0 #define PORTD1 1 #define PD1 1 #define PORTD2 2 #define PD2 2 #define PORTD3 3 #define PD3 3 #define PORTD4 4 #define PD4 4 #define PORTD5 5 #define PD5 5 #define PORTD6 6 #define PD6 6 #define PORTD7 7 #define PD7 7 /* Port E Input Pins Address */ #define PINE _SFR_IO8(0x0C) /* PINE */ #define PINE0 0 #define PINE1 1 #define PINE2 2 #define PINE3 3 #define PINE4 4 #define PINE5 5 #define PINE6 6 #define PINE7 7 /* Port E Data Direction Register */ #define DDRE _SFR_IO8(0x0D) /* DDRE */ #define DDE0 0 #define DDE1 1 #define DDE2 2 #define DDE3 3 #define DDE4 4 #define DDE5 5 #define DDE6 6 #define DDE7 7 /* Port E Data Register */ #define PORTE _SFR_IO8(0x0E) /* PORTE */ #define PORTE0 0 #define PE0 0 #define PORTE1 1 #define PE1 1 #define PORTE2 2 #define PE2 2 #define PORTE3 3 #define PE3 3 #define PORTE4 4 #define PE4 4 #define PORTE5 5 #define PE5 5 #define PORTE6 6 #define PE6 6 #define PORTE7 7 #define PE7 7 /* Port F Input Pins Address */ #define PINF _SFR_IO8(0x0F) /* PINF */ #define PINF0 0 #define PINF1 1 #define PINF2 2 #define PINF3 3 #define PINF4 4 #define PINF5 5 #define PINF6 6 #define PINF7 7 /* Port F Data Direction Register */ #define DDRF _SFR_IO8(0x10) /* DDRF */ #define DDF0 0 #define DDF1 1 #define DDF2 2 #define DDF3 3 #define DDF4 4 #define DDF5 5 #define DDF6 6 #define DDF7 7 /* Port F Data Register */ #define PORTF _SFR_IO8(0x11) /* PORTF */ #define PORTF0 0 #define PF0 0 #define PORTF1 1 #define PF1 1 #define PORTF2 2 #define PF2 2 #define PORTF3 3 #define PF3 3 #define PORTF4 4 #define PF4 4 #define PORTF5 5 #define PF5 5 #define PORTF6 6 #define PF6 6 #define PORTF7 7 #define PF7 7 /* Port G Input Pins Address */ #define PING _SFR_IO8(0x12) /* PING */ #define PING0 0 #define PING1 1 #define PING2 2 #define PING3 3 #define PING4 4 #define PING5 5 /* Port G Data Direction Register */ #define DDRG _SFR_IO8(0x13) /* DDRG */ #define DDG0 0 #define DDG1 1 #define DDG2 2 #define DDG3 3 #define DDG4 4 #define DDG5 5 /* Port G Data Register */ #define PORTG _SFR_IO8(0x14) /* PORTG */ #define PORTG0 0 #define PG0 0 #define PORTG1 1 #define PG1 1 #define PORTG2 2 #define PG2 2 #define PORTG3 3 #define PG3 3 #define PORTG4 4 #define PG4 4 #define PORTG5 5 #define PG5 5 /* Timer/Counter0 Interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR0 { unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ unsigned int : 5; }; #define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) #endif /* __ASSEMBLER__ */ /* TIFR0 */ #define TOV0 0 #define OCF0A 1 #define OCF0B 2 /* Timer/Counter1 Interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR1 { unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ unsigned int : 1; unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ unsigned int : 2; }; #define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) #endif /* __ASSEMBLER__ */ /* TIFR1 */ #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define OCF1C 3 #define ICF1 5 /* Timer/Counter Interrupt Flag Register */ #define TIFR2 _SFR_IO8(0x17) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR2 { unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ unsigned int : 5; }; #define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) #endif /* __ASSEMBLER__ */ /* TIFR2 */ #define TOV2 0 #define OCF2A 1 #define OCF2B 2 /* Timer/Counter3 Interrupt Flag Register */ #define TIFR3 _SFR_IO8(0x18) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR3 { unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ unsigned int : 1; unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ unsigned int : 2; }; #define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) #endif /* __ASSEMBLER__ */ /* TIFR3 */ #define TOV3 0 #define OCF3A 1 #define OCF3B 2 #define OCF3C 3 #define ICF3 5 /* Timer/Counter4 Interrupt Flag Register */ #define TIFR4 _SFR_IO8(0x19) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR4 { unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ unsigned int : 1; unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ unsigned int : 2; }; #define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) #endif /* __ASSEMBLER__ */ /* TIFR4 */ #define TOV4 0 #define OCF4A 1 #define OCF4B 2 #define OCF4C 3 #define ICF4 5 /* Timer/Counter5 Interrupt Flag Register */ #define TIFR5 _SFR_IO8(0x1A) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIFR5 { unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ unsigned int : 1; unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ unsigned int : 2; }; #define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) #endif /* __ASSEMBLER__ */ /* TIFR5 */ #define TOV5 0 #define OCF5A 1 #define OCF5B 2 #define OCF5C 3 #define ICF5 5 /* Pin Change Interrupt Flag Register */ #define PCIFR _SFR_IO8(0x1B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PCIFR { unsigned int pcif : 3; /* Pin Change Interrupt Flag 2 */ unsigned int : 5; }; #define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) #endif /* __ASSEMBLER__ */ /* PCIFR */ #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_EIFR { unsigned int intf : 8; /* External Interrupt Flag */ }; #define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) #endif /* __ASSEMBLER__ */ /* EIFR */ #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define INTF4 4 #define INTF5 5 #define INTF6 6 #define INTF7 7 /* External Interrupt Mask Register */ #define EIMSK _SFR_IO8(0x1D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_EIMSK { unsigned int intm : 8; /* External Interrupt Request Enable */ }; #define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) #endif /* __ASSEMBLER__ */ /* EIMSK */ #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define INT4 4 #define INT5 5 #define INT6 6 #define INT7 7 /* General Purpose IO Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_GPIOR0 { unsigned int gpior0 : 8; /* General Purpose I/O Register 0 Value */ }; #define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) #endif /* __ASSEMBLER__ */ /* GPIOR0 */ #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_EECR { unsigned int eere : 1; /* EEPROM Read Enable */ unsigned int eepe : 1; /* EEPROM Programming Enable */ unsigned int eempe : 1; /* EEPROM Master Write Enable */ unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ unsigned int eepm : 2; /* EEPROM Programming Mode */ unsigned int : 2; }; #define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) #endif /* __ASSEMBLER__ */ /* EECR */ #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x20) /* EEDR */ #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 /* EEPROM Address Register Bytes */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0x22) /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_GTCCR { unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ unsigned int : 5; unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ }; #define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) #endif /* __ASSEMBLER__ */ /* GTCCR */ #define PSRSYNC 0 #define PSR10 0 #define PSRASY 1 #define PSR2 1 #define TSM 7 /* Timer/Counter0 Control Register A */ #define TCCR0A _SFR_IO8(0x24) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR0A { unsigned int wgm0 : 2; /* Waveform Generation Mode */ unsigned int : 2; unsigned int com0b : 2; /* Compare Match Output B Mode */ unsigned int com0a : 2; /* Compare Match Output A Mode */ }; #define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) #endif /* __ASSEMBLER__ */ /* TCCR0A */ #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 /* Timer/Counter0 Control Register B */ #define TCCR0B _SFR_IO8(0x25) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR0B { unsigned int cs0 : 3; /* Clock Select */ unsigned int wgm02 : 1; /* */ unsigned int : 2; unsigned int foc0b : 1; /* Force Output Compare B */ unsigned int foc0a : 1; /* Force Output Compare A */ }; #define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) #endif /* __ASSEMBLER__ */ /* TCCR0B */ #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 /* Timer/Counter0 Register */ #define TCNT0 _SFR_IO8(0x26) /* TCNT0 */ #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 /* Timer/Counter0 Output Compare Register */ #define OCR0A _SFR_IO8(0x27) /* OCR0A */ #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 /* Timer/Counter0 Output Compare Register B */ #define OCR0B _SFR_IO8(0x28) /* OCR0B */ #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 /* General Purpose IO Register 1 */ #define GPIOR1 _SFR_IO8(0x2A) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_GPIOR1 { unsigned int gpior1 : 8; /* General Purpose I/O Register 1 Value */ }; #define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) #endif /* __ASSEMBLER__ */ /* GPIOR1 */ #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 /* General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x2B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_GPIOR2 { unsigned int gpior2 : 8; /* General Purpose I/O Register 2 Value */ }; #define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) #endif /* __ASSEMBLER__ */ /* GPIOR2 */ #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 /* SPI Control Register */ #define SPCR _SFR_IO8(0x2C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SPCR { unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ unsigned int cpha : 1; /* Clock Phase */ unsigned int cpol : 1; /* Clock polarity */ unsigned int mstr : 1; /* Master/Slave Select */ unsigned int dord : 1; /* Data Order */ unsigned int spe : 1; /* SPI Enable */ unsigned int spie : 1; /* SPI Interrupt Enable */ }; #define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) #endif /* __ASSEMBLER__ */ /* SPCR */ #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 /* SPI Status Register */ #define SPSR _SFR_IO8(0x2D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SPSR { unsigned int spi2x : 1; /* Double SPI Speed Bit */ unsigned int : 5; unsigned int wcol : 1; /* Write Collision Flag */ unsigned int spif : 1; /* SPI Interrupt Flag */ }; #define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) #endif /* __ASSEMBLER__ */ /* SPSR */ #define SPI2X 0 #define WCOL 6 #define SPIF 7 /* SPI Data Register */ #define SPDR _SFR_IO8(0x2E) /* SPDR */ #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 /* Analog Comparator Control And Status Register */ #define ACSR _SFR_IO8(0x30) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_ACSR { unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ unsigned int aco : 1; /* Analog Compare Output */ unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ unsigned int acd : 1; /* Analog Comparator Disable */ }; #define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) #endif /* __ASSEMBLER__ */ /* ACSR */ #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 /* On-Chip Debug Register */ #define OCDR _SFR_IO8(0x31) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_OCDR { unsigned int ocdr : 8; /* On-Chip Debug Register Data */ }; #define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) #endif /* __ASSEMBLER__ */ /* OCDR */ #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SMCR { unsigned int se : 1; /* Sleep Enable */ unsigned int sm : 3; /* Sleep Mode Select bits */ unsigned int : 4; }; #define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) #endif /* __ASSEMBLER__ */ /* SMCR */ #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_MCUSR { unsigned int porf : 1; /* Power-on Reset Flag */ unsigned int extrf : 1; /* External Reset Flag */ unsigned int borf : 1; /* Brown-out Reset Flag */ unsigned int wdrf : 1; /* Watchdog Reset Flag */ unsigned int jtrf : 1; /* JTAG Reset Flag */ unsigned int : 3; }; #define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) #endif /* __ASSEMBLER__ */ /* MCUSR */ #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 /* MCU Control Register */ #define MCUCR _SFR_IO8(0x35) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_MCUCR { unsigned int ivce : 1; /* Interrupt Vector Change Enable */ unsigned int ivsel : 1; /* Interrupt Vector Select */ unsigned int : 2; unsigned int pud : 1; /* Pull-up Disable */ unsigned int : 2; unsigned int jtd : 1; /* JTAG Interface Disable */ }; #define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) #endif /* __ASSEMBLER__ */ /* MCUCR */ #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 /* Store Program Memory Control Register */ #define SPMCSR _SFR_IO8(0x37) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SPMCSR { unsigned int spmen : 1; /* Store Program Memory Enable */ unsigned int pgers : 1; /* Page Erase */ unsigned int pgwrt : 1; /* Page Write */ unsigned int blbset : 1; /* Boot Lock Bit Set */ unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ unsigned int sigrd : 1; /* Signature Row Read */ unsigned int rwwsb : 1; /* Read While Write Section Busy */ unsigned int spmie : 1; /* SPM Interrupt Enable */ }; #define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) #endif /* __ASSEMBLER__ */ /* SPMCSR */ #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 /* Extended Z-pointer Register for ELPM/SPM */ #define RAMPZ _SFR_IO8(0x3B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_RAMPZ { unsigned int rampz : 2; /* Extended Z-Pointer Value */ unsigned int : 6; }; #define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) #endif /* __ASSEMBLER__ */ /* RAMPZ */ #define RAMPZ0 0 #define RAMPZ1 1 /* Stack Pointer */ #define SP _SFR_IO16(0x3D) #define SPL _SFR_IO8(0x3D) #define SPH _SFR_IO8(0x3E) /* Status Register */ #define SREG _SFR_IO8(0x3F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SREG { unsigned int c : 1; /* Carry Flag */ unsigned int z : 1; /* Zero Flag */ unsigned int n : 1; /* Negative Flag */ unsigned int v : 1; /* Two's Complement Overflow Flag */ unsigned int s : 1; /* Sign Bit */ unsigned int h : 1; /* Half Carry Flag */ unsigned int t : 1; /* Bit Copy Storage */ unsigned int i : 1; /* Global Interrupt Enable */ }; #define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) #endif /* __ASSEMBLER__ */ /* SREG */ #define SREG_C 0 #define SREG_Z 1 #define SREG_N 2 #define SREG_V 3 #define SREG_S 4 #define SREG_H 5 #define SREG_T 6 #define SREG_I 7 /* Watchdog Timer Control Register */ #define WDTCSR _SFR_MEM8(0x60) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_WDTCSR { unsigned int wdp : 3; /* Watchdog Timer Prescaler bits */ unsigned int wde : 1; /* Watch Dog Enable */ unsigned int wdce : 1; /* Watchdog Change Enable */ unsigned int : 1; unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ }; #define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) #endif /* __ASSEMBLER__ */ /* WDTCSR */ #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 /* Clock Prescale Register */ #define CLKPR _SFR_MEM8(0x61) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_CLKPR { unsigned int clkps : 4; /* Clock Prescaler Select Bits */ unsigned int : 3; unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ }; #define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) #endif /* __ASSEMBLER__ */ /* CLKPR */ #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Power Reduction Register 2 */ #define PRR2 _SFR_MEM8(0x63) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PRR2 { unsigned int prram : 4; /* Power Reduction SRAM 3 */ unsigned int : 4; }; #define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) #endif /* __ASSEMBLER__ */ /* PRR2 */ #define PRRAM0 0 #define PRRAM1 1 #define PRRAM2 2 #define PRRAM3 3 /* Power Reduction Register0 */ #define PRR0 _SFR_MEM8(0x64) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PRR0 { unsigned int pradc : 1; /* Power Reduction ADC */ unsigned int prusart0 : 1; /* Power Reduction USART */ unsigned int prspi : 1; /* Power Reduction Serial Peripheral Interface */ unsigned int prtim1 : 1; /* Power Reduction Timer/Counter1 */ unsigned int prpga : 1; /* Power Reduction PGA */ unsigned int prtim0 : 1; /* Power Reduction Timer/Counter0 */ unsigned int prtim2 : 1; /* Power Reduction Timer/Counter2 */ unsigned int prtwi : 1; /* Power Reduction TWI */ }; #define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0) #endif /* __ASSEMBLER__ */ /* PRR0 */ #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRPGA 4 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 /* Power Reduction Register 1 */ #define PRR1 _SFR_MEM8(0x65) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PRR1 { unsigned int prusart : 3; /* Reserved */ unsigned int prtim3 : 1; /* Power Reduction Timer/Counter3 */ unsigned int prtim4 : 1; /* Power Reduction Timer/Counter4 */ unsigned int prtim5 : 1; /* Power Reduction Timer/Counter5 */ unsigned int prtrx24 : 1; /* Power Reduction Transceiver */ unsigned int : 1; }; #define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1) #endif /* __ASSEMBLER__ */ /* PRR1 */ #define PRUSART1 0 #define PRUSART2 1 #define PRUSART3 2 #define PRTIM3 3 #define PRTIM4 4 #define PRTIM5 5 #define PRTRX24 6 /* Oscillator Calibration Value */ #define OSCCAL _SFR_MEM8(0x66) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_OSCCAL { unsigned int cal : 8; /* Oscillator Calibration Tuning Value */ }; #define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL) #endif /* __ASSEMBLER__ */ /* OSCCAL */ #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 /* Reference Voltage Calibration Register */ #define BGCR _SFR_MEM8(0x67) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_BGCR { unsigned int bgcal : 3; /* Coarse Calibration Bits */ unsigned int bgcal_fine : 4; /* Fine Calibration Bits */ unsigned int : 1; }; #define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR) #endif /* __ASSEMBLER__ */ /* BGCR */ #define BGCAL0 0 #define BGCAL1 1 #define BGCAL2 2 #define BGCAL_FINE0 3 #define BGCAL_FINE1 4 #define BGCAL_FINE2 5 #define BGCAL_FINE3 6 /* Pin Change Interrupt Control Register */ #define PCICR _SFR_MEM8(0x68) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PCICR { unsigned int pcie : 3; /* Pin Change Interrupt Enable 2 */ unsigned int : 5; }; #define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR) #endif /* __ASSEMBLER__ */ /* PCICR */ #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x69) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_EICRA { unsigned int isc0 : 2; /* External Interrupt 0 Sense Control Bit */ unsigned int isc1 : 2; /* External Interrupt 1 Sense Control Bit */ unsigned int isc2 : 2; /* External Interrupt 2 Sense Control Bit */ unsigned int isc3 : 2; /* External Interrupt 3 Sense Control Bit */ }; #define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA) #endif /* __ASSEMBLER__ */ /* EICRA */ #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 /* External Interrupt Control Register B */ #define EICRB _SFR_MEM8(0x6A) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_EICRB { unsigned int isc4 : 2; /* External Interrupt 4 Sense Control Bit */ unsigned int isc5 : 2; /* External Interrupt 5 Sense Control Bit */ unsigned int isc6 : 2; /* External Interrupt 6 Sense Control Bit */ unsigned int isc7 : 2; /* External Interrupt 7 Sense Control Bit */ }; #define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB) #endif /* __ASSEMBLER__ */ /* EICRB */ #define ISC40 0 #define ISC41 1 #define ISC50 2 #define ISC51 3 #define ISC60 4 #define ISC61 5 #define ISC70 6 #define ISC71 7 /* Pin Change Mask Register 0 */ #define PCMSK0 _SFR_MEM8(0x6B) /* PCMSK0 */ #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 /* Pin Change Mask Register 1 */ #define PCMSK1 _SFR_MEM8(0x6C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PCMSK1 { unsigned int pcint : 2; /* Pin Change Enable Mask */ unsigned int pcint1 : 6; /* Pin Change Enable Mask */ }; #define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1) #endif /* __ASSEMBLER__ */ /* PCMSK1 */ #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 /* Pin Change Mask Register 2 */ #define PCMSK2 _SFR_MEM8(0x6D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PCMSK2 { unsigned int pcint1 : 4; /* Pin Change Enable Mask */ unsigned int pcint2 : 4; /* Pin Change Enable Mask */ }; #define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2) #endif /* __ASSEMBLER__ */ /* PCMSK2 */ #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 /* Timer/Counter0 Interrupt Mask Register */ #define TIMSK0 _SFR_MEM8(0x6E) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIMSK0 { unsigned int toie0 : 1; /* Timer/Counter0 Overflow Interrupt Enable */ unsigned int ocie0a : 1; /* Timer/Counter0 Output Compare Match A Interrupt Enable */ unsigned int ocie0b : 1; /* Timer/Counter0 Output Compare Match B Interrupt Enable */ unsigned int : 5; }; #define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0) #endif /* __ASSEMBLER__ */ /* TIMSK0 */ #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 /* Timer/Counter1 Interrupt Mask Register */ #define TIMSK1 _SFR_MEM8(0x6F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIMSK1 { unsigned int toie1 : 1; /* Timer/Counter1 Overflow Interrupt Enable */ unsigned int ocie1a : 1; /* Timer/Counter1 Output Compare A Match Interrupt Enable */ unsigned int ocie1b : 1; /* Timer/Counter1 Output Compare B Match Interrupt Enable */ unsigned int ocie1c : 1; /* Timer/Counter1 Output Compare C Match Interrupt Enable */ unsigned int : 1; unsigned int icie1 : 1; /* Timer/Counter1 Input Capture Interrupt Enable */ unsigned int : 2; }; #define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1) #endif /* __ASSEMBLER__ */ /* TIMSK1 */ #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define OCIE1C 3 #define ICIE1 5 /* Timer/Counter Interrupt Mask register */ #define TIMSK2 _SFR_MEM8(0x70) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIMSK2 { unsigned int toie2 : 1; /* Timer/Counter2 Overflow Interrupt Enable */ unsigned int ocie2a : 1; /* Timer/Counter2 Output Compare Match A Interrupt Enable */ unsigned int ocie2b : 1; /* Timer/Counter2 Output Compare Match B Interrupt Enable */ unsigned int : 5; }; #define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2) #endif /* __ASSEMBLER__ */ /* TIMSK2 */ #define TOIE2 0 #define TOIE2A 0 #define OCIE2A 1 #define OCIE2B 2 /* Timer/Counter3 Interrupt Mask Register */ #define TIMSK3 _SFR_MEM8(0x71) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIMSK3 { unsigned int toie3 : 1; /* Timer/Counter3 Overflow Interrupt Enable */ unsigned int ocie3a : 1; /* Timer/Counter3 Output Compare A Match Interrupt Enable */ unsigned int ocie3b : 1; /* Timer/Counter3 Output Compare B Match Interrupt Enable */ unsigned int ocie3c : 1; /* Timer/Counter3 Output Compare C Match Interrupt Enable */ unsigned int : 1; unsigned int icie3 : 1; /* Timer/Counter3 Input Capture Interrupt Enable */ unsigned int : 2; }; #define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3) #endif /* __ASSEMBLER__ */ /* TIMSK3 */ #define TOIE3 0 #define OCIE3A 1 #define OCIE3B 2 #define OCIE3C 3 #define ICIE3 5 /* Timer/Counter4 Interrupt Mask Register */ #define TIMSK4 _SFR_MEM8(0x72) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIMSK4 { unsigned int toie4 : 1; /* Timer/Counter4 Overflow Interrupt Enable */ unsigned int ocie4a : 1; /* Timer/Counter4 Output Compare A Match Interrupt Enable */ unsigned int ocie4b : 1; /* Timer/Counter4 Output Compare B Match Interrupt Enable */ unsigned int ocie4c : 1; /* Timer/Counter4 Output Compare C Match Interrupt Enable */ unsigned int : 1; unsigned int icie4 : 1; /* Timer/Counter4 Input Capture Interrupt Enable */ unsigned int : 2; }; #define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4) #endif /* __ASSEMBLER__ */ /* TIMSK4 */ #define TOIE4 0 #define OCIE4A 1 #define OCIE4B 2 #define OCIE4C 3 #define ICIE4 5 /* Timer/Counter5 Interrupt Mask Register */ #define TIMSK5 _SFR_MEM8(0x73) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TIMSK5 { unsigned int toie5 : 1; /* Timer/Counter5 Overflow Interrupt Enable */ unsigned int ocie5a : 1; /* Timer/Counter5 Output Compare A Match Interrupt Enable */ unsigned int ocie5b : 1; /* Timer/Counter5 Output Compare B Match Interrupt Enable */ unsigned int ocie5c : 1; /* Timer/Counter5 Output Compare C Match Interrupt Enable */ unsigned int : 1; unsigned int icie5 : 1; /* Timer/Counter5 Input Capture Interrupt Enable */ unsigned int : 2; }; #define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5) #endif /* __ASSEMBLER__ */ /* TIMSK5 */ #define TOIE5 0 #define OCIE5A 1 #define OCIE5B 2 #define OCIE5C 3 #define ICIE5 5 /* Flash Extended-Mode Control-Register */ #define NEMCR _SFR_MEM8(0x75) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_NEMCR { unsigned int : 4; unsigned int aeam : 2; /* Address for Extended Address Mode of Extra Rows */ unsigned int eneam : 1; /* Enable Extended Address Mode for Extra Rows */ unsigned int : 1; }; #define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR) #endif /* __ASSEMBLER__ */ /* NEMCR */ #define AEAM0 4 #define AEAM1 5 #define ENEAM 6 /* The ADC Control and Status Register C */ #define ADCSRC _SFR_MEM8(0x77) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_ADCSRC { unsigned int adsut : 5; /* ADC Start-up Time */ unsigned int res0 : 1; /* Reserved */ unsigned int adtht : 2; /* ADC Track-and-Hold Time */ }; #define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC) #endif /* __ASSEMBLER__ */ /* ADCSRC */ #define ADSUT0 0 #define ADSUT1 1 #define ADSUT2 2 #define ADSUT3 3 #define ADSUT4 4 #define ADTHT0 6 #define ADTHT1 7 /* ADC Data Register Bytes */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #endif /* __ASSEMBLER__ */ #define ADCW _SFR_MEM16(0x78) #define ADCWL _SFR_MEM8(0x78) #define ADCWH _SFR_MEM8(0x79) /* The ADC Control and Status Register A */ #define ADCSRA _SFR_MEM8(0x7A) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_ADCSRA { unsigned int adps : 3; /* ADC Prescaler Select Bits */ unsigned int adie : 1; /* ADC Interrupt Enable */ unsigned int adif : 1; /* ADC Interrupt Flag */ unsigned int adate : 1; /* ADC Auto Trigger Enable */ unsigned int adsc : 1; /* ADC Start Conversion */ unsigned int aden : 1; /* ADC Enable */ }; #define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA) #endif /* __ASSEMBLER__ */ /* ADCSRA */ #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 /* ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x7B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_ADCSRB { unsigned int adts : 3; /* ADC Auto Trigger Source */ unsigned int mux5 : 1; /* Analog Channel and Gain Selection Bits */ unsigned int acch : 1; /* Analog Channel Change */ unsigned int refok : 1; /* Reference Voltage OK */ unsigned int acme : 1; /* Analog Comparator Multiplexer Enable */ unsigned int avddok : 1; /* AVDD Supply Voltage OK */ }; #define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB) #endif /* __ASSEMBLER__ */ /* ADCSRB */ #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define MUX5 3 #define ACCH 4 #define REFOK 5 #define ACME 6 #define AVDDOK 7 /* The ADC Multiplexer Selection Register */ #define ADMUX _SFR_MEM8(0x7C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_ADMUX { unsigned int mux : 5; /* Analog Channel and Gain Selection Bits */ unsigned int adlar : 1; /* ADC Left Adjust Result */ unsigned int refs : 2; /* Reference Selection Bits */ }; #define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX) #endif /* __ASSEMBLER__ */ /* ADMUX */ #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Digital Input Disable Register 2 */ #define DIDR2 _SFR_MEM8(0x7D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_DIDR2 { unsigned int adc8d : 1; /* Reserved Bits */ unsigned int adc9d : 1; /* Reserved Bits */ unsigned int adc10d : 1; /* Reserved Bits */ unsigned int adc11d : 1; /* Reserved Bits */ unsigned int adc12d : 1; /* Reserved Bits */ unsigned int adc13d : 1; /* Reserved Bits */ unsigned int adc14d : 1; /* Reserved Bits */ unsigned int adc15d : 1; /* Reserved Bits */ }; #define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2) #endif /* __ASSEMBLER__ */ /* DIDR2 */ #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define ADC11D 3 #define ADC12D 4 #define ADC13D 5 #define ADC14D 6 #define ADC15D 7 /* Digital Input Disable Register 0 */ #define DIDR0 _SFR_MEM8(0x7E) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_DIDR0 { unsigned int adc0d : 1; /* Disable ADC7:0 Digital Input */ unsigned int adc1d : 1; /* Disable ADC7:0 Digital Input */ unsigned int adc2d : 1; /* Disable ADC7:0 Digital Input */ unsigned int adc3d : 1; /* Disable ADC7:0 Digital Input */ unsigned int adc4d : 1; /* Disable ADC7:0 Digital Input */ unsigned int adc5d : 1; /* Disable ADC7:0 Digital Input */ unsigned int adc6d : 1; /* Disable ADC7:0 Digital Input */ unsigned int adc7d : 1; /* Disable ADC7:0 Digital Input */ }; #define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0) #endif /* __ASSEMBLER__ */ /* DIDR0 */ #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 /* Digital Input Disable Register 1 */ #define DIDR1 _SFR_MEM8(0x7F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_DIDR1 { unsigned int ain0d : 1; /* AIN0 Digital Input Disable */ unsigned int ain1d : 1; /* AIN1 Digital Input Disable */ unsigned int : 6; }; #define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1) #endif /* __ASSEMBLER__ */ /* DIDR1 */ #define AIN0D 0 #define AIN1D 1 /* Timer/Counter1 Control Register A */ #define TCCR1A _SFR_MEM8(0x80) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR1A { unsigned int wgm1 : 2; /* Waveform Generation Mode */ unsigned int com1c : 2; /* Compare Output Mode for Channel C */ unsigned int com1b : 2; /* Compare Output Mode for Channel B */ unsigned int com1a : 2; /* Compare Output Mode for Channel A */ }; #define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A) #endif /* __ASSEMBLER__ */ /* TCCR1A */ #define WGM10 0 #define WGM11 1 #define COM1C0 2 #define COM1C1 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 /* Timer/Counter1 Control Register B */ #define TCCR1B _SFR_MEM8(0x81) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR1B { unsigned int cs1 : 3; /* Clock Select */ unsigned int wgm1 : 2; /* Waveform Generation Mode */ unsigned int : 1; unsigned int ices1 : 1; /* Input Capture 1 Edge Select */ unsigned int icnc1 : 1; /* Input Capture 1 Noise Canceller */ }; #define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B) #endif /* __ASSEMBLER__ */ /* TCCR1B */ #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 /* Timer/Counter1 Control Register C */ #define TCCR1C _SFR_MEM8(0x82) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR1C { unsigned int : 5; unsigned int foc1c : 1; /* Force Output Compare for Channel C */ unsigned int foc1b : 1; /* Force Output Compare for Channel B */ unsigned int foc1a : 1; /* Force Output Compare for Channel A */ }; #define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C) #endif /* __ASSEMBLER__ */ /* TCCR1C */ #define FOC1C 5 #define FOC1B 6 #define FOC1A 7 /* Timer/Counter1 Bytes */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Timer/Counter1 Input Capture Register Bytes */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Timer/Counter1 Output Compare Register A Bytes */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Timer/Counter1 Output Compare Register B Bytes */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Timer/Counter1 Output Compare Register C Bytes */ #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CH _SFR_MEM8(0x8D) /* Timer/Counter3 Control Register A */ #define TCCR3A _SFR_MEM8(0x90) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR3A { unsigned int wgm3 : 2; /* Waveform Generation Mode */ unsigned int com3c : 2; /* Compare Output Mode for Channel C */ unsigned int com3b : 2; /* Compare Output Mode for Channel B */ unsigned int com3a : 2; /* Compare Output Mode for Channel A */ }; #define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A) #endif /* __ASSEMBLER__ */ /* TCCR3A */ #define WGM30 0 #define WGM31 1 #define COM3C0 2 #define COM3C1 3 #define COM3B0 4 #define COM3B1 5 #define COM3A0 6 #define COM3A1 7 /* Timer/Counter3 Control Register B */ #define TCCR3B _SFR_MEM8(0x91) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR3B { unsigned int cs3 : 3; /* Clock Select */ unsigned int wgm3 : 2; /* Waveform Generation Mode */ unsigned int : 1; unsigned int ices3 : 1; /* Input Capture 3 Edge Select */ unsigned int icnc3 : 1; /* Input Capture 3 Noise Canceller */ }; #define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B) #endif /* __ASSEMBLER__ */ /* TCCR3B */ #define CS30 0 #define CS31 1 #define CS32 2 #define WGM32 3 #define WGM33 4 #define ICES3 6 #define ICNC3 7 /* Timer/Counter3 Control Register C */ #define TCCR3C _SFR_MEM8(0x92) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR3C { unsigned int : 5; unsigned int foc3c : 1; /* Force Output Compare for Channel C */ unsigned int foc3b : 1; /* Force Output Compare for Channel B */ unsigned int foc3a : 1; /* Force Output Compare for Channel A */ }; #define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C) #endif /* __ASSEMBLER__ */ /* TCCR3C */ #define FOC3C 5 #define FOC3B 6 #define FOC3A 7 /* Timer/Counter3 Bytes */ #define TCNT3 _SFR_MEM16(0x94) #define TCNT3L _SFR_MEM8(0x94) #define TCNT3H _SFR_MEM8(0x95) /* Timer/Counter3 Input Capture Register Bytes */ #define ICR3 _SFR_MEM16(0x96) #define ICR3L _SFR_MEM8(0x96) #define ICR3H _SFR_MEM8(0x97) /* Timer/Counter3 Output Compare Register A Bytes */ #define OCR3A _SFR_MEM16(0x98) #define OCR3AL _SFR_MEM8(0x98) #define OCR3AH _SFR_MEM8(0x99) /* Timer/Counter3 Output Compare Register B Bytes */ #define OCR3B _SFR_MEM16(0x9A) #define OCR3BL _SFR_MEM8(0x9A) #define OCR3BH _SFR_MEM8(0x9B) /* Timer/Counter3 Output Compare Register C Bytes */ #define OCR3C _SFR_MEM16(0x9C) #define OCR3CL _SFR_MEM8(0x9C) #define OCR3CH _SFR_MEM8(0x9D) /* Timer/Counter4 Control Register A */ #define TCCR4A _SFR_MEM8(0xA0) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR4A { unsigned int wgm4 : 2; /* Waveform Generation Mode */ unsigned int com4c : 2; /* Compare Output Mode for Channel C */ unsigned int com4b : 2; /* Compare Output Mode for Channel B */ unsigned int com4a : 2; /* Compare Output Mode for Channel A */ }; #define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A) #endif /* __ASSEMBLER__ */ /* TCCR4A */ #define WGM40 0 #define WGM41 1 #define COM4C0 2 #define COM4C1 3 #define COM4B0 4 #define COM4B1 5 #define COM4A0 6 #define COM4A1 7 /* Timer/Counter4 Control Register B */ #define TCCR4B _SFR_MEM8(0xA1) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR4B { unsigned int cs4 : 3; /* Clock Select */ unsigned int wgm4 : 2; /* Waveform Generation Mode */ unsigned int : 1; unsigned int ices4 : 1; /* Input Capture 4 Edge Select */ unsigned int icnc4 : 1; /* Input Capture 4 Noise Canceller */ }; #define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B) #endif /* __ASSEMBLER__ */ /* TCCR4B */ #define CS40 0 #define CS41 1 #define CS42 2 #define WGM42 3 #define WGM43 4 #define ICES4 6 #define ICNC4 7 /* Timer/Counter4 Control Register C */ #define TCCR4C _SFR_MEM8(0xA2) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR4C { unsigned int : 5; unsigned int foc4c : 1; /* Force Output Compare for Channel C */ unsigned int foc4b : 1; /* Force Output Compare for Channel B */ unsigned int foc4a : 1; /* Force Output Compare for Channel A */ }; #define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C) #endif /* __ASSEMBLER__ */ /* TCCR4C */ #define FOC4C 5 #define FOC4B 6 #define FOC4A 7 /* Timer/Counter4 Bytes */ #define TCNT4 _SFR_MEM16(0xA4) #define TCNT4L _SFR_MEM8(0xA4) #define TCNT4H _SFR_MEM8(0xA5) /* Timer/Counter4 Input Capture Register Bytes */ #define ICR4 _SFR_MEM16(0xA6) #define ICR4L _SFR_MEM8(0xA6) #define ICR4H _SFR_MEM8(0xA7) /* Timer/Counter4 Output Compare Register A Bytes */ #define OCR4A _SFR_MEM16(0xA8) #define OCR4AL _SFR_MEM8(0xA8) #define OCR4AH _SFR_MEM8(0xA9) /* Timer/Counter4 Output Compare Register B Bytes */ #define OCR4B _SFR_MEM16(0xAA) #define OCR4BL _SFR_MEM8(0xAA) #define OCR4BH _SFR_MEM8(0xAB) /* Timer/Counter4 Output Compare Register C Bytes */ #define OCR4C _SFR_MEM16(0xAC) #define OCR4CL _SFR_MEM8(0xAC) #define OCR4CH _SFR_MEM8(0xAD) /* Timer/Counter2 Control Register A */ #define TCCR2A _SFR_MEM8(0xB0) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR2A { unsigned int wgm2 : 2; /* Waveform Generation Mode */ unsigned int : 2; unsigned int com2b : 2; /* Compare Match Output B Mode */ unsigned int com2a : 2; /* Compare Match Output A Mode */ }; #define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A) #endif /* __ASSEMBLER__ */ /* TCCR2A */ #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 /* Timer/Counter2 Control Register B */ #define TCCR2B _SFR_MEM8(0xB1) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR2B { unsigned int cs2 : 3; /* Clock Select */ unsigned int wgm22 : 1; /* Waveform Generation Mode */ unsigned int : 2; unsigned int foc2b : 1; /* Force Output Compare B */ unsigned int foc2a : 1; /* Force Output Compare A */ }; #define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B) #endif /* __ASSEMBLER__ */ /* TCCR2B */ #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 /* Timer/Counter2 */ #define TCNT2 _SFR_MEM8(0xB2) /* TCNT2 */ #define TCNT20 0 #define TCNT21 1 #define TCNT22 2 #define TCNT23 3 #define TCNT24 4 #define TCNT25 5 #define TCNT26 6 #define TCNT27 7 /* Timer/Counter2 Output Compare Register A */ #define OCR2A _SFR_MEM8(0xB3) /* OCR2A */ #define OCR2A0 0 #define OCR2A1 1 #define OCR2A2 2 #define OCR2A3 3 #define OCR2A4 4 #define OCR2A5 5 #define OCR2A6 6 #define OCR2A7 7 /* Timer/Counter2 Output Compare Register B */ #define OCR2B _SFR_MEM8(0xB4) /* OCR2B */ #define OCR2B0 0 #define OCR2B1 1 #define OCR2B2 2 #define OCR2B3 3 #define OCR2B4 4 #define OCR2B5 5 #define OCR2B6 6 #define OCR2B7 7 /* Asynchronous Status Register */ #define ASSR _SFR_MEM8(0xB6) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_ASSR { unsigned int tcr2bub : 1; /* Timer/Counter2 Control Register B Update Busy */ unsigned int tcr2aub : 1; /* Timer/Counter2 Control Register A Update Busy */ unsigned int ocr2bub : 1; /* Timer/Counter2 Output Compare Register B Update Busy */ unsigned int ocr2aub : 1; /* Timer/Counter2 Output Compare Register A Update Busy */ unsigned int tcn2ub : 1; /* Timer/Counter2 Update Busy */ unsigned int as2 : 1; /* Timer/Counter2 Asynchronous Mode */ unsigned int exclk : 1; /* Enable External Clock Input */ unsigned int exclkamr : 1; /* Enable External Clock Input for AMR */ }; #define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR) #endif /* __ASSEMBLER__ */ /* ASSR */ #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define EXCLKAMR 7 /* TWI Bit Rate Register */ #define TWBR _SFR_MEM8(0xB8) /* TWBR */ #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 /* TWI Status Register */ #define TWSR _SFR_MEM8(0xB9) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TWSR { unsigned int twps : 2; /* TWI Prescaler Bits */ unsigned int : 1; unsigned int tws : 5; /* TWI Status */ }; #define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR) #endif /* __ASSEMBLER__ */ /* TWSR */ #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 /* TWI (Slave) Address Register */ #define TWAR _SFR_MEM8(0xBA) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TWAR { unsigned int twgce : 1; /* TWI General Call Recognition Enable Bit */ unsigned int twa : 7; /* TWI (Slave) Address */ }; #define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR) #endif /* __ASSEMBLER__ */ /* TWAR */ #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 /* TWI Data Register */ #define TWDR _SFR_MEM8(0xBB) /* TWDR */ #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 /* TWI Control Register */ #define TWCR _SFR_MEM8(0xBC) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TWCR { unsigned int twie : 1; /* TWI Interrupt Enable */ unsigned int : 1; unsigned int twen : 1; /* TWI Enable Bit */ unsigned int twwc : 1; /* TWI Write Collision Flag */ unsigned int twsto : 1; /* TWI STOP Condition Bit */ unsigned int twsta : 1; /* TWI START Condition Bit */ unsigned int twea : 1; /* TWI Enable Acknowledge Bit */ unsigned int twint : 1; /* TWI Interrupt Flag */ }; #define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR) #endif /* __ASSEMBLER__ */ /* TWCR */ #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 /* TWI (Slave) Address Mask Register */ #define TWAMR _SFR_MEM8(0xBD) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TWAMR { unsigned int : 1; unsigned int twam : 7; /* TWI Address Mask */ }; #define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR) #endif /* __ASSEMBLER__ */ /* TWAMR */ #define TWAM0 1 #define TWAMR0 1 #define TWAM1 2 #define TWAMR1 2 #define TWAM2 3 #define TWAMR2 3 #define TWAM3 4 #define TWAMR3 4 #define TWAM4 5 #define TWAMR4 5 #define TWAM5 6 #define TWAMR5 6 #define TWAM6 7 #define TWAMR6 7 /* USART0 Control and Status Register A */ #define UCSR0A _SFR_MEM8(0xC0) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_UCSR0A { unsigned int mpcm0 : 1; /* Multi-processor Communication Mode */ unsigned int u2x0 : 1; /* Double the USART Transmission Speed */ unsigned int upe0 : 1; /* USART Parity Error */ unsigned int dor0 : 1; /* Data OverRun */ unsigned int fe0 : 1; /* Frame Error */ unsigned int udre0 : 1; /* USART Data Register Empty */ unsigned int txc0 : 1; /* USART Transmit Complete */ unsigned int rxc0 : 1; /* USART Receive Complete */ }; #define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A) #endif /* __ASSEMBLER__ */ /* UCSR0A */ #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 /* USART0 Control and Status Register B */ #define UCSR0B _SFR_MEM8(0xC1) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_UCSR0B { unsigned int txb80 : 1; /* Transmit Data Bit 8 */ unsigned int rxb80 : 1; /* Receive Data Bit 8 */ unsigned int ucsz02 : 1; /* Character Size */ unsigned int txen0 : 1; /* Transmitter Enable */ unsigned int rxen0 : 1; /* Receiver Enable */ unsigned int udrie0 : 1; /* USART Data Register Empty Interrupt Enable */ unsigned int txcie0 : 1; /* TX Complete Interrupt Enable */ unsigned int rxcie0 : 1; /* RX Complete Interrupt Enable */ }; #define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B) #endif /* __ASSEMBLER__ */ /* UCSR0B */ #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 /* USART0 Control and Status Register C */ #define UCSR0C _SFR_MEM8(0xC2) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_UCSR0C { unsigned int ucpol0 : 1; /* Clock Polarity */ unsigned int ucsz0 : 2; /* Character Size */ unsigned int ucpha0 : 1; /* Clock Phase */ unsigned int udord0 : 1; /* Data Order */ unsigned int usbs0 : 1; /* Stop Bit Select */ unsigned int upm0 : 2; /* Parity Mode */ unsigned int umsel0 : 2; /* USART Mode Select */ }; #define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C) #endif /* __ASSEMBLER__ */ /* UCSR0C */ #define UCPOL0 0 #define UCPHA0 1 #define UCPHA0 1 #define UCSZ00 1 #define UDORD0 2 #define UDORD0 2 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL0 6 #define UMSEL01 7 #define UMSEL1 7 /* USART0 Baud Rate Register Bytes */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) /* USART0 I/O Data Register */ #define UDR0 _SFR_MEM8(0xC6) /* UDR0 */ #define UDR00 0 #define UDR01 1 #define UDR02 2 #define UDR03 3 #define UDR04 4 #define UDR05 5 #define UDR06 6 #define UDR07 7 /* USART1 Control and Status Register A */ #define UCSR1A _SFR_MEM8(0xC8) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_UCSR1A { unsigned int mpcm1 : 1; /* Multi-processor Communication Mode */ unsigned int u2x1 : 1; /* Double the USART Transmission Speed */ unsigned int upe1 : 1; /* USART Parity Error */ unsigned int dor1 : 1; /* Data OverRun */ unsigned int fe1 : 1; /* Frame Error */ unsigned int udre1 : 1; /* USART Data Register Empty */ unsigned int txc1 : 1; /* USART Transmit Complete */ unsigned int rxc1 : 1; /* USART Receive Complete */ }; #define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A) #endif /* __ASSEMBLER__ */ /* UCSR1A */ #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 /* USART1 Control and Status Register B */ #define UCSR1B _SFR_MEM8(0xC9) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_UCSR1B { unsigned int txb81 : 1; /* Transmit Data Bit 8 */ unsigned int rxb81 : 1; /* Receive Data Bit 8 */ unsigned int ucsz12 : 1; /* Character Size */ unsigned int txen1 : 1; /* Transmitter Enable */ unsigned int rxen1 : 1; /* Receiver Enable */ unsigned int udrie1 : 1; /* USART Data Register Empty Interrupt Enable */ unsigned int txcie1 : 1; /* TX Complete Interrupt Enable */ unsigned int rxcie1 : 1; /* RX Complete Interrupt Enable */ }; #define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B) #endif /* __ASSEMBLER__ */ /* UCSR1B */ #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 /* USART1 Control and Status Register C */ #define UCSR1C _SFR_MEM8(0xCA) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_UCSR1C { unsigned int ucpol1 : 1; /* Clock Polarity */ unsigned int ucsz1 : 2; /* Character Size */ unsigned int ucpha1 : 1; /* Clock Phase */ unsigned int udord1 : 1; /* Data Order */ unsigned int usbs1 : 1; /* Stop Bit Select */ unsigned int upm1 : 2; /* Parity Mode */ unsigned int umsel1 : 2; /* USART Mode Select */ }; #define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C) #endif /* __ASSEMBLER__ */ /* UCSR1C */ #define UCPOL1 0 #define UCPHA1 1 #define UCPHA1 1 #define UCSZ10 1 #define UDORD1 2 #define UDORD1 2 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 /* USART1 Baud Rate Register Bytes */ #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1H _SFR_MEM8(0xCD) /* USART1 I/O Data Register */ #define UDR1 _SFR_MEM8(0xCE) /* UDR1 */ #define UDR10 0 #define UDR11 1 #define UDR12 2 #define UDR13 3 #define UDR14 4 #define UDR15 5 #define UDR16 6 #define UDR17 7 /* Symbol Counter Control Register 0 */ #define SCCR0 _SFR_MEM8(0xDC) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCCR0 { unsigned int sccmp : 3; /* Symbol Counter Compare Unit 3 Mode select */ unsigned int sctse : 1; /* Symbol Counter Automatic Timestamping enable */ unsigned int sccksel : 1; /* Symbol Counter Clock Source select */ unsigned int scen : 1; /* Symbol Counter enable */ unsigned int scmbts : 1; /* Manual Beacon Timestamp */ unsigned int scres : 1; /* Symbol Counter Synchronization */ }; #define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0) #endif /* __ASSEMBLER__ */ /* SCCR0 */ #define SCCMP1 0 #define SCCMP2 1 #define SCCMP3 2 #define SCTSE 3 #define SCCKSEL 4 #define SCEN 5 #define SCMBTS 6 #define SCRES 7 /* Symbol Counter Control Register 1 */ #define SCCR1 _SFR_MEM8(0xDD) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCCR1 { unsigned int scenbo : 1; /* Backoff Slot Counter enable */ unsigned int : 7; }; #define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1) #endif /* __ASSEMBLER__ */ /* SCCR1 */ #define SCENBO 0 /* Symbol Counter Status Register */ #define SCSR _SFR_MEM8(0xDE) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCSR { unsigned int scbsy : 1; /* Symbol Counter busy */ unsigned int : 7; }; #define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR) #endif /* __ASSEMBLER__ */ /* SCSR */ #define SCBSY 0 /* Symbol Counter Interrupt Mask Register */ #define SCIRQM _SFR_MEM8(0xDF) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCIRQM { unsigned int irqmcp : 3; /* Symbol Counter Compare Match 3 IRQ enable */ unsigned int irqmof : 1; /* Symbol Counter Overflow IRQ enable */ unsigned int irqmbo : 1; /* Backoff Slot Counter IRQ enable */ unsigned int : 3; }; #define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM) #endif /* __ASSEMBLER__ */ /* SCIRQM */ #define IRQMCP1 0 #define IRQMCP2 1 #define IRQMCP3 2 #define IRQMOF 3 #define IRQMBO 4 /* Symbol Counter Interrupt Status Register */ #define SCIRQS _SFR_MEM8(0xE0) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCIRQS { unsigned int irqscp : 3; /* Compare Unit 3 Compare Match IRQ */ unsigned int irqsof : 1; /* Symbol Counter Overflow IRQ */ unsigned int irqsbo : 1; /* Backoff Slot Counter IRQ */ unsigned int : 3; }; #define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS) #endif /* __ASSEMBLER__ */ /* SCIRQS */ #define IRQSCP1 0 #define IRQSCP2 1 #define IRQSCP3 2 #define IRQSOF 3 #define IRQSBO 4 /* Symbol Counter Register LL-Byte */ #define SCCNTLL _SFR_MEM8(0xE1) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCCNTLL { unsigned int sccntll : 8; /* Symbol Counter Register LL-Byte */ }; #define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL) #endif /* __ASSEMBLER__ */ /* SCCNTLL */ #define SCCNTLL0 0 #define SCCNTLL1 1 #define SCCNTLL2 2 #define SCCNTLL3 3 #define SCCNTLL4 4 #define SCCNTLL5 5 #define SCCNTLL6 6 #define SCCNTLL7 7 /* Symbol Counter Register LH-Byte */ #define SCCNTLH _SFR_MEM8(0xE2) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCCNTLH { unsigned int sccntlh : 8; /* Symbol Counter Register LH-Byte */ }; #define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH) #endif /* __ASSEMBLER__ */ /* SCCNTLH */ #define SCCNTLH0 0 #define SCCNTLH1 1 #define SCCNTLH2 2 #define SCCNTLH3 3 #define SCCNTLH4 4 #define SCCNTLH5 5 #define SCCNTLH6 6 #define SCCNTLH7 7 /* Symbol Counter Register HL-Byte */ #define SCCNTHL _SFR_MEM8(0xE3) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCCNTHL { unsigned int sccnthl : 8; /* Symbol Counter Register HL-Byte */ }; #define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL) #endif /* __ASSEMBLER__ */ /* SCCNTHL */ #define SCCNTHL0 0 #define SCCNTHL1 1 #define SCCNTHL2 2 #define SCCNTHL3 3 #define SCCNTHL4 4 #define SCCNTHL5 5 #define SCCNTHL6 6 #define SCCNTHL7 7 /* Symbol Counter Register HH-Byte */ #define SCCNTHH _SFR_MEM8(0xE4) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCCNTHH { unsigned int sccnthh : 8; /* Symbol Counter Register HH-Byte */ }; #define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH) #endif /* __ASSEMBLER__ */ /* SCCNTHH */ #define SCCNTHH0 0 #define SCCNTHH1 1 #define SCCNTHH2 2 #define SCCNTHH3 3 #define SCCNTHH4 4 #define SCCNTHH5 5 #define SCCNTHH6 6 #define SCCNTHH7 7 /* Symbol Counter Beacon Timestamp Register LL-Byte */ #define SCBTSRLL _SFR_MEM8(0xE5) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCBTSRLL { unsigned int scbtsrll : 8; /* Symbol Counter Beacon Timestamp Register LL-Byte */ }; #define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL) #endif /* __ASSEMBLER__ */ /* SCBTSRLL */ #define SCBTSRLL0 0 #define SCBTSRLL1 1 #define SCBTSRLL2 2 #define SCBTSRLL3 3 #define SCBTSRLL4 4 #define SCBTSRLL5 5 #define SCBTSRLL6 6 #define SCBTSRLL7 7 /* Symbol Counter Beacon Timestamp Register LH-Byte */ #define SCBTSRLH _SFR_MEM8(0xE6) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCBTSRLH { unsigned int scbtsrlh : 8; /* Symbol Counter Beacon Timestamp Register LH-Byte */ }; #define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH) #endif /* __ASSEMBLER__ */ /* SCBTSRLH */ #define SCBTSRLH0 0 #define SCBTSRLH1 1 #define SCBTSRLH2 2 #define SCBTSRLH3 3 #define SCBTSRLH4 4 #define SCBTSRLH5 5 #define SCBTSRLH6 6 #define SCBTSRLH7 7 /* Symbol Counter Beacon Timestamp Register HL-Byte */ #define SCBTSRHL _SFR_MEM8(0xE7) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCBTSRHL { unsigned int scbtsrhl : 8; /* Symbol Counter Beacon Timestamp Register HL-Byte */ }; #define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL) #endif /* __ASSEMBLER__ */ /* SCBTSRHL */ #define SCBTSRHL0 0 #define SCBTSRHL1 1 #define SCBTSRHL2 2 #define SCBTSRHL3 3 #define SCBTSRHL4 4 #define SCBTSRHL5 5 #define SCBTSRHL6 6 #define SCBTSRHL7 7 /* Symbol Counter Beacon Timestamp Register HH-Byte */ #define SCBTSRHH _SFR_MEM8(0xE8) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCBTSRHH { unsigned int scbtsrhh : 8; /* Symbol Counter Beacon Timestamp Register HH-Byte */ }; #define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH) #endif /* __ASSEMBLER__ */ /* SCBTSRHH */ #define SCBTSRHH0 0 #define SCBTSRHH1 1 #define SCBTSRHH2 2 #define SCBTSRHH3 3 #define SCBTSRHH4 4 #define SCBTSRHH5 5 #define SCBTSRHH6 6 #define SCBTSRHH7 7 /* Symbol Counter Frame Timestamp Register LL-Byte */ #define SCTSRLL _SFR_MEM8(0xE9) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCTSRLL { unsigned int sctsrll : 8; /* Symbol Counter Frame Timestamp Register LL-Byte */ }; #define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL) #endif /* __ASSEMBLER__ */ /* SCTSRLL */ #define SCTSRLL0 0 #define SCTSRLL1 1 #define SCTSRLL2 2 #define SCTSRLL3 3 #define SCTSRLL4 4 #define SCTSRLL5 5 #define SCTSRLL6 6 #define SCTSRLL7 7 /* Symbol Counter Frame Timestamp Register LH-Byte */ #define SCTSRLH _SFR_MEM8(0xEA) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCTSRLH { unsigned int sctsrlh : 8; /* Symbol Counter Frame Timestamp Register LH-Byte */ }; #define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH) #endif /* __ASSEMBLER__ */ /* SCTSRLH */ #define SCTSRLH0 0 #define SCTSRLH1 1 #define SCTSRLH2 2 #define SCTSRLH3 3 #define SCTSRLH4 4 #define SCTSRLH5 5 #define SCTSRLH6 6 #define SCTSRLH7 7 /* Symbol Counter Frame Timestamp Register HL-Byte */ #define SCTSRHL _SFR_MEM8(0xEB) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCTSRHL { unsigned int sctsrhl : 8; /* Symbol Counter Frame Timestamp Register HL-Byte */ }; #define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL) #endif /* __ASSEMBLER__ */ /* SCTSRHL */ #define SCTSRHL0 0 #define SCTSRHL1 1 #define SCTSRHL2 2 #define SCTSRHL3 3 #define SCTSRHL4 4 #define SCTSRHL5 5 #define SCTSRHL6 6 #define SCTSRHL7 7 /* Symbol Counter Frame Timestamp Register HH-Byte */ #define SCTSRHH _SFR_MEM8(0xEC) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCTSRHH { unsigned int sctsrhh : 8; /* Symbol Counter Frame Timestamp Register HH-Byte */ }; #define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH) #endif /* __ASSEMBLER__ */ /* SCTSRHH */ #define SCTSRHH0 0 #define SCTSRHH1 1 #define SCTSRHH2 2 #define SCTSRHH3 3 #define SCTSRHH4 4 #define SCTSRHH5 5 #define SCTSRHH6 6 #define SCTSRHH7 7 /* Symbol Counter Output Compare Register 3 LL-Byte */ #define SCOCR3LL _SFR_MEM8(0xED) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR3LL { unsigned int scocr3ll : 8; /* Symbol Counter Output Compare Register 3 LL-Byte */ }; #define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL) #endif /* __ASSEMBLER__ */ /* SCOCR3LL */ #define SCOCR3LL0 0 #define SCOCR3LL1 1 #define SCOCR3LL2 2 #define SCOCR3LL3 3 #define SCOCR3LL4 4 #define SCOCR3LL5 5 #define SCOCR3LL6 6 #define SCOCR3LL7 7 /* Symbol Counter Output Compare Register 3 LH-Byte */ #define SCOCR3LH _SFR_MEM8(0xEE) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR3LH { unsigned int scocr3lh : 8; /* Symbol Counter Output Compare Register 3 LH-Byte */ }; #define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH) #endif /* __ASSEMBLER__ */ /* SCOCR3LH */ #define SCOCR3LH0 0 #define SCOCR3LH1 1 #define SCOCR3LH2 2 #define SCOCR3LH3 3 #define SCOCR3LH4 4 #define SCOCR3LH5 5 #define SCOCR3LH6 6 #define SCOCR3LH7 7 /* Symbol Counter Output Compare Register 3 HL-Byte */ #define SCOCR3HL _SFR_MEM8(0xEF) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR3HL { unsigned int scocr3hl : 8; /* Symbol Counter Output Compare Register 3 HL-Byte */ }; #define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL) #endif /* __ASSEMBLER__ */ /* SCOCR3HL */ #define SCOCR3HL0 0 #define SCOCR3HL1 1 #define SCOCR3HL2 2 #define SCOCR3HL3 3 #define SCOCR3HL4 4 #define SCOCR3HL5 5 #define SCOCR3HL6 6 #define SCOCR3HL7 7 /* Symbol Counter Output Compare Register 3 HH-Byte */ #define SCOCR3HH _SFR_MEM8(0xF0) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR3HH { unsigned int scocr3hh : 8; /* Symbol Counter Output Compare Register 3 HH-Byte */ }; #define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH) #endif /* __ASSEMBLER__ */ /* SCOCR3HH */ #define SCOCR3HH0 0 #define SCOCR3HH1 1 #define SCOCR3HH2 2 #define SCOCR3HH3 3 #define SCOCR3HH4 4 #define SCOCR3HH5 5 #define SCOCR3HH6 6 #define SCOCR3HH7 7 /* Symbol Counter Output Compare Register 2 LL-Byte */ #define SCOCR2LL _SFR_MEM8(0xF1) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR2LL { unsigned int scocr2ll : 8; /* Symbol Counter Output Compare Register 2 LL-Byte */ }; #define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL) #endif /* __ASSEMBLER__ */ /* SCOCR2LL */ #define SCOCR2LL0 0 #define SCOCR2LL1 1 #define SCOCR2LL2 2 #define SCOCR2LL3 3 #define SCOCR2LL4 4 #define SCOCR2LL5 5 #define SCOCR2LL6 6 #define SCOCR2LL7 7 /* Symbol Counter Output Compare Register 2 LH-Byte */ #define SCOCR2LH _SFR_MEM8(0xF2) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR2LH { unsigned int scocr2lh : 8; /* Symbol Counter Output Compare Register 2 LH-Byte */ }; #define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH) #endif /* __ASSEMBLER__ */ /* SCOCR2LH */ #define SCOCR2LH0 0 #define SCOCR2LH1 1 #define SCOCR2LH2 2 #define SCOCR2LH3 3 #define SCOCR2LH4 4 #define SCOCR2LH5 5 #define SCOCR2LH6 6 #define SCOCR2LH7 7 /* Symbol Counter Output Compare Register 2 HL-Byte */ #define SCOCR2HL _SFR_MEM8(0xF3) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR2HL { unsigned int scocr2hl : 8; /* Symbol Counter Output Compare Register 2 HL-Byte */ }; #define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL) #endif /* __ASSEMBLER__ */ /* SCOCR2HL */ #define SCOCR2HL0 0 #define SCOCR2HL1 1 #define SCOCR2HL2 2 #define SCOCR2HL3 3 #define SCOCR2HL4 4 #define SCOCR2HL5 5 #define SCOCR2HL6 6 #define SCOCR2HL7 7 /* Symbol Counter Output Compare Register 2 HH-Byte */ #define SCOCR2HH _SFR_MEM8(0xF4) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR2HH { unsigned int scocr2hh : 8; /* Symbol Counter Output Compare Register 2 HH-Byte */ }; #define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH) #endif /* __ASSEMBLER__ */ /* SCOCR2HH */ #define SCOCR2HH0 0 #define SCOCR2HH1 1 #define SCOCR2HH2 2 #define SCOCR2HH3 3 #define SCOCR2HH4 4 #define SCOCR2HH5 5 #define SCOCR2HH6 6 #define SCOCR2HH7 7 /* Symbol Counter Output Compare Register 1 LL-Byte */ #define SCOCR1LL _SFR_MEM8(0xF5) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR1LL { unsigned int scocr1ll : 8; /* Symbol Counter Output Compare Register 1 LL-Byte */ }; #define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL) #endif /* __ASSEMBLER__ */ /* SCOCR1LL */ #define SCOCR1LL0 0 #define SCOCR1LL1 1 #define SCOCR1LL2 2 #define SCOCR1LL3 3 #define SCOCR1LL4 4 #define SCOCR1LL5 5 #define SCOCR1LL6 6 #define SCOCR1LL7 7 /* Symbol Counter Output Compare Register 1 LH-Byte */ #define SCOCR1LH _SFR_MEM8(0xF6) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR1LH { unsigned int scocr1lh : 8; /* Symbol Counter Output Compare Register 1 LH-Byte */ }; #define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH) #endif /* __ASSEMBLER__ */ /* SCOCR1LH */ #define SCOCR1LH0 0 #define SCOCR1LH1 1 #define SCOCR1LH2 2 #define SCOCR1LH3 3 #define SCOCR1LH4 4 #define SCOCR1LH5 5 #define SCOCR1LH6 6 #define SCOCR1LH7 7 /* Symbol Counter Output Compare Register 1 HL-Byte */ #define SCOCR1HL _SFR_MEM8(0xF7) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR1HL { unsigned int scocr1hl : 8; /* Symbol Counter Output Compare Register 1 HL-Byte */ }; #define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL) #endif /* __ASSEMBLER__ */ /* SCOCR1HL */ #define SCOCR1HL0 0 #define SCOCR1HL1 1 #define SCOCR1HL2 2 #define SCOCR1HL3 3 #define SCOCR1HL4 4 #define SCOCR1HL5 5 #define SCOCR1HL6 6 #define SCOCR1HL7 7 /* Symbol Counter Output Compare Register 1 HH-Byte */ #define SCOCR1HH _SFR_MEM8(0xF8) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SCOCR1HH { unsigned int scocr1hh : 8; /* Symbol Counter Output Compare Register 1 HH-Byte */ }; #define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH) #endif /* __ASSEMBLER__ */ /* SCOCR1HH */ #define SCOCR1HH0 0 #define SCOCR1HH1 1 #define SCOCR1HH2 2 #define SCOCR1HH3 3 #define SCOCR1HH4 4 #define SCOCR1HH5 5 #define SCOCR1HH6 6 #define SCOCR1HH7 7 /* Timer/Counter5 Control Register A */ #define TCCR5A _SFR_MEM8(0x120) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR5A { unsigned int wgm5 : 2; /* Waveform Generation Mode */ unsigned int com5c : 2; /* Compare Output Mode for Channel C */ unsigned int com5b : 2; /* Compare Output Mode for Channel B */ unsigned int com5a : 2; /* Compare Output Mode for Channel A */ }; #define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A) #endif /* __ASSEMBLER__ */ /* TCCR5A */ #define WGM50 0 #define WGM51 1 #define COM5C0 2 #define COM5C1 3 #define COM5B0 4 #define COM5B1 5 #define COM5A0 6 #define COM5A1 7 /* Timer/Counter5 Control Register B */ #define TCCR5B _SFR_MEM8(0x121) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR5B { unsigned int cs5 : 3; /* Clock Select */ unsigned int wgm5 : 2; /* Waveform Generation Mode */ unsigned int : 1; unsigned int ices5 : 1; /* Input Capture 5 Edge Select */ unsigned int icnc5 : 1; /* Input Capture 5 Noise Canceller */ }; #define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B) #endif /* __ASSEMBLER__ */ /* TCCR5B */ #define CS50 0 #define CS51 1 #define CS52 2 #define WGM52 3 #define WGM53 4 #define ICES5 6 #define ICNC5 7 /* Timer/Counter5 Control Register C */ #define TCCR5C _SFR_MEM8(0x122) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TCCR5C { unsigned int : 5; unsigned int foc5c : 1; /* Force Output Compare for Channel C */ unsigned int foc5b : 1; /* Force Output Compare for Channel B */ unsigned int foc5a : 1; /* Force Output Compare for Channel A */ }; #define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C) #endif /* __ASSEMBLER__ */ /* TCCR5C */ #define FOC5C 5 #define FOC5B 6 #define FOC5A 7 /* Timer/Counter5 Bytes */ #define TCNT5 _SFR_MEM16(0x124) #define TCNT5L _SFR_MEM8(0x124) #define TCNT5H _SFR_MEM8(0x125) /* Timer/Counter5 Input Capture Register Bytes */ #define ICR5 _SFR_MEM16(0x126) #define ICR5L _SFR_MEM8(0x126) #define ICR5H _SFR_MEM8(0x127) /* Timer/Counter5 Output Compare Register A Bytes */ #define OCR5A _SFR_MEM16(0x128) #define OCR5AL _SFR_MEM8(0x128) #define OCR5AH _SFR_MEM8(0x129) /* Timer/Counter5 Output Compare Register B Bytes */ #define OCR5B _SFR_MEM16(0x12A) #define OCR5BL _SFR_MEM8(0x12A) #define OCR5BH _SFR_MEM8(0x12B) /* Timer/Counter5 Output Compare Register C Bytes */ #define OCR5C _SFR_MEM16(0x12C) #define OCR5CL _SFR_MEM8(0x12C) #define OCR5CH _SFR_MEM8(0x12D) /* Low Leakage Voltage Regulator Control Register */ #define LLCR _SFR_MEM8(0x12F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_LLCR { unsigned int llencal : 1; /* Enable Automatic Calibration */ unsigned int llshort : 1; /* Short Lower Calibration Circuit */ unsigned int lltco : 1; /* Temperature Coefficient of Current Source */ unsigned int llcal : 1; /* Calibration Active */ unsigned int llcomp : 1; /* Comparator Output */ unsigned int lldone : 1; /* Calibration Done */ unsigned int : 2; }; #define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR) #endif /* __ASSEMBLER__ */ /* LLCR */ #define LLENCAL 0 #define LLSHORT 1 #define LLTCO 2 #define LLCAL 3 #define LLCOMP 4 #define LLDONE 5 /* Low Leakage Voltage Regulator Data Register (Low-Byte) */ #define LLDRL _SFR_MEM8(0x130) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_LLDRL { unsigned int lldrl : 4; /* Low-Byte Data Register Bits */ unsigned int : 4; }; #define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL) #endif /* __ASSEMBLER__ */ /* LLDRL */ #define LLDRL0 0 #define LLDRL1 1 #define LLDRL2 2 #define LLDRL3 3 /* Low Leakage Voltage Regulator Data Register (High-Byte) */ #define LLDRH _SFR_MEM8(0x131) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_LLDRH { unsigned int lldrh : 5; /* High-Byte Data Register Bits */ unsigned int : 3; }; #define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH) #endif /* __ASSEMBLER__ */ /* LLDRH */ #define LLDRH0 0 #define LLDRH1 1 #define LLDRH2 2 #define LLDRH3 3 #define LLDRH4 4 /* Data Retention Configuration Register of SRAM 3 */ #define DRTRAM3 _SFR_MEM8(0x132) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_DRTRAM3 { unsigned int : 4; unsigned int endrt : 1; /* Enable SRAM Data Retention */ unsigned int drtswok : 1; /* DRT Switch OK */ unsigned int : 2; }; #define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3) #endif /* __ASSEMBLER__ */ /* DRTRAM3 */ #define ENDRT 4 #define DRTSWOK 5 /* Data Retention Configuration Register of SRAM 2 */ #define DRTRAM2 _SFR_MEM8(0x133) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_DRTRAM2 { unsigned int : 4; unsigned int endrt : 1; /* Enable SRAM Data Retention */ unsigned int drtswok : 1; /* DRT Switch OK */ unsigned int : 2; }; #define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2) #endif /* __ASSEMBLER__ */ /* DRTRAM2 */ #define ENDRT 4 #define DRTSWOK 5 /* Data Retention Configuration Register of SRAM 1 */ #define DRTRAM1 _SFR_MEM8(0x134) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_DRTRAM1 { unsigned int : 4; unsigned int endrt : 1; /* Enable SRAM Data Retention */ unsigned int drtswok : 1; /* DRT Switch OK */ unsigned int : 2; }; #define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1) #endif /* __ASSEMBLER__ */ /* DRTRAM1 */ #define ENDRT 4 #define DRTSWOK 5 /* Data Retention Configuration Register of SRAM 0 */ #define DRTRAM0 _SFR_MEM8(0x135) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_DRTRAM0 { unsigned int : 4; unsigned int endrt : 1; /* Enable SRAM Data Retention */ unsigned int drtswok : 1; /* DRT Switch OK */ unsigned int : 2; }; #define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0) #endif /* __ASSEMBLER__ */ /* DRTRAM0 */ #define ENDRT 4 #define DRTSWOK 5 /* Port Driver Strength Register 0 */ #define DPDS0 _SFR_MEM8(0x136) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_DPDS0 { unsigned int pbdrv : 2; /* Driver Strength Port B */ unsigned int pddrv : 2; /* Driver Strength Port D */ unsigned int pedrv : 2; /* Driver Strength Port E */ unsigned int pfdrv : 2; /* Driver Strength Port F */ }; #define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0) #endif /* __ASSEMBLER__ */ /* DPDS0 */ #define PBDRV0 0 #define PBDRV1 1 #define PDDRV0 2 #define PDDRV1 3 #define PEDRV0 4 #define PEDRV1 5 #define PFDRV0 6 #define PFDRV1 7 /* Port Driver Strength Register 1 */ #define DPDS1 _SFR_MEM8(0x137) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_DPDS1 { unsigned int pgdrv : 2; /* Driver Strength Port G */ unsigned int : 6; }; #define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1) #endif /* __ASSEMBLER__ */ /* DPDS1 */ #define PGDRV0 0 #define PGDRV1 1 /* Transceiver Pin Register */ #define TRXPR _SFR_MEM8(0x139) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TRXPR { unsigned int trxrst : 1; /* Force Transceiver Reset */ unsigned int slptr : 1; /* Multi-purpose Transceiver Control Bit */ unsigned int : 6; }; #define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR) #endif /* __ASSEMBLER__ */ /* TRXPR */ #define TRXRST 0 #define SLPTR 1 /* AES Control Register */ #define AES_CTRL _SFR_MEM8(0x13C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_AES_CTRL { unsigned int : 2; unsigned int aes_im : 1; /* AES Interrupt Enable */ unsigned int aes_dir : 1; /* Set AES Operation Direction */ unsigned int : 1; unsigned int aes_mode : 1; /* Set AES Operation Mode */ unsigned int : 1; unsigned int aes_request : 1; /* Request AES Operation. */ }; #define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL) /* symbolic names */ #define AES_DIR_ENC 0 #define AES_DIR_DEC 1 #define AES_MODE_ECB 0 #define AES_MODE_CBC 1 #endif /* __ASSEMBLER__ */ /* AES_CTRL */ #define AES_IM 2 #define AES_DIR 3 #define AES_MODE 5 #define AES_REQUEST 7 /* AES Status Register */ #define AES_STATUS _SFR_MEM8(0x13D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_AES_STATUS { unsigned int aes_done : 1; /* AES Operation Finished with Success */ unsigned int : 6; unsigned int aes_er : 1; /* AES Operation Finished with Error */ }; #define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS) #endif /* __ASSEMBLER__ */ /* AES_STATUS */ #define AES_DONE 0 #define AES_ER 7 /* AES Plain and Cipher Text Buffer Register */ #define AES_STATE _SFR_MEM8(0x13E) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_AES_STATE { unsigned int aes_state : 8; /* AES Plain and Cipher Text Buffer */ }; #define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE) #endif /* __ASSEMBLER__ */ /* AES_STATE */ #define AES_STATE0 0 #define AES_STATE1 1 #define AES_STATE2 2 #define AES_STATE3 3 #define AES_STATE4 4 #define AES_STATE5 5 #define AES_STATE6 6 #define AES_STATE7 7 /* AES Encryption and Decryption Key Buffer Register */ #define AES_KEY _SFR_MEM8(0x13F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_AES_KEY { unsigned int aes_key : 8; /* AES Encryption/Decryption Key Buffer */ }; #define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY) #endif /* __ASSEMBLER__ */ /* AES_KEY */ #define AES_KEY0 0 #define AES_KEY1 1 #define AES_KEY2 2 #define AES_KEY3 3 #define AES_KEY4 4 #define AES_KEY5 5 #define AES_KEY6 6 #define AES_KEY7 7 /* Transceiver Status Register */ #define TRX_STATUS _SFR_MEM8(0x141) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TRX_STATUS { unsigned int trx_status : 5; /* Transceiver Main Status */ unsigned int tst_status : 1; /* Test mode status */ unsigned int cca_status : 1; /* CCA Status Result */ unsigned int cca_done : 1; /* CCA Algorithm Status */ }; #define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS) /* symbolic names */ #define P_ON 0 #define BUSY_RX 1 #define BUSY_TX 2 #define RX_ON 6 #define TRX_OFF 8 #define PLL_ON 9 #define SLEEP 15 #define BUSY_RX_AACK 17 #define BUSY_TX_ARET 18 #define RX_AACK_ON 22 #define TX_ARET_ON 25 #define STATE_TRANSITION_IN_PROGRESS 31 #define TST_DISABLED 0 #define TST_ENABLED 1 #define CCA_BUSY 0 #define CCA_IDLE 1 #define CCA_NOT_FIN 0 #define CCA_FIN 1 #endif /* __ASSEMBLER__ */ /* TRX_STATUS */ #define TRX_STATUS0 0 #define TRX_STATUS1 1 #define TRX_STATUS2 2 #define TRX_STATUS3 3 #define TRX_STATUS4 4 #define TST_STATUS 5 #define CCA_STATUS 6 #define CCA_DONE 7 /* Transceiver State Control Register */ #define TRX_STATE _SFR_MEM8(0x142) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TRX_STATE { unsigned int trx_cmd : 5; /* State Control Command */ unsigned int trac_status : 3; /* Transaction Status */ }; #define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE) /* symbolic names */ #define CMD_NOP 0 #define CMD_TX_START 2 #define CMD_FORCE_TRX_OFF 3 #define CMD_FORCE_PLL_ON 4 #define CMD_RX_ON 6 #define CMD_TRX_OFF 8 #define CMD_PLL_ON 9 #define CMD_RX_AACK_ON 22 #define CMD_TX_ARET_ON 25 #define TRAC_SUCCESS 0 #define TRAC_SUCCESS_DATA_PENDING 1 #define TRAC_SUCCESS_WAIT_FOR_ACK 2 #define TRAC_CHANNEL_ACCESS_FAILURE 3 #define TRAC_NO_ACK 5 #define TRAC_INVALID 7 #endif /* __ASSEMBLER__ */ /* TRX_STATE */ #define TRX_CMD0 0 #define TRX_CMD1 1 #define TRX_CMD2 2 #define TRX_CMD3 3 #define TRX_CMD4 4 #define TRAC_STATUS0 5 #define TRAC_STATUS1 6 #define TRAC_STATUS2 7 /* Reserved */ #define TRX_CTRL_0 _SFR_MEM8(0x143) /* Transceiver Control Register 1 */ #define TRX_CTRL_1 _SFR_MEM8(0x144) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TRX_CTRL_1 { unsigned int : 5; unsigned int tx_auto_crc_on : 1; /* Enable Automatic CRC Calculation */ unsigned int irq_2_ext_en : 1; /* Connect Frame Start IRQ to TC1 */ unsigned int pa_ext_en : 1; /* External PA support enable */ }; #define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1) #endif /* __ASSEMBLER__ */ /* TRX_CTRL_1 */ #define TX_AUTO_CRC_ON 5 #define IRQ_2_EXT_EN 6 #define PA_EXT_EN 7 /* Transceiver Transmit Power Control Register */ #define PHY_TX_PWR _SFR_MEM8(0x145) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PHY_TX_PWR { unsigned int tx_pwr : 4; /* Transmit Power Setting */ unsigned int pa_lt : 2; /* Power Amplifier Lead Time */ unsigned int pa_buf_lt : 2; /* Power Amplifier Buffer Lead Time */ }; #define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR) /* symbolic names */ #define PA_LT_2US 0 #define PA_LT_4US 1 #define PA_LT_6US 2 #define PA_LT_8US 3 #define PA_BUF_LT_0US 0 #define PA_BUF_LT_2US 1 #define PA_BUF_LT_4US 2 #define PA_BUF_LT_6US 3 #endif /* __ASSEMBLER__ */ /* PHY_TX_PWR */ #define TX_PWR0 0 #define TX_PWR1 1 #define TX_PWR2 2 #define TX_PWR3 3 #define PA_LT0 4 #define PA_LT1 5 #define PA_BUF_LT0 6 #define PA_BUF_LT1 7 /* Receiver Signal Strength Indicator Register */ #define PHY_RSSI _SFR_MEM8(0x146) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PHY_RSSI { unsigned int rssi : 5; /* Receiver Signal Strength Indicator */ unsigned int rnd_value : 2; /* Random Value */ unsigned int rx_crc_valid : 1; /* Received Frame CRC Status */ }; #define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI) /* symbolic names */ #define RSSI_MIN 0 #define RSSI_MIN_PLUS_3dB 1 #define RSSI_MAX 28 #define CRC_INVALID 0 #define CRC_VALID 1 #endif /* __ASSEMBLER__ */ /* PHY_RSSI */ #define RSSI0 0 #define RSSI1 1 #define RSSI2 2 #define RSSI3 3 #define RSSI4 4 #define RND_VALUE0 5 #define RND_VALUE1 6 #define RX_CRC_VALID 7 /* Transceiver Energy Detection Level Register */ #define PHY_ED_LEVEL _SFR_MEM8(0x147) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PHY_ED_LEVEL { unsigned int ed_level : 8; /* Energy Detection Level */ }; #define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL) /* symbolic names */ #define ED_MIN 0 #define ED_MIN_PLUS_1dB 1 #define ED_MAX 84 #define ED_RESET 255 #endif /* __ASSEMBLER__ */ /* PHY_ED_LEVEL */ #define ED_LEVEL0 0 #define ED_LEVEL1 1 #define ED_LEVEL2 2 #define ED_LEVEL3 3 #define ED_LEVEL4 4 #define ED_LEVEL5 5 #define ED_LEVEL6 6 #define ED_LEVEL7 7 /* Transceiver Clear Channel Assessment (CCA) Control Register */ #define PHY_CC_CCA _SFR_MEM8(0x148) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PHY_CC_CCA { unsigned int channel : 5; /* RX/TX Channel Selection */ unsigned int cca_mode : 2; /* Select CCA Measurement Mode */ unsigned int cca_request : 1; /* Manual CCA Measurement Request */ }; #define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA) /* symbolic names */ #define F_2405MHZ 11 #define F_2410MHZ 12 #define F_2415MHZ 13 #define F_2420MHZ 14 #define F_2425MHZ 15 #define F_2430MHZ 16 #define F_2435MHZ 17 #define F_2440MHZ 18 #define F_2445MHZ 19 #define F_2450MHZ 20 #define F_2455MHZ 21 #define F_2460MHZ 22 #define F_2465MHZ 23 #define F_2470MHZ 24 #define F_2475MHZ 25 #define F_2480MHZ 26 #define CCA_CS_OR_ED 0 #define CCA_ED 1 #define CCA_CS 2 #define CCA_CS_AND_ED 3 #endif /* __ASSEMBLER__ */ /* PHY_CC_CCA */ #define CHANNEL0 0 #define CHANNEL1 1 #define CHANNEL2 2 #define CHANNEL3 3 #define CHANNEL4 4 #define CCA_MODE0 5 #define CCA_MODE1 6 #define CCA_REQUEST 7 /* Transceiver CCA Threshold Setting Register */ #define CCA_THRES _SFR_MEM8(0x149) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_CCA_THRES { unsigned int cca_ed_thres : 4; /* ED Threshold Level for CCA Measurement */ unsigned int cca_cs_thres : 4; /* CS Threshold Level for CCA Measurement */ }; #define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES) #endif /* __ASSEMBLER__ */ /* CCA_THRES */ #define CCA_ED_THRES0 0 #define CCA_ED_THRES1 1 #define CCA_ED_THRES2 2 #define CCA_ED_THRES3 3 #define CCA_CS_THRES0 4 #define CCA_CS_THRES1 5 #define CCA_CS_THRES2 6 #define CCA_CS_THRES3 7 /* Transceiver Receive Control Register */ #define RX_CTRL _SFR_MEM8(0x14A) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_RX_CTRL { unsigned int pdt_thres : 4; /* Receiver Sensitivity Control */ unsigned int : 4; }; #define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL) /* symbolic names */ #define PDT_THRES_ANT_DIV_OFF 7 #define PDT_THRES_ANT_DIV_ON 3 #endif /* __ASSEMBLER__ */ /* RX_CTRL */ #define PDT_THRES0 0 #define PDT_THRES1 1 #define PDT_THRES2 2 #define PDT_THRES3 3 /* Start of Frame Delimiter Value Register */ #define SFD_VALUE _SFR_MEM8(0x14B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SFD_VALUE { unsigned int sfd_value : 8; /* Start of Frame Delimiter Value */ }; #define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE) /* symbolic names */ #define IEEE_SFD 167 #endif /* __ASSEMBLER__ */ /* SFD_VALUE */ #define SFD_VALUE0 0 #define SFD_VALUE1 1 #define SFD_VALUE2 2 #define SFD_VALUE3 3 #define SFD_VALUE4 4 #define SFD_VALUE5 5 #define SFD_VALUE6 6 #define SFD_VALUE7 7 /* Transceiver Control Register 2 */ #define TRX_CTRL_2 _SFR_MEM8(0x14C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TRX_CTRL_2 { unsigned int oqpsk_data_rate : 2; /* Data Rate Selection */ unsigned int : 5; unsigned int rx_safe_mode : 1; /* RX Safe Mode */ }; #define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2) /* symbolic names */ #define RATE_250KB 0 #define RATE_500KB 1 #define RATE_1000KB 2 #define RATE_2000KB 3 #endif /* __ASSEMBLER__ */ /* TRX_CTRL_2 */ #define OQPSK_DATA_RATE0 0 #define OQPSK_DATA_RATE1 1 #define RX_SAFE_MODE 7 /* Antenna Diversity Control Register */ #define ANT_DIV _SFR_MEM8(0x14D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_ANT_DIV { unsigned int ant_ctrl : 2; /* Static Antenna Diversity Switch Control */ unsigned int ant_ext_sw_en : 1; /* Enable External Antenna Switch Control */ unsigned int ant_div_en : 1; /* Enable Antenna Diversity */ unsigned int : 3; unsigned int ant_sel : 1; /* Antenna Diversity Antenna Status */ }; #define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV) /* symbolic names */ #define ANT_1 1 #define ANT_0 2 #define ANT_RESET 3 #define ANT_DIV_EXT_SW_DIS 0 #define ANT_DIV_EXT_SW_EN 1 #define ANTENNA_0 0 #define ANTENNA_1 1 #endif /* __ASSEMBLER__ */ /* ANT_DIV */ #define ANT_CTRL0 0 #define ANT_CTRL1 1 #define ANT_EXT_SW_EN 2 #define ANT_DIV_EN 3 #define ANT_SEL 7 /* Transceiver Interrupt Enable Register */ #define IRQ_MASK _SFR_MEM8(0x14E) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IRQ_MASK { unsigned int pll_lock_en : 1; /* PLL Lock Interrupt Enable */ unsigned int pll_unlock_en : 1; /* PLL Unlock Interrupt Enable */ unsigned int rx_start_en : 1; /* RX_START Interrupt Enable */ unsigned int rx_end_en : 1; /* RX_END Interrupt Enable */ unsigned int cca_ed_done_en : 1; /* End of ED Measurement Interrupt Enable */ unsigned int ami_en : 1; /* Address Match Interrupt Enable */ unsigned int tx_end_en : 1; /* TX_END Interrupt Enable */ unsigned int awake_en : 1; /* Awake Interrupt Enable */ }; #define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK) #endif /* __ASSEMBLER__ */ /* IRQ_MASK */ #define PLL_LOCK_EN 0 #define PLL_UNLOCK_EN 1 #define RX_START_EN 2 #define RX_END_EN 3 #define CCA_ED_DONE_EN 4 #define AMI_EN 5 #define TX_END_EN 6 #define AWAKE_EN 7 /* Transceiver Interrupt Status Register */ #define IRQ_STATUS _SFR_MEM8(0x14F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IRQ_STATUS { unsigned int pll_lock : 1; /* PLL Lock Interrupt Status */ unsigned int pll_unlock : 1; /* PLL Unlock Interrupt Status */ unsigned int rx_start : 1; /* RX_START Interrupt Status */ unsigned int rx_end : 1; /* RX_END Interrupt Status */ unsigned int cca_ed_done : 1; /* End of ED Measurement Interrupt Status */ unsigned int ami : 1; /* Address Match Interrupt Status */ unsigned int tx_end : 1; /* TX_END Interrupt Status */ unsigned int awake : 1; /* Awake Interrupt Status */ }; #define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS) #endif /* __ASSEMBLER__ */ /* IRQ_STATUS */ #define PLL_LOCK 0 #define PLL_UNLOCK 1 #define RX_START 2 #define RX_END 3 #define CCA_ED_DONE 4 #define AMI 5 #define TX_END 6 #define AWAKE 7 /* Voltage Regulator Control and Status Register */ #define VREG_CTRL _SFR_MEM8(0x150) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_VREG_CTRL { unsigned int : 2; unsigned int dvdd_ok : 1; /* DVDD Supply Voltage Valid */ unsigned int dvreg_ext : 1; /* Use External DVDD Regulator */ unsigned int : 2; unsigned int avdd_ok : 1; /* AVDD Supply Voltage Valid */ unsigned int avreg_ext : 1; /* Use External AVDD Regulator */ }; #define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL) /* symbolic names */ #define DVDD_INT 0 #define DVDD_EXT 1 #define AVDD_INT 0 #define AVDD_EXT 1 #endif /* __ASSEMBLER__ */ /* VREG_CTRL */ #define DVDD_OK 2 #define DVREG_EXT 3 #define AVDD_OK 6 #define AVREG_EXT 7 /* Battery Monitor Control and Status Register */ #define BATMON _SFR_MEM8(0x151) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_BATMON { unsigned int batmon_vth : 4; /* Battery Monitor Threshold Voltage */ unsigned int batmon_hr : 1; /* Battery Monitor Voltage Range */ unsigned int batmon_ok : 1; /* Battery Monitor Status */ unsigned int bat_low_en : 1; /* Battery Monitor Interrupt Enable */ unsigned int bat_low : 1; /* Battery Monitor Interrupt Status */ }; #define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON) /* symbolic names */ #define BATMON_HR_DIS 0 #define BATMON_HR_EN 1 #endif /* __ASSEMBLER__ */ /* BATMON */ #define BATMON_VTH0 0 #define BATMON_VTH1 1 #define BATMON_VTH2 2 #define BATMON_VTH3 3 #define BATMON_HR 4 #define BATMON_OK 5 #define BAT_LOW_EN 6 #define BAT_LOW 7 /* Crystal Oscillator Control Register */ #define XOSC_CTRL _SFR_MEM8(0x152) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_XOSC_CTRL { unsigned int xtal_trim : 4; /* Crystal Oscillator Load Capacitance Trimming */ unsigned int xtal_mode : 4; /* Crystal Oscillator Operating Mode */ }; #define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL) /* symbolic names */ #define XTAL_TRIM_MIN 0 #define XTAL_TRIM_MAX 15 #endif /* __ASSEMBLER__ */ /* XOSC_CTRL */ #define XTAL_TRIM0 0 #define XTAL_TRIM1 1 #define XTAL_TRIM2 2 #define XTAL_TRIM3 3 #define XTAL_MODE0 4 #define XTAL_MODE1 5 #define XTAL_MODE2 6 #define XTAL_MODE3 7 /* Transceiver Receiver Sensitivity Control Register */ #define RX_SYN _SFR_MEM8(0x155) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_RX_SYN { unsigned int rx_pdt_level : 4; /* Reduce Receiver Sensitivity */ unsigned int : 3; unsigned int rx_pdt_dis : 1; /* Prevent Frame Reception */ }; #define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN) /* symbolic names */ #define RX_PDT_LEVEL_MIN 0 #define RX_PDT_LEVEL_MAX 15 #endif /* __ASSEMBLER__ */ /* RX_SYN */ #define RX_PDT_LEVEL0 0 #define RX_PDT_LEVEL1 1 #define RX_PDT_LEVEL2 2 #define RX_PDT_LEVEL3 3 #define RX_PDT_DIS 7 /* Transceiver Acknowledgment Frame Control Register 1 */ #define XAH_CTRL_1 _SFR_MEM8(0x157) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_XAH_CTRL_1 { unsigned int : 1; unsigned int aack_prom_mode : 1; /* Enable Promiscuous Mode */ unsigned int aack_ack_time : 1; /* Reduce Acknowledgment Time */ unsigned int : 1; unsigned int aack_upld_res_ft : 1; /* Process Reserved Frames */ unsigned int aack_fltr_res_ft : 1; /* Filter Reserved Frames */ unsigned int : 2; }; #define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1) /* symbolic names */ #define AACK_ACK_TIME_12_SYM 0 #define AACK_ACK_TIME_2_SYM 1 #endif /* __ASSEMBLER__ */ /* XAH_CTRL_1 */ #define AACK_PROM_MODE 1 #define AACK_ACK_TIME 2 #define AACK_UPLD_RES_FT 4 #define AACK_FLTR_RES_FT 5 /* Transceiver Filter Tuning Control Register */ #define FTN_CTRL _SFR_MEM8(0x158) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_FTN_CTRL { unsigned int : 7; unsigned int ftn_start : 1; /* Start Calibration Loop of Filter Tuning Network */ }; #define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL) #endif /* __ASSEMBLER__ */ /* FTN_CTRL */ #define FTN_START 7 /* Transceiver Center Frequency Calibration Control Register */ #define PLL_CF _SFR_MEM8(0x15A) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PLL_CF { unsigned int : 7; unsigned int pll_cf_start : 1; /* Start Center Frequency Calibration */ }; #define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF) #endif /* __ASSEMBLER__ */ /* PLL_CF */ #define PLL_CF_START 7 /* Transceiver Delay Cell Calibration Control Register */ #define PLL_DCU _SFR_MEM8(0x15B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PLL_DCU { unsigned int : 7; unsigned int pll_dcu_start : 1; /* Start Delay Cell Calibration */ }; #define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU) #endif /* __ASSEMBLER__ */ /* PLL_DCU */ #define PLL_DCU_START 7 /* Device Identification Register (Part Number) */ #define PART_NUM _SFR_MEM8(0x15C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PART_NUM { unsigned int part_num : 8; /* Part Number */ }; #define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM) /* symbolic names */ #define P_ATmega128RFA1 131 #endif /* __ASSEMBLER__ */ /* PART_NUM */ #define PART_NUM0 0 #define PART_NUM1 1 #define PART_NUM2 2 #define PART_NUM3 3 #define PART_NUM4 4 #define PART_NUM5 5 #define PART_NUM6 6 #define PART_NUM7 7 /* Device Identification Register (Version Number) */ #define VERSION_NUM _SFR_MEM8(0x15D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_VERSION_NUM { unsigned int version_num : 8; /* Version Number */ }; #define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM) /* symbolic names */ #define REV_A 2 #define REV_B 3 #endif /* __ASSEMBLER__ */ /* VERSION_NUM */ #define VERSION_NUM0 0 #define VERSION_NUM1 1 #define VERSION_NUM2 2 #define VERSION_NUM3 3 #define VERSION_NUM4 4 #define VERSION_NUM5 5 #define VERSION_NUM6 6 #define VERSION_NUM7 7 /* Device Identification Register (Manufacture ID Low Byte) */ #define MAN_ID_0 _SFR_MEM8(0x15E) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_MAN_ID_0 { unsigned int man_id_0 : 8; /* Manufacturer ID (Low Byte) */ }; #define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0) /* symbolic names */ #define ATMEL_BYTE_0 31 #endif /* __ASSEMBLER__ */ /* MAN_ID_0 */ #define MAN_ID_00 0 #define MAN_ID_01 1 #define MAN_ID_02 2 #define MAN_ID_03 3 #define MAN_ID_04 4 #define MAN_ID_05 5 #define MAN_ID_06 6 #define MAN_ID_07 7 /* Device Identification Register (Manufacture ID High Byte) */ #define MAN_ID_1 _SFR_MEM8(0x15F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_MAN_ID_1 { unsigned int man_id_1 : 8; /* Manufacturer ID (High Byte) */ }; #define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1) /* symbolic names */ #define ATMEL_BYTE_1 0 #endif /* __ASSEMBLER__ */ /* MAN_ID_1 */ #define MAN_ID_10 0 #define MAN_ID_11 1 #define MAN_ID_12 2 #define MAN_ID_13 3 #define MAN_ID_14 4 #define MAN_ID_15 5 #define MAN_ID_16 6 #define MAN_ID_17 7 /* Transceiver MAC Short Address Register (Low Byte) */ #define SHORT_ADDR_0 _SFR_MEM8(0x160) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SHORT_ADDR_0 { unsigned int short_addr_0 : 8; /* MAC Short Address */ }; #define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0) #endif /* __ASSEMBLER__ */ /* SHORT_ADDR_0 */ #define SHORT_ADDR_00 0 #define SHORT_ADDR_01 1 #define SHORT_ADDR_02 2 #define SHORT_ADDR_03 3 #define SHORT_ADDR_04 4 #define SHORT_ADDR_05 5 #define SHORT_ADDR_06 6 #define SHORT_ADDR_07 7 /* Transceiver MAC Short Address Register (High Byte) */ #define SHORT_ADDR_1 _SFR_MEM8(0x161) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_SHORT_ADDR_1 { unsigned int short_addr_1 : 8; /* MAC Short Address */ }; #define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1) #endif /* __ASSEMBLER__ */ /* SHORT_ADDR_1 */ #define SHORT_ADDR_10 0 #define SHORT_ADDR_11 1 #define SHORT_ADDR_12 2 #define SHORT_ADDR_13 3 #define SHORT_ADDR_14 4 #define SHORT_ADDR_15 5 #define SHORT_ADDR_16 6 #define SHORT_ADDR_17 7 /* Transceiver Personal Area Network ID Register (Low Byte) */ #define PAN_ID_0 _SFR_MEM8(0x162) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PAN_ID_0 { unsigned int pan_id_0 : 8; /* MAC Personal Area Network ID */ }; #define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0) #endif /* __ASSEMBLER__ */ /* PAN_ID_0 */ #define PAN_ID_00 0 #define PAN_ID_01 1 #define PAN_ID_02 2 #define PAN_ID_03 3 #define PAN_ID_04 4 #define PAN_ID_05 5 #define PAN_ID_06 6 #define PAN_ID_07 7 /* Transceiver Personal Area Network ID Register (High Byte) */ #define PAN_ID_1 _SFR_MEM8(0x163) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_PAN_ID_1 { unsigned int pan_id_1 : 8; /* MAC Personal Area Network ID */ }; #define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1) #endif /* __ASSEMBLER__ */ /* PAN_ID_1 */ #define PAN_ID_10 0 #define PAN_ID_11 1 #define PAN_ID_12 2 #define PAN_ID_13 3 #define PAN_ID_14 4 #define PAN_ID_15 5 #define PAN_ID_16 6 #define PAN_ID_17 7 /* Transceiver MAC IEEE Address Register 0 */ #define IEEE_ADDR_0 _SFR_MEM8(0x164) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IEEE_ADDR_0 { unsigned int ieee_addr_0 : 8; /* MAC IEEE Address */ }; #define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0) #endif /* __ASSEMBLER__ */ /* IEEE_ADDR_0 */ #define IEEE_ADDR_00 0 #define IEEE_ADDR_01 1 #define IEEE_ADDR_02 2 #define IEEE_ADDR_03 3 #define IEEE_ADDR_04 4 #define IEEE_ADDR_05 5 #define IEEE_ADDR_06 6 #define IEEE_ADDR_07 7 /* Transceiver MAC IEEE Address Register 1 */ #define IEEE_ADDR_1 _SFR_MEM8(0x165) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IEEE_ADDR_1 { unsigned int ieee_addr_1 : 8; /* MAC IEEE Address */ }; #define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1) #endif /* __ASSEMBLER__ */ /* IEEE_ADDR_1 */ #define IEEE_ADDR_10 0 #define IEEE_ADDR_11 1 #define IEEE_ADDR_12 2 #define IEEE_ADDR_13 3 #define IEEE_ADDR_14 4 #define IEEE_ADDR_15 5 #define IEEE_ADDR_16 6 #define IEEE_ADDR_17 7 /* Transceiver MAC IEEE Address Register 2 */ #define IEEE_ADDR_2 _SFR_MEM8(0x166) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IEEE_ADDR_2 { unsigned int ieee_addr_2 : 8; /* MAC IEEE Address */ }; #define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2) #endif /* __ASSEMBLER__ */ /* IEEE_ADDR_2 */ #define IEEE_ADDR_20 0 #define IEEE_ADDR_21 1 #define IEEE_ADDR_22 2 #define IEEE_ADDR_23 3 #define IEEE_ADDR_24 4 #define IEEE_ADDR_25 5 #define IEEE_ADDR_26 6 #define IEEE_ADDR_27 7 /* Transceiver MAC IEEE Address Register 3 */ #define IEEE_ADDR_3 _SFR_MEM8(0x167) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IEEE_ADDR_3 { unsigned int ieee_addr_3 : 8; /* MAC IEEE Address */ }; #define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3) #endif /* __ASSEMBLER__ */ /* IEEE_ADDR_3 */ #define IEEE_ADDR_30 0 #define IEEE_ADDR_31 1 #define IEEE_ADDR_32 2 #define IEEE_ADDR_33 3 #define IEEE_ADDR_34 4 #define IEEE_ADDR_35 5 #define IEEE_ADDR_36 6 #define IEEE_ADDR_37 7 /* Transceiver MAC IEEE Address Register 4 */ #define IEEE_ADDR_4 _SFR_MEM8(0x168) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IEEE_ADDR_4 { unsigned int ieee_addr_4 : 8; /* MAC IEEE Address */ }; #define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4) #endif /* __ASSEMBLER__ */ /* IEEE_ADDR_4 */ #define IEEE_ADDR_40 0 #define IEEE_ADDR_41 1 #define IEEE_ADDR_42 2 #define IEEE_ADDR_43 3 #define IEEE_ADDR_44 4 #define IEEE_ADDR_45 5 #define IEEE_ADDR_46 6 #define IEEE_ADDR_47 7 /* Transceiver MAC IEEE Address Register 5 */ #define IEEE_ADDR_5 _SFR_MEM8(0x169) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IEEE_ADDR_5 { unsigned int ieee_addr_5 : 8; /* MAC IEEE Address */ }; #define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5) #endif /* __ASSEMBLER__ */ /* IEEE_ADDR_5 */ #define IEEE_ADDR_50 0 #define IEEE_ADDR_51 1 #define IEEE_ADDR_52 2 #define IEEE_ADDR_53 3 #define IEEE_ADDR_54 4 #define IEEE_ADDR_55 5 #define IEEE_ADDR_56 6 #define IEEE_ADDR_57 7 /* Transceiver MAC IEEE Address Register 6 */ #define IEEE_ADDR_6 _SFR_MEM8(0x16A) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IEEE_ADDR_6 { unsigned int ieee_addr_6 : 8; /* MAC IEEE Address */ }; #define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6) #endif /* __ASSEMBLER__ */ /* IEEE_ADDR_6 */ #define IEEE_ADDR_60 0 #define IEEE_ADDR_61 1 #define IEEE_ADDR_62 2 #define IEEE_ADDR_63 3 #define IEEE_ADDR_64 4 #define IEEE_ADDR_65 5 #define IEEE_ADDR_66 6 #define IEEE_ADDR_67 7 /* Transceiver MAC IEEE Address Register 7 */ #define IEEE_ADDR_7 _SFR_MEM8(0x16B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_IEEE_ADDR_7 { unsigned int ieee_addr_7 : 8; /* MAC IEEE Address */ }; #define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7) #endif /* __ASSEMBLER__ */ /* IEEE_ADDR_7 */ #define IEEE_ADDR_70 0 #define IEEE_ADDR_71 1 #define IEEE_ADDR_72 2 #define IEEE_ADDR_73 3 #define IEEE_ADDR_74 4 #define IEEE_ADDR_75 5 #define IEEE_ADDR_76 6 #define IEEE_ADDR_77 7 /* Transceiver Extended Operating Mode Control Register */ #define XAH_CTRL_0 _SFR_MEM8(0x16C) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_XAH_CTRL_0 { unsigned int slotted_operation : 1; /* Set Slotted Acknowledgment */ unsigned int max_csma_retries : 3; /* Maximum Number of CSMA-CA Procedure Repetition Attempts */ unsigned int max_frame_retries : 4; /* Maximum Number of Frame Re-transmission Attempts */ }; #define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0) /* symbolic names */ #define SLOTTED_OP_DIS 0 #define SLOTTED_OP_EN 1 #endif /* __ASSEMBLER__ */ /* XAH_CTRL_0 */ #define SLOTTED_OPERATION 0 #define MAX_CSMA_RETRIES0 1 #define MAX_CSMA_RETRIES1 2 #define MAX_CSMA_RETRIES2 3 #define MAX_FRAME_RETRIES0 4 #define MAX_FRAME_RETRIES1 5 #define MAX_FRAME_RETRIES2 6 #define MAX_FRAME_RETRIES3 7 /* Transceiver CSMA-CA Random Number Generator Seed Register */ #define CSMA_SEED_0 _SFR_MEM8(0x16D) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_CSMA_SEED_0 { unsigned int csma_seed_0 : 8; /* Seed Value for CSMA Random Number Generator */ }; #define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0) #endif /* __ASSEMBLER__ */ /* CSMA_SEED_0 */ #define CSMA_SEED_00 0 #define CSMA_SEED_01 1 #define CSMA_SEED_02 2 #define CSMA_SEED_03 3 #define CSMA_SEED_04 4 #define CSMA_SEED_05 5 #define CSMA_SEED_06 6 #define CSMA_SEED_07 7 /* Transceiver Acknowledgment Frame Control Register 2 */ #define CSMA_SEED_1 _SFR_MEM8(0x16E) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_CSMA_SEED_1 { unsigned int csma_seed_1 : 3; /* Seed Value for CSMA Random Number Generator */ unsigned int aack_i_am_coord : 1; /* Set Personal Area Network Coordinator */ unsigned int aack_dis_ack : 1; /* Disable Acknowledgment Frame Transmission */ unsigned int aack_set_pd : 1; /* Set Frame Pending Sub-field */ unsigned int aack_fvn_mode : 2; /* Acknowledgment Frame Filter Mode */ }; #define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1) #endif /* __ASSEMBLER__ */ /* CSMA_SEED_1 */ #define CSMA_SEED_10 0 #define CSMA_SEED_11 1 #define CSMA_SEED_12 2 #define AACK_I_AM_COORD 3 #define AACK_DIS_ACK 4 #define AACK_SET_PD 5 #define AACK_FVN_MODE0 6 #define AACK_FVN_MODE1 7 /* Transceiver CSMA-CA Back-off Exponent Control Register */ #define CSMA_BE _SFR_MEM8(0x16F) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_CSMA_BE { unsigned int min_be : 4; /* Minimum Back-off Exponent */ unsigned int max_be : 4; /* Maximum Back-off Exponent */ }; #define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE) #endif /* __ASSEMBLER__ */ /* CSMA_BE */ #define MIN_BE0 0 #define MIN_BE1 1 #define MIN_BE2 2 #define MIN_BE3 3 #define MAX_BE0 4 #define MAX_BE1 5 #define MAX_BE2 6 #define MAX_BE3 7 /* Transceiver Digital Test Control Register */ #define TST_CTRL_DIGI _SFR_MEM8(0x176) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TST_CTRL_DIGI { unsigned int tst_ctrl_dig : 4; /* Digital Test Controller Register */ unsigned int : 4; }; #define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI) #endif /* __ASSEMBLER__ */ /* TST_CTRL_DIGI */ #define TST_CTRL_DIG0 0 #define TST_CTRL_DIG1 1 #define TST_CTRL_DIG2 2 #define TST_CTRL_DIG3 3 /* Transceiver Received Frame Length Register */ #define TST_RX_LENGTH _SFR_MEM8(0x17B) #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) struct __reg_TST_RX_LENGTH { unsigned int rx_length : 8; /* Received Frame Length */ }; #define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH) #endif /* __ASSEMBLER__ */ /* TST_RX_LENGTH */ #define RX_LENGTH0 0 #define RX_LENGTH1 1 #define RX_LENGTH2 2 #define RX_LENGTH3 3 #define RX_LENGTH4 4 #define RX_LENGTH5 5 #define RX_LENGTH6 6 #define RX_LENGTH7 7 /* Start of frame buffer */ #define TRXFBST _SFR_MEM8(0x180) /* TRXFBST */ #define TRXFBST0 0 #define TRXFBST1 1 #define TRXFBST2 2 #define TRXFBST3 3 #define TRXFBST4 4 #define TRXFBST5 5 #define TRXFBST6 6 #define TRXFBST7 7 /* End of frame buffer */ #define TRXFBEND _SFR_MEM8(0x1FF) /* TRXFBEND */ #define TRXFBEND0 0 #define TRXFBEND1 1 #define TRXFBEND2 2 #define TRXFBEND3 3 #define TRXFBEND4 4 #define TRXFBEND5 5 #define TRXFBEND6 6 #define TRXFBEND7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define _VECTORS_SIZE 288 /* External Interrupt Request 0 */ #define INT0_vect _VECTOR(1) #define INT0_vect_num 1 /* External Interrupt Request 1 */ #define INT1_vect _VECTOR(2) #define INT1_vect_num 2 /* External Interrupt Request 2 */ #define INT2_vect _VECTOR(3) #define INT2_vect_num 3 /* External Interrupt Request 3 */ #define INT3_vect _VECTOR(4) #define INT3_vect_num 4 /* External Interrupt Request 4 */ #define INT4_vect _VECTOR(5) #define INT4_vect_num 5 /* External Interrupt Request 5 */ #define INT5_vect _VECTOR(6) #define INT5_vect_num 6 /* External Interrupt Request 6 */ #define INT6_vect _VECTOR(7) #define INT6_vect_num 7 /* External Interrupt Request 7 */ #define INT7_vect _VECTOR(8) #define INT7_vect_num 8 /* Pin Change Interrupt Request 0 */ #define PCINT0_vect _VECTOR(9) #define PCINT0_vect_num 9 /* Pin Change Interrupt Request 1 */ #define PCINT1_vect _VECTOR(10) #define PCINT1_vect_num 10 /* Pin Change Interrupt Request 2 */ #define PCINT2_vect _VECTOR(11) #define PCINT2_vect_num 11 /* Watchdog Time-out Interrupt */ #define WDT_vect _VECTOR(12) #define WDT_vect_num 12 /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPA_vect _VECTOR(13) #define TIMER2_COMPA_vect_num 13 /* Timer/Counter2 Compare Match B */ #define TIMER2_COMPB_vect _VECTOR(14) #define TIMER2_COMPB_vect_num 14 /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect _VECTOR(15) #define TIMER2_OVF_vect_num 15 /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect _VECTOR(16) #define TIMER1_CAPT_vect_num 16 /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect _VECTOR(17) #define TIMER1_COMPA_vect_num 17 /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect _VECTOR(18) #define TIMER1_COMPB_vect_num 18 /* Timer/Counter1 Compare Match C */ #define TIMER1_COMPC_vect _VECTOR(19) #define TIMER1_COMPC_vect_num 19 /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect _VECTOR(20) #define TIMER1_OVF_vect_num 20 /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPA_vect _VECTOR(21) #define TIMER0_COMPA_vect_num 21 /* Timer/Counter0 Compare Match B */ #define TIMER0_COMPB_vect _VECTOR(22) #define TIMER0_COMPB_vect_num 22 /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect _VECTOR(23) #define TIMER0_OVF_vect_num 23 /* SPI Serial Transfer Complete */ #define SPI_STC_vect _VECTOR(24) #define SPI_STC_vect_num 24 /* USART0, Rx Complete */ #define USART0_RX_vect _VECTOR(25) #define USART0_RX_vect_num 25 /* USART0 Data register Empty */ #define USART0_UDRE_vect _VECTOR(26) #define USART0_UDRE_vect_num 26 /* USART0, Tx Complete */ #define USART0_TX_vect _VECTOR(27) #define USART0_TX_vect_num 27 /* Analog Comparator */ #define ANALOG_COMP_vect _VECTOR(28) #define ANALOG_COMP_vect_num 28 /* ADC Conversion Complete */ #define ADC_vect _VECTOR(29) #define ADC_vect_num 29 /* EEPROM Ready */ #define EE_READY_vect _VECTOR(30) #define EE_READY_vect_num 30 /* Timer/Counter3 Capture Event */ #define TIMER3_CAPT_vect _VECTOR(31) #define TIMER3_CAPT_vect_num 31 /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPA_vect _VECTOR(32) #define TIMER3_COMPA_vect_num 32 /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPB_vect _VECTOR(33) #define TIMER3_COMPB_vect_num 33 /* Timer/Counter3 Compare Match C */ #define TIMER3_COMPC_vect _VECTOR(34) #define TIMER3_COMPC_vect_num 34 /* Timer/Counter3 Overflow */ #define TIMER3_OVF_vect _VECTOR(35) #define TIMER3_OVF_vect_num 35 /* USART1, Rx Complete */ #define USART1_RX_vect _VECTOR(36) #define USART1_RX_vect_num 36 /* USART1 Data register Empty */ #define USART1_UDRE_vect _VECTOR(37) #define USART1_UDRE_vect_num 37 /* USART1, Tx Complete */ #define USART1_TX_vect _VECTOR(38) #define USART1_TX_vect_num 38 /* 2-wire Serial Interface */ #define TWI_vect _VECTOR(39) #define TWI_vect_num 39 /* Store Program Memory Read */ #define SPM_READY_vect _VECTOR(40) #define SPM_READY_vect_num 40 /* Timer/Counter4 Capture Event */ #define TIMER4_CAPT_vect _VECTOR(41) #define TIMER4_CAPT_vect_num 41 /* Timer/Counter4 Compare Match A */ #define TIMER4_COMPA_vect _VECTOR(42) #define TIMER4_COMPA_vect_num 42 /* Timer/Counter4 Compare Match B */ #define TIMER4_COMPB_vect _VECTOR(43) #define TIMER4_COMPB_vect_num 43 /* Timer/Counter4 Compare Match C */ #define TIMER4_COMPC_vect _VECTOR(44) #define TIMER4_COMPC_vect_num 44 /* Timer/Counter4 Overflow */ #define TIMER4_OVF_vect _VECTOR(45) #define TIMER4_OVF_vect_num 45 /* Timer/Counter5 Capture Event */ #define TIMER5_CAPT_vect _VECTOR(46) #define TIMER5_CAPT_vect_num 46 /* Timer/Counter5 Compare Match A */ #define TIMER5_COMPA_vect _VECTOR(47) #define TIMER5_COMPA_vect_num 47 /* Timer/Counter5 Compare Match B */ #define TIMER5_COMPB_vect _VECTOR(48) #define TIMER5_COMPB_vect_num 48 /* Timer/Counter5 Compare Match C */ #define TIMER5_COMPC_vect _VECTOR(49) #define TIMER5_COMPC_vect_num 49 /* Timer/Counter5 Overflow */ #define TIMER5_OVF_vect _VECTOR(50) #define TIMER5_OVF_vect_num 50 /* USART2, Rx Complete */ #define USART2_RX_vect _VECTOR(51) #define USART2_RX_vect_num 51 /* USART2 Data register Empty */ #define USART2_UDRE_vect _VECTOR(52) #define USART2_UDRE_vect_num 52 /* USART2, Tx Complete */ #define USART2_TX_vect _VECTOR(53) #define USART2_TX_vect_num 53 /* USART3, Rx Complete */ #define USART3_RX_vect _VECTOR(54) #define USART3_RX_vect_num 54 /* USART3 Data register Empty */ #define USART3_UDRE_vect _VECTOR(55) #define USART3_UDRE_vect_num 55 /* USART3, Tx Complete */ #define USART3_TX_vect _VECTOR(56) #define USART3_TX_vect_num 56 /* TRX24 - PLL lock interrupt */ #define TRX24_PLL_LOCK_vect _VECTOR(57) #define TRX24_PLL_LOCK_vect_num 57 /* TRX24 - PLL unlock interrupt */ #define TRX24_PLL_UNLOCK_vect _VECTOR(58) #define TRX24_PLL_UNLOCK_vect_num 58 /* TRX24 - Receive start interrupt */ #define TRX24_RX_START_vect _VECTOR(59) #define TRX24_RX_START_vect_num 59 /* TRX24 - RX_END interrupt */ #define TRX24_RX_END_vect _VECTOR(60) #define TRX24_RX_END_vect_num 60 /* TRX24 - CCA/ED done interrupt */ #define TRX24_CCA_ED_DONE_vect _VECTOR(61) #define TRX24_CCA_ED_DONE_vect_num 61 /* TRX24 - XAH - AMI */ #define TRX24_XAH_AMI_vect _VECTOR(62) #define TRX24_XAH_AMI_vect_num 62 /* TRX24 - TX_END interrupt */ #define TRX24_TX_END_vect _VECTOR(63) #define TRX24_TX_END_vect_num 63 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ #define TRX24_AWAKE_vect _VECTOR(64) #define TRX24_AWAKE_vect_num 64 /* Symbol counter - compare match 1 interrupt */ #define SCNT_CMP1_vect _VECTOR(65) #define SCNT_CMP1_vect_num 65 /* Symbol counter - compare match 2 interrupt */ #define SCNT_CMP2_vect _VECTOR(66) #define SCNT_CMP2_vect_num 66 /* Symbol counter - compare match 3 interrupt */ #define SCNT_CMP3_vect _VECTOR(67) #define SCNT_CMP3_vect_num 67 /* Symbol counter - overflow interrupt */ #define SCNT_OVFL_vect _VECTOR(68) #define SCNT_OVFL_vect_num 68 /* Symbol counter - backoff interrupt */ #define SCNT_BACKOFF_vect _VECTOR(69) #define SCNT_BACKOFF_vect_num 69 /* AES engine ready interrupt */ #define AES_READY_vect _VECTOR(70) #define AES_READY_vect_num 70 /* Battery monitor indicates supply voltage below threshold */ #define BAT_LOW_vect _VECTOR(71) #define BAT_LOW_vect_num 71 /* memory parameters */ #define SPM_PAGESIZE (256) #define RAMSTART (0x200) #define RAMSIZE (0x4000) #define RAMEND (0x41FF) #define XRAMSTART (0x0000) #define XRAMSIZE (0x0000) #define XRAMEND RAMEND #define E2END (0xFFF) #define E2PAGESIZE (0x08) #define FLASHEND (0x1ffff) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* LFUSE Byte */ #define FUSE_CKSEL0 ~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 ~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 ~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 ~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 ~_BV(4) /* Select start-up time */ #define FUSE_SUT1 ~_BV(5) /* Select start-up time */ #define FUSE_CKOUT ~_BV(6) /* Clock output */ #define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) /* HFUSE Byte */ #define FUSE_BOOTRST ~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 ~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 ~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON ~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN ~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN ~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* EFUSE Byte */ #define FUSE_BODLEVEL0 ~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 ~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 ~_BV(2) /* Brown-out Detector trigger level */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0xA7 #define SIGNATURE_2 0x01 #endif /* _AVR_IOM128RFA1_H_ */ avr-libc-1.8.0.orig/include/avr/iom324pa.h0000644000000000000000000006631111732702554015003 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom324pa.h 2063 2009-11-18 22:06:28Z arcanum $ */ /* avr/iom324pa.h - definitions for ATmega324PA */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom324pa.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega324PA_H_ #define _AVR_ATmega324PA_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR0 _SFR_IO8(0x2C) #define SPR00 0 #define SPR10 1 #define CPHA0 2 #define CPOL0 3 #define MSTR0 4 #define DORD0 5 #define SPE0 6 #define SPIE0 7 #define SPSR0 _SFR_IO8(0x2D) #define SPI2X0 0 #define WCOL0 6 #define SPIF0 7 #define SPDR0 _SFR_IO8(0x2E) #define SPDRB0 0 #define SPDRB1 1 #define SPDRB2 2 #define SPDRB3 3 #define SPDRB4 4 #define SPDRB5 5 #define SPDRB6 6 #define SPDRB7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 #define BODS 6 #define JTD 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRUSART1 4 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #define PCMSK3 _SFR_MEM8(0x73) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define PCINT27 3 #define PCINT28 4 #define PCINT29 5 #define PCINT30 6 #define PCINT31 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2A_0 0 #define OCR2A_1 1 #define OCR2A_2 2 #define OCR2A_3 3 #define OCR2A_4 4 #define OCR2A_5 5 #define OCR2A_6 6 #define OCR2A_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2B_0 0 #define OCR2B_1 1 #define OCR2B_2 2 #define OCR2B_3 3 #define OCR2B_4 4 #define OCR2B_5 5 #define OCR2B_6 6 #define OCR2B_7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL01 7 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define _UBRR0 0 #define _UBRR1 1 #define UBRR2 2 #define UBRR3 3 #define UBRR4 4 #define UBRR5 5 #define UBRR6 6 #define UBRR7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR8 0 #define UBRR9 1 #define UBRR10 2 #define UBRR11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR0_0 0 #define UDR0_1 1 #define UDR0_2 2 #define UDR0_3 3 #define UDR0_4 4 #define UDR0_5 5 #define UDR0_6 6 #define UDR0_7 7 #define UCSR1A _SFR_MEM8(0xC8) #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 #define UCSR1B _SFR_MEM8(0xC9) #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 #define UCSR1C _SFR_MEM8(0xCA) #define UCPOL1 0 #define UCSZ10 1 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR_0 0 #define UBRR_1 1 #define UBRR_2 2 #define UBRR_3 3 #define UBRR_4 4 #define UBRR_5 5 #define UBRR_6 6 #define UBRR_7 7 #define UBRR1H _SFR_MEM8(0xCD) #define UBRR_8 0 #define UBRR_9 1 #define UBRR_10 2 #define UBRR_11 3 #define UDR1 _SFR_MEM8(0xCE) #define UDR1_0 0 #define UDR1_1 1 #define UDR1_2 2 #define UDR1_3 3 #define UDR1_4 4 #define UDR1_5 5 #define UDR1_6 6 #define UDR1_7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define PCINT0_vect_num 4 #define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 5 #define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 6 #define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */ #define PCINT3_vect_num 7 #define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 9 #define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 10 #define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ #define TIMER2_OVF_vect_num 11 #define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 12 #define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 16 #define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 17 #define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 18 #define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 19 #define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ #define USART0_RX_vect_num 20 #define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ #define USART0_UDRE_vect_num 21 #define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ #define USART0_TX_vect_num 22 #define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ #define ADC_vect_num 24 #define ADC_vect _VECTOR(24) /* ADC Conversion Complete */ #define EE_READY_vect_num 25 #define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ #define TWI_vect_num 26 #define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ #define SPM_READY_vect_num 27 #define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ #define USART1_RX_vect_num 28 #define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */ #define USART1_UDRE_vect_num 29 #define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */ #define USART1_TX_vect_num 30 #define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (31 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (2048) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (0x0) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x3FF) #define E2PAGESIZE (4) #define FLASHEND (0x7FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x11 /* Device Pin Definitions */ #define MOSI_DDR DDRB #define MOSI_PORT PORTB #define MOSI_PIN PINB #define MOSI_BIT 5 #define PCINT13_DDR DDRB #define PCINT13_PORT PORTB #define PCINT13_PIN PINB #define PCINT13_BIT 5 #define MISO_DDR DDRB #define MISO_PORT PORTB #define MISO_PIN PINB #define MISO_BIT 6 #define PCINT14_DDR DDRB #define PCINT14_PORT PORTB #define PCINT14_PIN PINB #define PCINT14_BIT 6 #define SCK_DDR DDRB #define SCK_PORT PORTB #define SCK_PIN PINB #define SCK_BIT 7 #define PCINT15_DDR DDRB #define PCINT15_PORT PORTB #define PCINT15_PIN PINB #define PCINT15_BIT 7 #define RXD_DDR DDRD #define RXD_PORT PORTD #define RXD_PIN PIND #define RXD_BIT 0 #define PCINT24_DDR DDRD #define PCINT24_PORT PORTD #define PCINT24_PIN PIND #define PCINT24_BIT 0 #define TXD_DDR DDRD #define TXD_PORT PORTD #define TXD_PIN PIND #define TXD_BIT 1 #define PCINT25_DDR DDRD #define PCINT25_PORT PORTD #define PCINT25_PIN PIND #define PCINT25_BIT 1 #define INT0_DDR DDRD #define INT0_PORT PORTD #define INT0_PIN PIND #define INT0_BIT 2 #define PCINT26_DDR DDRD #define PCINT26_PORT PORTD #define PCINT26_PIN PIND #define PCINT26_BIT 2 #define INT1_DDR DDRD #define INT1_PORT PORTD #define INT1_PIN PIND #define INT1_BIT 3 #define PCINT27_DDR DDRD #define PCINT27_PORT PORTD #define PCINT27_PIN PIND #define PCINT27_BIT 3 #define OC1B_DDR DDRD #define OC1B_PORT PORTD #define OC1B_PIN PIND #define OC1B_BIT 4 #define PCINT28_DDR DDRD #define PCINT28_PORT PORTD #define PCINT28_PIN PIND #define PCINT28_BIT 4 #define OC1A_DDR DDRD #define OC1A_PORT PORTD #define OC1A_PIN PIND #define OC1A_BIT 5 #define PCINT29_DDR DDRD #define PCINT29_PORT PORTD #define PCINT29_PIN PIND #define PCINT29_BIT 5 #define ICP_DDR DDRD #define ICP_PORT PORTD #define ICP_PIN PIND #define ICP_BIT 6 #define OC2B_DDR DDRD #define OC2B_PORT PORTD #define OC2B_PIN PIND #define OC2B_BIT 6 #define PCINT30_DDR DDRD #define PCINT30_PORT PORTD #define PCINT30_PIN PIND #define PCINT30_BIT 6 #define OC2A_DDR DDRD #define OC2A_PORT PORTD #define OC2A_PIN PIND #define OC2A_BIT 7 #define PCINT31_DDR DDRD #define PCINT31_PORT PORTD #define PCINT31_PIN PIND #define PCINT31_BIT 7 #define SCL_DDR DDRC #define SCL_PORT PORTC #define SCL_PIN PINC #define SCL_BIT 0 #define PCINT16_DDR DDRC #define PCINT16_PORT PORTC #define PCINT16_PIN PINC #define PCINT16_BIT 0 #define SDA_DDR DDRC #define SDA_PORT PORTC #define SDA_PIN PINC #define SDA_BIT 1 #define PCINT17_DDR DDRC #define PCINT17_PORT PORTC #define PCINT17_PIN PINC #define PCINT17_BIT 1 #define PCINT18_DDR DDRC #define PCINT18_PORT PORTC #define PCINT18_PIN PINC #define PCINT18_BIT 2 #define PCINT19_DDR DDRC #define PCINT19_PORT PORTC #define PCINT19_PIN PINC #define PCINT19_BIT 3 #define PCINT20_DDR DDRC #define PCINT20_PORT PORTC #define PCINT20_PIN PINC #define PCINT20_BIT 4 #define PCINT21_DDR DDRC #define PCINT21_PORT PORTC #define PCINT21_PIN PINC #define PCINT21_BIT 5 #define PCINT22_DDR DDRC #define PCINT22_PORT PORTC #define PCINT22_PIN PINC #define PCINT22_BIT 6 #define PCINT23_DDR DDRC #define PCINT23_PORT PORTC #define PCINT23_PIN PINC #define PCINT23_BIT 7 #define ADC7_DDR DDRA #define ADC7_PORT PORTA #define ADC7_PIN PINA #define ADC7_BIT 7 #define PCINT7_DDR DDRA #define PCINT7_PORT PORTA #define PCINT7_PIN PINA #define PCINT7_BIT 7 #define ADC6_DDR DDRA #define ADC6_PORT PORTA #define ADC6_PIN PINA #define ADC6_BIT 6 #define PCINT6_DDR DDRA #define PCINT6_PORT PORTA #define PCINT6_PIN PINA #define PCINT6_BIT 6 #define ADC5_DDR DDRA #define ADC5_PORT PORTA #define ADC5_PIN PINA #define ADC5_BIT 5 #define PCINT5_DDR DDRA #define PCINT5_PORT PORTA #define PCINT5_PIN PINA #define PCINT5_BIT 5 #define ADC4_DDR DDRA #define ADC4_PORT PORTA #define ADC4_PIN PINA #define ADC4_BIT 4 #define PCINT4_DDR DDRA #define PCINT4_PORT PORTA #define PCINT4_PIN PINA #define PCINT4_BIT 4 #define ADC3_DDR DDRA #define ADC3_PORT PORTA #define ADC3_PIN PINA #define ADC3_BIT 3 #define PCINT3_DDR DDRA #define PCINT3_PORT PORTA #define PCINT3_PIN PINA #define PCINT3_BIT 3 #define ADC2_DDR DDRA #define ADC2_PORT PORTA #define ADC2_PIN PINA #define ADC2_BIT 2 #define PCINT2_DDR DDRA #define PCINT2_PORT PORTA #define PCINT2_PIN PINA #define PCINT2_BIT 2 #define ADC1_DDR DDRA #define ADC1_PORT PORTA #define ADC1_PIN PINA #define ADC1_BIT 1 #define PCINT1_DDR DDRA #define PCINT1_PORT PORTA #define PCINT1_PIN PINA #define PCINT1_BIT 1 #define ADC0_DDR DDRA #define ADC0_PORT PORTA #define ADC0_PIN PINA #define ADC0_BIT 0 #define PCINT0_DDR DDRA #define PCINT0_PORT PORTA #define PCINT0_PIN PINA #define PCINT0_BIT 0 #define XCK_DDR DDRB #define XCK_PORT PORTB #define XCK_PIN PINB #define XCK_BIT 0 #define T0_DDR DDRB #define T0_PORT PORTB #define T0_PIN PINB #define T0_BIT 0 #define PCINT8_DDR DDRB #define PCINT8_PORT PORTB #define PCINT8_PIN PINB #define PCINT8_BIT 0 #define T1_DDR DDRB #define T1_PORT PORTB #define T1_PIN PINB #define T1_BIT 1 #define CLKO_DDR DDRB #define CLKO_PORT PORTB #define CLKO_PIN PINB #define CLKO_BIT 1 #define PCINT9_DDR DDRB #define PCINT9_PORT PORTB #define PCINT9_PIN PINB #define PCINT9_BIT 1 #define AIN0_DDR DDRB #define AIN0_PORT PORTB #define AIN0_PIN PINB #define AIN0_BIT 2 #define INT2_DDR DDRB #define INT2_PORT PORTB #define INT2_PIN PINB #define INT2_BIT 2 #define PCINT10_DDR DDRB #define PCINT10_PORT PORTB #define PCINT10_PIN PINB #define PCINT10_BIT 2 #define AIN1_DDR DDRB #define AIN1_PORT PORTB #define AIN1_PIN PINB #define AIN1_BIT 3 #define OC0A_DDR DDRB #define OC0A_PORT PORTB #define OC0A_PIN PINB #define OC0A_BIT 3 #define PCINT11_DDR DDRB #define PCINT11_PORT PORTB #define PCINT11_PIN PINB #define PCINT11_BIT 3 #define SS_DDR DDRB #define SS_PORT PORTB #define SS_PIN PINB #define SS_BIT 4 #define OC0B_DDR DDRB #define OC0B_PORT PORTB #define OC0B_PIN PINB #define OC0B_BIT 4 #define PCINT12_DDR DDRB #define PCINT12_PORT PORTB #define PCINT12_PIN PINB #define PCINT12_BIT 4 #endif /* _AVR_ATmega324PA_H_ */ avr-libc-1.8.0.orig/include/avr/iom2560.h0000644000000000000000000000642111732702554014542 0ustar /* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id */ /* avr/iom2560.h - definitions for ATmega2560 */ #ifndef _AVR_IOM2560_H_ #define _AVR_IOM2560_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x21FF #define XRAMEND 0xFFFF #define E2END 0xFFF #define E2PAGESIZE 8 #define FLASHEND 0x3FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x98 #define SIGNATURE_2 0x01 #endif /* _AVR_IOM2560_H_ */ avr-libc-1.8.0.orig/include/avr/iox64a1.h0000644000000000000000000113476711732702554014654 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox64a1.h 2260 2011-11-02 16:53:30Z arcanum $ */ /* avr/iox64a1.h - definitions for ATxmega64A1 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox64a1.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega64A1_H_ #define _AVR_ATxmega64A1_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* JTAG User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t GAINCAL; /* Gain Calibration */ register8_t OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ #define DACA (*(DAC_t *) 0x0300) /* Digitalto Analog Converter A */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTH (*(PORT_t *) 0x06E0) /* Port H */ #define PORTJ (*(PORT_t *) 0x0700) /* Port J */ #define PORTK (*(PORT_t *) 0x0720) /* Port K */ #define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* ADCB - Analog to Digital Converter B */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) #define ADCB_EVCTRL _SFR_MEM8(0x0243) #define ADCB_PRESCALER _SFR_MEM8(0x0244) #define ADCB_INTFLAGS _SFR_MEM8(0x0246) #define ADCB_CAL _SFR_MEM16(0x024C) #define ADCB_CH0RES _SFR_MEM16(0x0250) #define ADCB_CH1RES _SFR_MEM16(0x0252) #define ADCB_CH2RES _SFR_MEM16(0x0254) #define ADCB_CH3RES _SFR_MEM16(0x0256) #define ADCB_CMP _SFR_MEM16(0x0258) #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) /* DACA - Digitalto Analog Converter A */ #define DACA_CTRLA _SFR_MEM8(0x0300) #define DACA_CTRLB _SFR_MEM8(0x0301) #define DACA_CTRLC _SFR_MEM8(0x0302) #define DACA_EVCTRL _SFR_MEM8(0x0303) #define DACA_TIMCTRL _SFR_MEM8(0x0304) #define DACA_STATUS _SFR_MEM8(0x0305) #define DACA_GAINCAL _SFR_MEM8(0x0308) #define DACA_OFFSETCAL _SFR_MEM8(0x0309) #define DACA_CH0DATA _SFR_MEM16(0x0318) #define DACA_CH1DATA _SFR_MEM16(0x031A) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_GAINCAL _SFR_MEM8(0x0328) #define DACB_OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* EBI - External Bus Interface */ #define EBI_CTRL _SFR_MEM8(0x0440) #define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) #define EBI_REFRESH _SFR_MEM16(0x0444) #define EBI_INITDLY _SFR_MEM16(0x0446) #define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) #define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) #define EBI_CS0_CTRLA _SFR_MEM8(0x0450) #define EBI_CS0_CTRLB _SFR_MEM8(0x0451) #define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) #define EBI_CS1_CTRLA _SFR_MEM8(0x0454) #define EBI_CS1_CTRLB _SFR_MEM8(0x0455) #define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) #define EBI_CS2_CTRLA _SFR_MEM8(0x0458) #define EBI_CS2_CTRLB _SFR_MEM8(0x0459) #define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) #define EBI_CS3_CTRLA _SFR_MEM8(0x045C) #define EBI_CS3_CTRLB _SFR_MEM8(0x045D) #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWID - Two-Wire Interface D */ #define TWID_CTRL _SFR_MEM8(0x0490) #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) #define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) #define TWID_MASTER_STATUS _SFR_MEM8(0x0494) #define TWID_MASTER_BAUD _SFR_MEM8(0x0495) #define TWID_MASTER_ADDR _SFR_MEM8(0x0496) #define TWID_MASTER_DATA _SFR_MEM8(0x0497) #define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) #define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) #define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) #define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) #define TWID_SLAVE_DATA _SFR_MEM8(0x049C) #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* TWIF - Two-Wire Interface F */ #define TWIF_CTRL _SFR_MEM8(0x04B0) #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) #define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) #define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) #define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) #define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) #define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) #define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) #define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) #define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) #define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTH - Port H */ #define PORTH_DIR _SFR_MEM8(0x06E0) #define PORTH_DIRSET _SFR_MEM8(0x06E1) #define PORTH_DIRCLR _SFR_MEM8(0x06E2) #define PORTH_DIRTGL _SFR_MEM8(0x06E3) #define PORTH_OUT _SFR_MEM8(0x06E4) #define PORTH_OUTSET _SFR_MEM8(0x06E5) #define PORTH_OUTCLR _SFR_MEM8(0x06E6) #define PORTH_OUTTGL _SFR_MEM8(0x06E7) #define PORTH_IN _SFR_MEM8(0x06E8) #define PORTH_INTCTRL _SFR_MEM8(0x06E9) #define PORTH_INT0MASK _SFR_MEM8(0x06EA) #define PORTH_INT1MASK _SFR_MEM8(0x06EB) #define PORTH_INTFLAGS _SFR_MEM8(0x06EC) #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) #define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) #define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) #define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) /* PORTJ - Port J */ #define PORTJ_DIR _SFR_MEM8(0x0700) #define PORTJ_DIRSET _SFR_MEM8(0x0701) #define PORTJ_DIRCLR _SFR_MEM8(0x0702) #define PORTJ_DIRTGL _SFR_MEM8(0x0703) #define PORTJ_OUT _SFR_MEM8(0x0704) #define PORTJ_OUTSET _SFR_MEM8(0x0705) #define PORTJ_OUTCLR _SFR_MEM8(0x0706) #define PORTJ_OUTTGL _SFR_MEM8(0x0707) #define PORTJ_IN _SFR_MEM8(0x0708) #define PORTJ_INTCTRL _SFR_MEM8(0x0709) #define PORTJ_INT0MASK _SFR_MEM8(0x070A) #define PORTJ_INT1MASK _SFR_MEM8(0x070B) #define PORTJ_INTFLAGS _SFR_MEM8(0x070C) #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) #define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) #define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) #define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) /* PORTK - Port K */ #define PORTK_DIR _SFR_MEM8(0x0720) #define PORTK_DIRSET _SFR_MEM8(0x0721) #define PORTK_DIRCLR _SFR_MEM8(0x0722) #define PORTK_DIRTGL _SFR_MEM8(0x0723) #define PORTK_OUT _SFR_MEM8(0x0724) #define PORTK_OUTSET _SFR_MEM8(0x0725) #define PORTK_OUTCLR _SFR_MEM8(0x0726) #define PORTK_OUTTGL _SFR_MEM8(0x0727) #define PORTK_IN _SFR_MEM8(0x0728) #define PORTK_INTCTRL _SFR_MEM8(0x0729) #define PORTK_INT0MASK _SFR_MEM8(0x072A) #define PORTK_INT1MASK _SFR_MEM8(0x072B) #define PORTK_INTFLAGS _SFR_MEM8(0x072C) #define PORTK_PIN0CTRL _SFR_MEM8(0x0730) #define PORTK_PIN1CTRL _SFR_MEM8(0x0731) #define PORTK_PIN2CTRL _SFR_MEM8(0x0732) #define PORTK_PIN3CTRL _SFR_MEM8(0x0733) #define PORTK_PIN4CTRL _SFR_MEM8(0x0734) #define PORTK_PIN5CTRL _SFR_MEM8(0x0735) #define PORTK_PIN6CTRL _SFR_MEM8(0x0736) #define PORTK_PIN7CTRL _SFR_MEM8(0x0737) /* PORTQ - Port Q */ #define PORTQ_DIR _SFR_MEM8(0x07C0) #define PORTQ_DIRSET _SFR_MEM8(0x07C1) #define PORTQ_DIRCLR _SFR_MEM8(0x07C2) #define PORTQ_DIRTGL _SFR_MEM8(0x07C3) #define PORTQ_OUT _SFR_MEM8(0x07C4) #define PORTQ_OUTSET _SFR_MEM8(0x07C5) #define PORTQ_OUTCLR _SFR_MEM8(0x07C6) #define PORTQ_OUTTGL _SFR_MEM8(0x07C7) #define PORTQ_IN _SFR_MEM8(0x07C8) #define PORTQ_INTCTRL _SFR_MEM8(0x07C9) #define PORTQ_INT0MASK _SFR_MEM8(0x07CA) #define PORTQ_INT1MASK _SFR_MEM8(0x07CB) #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) #define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) #define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) #define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* TCE1 - Timer/Counter E1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) #define TCE1_CTRLD _SFR_MEM8(0x0A43) #define TCE1_CTRLE _SFR_MEM8(0x0A44) #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) #define TCE1_TEMP _SFR_MEM8(0x0A4F) #define TCE1_CNT _SFR_MEM16(0x0A60) #define TCE1_PER _SFR_MEM16(0x0A66) #define TCE1_CCA _SFR_MEM16(0x0A68) #define TCE1_CCB _SFR_MEM16(0x0A6A) #define TCE1_PERBUF _SFR_MEM16(0x0A76) #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) #define USARTE1_CTRLB _SFR_MEM8(0x0AB4) #define USARTE1_CTRLC _SFR_MEM8(0x0AB5) #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /* TCF1 - Timer/Counter F1 */ #define TCF1_CTRLA _SFR_MEM8(0x0B40) #define TCF1_CTRLB _SFR_MEM8(0x0B41) #define TCF1_CTRLC _SFR_MEM8(0x0B42) #define TCF1_CTRLD _SFR_MEM8(0x0B43) #define TCF1_CTRLE _SFR_MEM8(0x0B44) #define TCF1_INTCTRLA _SFR_MEM8(0x0B46) #define TCF1_INTCTRLB _SFR_MEM8(0x0B47) #define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) #define TCF1_CTRLFSET _SFR_MEM8(0x0B49) #define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) #define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) #define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) #define TCF1_TEMP _SFR_MEM8(0x0B4F) #define TCF1_CNT _SFR_MEM16(0x0B60) #define TCF1_PER _SFR_MEM16(0x0B66) #define TCF1_CCA _SFR_MEM16(0x0B68) #define TCF1_CCB _SFR_MEM16(0x0B6A) #define TCF1_PERBUF _SFR_MEM16(0x0B76) #define TCF1_CCABUF _SFR_MEM16(0x0B78) #define TCF1_CCBBUF _SFR_MEM16(0x0B7A) /* HIRESF - High-Resolution Extension F */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) /* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) #define USARTF1_CTRLB _SFR_MEM8(0x0BB4) #define USARTF1_CTRLC _SFR_MEM8(0x0BB5) #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) /* SPIF - Serial Peripheral Interface F */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) #define SPIF_DATA _SFR_MEM8(0x0BC3) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ #define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ #define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ #define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ #define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ #define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ #define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ #define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ #define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ #define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ #define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ #define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ #define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ #define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ #define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ #define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ #define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ #define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ #define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ #define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* ACB interrupt vectors */ #define ACB_AC0_vect_num 36 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ #define ACB_AC1_vect_num 37 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ #define ACB_ACW_vect_num 38 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ /* ADCB interrupt vectors */ #define ADCB_CH0_vect_num 39 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ #define ADCB_CH1_vect_num 40 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ #define ADCB_CH2_vect_num 41 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ #define ADCB_CH3_vect_num 42 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* SPIE interrupt vectors */ #define SPIE_INT_vect_num 57 #define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* USARTE1 interrupt vectors */ #define USARTE1_RXC_vect_num 61 #define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ #define USARTE1_DRE_vect_num 62 #define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ #define USARTE1_TXC_vect_num 63 #define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TWID interrupt vectors */ #define TWID_TWIS_vect_num 75 #define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ #define TWID_TWIM_vect_num 76 #define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ /* PORTQ interrupt vectors */ #define PORTQ_INT0_vect_num 94 #define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ #define PORTQ_INT1_vect_num 95 #define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ /* PORTH interrupt vectors */ #define PORTH_INT0_vect_num 96 #define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ #define PORTH_INT1_vect_num 97 #define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ /* PORTJ interrupt vectors */ #define PORTJ_INT0_vect_num 98 #define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ #define PORTJ_INT1_vect_num 99 #define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ /* PORTK interrupt vectors */ #define PORTK_INT0_vect_num 100 #define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ #define PORTK_INT1_vect_num 101 #define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TWIF interrupt vectors */ #define TWIF_TWIS_vect_num 106 #define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ #define TWIF_TWIM_vect_num 107 #define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ /* TCF1 interrupt vectors */ #define TCF1_OVF_vect_num 114 #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ #define TCF1_ERR_vect_num 115 #define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ #define TCF1_CCA_vect_num 116 #define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ #define TCF1_CCB_vect_num 117 #define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ /* SPIF interrupt vectors */ #define SPIF_INT_vect_num 118 #define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ /* USARTF0 interrupt vectors */ #define USARTF0_RXC_vect_num 119 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ #define USARTF0_DRE_vect_num 120 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ #define USARTF0_TXC_vect_num 121 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ /* USARTF1 interrupt vectors */ #define USARTF1_RXC_vect_num 122 #define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ #define USARTF1_DRE_vect_num 123 #define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ #define USARTF1_TXC_vect_num 124 #define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (125 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (69632) #define PROGMEM_PAGE_SIZE (256) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (65536) #define APP_SECTION_PAGE_SIZE (256) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x0F000) #define APPTABLE_SECTION_SIZE (4096) #define APPTABLE_SECTION_PAGE_SIZE (256) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x10000) #define BOOT_SECTION_SIZE (4096) #define BOOT_SECTION_PAGE_SIZE (256) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (16777216) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (2048) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (4096) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EXTERNAL_SRAM_START (0x3000) #define EXTERNAL_SRAM_SIZE (16764928) #define EXTERNAL_SRAM_PAGE_SIZE (0) #define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (2048) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (256) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND EXTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ #define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ #define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ #define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ #define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ #define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ #define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ #define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x4E #endif /* _AVR_ATxmega64A1_H_ */ avr-libc-1.8.0.orig/include/avr/eeprom.h0000644000000000000000000005171311732702554014734 0ustar /* Copyright (c) 2002, 2003, 2004, 2007 Marek Michalkiewicz Copyright (c) 2005, 2006 Bjoern Haase Copyright (c) 2008 Atmel Corporation Copyright (c) 2008 Wouter van Gulik Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eeprom.h 2211 2011-02-14 14:04:25Z aboyapati $ */ #ifndef _AVR_EEPROM_H_ #define _AVR_EEPROM_H_ 1 #include #if !E2END && !defined(__DOXYGEN__) && !defined(__COMPILING_AVR_LIBC__) # warning "Device does not have EEPROM available." #else #ifndef __DOXYGEN__ #if defined (__AVR_AT94K__) # define _EEPROM_SUFFIX _at94k #elif defined (__AVR_AT43USB320__) # define _EEPROM_SUFFIX _43u320 #elif defined (__AVR_AT43USB355__) # define _EEPROM_SUFFIX _43u355 #elif defined (__AVR_AT76C711__) # define _EEPROM_SUFFIX _76c711 #elif defined (__AVR_AT86RF401__) # define _EEPROM_SUFFIX _86r401 #elif defined (__AVR_AT90PWM1__) # define _EEPROM_SUFFIX _90pwm1 #elif defined (__AVR_AT90PWM2__) # define _EEPROM_SUFFIX _90pwm2 #elif defined (__AVR_AT90PWM2B__) # define _EEPROM_SUFFIX _90pwm2b #elif defined (__AVR_AT90PWM3__) # define _EEPROM_SUFFIX _90pwm3 #elif defined (__AVR_AT90PWM3B__) # define _EEPROM_SUFFIX _90pwm3b #elif defined (__AVR_AT90PWM216__) # define _EEPROM_SUFFIX _90pwm216 #elif defined (__AVR_AT90PWM316__) # define _EEPROM_SUFFIX _90pwm316 #elif defined (__AVR_AT90PWM81__) # define _EEPROM_SUFFIX _90pwm81 #elif defined (__AVR_ATmega16M1__) # define _EEPROM_SUFFIX _m16m1 #elif defined (__AVR_ATmega8U2__) # define _EEPROM_SUFFIX _m8u2 #elif defined (__AVR_ATmega16U2__) # define _EEPROM_SUFFIX _m16u2 #elif defined (__AVR_ATmega16U4__) # define _EEPROM_SUFFIX _m16u4 #elif defined (__AVR_ATmega32C1__) # define _EEPROM_SUFFIX _m32c1 #elif defined (__AVR_ATmega32M1__) # define _EEPROM_SUFFIX _m32m1 #elif defined (__AVR_ATmega32U2__) # define _EEPROM_SUFFIX _m32u2 #elif defined (__AVR_ATmega32U4__) # define _EEPROM_SUFFIX _m32u4 #elif defined (__AVR_ATmega32U6__) # define _EEPROM_SUFFIX _m32u6 #elif defined (__AVR_ATmega64C1__) # define _EEPROM_SUFFIX _m64c1 #elif defined (__AVR_ATmega64M1__) # define _EEPROM_SUFFIX _m64m1 #elif defined (__AVR_ATmega128__) # define _EEPROM_SUFFIX _m128 #elif defined (__AVR_ATmega1280__) # define _EEPROM_SUFFIX _m1280 #elif defined (__AVR_ATmega1281__) # define _EEPROM_SUFFIX _m1281 #elif defined (__AVR_ATmega1284P__) # define _EEPROM_SUFFIX _m1284p #elif defined (__AVR_ATmega128RFA1__) # define _EEPROM_SUFFIX _m128rfa1 #elif defined (__AVR_ATmega2560__) # define _EEPROM_SUFFIX _m2560 #elif defined (__AVR_ATmega2561__) # define _EEPROM_SUFFIX _m2561 #elif defined (__AVR_AT90CAN32__) # define _EEPROM_SUFFIX _can32 #elif defined (__AVR_AT90CAN64__) # define _EEPROM_SUFFIX _can64 #elif defined (__AVR_AT90CAN128__) # define _EEPROM_SUFFIX _can128 #elif defined (__AVR_AT90USB82__) # define _EEPROM_SUFFIX _usb82 #elif defined (__AVR_AT90USB162__) # define _EEPROM_SUFFIX _usb162 #elif defined (__AVR_AT90USB646__) # define _EEPROM_SUFFIX _usb646 #elif defined (__AVR_AT90USB647__) # define _EEPROM_SUFFIX _usb647 #elif defined (__AVR_AT90USB1286__) # define _EEPROM_SUFFIX _usb1286 #elif defined (__AVR_AT90USB1287__) # define _EEPROM_SUFFIX _usb1287 #elif defined (__AVR_ATmega64__) # define _EEPROM_SUFFIX _m64 #elif defined (__AVR_ATmega640__) # define _EEPROM_SUFFIX _m640 #elif defined (__AVR_ATmega644__) # define _EEPROM_SUFFIX _m644 #elif defined (__AVR_ATmega644A__) # define _EEPROM_SUFFIX _m644a #elif defined (__AVR_ATmega644P__) # define _EEPROM_SUFFIX _m644p #elif defined (__AVR_ATmega644PA__) # define _EEPROM_SUFFIX _m644pa #elif defined (__AVR_ATmega645__) # define _EEPROM_SUFFIX _m645 #elif defined (__AVR_ATmega645A__) # define _EEPROM_SUFFIX _m645a #elif defined (__AVR_ATmega645P__) # define _EEPROM_SUFFIX _m645p #elif defined (__AVR_ATmega6450__) # define _EEPROM_SUFFIX _m6450 #elif defined (__AVR_ATmega6450A__) # define _EEPROM_SUFFIX _m6450a #elif defined (__AVR_ATmega6450P__) # define _EEPROM_SUFFIX _m6450p #elif defined (__AVR_ATmega649__) # define _EEPROM_SUFFIX _m649 #elif defined (__AVR_ATmega649A__) # define _EEPROM_SUFFIX _m649a #elif defined (__AVR_ATmega649P__) # define _EEPROM_SUFFIX _m649p #elif defined (__AVR_ATmega6490__) # define _EEPROM_SUFFIX _m6490 #elif defined (__AVR_ATmega6490A__) # define _EEPROM_SUFFIX _m6490a #elif defined (__AVR_ATmega6490P__) # define _EEPROM_SUFFIX _m6490p #elif defined (__AVR_ATmega103__) # define _EEPROM_SUFFIX _m103 #elif defined (__AVR_ATmega32__) # define _EEPROM_SUFFIX _m32 #elif defined (__AVR_ATmega323__) # define _EEPROM_SUFFIX _m323 #elif defined (__AVR_ATmega324A__) # define _EEPROM_SUFFIX _m324a #elif defined (__AVR_ATmega324P__) # define _EEPROM_SUFFIX _m324p #elif defined (__AVR_ATmega324PA__) # define _EEPROM_SUFFIX _m324pa #elif defined (__AVR_ATmega325__) # define _EEPROM_SUFFIX _m325 #elif defined (__AVR_ATmega325A__) # define _EEPROM_SUFFIX _m325a #elif defined (__AVR_ATmega325P__) # define _EEPROM_SUFFIX _m325p #elif defined (__AVR_ATmega3250__) # define _EEPROM_SUFFIX _m3250 #elif defined (__AVR_ATmega3250A__) # define _EEPROM_SUFFIX _m3250a #elif defined (__AVR_ATmega3250P__) # define _EEPROM_SUFFIX _m3250p #elif defined (__AVR_ATmega328__) # define _EEPROM_SUFFIX _m328 #elif defined (__AVR_ATmega328P__) # define _EEPROM_SUFFIX _m328p #elif defined (__AVR_ATmega329__) # define _EEPROM_SUFFIX _m329 #elif defined (__AVR_ATmega329A__) # define _EEPROM_SUFFIX _m329a #elif defined (__AVR_ATmega329P__) # define _EEPROM_SUFFIX _m329p #elif defined (__AVR_ATmega329PA__) # define _EEPROM_SUFFIX _m329pa #elif defined (__AVR_ATmega3290__) # define _EEPROM_SUFFIX _m3290 #elif defined (__AVR_ATmega3290A__) # define _EEPROM_SUFFIX _m3290a #elif defined (__AVR_ATmega3290P__) # define _EEPROM_SUFFIX _m3290p #elif defined (__AVR_ATmega32HVB__) # define _EEPROM_SUFFIX _m32hvb #elif defined (__AVR_ATmega32HVBREVB__) # define _EEPROM_SUFFIX _m32hvbrevb #elif defined (__AVR_ATmega64HVE__) # define _EEPROM_SUFFIX _m64hve #elif defined (__AVR_ATmega406__) # define _EEPROM_SUFFIX _m406 #elif defined (__AVR_ATmega16__) # define _EEPROM_SUFFIX _m16 #elif defined (__AVR_ATmega16A__) # define _EEPROM_SUFFIX _m16a #elif defined (__AVR_ATmega161__) # define _EEPROM_SUFFIX _m161 #elif defined (__AVR_ATmega162__) # define _EEPROM_SUFFIX _m162 #elif defined (__AVR_ATmega163__) # define _EEPROM_SUFFIX _m163 #elif defined (__AVR_ATmega164__) # define _EEPROM_SUFFIX _m164 #elif defined (__AVR_ATmega164P__) # define _EEPROM_SUFFIX _m164p #elif defined (__AVR_ATmega165__) # define _EEPROM_SUFFIX _m165 #elif defined (__AVR_ATmega165A__) # define _EEPROM_SUFFIX _m165a #elif defined (__AVR_ATmega165P__) # define _EEPROM_SUFFIX _m165p #elif defined (__AVR_ATmega168__) # define _EEPROM_SUFFIX _m168 #elif defined (__AVR_ATmega168A__) # define _EEPROM_SUFFIX _m168a #elif defined (__AVR_ATmega168P__) # define _EEPROM_SUFFIX _m168p #elif defined (__AVR_ATmega169__) # define _EEPROM_SUFFIX _m169 #elif defined (__AVR_ATmega169A__) # define _EEPROM_SUFFIX _m169a #elif defined (__AVR_ATmega169P__) # define _EEPROM_SUFFIX _m169p #elif defined (__AVR_ATmega169PA__) # define _EEPROM_SUFFIX _m169pa #elif defined (__AVR_ATmega8HVA__) # define _EEPROM_SUFFIX _m8hva #elif defined (__AVR_ATmega16HVA__) # define _EEPROM_SUFFIX _m16hva #elif defined (__AVR_ATmega16HVA2__) # define _EEPROM_SUFFIX _m16hva2 #elif defined (__AVR_ATmega16HVB__) # define _EEPROM_SUFFIX _m16hvb #elif defined (__AVR_ATmega16HVBREVB__) # define _EEPROM_SUFFIX _m16hvbrevb #elif defined (__AVR_ATmega8__) # define _EEPROM_SUFFIX _m8 #elif defined (__AVR_ATmega48__) # define _EEPROM_SUFFIX _m48 #elif defined (__AVR_ATmega48A__) # define _EEPROM_SUFFIX _m48a #elif defined (__AVR_ATmega48P__) # define _EEPROM_SUFFIX _m48p #elif defined (__AVR_ATmega88__) # define _EEPROM_SUFFIX _m88 #elif defined (__AVR_ATmega88A__) # define _EEPROM_SUFFIX _m88a #elif defined (__AVR_ATmega88P__) # define _EEPROM_SUFFIX _m88p #elif defined (__AVR_ATmega88PA__) # define _EEPROM_SUFFIX _m88pa #elif defined (__AVR_ATmega8515__) # define _EEPROM_SUFFIX _m8515 #elif defined (__AVR_ATmega8535__) # define _EEPROM_SUFFIX _m8535 #elif defined (__AVR_AT90S8535__) # define _EEPROM_SUFFIX _8535 #elif defined (__AVR_AT90C8534__) # define _EEPROM_SUFFIX _8534 #elif defined (__AVR_AT90S8515__) # define _EEPROM_SUFFIX _8515 #elif defined (__AVR_AT90S4434__) # define _EEPROM_SUFFIX _4434 #elif defined (__AVR_AT90S4433__) # define _EEPROM_SUFFIX _4433 #elif defined (__AVR_AT90S4414__) # define _EEPROM_SUFFIX _4414 #elif defined (__AVR_ATtiny22__) # define _EEPROM_SUFFIX _tn22 #elif defined (__AVR_ATtiny26__) # define _EEPROM_SUFFIX _tn26 #elif defined (__AVR_AT90S2343__) # define _EEPROM_SUFFIX _2343 #elif defined (__AVR_AT90S2333__) # define _EEPROM_SUFFIX _2333 #elif defined (__AVR_AT90S2323__) # define _EEPROM_SUFFIX _2323 #elif defined (__AVR_AT90S2313__) # define _EEPROM_SUFFIX _2313 #elif defined (__AVR_ATtiny2313__) # define _EEPROM_SUFFIX _tn2313 #elif defined (__AVR_ATtiny2313A__) # define _EEPROM_SUFFIX _tn2313a #elif defined (__AVR_ATtiny4313__) # define _EEPROM_SUFFIX _tn4313 #elif defined (__AVR_ATtiny13__) # define _EEPROM_SUFFIX _tn13 #elif defined (__AVR_ATtiny13A__) # define _EEPROM_SUFFIX _tn13a #elif defined (__AVR_ATtiny25__) # define _EEPROM_SUFFIX _tn25 #elif defined (__AVR_ATtiny45__) # define _EEPROM_SUFFIX _tn45 #elif defined (__AVR_ATtiny85__) # define _EEPROM_SUFFIX _tn85 #elif defined (__AVR_ATtiny24__) # define _EEPROM_SUFFIX _tn24 #elif defined (__AVR_ATtiny24A__) # define _EEPROM_SUFFIX _tn24a #elif defined (__AVR_ATtiny44__) # define _EEPROM_SUFFIX _tn44 #elif defined (__AVR_ATtiny44A__) # define _EEPROM_SUFFIX _tn44a #elif defined (__AVR_ATtiny84__) # define _EEPROM_SUFFIX _tn84 #elif defined (__AVR_ATtiny84A__) # define _EEPROM_SUFFIX _tn84a #elif defined (__AVR_ATtiny261__) # define _EEPROM_SUFFIX _tn261 #elif defined (__AVR_ATtiny261A__) # define _EEPROM_SUFFIX _tn261a #elif defined (__AVR_ATtiny461__) # define _EEPROM_SUFFIX _tn461 #elif defined (__AVR_ATtiny461A__) # define _EEPROM_SUFFIX _tn461a #elif defined (__AVR_ATtiny861__) # define _EEPROM_SUFFIX _tn861 #elif defined (__AVR_ATtiny861A__) # define _EEPROM_SUFFIX _tn861a #elif defined (__AVR_ATtiny43U__) # define _EEPROM_SUFFIX _tn43u #elif defined (__AVR_ATtiny48__) # define _EEPROM_SUFFIX _tn48 #elif defined (__AVR_ATtiny88__) # define _EEPROM_SUFFIX _tn88 #elif defined (__AVR_ATtiny87__) # define _EEPROM_SUFFIX _tn87 #elif defined (__AVR_ATtiny167__) # define _EEPROM_SUFFIX _tn167 #elif defined (__AVR_AT90SCR100__) # define _EEPROM_SUFFIX _90scr100 #elif defined (__AVR_ATxmega16A4__) # define _EEPROM_SUFFIX _x16a4 #elif defined (__AVR_ATxmega16D4__) # define _EEPROM_SUFFIX _x16d4 #elif defined (__AVR_ATxmega32A4__) # define _EEPROM_SUFFIX _x32a4 #elif defined (__AVR_ATxmega32D4__) # define _EEPROM_SUFFIX _x32d4 #elif defined (__AVR_ATxmega64A1__) # define _EEPROM_SUFFIX _x64a1 #elif defined (__AVR_ATxmega64A1U__) # define _EEPROM_SUFFIX _x64a1u #elif defined (__AVR_ATxmega64A3__) # define _EEPROM_SUFFIX _x64a3 #elif defined (__AVR_ATxmega64D3__) # define _EEPROM_SUFFIX _x64d3 #elif defined (__AVR_ATxmega128A1__) # define _EEPROM_SUFFIX _x128a1 #elif defined (__AVR_ATxmega128A1U__) # define _EEPROM_SUFFIX _x128a1u #elif defined (__AVR_ATxmega128A3__) # define _EEPROM_SUFFIX _x128a3 #elif defined (__AVR_ATxmega128D3__) # define _EEPROM_SUFFIX _x128d3 #elif defined (__AVR_ATxmega192A3__) # define _EEPROM_SUFFIX _x192a3 #elif defined (__AVR_ATxmega192D3__) # define _EEPROM_SUFFIX _x192d3 #elif defined (__AVR_ATxmega256A3__) # define _EEPROM_SUFFIX _x256a3 #elif defined (__AVR_ATxmega256A3B__) # define _EEPROM_SUFFIX _x256a3b #elif defined (__AVR_ATxmega256D3__) # define _EEPROM_SUFFIX _x256d3 #elif defined (__AVR_ATA6289__) # define _EEPROM_SUFFIX _a6289 /* avr1: the following only supported for assembler programs */ #elif defined (__AVR_ATtiny28__) # define _EEPROM_SUFFIX _tn28 #elif defined (__AVR_AT90S1200__) # define _EEPROM_SUFFIX _1200 #elif defined (__AVR_ATtiny15__) # define _EEPROM_SUFFIX _tn15 #elif defined (__AVR_ATtiny12__) # define _EEPROM_SUFFIX _tn12 #elif defined (__AVR_ATtiny11__) # define _EEPROM_SUFFIX _tn11 #else # define _EEPROM_SUFFIX _UNKNOWN #endif #define _EEPROM_CONCAT1(s1, s2) s1 ## s2 #define _EEPROM_CONCAT2(s1, s2) _EEPROM_CONCAT1 (s1, s2) #define eeprom_read_byte _EEPROM_CONCAT2 (__eerd_byte, _EEPROM_SUFFIX) #define eeprom_read_word _EEPROM_CONCAT2 (__eerd_word, _EEPROM_SUFFIX) #define eeprom_read_dword _EEPROM_CONCAT2 (__eerd_dword, _EEPROM_SUFFIX) #define eeprom_read_float _EEPROM_CONCAT2 (__eerd_float, _EEPROM_SUFFIX) #define eeprom_read_block _EEPROM_CONCAT2 (__eerd_block, _EEPROM_SUFFIX) #define eeprom_write_byte _EEPROM_CONCAT2 (__eewr_byte, _EEPROM_SUFFIX) #define eeprom_write_word _EEPROM_CONCAT2 (__eewr_word, _EEPROM_SUFFIX) #define eeprom_write_dword _EEPROM_CONCAT2 (__eewr_dword, _EEPROM_SUFFIX) #define eeprom_write_float _EEPROM_CONCAT2 (__eewr_float, _EEPROM_SUFFIX) #define eeprom_write_block _EEPROM_CONCAT2 (__eewr_block, _EEPROM_SUFFIX) #define eeprom_update_byte _EEPROM_CONCAT2 (__eeupd_byte, _EEPROM_SUFFIX) #define eeprom_update_word _EEPROM_CONCAT2 (__eeupd_word, _EEPROM_SUFFIX) #define eeprom_update_dword _EEPROM_CONCAT2 (__eeupd_dword, _EEPROM_SUFFIX) #define eeprom_update_float _EEPROM_CONCAT2 (__eeupd_float, _EEPROM_SUFFIX) #define eeprom_update_block _EEPROM_CONCAT2 (__eeupd_block, _EEPROM_SUFFIX) #endif /* !__DOXYGEN__ */ #ifndef __ASSEMBLER__ #include /* size_t */ #include /** \defgroup avr_eeprom : EEPROM handling \code #include \endcode This header file declares the interface to some simple library routines suitable for handling the data EEPROM contained in the AVR microcontrollers. The implementation uses a simple polled mode interface. Applications that require interrupt-controlled EEPROM access to ensure that no time will be wasted in spinloops will have to deploy their own implementation. \par Notes: - In addition to the write functions there is a set of update ones. This functions read each byte first and skip the burning if the old value is the same with new. The scaning direction is from high address to low, to obtain quick return in common cases. - All of the read/write functions first make sure the EEPROM is ready to be accessed. Since this may cause long delays if a write operation is still pending, time-critical applications should first poll the EEPROM e. g. using eeprom_is_ready() before attempting any actual I/O. But this functions are not wait until SELFPRGEN in SPMCSR becomes zero. Do this manually, if your softwate contains the Flash burning. - As these functions modify IO registers, they are known to be non-reentrant. If any of these functions are used from both, standard and interrupt context, the applications must ensure proper protection (e.g. by disabling interrupts before accessing them). - All write functions force erase_and_write programming mode. - For Xmega the EEPROM start address is 0, like other architectures. The reading functions add the 0x2000 value to use EEPROM mapping into data space. */ #ifdef __cplusplus extern "C" { #endif #ifndef __ATTR_PURE__ # ifdef __DOXYGEN__ # define __ATTR_PURE__ # else # define __ATTR_PURE__ __attribute__((__pure__)) # endif #endif /** \def EEMEM \ingroup avr_eeprom Attribute expression causing a variable to be allocated within the .eeprom section. */ #define EEMEM __attribute__((section(".eeprom"))) /** \def eeprom_is_ready \ingroup avr_eeprom \returns 1 if EEPROM is ready for a new read/write operation, 0 if not. */ #if defined (__DOXYGEN__) # define eeprom_is_ready() #elif defined (__AVR_XMEGA__) && __AVR_XMEGA__ # define eeprom_is_ready() bit_is_clear (NVM_STATUS, NVM_NVMBUSY_bp) #elif defined (DEECR) # define eeprom_is_ready() bit_is_clear (DEECR, BSY) #elif defined (EEPE) # define eeprom_is_ready() bit_is_clear (EECR, EEPE) #else # define eeprom_is_ready() bit_is_clear (EECR, EEWE) #endif /** \def eeprom_busy_wait \ingroup avr_eeprom Loops until the eeprom is no longer busy. \returns Nothing. */ #define eeprom_busy_wait() do {} while (!eeprom_is_ready()) /** \ingroup avr_eeprom Read one byte from EEPROM address \a __p. */ uint8_t eeprom_read_byte (const uint8_t *__p) __ATTR_PURE__; /** \ingroup avr_eeprom Read one 16-bit word (little endian) from EEPROM address \a __p. */ uint16_t eeprom_read_word (const uint16_t *__p) __ATTR_PURE__; /** \ingroup avr_eeprom Read one 32-bit double word (little endian) from EEPROM address \a __p. */ uint32_t eeprom_read_dword (const uint32_t *__p) __ATTR_PURE__; /** \ingroup avr_eeprom Read one float value (little endian) from EEPROM address \a __p. */ float eeprom_read_float (const float *__p) __ATTR_PURE__; /** \ingroup avr_eeprom Read a block of \a __n bytes from EEPROM address \a __src to SRAM \a __dst. */ void eeprom_read_block (void *__dst, const void *__src, size_t __n); /** \ingroup avr_eeprom Write a byte \a __value to EEPROM address \a __p. */ void eeprom_write_byte (uint8_t *__p, uint8_t __value); /** \ingroup avr_eeprom Write a word \a __value to EEPROM address \a __p. */ void eeprom_write_word (uint16_t *__p, uint16_t __value); /** \ingroup avr_eeprom Write a 32-bit double word \a __value to EEPROM address \a __p. */ void eeprom_write_dword (uint32_t *__p, uint32_t __value); /** \ingroup avr_eeprom Write a float \a __value to EEPROM address \a __p. */ void eeprom_write_float (float *__p, float __value); /** \ingroup avr_eeprom Write a block of \a __n bytes to EEPROM address \a __dst from \a __src. \note The argument order is mismatch with common functions like strcpy(). */ void eeprom_write_block (const void *__src, void *__dst, size_t __n); /** \ingroup avr_eeprom Update a byte \a __value to EEPROM address \a __p. */ void eeprom_update_byte (uint8_t *__p, uint8_t __value); /** \ingroup avr_eeprom Update a word \a __value to EEPROM address \a __p. */ void eeprom_update_word (uint16_t *__p, uint16_t __value); /** \ingroup avr_eeprom Update a 32-bit double word \a __value to EEPROM address \a __p. */ void eeprom_update_dword (uint32_t *__p, uint32_t __value); /** \ingroup avr_eeprom Update a float \a __value to EEPROM address \a __p. */ void eeprom_update_float (float *__p, float __value); /** \ingroup avr_eeprom Update a block of \a __n bytes to EEPROM address \a __dst from \a __src. \note The argument order is mismatch with common functions like strcpy(). */ void eeprom_update_block (const void *__src, void *__dst, size_t __n); /** \name IAR C compatibility defines */ /*@{*/ /** \def _EEPUT \ingroup avr_eeprom Write a byte to EEPROM. Compatibility define for IAR C. */ #define _EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val)) /** \def __EEPUT \ingroup avr_eeprom Write a byte to EEPROM. Compatibility define for IAR C. */ #define __EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val)) /** \def _EEGET \ingroup avr_eeprom Read a byte from EEPROM. Compatibility define for IAR C. */ #define _EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr)) /** \def __EEGET \ingroup avr_eeprom Read a byte from EEPROM. Compatibility define for IAR C. */ #define __EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr)) /*@}*/ #ifdef __cplusplus } #endif #endif /* !__ASSEMBLER__ */ #endif /* E2END || defined(__DOXYGEN__) || defined(__COMPILING_AVR_LIBC__) */ #endif /* !_AVR_EEPROM_H_ */ avr-libc-1.8.0.orig/include/avr/iom6490.h0000644000000000000000000005612311732702554014554 0ustar /* Copyright (c) 2004 Eric B. Weddington Copyright (c) 2005,2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/iom6490.h - definitions for ATmega6490 */ #ifndef _AVR_IOM6490_H_ #define _AVR_IOM6490_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom6490.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define PCIF2 6 #define PCIF3 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define PCIE2 6 #define PCIE3 7 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRLCD 4 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x72] */ #define PCMSK3 _SFR_MEM8(0x73) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define PCINT27 3 #define PCINT28 4 #define PCINT29 5 #define PCINT30 6 /* Reserved [0x74..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0XC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7..0xD7] */ #define PINH _SFR_MEM8(0xD8) #define PINH7 7 #define PINH6 6 #define PINH5 5 #define PINH4 4 #define PINH3 3 #define PINH2 2 #define PINH1 1 #define PINH0 0 #define DDRH _SFR_MEM8(0xD9) #define DDH7 7 #define DDH6 6 #define DDH5 5 #define DDH4 4 #define DDH3 3 #define DDH2 2 #define DDH1 1 #define DDH0 0 #define PORTH _SFR_MEM8(0xDA) #define PH7 7 #define PH6 6 #define PH5 5 #define PH4 4 #define PH3 3 #define PH2 2 #define PH1 1 #define PH0 0 #define PINJ _SFR_MEM8(0xDB) #define PINJ6 6 #define PINJ5 5 #define PINJ4 4 #define PINJ3 3 #define PINJ2 2 #define PINJ1 1 #define PINJ0 0 #define DDRJ _SFR_MEM8(0xDC) #define DDJ6 6 #define DDJ5 5 #define DDJ4 4 #define DDJ3 3 #define DDJ2 2 #define DDJ1 1 #define DDJ0 0 #define PORTJ _SFR_MEM8(0xDD) #define PJ6 6 #define PJ5 5 #define PJ4 4 #define PJ3 3 #define PJ2 2 #define PJ1 1 #define PJ0 0 /* Reserved [0xDE..0xE3] */ #define LCDCRA _SFR_MEM8(0XE4) #define LCDBL 0 #define LCDIE 3 #define LCDIF 4 #define LCDAB 6 #define LCDEN 7 #define LCDCRB _SFR_MEM8(0XE5) #define LCDPM0 0 #define LCDPM1 1 #define LCDPM2 2 #define LCDPM3 3 #define LCDMUX0 4 #define LCDMUX1 5 #define LCD2B 6 #define LCDCS 7 #define LCDFRR _SFR_MEM8(0XE6) #define LCDCD0 0 #define LCDCD1 1 #define LCDCD2 2 #define LCDPS0 4 #define LCDPS1 5 #define LCDPS2 6 #define LCDCCR _SFR_MEM8(0XE7) #define LCDCC0 0 #define LCDCC1 1 #define LCDCC2 2 #define LCDCC3 3 #define LCDDC0 5 #define LCDDC1 6 #define LCDDC2 7 /* Reserved [0xE8..0xEB] */ #define LCDDR00 _SFR_MEM8(0XEC) #define SEG000 0 #define SEG001 1 #define SEG002 2 #define SEG003 3 #define SEG004 4 #define SEG005 5 #define SEG006 6 #define SEG007 7 #define LCDDR01 _SFR_MEM8(0XED) #define SEG008 0 #define SEG009 1 #define SEG010 2 #define SEG011 3 #define SEG012 4 #define SEG013 5 #define SEG014 6 #define SEG015 7 #define LCDDR02 _SFR_MEM8(0XEE) #define SEG016 0 #define SEG017 1 #define SEG018 2 #define SEG019 3 #define SEG020 4 #define SEG021 5 #define SEG022 6 #define SEG023 7 #define LCDDR03 _SFR_MEM8(0XEF) #define SEG024 0 #define SEG025 1 #define SEG026 2 #define SEG027 3 #define SEG028 4 #define SEG029 5 #define SEG030 6 #define SEG031 7 #define LCDDR04 _SFR_MEM8(0XF0) #define SEG032 0 #define SEG033 1 #define SEG034 2 #define SEG035 3 #define SEG036 4 #define SEG037 5 #define SEG038 6 #define SEG039 7 #define LCDDR05 _SFR_MEM8(0XF1) #define SEG100 0 #define SEG101 1 #define SEG102 2 #define SEG103 3 #define SEG104 4 #define SEG105 5 #define SEG106 6 #define SEG107 7 #define LCDDR06 _SFR_MEM8(0XF2) #define SEG108 0 #define SEG109 1 #define SEG110 2 #define SEG111 3 #define SEG112 4 #define SEG113 5 #define SEG114 6 #define SEG115 7 #define LCDDR07 _SFR_MEM8(0XF3) #define SEG116 0 #define SEG117 1 #define SEG118 2 #define SEG119 3 #define SEG120 4 #define SEG121 5 #define SEG122 6 #define SEG123 7 #define LCDDR08 _SFR_MEM8(0XF4) #define SEG124 0 #define SEG125 1 #define SEG126 2 #define SEG127 3 #define SEG128 4 #define SEG129 5 #define SEG130 6 #define SEG131 7 #define LCDDR09 _SFR_MEM8(0XF5) #define SEG132 0 #define SEG133 1 #define SEG134 2 #define SEG135 3 #define SEG136 4 #define SEG137 5 #define SEG138 6 #define SEG139 7 #define LCDDR10 _SFR_MEM8(0XF6) #define SEG200 0 #define SEG201 1 #define SEG202 2 #define SEG203 3 #define SEG204 4 #define SEG205 5 #define SEG206 6 #define SEG207 7 #define LCDDR11 _SFR_MEM8(0XF7) #define SEG208 0 #define SEG209 1 #define SEG210 2 #define SEG211 3 #define SEG212 4 #define SEG213 5 #define SEG214 6 #define SEG215 7 #define LCDDR12 _SFR_MEM8(0XF8) #define SEG216 0 #define SEG217 1 #define SEG218 2 #define SEG219 3 #define SEG220 4 #define SEG221 5 #define SEG222 6 #define SEG223 7 #define LCDDR13 _SFR_MEM8(0XF9) #define SEG224 0 #define SEG225 1 #define SEG226 2 #define SEG227 3 #define SEG228 4 #define SEG229 5 #define SEG230 6 #define SEG231 7 #define LCDDR14 _SFR_MEM8(0XFA) #define SEG232 0 #define SEG233 1 #define SEG234 2 #define SEG235 3 #define SEG236 4 #define SEG237 5 #define SEG238 6 #define SEG239 7 #define LCDDR15 _SFR_MEM8(0XFB) #define SEG300 0 #define SEG301 1 #define SEG302 2 #define SEG303 3 #define SEG304 4 #define SEG305 5 #define SEG306 6 #define SEG307 7 #define LCDDR16 _SFR_MEM8(0XFC) #define SEG308 0 #define SEG309 1 #define SEG310 2 #define SEG311 3 #define SEG312 4 #define SEG313 5 #define SEG314 6 #define SEG315 7 #define LCDDR17 _SFR_MEM8(0XFD) #define SEG316 0 #define SEG217 1 #define SEG318 2 #define SEG319 3 #define SEG320 4 #define SEG321 5 #define SEG322 6 #define SEG323 7 #define LCDDR18 _SFR_MEM8(0XFE) #define SEG324 0 #define SEG325 1 #define SEG326 2 #define SEG327 3 #define SEG328 4 #define SEG329 5 #define SEG330 6 #define SEG331 7 #define LCDDR19 _SFR_MEM8(0XFF) #define SEG332 0 #define SEG333 1 #define SEG334 2 #define SEG335 3 #define SEG336 4 #define SEG337 5 #define SEG338 6 #define SEG339 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART, Rx Complete */ #define USART_RX_vect_num 13 #define USART_RX_vect _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) /* USART Data register Empty */ #define USART_UDRE_vect_num 14 #define USART_UDRE_vect _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* LCD Start of Frame */ #define LCD_vect_num 22 #define LCD_vect _VECTOR(22) #define SIG_LCD _VECTOR(22) /* Pin Change Interrupt Request 2 */ #define PCINT2_vect_num 23 #define PCINT2_vect _VECTOR(23) #define SIG_PIN_CHANGE2 _VECTOR(23) /* Pin Change Interrupt Request 3 */ #define PCINT3_vect_num 24 #define PCINT3_vect _VECTOR(24) #define SIG_PIN_CHANGE3 _VECTOR(24) #define _VECTORS_SIZE 100 /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x10FF #define XRAMEND RAMEND #define E2END 0x7FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x04 #endif /* _AVR_IOM6490_H_ */ avr-libc-1.8.0.orig/include/avr/iom406.h0000644000000000000000000004125511732702554014463 0ustar /* Copyright (c) 2006, Pieter Conradie All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom406.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iom406.h - definitions for ATmega406 */ #ifndef _AVR_IOM406_H_ #define _AVR_IOM406_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom406.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Reserved [0x06..0x07] */ #define PORTC _SFR_IO8(0x08) #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD1 1 #define PD0 0 /* Reserved [0x0C..0x14] */ /* Timer/Counter0 Interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) #define OCF0B 2 #define OCF0A 1 #define TOV0 0 /* Timer/Counter1 Interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) #define OCF1A 1 #define TOV1 0 /* Reserved [0x17..0x1A] */ /* Pin Change Interrupt Control Register */ #define PCIFR _SFR_IO8(0x1B) #define PCIF1 1 #define PCIF0 0 /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 /* External Interrupt MaSK register */ #define EIMSK _SFR_IO8(0x1D) #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 /* General Purpose I/O Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1F) #define EEPM1 5 #define EEPM0 4 #define EERIE 3 #define EEMPE 2 #define EEPE 1 #define EERE 0 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x20) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0x22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) #define TSM 7 #define PSRSYNC 0 /* Timer/Counter Control Register A */ #define TCCR0A _SFR_IO8(0x24) #define COM0A1 7 #define COM0A0 6 #define COM0B1 5 #define COM0B0 4 #define WGM01 1 #define WGM00 0 /* Timer/Counter Control Register B */ #define TCCR0B _SFR_IO8(0x25) #define FOC0A 7 #define FOC0B 6 #define WGM02 3 #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x26) /* Output Compare Register A */ #define OCR0A _SFR_IO8(0x27) /* Output Compare Register B */ #define OCR0B _SFR_IO8(0x28) /* Reserved [0x29] */ /* General Purpose I/O Register 1 */ #define GPIOR1 _SFR_IO8(0x2A) /* General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x2B) /* Reserved [0x2C..0x30] */ /* On-chip Debug Register */ #define OCDR _SFR_IO8(0x31) /* Reserved [0x32] */ /* Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) #define SM2 3 #define SM1 2 #define SM0 1 #define SE 0 /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) #define JTRF 4 #define WDRF 3 #define BODRF 2 #define EXTRF 1 #define PORF 0 /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) #define JTD 7 #define PUD 4 #define IVSEL 1 #define IVCE 0 /* Reserved [0x36] */ /* Store Program Memory Control and Status Register */ #define SPMCSR _SFR_IO8(0x37) #define SPMIE 7 #define RWWSB 6 #define SIGRD 5 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* Reserved [0x36..0x3C] */ /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Extended I/O registers */ /* Watchdog Timer Control Register */ #define WDTCSR _SFR_MEM8(0x60) #define WDIF 7 #define WDIE 6 #define WDP3 5 #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Reserved [0x61] */ /* Wake-up Timer Control and Status Register */ #define WUTCSR _SFR_MEM8(0x62) #define WUTIF 7 #define WUTIE 6 #define WUTCF 5 #define WUTR 4 #define WUTE 3 #define WUTP2 2 #define WUTP1 1 #define WUTP0 0 /* Reserved [0x63] */ /* Power Reduction Register 0 */ #define PRR0 _SFR_MEM8(0x64) #define PRTWI 3 #define PRTIM1 2 #define PRTIM0 1 #define PRVADC 0 /* Reserved [0x65] */ /* Fast Oscillator Calibration Register */ #define FOSCCAL _SFR_MEM8(0x66) /* Reserved [0x67] */ /* Pin Change Interrupt Control Register */ #define PCICR _SFR_MEM8(0x68) #define PCIE1 1 #define PCIE0 0 /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x69) #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Reserved [0x6A] */ /* Pin Change Mask Register 0 */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT7 7 #define PCINT6 6 #define PCINT5 5 #define PCINT4 4 #define PCINT3 3 #define PCINT2 2 #define PCINT1 1 #define PCINT0 0 /* Pin Change Mask Register 1 */ #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT15 7 #define PCINT14 6 #define PCINT13 5 #define PCINT12 4 #define PCINT11 3 #define PCINT10 2 #define PCINT9 1 #define PCINT8 0 /* Reserved [0x6D] */ /* Timer/Counter Interrupt MaSK register 0 */ #define TIMSK0 _SFR_MEM8(0x6E) #define OCIE0B 2 #define OCIE0A 1 #define TOIE0 0 /* Timer/Counter Interrupt MaSK register 1 */ #define TIMSK1 _SFR_MEM8(0x6F) #define OCIE1A 1 #define TOIE1 0 /* Reserved [0x70..0x77] */ /* V-ADC Data Register */ #define VADC _SFR_MEM16(0x78) #define VADCL _SFR_MEM8(0x78) #define VADCH _SFR_MEM8(0x79) /* V-ADC Control and Status Register */ #define VADCSR _SFR_MEM8(0x7A) #define VADEN 3 #define VADSC 2 #define VADCCIF 1 #define VADCCIE 0 /* Reserved [0x7B] */ /* V-ADC Multiplexer Selection Register */ #define VADMUX _SFR_MEM8(0x7C) #define VADMUX3 3 #define VADMUX2 2 #define VADMUX1 1 #define VADMUX0 0 /* Reserved [0x7D] */ /* Digital Input Disable Register 0 */ #define DIDR0 _SFR_MEM8(0x7E) #define VADC3D 3 #define VADC2D 2 #define VADC1D 1 #define VADC0D 0 /* Reserved [0x82..0x83] */ /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_MEM8(0x81) #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Reserved [0x82..0x83] */ /* Timer/Counter 1 */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Reserved [0x86..0x87] */ /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Reserved [0x8A..0xB7] */ /* 2-wire Serial Interface Bit Rate Register */ #define TWBR _SFR_MEM8(0xB8) /* 2-wire Serial Interface Status Register */ #define TWSR _SFR_MEM8(0xB9) #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 /* 2-wire Serial Interface Address Register */ #define TWAR _SFR_MEM8(0xBA) #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 /* 2-wire Serial Interface Data Register */ #define TWDR _SFR_MEM8(0xBB) /* 2-wire Serial Interface Control Register */ #define TWCR _SFR_MEM8(0xBC) #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 /* 2-wire Serial (Slave) Address Mask Register */ #define TWAMR _SFR_MEM8(0xBD) #define TWAM6 7 #define TWAM5 6 #define TWAM4 5 #define TWAM3 4 #define TWAM2 3 #define TWAM1 2 #define TWAM0 1 /* 2-wire Serial Bus Control and Status Register */ #define TWBCSR _SFR_MEM8(0xBE) #define TWBCIF 7 #define TWBCIE 6 #define TWBDT1 2 #define TWBDT0 1 #define TWBCIP 0 /* Reserved [0xBF] */ /* Clock Control Status Register */ #define CCSR _SFR_MEM8(0xC0) #define XOE 1 #define ACS 0 /* Reserved [0xC1..0xCF] */ /* Bandgap Calibration C Register */ #define BGCCR _SFR_MEM8(0xD0) #define BGEN 7 #define BGCC5 5 #define BGCC4 4 #define BGCC3 3 #define BGCC2 2 #define BGCC1 1 #define BGCC0 0 /* Bandgap Calibration R Register */ #define BGCRR _SFR_MEM8(0xD1) #define BGCR7 7 #define BGCR6 6 #define BGCR5 5 #define BGCR4 4 #define BGCR3 3 #define BGCR2 2 #define BGCR1 1 #define BGCR0 0 /* Reserved [0xD2..0xDF] */ /* CC-ADC Accumulate Current */ /* TODO: Add _SFR_MEM32 */ /* #define CADAC _SFR_MEM32(0xE0) */ #define CADAC0 _SFR_MEM8(0xE0) #define CADAC1 _SFR_MEM8(0xE1) #define CADAC2 _SFR_MEM8(0xE2) #define CADAC3 _SFR_MEM8(0xE3) /* CC-ADC Control and Status Register A */ #define CADCSRA _SFR_MEM8(0xE4) #define CADEN 7 #define CADUB 5 #define CADAS1 4 #define CADAS0 3 #define CADSI1 2 #define CADSI0 1 #define CADSE 0 /* CC-ADC Control and Status Register B */ #define CADCSRB _SFR_MEM8(0xE5) #define CADACIE 6 #define CADRCIE 5 #define CADICIE 4 #define CADACIF 2 #define CADRCIF 1 #define CADICIF 0 /* CC-ADC Regular Charge Current */ #define CADRCC _SFR_MEM8(0xE6) /* CC-ADC Regular Discharge Current */ #define CADRDC _SFR_MEM8(0xE7) /* CC-ADC Instantaneous Current */ #define CADIC _SFR_MEM16(0xE8) #define CADICL _SFR_MEM8(0xE8) #define CADICH _SFR_MEM8(0xE9) /* Reserved [0xEA..0xEF] */ /* FET Control and Status Register */ #define FCSR _SFR_MEM8(0xF0) #define PWMOC 5 #define PWMOPC 4 #define CPS 3 #define DFE 2 #define CFE 1 #define PFD 0 /* Cell Balancing Control Register */ #define CBCR _SFR_MEM8(0xF1) #define CBE4 3 #define CBE3 2 #define CBE2 1 #define CBE1 0 /* Battery Protection Interrupt Register */ #define BPIR _SFR_MEM8(0xF2) #define DUVIF 7 #define COCIF 6 #define DOCIF 5 #define SCIF 4 #define DUVIE 3 #define COCIE 2 #define DOCIE 1 #define SCIE 0 /* Battery Protection Deep Under Voltage Register */ #define BPDUV _SFR_MEM8(0xF3) #define DUVT1 5 #define DUVT0 4 #define DUDL3 3 #define DUDL2 2 #define DUDL1 1 #define DUDL0 0 /* Battery Protection Short-circuit Detection Level Register */ #define BPSCD _SFR_MEM8(0xF4) #define SCDL3 3 #define SCDL2 2 #define SCDL1 1 #define SCDL0 0 /* Battery Protection Over-current Detection Level Register */ #define BPOCD _SFR_MEM8(0xF5) #define DCDL3 7 #define DCDL2 6 #define DCDL1 5 #define DCDL0 4 #define CCDL3 3 #define CCDL2 2 #define CCDL1 1 #define CCDL0 0 /* Current Battery Protection Timing Register */ #define CBPTR _SFR_MEM8(0xF6) #define SCPT3 7 #define SCPT2 6 #define SCPT1 5 #define SCPT0 4 #define OCPT3 3 #define OCPT2 2 #define OCPT1 1 #define OCPT0 0 /* Battery Protection Control Register */ #define BPCR _SFR_MEM8(0xF7) #define DUVD 3 #define SCD 2 #define DCD 1 #define CCD 0 /* Battery Protection Parameter Lock Register */ #define BPPLR _SFR_MEM8(0xF8) #define BPPLE 1 #define BPPL 0 /* Reserved [0xF9..0xFF] */ /* Interrupt vectors */ /* Battery Protection Interrupt */ #define BPINT_vect_num 1 #define BPINT_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT0_vect_num 2 #define INT0_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT1_vect_num 3 #define INT1_vect _VECTOR(3) /* External Interrupt Request 2 */ #define INT2_vect_num 4 #define INT2_vect _VECTOR(4) /* External Interrupt Request 3 */ #define INT3_vect_num 5 #define INT3_vect _VECTOR(5) /* Pin Change Interrupt 0 */ #define PCINT0_vect_num 6 #define PCINT0_vect _VECTOR(6) /* Pin Change Interrupt 1 */ #define PCINT1_vect_num 7 #define PCINT1_vect _VECTOR(7) /* Watchdog Timeout Interrupt */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Wakeup timer overflow */ #define WAKE_UP_vect_num 9 #define WAKE_UP_vect _VECTOR(9) /* Timer/Counter 1 Compare Match */ #define TIM1_COMP_vect_num 10 #define TIM1_COMP_vect _VECTOR(10) /* Timer/Counter 1 Overflow */ #define TIM1_OVF_vect_num 11 #define TIM1_OVF_vect _VECTOR(11) /* Timer/Counter0 Compare A Match */ #define TIM0_COMPA_vect_num 12 #define TIM0_COMPA_vect _VECTOR(12) /* Timer/Counter0 Compare B Match */ #define TIM0_COMPB_vect_num 13 #define TIM0_COMPB_vect _VECTOR(13) /* Timer/Counter0 Overflow */ #define TIM0_OVF_vect_num 14 #define TIM0_OVF_vect _VECTOR(14) /* Two-Wire Bus Connect/Disconnect */ #define TWI_BUS_CD_vect_num 15 #define TWI_BUS_CD_vect _VECTOR(15) /* Two-Wire Serial Interface */ #define TWI_vect_num 16 #define TWI_vect _VECTOR(16) /* Voltage ADC Conversion Complete */ #define VADC_vect_num 17 #define VADC_vect _VECTOR(17) /* Coulomb Counter ADC Conversion Complete */ #define CCADC_CONV_vect_num 18 #define CCADC_CONV_vect _VECTOR(18) /* Coloumb Counter ADC Regular Current */ #define CCADC_REG_CUR_vect_num 19 #define CCADC_REG_CUR_vect _VECTOR(19) /* Coloumb Counter ADC Accumulator */ #define CCADC_ACC_vect_num 20 #define CCADC_ACC_vect _VECTOR(20) /* EEPROM Ready */ #define EE_READY_vect_num 21 #define EE_READY_vect _VECTOR(21) /* Store Program Memory Ready */ #define SPM_READY_vect_num 22 #define SPM_READY_vect _VECTOR(22) #define _VECTORS_SIZE 92 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x8FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x9FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL (unsigned char)~_BV(0) #define FUSE_SUT0 (unsigned char)~_BV(1) #define FUSE_SUT1 (unsigned char)~_BV(2) #define FUSE_BOOTRST (unsigned char)~_BV(3) #define FUSE_BOOTSZ0 (unsigned char)~_BV(4) #define FUSE_BOOTSZ1 (unsigned char)~_BV(5) #define FUSE_EESAVE (unsigned char)~_BV(6) #define FUSE_WDTON (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* High Fuse Byte */ #define FUSE_JTAGEN (unsigned char)~_BV(0) #define FUSE_OCDEN (unsigned char)~_BV(1) #define HFUSE_DEFAULT (FUSE_JTAGEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x07 #endif /* _AVR_IOM406_H_ */ avr-libc-1.8.0.orig/include/avr/iotn26.h0000644000000000000000000002232211732702554014560 0ustar /* Copyright (c) 2004,2005 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn26.h 2236 2011-03-17 21:53:39Z arcanum $ */ /* avr/iotn26.h - definitions for ATtiny26 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn26.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOTN26_H_ #define _AVR_IOTN26_H_ 1 /* Registers and associated bit numbers */ /* Reserved [0x00..0x03] */ #define ADCW _SFR_IO16(0x04) #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSR _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADFR 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACME 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 /* Reserved [0x09..0x0C] */ #define USICR _SFR_IO8(0x0D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x0E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x0F) /* Reserved [0x10..0x15] */ #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PB0 0 #define PB1 1 #define PB2 2 #define PB3 3 #define PB4 4 #define PB5 5 #define PB6 6 #define PB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PA0 0 #define PA1 1 #define PA2 2 #define PA3 3 #define PA4 4 #define PA5 5 #define PA6 6 #define PA7 7 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Reserved [0x1F..0x20] */ #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 /* Reserved [0x22..0x28] */ #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PCKE 2 /* Reserved [0x2A] */ #define OCR1C _SFR_IO8(0x2B) #define OCR1B _SFR_IO8(0x2C) #define OCR1A _SFR_IO8(0x2D) #define TCNT1 _SFR_IO8(0x2E) #define TCCR1B _SFR_IO8(0x2F) #define CS10 0 #define CS11 1 #define CS12 2 #define CS13 3 #define PSR1 6 #define CTC1 7 #define TCCR1A _SFR_IO8(0x30) #define PWM1B 0 #define PWM1A 1 #define FOC1B 2 #define FOC1A 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define OSCCAL _SFR_IO8(0x31) #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define PSR0 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 /* Reserved [0x36..0x37] */ #define TIFR _SFR_IO8(0x38) #define TOV0 1 #define TOV1 2 #define OCF1B 5 #define OCF1A 6 #define TIMSK _SFR_IO8(0x39) #define TOIE0 1 #define TOIE1 2 #define OCIE1B 5 #define OCIE1A 6 #define GIFR _SFR_IO8(0x3A) #define PCIF 5 #define INTF0 6 #define GIMSK _SFR_IO8(0x3B) #define PCIE0 4 #define PCIE1 5 #define INT0 6 /* Reserved [0x3C] */ /* SP [0x3D] */ /* Reserved [0x3E] */ /* SREG [0x3F] */ /* Interrupt vectors */ /* Interrupt vector 0 is the reset vector. */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 0 */ #define IO_PINS_vect_num 2 #define IO_PINS_vect _VECTOR(2) #define SIG_PIN_CHANGE _VECTOR(2) /* Timer/Counter1 Compare Match 1A */ #define TIMER1_CMPA_vect_num 3 #define TIMER1_CMPA_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE1A _VECTOR(3) /* Timer/Counter1 Compare Match 1B */ #define TIMER1_CMPB_vect_num 4 #define TIMER1_CMPB_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1B _VECTOR(4) /* Timer/Counter1 Overflow */ #define TIMER1_OVF1_vect_num 5 #define TIMER1_OVF1_vect _VECTOR(5) #define SIG_OVERFLOW1 _VECTOR(5) /* Timer/Counter0 Overflow */ #define TIMER0_OVF0_vect_num 6 #define TIMER0_OVF0_vect _VECTOR(6) #define SIG_OVERFLOW0 _VECTOR(6) /* USI Start */ #define USI_STRT_vect_num 7 #define USI_STRT_vect _VECTOR(7) #define SIG_USI_START _VECTOR(7) /* USI Overflow */ #define USI_OVF_vect_num 8 #define USI_OVF_vect _VECTOR(8) #define SIG_USI_OVERFLOW _VECTOR(8) /* EEPROM Ready */ #define EE_RDY_vect_num 9 #define EE_RDY_vect _VECTOR(9) #define SIG_EEPROM_READY _VECTOR(9) /* Analog Comparator */ #define ANA_COMP_vect_num 10 #define ANA_COMP_vect _VECTOR(10) #define SIG_ANA_COMP _VECTOR(10) #define SIG_COMPARATOR _VECTOR(10) /* ADC Conversion Complete */ #define ADC_vect_num 11 #define ADC_vect _VECTOR(11) #define SIG_ADC _VECTOR(11) #define _VECTORS_SIZE 24 /* Constants */ #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 4 #define FLASHEND 0x07FF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOPT (unsigned char)~_BV(6) #define FUSE_PLLCK (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BODEN (unsigned char)~_BV(0) #define FUSE_BODLEVEL (unsigned char)~_BV(1) #define FUSE_EESAVE (unsigned char)~_BV(2) #define FUSE_SPIEN (unsigned char)~_BV(3) #define FUSE_RSTDISBL (unsigned char)~_BV(4) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x09 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_ANA_COMP #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOTN26_H_ */ avr-libc-1.8.0.orig/include/avr/Makefile.am0000644000000000000000000001213111732702554015317 0ustar # Copyright (c) 2004,2005,2006,2007 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 2211 2011-02-14 14:04:25Z aboyapati $ # avrdir = $(prefix)/avr/include/avr avr_HEADERS = \ boot.h \ common.h \ cpufunc.h \ crc16.h \ delay.h \ eeprom.h \ fuse.h \ interrupt.h \ io.h \ io1200.h \ io2313.h \ io2323.h \ io2333.h \ io2343.h \ io43u32x.h \ io43u35x.h \ io4414.h \ io4433.h \ io4434.h \ io76c711.h \ io8515.h \ io8534.h \ io8535.h \ io86r401.h \ io90pwm1.h \ io90pwmx.h \ io90pwm2b.h \ io90pwm216.h \ io90pwm3b.h \ io90pwm316.h \ io90pwm81.h \ io90scr100.h \ ioa6289.h \ ioat94k.h \ iocan32.h \ iocan64.h \ iocan128.h \ iocanxx.h \ iom103.h \ iom128.h \ iom1280.h \ iom1281.h \ iom1284p.h \ iom128rfa1.h \ iom16.h \ iom16a.h \ iom161.h \ iom162.h \ iom163.h \ iom164.h \ iom165.h \ iom165p.h \ iom168.h \ iom168p.h \ iom169.h \ iom169p.h \ iom169pa.h \ iom16hva.h \ iom16hva2.h \ iom16hvb.h \ iom16hvbrevb.h \ iom16m1.h \ iom16u2.h \ iom16u4.h \ iom2560.h \ iom2561.h \ iom3000.h \ iom32.h \ iom323.h \ iom324.h \ iom324pa.h \ iom325.h \ iom3250.h \ iom328p.h \ iom329.h \ iom3290.h \ iom32hvb.h \ iom32hvbrevb.h \ iom32c1.h \ iom32m1.h \ iom32u2.h \ iom32u4.h \ iom32u6.h \ iom48.h \ iom48p.h \ iom406.h \ iom64.h \ iom640.h \ iom644.h \ iom644p.h \ iom644pa.h \ iom645.h \ iom6450.h \ iom649.h \ iom649p.h \ iom6490.h \ iom64c1.h \ iom64hve.h \ iom64m1.h \ iom8.h \ iom8515.h \ iom8535.h \ iom88.h \ iom88p.h \ iom88pa.h \ iom8hva.h \ iom8u2.h \ iomx8.h \ iomxx0_1.h \ iomxx4.h \ iomxxhva.h \ iotn4.h \ iotn5.h \ iotn9.h \ iotn10.h \ iotn11.h \ iotn12.h \ iotn13.h \ iotn13a.h \ iotn15.h \ iotn167.h \ iotn20.h \ iotn22.h \ iotn2313.h \ iotn2313a.h \ iotn24.h \ iotn24a.h \ iotn25.h \ iotn26.h \ iotn261.h \ iotn261a.h \ iotn28.h \ iotn40.h \ iotn4313.h \ iotn43u.h \ iotn44.h \ iotn44a.h \ iotn45.h \ iotn461.h \ iotn461a.h \ iotn48.h \ iotn88.h \ iotn84.h \ iotn84a.h \ iotn85.h \ iotn861.h \ iotn861a.h \ iotn87.h \ iotnx4.h \ iotnx5.h \ iotnx61.h \ iousb82.h \ iousb1286.h \ iousb1287.h \ iousb162.h \ iousbxx2.h \ iousb646.h \ iousb647.h \ iousbxx6_7.h \ iox64d3.h \ iox128a1.h \ iox128a1u.h \ iox128a3.h \ iox128d3.h \ iox16a4.h \ iox16d4.h \ iox192a3.h \ iox192d3.h \ iox256a3.h \ iox256a3b.h \ iox256d3.h \ iox32a4.h \ iox32d4.h \ iox64a1.h \ iox64a1u.h \ iox64a3.h \ lock.h \ parity.h \ pgmspace.h \ portpins.h \ power.h \ signature.h \ sfr_defs.h \ signal.h \ sleep.h \ version.h \ wdt.h nodist_avr_HEADERS = \ builtins.h EXTRA_DIST = \ builtins.h.in \ version.h.in do_subst = sed \ -e 's,[@]AVR_LIBC_MAJOR[@],$(AVR_LIBC_MAJOR),g' \ -e 's,[@]AVR_LIBC_MINOR[@],$(AVR_LIBC_MINOR),g' \ -e 's,[@]AVR_LIBC_REVISION[@],$(AVR_LIBC_REVISION),g' \ -e 's,[@]AVR_LIBC_RELDATE[@],$(AVR_LIBC_RELDATE),g' \ -e 's,[@]AVR_LIBC_VERSION[@],$(AVR_LIBC_VERSION),g' \ -e 's,[@]AVR_LIBC_VERSION_NUMERIC[@],$(AVR_LIBC_VERSION_NUMERIC),g' version.h: version.h.in $(top_builddir)/config.h $(do_subst) < $(srcdir)/version.h.in > version.h CLEANFILES = version.h avr-libc-1.8.0.orig/include/avr/io4414.h0000644000000000000000000003017411732702554014367 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io4414.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io4414.h - definitions for AT90S4414 */ #ifndef _AVR_IO4414_H_ #define _AVR_IO4414_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io4414.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* UART Baud Rate Register */ #define UBRR _SFR_IO8(0x09) /* UART Control Register */ #define UCR _SFR_IO8(0x0A) /* UART Status Register */ #define USR _SFR_IO8(0x0B) /* UART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x24) #define ICR1L _SFR_IO8(0x24) #define ICR1H _SFR_IO8(0x25) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3C..0x3D SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter Capture Event */ #define TIMER1_CAPT_vect_num 3 #define TIMER1_CAPT_vect _VECTOR(3) #define SIG_INPUT_CAPTURE1 _VECTOR(3) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 4 #define TIMER1_COMPA_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE1A _VECTOR(4) /* Timer/Counter1 Compare MatchB */ #define TIMER1_COMPB_vect_num 5 #define TIMER1_COMPB_vect _VECTOR(5) #define SIG_OUTPUT_COMPARE1B _VECTOR(5) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 6 #define TIMER1_OVF_vect _VECTOR(6) #define SIG_OVERFLOW1 _VECTOR(6) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 7 #define TIMER0_OVF_vect _VECTOR(7) #define SIG_OVERFLOW0 _VECTOR(7) /* Serial Transfer Complete */ #define SPI_STC_vect_num 8 #define SPI_STC_vect _VECTOR(8) #define SIG_SPI _VECTOR(8) /* UART, Rx Complete */ #define UART_RX_vect_num 9 #define UART_RX_vect _VECTOR(9) #define SIG_UART_RECV _VECTOR(9) /* UART Data Register Empty */ #define UART_UDRE_vect_num 10 #define UART_UDRE_vect _VECTOR(10) #define SIG_UART_DATA _VECTOR(10) /* UART, Tx Complete */ #define UART_TX_vect_num 11 #define UART_TX_vect _VECTOR(11) #define SIG_UART_TRANS _VECTOR(11) /* Analog Comparator */ #define ANA_COMP_vect_num 12 #define ANA_COMP_vect _VECTOR(12) #define SIG_COMPARATOR _VECTOR(12) #define _VECTORS_SIZE 26 /* The Register Bit names are represented by their bit number (0-7). */ /* General Interrupt MaSK register */ #define INT1 7 #define INT0 6 /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 /* Timer/Counter Interrupt MaSK register */ #define TOIE1 7 #define OCIE1A 6 #define OCIE1B 5 #define TICIE1 3 #define TOIE0 1 /* Timer/Counter Interrupt Flag register */ #define TOV1 7 #define OCF1A 6 #define OCF1B 5 #define ICF1 3 #define TOV0 1 /* MCU general Control Register */ #define SRE 7 #define SRW 6 #define SE 5 #define SM 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define PWM11 1 #define PWM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define CTC1 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* Data Register, Port A */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Data Direction Register, Port A */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Input Pins, Port A */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port C */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Direction Register, Port C */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UART Status Register */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 /* UART Control Register */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define CHR9 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0x15F /* Last On-Chip SRAM Location */ #define XRAMEND 0xFFFF #define E2END 0xFF #define E2PAGESIZE 0 #define FLASHEND 0xFFF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ #define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ #define LFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x01 #endif /* _AVR_IO4414_H_ */ avr-libc-1.8.0.orig/include/avr/iom128.h0000644000000000000000000010255611732702554014466 0ustar /* Copyright (c) 2002, Peter Jansen Copyright (c) 2007, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom128.h 2226 2011-03-04 17:47:16Z arcanum $ */ /* avr/iom128.h - defines for ATmega128 As of 2002-08-27: - This should be up to date with data sheet 2467E-AVR-05/02 */ #ifndef _AVR_IOM128_H_ #define _AVR_IOM128_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom128.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Input Pins, Port F */ #define PINF _SFR_IO8(0x00) /* Input Pins, Port E */ #define PINE _SFR_IO8(0x01) /* Data Direction Register, Port E */ #define DDRE _SFR_IO8(0x02) /* Data Register, Port E */ #define PORTE _SFR_IO8(0x03) /* ADC Data Register */ #define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and status register */ #define ADCSR _SFR_IO8(0x06) #define ADCSRA _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */ /* ADC Multiplexer select */ #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* USART0 Baud Rate Register Low */ #define UBRR0L _SFR_IO8(0x09) /* USART0 Control and Status Register B */ #define UCSR0B _SFR_IO8(0x0A) /* USART0 Control and Status Register A */ #define UCSR0A _SFR_IO8(0x0B) /* USART0 I/O Data Register */ #define UDR0 _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* Special Function I/O Register */ #define SFIOR _SFR_IO8(0x20) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* On-chip Debug Register */ #define OCDR _SFR_IO8(0x22) /* Timer2 Output Compare Register */ #define OCR2 _SFR_IO8(0x23) /* Timer/Counter 2 */ #define TCNT2 _SFR_IO8(0x24) /* Timer/Counter 2 Control register */ #define TCCR2 _SFR_IO8(0x25) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 0 Asynchronous Control & Status Register */ #define ASSR _SFR_IO8(0x30) /* Output Compare Register 0 */ #define OCR0 _SFR_IO8(0x31) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) #define MCUCSR _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */ /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x36) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x37) /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x38) /* External Interrupt MaSK register */ #define EIMSK _SFR_IO8(0x39) /* External Interrupt Control Register B */ #define EICRB _SFR_IO8(0x3A) /* RAM Page Z select register */ #define RAMPZ _SFR_IO8(0x3B) /* XDIV Divide control register */ #define XDIV _SFR_IO8(0x3C) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Extended I/O registers */ /* Data Direction Register, Port F */ #define DDRF _SFR_MEM8(0x61) /* Data Register, Port F */ #define PORTF _SFR_MEM8(0x62) /* Input Pins, Port G */ #define PING _SFR_MEM8(0x63) /* Data Direction Register, Port G */ #define DDRG _SFR_MEM8(0x64) /* Data Register, Port G */ #define PORTG _SFR_MEM8(0x65) /* Store Program Memory Control and Status Register */ #define SPMCR _SFR_MEM8(0x68) #define SPMCSR _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */ /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x6A) /* External Memory Control Register B */ #define XMCRB _SFR_MEM8(0x6C) /* External Memory Control Register A */ #define XMCRA _SFR_MEM8(0x6D) /* Oscillator Calibration Register */ #define OSCCAL _SFR_MEM8(0x6F) /* 2-wire Serial Interface Bit Rate Register */ #define TWBR _SFR_MEM8(0x70) /* 2-wire Serial Interface Status Register */ #define TWSR _SFR_MEM8(0x71) /* 2-wire Serial Interface Address Register */ #define TWAR _SFR_MEM8(0x72) /* 2-wire Serial Interface Data Register */ #define TWDR _SFR_MEM8(0x73) /* 2-wire Serial Interface Control Register */ #define TWCR _SFR_MEM8(0x74) /* Time Counter 1 Output Compare Register C */ #define OCR1C _SFR_MEM16(0x78) #define OCR1CL _SFR_MEM8(0x78) #define OCR1CH _SFR_MEM8(0x79) /* Timer/Counter 1 Control Register C */ #define TCCR1C _SFR_MEM8(0x7A) /* Extended Timer Interrupt Flag Register */ #define ETIFR _SFR_MEM8(0x7C) /* Extended Timer Interrupt Mask Register */ #define ETIMSK _SFR_MEM8(0x7D) /* Timer/Counter 3 Input Capture Register */ #define ICR3 _SFR_MEM16(0x80) #define ICR3L _SFR_MEM8(0x80) #define ICR3H _SFR_MEM8(0x81) /* Timer/Counter 3 Output Compare Register C */ #define OCR3C _SFR_MEM16(0x82) #define OCR3CL _SFR_MEM8(0x82) #define OCR3CH _SFR_MEM8(0x83) /* Timer/Counter 3 Output Compare Register B */ #define OCR3B _SFR_MEM16(0x84) #define OCR3BL _SFR_MEM8(0x84) #define OCR3BH _SFR_MEM8(0x85) /* Timer/Counter 3 Output Compare Register A */ #define OCR3A _SFR_MEM16(0x86) #define OCR3AL _SFR_MEM8(0x86) #define OCR3AH _SFR_MEM8(0x87) /* Timer/Counter 3 Counter Register */ #define TCNT3 _SFR_MEM16(0x88) #define TCNT3L _SFR_MEM8(0x88) #define TCNT3H _SFR_MEM8(0x89) /* Timer/Counter 3 Control Register B */ #define TCCR3B _SFR_MEM8(0x8A) /* Timer/Counter 3 Control Register A */ #define TCCR3A _SFR_MEM8(0x8B) /* Timer/Counter 3 Control Register C */ #define TCCR3C _SFR_MEM8(0x8C) /* USART0 Baud Rate Register High */ #define UBRR0H _SFR_MEM8(0x90) /* USART0 Control and Status Register C */ #define UCSR0C _SFR_MEM8(0x95) /* USART1 Baud Rate Register High */ #define UBRR1H _SFR_MEM8(0x98) /* USART1 Baud Rate Register Low*/ #define UBRR1L _SFR_MEM8(0x99) /* USART1 Control and Status Register B */ #define UCSR1B _SFR_MEM8(0x9A) /* USART1 Control and Status Register A */ #define UCSR1A _SFR_MEM8(0x9B) /* USART1 I/O Data Register */ #define UDR1 _SFR_MEM8(0x9C) /* USART1 Control and Status Register C */ #define UCSR1C _SFR_MEM8(0x9D) /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* External Interrupt Request 2 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) #define SIG_INTERRUPT2 _VECTOR(3) /* External Interrupt Request 3 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) #define SIG_INTERRUPT3 _VECTOR(4) /* External Interrupt Request 4 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) #define SIG_INTERRUPT4 _VECTOR(5) /* External Interrupt Request 5 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) #define SIG_INTERRUPT5 _VECTOR(6) /* External Interrupt Request 6 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) #define SIG_INTERRUPT6 _VECTOR(7) /* External Interrupt Request 7 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) #define SIG_INTERRUPT7 _VECTOR(8) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 9 #define TIMER2_COMP_vect _VECTOR(9) #define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 10 #define TIMER2_OVF_vect _VECTOR(10) #define SIG_OVERFLOW2 _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) #define SIG_INPUT_CAPTURE1 _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 14 #define TIMER1_OVF_vect _VECTOR(14) #define SIG_OVERFLOW1 _VECTOR(14) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 15 #define TIMER0_COMP_vect _VECTOR(15) #define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 16 #define TIMER0_OVF_vect _VECTOR(16) #define SIG_OVERFLOW0 _VECTOR(16) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 17 #define SPI_STC_vect _VECTOR(17) #define SIG_SPI _VECTOR(17) /* USART0, Rx Complete */ #define USART0_RX_vect_num 18 #define USART0_RX_vect _VECTOR(18) #define SIG_USART0_RECV _VECTOR(18) #define SIG_UART0_RECV _VECTOR(18) /* USART0 Data Register Empty */ #define USART0_UDRE_vect_num 19 #define USART0_UDRE_vect _VECTOR(19) #define SIG_USART0_DATA _VECTOR(19) #define SIG_UART0_DATA _VECTOR(19) /* USART0, Tx Complete */ #define USART0_TX_vect_num 20 #define USART0_TX_vect _VECTOR(20) #define SIG_USART0_TRANS _VECTOR(20) #define SIG_UART0_TRANS _VECTOR(20) /* ADC Conversion Complete */ #define ADC_vect_num 21 #define ADC_vect _VECTOR(21) #define SIG_ADC _VECTOR(21) /* EEPROM Ready */ #define EE_READY_vect _VECTOR(22) #define EE_READY_vect _VECTOR(22) #define SIG_EEPROM_READY _VECTOR(22) /* Analog Comparator */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) #define SIG_COMPARATOR _VECTOR(23) /* Timer/Counter1 Compare Match C */ #define TIMER1_COMPC_vect_num 24 #define TIMER1_COMPC_vect _VECTOR(24) #define SIG_OUTPUT_COMPARE1C _VECTOR(24) /* Timer/Counter3 Capture Event */ #define TIMER3_CAPT_vect_num 25 #define TIMER3_CAPT_vect _VECTOR(25) #define SIG_INPUT_CAPTURE3 _VECTOR(25) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPA_vect_num 26 #define TIMER3_COMPA_vect _VECTOR(26) #define SIG_OUTPUT_COMPARE3A _VECTOR(26) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPB_vect_num 27 #define TIMER3_COMPB_vect _VECTOR(27) #define SIG_OUTPUT_COMPARE3B _VECTOR(27) /* Timer/Counter3 Compare Match C */ #define TIMER3_COMPC_vect_num 28 #define TIMER3_COMPC_vect _VECTOR(28) #define SIG_OUTPUT_COMPARE3C _VECTOR(28) /* Timer/Counter3 Overflow */ #define TIMER3_OVF_vect_num 29 #define TIMER3_OVF_vect _VECTOR(29) #define SIG_OVERFLOW3 _VECTOR(29) /* USART1, Rx Complete */ #define USART1_RX_vect_num 30 #define USART1_RX_vect _VECTOR(30) #define SIG_USART1_RECV _VECTOR(30) #define SIG_UART1_RECV _VECTOR(30) /* USART1, Data Register Empty */ #define USART1_UDRE_vect_num 31 #define USART1_UDRE_vect _VECTOR(31) #define SIG_USART1_DATA _VECTOR(31) #define SIG_UART1_DATA _VECTOR(31) /* USART1, Tx Complete */ #define USART1_TX_vect_num 32 #define USART1_TX_vect _VECTOR(32) #define SIG_USART1_TRANS _VECTOR(32) #define SIG_UART1_TRANS _VECTOR(32) /* 2-wire Serial Interface */ #define TWI_vect_num 33 #define TWI_vect _VECTOR(33) #define SIG_2WIRE_SERIAL _VECTOR(33) /* Store Program Memory Read */ #define SPM_READY_vect_num 34 #define SPM_READY_vect _VECTOR(34) #define SPM_READY_vect _VECTOR(34) #define SIG_SPM_READY _VECTOR(34) #define _VECTORS_SIZE 140 /* The Register Bit names are represented by their bit number (0-7). */ /* 2-wire Control Register - TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 /* 2-wire Address Register - TWAR */ #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 /* 2-wire Status Register - TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 /* External Memory Control Register A - XMCRA */ #define SRL2 6 #define SRL1 5 #define SRL0 4 #define SRW01 3 #define SRW00 2 #define SRW11 1 /* External Memory Control Register B - XMCRA */ #define XMBK 7 #define XMM2 2 #define XMM1 1 #define XMM0 0 /* XDIV Divide control register - XDIV */ #define XDIVEN 7 #define XDIV6 6 #define XDIV5 5 #define XDIV4 4 #define XDIV3 3 #define XDIV2 2 #define XDIV1 1 #define XDIV0 0 /* RAM Page Z select register - RAMPZ */ #define RAMPZ0 0 /* External Interrupt Control Register A - EICRA */ #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* External Interrupt Control Register B - EICRB */ #define ISC71 7 #define ISC70 6 #define ISC61 5 #define ISC60 4 #define ISC51 3 #define ISC50 2 #define ISC41 1 #define ISC40 0 /* Store Program Memory Control Register - SPMCSR, SPMCR */ #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* External Interrupt MaSK register - EIMSK */ #define INT7 7 #define INT6 6 #define INT5 5 #define INT4 4 #define INT3 3 #define INT2 2 #define INT1 1 #define INT0 0 /* External Interrupt Flag Register - EIFR */ #define INTF7 7 #define INTF6 6 #define INTF5 5 #define INTF4 4 #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 /* Timer/Counter Interrupt MaSK register - TIMSK */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 /* Timer/Counter Interrupt Flag Register - TIFR */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 /* Extended Timer Interrupt MaSK register - ETIMSK */ #define TICIE3 5 #define OCIE3A 4 #define OCIE3B 3 #define TOIE3 2 #define OCIE3C 1 #define OCIE1C 0 /* Extended Timer Interrupt Flag Register - ETIFR */ #define ICF3 5 #define OCF3A 4 #define OCF3B 3 #define TOV3 2 #define OCF3C 1 #define OCF1C 0 /* MCU general Control Register - MCUCR */ #define SRE 7 #define SRW 6 #define SRW10 6 /* new name in datasheet (2467E-AVR-05/02) */ #define SE 5 #define SM1 4 #define SM0 3 #define SM2 2 #define IVSEL 1 #define IVCE 0 /* MCU Status Register - MCUSR, MCUCSR */ #define JTD 7 #define JTRF 4 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* Timer/Counter Control Register (generic) */ #define FOC 7 #define WGM0 6 #define COM1 5 #define COM0 4 #define WGM1 3 #define CS2 2 #define CS1 1 #define CS0 0 /* Timer/Counter 0 Control Register - TCCR0 */ #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* Timer/Counter 2 Control Register - TCCR2 */ #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ #define AS0 3 #define TCN0UB 2 #define OCR0UB 1 #define TCR0UB 0 /* Timer/Counter Control Register A (generic) */ #define COMA1 7 #define COMA0 6 #define COMB1 5 #define COMB0 4 #define COMC1 3 #define COMC0 2 #define WGMA1 1 #define WGMA0 0 /* Timer/Counter 1 Control and Status Register A - TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define COM1C1 3 #define COM1C0 2 #define WGM11 1 #define WGM10 0 /* Timer/Counter 3 Control and Status Register A - TCCR3A */ #define COM3A1 7 #define COM3A0 6 #define COM3B1 5 #define COM3B0 4 #define COM3C1 3 #define COM3C0 2 #define WGM31 1 #define WGM30 0 /* Timer/Counter Control and Status Register B (generic) */ #define ICNC 7 #define ICES 6 #define WGMB3 4 #define WGMB2 3 #define CSB2 2 #define CSB1 1 #define CSB0 0 /* Timer/Counter 1 Control and Status Register B - TCCR1B */ #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Timer/Counter 3 Control and Status Register B - TCCR3B */ #define ICNC3 7 #define ICES3 6 #define WGM33 4 #define WGM32 3 #define CS32 2 #define CS31 1 #define CS30 0 /* Timer/Counter Control Register C (generic) */ #define FOCA 7 #define FOCB 6 #define FOCC 5 /* Timer/Counter 3 Control Register C - TCCR3C */ #define FOC3A 7 #define FOC3B 6 #define FOC3C 5 /* Timer/Counter 1 Control Register C - TCCR1C */ #define FOC1A 7 #define FOC1B 6 #define FOC1C 5 /* On-chip Debug Register - OCDR */ #define IDRD 7 #define OCDR7 7 #define OCDR6 6 #define OCDR5 5 #define OCDR4 4 #define OCDR3 3 #define OCDR2 2 #define OCDR1 1 #define OCDR0 0 /* Watchdog Timer Control Register - WDTCR */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ /* Special Function I/O Register - SFIOR */ #define TSM 7 #define ACME 3 #define PUD 2 #define PSR0 1 #define PSR321 0 /* SPI Status Register - SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPI Control Register - SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* USART Register C (generic) */ #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* USART1 Register C - UCSR1C */ #define UMSEL1 6 #define UPM11 5 #define UPM10 4 #define USBS1 3 #define UCSZ11 2 #define UCSZ10 1 #define UCPOL1 0 /* USART0 Register C - UCSR0C */ #define UMSEL0 6 #define UPM01 5 #define UPM00 4 #define USBS0 3 #define UCSZ01 2 #define UCSZ00 1 #define UCPOL0 0 /* USART Status Register A (generic) */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define UPE 2 #define U2X 1 #define MPCM 0 /* USART1 Status Register A - UCSR1A */ #define RXC1 7 #define TXC1 6 #define UDRE1 5 #define FE1 4 #define DOR1 3 #define UPE1 2 #define U2X1 1 #define MPCM1 0 /* USART0 Status Register A - UCSR0A */ #define RXC0 7 #define TXC0 6 #define UDRE0 5 #define FE0 4 #define DOR0 3 #define UPE0 2 #define U2X0 1 #define MPCM0 0 /* USART Control Register B (generic) */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ 2 #define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ #define RXB8 1 #define TXB8 0 /* USART1 Control Register B - UCSR1B */ #define RXCIE1 7 #define TXCIE1 6 #define UDRIE1 5 #define RXEN1 4 #define TXEN1 3 #define UCSZ12 2 #define RXB81 1 #define TXB81 0 /* USART0 Control Register B - UCSR0B */ #define RXCIE0 7 #define TXCIE0 6 #define UDRIE0 5 #define RXEN0 4 #define TXEN0 3 #define UCSZ02 2 #define RXB80 1 #define TXB80 0 /* Analog Comparator Control and Status Register - ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADC Control and status register - ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADC Multiplexer select - ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* Port A Data Register - PORTA */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Port A Data Direction Register - DDRA */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Port A Input Pins - PINA */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Port B Data Register - PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Port B Data Direction Register - DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Port B Input Pins - PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Port C Data Register - PORTC */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Port C Data Direction Register - DDRC */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Port C Input Pins - PINC */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Port D Data Register - PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Port D Data Direction Register - DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Port D Input Pins - PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Port E Data Register - PORTE */ #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 /* Port E Data Direction Register - DDRE */ #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 /* Port E Input Pins - PINE */ #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 /* Port F Data Register - PORTF */ #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 /* Port F Data Direction Register - DDRF */ #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 /* Port F Input Pins - PINF */ #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 /* Port G Data Register - PORTG */ #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 /* Port G Data Direction Register - DDRG */ #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 /* Port G Input Pins - PING */ #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x10FF /* Last On-Chip SRAM Location */ #define XRAMEND 0xFFFF #define E2END 0x0FFF #define E2PAGESIZE 8 #define FLASHEND 0x1FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_WDTON (unsigned char)~_BV(0) #define FUSE_M103C (unsigned char)~_BV(1) #define EFUSE_DEFAULT (FUSE_M103C) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x02 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison ADCW #pragma GCC poison MCUSR #pragma GCC poison SPMCR #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_INTERRUPT3 #pragma GCC poison SIG_INTERRUPT4 #pragma GCC poison SIG_INTERRUPT5 #pragma GCC poison SIG_INTERRUPT6 #pragma GCC poison SIG_INTERRUPT7 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_USART0_RECV #pragma GCC poison SIG_UART0_RECV #pragma GCC poison SIG_USART0_DATA #pragma GCC poison SIG_UART0_DATA #pragma GCC poison SIG_USART0_TRANS #pragma GCC poison SIG_UART0_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_OUTPUT_COMPARE1C #pragma GCC poison SIG_INPUT_CAPTURE3 #pragma GCC poison SIG_OUTPUT_COMPARE3A #pragma GCC poison SIG_OUTPUT_COMPARE3B #pragma GCC poison SIG_OUTPUT_COMPARE3C #pragma GCC poison SIG_OVERFLOW3 #pragma GCC poison SIG_USART1_RECV #pragma GCC poison SIG_UART1_RECV #pragma GCC poison SIG_USART1_DATA #pragma GCC poison SIG_UART1_DATA #pragma GCC poison SIG_USART1_TRANS #pragma GCC poison SIG_UART1_TRANS #pragma GCC poison SIG_2WIRE_SERIAL #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM128_H_ */ avr-libc-1.8.0.orig/include/avr/iom165p.h0000644000000000000000000004504511732702554014646 0ustar /* Copyright (c) 2004,2005,2006 Eric B. Weddington Copyright (c) 2006 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom165p.h 2231 2011-03-07 05:06:55Z arcanum $ */ /* avr/iom165p.h - definitions for ATmega165P */ #ifndef _AVR_IOM165P_H_ #define _AVR_IOM165P_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom165p.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 6 #define PCIF1 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 6 #define PCIE1 7 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCD 7 // The datasheet defines this but IMO it should be OCDR7. #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ /* Combine PCMSK0 and PCMSK1 */ #define PCMSK _SFR_MEM16(0x6B) #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 /* Reserved [0x6D] */ #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0XC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 /* Reserved [0xC3] */ /* Combine UBRRL and UBRRH */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7..0xFF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART0, Rx Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) #define USART_RX_vect _VECTOR(13) /* Alias */ #define SIG_UART_RECV _VECTOR(13) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) #define USART_UDRE_vect _VECTOR(14) /* Alias */ #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define USART_TX_vect _VECTOR(15) /* Alias */ #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) #define _VECTORS_SIZE 88 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x4FF #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x07 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison USART_RX_vect #pragma GCC poison SIG_UART_RECV #pragma GCC poison USART_UDRE_vect #pragma GCC poison SIG_UART_DATA #pragma GCC poison USART_TX_vect #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM165P_H_ */ avr-libc-1.8.0.orig/include/avr/iom1280.h0000644000000000000000000000650511732702554014543 0ustar /* Copyright (c) 2005 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom1280.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/iom1280.h - definitions for ATmega1280 */ #ifndef _AVR_IOM1280_H_ #define _AVR_IOM1280_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x21FF #define XRAMEND 0xFFFF #define E2END 0xFFF #define E2PAGESIZE 8 #define FLASHEND 0x1FFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 #define SIGNATURE_2 0x03 #endif /* _AVR_IOM1280_H_ */ avr-libc-1.8.0.orig/include/avr/iotn167.h0000644000000000000000000004175311732702554014657 0ustar /* Copyright (c) 2008-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn167.h 2253 2011-09-26 14:53:41Z arcanum $ */ /* avr/iotn167.h - definitions for ATtiny167. */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn167.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOTN167_H_ #define _AVR_IOTN167_H_ 1 /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PORTCR _SFR_IO8(0x12) #define PUDA 0 #define PUDB 2 #define BBMA 4 #define BBMB 5 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define GTCCR _SFR_IO8(0x23) #define PSR1 0 #define PSR0 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x25) #define WGM00 0 #define WGM01 1 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x26) #define CS00 0 #define CS01 1 #define CS02 2 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x27) #define TCNT00 0 #define TCNT01 1 #define TCNT02 2 #define TCNT03 3 #define TCNT04 4 #define TCNT05 5 #define TCNT06 6 #define TCNT07 7 #define OCR0A _SFR_IO8(0x28) #define OCR00 0 #define OCR01 1 #define OCR02 2 #define OCR03 3 #define OCR04 4 #define OCR05 5 #define OCR06 6 #define OCR07 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACIRS 6 #define ACD 7 #define DWDR _SFR_IO8(0x31) #define DWDR0 0 #define DWDR1 1 #define DWDR2 2 #define DWDR3 3 #define DWDR4 4 #define DWDR5 5 #define DWDR6 6 #define DWDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define PUD 4 #define BODSE 5 #define BODS 6 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define SIGRD 5 #define RWWSB 6 #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define CLKCSR _SFR_MEM8(0x62) #define CLKC0 0 #define CLKC1 1 #define CLKC2 2 #define CLKC3 3 #define CLKRDY 4 #define CLKCCE 7 #define CLKSELR _SFR_MEM8(0x63) #define CSEL0 0 #define CSEL1 1 #define CSEL2 2 #define CSEL3 3 #define CSUT0 4 #define CSUT1 5 #define COUT 6 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define PRSPI 4 #define PRLIN 5 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define AMISCR _SFR_MEM8(0x77) #define ISRCEN 0 #define XREFEN 1 #define AREFEN 2 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACIR0 4 #define ACIR1 5 #define ACME 6 #define BIN 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCCR1D _SFR_MEM8(0x83) #define OC1AU 0 #define OC1AV 1 #define OC1AW 2 #define OC1AX 3 #define OC1BU 4 #define OC1BV 5 #define OC1BW 6 #define OC1BX 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR0BUB 0 #define TCR0AUB 1 #define OCR0AUB 3 #define TCN0UB 4 #define AS0 5 #define EXCLK 6 #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define USIBR _SFR_MEM8(0xBB) #define USIBR0 0 #define USIBR1 1 #define USIBR2 2 #define USIBR3 3 #define USIBR4 4 #define USIBR5 5 #define USIBR6 6 #define USIBR7 7 #define USIPP _SFR_MEM8(0xBC) #define USIPOS 0 #define LINCR _SFR_MEM8(0xC8) #define LCMD0 0 #define LCMD1 1 #define LCMD2 2 #define LENA 3 #define LCONF0 4 #define LCONF1 5 #define LIN13 6 #define LSWRES 7 #define LINSIR _SFR_MEM8(0xC9) #define LRXOK 0 #define LTXOK 1 #define LIDOK 2 #define LERR 3 #define LBUSY 4 #define LIDST0 5 #define LIDST1 6 #define LIDST2 7 #define LINENIR _SFR_MEM8(0xCA) #define LENRXOK 0 #define LENTXOK 1 #define LENIDOK 2 #define LENERR 3 #define LINERR _SFR_MEM8(0xCB) #define LBERR 0 #define LCERR 1 #define LPERR 2 #define LSERR 3 #define LFERR 4 #define LOVERR 5 #define LTOERR 6 #define LABORT 7 #define LINBTR _SFR_MEM8(0xCC) #define LBT0 0 #define LBT1 1 #define LBT2 2 #define LBT3 3 #define LBT4 4 #define LBT5 5 #define LDISR 7 #define LINBRR _SFR_MEM16(0xCD) #define LINBRRL _SFR_MEM8(0xCD) #define LDIV0 0 #define LDIV1 1 #define LDIV2 2 #define LDIV3 3 #define LDIV4 4 #define LDIV5 5 #define LDIV6 6 #define LDIV7 7 #define LINBRRH _SFR_MEM8(0xCE) #define LDIV8 0 #define LDIV9 1 #define LDIV10 2 #define LDIV11 3 #define LINDLR _SFR_MEM8(0xCF) #define LRXDL0 0 #define LRXDL1 1 #define LRXDL2 2 #define LRXDL3 3 #define LTXDL0 4 #define LTXDL1 5 #define LTXDL2 6 #define LTXDL3 7 #define LINIDR _SFR_MEM8(0xD0) #define LID0 0 #define LID1 1 #define LID2 2 #define LID3 3 #define LID4 4 #define LID5 5 #define LP0 6 #define LP1 7 #define LINSEL _SFR_MEM8(0xD1) #define LINDX0 0 #define LINDX1 1 #define LINDX2 2 #define LAINC 3 #define LINDAT _SFR_MEM8(0xD2) #define LDATA0 0 #define LDATA1 1 #define LDATA2 2 #define LDATA3 3 #define LDATA4 4 #define LDATA5 5 #define LDATA6 6 #define LDATA7 7 /* Interrupt Vectors */ /* Interrupt Vector 0 is the reset vector. */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ #define WDT_vect_num 5 #define WDT_vect _VECTOR(5) /* Watchdog Time-Out Interrupt */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match 1A */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter1 Compare Match 1B */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 10 #define TIMER0_COMPA_vect _VECTOR(10) /* Timer/Counter0 Compare Match 0A */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ #define LIN_TC_vect_num 12 #define LIN_TC_vect _VECTOR(12) /* LIN Transfer Complete */ #define LIN_ERR_vect_num 13 #define LIN_ERR_vect _VECTOR(13) /* LIN Error */ #define SPI_STC_vect_num 14 #define SPI_STC_vect _VECTOR(14) /* SPI Serial Transfer Complete */ #define ADC_vect_num 15 #define ADC_vect _VECTOR(15) /* ADC Conversion Complete */ #define EE_RDY_vect_num 16 #define EE_RDY_vect _VECTOR(16) /* EEPROM Ready */ #define ANA_COMP_vect_num 17 #define ANA_COMP_vect _VECTOR(17) /* Analog Comparator */ #define USI_START_vect_num 18 #define USI_START_vect _VECTOR(18) /* USI Start */ #define USI_OVF_vect_num 19 #define USI_OVF_vect _VECTOR(19) /* USI Overflow */ #define _VECTORS_SIZE (20 * 4) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (0x1FF) #define RAMEND (RAMSTART + RAMSIZE - 1) /* Last On-Chip SRAM Location */ #define XRAMSIZE (0) #define XRAMEND RAMEND #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x3FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always ON */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x87 #endif /* _AVR_IOTN167_H_ */ avr-libc-1.8.0.orig/include/avr/iom168p.h0000644000000000000000000004445611732702554014656 0ustar /* Copyright (c) 2007 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom168p.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iom168p.h - definitions for ATmega168P. */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom168p.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOM168P_H_ #define _AVR_IOM168P_H_ 1 /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEPROM_REG_LOCATIONS 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 #define BODS 6 #define SPMCSR _SFR_IO8(0x37) #define SELFPRGEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 0 #define TWAM1 1 #define TWAM2 2 #define TWAM3 3 #define TWAM4 4 #define TWAM5 5 #define TWAM6 6 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCPHA0 1 #define UCSZ01 2 #define UDORD0 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL01 7 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0_0 0 #define UBRR0_1 1 #define UBRR0_2 2 #define UBRR0_3 3 #define UBRR0_4 4 #define UBRR0_5 5 #define UBRR0_6 6 #define UBRR0_7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR0_8 0 #define UBRR0_9 1 #define UBRR0_10 2 #define UBRR0_11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR0_0 0 #define UDR0_1 1 #define UDR0_2 2 #define UDR0_3 3 #define UDR0_4 4 #define UDR0_5 5 #define UDR0_6 6 #define UDR0_7 7 /* Interrupt Vectors */ /* Interrupt Vector 0 is the reset vector. */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ #define PCINT2_vect_num 5 #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ #define WDT_vect_num 6 #define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 7 #define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 8 #define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ #define TIMER2_OVF_vect_num 9 #define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 10 #define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 11 #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 12 #define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ #define TIMER0_OVF_vect_num 16 #define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ #define SPI_STC_vect_num 17 #define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ #define USART_RX_vect_num 18 #define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ #define USART_UDRE_vect_num 19 #define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ #define USART_TX_vect_num 20 #define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ #define ADC_vect_num 21 #define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ #define EE_READY_vect_num 22 #define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ #define TWI_vect_num 24 #define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ #define SPM_READY_vect_num 25 #define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ #define _VECTORS_SIZE (26 * 4) /* Constants */ #define SPM_PAGESIZE 128 #define RAMSTART (0x100) #define RAMEND 0x4FF /* Last On-Chip SRAM Location */ #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x0B #endif /* _AVR_IOM168P_H_ */ avr-libc-1.8.0.orig/include/avr/iom329.h0000644000000000000000000005263511732702554014473 0ustar /* Copyright (c) 2004 Eric B. Weddington Copyright (c) 2005, 2006, 2007 Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* avr/iom329.h - definitions for ATmega329 and ATmega329P. */ #ifndef _AVR_IOM329_H_ #define _AVR_IOM329_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom329.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #if defined(__AVR_ATmega329P__) #define BODSE 5 #define BODS 6 #endif #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRLCD 4 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 /* Reserved [0x6D] */ #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0XC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7..0xE3] */ #define LCDCRA _SFR_MEM8(0XE4) #define LCDBL 0 #if defined(__AVR_ATmega329P__) #define LCDCCD 1 #define LCDBD 2 #endif #define LCDIE 3 #define LCDIF 4 #define LCDAB 6 #define LCDEN 7 #define LCDCRB _SFR_MEM8(0XE5) #define LCDPM0 0 #define LCDPM1 1 #define LCDPM2 2 #define LCDMUX0 4 #define LCDMUX1 5 #define LCD2B 6 #define LCDCS 7 #define LCDFRR _SFR_MEM8(0XE6) #define LCDCD0 0 #define LCDCD1 1 #define LCDCD2 2 #define LCDPS0 4 #define LCDPS1 5 #define LCDPS2 6 #define LCDCCR _SFR_MEM8(0XE7) #define LCDCC0 0 #define LCDCC1 1 #define LCDCC2 2 #define LCDCC3 3 #if defined(__AVR_ATmega329P__) #define LCDMDT 4 #endif #define LCDDC0 5 #define LCDDC1 6 #define LCDDC2 7 /* Reserved [0xE8..0xEB] */ #define LCDDR00 _SFR_MEM8(0XEC) #define SEG000 0 #define SEG001 1 #define SEG002 2 #define SEG003 3 #define SEG004 4 #define SEG005 5 #define SEG006 6 #define SEG007 7 #define LCDDR01 _SFR_MEM8(0XED) #define SEG008 0 #define SEG009 1 #define SEG010 2 #define SEG011 3 #define SEG012 4 #define SEG013 5 #define SEG014 6 #define SEG015 7 #define LCDDR02 _SFR_MEM8(0XEE) #define SEG016 0 #define SEG017 1 #define SEG018 2 #define SEG019 3 #define SEG020 4 #define SEG021 5 #define SEG022 6 #define SEG023 7 #define LCDDR03 _SFR_MEM8(0XEF) #define SEG024 0 /* Reserved [0xF0] */ #define LCDDR05 _SFR_MEM8(0XF1) #define SEG100 0 #define SEG101 1 #define SEG102 2 #define SEG103 3 #define SEG104 4 #define SEG105 5 #define SEG106 6 #define SEG107 7 #define LCDDR06 _SFR_MEM8(0XF2) #define SEG108 0 #define SEG109 1 #define SEG110 2 #define SEG111 3 #define SEG112 4 #define SEG113 5 #define SEG114 6 #define SEG115 7 #define LCDDR07 _SFR_MEM8(0XF3) #define SEG116 0 #define SEG117 1 #define SEG118 2 #define SEG119 3 #define SEG120 4 #define SEG121 5 #define SEG122 6 #define SEG123 7 #define LCDDR08 _SFR_MEM8(0XF4) #define SEG124 0 /* Reserved [0xF5] */ #define LCDDR10 _SFR_MEM8(0XF6) #define SEG200 0 #define SEG201 1 #define SEG202 2 #define SEG203 3 #define SEG204 4 #define SEG205 5 #define SEG206 6 #define SEG207 7 #define LCDDR11 _SFR_MEM8(0XF7) #define SEG208 0 #define SEG209 1 #define SEG210 2 #define SEG211 3 #define SEG212 4 #define SEG213 5 #define SEG214 6 #define SEG215 7 #define LCDDR12 _SFR_MEM8(0XF8) #define SEG216 0 #define SEG217 1 #define SEG218 2 #define SEG219 3 #define SEG220 4 #define SEG221 5 #define SEG222 6 #define SEG223 7 #define LCDDR13 _SFR_MEM8(0XF9) #define SEG224 0 /* Reserved [0xFA] */ #define LCDDR15 _SFR_MEM8(0XFB) #define SEG300 0 #define SEG301 1 #define SEG302 2 #define SEG303 3 #define SEG304 4 #define SEG305 5 #define SEG306 6 #define SEG307 7 #define LCDDR16 _SFR_MEM8(0XFC) #define SEG308 0 #define SEG309 1 #define SEG310 2 #define SEG311 3 #define SEG312 4 #define SEG313 5 #define SEG314 6 #define SEG315 7 #define LCDDR17 _SFR_MEM8(0XFD) #define SEG316 0 #define SEG217 1 #define SEG318 2 #define SEG319 3 #define SEG320 4 #define SEG321 5 #define SEG322 6 #define SEG323 7 #define LCDDR18 _SFR_MEM8(0XFE) #define SEG324 0 /* Reserved [0xFF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART0, Rx Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* LCD Start of Frame */ #define LCD_vect_num 22 #define LCD_vect _VECTOR(22) #define SIG_LCD _VECTOR(22) #define _VECTORS_SIZE 92 /* Constants */ #define SPM_PAGESIZE 128 #define RAMEND 0x8FF #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 4 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x03 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #pragma GCC poison SIG_LCD #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM329_H_ */ avr-libc-1.8.0.orig/include/avr/signature.h0000644000000000000000000000631411732702554015443 0ustar /* Copyright (c) 2009, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: signature.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/signature.h - Signature API */ #ifndef _AVR_SIGNATURE_H_ #define _AVR_SIGNATURE_H_ 1 /** \file */ /** \defgroup avr_signature : Signature Support \par Introduction The header file allows the user to automatically and easily include the device's signature data in a special section of the final linked ELF file. This value can then be used by programming software to compare the on-device signature with the signature recorded in the ELF file to look for a match before programming the device. \par API Usage Example Usage is very simple; just include the header file: \code #include \endcode This will declare a constant unsigned char array and it is initialized with the three signature bytes, MSB first, that are defined in the device I/O header file. This array is then placed in the .signature section in the resulting linked ELF file. The three signature bytes that are used to initialize the array are these defined macros in the device I/O header file, from MSB to LSB: SIGNATURE_2, SIGNATURE_1, SIGNATURE_0. This header file should only be included once in an application. */ #ifndef __ASSEMBLER__ #include #if defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) const unsigned char __signature[3] __attribute__((section (".signature"))) = { SIGNATURE_2, SIGNATURE_1, SIGNATURE_0 }; #endif /* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */ #endif /* __ASSEMBLER__ */ #endif /* _AVR_SIGNATURE_H_ */ avr-libc-1.8.0.orig/include/avr/iotn861.h0000644000000000000000000000616511732702554014656 0ustar /* Copyright (c) 2006, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn861.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iotn861.h - definitions for ATtiny861 */ #ifndef _AVR_IOTN861_H_ #define _AVR_IOTN861_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x60) #define RAMEND 0x25F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x0D #endif /* _AVR_IOTN861_H_ */ avr-libc-1.8.0.orig/include/avr/io90pwm81.h0000644000000000000000000005116211732702554015120 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io90pwm81.h 2206 2011-02-11 06:58:02Z aboyapati $ */ /* avr/io90pwm81.h - definitions for AT90PWM81 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io90pwm81.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_AT90PWM81_H_ #define _AVR_AT90PWM81_H_ 1 /* Registers and associated bit numbers. */ #define ACSR _SFR_IO8(0x00) #define AC1O 1 #define AC2O 2 #define AC3O 3 #define AC1IF 5 #define AC2IF 6 #define AC3IF 7 #define TIMSK1 _SFR_IO8(0x01) #define TOIE1 0 #define ICIE1 5 #define TIFR1 _SFR_IO8(0x02) #define TOV1 0 #define ICF1 5 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_IO8(0x07) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define ADSSEN 4 #define ADNCDIS 6 #define ADHSM 7 #define ADMUX _SFR_IO8(0x08) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define PIM0 _SFR_IO8(0x0F) #define PEOPE0 0 #define PEOEPE0 1 #define PEVE0A 3 #define PEVE0B 4 #define PIFR0 _SFR_IO8(0x10) #define PEOP0 0 #define PRN00 1 #define PRN01 2 #define PEV0A 3 #define PEV0B 4 #define POAC0A 6 #define POAC0B 7 #define PCNF0 _SFR_IO8(0x11) #define PCLKSEL0 1 #define POP0 2 #define PMODE00 3 #define PMODE01 4 #define PLOCK0 5 #define PALOCK0 6 #define PFIFTY0 7 #define PCTL0 _SFR_IO8(0x12) #define PRUN0 0 #define PCCYC0 1 #define PBFM00 2 #define PAOC0A 3 #define PAOC0B 4 #define PBFM01 5 #define PPRE00 6 #define PPRE01 7 #define PIM2 _SFR_IO8(0x13) #define PEOPE2 0 #define PEOEPE2 1 #define PEVE2A 3 #define PEVE2B 4 #define PSEIE2 5 #define PIFR2 _SFR_IO8(0x14) #define PEOP2 0 #define PRN20 1 #define PRN21 2 #define PEV2A 3 #define PEV2B 4 #define PSEI2 5 #define POAC2A 6 #define POAC2B 7 #define PCNF2 _SFR_IO8(0x15) #define POME2 0 #define PCLKSEL2 1 #define POP2 2 #define PMODE20 3 #define PMODE21 4 #define PLOCK2 5 #define PALOCK2 6 #define PFIFTY2 7 #define PCTL2 _SFR_IO8(0x16) #define PRUN2 0 #define PCCYC2 1 #define PARUN2 2 #define PAOC2A 3 #define PAOC2B 4 #define PBFM2 5 #define PPRE20 6 #define PPRE21 7 #define SPCR _SFR_IO8(0x17) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x18) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define GPIOR0 _SFR_IO8(0x19) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x1A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x1B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEPAGE 6 #define NVMBSY 7 #define EEDR _SFR_IO8(0x1D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARL0 0 #define EEARL1 1 #define EEARL2 2 #define EEARL3 3 #define EEARL4 4 #define EEARL5 5 #define EEARL6 6 #define EEARL7 7 #define EEARH _SFR_IO8(0x1F) #define EEAR8 0 #define EIFR _SFR_IO8(0x20) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define EIMSK _SFR_IO8(0x21) #define INT0 0 #define INT1 1 #define INT2 2 #define OCR0SB _SFR_IO16(0x22) #define OCR0SBL _SFR_IO8(0x22) #define OCR0SB_0 0 #define OCR0SB_1 1 #define OCR0SB_2 2 #define OCR0SB_3 3 #define OCR0SB_4 4 #define OCR0SB_5 5 #define OCR0SB_6 6 #define OCR0SB_7 7 #define OCR0SBH _SFR_IO8(0x23) #define OCR0SB_8 0 #define OCR0SB_9 1 #define OCR0SB_00 2 #define OCR0SB_01 3 #define OCR0RB _SFR_IO16(0x24) #define OCR0RBL _SFR_IO8(0x24) #define OCR0RB_0 0 #define OCR0RB_1 1 #define OCR0RB_2 2 #define OCR0RB_3 3 #define OCR0RB_4 4 #define OCR0RB_5 5 #define OCR0RB_6 6 #define OCR0RB_7 7 #define OCR0RBH _SFR_IO8(0x25) #define OCR0RB_8 0 #define OCR0RB_9 1 #define OCR0RB_00 2 #define OCR0RB_01 3 #define OCR0RB_02 4 #define OCR0RB_03 5 #define OCR0RB_04 6 #define OCR0RB_05 7 #define OCR2SB _SFR_IO16(0x26) #define OCR2SBL _SFR_IO8(0x26) #define OCR2SB_0 0 #define OCR2SB_1 1 #define OCR2SB_2 2 #define OCR2SB_3 3 #define OCR2SB_4 4 #define OCR2SB_5 5 #define OCR2SB_6 6 #define OCR2SB_7 7 #define OCR2SBH _SFR_IO8(0x27) #define OCR2SB_8 0 #define OCR2SB_9 1 #define OCR2SB_10 2 #define OCR2SB_11 3 #define OCR2RB _SFR_IO16(0x28) #define OCR2RBL _SFR_IO8(0x28) #define OCR2RB_0 0 #define OCR2RB_1 1 #define OCR2RB_2 2 #define OCR2RB_3 3 #define OCR2RB_4 4 #define OCR2RB_5 5 #define OCR2RB_6 6 #define OCR2RB_7 7 #define OCR2RBH _SFR_IO8(0x29) #define OCR2RB_8 0 #define OCR2RB_9 1 #define OCR2RB_10 2 #define OCR2RB_11 3 #define OCR2RB_12 4 #define OCR2RB_13 5 #define OCR2RB_14 6 #define OCR2RB_15 7 #define OCR0RA _SFR_IO16(0x2A) #define OCR0RAL _SFR_IO8(0x2A) #define OCR0RA_0 0 #define OCR0RA_1 1 #define OCR0RA_2 2 #define OCR0RA_3 3 #define OCR0RA_4 4 #define OCR0RA_5 5 #define OCR0RA_6 6 #define OCR0RA_7 7 #define OCR0RAH _SFR_IO8(0x2B) #define OCR0RA_8 0 #define OCR0RA_9 1 #define OCR0RA_00 2 #define OCR0RA_01 3 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x2C) #endif #define ADCW _SFR_IO16(0x2C) #define ADCL _SFR_IO8(0x2C) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x2D) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define OCR2RA _SFR_IO16(0x2E) #define OCR2RAL _SFR_IO8(0x2E) #define OCR2RA_0 0 #define OCR2RA_1 1 #define OCR2RA_2 2 #define OCR2RA_3 3 #define OCR2RA_4 4 #define OCR2RA_5 5 #define OCR2RA_6 6 #define OCR2RA_7 7 #define OCR2RAH _SFR_IO8(0x2F) #define OCR2RA_8 0 #define OCR2RA_9 1 #define OCR2RA_10 2 #define OCR2RA_11 3 #define DWDR _SFR_IO8(0x31) #define MSMCR _SFR_IO8(0x32) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define CKRC81 2 #define RSTDIS 3 #define PUD 4 #define SPDR _SFR_IO8(0x36) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define DAC _SFR_IO16(0x38) #define DACL _SFR_IO8(0x38) #define DACL0 0 #define DACL1 1 #define DACL2 2 #define DACL3 3 #define DACL4 4 #define DACL5 5 #define DACL6 6 #define DACL7 7 #define DACH _SFR_IO8(0x39) #define DACH0 0 #define DACH1 1 #define DACH2 2 #define DACH3 3 #define DACH4 4 #define DACH5 5 #define DACH6 6 #define DACH7 7 #define TCNT1 _SFR_IO16(0x3A) #define TCNT1L _SFR_IO8(0x3A) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_IO8(0x3B) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define OCR0SA _SFR_MEM16(0x60) #define OCR0SAL _SFR_MEM8(0x60) #define OCR0SA_0 0 #define OCR0SA_1 1 #define OCR0SA_2 2 #define OCR0SA_3 3 #define OCR0SA_4 4 #define OCR0SA_5 5 #define OCR0SA_6 6 #define OCR0SA_7 7 #define OCR0SAH _SFR_MEM8(0x61) #define OCR0SA_8 0 #define OCR0SA_9 1 #define OCR0SA_00 2 #define OCR0SA_01 3 #define PFRC0A _SFR_MEM8(0x62) #define PRFM0A0 0 #define PRFM0A1 1 #define PRFM0A2 2 #define PRFM0A3 3 #define PFLTE0A 4 #define PELEV0A 5 #define PISEL0A 6 #define PCAE0A 7 #define PFRC0B _SFR_MEM8(0x63) #define PRFM0B0 0 #define PRFM0B1 1 #define PRFM0B2 2 #define PRFM0B3 3 #define PFLTE0B 4 #define PELEV0B 5 #define PISEL0B 6 #define PCAE0B 7 #define OCR2SA _SFR_MEM16(0x64) #define OCR2SAL _SFR_MEM8(0x64) #define OCR2SA_0 0 #define OCR2SA_1 1 #define OCR2SA_2 2 #define OCR2SA_3 3 #define OCR2SA_4 4 #define OCR2SA_5 5 #define OCR2SA_6 6 #define OCR2SA_7 7 #define OCR2SAH _SFR_MEM8(0x65) #define OCR2SA_8 0 #define OCR2SA_9 1 #define OCR2SA_10 2 #define OCR2SA_11 3 #define PFRC2A _SFR_MEM8(0x66) #define PRFM2A0 0 #define PRFM2A1 1 #define PRFM2A2 2 #define PRFM2A3 3 #define PFLTE2A 4 #define PELEV2A 5 #define PISEL2A 6 #define PCAE2A 7 #define PFRC2B _SFR_MEM8(0x67) #define PRFM2B0 0 #define PRFM2B1 1 #define PRFM2B2 2 #define PRFM2B3 3 #define PFLTE2B 4 #define PELEV2B 5 #define PISEL2B 6 #define PCAE2B 7 #define PICR0 _SFR_MEM16(0x68) #define PICR0L _SFR_MEM8(0x68) #define PICR0_0 0 #define PICR0_1 1 #define PICR0_2 2 #define PICR0_3 3 #define PICR0_4 4 #define PICR0_5 5 #define PICR0_6 6 #define PICR0_7 7 #define PICR0H _SFR_MEM8(0x69) #define PICR0_8 0 #define PICR0_9 1 #define PICR0_10 2 #define PICR0_11 3 #define PCST0 7 #define PSOC0 _SFR_MEM8(0x6A) #define POEN0A 0 #define POEN0B 2 #define PSYNC00 4 #define PSYNC01 5 #define PISEL0B1 6 #define PISEL0A1 7 #define PICR2 _SFR_MEM16(0x6C) #define PICR2L _SFR_MEM8(0x6C) #define PICR2_0 0 #define PICR2_1 1 #define PICR2_2 2 #define PICR2_3 3 #define PICR2_4 4 #define PICR2_5 5 #define PICR2_6 6 #define PICR2_7 7 #define PICR2H _SFR_MEM8(0x6D) #define PICR2_8 0 #define PICR2_9 1 #define PICR2_10 2 #define PICR2_11 3 #define PCST2 7 #define PSOC2 _SFR_MEM8(0x6E) #define POEN2A 0 #define POEN2C 1 #define POEN2B 2 #define POEN2D 3 #define PSYNC2_0 4 #define PSYNC2_1 5 #define POS22 6 #define POS23 7 #define POM2 _SFR_MEM8(0x6F) #define POMV2A0 0 #define POMV2A1 1 #define POMV2A2 2 #define POMV2A3 3 #define POMV2B0 4 #define POMV2B1 5 #define POMV2B2 6 #define POMV2B3 7 #define PCNFE2 _SFR_MEM8(0x70) #define PISEL2B1 0 #define PISEL2A1 1 #define PELEV2B1 2 #define PELEV2A1 3 #define PBFM21 4 #define PASDLK20 5 #define PASDLK21 6 #define PASDLK22 7 #define PASDLY2 _SFR_MEM8(0x71) #define PASDLY2_0 0 #define PASDLY2_1 1 #define PASDLY2_2 2 #define PASDLY2_3 3 #define PASDLY2_4 4 #define PASDLY2_5 5 #define PASDLY2_6 6 #define PASDLY2_7 7 #define DACON _SFR_MEM8(0x76) #define DAEN 0 #define DALA 2 #define DATS0 4 #define DATS1 5 #define DATS2 6 #define DAATE 7 #define DIDR0 _SFR_MEM8(0x77) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC7D 6 #define ADC8D 7 #define DIDR1 _SFR_MEM8(0x78) #define ADC9D 0 #define ADC10D 1 #define AMP0PD 2 #define ACMP1MD 3 #define AMP0CSR _SFR_MEM8(0x79) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0GS 3 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 #define AC1ECON _SFR_MEM8(0x7A) #define AC1H0 0 #define AC1H1 1 #define AC1H2 2 #define AC1ICE 3 #define AC1OE 4 #define AC1OI 5 #define AC2ECON _SFR_MEM8(0x7B) #define AC2H0 0 #define AC2H1 1 #define AC2H2 2 #define AC2OE 4 #define AC2OI 5 #define AC3ECON _SFR_MEM8(0x7C) #define AC3H0 0 #define AC3H1 1 #define AC3H2 2 #define AC3OE 4 #define AC3OI 5 #define AC1CON _SFR_MEM8(0x7D) #define AC1M0 0 #define AC1M1 1 #define AC1M2 2 #define AC1IS0 4 #define AC1IS1 5 #define AC1IE 6 #define AC1EN 7 #define AC2CON _SFR_MEM8(0x7E) #define AC2M0 0 #define AC2M1 1 #define AC2M2 2 #define AC2IS0 4 #define AC2IS1 5 #define AC2IE 6 #define AC2EN 7 #define AC3CON _SFR_MEM8(0x7F) #define AC3M0 0 #define AC3M1 1 #define AC3M2 2 #define AC3OEA 3 #define AC3IS0 4 #define AC3IS1 5 #define AC3IE 6 #define AC3EN 7 #define BGCRR _SFR_MEM8(0x80) #define BGCR0 0 #define BGCR1 1 #define BGCR2 2 #define BGCR3 3 #define BGCCR _SFR_MEM8(0x81) #define BGCC0 0 #define BGCC1 1 #define BGCC2 2 #define BGCC3 3 #define WDTCSR _SFR_MEM8(0x82) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x83) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define CLKCSR _SFR_MEM8(0x84) #define CLKC0 0 #define CLKC1 1 #define CLKC2 2 #define CLKC3 3 #define CLKRDY 4 #define CLKCCE 7 #define CLKSELR _SFR_MEM8(0x85) #define CKSEL0 0 #define CKSEL1 1 #define CKSEL2 2 #define CKSEL3 3 #define CSUT0 4 #define CSUT1 5 #define COUT 6 #define PRR _SFR_MEM8(0x86) #define PRADC 0 #define PRSPI 2 #define PRTIM1 4 #define PRPSCR 5 #define PRPSC2 7 #define PLLCSR _SFR_MEM8(0x87) #define PLOCK 0 #define PLLE 1 #define PLLF0 2 #define PLLF1 3 #define PLLF2 4 #define PLLF3 5 #define OSCCAL _SFR_MEM8(0x88) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define EICRA _SFR_MEM8(0x89) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define TCCR1B _SFR_MEM8(0x8A) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define ICR1 _SFR_MEM16(0x8C) #define ICR1L _SFR_MEM8(0x8C) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x8D) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define PSC2_CAPT_vect_num 1 #define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ #define PSC2_EC_vect_num 2 #define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ #define PSC2_EEC_vect_num 3 #define PSC2_EEC_vect _VECTOR(3) /* PSC2 End Of Enhanced Cycle */ #define PSC0_CAPT_vect_num 4 #define PSC0_CAPT_vect _VECTOR(4) /* PSC0 Capture Event */ #define PSC0_EC_vect_num 5 #define PSC0_EC_vect _VECTOR(5) /* PSC0 End Cycle */ #define PSC0_EEC_vect_num 6 #define PSC0_EEC_vect _VECTOR(6) /* PSC0 End Of Enhanced Cycle */ #define ANALOG_COMP_1_vect_num 7 #define ANALOG_COMP_1_vect _VECTOR(7) /* Analog Comparator 1 */ #define ANALOG_COMP_2_vect_num 8 #define ANALOG_COMP_2_vect _VECTOR(8) /* Analog Comparator 2 */ #define ANALOG_COMP_3_vect_num 9 #define ANALOG_COMP_3_vect _VECTOR(9) /* Analog Comparator 3 */ #define INT0_vect_num 10 #define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_OVF_vect_num 12 #define TIMER1_OVF_vect _VECTOR(12) /* Timer/Counter1 Overflow */ #define ADC_vect_num 13 #define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ #define INT1_vect_num 14 #define INT1_vect _VECTOR(14) /* External Interrupt Request 1 */ #define SPI_STC_vect_num 15 #define SPI_STC_vect _VECTOR(15) /* SPI Serial Transfer Complet */ #define INT2_vect_num 16 #define INT2_vect _VECTOR(16) /* External Interrupt Request 2 */ #define WDT_vect_num 17 #define WDT_vect _VECTOR(17) /* Watchdog Timeout Interrupt */ #define EE_READY_vect_num 18 #define EE_READY_vect _VECTOR(18) /* EEPROM Ready */ #define SPM_READY_vect_num 19 #define SPM_READY_vect _VECTOR(19) /* Store Program Memory Read */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (20 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x0100) #define RAMSIZE (256) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x1FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ #define FUSE_PSCINRB (unsigned char)~_BV(3) /* PSC2 & PSC0 Input Reset Behavior */ #define FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ #define FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ #define FUSE_PSC2RBA (unsigned char)~_BV(6) /* PSC2 Rest Behavior for out OUT22 & 23 */ #define FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x88 #endif /* _AVR_AT90PWM81_H_ */ avr-libc-1.8.0.orig/include/avr/io90pwm1.h0000644000000000000000000010273711732702554015035 0ustar /* Copyright (c) 2005, Andrey Pashchenko Copyright (c) 2007, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io90pwm1.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iopwm1.h - definitions for AT90PWM1 device */ #ifndef _AVR_IOPWM1_H_ #define _AVR_IOPWM1_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iopwm1.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Reserved [0x00..0x02] */ /* Port B Input Pins Address */ #define PINB _SFR_IO8(0x03) /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Port B Data Direction Register */ #define DDRB _SFR_IO8(0x04) /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Port B Data Register */ #define PORTB _SFR_IO8(0x05) /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Reserved [0x06..0x08] */ /* Port D Input Pins Address */ #define PIND _SFR_IO8(0x09) /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* Port D Data Direction Register */ #define DDRD _SFR_IO8(0x0A) /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Port D Data Register */ #define PORTD _SFR_IO8(0x0B) /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Port E Input Pins Address */ #define PINE _SFR_IO8(0x0C) /* PINE */ #define PINE2 2 #define PINE1 1 #define PINE0 0 /* Port E Data Direction Register */ #define DDRE _SFR_IO8(0x0D) /* DDRE */ #define DDE2 2 #define DDE1 1 #define DDE0 0 /* Port E Data Register */ #define PORTE _SFR_IO8(0x0E) /* PORTE */ #define PE2 2 #define PE1 1 #define PE0 0 /* Reserved [0x0F..0x14] */ /* Timer/Counter 0 Interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) /* TIFR0 */ #define OCF0B 2 /* Output Compare Flag 0B */ #define OCF0A 1 /* Output Compare Flag 0A */ #define TOV0 0 /* Overflow Flag */ /* Timer/Counter1 Interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) /* TIFR1 */ #define ICF1 5 /* Input Capture Flag 1 */ #define OCF1B 2 /* Output Compare Flag 1B*/ #define OCF1A 1 /* Output Compare Flag 1A*/ #define TOV1 0 /* Overflow Flag */ /* Reserved [0x17..0x18] */ /* General Purpose I/O Register 1 */ #define GPIOR1 _SFR_IO8(0x19) /* GPIOR1 */ #define GPIOR17 7 #define GPIOR16 6 #define GPIOR15 5 #define GPIOR14 4 #define GPIOR13 3 #define GPIOR12 2 #define GPIOR11 1 #define GPIOR10 0 /* General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x1A) /* GPIOR2 */ #define GPIOR27 7 #define GPIOR26 6 #define GPIOR25 5 #define GPIOR24 4 #define GPIOR23 3 #define GPIOR22 2 #define GPIOR21 1 #define GPIOR20 0 /* General Purpose I/O Register 3 */ #define GPIOR3 _SFR_IO8(0x1B) /* GPIOR3 */ #define GPIOR37 7 #define GPIOR36 6 #define GPIOR35 5 #define GPIOR34 4 #define GPIOR33 3 #define GPIOR32 2 #define GPIOR31 1 #define GPIOR30 0 /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) /* EIFR */ #define INTF3 3 #define INTF2 2 #define INTF1 1 #define INTF0 0 /* External Interrupt Mask Register */ #define EIMSK _SFR_IO8(0x1D) /* EIMSK */ #define INT3 3 /* External Interrupt Request 3 Enable */ #define INT2 2 /* External Interrupt Request 2 Enable */ #define INT1 1 /* External Interrupt Request 1 Enable */ #define INT0 0 /* External Interrupt Request 0 Enable */ /* General Purpose I/O Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) /* GPIOR0 */ #define GPIOR07 7 #define GPIOR06 6 #define GPIOR05 5 #define GPIOR04 4 #define GPIOR03 3 #define GPIOR02 2 #define GPIOR01 1 #define GPIOR00 0 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1F) /* EECR */ #define EERIE 3 /* EEPROM Ready Interrupt Enable */ #define EEMWE 2 /* EEPROM Master Write Enable */ #define EEWE 1 /* EEPROM Write Enable */ #define EERE 0 /* EEPROM Read Enable */ /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x20) /* EEDR */ #define EEDR7 7 #define EEDR6 6 #define EEDR5 5 #define EEDR4 4 #define EEDR3 3 #define EEDR2 2 #define EEDR1 1 #define EEDR0 0 /* The EEPROM Address Registers */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0x22) /* EEARH */ #define EEAR11 3 #define EEAR10 2 #define EEAR9 1 #define EEAR8 0 /* EEARL */ #define EEAR7 7 #define EEAR6 6 #define EEAR5 5 #define EEAR4 4 #define EEAR3 3 #define EEAR2 2 #define EEAR1 1 #define EEAR0 0 /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) /* GTCCR */ #define TSM 7 /* Timer/Counter Synchronization Mode */ #define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ #define PSRSYNC 0 /* Timer/Counter Control Register A */ #define TCCR0A _SFR_IO8(0x24) /* TCCR0A */ #define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ #define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ #define COM0B1 5 /* Compare Output Mode, Fast PWm */ #define COM0B0 4 /* Compare Output Mode, Fast PWm */ #define WGM01 1 /* Waveform Generation Mode */ #define WGM00 0 /* Waveform Generation Mode */ /* Timer/Counter Control Register B */ #define TCCR0B _SFR_IO8(0x25) /* TCCR0B */ #define FOC0A 7 /* Force Output Compare A */ #define FOC0B 6 /* Force Output Compare B */ #define WGM02 3 /* Waveform Generation Mode */ #define CS02 2 /* Clock Select */ #define CS01 1 /* Clock Select */ #define CS00 0 /* Clock Select */ /* Timer/Counter0 Register */ #define TCNT0 _SFR_IO8(0x26) /* TCNT0 */ #define TCNT07 7 #define TCNT06 6 #define TCNT05 5 #define TCNT04 4 #define TCNT03 3 #define TCNT02 2 #define TCNT01 1 #define TCNT00 0 /* Timer/Counter0 Output Compare Register A */ #define OCR0A _SFR_IO8(0x27) /* OCR0A */ #define OCR0A7 7 #define OCR0A6 6 #define OCR0A5 5 #define OCR0A4 4 #define OCR0A3 3 #define OCR0A2 2 #define OCR0A1 1 #define OCR0A0 0 /* Timer/Counter0 Output Compare Register B */ #define OCR0B _SFR_IO8(0x28) /* OCR0B */ #define OCR0B7 7 #define OCR0B6 6 #define OCR0B5 5 #define OCR0B4 4 #define OCR0B3 3 #define OCR0B2 2 #define OCR0B1 1 #define OCR0B0 0 /* PLL Control and Status Register */ #define PLLCSR _SFR_IO8(0x29) /* PLLCSR */ #define PLLF 2 #define PLLE 1 /* PLL Enable */ #define PLOCK 0 /* PLL Lock Detector */ /* Reserved [0x2A..0x2B] */ /* SPI Control Register */ #define SPCR _SFR_IO8(0x2C) /* SPCR */ #define SPIE 7 /* SPI Interrupt Enable */ #define SPE 6 /* SPI Enable */ #define DORD 5 /* Data Order */ #define MSTR 4 /* Master/Slave Select */ #define CPOL 3 /* Clock polarity */ #define CPHA 2 /* Clock Phase */ #define SPR1 1 /* SPI Clock Rate Select 1 */ #define SPR0 0 /* SPI Clock Rate Select 0 */ /* SPI Status Register */ #define SPSR _SFR_IO8(0x2D) /* SPSR */ #define SPIF 7 /* SPI Interrupt Flag */ #define WCOL 6 /* Write Collision Flag */ #define SPI2X 0 /* Double SPI Speed Bit */ /* SPI Data Register */ #define SPDR _SFR_IO8(0x2E) /* SPDR */ #define SPD7 7 #define SPD6 6 #define SPD5 5 #define SPD4 4 #define SPD3 3 #define SPD2 2 #define SPD1 1 #define SPD0 0 /* Reserved [0x2F] */ /* Analog Comparator Status Register */ #define ACSR _SFR_IO8(0x30) /* ACSR */ #define ACCKDIV 7 /* Analog Comparator Clock Divider */ #define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ #define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ #define AC2O 2 /* Analog Comparator 2 Output Bit */ #define AC0O 0 /* Analog Comparator 0 Output Bit */ /* Monitor Data Register */ #define MONDR _SFR_IO8(0x31) /* Monitor Stop Mode Control Register */ #define MSMCR _SFR_IO8(0x32) /* Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) /* SMCR */ #define SM2 3 /* Sleep Mode Select bit2 */ #define SM1 2 /* Sleep Mode Select bit1 */ #define SM0 1 /* Sleep Mode Select bit0 */ #define SE 0 /* Sleep Enable */ /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCUSR */ #define WDRF 3 /* Watchdog Reset Flag */ #define BORF 2 /* Brown-out Reset Flag */ #define EXTRF 1 /* External Reset Flag */ #define PORF 0 /* Power-on reset flag */ /* MCU Control Register */ #define MCUCR _SFR_IO8(0x35) /* MCUCR */ #define SPIPS 7 /* SPI Pin Select */ #define PUD 4 /* Pull-up disable */ #define IVSEL 1 /* Interrupt Vector Select */ #define IVCE 0 /* Interrupt Vector Change Enable */ /* Reserved [0x36] */ /* Store Program Memory Control Register */ #define SPMCSR _SFR_IO8(0x37) /* SPMCSR */ #define SPMIE 7 /* SPM Interrupt Enable */ #define RWWSB 6 /* Read While Write Section Busy */ #define RWWSRE 4 /* Read While Write section read enable */ #define BLBSET 3 /* Boot Lock Bit Set */ #define PGWRT 2 /* Page Write */ #define PGERS 1 /* Page Erase */ #define SPMEN 0 /* Store Program Memory Enable */ /* Reserved [0x38..0x3C] */ /* 0x3D..0x3E SP [defined in ] */ /* 0x3F SREG [defined in ] */ /* Watchdog Timer Control Register */ #define WDTCSR _SFR_MEM8(0x60) /* WDTCSR */ #define WDIF 7 /* Watchdog Timeout Interrupt Flag */ #define WDIE 6 /* Watchdog Timeout Interrupt Enable */ #define WDP3 5 /* Watchdog Timer Prescaler bit3 */ #define WDCE 4 /* Watchdog Change Enable */ #define WDE 3 /* Watchdog Enable */ #define WDP2 2 /* Watchdog Timer Prescaler bit2 */ #define WDP1 1 /* Watchdog Timer Prescaler bit1 */ #define WDP0 0 /* Watchdog Timer Prescaler bit0 */ /* Clock Prescaler Register */ #define CLKPR _SFR_MEM8(0x61) /* CLKPR */ #define CLKPCE 7 /* Clock Prescaler Change Enable */ #define CLKPS3 3 /* Clock Prescaler Select bit3 */ #define CLKPS2 2 /* Clock Prescaler Select bit2 */ #define CLKPS1 1 /* Clock Prescaler Select bit1 */ #define CLKPS0 0 /* Clock Prescaler Select bit0 */ /* Reserved [0x62..0x63] */ /* Power Reduction Register */ #define PRR _SFR_MEM8(0x64) /* PRR */ #define PRPSC2 7 /* Power Reduction PSC2 */ #define PRPSC1 6 /* Power Reduction PSC1 */ #define PRPSC0 5 /* Power Reduction PSC0 */ #define PRTIM1 4 /* Power Reduction Timer/Counter1 */ #define PRTIM0 3 /* Power Reduction Timer/Counter0 */ #define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ #define PRADC 0 /* Power Reduction ADC */ /* Reserved [0x65] */ /* Oscillator Calibration Value */ #define OSCCAL _SFR_MEM8(0x66) /* OSCCAL */ #define CAL6 6 #define CAL5 5 #define CAL4 4 #define CAL3 3 #define CAL2 2 #define CAL1 1 #define CAL0 0 /* Reserved [0x67..0x68] */ /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x69) /* EICRA */ #define ISC31 7 #define ISC30 6 #define ISC21 5 #define ISC20 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* Reserved [0x6A..0x6D] */ /* Timer/Counter0 Interrupt Mask Register */ #define TIMSK0 _SFR_MEM8(0x6E) /* TIMSK0 */ #define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ #define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ #define TOIE0 0 /* Overflow Interrupt Enable */ /* Timer/Counter1 Interrupt Mask Register */ #define TIMSK1 _SFR_MEM8(0x6F) /* TIMSK1 */ #define ICIE1 5 /* Input Capture Interrupt Enable */ #define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ #define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ #define TOIE1 0 /* Overflow Interrupt Enable */ /* Reserved [0x70..0x75] */ /* Amplifier 0 Control and Status register */ #define AMP0CSR _SFR_MEM8(0x76) #define AMP0EN 7 #define AMP0IS 6 #define AMP0G1 5 #define AMP0G0 4 #define AMP0TS1 1 #define AMP0TS0 0 /* Reserved [0x77] */ /* ADC Result Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) /* ADC Control and Status Register A */ #define ADCSRA _SFR_MEM8(0x7A) /* ADCSRA */ #define ADEN 7 /* ADC Enable */ #define ADSC 6 /* ADC Start Conversion */ #define ADATE 5 /* ADC Auto Trigger Enable */ #define ADIF 4 /* ADC Interrupt Flag */ #define ADIE 3 /* ADC Interrupt Enable */ #define ADPS2 2 /* ADC Prescaler Select bit2 */ #define ADPS1 1 /* ADC Prescaler Select bit1 */ #define ADPS0 0 /* ADC Prescaler Select bit0 */ /* ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x7B) /* ADCSRB */ #define ADTS3 3 /* ADC Auto Trigger Source 2 */ #define ADTS2 2 /* ADC Auto Trigger Source 2 */ #define ADTS1 1 /* ADC Auto Trigger Source 1 */ #define ADTS0 0 /* ADC Auto Trigger Source 0 */ /* ADC multiplexer Selection Register */ #define ADMUX _SFR_MEM8(0x7C) /* ADMUX */ #define REFS1 7 /* Reference Selection bit1 */ #define REFS0 6 /* Reference Selection bit0 */ #define ADLAR 5 /* Left Adjust Result */ #define MUX3 3 /* Analog Channel and Gain Selection bit3 */ #define MUX2 2 /* Analog Channel and Gain Selection bit2 */ #define MUX1 1 /* Analog Channel and Gain Selection bit1 */ #define MUX0 0 /* Analog Channel and Gain Selection bit0 */ /* Reserved [0x7D] */ /* Digital Input Disable Register 0 */ #define DIDR0 _SFR_MEM8(0x7E) /* DIDR0 */ #define ADC7D 7 /* ADC7 Digital input Disable */ #define ADC6D 6 /* ADC6 Digital input Disable */ #define ADC5D 5 /* ADC5 Digital input Disable */ #define ADC4D 4 /* ADC4 Digital input Disable */ #define ADC3D 3 /* ADC3 Digital input Disable */ #define ADC2D 2 /* ADC2 Digital input Disable */ #define ADC1D 1 /* ADC1 Digital input Disable */ #define ADC0D 0 /* ADC0 Digital input Disable */ /* Digital Input Disable Register 1 */ #define DIDR1 _SFR_MEM8(0x7F) /* DIDR1 */ #define ACMP0D 5 #define AMP0PD 4 #define AMP0ND 3 #define ADC10D 2 /* ADC10 Digital input Disable */ #define ADC9D 1 /* ADC9 Digital input Disable */ #define ADC8D 0 /* ADC8 Digital input Disable */ /* Timer/Counter1 Control Register A */ #define TCCR1A _SFR_MEM8(0x80) /* TCCR1A */ #define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ #define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ #define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ #define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ #define WGM11 1 /* Waveform Generation Mode */ #define WGM10 0 /* Waveform Generation Mode */ /* Timer/Counter1 Control Register B */ #define TCCR1B _SFR_MEM8(0x81) /* TCCR1B */ #define ICNC1 7 /* Input Capture 1 Noise Canceler */ #define ICES1 6 /* Input Capture 1 Edge Select */ #define WGM13 4 /* Waveform Generation Mode */ #define WGM12 3 /* Waveform Generation Mode */ #define CS12 2 /* Prescaler source of Timer/Counter 1 */ #define CS11 1 /* Prescaler source of Timer/Counter 1 */ #define CS10 0 /* Prescaler source of Timer/Counter 1 */ /* Timer/Counter1 Control Register C */ #define TCCR1C _SFR_MEM8(0x82) /* TCCR1C */ #define FOC1A 7 /* Force Output Compare for Channel A */ #define FOC1B 6 /* Force Output Compare for Channel B */ /* Reserved [0x83] */ /* Timer/Counter1 */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* TCNT1H */ #define TCNT115 7 #define TCNT114 6 #define TCNT113 5 #define TCNT112 4 #define TCNT111 3 #define TCNT110 2 #define TCNT19 1 #define TCNT18 0 /* TCNT1L */ #define TCNT17 7 #define TCNT16 6 #define TCNT15 5 #define TCNT14 4 #define TCNT13 3 #define TCNT12 2 #define TCNT11 1 #define TCNT10 0 /* Input Capture Register 1 */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* ICR1H */ #define ICR115 7 #define ICR114 6 #define ICR113 5 #define ICR112 4 #define ICR111 3 #define ICR110 2 #define ICR19 1 #define ICR18 0 /* ICR1L */ #define ICR17 7 #define ICR16 6 #define ICR15 5 #define ICR14 4 #define ICR13 3 #define ICR12 2 #define ICR11 1 #define ICR10 0 /* Output Compare Register 1 A */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* OCR1AH */ #define OCR1A15 7 #define OCR1A14 6 #define OCR1A13 5 #define OCR1A12 4 #define OCR1A11 3 #define OCR1A10 2 #define OCR1A9 1 #define OCR1A8 0 /* OCR1AL */ #define OCR1A7 7 #define OCR1A6 6 #define OCR1A5 5 #define OCR1A4 4 #define OCR1A3 3 #define OCR1A2 2 #define OCR1A1 1 #define OCR1A0 0 /* Output Compare Register 1 B */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* OCR1BH */ #define OCR1B15 7 #define OCR1B14 6 #define OCR1B13 5 #define OCR1B12 4 #define OCR1B11 3 #define OCR1B10 2 #define OCR1B9 1 #define OCR1B8 0 /* OCR1BL */ #define OCR1B7 7 #define OCR1B6 6 #define OCR1B5 5 #define OCR1B4 4 #define OCR1B3 3 #define OCR1B2 2 #define OCR1B1 1 #define OCR1B0 0 /* Reserved [0x8C..0x9F] */ /* PSC0 Interrupt Flag Register */ #define PIFR0 _SFR_MEM8(0xA0) /* PIFR0 */ #define PSEI0 5 /* PSC0 Synchro Error Interrupt */ #define PEV0B 4 /* PSC0 External Event B Interrupt */ #define PEV0A 3 /* PSC0 External Event A Interrupt */ #define PRN01 2 /* PSC0 Ramp Number bit1 */ #define PRN00 1 /* PSC0 Ramp Number bit0 */ #define PEOP0 0 /* End Of PSC0 Interrupt */ /* PSC0 Interrupt Mask Register */ #define PIM0 _SFR_MEM8(0xA1) /* PIM0 */ #define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ #define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ #define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ #define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ /* Reserved [0xA2..0xA3] */ /* PSC2 Interrupt Flag Register */ #define PIFR2 _SFR_MEM8(0xA4) /* PIFR2 */ #define PSEI2 5 /* PSC2 Synchro Error Interrupt */ #define PEV2B 4 /* PSC2 External Event B Interrupt */ #define PEV2A 3 /* PSC2 External Event A Interrupt */ #define PRN21 2 /* PSC2 Ramp Number bit1 */ #define PRN20 1 /* PSC2 Ramp Number bit0 */ #define PEOP2 0 /* End Of PSC2 Interrupt */ /* PSC2 Interrupt Mask Register */ #define PIM2 _SFR_MEM8(0xA5) /* PIM2 */ #define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ #define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ #define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ #define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ /* Reserved [0xA6..0xAC] */ /* Analog Comparator 0 Control Register */ #define AC0CON _SFR_MEM8(0xAD) /* AC0CON */ #define AC0EN 7 /* Analog Comparator 0 Enable Bit */ #define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ #define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ #define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ #define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ #define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ #define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ /* Reserved [0xB0..0xAE] */ /* Analog Comparator 2 Control Register */ #define AC2CON _SFR_MEM8(0xAF) /* AC2CON */ #define AC2EN 7 /* Analog Comparator 2 Enable Bit */ #define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ #define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ #define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ #define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ #define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ #define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ /* Reserved [0xB0..0xCF] */ /* PSC 0 Synchro and Output Configuration */ #define PSOC0 _SFR_MEM8(0xD0) /* PSOC0 */ #define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ #define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ #define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ #define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ /* Reserved [0xD1] */ /* Output Compare SA Registers */ #define OCR0SA _SFR_MEM16(0xD2) #define OCR0SAL _SFR_MEM8(0xD2) #define OCR0SAH _SFR_MEM8(0xD3) /* Output Compare RA Registers */ #define OCR0RA _SFR_MEM16(0xD4) #define OCR0RAL _SFR_MEM8(0xD4) #define OCR0RAH _SFR_MEM8(0xD5) /* Output Compare SB Registers */ #define OCR0SB _SFR_MEM16(0xD6) #define OCR0SBL _SFR_MEM8(0xD6) #define OCR0SBH _SFR_MEM8(0xD7) /* Output Compare RB Registers */ #define OCR0RB _SFR_MEM16(0xD8) #define OCR0RBL _SFR_MEM8(0xD8) #define OCR0RBH _SFR_MEM8(0xD9) /* PSC 0 Configuration Register */ #define PCNF0 _SFR_MEM8(0xDA) /* PCNF0 */ #define PFIFTY0 7 /* PSC 0 Fifty */ #define PALOCK0 6 /* PSC 0 Autolock */ #define PLOCK0 5 /* PSC 0 Lock */ #define PMODE01 4 /* PSC 0 Mode bit1 */ #define PMODE00 3 /* PSC 0 Mode bit0 */ #define POP0 2 /* PSC 0 Output Polarity */ #define PCLKSEL0 1 /* PSC 0 Input Clock Select */ /* PSC 0 Control Register */ #define PCTL0 _SFR_MEM8(0xDB) /* PCTL0 */ #define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ #define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ #define PBFM0 5 /* Balance Flank Width Modulation */ #define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ #define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ #define PARUN0 2 /* PSC 0 Autorun */ #define PCCYC0 1 /* PSC 0 Complete Cycle */ #define PRUN0 0 /* PSC 0 Run */ /* PSC 0 Input A Control Register */ #define PFRC0A _SFR_MEM8(0xDC) /* PFRC0A */ #define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ #define PISEL0A 6 /* PSC 0 Input Select for Part A */ #define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ #define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ #define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ #define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ #define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ #define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ /* PSC 0 Input B Control Register */ #define PFRC0B _SFR_MEM8(0xDD) /* PFRC0B */ #define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ #define PISEL0B 6 /* PSC 0 Input Select for Part B */ #define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ #define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ #define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ #define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ #define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ #define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ /* PSC 0 Input Capture Registers */ #define PICR0 _SFR_MEM16(0xDE) #define PICR0L _SFR_MEM8(0xDE) #define PICR0H _SFR_MEM8(0xDF) #define PCST0 7 /* PSC Capture Software Trig bit */ /* Reserved [0xE0..0xEF] */ /* PSC 2 Synchro and Output Configuration */ #define PSOC2 _SFR_MEM8(0xF0) /* PSOC2 */ #define POS23 7 /* PSCOUT23 Selection */ #define POS22 6 /* PSCOUT22 Selection */ #define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ #define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ #define POEN2D 3 /* PSCOUT23 Output Enable */ #define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ #define POEN2C 1 /* PSCOUT22 Output Enable */ #define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ /* PSC 2 Output Matrix */ #define POM2 _SFR_MEM8(0xF1) /* POM2 */ #define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ #define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ #define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ #define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ #define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ #define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ #define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ #define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ /* Output Compare SA Registers */ #define OCR2SA _SFR_MEM16(0xF2) #define OCR2SAL _SFR_MEM8(0xF2) #define OCR2SAH _SFR_MEM8(0xF3) /* Output Compare RA Registers */ #define OCR2RA _SFR_MEM16(0xF4) #define OCR2RAL _SFR_MEM8(0xF4) #define OCR2RAH _SFR_MEM8(0xF5) /* Output Compare SB Registers */ #define OCR2SB _SFR_MEM16(0xF6) #define OCR2SBL _SFR_MEM8(0xF6) #define OCR2SBH _SFR_MEM8(0xF7) /* Output Compare RB Registers */ #define OCR2RB _SFR_MEM16(0xF8) #define OCR2RBL _SFR_MEM8(0xF8) #define OCR2RBH _SFR_MEM8(0xF9) /* PSC 2 Configuration Register */ #define PCNF2 _SFR_MEM8(0xFA) /* PCNF2 */ #define PFIFTY2 7 /* PSC 2 Fifty */ #define PALOCK2 6 /* PSC 2 Autolock */ #define PLOCK2 5 /* PSC 2 Lock */ #define PMODE21 4 /* PSC 2 Mode bit1 */ #define PMODE20 3 /* PSC 2 Mode bit0 */ #define POP2 2 /* PSC 2 Output Polarity */ #define PCLKSEL2 1 /* PSC 2 Input Clock Select */ #define POME2 0 /* PSC 2 Output Matrix Enable */ /* PSC 2 Control Register */ #define PCTL2 _SFR_MEM8(0xFB) /* PCTL2 */ #define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ #define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ #define PBFM2 5 /* Balance Flank Width Modulation */ #define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ #define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ #define PARUN2 2 /* PSC 2 Autorun */ #define PCCYC2 1 /* PSC 2 Complete Cycle */ #define PRUN2 0 /* PSC 2 Run */ /* PSC 2 Input A Control Register */ #define PFRC2A _SFR_MEM8(0xFC) /* PFRC2A */ #define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ #define PISEL2A 6 /* PSC 2 Input Select for Part A */ #define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ #define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ #define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ #define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ #define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ #define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ /* PSC 2 Input B Control Register */ #define PFRC2B _SFR_MEM8(0xFD) /* PFRC2B */ #define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ #define PISEL2B 6 /* PSC 2 Input Select for Part B */ #define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ #define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ #define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ #define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ #define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ #define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ /* PSC 2 Input Capture Registers */ #define PICR2 _SFR_MEM16(0xFE) #define PICR2L _SFR_MEM8(0xFE) #define PICR2H _SFR_MEM8(0xFF) #define PCST2 7 /* PSC Capture Software Trig bit */ /* not implemented on AT90PWM2/AT90PWM3 */ /* Interrupt vectors */ /* PSC2 Capture Event */ #define PSC2_CAPT_vect_num 1 #define PSC2_CAPT_vect _VECTOR(1) #define SIG_PSC2_CAPTURE _VECTOR(1) /* PSC2 End Cycle */ #define PSC2_EC_vect_num 2 #define PSC2_EC_vect _VECTOR(2) #define SIG_PSC2_END_CYCLE _VECTOR(2) /* PSC0 Capture Event */ #define PSC0_CAPT_vect_num 5 #define PSC0_CAPT_vect _VECTOR(5) #define SIG_PSC0_CAPTURE _VECTOR(5) /* PSC0 End Cycle */ #define PSC0_EC_vect_num 6 #define PSC0_EC_vect _VECTOR(6) #define SIG_PSC0_END_CYCLE _VECTOR(6) /* Analog Comparator 0 */ #define ANALOG_COMP_0_vect_num 7 #define ANALOG_COMP_0_vect _VECTOR(7) #define SIG_COMPARATOR0 _VECTOR(7) /* Analog Comparator 2 */ #define ANALOG_COMP_2_vect_num 9 #define ANALOG_COMP_2_vect _VECTOR(9) #define SIG_COMPARATOR2 _VECTOR(9) /* External Interrupt Request 0 */ #define INT0_vect_num 10 #define INT0_vect _VECTOR(10) #define SIG_INTERRUPT0 _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) #define SIG_INPUT_CAPTURE1 _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) #define SIG_OUTPUT_COMPARE1A _VECTOR(12) #define SIG_OUTPUT_COMPARE1_A _VECTOR(12) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) #define SIG_OUTPUT_COMPARE1B _VECTOR(13) #define SIG_OUTPUT_COMPARE1_B _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) #define SIG_OVERFLOW1 _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMP_A_vect_num 16 #define TIMER0_COMP_A_vect _VECTOR(16) #define SIG_OUTPUT_COMPARE0A _VECTOR(16) #define SIG_OUTPUT_COMPARE0_A _VECTOR(16) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) #define SIG_OVERFLOW0 _VECTOR(17) /* ADC Conversion Complete */ #define ADC_vect_num 18 #define ADC_vect _VECTOR(18) #define SIG_ADC _VECTOR(18) /* External Interrupt Request 1 */ #define INT1_vect_num 19 #define INT1_vect _VECTOR(19) #define SIG_INTERRUPT1 _VECTOR(19) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 20 #define SPI_STC_vect _VECTOR(20) #define SIG_SPI _VECTOR(20) /* External Interrupt Request 2 */ #define INT2_vect_num 24 #define INT2_vect _VECTOR(24) #define SIG_INTERRUPT2 _VECTOR(24) /* Watchdog Timeout Interrupt */ #define WDT_vect_num 25 #define WDT_vect _VECTOR(25) #define SIG_WDT _VECTOR(25) #define SIG_WATCHDOG_TIMEOUT _VECTOR(25) /* EEPROM Ready */ #define EE_READY_vect_num 26 #define EE_READY_vect _VECTOR(26) #define SIG_EEPROM_READY _VECTOR(26) /* Timer Counter 0 Compare Match B */ #define TIMER0_COMPB_vect_num 27 #define TIMER0_COMPB_vect _VECTOR(27) #define SIG_OUTPUT_COMPARE0B _VECTOR(27) #define SIG_OUTPUT_COMPARE0_B _VECTOR(27) /* External Interrupt Request 3 */ #define INT3_vect_num 28 #define INT3_vect _VECTOR(28) #define SIG_INTERRUPT3 _VECTOR(28) /* Store Program Memory Read */ #define SPM_READY_vect_num 31 #define SPM_READY_vect _VECTOR(31) #define SIG_SPM_READY _VECTOR(31) #define _VECTORS_SIZE 64 /* Constants */ #define SPM_PAGESIZE 64 #define RAMEND 0x02FF #define XRAMEND RAMEND #define E2END 0x01FF #define FLASHEND 0x0FFF /* Fuse Information */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_PSCRV (unsigned char)~_BV(4) #define FUSE_PSC0RB (unsigned char)~_BV(5) #define FUSE_PSC2RB (unsigned char)~_BV(7) #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST #endif /* _AVR_IOPWM1_H_ */ avr-libc-1.8.0.orig/include/avr/iocan32.h0000644000000000000000000000655111732702554014703 0ustar /* Copyright (c) 2004,2005, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iocan32.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* iocan32.h - definitions for CAN32 */ #ifndef _AVR_IOCAN32_H_ #define _AVR_IOCAN32_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x08FF /* Last On-Chip SRAM Location */ #define XRAMEND 0xFFFF #define E2END 0x03FF #define E2PAGESIZE 8 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x81 #endif /* _AVR_IOCAN32_H_ */ avr-libc-1.8.0.orig/include/avr/io2343.h0000644000000000000000000001173311732702554014366 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io2343.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io2343.h - definitions for AT90S2343 */ #ifndef _AVR_IO2343_H_ #define _AVR_IO2343_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io2343.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Timer/Counter0 Overflow */ #define TIMER0_OVF0_vect_num 2 #define TIMER0_OVF0_vect _VECTOR(2) #define SIG_OVERFLOW0 _VECTOR(2) #define _VECTORS_SIZE 6 /* The Register Bit names are represented by their bit number (0-7). */ /* General Interrupt MaSK register */ #define INT0 6 #define INTF0 6 /* General Interrupt Flag Register */ #define TOIE0 1 #define TOV0 1 /* MCU general Control Register */ #define SE 5 #define SM 4 #define ISC01 1 #define ISC00 0 /* MCU Status Register */ #define PORF 0 #define EXTRF 1 /* Timer/Counter 0 Control Register */ #define CS02 2 #define CS01 1 #define CS00 0 /* Watchdog Timer Control Register */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PB3 = CLOCK PB2 = SCK/T0 PB1 = MISO/INT0 PB0 = MOSI */ /* Data Register, Port B */ #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F #define E2PAGESIZE 0 #define FLASHEND 0x07FF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_RCEN (unsigned char)~_BV(0) #define FUSE_SPIEN (unsigned char)~_BV(5) #define LFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x03 #endif /* _AVR_IO2343_H_ */ avr-libc-1.8.0.orig/include/avr/iom64c1.h0000644000000000000000000006305511732702554014631 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom64c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ /* avr/iom64c1.h - definitions for ATmega64C1 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom64c1.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega64C1_H_ #define _AVR_ATmega64C1_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define GPIOR1 _SFR_IO8(0x19) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x1A) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define PCIF3 3 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSRSYNC 0 #define ICPSEL1 6 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLF 2 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define AC0O 0 #define AC1O 1 #define AC2O 2 #define AC3O 3 #define AC0IF 4 #define AC1IF 5 #define AC2IF 6 #define AC3IF 7 #define DWDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPIPS 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRLIN 1 #define PRSPI 2 #define PRTIM0 3 #define PRTIM1 4 #define PRPSC 5 #define PRCAN 6 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define PCIE3 3 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6A) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6B) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK2 _SFR_MEM8(0x6C) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define PCMSK3 _SFR_MEM8(0x6D) #define PCINT24 0 #define PCINT25 1 #define PCINT26 2 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define AMP0CSR _SFR_MEM8(0x75) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0TS2 2 #define AMPCMP0 3 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 #define AMP1CSR _SFR_MEM8(0x76) #define AMP1TS0 0 #define AMP1TS1 1 #define AMP1TS2 2 #define AMPCMP1 3 #define AMP1G0 4 #define AMP1G1 5 #define AMP1IS 6 #define AMP1EN 7 #define AMP2CSR _SFR_MEM8(0x77) #define AMP2TS0 0 #define AMP2TS1 1 #define AMP2TS2 2 #define AMPCMP2 3 #define AMP2G0 4 #define AMP2G1 5 #define AMP2IS 6 #define AMP2EN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define AREFEN 5 #define ISRCEN 6 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define AMP0ND 3 #define AMP0PD 4 #define ACMP0D 5 #define AMP2PD 6 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define DACON _SFR_MEM8(0x90) #define DAEN 0 #define DAOE 1 #define DALA 2 #define DATS0 4 #define DATS1 5 #define DATS2 6 #define DAATE 7 #define DAC _SFR_MEM16(0x91) #define DACL _SFR_MEM8(0x91) #define DACL0 0 #define DACL1 1 #define DACL2 2 #define DACL3 3 #define DACL4 4 #define DACL5 5 #define DACL6 6 #define DACL7 7 #define DACH _SFR_MEM8(0x92) #define DACH0 0 #define DACH1 1 #define DACH2 2 #define DACH3 3 #define DACH4 4 #define DACH5 5 #define DACH6 6 #define DACH7 7 #define AC0CON _SFR_MEM8(0x94) #define AC0M0 0 #define AC0M1 1 #define AC0M2 2 #define ACCKSEL 3 #define AC0IS0 4 #define AC0IS1 5 #define AC0IE 6 #define AC0EN 7 #define AC1CON _SFR_MEM8(0x95) #define AC1M0 0 #define AC1M1 1 #define AC1M2 2 #define AC1ICE 3 #define AC1IS0 4 #define AC1IS1 5 #define AC1IE 6 #define AC1EN 7 #define AC2CON _SFR_MEM8(0x96) #define AC2M0 0 #define AC2M1 1 #define AC2M2 2 #define AC2IS0 4 #define AC2IS1 5 #define AC2IE 6 #define AC2EN 7 #define AC3CON _SFR_MEM8(0x97) #define AC3M0 0 #define AC3M1 1 #define AC3M2 2 #define AC3IS0 4 #define AC3IS1 5 #define AC3IE 6 #define AC3EN 7 #define LINCR _SFR_MEM8(0xC8) #define LCMD0 0 #define LCMD1 1 #define LCMD2 2 #define LENA 3 #define LCONF0 4 #define LCONF1 5 #define LIN13 6 #define LSWRES 7 #define LINSIR _SFR_MEM8(0xC9) #define LRXOK 0 #define LTXOK 1 #define LIDOK 2 #define LERR 3 #define LBUSY 4 #define LIDST0 5 #define LIDST1 6 #define LIDST2 7 #define LINENIR _SFR_MEM8(0xCA) #define LENRXOK 0 #define LENTXOK 1 #define LENIDOK 2 #define LENERR 3 #define LINERR _SFR_MEM8(0xCB) #define LBERR 0 #define LCERR 1 #define LPERR 2 #define LSERR 3 #define LFERR 4 #define LOVERR 5 #define LTOERR 6 #define LABORT 7 #define LINBTR _SFR_MEM8(0xCC) #define LBT0 0 #define LBT1 1 #define LBT2 2 #define LBT3 3 #define LBT4 4 #define LBT5 5 #define LDISR 7 #define LINBRR _SFR_MEM16(0xCD) #define LINBRRL _SFR_MEM8(0xCD) #define LDIV0 0 #define LDIV1 1 #define LDIV2 2 #define LDIV3 3 #define LDIV4 4 #define LDIV5 5 #define LDIV6 6 #define LDIV7 7 #define LINBRRH _SFR_MEM8(0xCE) #define LDIV8 0 #define LDIV9 1 #define LDIV10 2 #define LDIV11 3 #define LINDLR _SFR_MEM8(0xCF) #define LRXDL0 0 #define LRXDL1 1 #define LRXDL2 2 #define LRXDL3 3 #define LTXDL0 4 #define LTXDL1 5 #define LTXDL2 6 #define LTXDL3 7 #define LINIDR _SFR_MEM8(0xD0) #define LID0 0 #define LID1 1 #define LID2 2 #define LID3 3 #define LID4 4 #define LID5 5 #define LP0 6 #define LP1 7 #define LINSEL _SFR_MEM8(0xD1) #define LINDX0 0 #define LINDX1 1 #define LINDX2 2 #define LAINC 3 #define LINDAT _SFR_MEM8(0xD2) #define LDATA0 0 #define LDATA1 1 #define LDATA2 2 #define LDATA3 3 #define LDATA4 4 #define LDATA5 5 #define LDATA6 6 #define LDATA7 7 #define CANGCON _SFR_MEM8(0xD8) #define SWRES 0 #define ENASTB 1 #define TEST 2 #define LISTEN 3 #define SYNTTC 4 #define TTC 5 #define OVRQ 6 #define ABRQ 7 #define CANGSTA _SFR_MEM8(0xD9) #define ERRP 0 #define BOFF 1 #define ENFG 2 #define RXBSY 3 #define TXBSY 4 #define OVFG 6 #define CANGIT _SFR_MEM8(0xDA) #define AERG 0 #define FERG 1 #define CERG 2 #define SERG 3 #define BXOK 4 #define OVRTIM 5 #define BOFFIT 6 #define CANIT 7 #define CANGIE _SFR_MEM8(0xDB) #define ENOVRT 0 #define ENERG 1 #define ENBX 2 #define ENERR 3 #define ENTX 4 #define ENRX 5 #define ENBOFF 6 #define ENIT 7 #define CANEN2 _SFR_MEM8(0xDC) #define ENMOB0 0 #define ENMOB1 1 #define ENMOB2 2 #define ENMOB3 3 #define ENMOB4 4 #define ENMOB5 5 #define CANEN1 _SFR_MEM8(0xDD) #define CANIE2 _SFR_MEM8(0xDE) #define IEMOB0 0 #define IEMOB1 1 #define IEMOB2 2 #define IEMOB3 3 #define IEMOB4 4 #define IEMOB5 5 #define CANIE1 _SFR_MEM8(0xDF) /* RegDef: CAN Status Interrupt MOb Register*/ #define CANSIT _SFR_MEM16(0xE0) #define CANSIT2 _SFR_MEM8(0xE0) #define SIT0 0 #define SIT1 1 #define SIT2 2 #define SIT3 3 #define SIT4 4 #define SIT5 5 #define CANSIT1 _SFR_MEM8(0xE1) #define CANBT1 _SFR_MEM8(0xE2) #define BRP0 1 #define BRP1 2 #define BRP2 3 #define BRP3 4 #define BRP4 5 #define BRP5 6 #define CANBT2 _SFR_MEM8(0xE3) #define PRS0 1 #define PRS1 2 #define PRS2 3 #define SJW0 5 #define SJW1 6 #define CANBT3 _SFR_MEM8(0xE4) #define SMP 0 #define PHS10 1 #define PHS11 2 #define PHS12 3 #define PHS20 4 #define PHS21 5 #define PHS22 6 #define CANTCON _SFR_MEM8(0xE5) #define TPRSC0 0 #define TPRSC1 1 #define TPRSC2 2 #define TPRSC3 3 #define TPRSC4 4 #define TPRSC5 5 #define TPRSC6 6 #define TPRSC7 7 #define CANTIM _SFR_MEM16(0xE6) #define CANTIML _SFR_MEM8(0xE6) #define CANTIM0 0 #define CANTIM1 1 #define CANTIM2 2 #define CANTIM3 3 #define CANTIM4 4 #define CANTIM5 5 #define CANTIM6 6 #define CANTIM7 7 #define CANTIMH _SFR_MEM8(0xE7) #define CANTIM8 0 #define CANTIM9 1 #define CANTIM10 2 #define CANTIM11 3 #define CANTIM12 4 #define CANTIM13 5 #define CANTIM14 6 #define CANTIM15 7 #define CANTTC _SFR_MEM16(0xE8) #define CANTTCL _SFR_MEM8(0xE8) #define TIMTCC0 0 #define TIMTCC1 1 #define TIMTCC2 2 #define TIMTCC3 3 #define TIMTCC4 4 #define TIMTCC5 5 #define TIMTCC6 6 #define TIMTCC7 7 #define CANTTCH _SFR_MEM8(0xE9) #define TIMTCC8 0 #define TIMTCC9 1 #define TIMTCC10 2 #define TIMTCC11 3 #define TIMTCC12 4 #define TIMTCC13 5 #define TIMTCC14 6 #define TIMTCC15 7 #define CANTEC _SFR_MEM8(0xEA) #define TEC0 0 #define TEC1 1 #define TEC2 2 #define TEC3 3 #define TEC4 4 #define TEC5 5 #define TEC6 6 #define TEC7 7 #define CANREC _SFR_MEM8(0xEB) #define REC0 0 #define REC1 1 #define REC2 2 #define REC3 3 #define REC4 4 #define REC5 5 #define REC6 6 #define REC7 7 #define CANHPMOB _SFR_MEM8(0xEC) #define CGP0 0 #define CGP1 1 #define CGP2 2 #define CGP3 3 #define HPMOB0 4 #define HPMOB1 5 #define HPMOB2 6 #define HPMOB3 7 #define CANPAGE _SFR_MEM8(0xED) #define INDX0 0 #define INDX1 1 #define INDX2 2 #define AINC 3 #define MOBNB0 4 #define MOBNB1 5 #define MOBNB2 6 #define MOBNB3 7 #define CANSTMOB _SFR_MEM8(0xEE) #define AERR 0 #define FERR 1 #define CERR 2 #define SERR 3 #define BERR 4 #define RXOK 5 #define TXOK 6 #define DLCW 7 #define CANCDMOB _SFR_MEM8(0xEF) #define DLC0 0 #define DLC1 1 #define DLC2 2 #define DLC3 3 #define IDE 4 #define RPLV 5 #define CONMOB0 6 #define CONMOB1 7 /* RegDef: CAN Identifier Tag Registers*/ #define CANIDT _SFR_MEM32(0xF0) #define CANIDT4 _SFR_MEM8(0xF0) #define RB0TAG 0 #define RB1TAG 1 #define RTRTAG 2 #define IDT0 3 #define IDT1 4 #define IDT2 5 #define IDT3 6 #define IDT4 7 #define CANIDT3 _SFR_MEM8(0xF1) #define IDT5 0 #define IDT6 1 #define IDT7 2 #define IDT8 3 #define IDT9 4 #define IDT10 5 #define IDT11 6 #define IDT12 7 #define CANIDT2 _SFR_MEM8(0xF2) #define IDT13 0 #define IDT14 1 #define IDT15 2 #define IDT16 3 #define IDT17 4 #define IDT18 5 #define IDT19 6 #define IDT20 7 #define CANIDT1 _SFR_MEM8(0xF3) #define IDT21 0 #define IDT22 1 #define IDT23 2 #define IDT24 3 #define IDT25 4 #define IDT26 5 #define IDT27 6 #define IDT28 7 /* RegDef: CAN Identifier Mask Registers */ #define CANIDM _SFR_MEM32(0xF4) #define CANIDM4 _SFR_MEM8(0xF4) #define IDEMSK 0 #define RTRMSK 2 #define IDMSK0 3 #define IDMSK1 4 #define IDMSK2 5 #define IDMSK3 6 #define IDMSK4 7 #define CANIDM3 _SFR_MEM8(0xF5) #define IDMSK5 0 #define IDMSK6 1 #define IDMSK7 2 #define IDMSK8 3 #define IDMSK9 4 #define IDMSK10 5 #define IDMSK11 6 #define IDMSK12 7 #define CANIDM2 _SFR_MEM8(0xF6) #define IDMSK13 0 #define IDMSK14 1 #define IDMSK15 2 #define IDMSK16 3 #define IDMSK17 4 #define IDMSK18 5 #define IDMSK19 6 #define IDMSK20 7 #define CANIDM1 _SFR_MEM8(0xF7) #define IDMSK21 0 #define IDMSK22 1 #define IDMSK23 2 #define IDMSK24 3 #define IDMSK25 4 #define IDMSK26 5 #define IDMSK27 6 #define IDMSK28 7 #define CANSTM _SFR_MEM16(0xF8) #define CANSTML _SFR_MEM8(0xF8) #define TIMSTM0 0 #define TIMSTM1 1 #define TIMSTM2 2 #define TIMSTM3 3 #define TIMSTM4 4 #define TIMSTM5 5 #define TIMSTM6 6 #define TIMSTM7 7 #define CANSTMH _SFR_MEM8(0xF9) #define TIMSTM8 0 #define TIMSTM9 1 #define TIMSTM10 2 #define TIMSTM11 3 #define TIMSTM12 4 #define TIMSTM13 5 #define TIMSTM14 6 #define TIMSTM15 7 #define CANMSG _SFR_MEM8(0xFA) #define MSG0 0 #define MSG1 1 #define MSG2 2 #define MSG3 3 #define MSG4 4 #define MSG5 5 #define MSG6 6 #define MSG7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define ANACOMP0_vect_num 1 #define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ #define ANACOMP1_vect_num 2 #define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ #define ANACOMP2_vect_num 3 #define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ #define ANACOMP3_vect_num 4 #define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ #define PSC_FAULT_vect_num 5 #define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ #define PSC_EC_vect_num 6 #define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ #define INT0_vect_num 7 #define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ #define INT1_vect_num 8 #define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ #define INT2_vect_num 9 #define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ #define INT3_vect_num 10 #define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 14 #define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 15 #define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 16 #define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ #define CAN_INT_vect_num 18 #define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ #define CAN_TOVF_vect_num 19 #define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ #define LIN_TC_vect_num 20 #define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ #define LIN_ERR_vect_num 21 #define LIN_ERR_vect _VECTOR(21) /* LIN Error */ #define PCINT0_vect_num 22 #define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 23 #define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ #define PCINT2_vect_num 24 #define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ #define PCINT3_vect_num 25 #define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ #define SPI_STC_vect_num 26 #define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ #define ADC_vect_num 27 #define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ #define WDT_vect_num 28 #define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ #define EE_READY_vect_num 29 #define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ #define SPM_READY_vect_num 30 #define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (31 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (256) #define RAMSTART (0x0100) #define RAMSIZE (4096) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (0x0) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x7FF) #define E2PAGESIZE (8) #define FLASHEND (0xFFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ #define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ #define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ #define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x86 #endif /* _AVR_ATmega64C1_H_ */ avr-libc-1.8.0.orig/include/avr/iox256a3b.h0000644000000000000000000111213411732702554015063 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox256a3b.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox256a3b.h - definitions for ATxmega256A3B */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox256a3b.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega256A3B_H_ #define _AVR_ATxmega256A3B_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated*/ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* JTAG User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t GAINCAL; /* Gain Calibration */ register8_t OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- RTC32 - 32-bit Real-Time Counter -------------------------------------------------------------------------- */ /* 32-bit Real-Time Clounter */ typedef struct RTC32_struct { register8_t CTRL; /* Control Register */ register8_t SYNCCTRL; /* Synchronization Control/Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ _DWORDREGISTER(CNT); /* Count Register */ _DWORDREGISTER(PER); /* Period Register */ _DWORDREGISTER(COMP); /* Compare Register */ } RTC32_t; /* Compare Interrupt level */ typedef enum RTC32_COMPINTLVL_enum { RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC32_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC32_OVFINTLVL_enum { RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC32_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* -------------------------------------------------------------------------- VBAT - VBAT Battery Backup Module -------------------------------------------------------------------------- */ /* VBAT Battery Backup Module */ typedef struct VBAT_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t BACKUP0; /* Battery Bacup Register 0 */ register8_t BACKUP1; /* Battery Backup Register 1 */ } VBAT_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define VBAT (*(VBAT_t *) 0x00F0) /* VBAT Battery Backup Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* VBAT - VBAT Battery Backup Module */ #define VBAT_CTRL _SFR_MEM8(0x00F0) #define VBAT_STATUS _SFR_MEM8(0x00F1) #define VBAT_BACKUP0 _SFR_MEM8(0x00F2) #define VBAT_BACKUP1 _SFR_MEM8(0x00F3) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* ADCB - Analog to Digital Converter B */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) #define ADCB_EVCTRL _SFR_MEM8(0x0243) #define ADCB_PRESCALER _SFR_MEM8(0x0244) #define ADCB_INTFLAGS _SFR_MEM8(0x0246) #define ADCB_CAL _SFR_MEM16(0x024C) #define ADCB_CH0RES _SFR_MEM16(0x0250) #define ADCB_CH1RES _SFR_MEM16(0x0252) #define ADCB_CH2RES _SFR_MEM16(0x0254) #define ADCB_CH3RES _SFR_MEM16(0x0256) #define ADCB_CMP _SFR_MEM16(0x0258) #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_GAINCAL _SFR_MEM8(0x0328) #define DACB_OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC32 - 32-bit Real-Time Counter */ #define RTC32_CTRL _SFR_MEM8(0x0420) #define RTC32_SYNCCTRL _SFR_MEM8(0x0421) #define RTC32_INTCTRL _SFR_MEM8(0x0422) #define RTC32_INTFLAGS _SFR_MEM8(0x0423) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* TCE1 - Timer/Counter E1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) #define TCE1_CTRLD _SFR_MEM8(0x0A43) #define TCE1_CTRLE _SFR_MEM8(0x0A44) #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) #define TCE1_TEMP _SFR_MEM8(0x0A4F) #define TCE1_CNT _SFR_MEM16(0x0A60) #define TCE1_PER _SFR_MEM16(0x0A66) #define TCE1_CCA _SFR_MEM16(0x0A68) #define TCE1_CCB _SFR_MEM16(0x0A6A) #define TCE1_PERBUF _SFR_MEM16(0x0A76) #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /* HIRESF - High-Resolution Extension F */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) /* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) #define USARTF1_CTRLB _SFR_MEM8(0x0BB4) #define USARTF1_CTRLC _SFR_MEM8(0x0BB5) #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) /* SPIF - Serial Peripheral Interface F */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) #define SPIF_DATA _SFR_MEM8(0x0BC3) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ #define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ #define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ #define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ #define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ #define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ #define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ #define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ #define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ #define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ #define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ #define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ #define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ #define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ #define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ #define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ #define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ #define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ #define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ #define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* RTC32 - 32-bit Real-Time Counter */ /* RTC32.CTRL bit masks and bit positions */ #define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ #define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ /* RTC32.SYNCCTRL bit masks and bit positions */ #define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ #define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ #define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC32.INTCTRL bit masks and bit positions */ #define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC32.INTFLAGS bit masks and bit positions */ #define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* VBAT - VBAT Battery Backup Module */ /* VBAT.CTRL bit masks and bit positions */ #define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ #define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ #define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ #define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ #define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ #define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ #define VBAT_ACCEN_bm 0x02 /* Battery Backup Access Enable bit mask. */ #define VBAT_ACCEN_bp 1 /* Battery Backup Access Enable bit position. */ #define VBAT_RESET_bm 0x01 /* Battery Backup Reset bit mask. */ #define VBAT_RESET_bp 0 /* Battery Backup Reset bit position. */ /* VBAT.STATUS bit masks and bit positions */ #define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ #define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ #define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ #define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ #define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ #define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ #define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ #define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ #define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ #define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC32 interrupt vectors */ #define RTC32_OVF_vect_num 10 #define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC32_COMP_vect_num 11 #define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* ACB interrupt vectors */ #define ACB_AC0_vect_num 36 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ #define ACB_AC1_vect_num 37 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ #define ACB_ACW_vect_num 38 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ /* ADCB interrupt vectors */ #define ADCB_CH0_vect_num 39 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ #define ADCB_CH1_vect_num 40 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ #define ADCB_CH2_vect_num 41 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ #define ADCB_CH3_vect_num 42 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ /* USARTF0 interrupt vectors */ #define USARTF0_RXC_vect_num 119 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ #define USARTF0_DRE_vect_num 120 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ #define USARTF0_TXC_vect_num 121 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (122 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (270336) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (262144) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x3E000) #define APPTABLE_SECTION_SIZE (8192) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x40000) #define BOOT_SECTION_SIZE (8192) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (24576) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (4096) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (16384) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (4096) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ #define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ #define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ #define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ #define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ #define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ #define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ #define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x98 #define SIGNATURE_2 0x43 #endif /* _AVR_ATxmega256A3B_H_ */ avr-libc-1.8.0.orig/include/avr/iotn44.h0000644000000000000000000000615411732702554014565 0ustar /* Copyright (c) 2005, Anatoly Sokolov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn44.h 2115 2010-04-05 23:19:53Z arcanum $ */ /* avr/iotn44.h - definitions for ATtiny44 */ #ifndef _AVR_IOTN44_H_ #define _AVR_IOTN44_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x60) #define RAMEND 0x15F #define XRAMEND RAMEND #define E2END 0xFF #define E2PAGESIZE 4 #define FLASHEND 0xFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x07 #endif /* _AVR_IOTN44_H_ */ avr-libc-1.8.0.orig/include/avr/io1200.h0000644000000000000000000001247311732702554014357 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io1200.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io1200.h - definitions for AT90S1200 */ #ifndef _AVR_IO1200_H_ #define _AVR_IO1200_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io1200.h" #else # error "Attempt to include more than one file." #endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" #endif /* I/O registers */ /* 0x00..0x07 reserved */ /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* 0x09..0x0F reserved */ #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) /* 0x13..0x15 reserved */ #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) /* 0x19..0x1B reserved */ /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* 0x1F..0x20 reserved */ /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* 0x22..0x31 reserved */ #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) /* 0x34 reserved */ #define MCUCR _SFR_IO8(0x35) /* 0x36..0x37 reserved */ /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK Register */ #define TIMSK _SFR_IO8(0x39) /* 0x3A reserved */ #define GIMSK _SFR_IO8(0x3B) /* 0x3C..0x3E reserved */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 2 #define TIMER0_OVF_vect _VECTOR(2) #define SIG_OVERFLOW0 _VECTOR(2) /* Analog Comparator */ #define ANA_COMP_vect_num 3 #define ANA_COMP_vect _VECTOR(3) #define SIG_COMPARATOR _VECTOR(3) #define _VECTORS_SIZE 8 /* Bit numbers */ /* GIMSK */ #define INT0 6 /* TIMSK */ #define TOIE0 1 /* TIFR */ #define TOV0 1 /* MCUCR */ #define SE 5 #define SM 4 #define ISC01 1 #define ISC00 0 /* TCCR0 */ #define CS02 2 #define CS01 1 #define CS00 0 /* WDTCR */ #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* EECR */ #undef EEMWE /* PB7 = SCK PB6 = MISO PB5 = MOSI PB1 = AIN1 PB0 = AIN0 */ /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PORTD */ #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* ACSR */ #define ACD 7 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIS1 1 #define ACIS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 #undef ZH /* Last memory addresses */ #define RAMEND 0x1F #define XRAMEND 0x0 #define E2END 0x3F #define E2PAGESIZE 0 #define FLASHEND 0x3FF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_RCEN (unsigned char)~_BV(0) #define FUSE_SPIEN (unsigned char)~_BV(5) #define LFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x01 #endif /* _AVR_IO1200_H_ */ avr-libc-1.8.0.orig/include/avr/iom328p.h0000644000000000000000000004450011732702554014642 0ustar /* Copyright (c) 2007 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom328p.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iom328p.h - definitions for ATmega328P. */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom328p.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOM328P_H_ #define _AVR_IOM328P_H_ 1 /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define PCIF2 2 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define _EEPROM_REG_LOCATIONS_ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define BODSE 5 #define BODS 6 #define SPMCSR _SFR_IO8(0x37) #define SELFPRGEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define PCIE2 2 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCMSK2 _SFR_MEM8(0x6D) #define PCINT16 0 #define PCINT17 1 #define PCINT18 2 #define PCINT19 3 #define PCINT20 4 #define PCINT21 5 #define PCINT22 6 #define PCINT23 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 0 #define TWAM1 1 #define TWAM2 2 #define TWAM3 3 #define TWAM4 4 #define TWAM5 5 #define TWAM6 6 #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0xC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCPHA0 1 #define UCSZ01 2 #define UDORD0 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL00 6 #define UMSEL01 7 #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0_0 0 #define UBRR0_1 1 #define UBRR0_2 2 #define UBRR0_3 3 #define UBRR0_4 4 #define UBRR0_5 5 #define UBRR0_6 6 #define UBRR0_7 7 #define UBRR0H _SFR_MEM8(0xC5) #define UBRR0_8 0 #define UBRR0_9 1 #define UBRR0_10 2 #define UBRR0_11 3 #define UDR0 _SFR_MEM8(0xC6) #define UDR0_0 0 #define UDR0_1 1 #define UDR0_2 2 #define UDR0_3 3 #define UDR0_4 4 #define UDR0_5 5 #define UDR0_6 6 #define UDR0_7 7 /* Interrupt Vectors */ /* Interrupt Vector 0 is the reset vector. */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define PCINT0_vect_num 3 #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 4 #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ #define PCINT2_vect_num 5 #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ #define WDT_vect_num 6 #define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 7 #define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 8 #define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ #define TIMER2_OVF_vect_num 9 #define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 10 #define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 11 #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 12 #define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ #define TIMER1_OVF_vect_num 13 #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ #define TIMER0_OVF_vect_num 16 #define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ #define SPI_STC_vect_num 17 #define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ #define USART_RX_vect_num 18 #define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ #define USART_UDRE_vect_num 19 #define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ #define USART_TX_vect_num 20 #define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ #define ADC_vect_num 21 #define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ #define EE_READY_vect_num 22 #define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ #define ANALOG_COMP_vect_num 23 #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ #define TWI_vect_num 24 #define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ #define SPM_READY_vect_num 25 #define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ #define _VECTORS_SIZE (26 * 4) /* Constants */ #define SPM_PAGESIZE 128 #define RAMSTART (0x100) #define RAMEND 0x8FF /* Last On-Chip SRAM Location */ #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x3FF #define E2PAGESIZE 4 #define FLASHEND 0x7FFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x0F #endif /* _AVR_IOM328P_H_ */ avr-libc-1.8.0.orig/include/avr/iox32a4.h0000644000000000000000000106553411732702554014645 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox32a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox32a4.h - definitions for ATxmega32A4 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox32a4.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega32A4_H_ #define _AVR_ATxmega32A4_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t GAINCAL; /* Gain Calibration */ register8_t OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_GAINCAL _SFR_MEM8(0x0328) #define DACB_OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (94 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (36864) #define PROGMEM_PAGE_SIZE (256) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (32768) #define APP_SECTION_PAGE_SIZE (256) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x07000) #define APPTABLE_SECTION_SIZE (4096) #define APPTABLE_SECTION_PAGE_SIZE (256) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x8000) #define BOOT_SECTION_SIZE (4096) #define BOOT_SECTION_PAGE_SIZE (256) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (12288) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (1024) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (4096) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (1024) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (256) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x41 #endif /* _AVR_ATxmega32A4_H_ */ avr-libc-1.8.0.orig/include/avr/iom32u2.h0000644000000000000000000005013411732702554014641 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom32u2.h 2240 2011-05-09 22:18:18Z arcanum $ */ /* avr/iom32u2.h - definitions for ATmega32U2 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32u2.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega32U2_H_ #define _AVR_ATmega32U2_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define OCF1C 3 #define ICF1 5 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define INTF4 4 #define INTF5 5 #define INTF6 6 #define INTF7 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define INT4 4 #define INT5 5 #define INT6 6 #define INT7 7 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLP0 2 #define PLLP1 3 #define PLLP2 4 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define DWDR _SFR_IO8(0x31) #define DWDR0 0 #define DWDR1 1 #define DWDR2 2 #define DWDR3 3 #define DWDR4 4 #define DWDR5 5 #define DWDR6 6 #define DWDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define USBRF 5 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define EIND _SFR_IO8(0x3C) #define EIND0 0 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define WDTCKD _SFR_MEM8(0x62) #define WCLKD0 0 #define WCLKD1 1 #define WDEWIE 2 #define WDEWIF 3 #define REGCR _SFR_MEM8(0x63) #define REGDIS 0 #define PRR0 _SFR_MEM8(0x64) #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRR1 _SFR_MEM8(0x65) #define PRUSART1 0 #define PRUSB 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define EICRB _SFR_MEM8(0x6A) #define ISC40 0 #define ISC41 1 #define ISC50 2 #define ISC51 3 #define ISC60 4 #define ISC61 5 #define ISC70 6 #define ISC71 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define OCIE1C 3 #define ICIE1 5 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1C0 2 #define COM1C1 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1C 5 #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CL0 0 #define OCR1CL1 1 #define OCR1CL2 2 #define OCR1CL3 3 #define OCR1CL4 4 #define OCR1CL5 5 #define OCR1CL6 6 #define OCR1CL7 7 #define OCR1CH _SFR_MEM8(0x8D) #define OCR1CH0 0 #define OCR1CH1 1 #define OCR1CH2 2 #define OCR1CH3 3 #define OCR1CH4 4 #define OCR1CH5 5 #define OCR1CH6 6 #define OCR1CH7 7 #define UCSR1A _SFR_MEM8(0xC8) #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 #define UCSR1B _SFR_MEM8(0xC9) #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 #define UCSR1C _SFR_MEM8(0xCA) #define UCPOL1 0 #define UCSZ10 1 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 #define UCSR1D _SFR_MEM8(0xCB) #define RTSEN 0 #define CTSEN 1 #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1_0 0 #define UBRR1_1 1 #define UBRR1_2 2 #define UBRR1_3 3 #define UBRR1_4 4 #define UBRR1_5 5 #define UBRR1_6 6 #define UBRR1_7 7 #define UBRR1H _SFR_MEM8(0xCD) #define UBRR1_8 0 #define UBRR1_9 1 #define UBRR1_10 2 #define UBRR1_11 3 #define UDR1 _SFR_MEM8(0xCE) #define UDR1_0 0 #define UDR1_1 1 #define UDR1_2 2 #define UDR1_3 3 #define UDR1_4 4 #define UDR1_5 5 #define UDR1_6 6 #define UDR1_7 7 #define CLKSEL0 _SFR_MEM8(0xD0) #define CLKS 0 #define EXTE 2 #define RCE 3 #define EXSUT0 4 #define EXSUT1 5 #define RCSUT0 6 #define RCSUT1 7 #define CLKSEL1 _SFR_MEM8(0xD1) #define EXCKSEL0 0 #define EXCKSEL1 1 #define EXCKSEL2 2 #define EXCKSEL3 3 #define RCCKSEL0 4 #define RCCKSEL1 5 #define RCCKSEL2 6 #define RCCKSEL3 7 #define CLKSTA _SFR_MEM8(0xD2) #define EXTON 0 #define RCON 1 #define USBCON _SFR_MEM8(0xD8) #define FRZCLK 5 #define USBE 7 #define UDCON _SFR_MEM8(0xE0) #define DETACH 0 #define RMWKUP 1 #define RSTCPU 2 #define UDINT _SFR_MEM8(0xE1) #define SUSPI 0 #define SOFI 2 #define EORSTI 3 #define WAKEUPI 4 #define EORSMI 5 #define UPRSMI 6 #define UDIEN _SFR_MEM8(0xE2) #define SUSPE 0 #define SOFE 2 #define EORSTE 3 #define WAKEUPE 4 #define EORSME 5 #define UPRSME 6 #define UDADDR _SFR_MEM8(0xE3) #define UADD0 0 #define UADD1 1 #define UADD2 2 #define UADD3 3 #define UADD4 4 #define UADD5 5 #define UADD6 6 #define ADDEN 7 #define UDFNUM _SFR_MEM16(0xE4) #define UDFNUML _SFR_MEM8(0xE4) #define FNUM0 0 #define FNUM1 1 #define FNUM2 2 #define FNUM3 3 #define FNUM4 4 #define FNUM5 5 #define FNUM6 6 #define FNUM7 7 #define UDFNUMH _SFR_MEM8(0xE5) #define FNUM8 0 #define FNUM9 1 #define FNUM10 2 #define UDMFN _SFR_MEM8(0xE6) #define FNCERR 4 #define UEINTX _SFR_MEM8(0xE8) #define TXINI 0 #define STALLEDI 1 #define RXOUTI 2 #define RXSTPI 3 #define NAKOUTI 4 #define RWAL 5 #define NAKINI 6 #define FIFOCON 7 #define UENUM _SFR_MEM8(0xE9) #define EPNUM0 0 #define EPNUM1 1 #define EPNUM2 2 #define UERST _SFR_MEM8(0xEA) #define EPRST0 0 #define EPRST1 1 #define EPRST2 2 #define EPRST3 3 #define EPRST4 4 #define UECONX _SFR_MEM8(0xEB) #define EPEN 0 #define RSTDT 3 #define STALLRQC 4 #define STALLRQ 5 #define UECFG0X _SFR_MEM8(0xEC) #define EPDIR 0 #define EPTYPE0 6 #define EPTYPE1 7 #define UECFG1X _SFR_MEM8(0xED) #define ALLOC 1 #define EPBK0 2 #define EPBK1 3 #define EPSIZE0 4 #define EPSIZE1 5 #define EPSIZE2 6 #define UESTA0X _SFR_MEM8(0xEE) #define NBUSYBK0 0 #define NBUSYBK1 1 #define DTSEQ0 2 #define DTSEQ1 3 #define UNDERFI 5 #define OVERFI 6 #define CFGOK 7 #define UESTA1X _SFR_MEM8(0xEF) #define CURRBK0 0 #define CURRBK1 1 #define CTRLDIR 2 #define UEIENX _SFR_MEM8(0xF0) #define TXINE 0 #define STALLEDE 1 #define RXOUTE 2 #define RXSTPE 3 #define NAKOUTE 4 #define NAKINE 6 #define FLERRE 7 #define UEDATX _SFR_MEM8(0xF1) #define DAT0 0 #define DAT1 1 #define DAT2 2 #define DAT3 3 #define DAT4 4 #define DAT5 5 #define DAT6 6 #define DAT7 7 #define UEBCLX _SFR_MEM8(0xF2) #define BYCT0 0 #define BYCT1 1 #define BYCT2 2 #define BYCT3 3 #define BYCT4 4 #define BYCT5 5 #define BYCT6 6 #define BYCT7 7 #define UEINT _SFR_MEM8(0xF4) #define EPINT0 0 #define EPINT1 1 #define EPINT2 2 #define EPINT3 3 #define EPINT4 4 #define PS2CON _SFR_MEM8(0xFA) #define PS2EN 0 #define UPOE _SFR_MEM8(0xFB) #define DMI 0 #define DPI 1 #define DATAI 2 #define SCKI 3 #define UPDRV0 4 #define UPDRV1 5 #define UPWE0 6 #define UPWE1 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ #define PCINT0_vect_num 9 #define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 10 #define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */ #define USB_GEN_vect_num 11 #define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */ #define USB_COM_vect_num 12 #define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */ #define WDT_vect_num 13 #define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */ #define TIMER1_CAPT_vect_num 14 #define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ #define TIMER1_COMPA_vect_num 15 #define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ #define TIMER0_COMPA_vect_num 19 #define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 20 #define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 21 #define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 22 #define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */ #define USART1_RX_vect_num 23 #define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */ #define USART1_UDRE_vect_num 24 #define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */ #define USART1_TX_vect_num 25 #define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */ #define ANALOG_COMP_vect_num 26 #define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */ #define EE_READY_vect_num 27 #define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ #define SPM_READY_vect_num 28 #define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */ #define TIMER1_COMPB_vect_num 16 #define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */ #define TIMER1_COMPC_vect_num 17 #define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */ #define TIMER1_OVF_vect_num 18 #define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (29 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (1024) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x3FF) #define E2PAGESIZE (4) #define FLASHEND (0x7FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */ #define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */ #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x8A /* Device Pin Definitions */ #endif /* _AVR_ATmega32U2_H_ */ avr-libc-1.8.0.orig/include/avr/io90pwm216.h0000644000000000000000000011361311732702554015200 0ustar /* Copyright (c) 2007, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: io90pwm216.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwm216.h - definitions for AT90PWM216 */ #ifndef _AVR_IO90PWM216_H_ #define _AVR_IO90PWM216_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "io90pwm216.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* Port B Input Pins Address */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 /* Port B Data Direction Register */ #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 /* Port B Data Register */ #define PORTB _SFR_IO8(0x05) #define PB0 0 #define PB1 1 #define PB2 2 #define PB3 3 #define PB4 4 #define PB5 5 #define PB6 6 #define PB7 7 /* Port C Input Pins Address */ #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 /* Port C Data Direction Register */ #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 /* Port C Data Register */ #define PORTC _SFR_IO8(0x08) #define PC0 0 #define PC1 1 #define PC2 2 #define PC3 3 #define PC4 4 #define PC5 5 #define PC6 6 #define PC7 7 /* Port D Input Pins Address */ #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 /* Port D Data Direction Register */ #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 /* Port D Data Register */ #define PORTD _SFR_IO8(0x0B) #define PD0 0 #define PD1 1 #define PD2 2 #define PD3 3 #define PD4 4 #define PD5 5 #define PD6 6 #define PD7 7 /* Port E Input Pins Address */ #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 /* Port E Data Direction Register */ #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 /* Port E Data Register */ #define PORTE _SFR_IO8(0x0E) #define PE0 0 #define PE1 1 #define PE2 2 /* Timer/Counter 0 Interrupt Flag Register */ #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 /* Overflow Flag */ #define OCF0A 1 /* Output Compare Flag 0A */ #define OCF0B 2 /* Output Compare Flag 0B */ /* Timer/Counter1 Interrupt Flag Register */ #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 /* Overflow Flag */ #define OCF1A 1 /* Output Compare Flag 1A*/ #define OCF1B 2 /* Output Compare Flag 1B*/ #define ICF1 5 /* Input Capture Flag 1 */ /* General Purpose I/O Register 1 */ #define GPIOR1 _SFR_IO8(0x19) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 /* General Purpose I/O Register 2 */ #define GPIOR2 _SFR_IO8(0x1A) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 /* General Purpose I/O Register 3 */ #define GPIOR3 _SFR_IO8(0x1B) #define GPIOR30 0 #define GPIOR31 1 #define GPIOR32 2 #define GPIOR33 3 #define GPIOR34 4 #define GPIOR35 5 #define GPIOR36 6 #define GPIOR37 7 /* External Interrupt Flag Register */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 /* External Interrupt Mask Register */ #define EIMSK _SFR_IO8(0x1D) #define INT0 0 /* External Interrupt Request 0 Enable */ #define INT1 1 /* External Interrupt Request 1 Enable */ #define INT2 2 /* External Interrupt Request 2 Enable */ #define INT3 3 /* External Interrupt Request 3 Enable */ /* General Purpose I/O Register 0 */ #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1F) #define EERE 0 /* EEPROM Read Enable */ #define EEWE 1 /* EEPROM Write Enable */ #define EEMWE 2 /* EEPROM Master Write Enable */ #define EERIE 3 /* EEPROM Ready Interrupt Enable */ /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 /* The EEPROM Address Registers */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 /* General Timer/Counter Control Register */ #define GTCCR _SFR_IO8(0x23) #define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ #define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ #define TSM 7 /* Timer/Counter Synchronization Mode */ /* Timer/Counter Control Register A */ #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 /* Waveform Generation Mode */ #define WGM01 1 /* Waveform Generation Mode */ #define COM0B0 4 /* Compare Output Mode, Fast PWm */ #define COM0B1 5 /* Compare Output Mode, Fast PWm */ #define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ #define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ /* Timer/Counter Control Register B */ #define TCCR0B _SFR_IO8(0x25) #define CS00 0 /* Clock Select */ #define CS01 1 /* Clock Select */ #define CS02 2 /* Clock Select */ #define WGM02 3 /* Waveform Generation Mode */ #define FOC0B 6 /* Force Output Compare B */ #define FOC0A 7 /* Force Output Compare A */ /* Timer/Counter0 Register */ #define TCNT0 _SFR_IO8(0x26) #define TCNT00 0 #define TCNT01 1 #define TCNT02 2 #define TCNT03 3 #define TCNT04 4 #define TCNT05 5 #define TCNT06 6 #define TCNT07 7 /* Timer/Counter0 Output Compare Register A */ #define OCR0A _SFR_IO8(0x27) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 /* Timer/Counter0 Output Compare Register B */ #define OCR0B _SFR_IO8(0x28) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 /* PLL Control and Status Register */ #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 /* PLL Lock Detector */ #define PLLE 1 /* PLL Enable */ #define PLLF 2 /* PLL Factor */ /* SPI Control Register */ #define SPCR _SFR_IO8(0x2C) #define SPR0 0 /* SPI Clock Rate Select 0 */ #define SPR1 1 /* SPI Clock Rate Select 1 */ #define CPHA 2 /* Clock Phase */ #define CPOL 3 /* Clock polarity */ #define MSTR 4 /* Master/Slave Select */ #define DORD 5 /* Data Order */ #define SPE 6 /* SPI Enable */ #define SPIE 7 /* SPI Interrupt Enable */ /* SPI Status Register */ #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 /* Double SPI Speed Bit */ #define WCOL 6 /* Write Collision Flag */ #define SPIF 7 /* SPI Interrupt Flag */ /* SPI Data Register */ #define SPDR _SFR_IO8(0x2E) #define SPD0 0 #define SPD1 1 #define SPD2 2 #define SPD3 3 #define SPD4 4 #define SPD5 5 #define SPD6 6 #define SPD7 7 /* Analog Comparator Status Register */ #define ACSR _SFR_IO8(0x30) #define AC0O 0 /* Analog Comparator 0 Output Bit */ #define AC1O 1 /* Analog Comparator 1 Output Bit */ #define AC2O 2 /* Analog Comparator 2 Output Bit */ #define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ #define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ #define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ #define ACCKDIV 7 /* Analog Comparator Clock Divider */ /* Sleep Mode Control Register */ #define SMCR _SFR_IO8(0x33) #define SE 0 /* Sleep Enable */ #define SM0 1 /* Sleep Mode Select bit0 */ #define SM1 2 /* Sleep Mode Select bit1 */ #define SM2 3 /* Sleep Mode Select bit2 */ /* MCU Status Register */ #define MCUSR _SFR_IO8(0x34) #define PORF 0 /* Power-on reset flag */ #define EXTRF 1 /* External Reset Flag */ #define BORF 2 /* Brown-out Reset Flag */ #define WDRF 3 /* Watchdog Reset Flag */ /* MCU Control Register */ #define MCUCR _SFR_IO8(0x35) #define IVCE 0 /* Interrupt Vector Change Enable */ #define IVSEL 1 /* Interrupt Vector Select */ #define PUD 4 /* Pull-up disable */ #define SPIPS 7 /* SPI Pin Select */ /* Store Program Memory Control Register */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 /* Store Program Memory Enable */ #define PGERS 1 /* Page Erase */ #define PGWRT 2 /* Page Write */ #define BLBSET 3 /* Boot Lock Bit Set */ #define RWWSRE 4 /* Read While Write section read enable */ #define RWWSB 6 /* Read While Write Section Busy */ #define SPMIE 7 /* SPM Interrupt Enable */ /* Watchdog Timer Control Register */ #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 /* Watchdog Timer Prescaler bit0 */ #define WDP1 1 /* Watchdog Timer Prescaler bit1 */ #define WDP2 2 /* Watchdog Timer Prescaler bit2 */ #define WDE 3 /* Watchdog Enable */ #define WDCE 4 /* Watchdog Change Enable */ #define WDP3 5 /* Watchdog Timer Prescaler bit3 */ #define WDIE 6 /* Watchdog Timeout Interrupt Enable */ #define WDIF 7 /* Watchdog Timeout Interrupt Flag */ /* Clock Prescaler Register */ #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 /* Clock Prescaler Select bit0 */ #define CLKPS1 1 /* Clock Prescaler Select bit1 */ #define CLKPS2 2 /* Clock Prescaler Select bit2 */ #define CLKPS3 3 /* Clock Prescaler Select bit3 */ #define CLKPCE 7 /* Clock Prescaler Change Enable */ /* Power Reduction Register */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 /* Power Reduction ADC */ #define PRUSART 1 /* Power Reduction USART */ #define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ #define PRTIM0 3 /* Power Reduction Timer/Counter0 */ #define PRTIM1 4 /* Power Reduction Timer/Counter1 */ #define PRPSC0 5 /* Power Reduction PSC0 */ #define PRPSC1 6 /* Power Reduction PSC1 */ #define PRPSC2 7 /* Power Reduction PSC2 */ /* Oscillator Calibration Value */ #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 /* External Interrupt Control Register A */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 /* Timer/Counter0 Interrupt Mask Register */ #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 /* Overflow Interrupt Enable */ #define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ #define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ /* Timer/Counter1 Interrupt Mask Register */ #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 /* Overflow Interrupt Enable */ #define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ #define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ #define ICIE1 5 /* Input Capture Interrupt Enable */ /* Amplifier 0 Control and Status register */ #define AMP0CSR _SFR_MEM8(0x76) #define AMP0TS0 0 #define AMP0TS1 1 #define AMP0G0 4 #define AMP0G1 5 #define AMP0IS 6 #define AMP0EN 7 /* Amplifier 1 Control and Status register */ #define AMP1CSR _SFR_MEM8(0x77) #define AMP1TS0 0 #define AMP1TS1 1 #define AMP1G0 4 #define AMP1G1 5 #define AMP1IS 6 #define AMP1EN 7 /* ADC Result Data Register */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) /* ADC Control and Status Register A */ #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 /* ADC Prescaler Select bit0 */ #define ADPS1 1 /* ADC Prescaler Select bit1 */ #define ADPS2 2 /* ADC Prescaler Select bit2 */ #define ADIE 3 /* ADC Interrupt Enable */ #define ADIF 4 /* ADC Interrupt Flag */ #define ADATE 5 /* ADC Auto Trigger Enable */ #define ADSC 6 /* ADC Start Conversion */ #define ADEN 7 /* ADC Enable */ /* ADC Control and Status Register B */ #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 /* ADC Auto Trigger Source 0 */ #define ADTS1 1 /* ADC Auto Trigger Source 1 */ #define ADTS2 2 /* ADC Auto Trigger Source 2 */ #define ADTS3 3 /* ADC Auto Trigger Source 3 */ #define ADHSM 7 /* ADC High Speed Mode */ /* ADC multiplexer Selection Register */ #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 /* Analog Channel and Gain Selection bit0 */ #define MUX1 1 /* Analog Channel and Gain Selection bit1 */ #define MUX2 2 /* Analog Channel and Gain Selection bit2 */ #define MUX3 3 /* Analog Channel and Gain Selection bit3 */ #define ADLAR 5 /* Left Adjust Result */ #define REFS0 6 /* Reference Selection bit0 */ #define REFS1 7 /* Reference Selection bit1 */ /* Digital Input Disable Register 0 */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 /* ADC0 Digital input Disable */ #define ADC1D 1 /* ADC1 Digital input Disable */ #define ADC2D 2 /* ADC2 Digital input Disable */ #define ADC3D 3 /* ADC3 Digital input Disable */ #define ADC4D 4 /* ADC4 Digital input Disable */ #define ADC5D 5 /* ADC5 Digital input Disable */ #define ADC6D 6 /* ADC6 Digital input Disable */ #define ADC7D 7 /* ADC7 Digital input Disable */ /* Digital Input Disable Register 1 */ #define DIDR1 _SFR_MEM8(0x7F) #define ADC8D 0 /* ADC8 Digital input Disable */ #define ADC9D 1 /* ADC9 Digital input Disable */ #define ADC10D 2 /* ADC10 Digital input Disable */ #define AMP0ND 3 #define AMP0PD 4 #define ACMP0D 5 /* Timer/Counter1 Control Register A */ #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 /* Waveform Generation Mode */ #define WGM11 1 /* Waveform Generation Mode */ #define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ #define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ #define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ #define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ /* Timer/Counter1 Control Register B */ #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 /* Prescaler source of Timer/Counter 1 */ #define CS11 1 /* Prescaler source of Timer/Counter 1 */ #define CS12 2 /* Prescaler source of Timer/Counter 1 */ #define WGM12 3 /* Waveform Generation Mode */ #define WGM13 4 /* Waveform Generation Mode */ #define ICES1 6 /* Input Capture 1 Edge Select */ #define ICNC1 7 /* Input Capture 1 Noise Canceler */ /* Timer/Counter1 Control Register C */ #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 /* Force Output Compare for Channel B */ #define FOC1A 7 /* Force Output Compare for Channel A */ /* Timer/Counter1 */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT10 0 #define TCNT11 1 #define TCNT12 2 #define TCNT13 3 #define TCNT14 4 #define TCNT15 5 #define TCNT16 6 #define TCNT17 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT18 0 #define TCNT19 1 #define TCNT110 2 #define TCNT111 3 #define TCNT112 4 #define TCNT113 5 #define TCNT114 6 #define TCNT115 7 /* Input Capture Register 1 */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR17 7 #define ICR16 6 #define ICR15 5 #define ICR14 4 #define ICR13 3 #define ICR12 2 #define ICR11 1 #define ICR10 0 #define ICR1H _SFR_MEM8(0x87) #define ICR115 7 #define ICR114 6 #define ICR113 5 #define ICR112 4 #define ICR111 3 #define ICR110 2 #define ICR19 1 #define ICR18 0 /* Output Compare Register 1 A */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1A8 0 #define OCR1A9 1 #define OCR1A10 2 #define OCR1A11 3 #define OCR1A12 4 #define OCR1A13 5 #define OCR1A14 6 #define OCR1A15 7 /* Output Compare Register 1 B */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1B8 0 #define OCR1B9 1 #define OCR1B10 2 #define OCR1B11 3 #define OCR1B12 4 #define OCR1B13 5 #define OCR1B14 6 #define OCR1B15 7 /* PSC0 Interrupt Flag Register */ #define PIFR0 _SFR_MEM8(0xA0) #define PEOP0 0 /* End Of PSC0 Interrupt */ #define PRN00 1 /* PSC0 Ramp Number bit0 */ #define PRN01 2 /* PSC0 Ramp Number bit1 */ #define PEV0A 3 /* PSC0 External Event A Interrupt */ #define PEV0B 4 /* PSC0 External Event B Interrupt */ #define PSEI0 5 /* PSC0 Synchro Error Interrupt */ #define POAC0A 6 /* PSC0 Output A Activity */ #define POAC0B 7 /* PSC0 Output B Activity */ /* PSC0 Interrupt Mask Register */ #define PIM0 _SFR_MEM8(0xA1) #define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ #define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ #define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ #define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ /* PSC1 Interrupt Flag Register */ #define PIFR1 _SFR_MEM8(0xA2) /* PSC1 Interrupt Mask Register */ #define PIM1 _SFR_MEM8(0xA3) /* PSC2 Interrupt Flag Register */ #define PIFR2 _SFR_MEM8(0xA4) #define PEOP2 0 /* End Of PSC2 Interrupt */ #define PRN20 1 /* PSC2 Ramp Number bit0 */ #define PRN21 2 /* PSC2 Ramp Number bit1 */ #define PEV2A 3 /* PSC2 External Event A Interrupt */ #define PEV2B 4 /* PSC2 External Event B Interrupt */ #define PSEI2 5 /* PSC2 Synchro Error Interrupt */ #define POAC2A 6 /* PSC2 Output A Activity */ #define POAC2B 7 /* PSC2 Output B Activity */ /* PSC2 Interrupt Mask Register */ #define PIM2 _SFR_MEM8(0xA5) #define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ #define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ #define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ #define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ /* Digital to Analog Conversion Control Register */ #define DACON _SFR_MEM8(0xAA) #define DAEN 0 /* Digital to Analog Enable bit */ #define DAOE 1 /* Digital to Analog Output Enable bit */ #define DALA 2 /* Digital to Analog Left Adjust */ #define DATS0 4 /* DAC Trigger Selection bit0 */ #define DATS1 5 /* DAC Trigger Selection bit1 */ #define DATS2 6 /* DAC Trigger Selection bit2 */ #define DAATE 7 /* DAC Auto Trigger Enable bit */ /* Digital to Analog Converter input Register */ #define DAC _SFR_MEM16(0xAB) #define DACL _SFR_MEM8(0xAB) #define DACH _SFR_MEM8(0xAC) /* Analog Comparator 0 Control Register */ #define AC0CON _SFR_MEM8(0xAD) #define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ #define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ #define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ #define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ #define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ #define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ #define AC0EN 7 /* Analog Comparator 0 Enable Bit */ /* Analog Comparator 1 Control Register */ #define AC1CON _SFR_MEM8(0xAE) #define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */ #define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */ #define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */ #define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */ #define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */ #define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */ #define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */ #define AC1EN 7 /* Analog Comparator 1 Enable Bit */ /* Analog Comparator 2 Control Register */ #define AC2CON _SFR_MEM8(0xAF) #define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ #define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ #define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ #define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ #define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ #define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ #define AC2EN 7 /* Analog Comparator 2 Enable Bit */ /* USART Control and Status Register A */ #define UCSRA _SFR_MEM8(0xC0) #define MPCM 0 /* Multi-processor Communication Mode */ #define U2X 1 /* Double the USART Transmission Speed */ #define UPE 2 /* USART Parity Error */ #define DOR 3 /* Data OverRun */ #define FE 4 /* Frame Error */ #define UDRE 5 /* USART Data Register Empty */ #define TXC 6 /* USART Transmit Complete */ #define RXC 7 /* USART Receive Complete */ /* USART Control and Status Register B */ #define UCSRB _SFR_MEM8(0xC1) #define TXB8 0 /* Transmit Data Bit 8 */ #define RXB8 1 /* Receive Data Bit 8 */ #define UCSZ2 2 /* Character Size */ #define TXEN 3 /* Transmitter Enable */ #define RXEN 4 /* Receiver Enable */ #define UDRIE 5 /* USART Data Register Empty Interrupt Enable */ #define TXCIE 6 /* TX Complete Interrupt Enable */ #define RXCIE 7 /* RX Complete Interrupt Enable */ /* USART Control and Status Register C */ #define UCSRC _SFR_MEM8(0xC2) #define UCPOL 0 /* Clock Polarity */ #define UCSZ0 1 /* Character Size bit0 */ #define UCSZ1 2 /* Character Size bit1 */ #define USBS 3 /* Stop Bit Select */ #define UPM0 4 /* Parity Mode bit0 */ #define UPM1 5 /* Parity Mode bit1 */ #define UMSEL 6 /* USART Mode Select */ /* USART Baud Rate Register */ #define UBRR _SFR_MEM16(0xC4) #define UBRRL _SFR_MEM8(0xC4) #define UBRRH _SFR_MEM8(0xC5) /* USART I/O Data Register */ #define UDR _SFR_MEM8(0xC6) /* EUSART Control and Status Register A */ #define EUCSRA _SFR_MEM8(0xC8) #define URxS0 0 /* EUSART Receive Character Size bit0 */ #define URxS1 1 /* EUSART Receive Character Size bit1 */ #define URxS2 2 /* EUSART Receive Character Size bit2 */ #define URxS3 3 /* EUSART Receive Character Size bit3 */ #define UTxS0 4 /* EUSART Transmit Character Size bit0 */ #define UTxS1 5 /* EUSART Transmit Character Size bit1 */ #define UTxS2 6 /* EUSART Transmit Character Size bit2 */ #define UTxS3 7 /* EUSART Transmit Character Size bit3 */ /* EUSART Control and Status Register B */ #define EUCSRB _SFR_MEM8(0xC9) #define BODR 0 /* Bit Order */ #define EMCH 1 /* Manchester mode */ #define EUSBS 3 /* EUSBS Enable Bit */ #define EUSART 4 /* EUSART Enable Bit */ /* EUSART Control and Status Register C */ #define EUCSRC _SFR_MEM8(0xCA) #define STP0 0 /* Stop bits values bit0 */ #define STP1 1 /* Stop bits values bit1 */ #define F1617 2 #define FEM 3 /* Frame Error Manchester */ /* Manchester receiver Baud Rate Registers */ #define MUBRR _SFR_MEM16(0xCC) #define MUBRRL _SFR_MEM8(0xCC) #define MUBRRH _SFR_MEM8(0xCD) /* EUSART I/O Data Register */ #define EUDR _SFR_MEM8(0xCE) /* PSC 0 Synchro and Output Configuration */ #define PSOC0 _SFR_MEM8(0xD0) #define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ #define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ #define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ #define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ /* Output Compare SA Registers */ #define OCR0SA _SFR_MEM16(0xD2) #define OCR0SAL _SFR_MEM8(0xD2) #define OCR0SAH _SFR_MEM8(0xD3) /* Output Compare RA Registers */ #define OCR0RA _SFR_MEM16(0xD4) #define OCR0RAL _SFR_MEM8(0xD4) #define OCR0RAH _SFR_MEM8(0xD5) /* Output Compare SB Registers */ #define OCR0SB _SFR_MEM16(0xD6) #define OCR0SBL _SFR_MEM8(0xD6) #define OCR0SBH _SFR_MEM8(0xD7) /* Output Compare RB Registers */ #define OCR0RB _SFR_MEM16(0xD8) #define OCR0RBL _SFR_MEM8(0xD8) #define OCR0RBH _SFR_MEM8(0xD9) /* PSC 0 Configuration Register */ #define PCNF0 _SFR_MEM8(0xDA) #define PCLKSEL0 1 /* PSC 0 Input Clock Select */ #define POP0 2 /* PSC 0 Output Polarity */ #define PMODE00 3 /* PSC 0 Mode bit0 */ #define PMODE01 4 /* PSC 0 Mode bit1 */ #define PLOCK0 5 /* PSC 0 Lock */ #define PALOCK0 6 /* PSC 0 Autolock */ #define PFIFTY0 7 /* PSC 0 Fifty */ /* PSC 0 Control Register */ #define PCTL0 _SFR_MEM8(0xDB) #define PRUN0 0 /* PSC 0 Run */ #define PCCYC0 1 /* PSC 0 Complete Cycle */ #define PARUN0 2 /* PSC 0 Autorun */ #define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ #define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ #define PBFM0 5 /* Balance Flank Width Modulation */ #define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ #define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ /* PSC 0 Input A Control Register */ #define PFRC0A _SFR_MEM8(0xDC) #define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ #define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ #define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ #define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ #define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ #define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ #define PISEL0A 6 /* PSC 0 Input Select for Part A */ #define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ /* PSC 0 Input B Control Register */ #define PFRC0B _SFR_MEM8(0xDD) #define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ #define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ #define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ #define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ #define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ #define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ #define PISEL0B 6 /* PSC 0 Input Select for Part B */ #define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ /* PSC 0 Input Capture Registers */ #define PICR0 _SFR_MEM16(0xDE) #define PICR0L _SFR_MEM8(0xDE) #define PICR0H _SFR_MEM8(0xDF) #define PCST0 7 /* PSC Capture Software Trig bit */ /* PSC 1 Synchro and Output Configuration */ #define PSOC1 _SFR_MEM8(0xE0) /* Output Compare SA Registers */ #define OCR1SA _SFR_MEM16(0xE2) #define OCR1SAL _SFR_MEM8(0xE2) #define OCR1SAH _SFR_MEM8(0xE3) /* Output Compare RA Registers */ #define OCR1RA _SFR_MEM16(0xE4) #define OCR1RAL _SFR_MEM8(0xE4) #define OCR1RAH _SFR_MEM8(0xE5) /* Output Compare SB Registers */ #define OCR1SB _SFR_MEM16(0xE6) #define OCR1SBL _SFR_MEM8(0xE6) #define OCR1SBH _SFR_MEM8(0xE7) /* Output Compare RB Registers */ #define OCR1RB _SFR_MEM16(0xE8) #define OCR1RBL _SFR_MEM8(0xE8) #define OCR1RBH _SFR_MEM8(0xE9) /* PSC 1 Configuration Register */ #define PCNF1 _SFR_MEM8(0xEA) /* PSC 1 Control Register */ #define PCTL1 _SFR_MEM8(0xEB) /* PSC 1 Input A Control Register */ #define PFRC1A _SFR_MEM8(0xEC) /* PSC 1 Input B Control Register */ #define PFRC1B _SFR_MEM8(0xED) /* PSC 1 Input Capture Registers */ #define PICR1 _SFR_MEM16(0xEE) #define PICR1L _SFR_MEM8(0xEE) #define PICR1H _SFR_MEM8(0xEF) /* PSC 2 Synchro and Output Configuration */ #define PSOC2 _SFR_MEM8(0xF0) #define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ #define POEN2C 1 /* PSCOUT22 Output Enable */ #define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ #define POEN2D 3 /* PSCOUT23 Output Enable */ #define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ #define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ #define POS22 6 /* PSCOUT22 Selection */ #define POS23 7 /* PSCOUT23 Selection */ /* PSC 2 Output Matrix */ #define POM2 _SFR_MEM8(0xF1) #define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ #define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ #define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ #define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ #define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ #define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ #define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ #define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ /* Output Compare SA Registers */ #define OCR2SA _SFR_MEM16(0xF2) #define OCR2SAL _SFR_MEM8(0xF2) #define OCR2SAH _SFR_MEM8(0xF3) /* Output Compare RA Registers */ #define OCR2RA _SFR_MEM16(0xF4) #define OCR2RAL _SFR_MEM8(0xF4) #define OCR2RAH _SFR_MEM8(0xF5) /* Output Compare SB Registers */ #define OCR2SB _SFR_MEM16(0xF6) #define OCR2SBL _SFR_MEM8(0xF6) #define OCR2SBH _SFR_MEM8(0xF7) /* Output Compare RB Registers */ #define OCR2RB _SFR_MEM16(0xF8) #define OCR2RBL _SFR_MEM8(0xF8) #define OCR2RBH _SFR_MEM8(0xF9) /* PSC 2 Configuration Register */ #define PCNF2 _SFR_MEM8(0xFA) #define POME2 0 /* PSC 2 Output Matrix Enable */ #define PCLKSEL2 1 /* PSC 2 Input Clock Select */ #define POP2 2 /* PSC 2 Output Polarity */ #define PMODE20 3 /* PSC 2 Mode bit0 */ #define PMODE21 4 /* PSC 2 Mode bit1 */ #define PLOCK2 5 /* PSC 2 Lock */ #define PALOCK2 6 /* PSC 2 Autolock */ #define PFIFTY2 7 /* PSC 2 Fifty */ /* PSC 2 Control Register */ #define PCTL2 _SFR_MEM8(0xFB) #define PRUN2 0 /* PSC 2 Run */ #define PCCYC2 1 /* PSC 2 Complete Cycle */ #define PARUN2 2 /* PSC 2 Autorun */ #define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ #define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ #define PBFM2 5 /* Balance Flank Width Modulation */ #define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ #define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ /* PSC 2 Input A Control Register */ #define PFRC2A _SFR_MEM8(0xFC) #define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ #define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ #define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ #define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ #define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ #define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ #define PISEL2A 6 /* PSC 2 Input Select for Part A */ #define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ /* PSC 2 Input B Control Register */ #define PFRC2B _SFR_MEM8(0xFD) #define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ #define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ #define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ #define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ #define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ #define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ #define PISEL2B 6 /* PSC 2 Input Select for Part B */ #define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ /* PSC 2 Input Capture Registers */ #define PICR2 _SFR_MEM16(0xFE) #define PICR2L _SFR_MEM8(0xFE) #define PICR2H _SFR_MEM8(0xFF) #define PCST2 7 /* PSC Capture Software Trig bit */ /* Interrupt Vectors */ /* Interrupt 0 is the reset vector. */ /* PSC2 Capture Event */ #define PSC2_CAPT_vect_num 1 #define PSC2_CAPT_vect _VECTOR(1) /* PSC2 End Cycle */ #define PSC2_EC_vect_num 2 #define PSC2_EC_vect _VECTOR(2) /* PSC1 Capture Event */ #define PSC1_CAPT_vect_num 3 #define PSC1_CAPT_vect _VECTOR(3) /* PSC1 End Cycle */ #define PSC1_EC_vect_num 4 #define PSC1_EC_vect _VECTOR(4) /* PSC0 Capture Event */ #define PSC0_CAPT_vect_num 5 #define PSC0_CAPT_vect _VECTOR(5) /* PSC0 End Cycle */ #define PSC0_EC_vect_num 6 #define PSC0_EC_vect _VECTOR(6) /* Analog Comparator 0 */ #define ANALOG_COMP_0_vect_num 7 #define ANALOG_COMP_0_vect _VECTOR(7) /* Analog Comparator 1 */ #define ANALOG_COMP_1_vect_num 8 #define ANALOG_COMP_1_vect _VECTOR(8) /* Analog Comparator 2 */ #define ANALOG_COMP_2_vect_num 9 #define ANALOG_COMP_2_vect _VECTOR(9) /* External Interrupt Request 0 */ #define INT0_vect_num 10 #define INT0_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 11 #define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 12 #define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 13 #define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMP_A_vect_num 16 #define TIMER0_COMP_A_vect _VECTOR(16) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 17 #define TIMER0_OVF_vect _VECTOR(17) /* ADC Conversion Complete */ #define ADC_vect_num 18 #define ADC_vect _VECTOR(18) /* External Interrupt Request 1 */ #define INT1_vect_num 19 #define INT1_vect _VECTOR(19) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 20 #define SPI_STC_vect _VECTOR(20) /* USART, Rx Complete */ #define USART_RX_vect_num 21 #define USART_RX_vect _VECTOR(21) /* USART Data Register Empty */ #define USART_UDRE_vect_num 22 #define USART_UDRE_vect _VECTOR(22) /* USART, Tx Complete */ #define USART_TX_vect_num 23 #define USART_TX_vect _VECTOR(23) /* External Interrupt Request 2 */ #define INT2_vect_num 24 #define INT2_vect _VECTOR(24) /* Watchdog Timeout Interrupt */ #define WDT_vect_num 25 #define WDT_vect _VECTOR(25) /* EEPROM Ready */ #define EE_READY_vect_num 26 #define EE_READY_vect _VECTOR(26) /* Timer Counter 0 Compare Match B */ #define TIMER0_COMPB_vect_num 27 #define TIMER0_COMPB_vect _VECTOR(27) /* External Interrupt Request 3 */ #define INT3_vect_num 28 #define INT3_vect _VECTOR(28) /* Store Program Memory Read */ #define SPM_READY_vect_num 31 #define SPM_READY_vect _VECTOR(31) #define _VECTORS_SIZE (4 * 32) /* Constants */ #define RAMEND 0x4FF #define XRAMSIZE 0 #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x3FFF #define SPM_PAGESIZE 128 /* Fuse Information */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_PSCRV (unsigned char)~_BV(4) #define FUSE_PSC0RB (unsigned char)~_BV(5) #define FUSE_PSC1RB (unsigned char)~_BV(6) #define FUSE_PSC2RB (unsigned char)~_BV(7) #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x83 #endif /* _AVR_IO90PWM216_H_ */ avr-libc-1.8.0.orig/include/avr/iotn261a.h0000644000000000000000000005054311732702554015010 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn261a.h 2063 2009-11-18 22:06:28Z arcanum $ */ /* avr/iotn261a.h - definitions for ATtiny261A */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn261a.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny261A_H_ #define _AVR_ATtiny261A_H_ 1 /* Registers and associated bit numbers. */ #define TCCR1E _SFR_IO8(0x00) #define OC1OE0 0 #define OC1OE1 1 #define OC1OE2 2 #define OC1OE3 3 #define OC1OE4 4 #define OC1OE5 5 #define DIDR0 _SFR_IO8(0x01) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define AREFD 3 #define ADC3D 4 #define ADC4D 5 #define ADC5D 6 #define ADC6D 7 #define DIDR1 _SFR_IO8(0x02) #define ADC7D 4 #define ADC8D 5 #define ADC9D 6 #define ADC10D 7 #define ADCSRB _SFR_IO8(0x03) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define MUX5 3 #define REFS2 4 #define IPR 5 #define GSEL 6 #define BIN 7 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x05) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define ACSRA _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACME 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define ACSRB _SFR_IO8(0x09) #define ACM0 0 #define ACM1 1 #define ACM2 2 #define HLEV 6 #define HSEL 7 #define GPIOR0 _SFR_IO8(0x0A) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x0B) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x0C) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define USICR _SFR_IO8(0x0D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x0E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x0F) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define USIBR _SFR_IO8(0x10) #define USIBR0 0 #define USIBR1 1 #define USIBR2 2 #define USIBR3 3 #define USIBR4 4 #define USIBR5 5 #define USIBR6 6 #define USIBR7 7 #define USIPP _SFR_IO8(0x11) #define USIPOS 0 #define OCR0B _SFR_IO8(0x12) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define OCR0A _SFR_IO8(0x13) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define TCNT0H _SFR_IO8(0x14) #define TCNT0H_0 0 #define TCNT0H_1 1 #define TCNT0H_2 2 #define TCNT0H_3 3 #define TCNT0H_4 4 #define TCNT0H_5 5 #define TCNT0H_6 6 #define TCNT0H_7 7 #define TCCR0A _SFR_IO8(0x15) #define WGM00 0 #define ACIC0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x1D) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x1F) #define EEAR8 0 #define DWDR _SFR_IO8(0x20) #define DWDR0 0 #define DWDR1 1 #define DWDR2 2 #define DWDR3 3 #define DWDR4 4 #define DWDR5 5 #define DWDR6 6 #define DWDR7 7 #define WDTCR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define PCMSK1 _SFR_IO8(0x22) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 #define PCMSK0 _SFR_IO8(0x23) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define DT1 _SFR_IO8(0x24) #define DT1L0 0 #define DT1L1 1 #define DT1L2 2 #define DT1L3 3 #define DT1H0 4 #define DT1H1 5 #define DT1H2 6 #define DT1H3 7 #define TC1H _SFR_IO8(0x25) #define TC18 0 #define TC19 1 #define TCCR1D _SFR_IO8(0x26) #define WGM10 0 #define WGM11 1 #define FPF1 2 #define FPAC1 3 #define FPES1 4 #define FPNC1 5 #define FPEN1 6 #define FPIE1 7 #define TCCR1C _SFR_IO8(0x27) #define PWM1D 0 #define FOC1D 1 #define COM1D0 2 #define COM1D1 3 #define COM1B0S 4 #define COM1B1S 5 #define COM1A0S 6 #define COM1A1S 7 #define CLKPR _SFR_IO8(0x28) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PCKE 2 #define LSM 7 #define OCR1D _SFR_IO8(0x2A) #define OCR1D0 0 #define OCR1D1 1 #define OCR1D2 2 #define OCR1D3 3 #define OCR1D4 4 #define OCR1D5 5 #define OCR1D6 6 #define OCR1D7 7 #define OCR1C _SFR_IO8(0x2B) #define OCR1C0 0 #define OCR1C1 1 #define OCR1C2 2 #define OCR1C3 3 #define OCR1C4 4 #define OCR1C5 5 #define OCR1C6 6 #define OCR1C7 7 #define OCR1B _SFR_IO8(0x2C) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define OCR1A _SFR_IO8(0x2D) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define TCNT1 _SFR_IO8(0x2E) #define TC1H_0 0 #define TC1H_1 1 #define TC1H_2 2 #define TC1H_3 3 #define TC1H_4 4 #define TC1H_5 5 #define TC1H_6 6 #define TC1H_7 7 #define TCCR1B _SFR_IO8(0x2F) #define CS10 0 #define CS11 1 #define CS12 2 #define CS13 3 #define DTPS10 4 #define DTPS11 5 #define PSR1 6 #define TCCR1A _SFR_IO8(0x30) #define PWM1B 0 #define PWM1A 1 #define FOC1B 2 #define FOC1A 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define OSCCAL _SFR_IO8(0x31) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define TCNT0L _SFR_IO8(0x32) #define TCNT0L_0 0 #define TCNT0L_1 1 #define TCNT0L_2 2 #define TCNT0L_3 3 #define TCNT0L_4 4 #define TCNT0L_5 5 #define TCNT0L_6 6 #define TCNT0L_7 7 #define TCCR0B _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define PSR0 3 #define TSM 4 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define BODSE 2 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 #define BODS 7 #define PRR _SFR_IO8(0x36) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR _SFR_IO8(0x38) #define ICF0 0 #define TOV0 1 #define TOV1 2 #define OCF0B 3 #define OCF0A 4 #define OCF1B 5 #define OCF1A 6 #define OCF1D 7 #define TIMSK _SFR_IO8(0x39) #define TICIE0 0 #define TOIE0 1 #define TOIE1 2 #define OCIE0B 3 #define OCIE0A 4 #define OCIE1B 5 #define OCIE1A 6 #define OCIE1D 7 #define GIFR _SFR_IO8(0x3A) #define PCIF 5 #define INTF0 6 #define INTF1 7 #define GIMSK _SFR_IO8(0x3B) #define PCIE0 4 #define PCIE1 5 #define INT0 6 #define INT1 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt 0 */ #define PCINT_vect_num 2 #define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ #define TIMER1_COMPA_vect_num 3 #define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ #define TIMER1_COMPB_vect_num 4 #define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ #define TIMER1_OVF_vect_num 5 #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ #define TIMER0_OVF_vect_num 6 #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ #define USI_START_vect_num 7 #define USI_START_vect _VECTOR(7) /* USI Start */ #define USI_OVF_vect_num 8 #define USI_OVF_vect _VECTOR(8) /* USI Overflow */ #define EE_RDY_vect_num 9 #define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ #define ANA_COMP_vect_num 10 #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ #define ADC_vect_num 11 #define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ #define INT1_vect_num 13 #define INT1_vect _VECTOR(13) /* External Interrupt 1 */ #define TIMER0_COMPA_vect_num 14 #define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 15 #define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ #define TIMER0_CAPT_vect_num 16 #define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ #define TIMER1_COMPD_vect_num 17 #define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ #define FAULT_PROTECTION_vect_num 18 #define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (19 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (32) #define RAMSTART (0x60) #define RAMSIZE (128) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x7F) #define E2PAGESIZE (4) #define FLASHEND (0x7FF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x0C /* Device Pin Definitions */ #define DI_B_DDR DDRMOSI #define DI_B_PORT PORTMOSI #define DI_B_PIN PINMOSI #define DI_B_BIT MOSI #define SDA_B_DDR DDRMOSI #define SDA_B_PORT PORTMOSI #define SDA_B_PIN PINMOSI #define SDA_B_BIT MOSI #define _OC1A_DDR DDRMOSI #define _OC1A_PORT PORTMOSI #define _OC1A_PIN PINMOSI #define _OC1A_BIT MOSI #define PCINT8_DDR DDRMOSI #define PCINT8_PORT PORTMOSI #define PCINT8_PIN PINMOSI #define PCINT8_BIT MOSI #define PB0_DDR DDRMOSI #define PB0_PORT PORTMOSI #define PB0_PIN PINMOSI #define PB0_BIT MOSI #define DO_B_DDR DDRMISO #define DO_B_PORT PORTMISO #define DO_B_PIN PINMISO #define DO_B_BIT MISO #define OC1A_DDR DDRMISO #define OC1A_PORT PORTMISO #define OC1A_PIN PINMISO #define OC1A_BIT MISO #define PCINT9_DDR DDRMISO #define PCINT9_PORT PORTMISO #define PCINT9_PIN PINMISO #define PCINT9_BIT MISO #define PB1_DDR DDRMISO #define PB1_PORT PORTMISO #define PB1_PIN PINMISO #define PB1_BIT MISO #define USCK_B_DDR DDRSCK #define USCK_B_PORT PORTSCK #define USCK_B_PIN PINSCK #define USCK_B_BIT SCK #define SCL_B_DDR DDRSCK #define SCL_B_PORT PORTSCK #define SCL_B_PIN PINSCK #define SCL_B_BIT SCK #define OC1B_DDR DDRSCK #define OC1B_PORT PORTSCK #define OC1B_PIN PINSCK #define OC1B_BIT SCK #define PCINT10_DDR DDRSCK #define PCINT10_PORT PORTSCK #define PCINT10_PIN PINSCK #define PCINT10_BIT SCK #define PB2_DDR DDRSCK #define PB2_PORT PORTSCK #define PB2_PIN PINSCK #define PB2_BIT SCK #define PCINT11_DDR DDROC1B #define PCINT11_PORT PORTOC1B #define PCINT11_PIN PINOC1B #define PCINT11_BIT OC1B #define PB3_DDR DDROC1B #define PB3_PORT PORTOC1B #define PB3_PIN PINOC1B #define PB3_BIT OC1B #define PCINT12_DDR DDRADC #define PCINT12_PORT PORTADC #define PCINT12_PIN PINADC #define PCINT12_BIT ADC7 #define _OC1D_DDR DDRADC #define _OC1D_PORT PORTADC #define _OC1D_PIN PINADC #define _OC1D_BIT ADC7 #define CLKI_DDR DDRADC #define CLKI_PORT PORTADC #define CLKI_PIN PINADC #define CLKI_BIT ADC7 #define PB4_DDR DDRADC #define PB4_PORT PORTADC #define PB4_PIN PINADC #define PB4_BIT ADC7 #define PCINT13_DDR DDRADC #define PCINT13_PORT PORTADC #define PCINT13_PIN PINADC #define PCINT13_BIT ADC8 #define OC1D_DDR DDRADC #define OC1D_PORT PORTADC #define OC1D_PIN PINADC #define OC1D_BIT ADC8 #define CKLO_DDR DDRADC #define CKLO_PORT PORTADC #define CKLO_PIN PINADC #define CKLO_BIT ADC8 #define PB5_DDR DDRADC #define PB5_PORT PORTADC #define PB5_PIN PINADC #define PB5_BIT ADC8 #define INT0_DDR DDRADC #define INT0_PORT PORTADC #define INT0_PIN PINADC #define INT0_BIT ADC9 #define T0_DDR DDRADC #define T0_PORT PORTADC #define T0_PIN PINADC #define T0_BIT ADC9 #define PCINT14_DDR DDRADC #define PCINT14_PORT PORTADC #define PCINT14_PIN PINADC #define PCINT14_BIT ADC9 #define PB6_DDR DDRADC #define PB6_PORT PORTADC #define PB6_PIN PINADC #define PB6_BIT ADC9 #define PCINT15_DDR DDRADC1 #define PCINT15_PORT PORTADC1 #define PCINT15_PIN PINADC1 #define PCINT15_BIT ADC10 #define PB7_DDR DDRADC1 #define PB7_PORT PORTADC1 #define PB7_PIN PINADC1 #define PB7_BIT ADC10 #define AIN1_DDR DDRADC #define AIN1_PORT PORTADC #define AIN1_PIN PINADC #define AIN1_BIT ADC6 #define PCINT7_DDR DDRADC #define PCINT7_PORT PORTADC #define PCINT7_PIN PINADC #define PCINT7_BIT ADC6 #define PA7_DDR DDRADC #define PA7_PORT PORTADC #define PA7_PIN PINADC #define PA7_BIT ADC6 #define AIN0_DDR DDRADC #define AIN0_PORT PORTADC #define AIN0_PIN PINADC #define AIN0_BIT ADC5 #define PCINT6_DDR DDRADC #define PCINT6_PORT PORTADC #define PCINT6_PIN PINADC #define PCINT6_BIT ADC5 #define PA6_DDR DDRADC #define PA6_PORT PORTADC #define PA6_PIN PINADC #define PA6_BIT ADC5 #define AIN2_DDR DDRADC #define AIN2_PORT PORTADC #define AIN2_PIN PINADC #define AIN2_BIT ADC4 #define PCINT5_DDR DDRADC #define PCINT5_PORT PORTADC #define PCINT5_PIN PINADC #define PCINT5_BIT ADC4 #define PA5_DDR DDRADC #define PA5_PORT PORTADC #define PA5_PIN PINADC #define PA5_BIT ADC4 #define ICP0_DDR DDRADC #define ICP0_PORT PORTADC #define ICP0_PIN PINADC #define ICP0_BIT ADC3 #define PCINT4_DDR DDRADC #define PCINT4_PORT PORTADC #define PCINT4_PIN PINADC #define PCINT4_BIT ADC3 #define PA4_DDR DDRADC #define PA4_PORT PORTADC #define PA4_PIN PINADC #define PA4_BIT ADC3 #define PCINT3_DDR DDRAREF #define PCINT3_PORT PORTAREF #define PCINT3_PIN PINAREF #define PCINT3_BIT AREF #define PA3_DDR DDRAREF #define PA3_PORT PORTAREF #define PA3_PIN PINAREF #define PA3_BIT AREF #define INT1_DDR DDRADC #define INT1_PORT PORTADC #define INT1_PIN PINADC #define INT1_BIT ADC2 #define USCK_A_DDR DDRADC #define USCK_A_PORT PORTADC #define USCK_A_PIN PINADC #define USCK_A_BIT ADC2 #define SCL_A_DDR DDRADC #define SCL_A_PORT PORTADC #define SCL_A_PIN PINADC #define SCL_A_BIT ADC2 #define PCINT2_DDR DDRADC #define PCINT2_PORT PORTADC #define PCINT2_PIN PINADC #define PCINT2_BIT ADC2 #define PA2_DDR DDRADC #define PA2_PORT PORTADC #define PA2_PIN PINADC #define PA2_BIT ADC2 #define DO_A_DDR DDRADC #define DO_A_PORT PORTADC #define DO_A_PIN PINADC #define DO_A_BIT ADC1 #define PCINT1_DDR DDRADC #define PCINT1_PORT PORTADC #define PCINT1_PIN PINADC #define PCINT1_BIT ADC1 #define PA1_DDR DDRADC #define PA1_PORT PORTADC #define PA1_PIN PINADC #define PA1_BIT ADC1 #define DI_A_DDR DDRADC #define DI_A_PORT PORTADC #define DI_A_PIN PINADC #define DI_A_BIT ADC0 #define SDA_A_DDR DDRADC #define SDA_A_PORT PORTADC #define SDA_A_PIN PINADC #define SDA_A_BIT ADC0 #define PCINT0_DDR DDRADC #define PCINT0_PORT PORTADC #define PCINT0_PIN PINADC #define PCINT0_BIT ADC0 #define PA0_DDR DDRADC #define PA0_PORT PORTADC #define PA0_PIN PINADC #define PA0_BIT ADC0 #endif /* _AVR_ATtiny261A_H_ */ avr-libc-1.8.0.orig/include/avr/iom32u4.h0000644000000000000000000007330711732702554014652 0ustar /* Copyright (c) 2008 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom32u4.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iom32u4.h - definitions for ATmega32U4. */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32u4.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOM32U4_H_ #define _AVR_IOM32U4_H_ 1 /* Registers and associated bit numbers */ #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE2 2 #define PINE6 6 #define DDRE _SFR_IO8(0x0D) #define DDE2 2 #define DDE6 6 #define PORTE _SFR_IO8(0x0E) #define PORTE2 2 #define PORTE6 6 #define PINF _SFR_IO8(0x0F) #define PINF0 0 #define PINF1 1 #define PINF4 4 #define PINF5 5 #define PINF6 6 #define PINF7 7 #define DDRF _SFR_IO8(0x10) #define DDF0 0 #define DDF1 1 #define DDF4 4 #define DDF5 5 #define DDF6 6 #define DDF7 7 #define PORTF _SFR_IO8(0x11) #define PORTF0 0 #define PORTF1 1 #define PORTF4 4 #define PORTF5 5 #define PORTF6 6 #define PORTF7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define OCF1C 3 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define TIFR3 _SFR_IO8(0x18) #define TOV3 0 #define OCF3A 1 #define OCF3B 2 #define OCF3C 3 #define ICF3 5 #define TIFR4 _SFR_IO8(0x19) #define TOV4 2 #define OCF4B 5 #define OCF4A 6 #define OCF4D 7 #define TIFR5 _SFR_IO8(0x1A) #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define INTF4 4 #define INTF5 5 #define INTF6 6 #define INTF7 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define INT4 4 #define INT5 5 #define INT6 6 #define INT7 7 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PINDIV 4 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define PLLFRQ _SFR_IO8(0x32) #define PDIV0 0 #define PDIV1 1 #define PDIV2 2 #define PDIV3 3 #define PLLTM0 4 #define PLLTM1 5 #define PLLUSB 6 #define PINMUX 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define RAMPZ _SFR_IO8(0x3B) #define RAMPZ0 0 #define EIND _SFR_IO8(0x3C) #define EIND0 0 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define PRR1 _SFR_MEM8(0x65) #define PRUSART1 0 #define PRTIM3 3 #define PRUSB 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define RCCTRL _SFR_MEM8(0x67) #define RCFREQ 0 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define EICRB _SFR_MEM8(0x6A) #define ISC40 0 #define ISC41 1 #define ISC50 2 #define ISC51 3 #define ISC60 4 #define ISC61 5 #define ISC70 6 #define ISC71 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCMSK2 _SFR_MEM8(0x6D) #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define OCIE1C 3 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #define TIMSK3 _SFR_MEM8(0x71) #define TOIE3 0 #define OCIE3A 1 #define OCIE3B 2 #define OCIE3C 3 #define ICIE3 5 #define TIMSK4 _SFR_MEM8(0x72) #define TOIE4 2 #define OCIE4B 5 #define OCIE4A 6 #define OCIE4D 7 #define TIMSK5 _SFR_MEM8(0x73) #ifndef _ASSEMBLER_ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADTS3 3 #define MUX5 5 #define ACME 6 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR2 _SFR_MEM8(0x7D) #define ADC8D 0 #define ADC9D 1 #define ADC10D 2 #define ADC11D 3 #define ADC12D 4 #define ADC13D 5 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1C0 2 #define COM1C1 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1C 5 #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CL0 0 #define OCR1CL1 1 #define OCR1CL2 2 #define OCR1CL3 3 #define OCR1CL4 4 #define OCR1CL5 5 #define OCR1CL6 6 #define OCR1CL7 7 #define OCR1CH _SFR_MEM8(0x8D) #define OCR1CH0 0 #define OCR1CH1 1 #define OCR1CH2 2 #define OCR1CH3 3 #define OCR1CH4 4 #define OCR1CH5 5 #define OCR1CH6 6 #define OCR1CH7 7 #define TCCR3A _SFR_MEM8(0x90) #define WGM30 0 #define WGM31 1 #define COM3C0 2 #define COM3C1 3 #define COM3B0 4 #define COM3B1 5 #define COM3A0 6 #define COM3A1 7 #define TCCR3B _SFR_MEM8(0x91) #define CS30 0 #define CS31 1 #define CS32 2 #define WGM32 3 #define WGM33 4 #define ICES3 6 #define ICNC3 7 #define TCCR3C _SFR_MEM8(0x92) #define FOC3C 5 #define FOC3B 6 #define FOC3A 7 #define TCNT3 _SFR_MEM16(0x94) #define TCNT3L _SFR_MEM8(0x94) #define TCNT3L0 0 #define TCNT3L1 1 #define TCNT3L2 2 #define TCNT3L3 3 #define TCNT3L4 4 #define TCNT3L5 5 #define TCNT3L6 6 #define TCNT3L7 7 #define TCNT3H _SFR_MEM8(0x95) #define TCNT3H0 0 #define TCNT3H1 1 #define TCNT3H2 2 #define TCNT3H3 3 #define TCNT3H4 4 #define TCNT3H5 5 #define TCNT3H6 6 #define TCNT3H7 7 #define ICR3 _SFR_MEM16(0x96) #define ICR3L _SFR_MEM8(0x96) #define ICR3L0 0 #define ICR3L1 1 #define ICR3L2 2 #define ICR3L3 3 #define ICR3L4 4 #define ICR3L5 5 #define ICR3L6 6 #define ICR3L7 7 #define ICR3H _SFR_MEM8(0x97) #define ICR3H0 0 #define ICR3H1 1 #define ICR3H2 2 #define ICR3H3 3 #define ICR3H4 4 #define ICR3H5 5 #define ICR3H6 6 #define ICR3H7 7 #define OCR3A _SFR_MEM16(0x98) #define OCR3AL _SFR_MEM8(0x98) #define OCR3AL0 0 #define OCR3AL1 1 #define OCR3AL2 2 #define OCR3AL3 3 #define OCR3AL4 4 #define OCR3AL5 5 #define OCR3AL6 6 #define OCR3AL7 7 #define OCR3AH _SFR_MEM8(0x99) #define OCR3AH0 0 #define OCR3AH1 1 #define OCR3AH2 2 #define OCR3AH3 3 #define OCR3AH4 4 #define OCR3AH5 5 #define OCR3AH6 6 #define OCR3AH7 7 #define OCR3B _SFR_MEM16(0x9A) #define OCR3BL _SFR_MEM8(0x9A) #define OCR3BL0 0 #define OCR3BL1 1 #define OCR3BL2 2 #define OCR3BL3 3 #define OCR3BL4 4 #define OCR3BL5 5 #define OCR3BL6 6 #define OCR3BL7 7 #define OCR3BH _SFR_MEM8(0x9B) #define OCR3BH0 0 #define OCR3BH1 1 #define OCR3BH2 2 #define OCR3BH3 3 #define OCR3BH4 4 #define OCR3BH5 5 #define OCR3BH6 6 #define OCR3BH7 7 #define OCR3C _SFR_MEM16(0x9C) #define OCR3CL _SFR_MEM8(0x9C) #define OCR3CL0 0 #define OCR3CL1 1 #define OCR3CL2 2 #define OCR3CL3 3 #define OCR3CL4 4 #define OCR3CL5 5 #define OCR3CL6 6 #define OCR3CL7 7 #define OCR3CH _SFR_MEM8(0x9D) #define OCR3CH0 0 #define OCR3CH1 1 #define OCR3CH2 2 #define OCR3CH3 3 #define OCR3CH4 4 #define OCR3CH5 5 #define OCR3CH6 6 #define OCR3CH7 7 #define UHCON _SFR_MEM8(0x9E) #define UHINT _SFR_MEM8(0x9F) #define UHIEN _SFR_MEM8(0xA0) #define UHADDR _SFR_MEM8(0xA1) #define UHFNUM _SFR_MEM16(0xA2) #define UHFNUML _SFR_MEM8(0xA2) #define UHFNUMH _SFR_MEM8(0xA3) #define UHFLEN _SFR_MEM8(0xA4) #define UPINRQX _SFR_MEM8(0xA5) #define UPINTX _SFR_MEM8(0xA6) #define UPNUM _SFR_MEM8(0xA7) #define UPRST _SFR_MEM8(0xA8) #define UPCONX _SFR_MEM8(0xA9) #define UPCFG0X _SFR_MEM8(0xAA) #define UPCFG1X _SFR_MEM8(0xAB) #define UPSTAX _SFR_MEM8(0xAC) #define UPCFG2X _SFR_MEM8(0xAD) #define UPIENX _SFR_MEM8(0xAE) #define UPDATX _SFR_MEM8(0xAF) #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2_0 0 #define OCR2_1 1 #define OCR2_2 2 #define OCR2_3 3 #define OCR2_4 4 #define OCR2_5 5 #define OCR2_6 6 #define OCR2_7 7 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define TCNT4 _SFR_MEM16(0xBE) #define TCNT4L _SFR_MEM8(0xBE) #define TC40 0 #define TC41 1 #define TC42 2 #define TC43 3 #define TC44 4 #define TC45 5 #define TC46 6 #define TC47 7 #define TCNT4H _SFR_MEM8(0xBF) /* Alias for naming consistency. */ #define TC4H _SFR_MEM8(0xBF) /* Per XML device file. */ #define TC48 0 #define TC49 1 #define TC410 2 #define TCCR4A _SFR_MEM8(0xC0) #define PWM4B 0 #define PWM4A 1 #define FOC4B 2 #define FOC4A 3 #define COM4B0 4 #define COM4B1 5 #define COM4A0 6 #define COM4A1 7 #define TCCR4B _SFR_MEM8(0xC1) #define CS40 0 #define CS41 1 #define CS42 2 #define CS43 3 #define DTPS40 4 #define DTPS41 5 #define PSR4 6 #define PWM4X 7 #define TCCR4C _SFR_MEM8(0xC2) #define PWM4D 0 #define FOC4D 1 #define COM4D0 2 #define COM4D1 3 #define COM4B0S 4 #define COM4B1S 5 #define COM4A0S 6 #define COM4A1S 7 #define TCCR4D _SFR_MEM8(0xC3) #define WGM40 0 #define WGM41 1 #define FPF4 2 #define FPAC4 3 #define FPES4 4 #define FPNC4 5 #define FPEN4 6 #define FPIE4 7 #define TCCR4E _SFR_MEM8(0xC4) #define OC4OE0 0 #define OC4OE1 1 #define OC4OE2 2 #define OC4OE3 3 #define OC4OE4 4 #define OC4OE5 5 #define ENHC4 6 #define TLOCK4 7 #define CLKSEL0 _SFR_MEM8(0xC5) #define CLKS 0 #define EXTE 2 #define RCE 3 #define EXSUT0 4 #define EXSUT1 5 #define RCSUT0 6 #define RCSUT1 7 #define CLKSEL1 _SFR_MEM8(0xC6) #define EXCKSEL0 0 #define EXCKSEL1 1 #define EXCKSEL2 2 #define EXCKSEL3 3 #define RCCKSEL0 4 #define RCCKSEL1 5 #define RCCKSEL2 6 #define RCCKSEL3 7 #define CLKSTA _SFR_MEM8(0xC7) #define EXTON 0 #define RCON 1 #define UCSR1A _SFR_MEM8(0xC8) #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 #define UCSR1B _SFR_MEM8(0xC9) #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 #define UCSR1C _SFR_MEM8(0xCA) #define UCPOL1 0 #define UCSZ10 1 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR1H _SFR_MEM8(0xCD) #define UDR1 _SFR_MEM8(0xCE) #define UDR1_0 0 #define UDR1_1 1 #define UDR1_2 2 #define UDR1_3 3 #define UDR1_4 4 #define UDR1_5 5 #define UDR1_6 6 #define UDR1_7 7 #define OCR4A _SFR_MEM8(0xCF) #define OCR4A0 0 #define OCR4A1 1 #define OCR4A2 2 #define OCR4A3 3 #define OCR4A4 4 #define OCR4A5 5 #define OCR4A6 6 #define OCR4A7 7 #define OCR4B _SFR_MEM8(0xD0) #define OCR4B0 0 #define OCR4B1 1 #define OCR4B2 2 #define OCR4B3 3 #define OCR4B4 4 #define OCR4B5 5 #define OCR4B6 6 #define OCR4B7 7 #define OCR4C _SFR_MEM8(0xD1) #define OCR4C0 0 #define OCR4C1 1 #define OCR4C2 2 #define OCR4C3 3 #define OCR4C4 4 #define OCR4C5 5 #define OCR4C6 6 #define OCR4C7 7 #define OCR4D _SFR_MEM8(0xD2) #define OCR4D0 0 #define OCR4D1 1 #define OCR4D2 2 #define OCR4D3 3 #define OCR4D4 4 #define OCR4D5 5 #define OCR4D6 6 #define OCR4D7 7 #define DT4 _SFR_MEM8(0xD4) #define DT4L0 0 #define DT4L1 1 #define DT4L2 2 #define DT4L3 3 #define DT4L4 4 #define DT4L5 5 #define DT4L6 6 #define DT4L7 7 #define UHWCON _SFR_MEM8(0xD7) #define UVREGE 0 #define USBCON _SFR_MEM8(0xD8) #define VBUSTE 0 #define OTGPADE 4 #define FRZCLK 5 #define USBE 7 #define USBSTA _SFR_MEM8(0xD9) #define VBUS 0 #define SPEED 3 #define USBINT _SFR_MEM8(0xDA) #define VBUSTI 0 #define OTGCON _SFR_MEM8(0xDD) #define OTGIEN _SFR_MEM8(0xDE) #define OTGINT _SFR_MEM8(0xDF) #define UDCON _SFR_MEM8(0xE0) #define DETACH 0 #define RMWKUP 1 #define LSM 2 #define RSTCPU 3 #define UDINT _SFR_MEM8(0xE1) #define SUSPI 0 #define SOFI 2 #define EORSTI 3 #define WAKEUPI 4 #define EORSMI 5 #define UPRSMI 6 #define UDIEN _SFR_MEM8(0xE2) #define SUSPE 0 #define SOFE 2 #define EORSTE 3 #define WAKEUPE 4 #define EORSME 5 #define UPRSME 6 #define UDADDR _SFR_MEM8(0xE3) #define UADD0 0 #define UADD1 1 #define UADD2 2 #define UADD3 3 #define UADD4 4 #define UADD5 5 #define UADD6 6 #define ADDEN 7 #define UDFNUM _SFR_MEM16(0xE4) #define UDFNUML _SFR_MEM8(0xE4) #define FNUM0 0 #define FNUM1 1 #define FNUM2 2 #define FNUM3 3 #define FNUM4 4 #define FNUM5 5 #define FNUM6 6 #define FNUM7 7 #define UDFNUMH _SFR_MEM8(0xE5) #define FNUM8 0 #define FNUM9 1 #define FNUM10 2 #define UDMFN _SFR_MEM8(0xE6) #define FNCERR 4 #define UDTST _SFR_MEM8(0xE7) #define UEINTX _SFR_MEM8(0xE8) #define TXINI 0 #define STALLEDI 1 #define RXOUTI 2 #define RXSTPI 3 #define NAKOUTI 4 #define RWAL 5 #define NAKINI 6 #define FIFOCON 7 #define UENUM _SFR_MEM8(0xE9) #define UENUM_0 0 #define UENUM_1 1 #define UENUM_2 2 #define UERST _SFR_MEM8(0xEA) #define EPRST0 0 #define EPRST1 1 #define EPRST2 2 #define EPRST3 3 #define EPRST4 4 #define EPRST5 5 #define EPRST6 6 #define UECONX _SFR_MEM8(0xEB) #define EPEN 0 #define RSTDT 3 #define STALLRQC 4 #define STALLRQ 5 #define UECFG0X _SFR_MEM8(0xEC) #define EPDIR 0 #define EPTYPE0 6 #define EPTYPE1 7 #define UECFG1X _SFR_MEM8(0xED) #define ALLOC 1 #define EPBK0 2 #define EPBK1 3 #define EPSIZE0 4 #define EPSIZE1 5 #define EPSIZE2 6 #define UESTA0X _SFR_MEM8(0xEE) #define NBUSYBK0 0 #define NBUSYBK1 1 #define DTSEQ0 2 #define DTSEQ1 3 #define UNDERFI 5 #define OVERFI 6 #define CFGOK 7 #define UESTA1X _SFR_MEM8(0xEF) #define CURRBK0 0 #define CURRBK1 1 #define CTRLDIR 2 #define UEIENX _SFR_MEM8(0xF0) #define TXINE 0 #define STALLEDE 1 #define RXOUTE 2 #define RXSTPE 3 #define NAKOUTE 4 #define NAKINE 6 #define FLERRE 7 #define UEDATX _SFR_MEM8(0xF1) #define DAT0 0 #define DAT1 1 #define DAT2 2 #define DAT3 3 #define DAT4 4 #define DAT5 5 #define DAT6 6 #define DAT7 7 #define UEBCX _SFR_MEM16(0xF2) #define UEBCLX _SFR_MEM8(0xF2) #define BYCT0 0 #define BYCT1 1 #define BYCT2 2 #define BYCT3 3 #define BYCT4 4 #define BYCT5 5 #define BYCT6 6 #define BYCT7 7 #define UEBCHX _SFR_MEM8(0xF3) #define UEINT _SFR_MEM8(0xF4) #define EPINT0 0 #define EPINT1 1 #define EPINT2 2 #define EPINT3 3 #define EPINT4 4 #define EPINT5 5 #define EPINT6 6 #define UPERRX _SFR_MEM8(0xF5) #define UPBCLX _SFR_MEM8(0xF6) #define UPBCHX _SFR_MEM8(0xF7) #define UPINT _SFR_MEM8(0xF8) #define OTGTCON _SFR_MEM8(0xF9) /* Interrupt Vectors */ /* Interrupt Vector 0 is the reset vector. */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ #define PCINT0_vect_num 9 #define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ #define USB_GEN_vect_num 10 #define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ #define USB_COM_vect_num 11 #define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ #define TIMER1_CAPT_vect_num 16 #define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 17 #define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 18 #define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPC_vect_num 19 #define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ #define TIMER1_OVF_vect_num 20 #define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 21 #define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 22 #define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 23 #define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 24 #define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ #define USART1_RX_vect_num 25 #define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ #define USART1_UDRE_vect_num 26 #define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ #define USART1_TX_vect_num 27 #define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ #define ANALOG_COMP_vect_num 28 #define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ #define ADC_vect_num 29 #define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ #define EE_READY_vect_num 30 #define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ #define TIMER3_CAPT_vect_num 31 #define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ #define TIMER3_COMPA_vect_num 32 #define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPB_vect_num 33 #define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPC_vect_num 34 #define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ #define TIMER3_OVF_vect_num 35 #define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ #define TWI_vect_num 36 #define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ #define SPM_READY_vect_num 37 #define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ #define TIMER4_COMPA_vect_num 38 #define TIMER4_COMPA_vect _VECTOR(38) /* Timer/Counter4 Compare Match A */ #define TIMER4_COMPB_vect_num 39 #define TIMER4_COMPB_vect _VECTOR(39) /* Timer/Counter4 Compare Match B */ #define TIMER4_COMPD_vect_num 40 #define TIMER4_COMPD_vect _VECTOR(40) /* Timer/Counter4 Compare Match D */ #define TIMER4_OVF_vect_num 41 #define TIMER4_OVF_vect _VECTOR(41) /* Timer/Counter4 Overflow */ #define TIMER4_FPF_vect_num 42 #define TIMER4_FPF_vect _VECTOR(42) /* Timer/Counter4 Fault Protection Interrupt */ #define _VECTORS_SIZE (43 * 4) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (0xA00) #define RAMEND (RAMSTART + RAMSIZE - 1) /* Last On-Chip SRAM Location */ #define XRAMSTART (0x2200) #define XRAMSIZE (0x10000) #define XRAMEND (XRAMSIZE - 1) #define E2END (0x3FF) #define E2PAGESIZE (4) #define FLASHEND (0x7FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT1 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x87 #endif /* _AVR_IOM32U4_H_ */ avr-libc-1.8.0.orig/include/avr/iom32u6.h0000644000000000000000000006726511732702554014662 0ustar /* Copyright (c) 2008 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom32u6.h 1873 2009-02-11 17:53:39Z arcanum $ */ /* avr/iom32u6.h - definitions for ATmega32U6 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom32u6.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega32U6_H_ #define _AVR_ATmega32U6_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define PINC6 6 #define PINC7 7 #define DDRC _SFR_IO8(0x07) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define DDC6 6 #define DDC7 7 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PORTC6 6 #define PORTC7 7 #define PIND _SFR_IO8(0x09) #define PIND0 0 #define PIND1 1 #define PIND2 2 #define PIND3 3 #define PIND4 4 #define PIND5 5 #define PIND6 6 #define PIND7 7 #define DDRD _SFR_IO8(0x0A) #define DDD0 0 #define DDD1 1 #define DDD2 2 #define DDD3 3 #define DDD4 4 #define DDD5 5 #define DDD6 6 #define DDD7 7 #define PORTD _SFR_IO8(0x0B) #define PORTD0 0 #define PORTD1 1 #define PORTD2 2 #define PORTD3 3 #define PORTD4 4 #define PORTD5 5 #define PORTD6 6 #define PORTD7 7 #define PINE _SFR_IO8(0x0C) #define PINE0 0 #define PINE1 1 #define PINE2 2 #define PINE3 3 #define PINE4 4 #define PINE5 5 #define PINE6 6 #define PINE7 7 #define DDRE _SFR_IO8(0x0D) #define DDE0 0 #define DDE1 1 #define DDE2 2 #define DDE3 3 #define DDE4 4 #define DDE5 5 #define DDE6 6 #define DDE7 7 #define PORTE _SFR_IO8(0x0E) #define PORTE0 0 #define PORTE1 1 #define PORTE2 2 #define PORTE3 3 #define PORTE4 4 #define PORTE5 5 #define PORTE6 6 #define PORTE7 7 #define PINF _SFR_IO8(0x0F) #define PINF0 0 #define PINF1 1 #define PINF2 2 #define PINF3 3 #define PINF4 4 #define PINF5 5 #define PINF6 6 #define PINF7 7 #define DDRF _SFR_IO8(0x10) #define DDF0 0 #define DDF1 1 #define DDF2 2 #define DDF3 3 #define DDF4 4 #define DDF5 5 #define DDF6 6 #define DDF7 7 #define PORTF _SFR_IO8(0x11) #define PORTF0 0 #define PORTF1 1 #define PORTF2 2 #define PORTF3 3 #define PORTF4 4 #define PORTF5 5 #define PORTF6 6 #define PORTF7 7 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define OCF1C 3 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 #define OCF2B 2 #define TIFR3 _SFR_IO8(0x18) #define TOV3 0 #define OCF3A 1 #define OCF3B 2 #define OCF3C 3 #define ICF3 5 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define INTF4 4 #define INTF5 5 #define INTF6 6 #define INTF7 7 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define INT4 4 #define INT5 5 #define INT6 6 #define INT7 7 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define EEAR10 2 #define EEAR11 3 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define PSRASY 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define TCNT0 _SFR_IO8(0x26) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define OCR0A _SFR_IO8(0x27) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define OCR0B _SFR_IO8(0x28) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define PLLCSR _SFR_IO8(0x29) #define PLOCK 0 #define PLLE 1 #define PLLP0 2 #define PLLP1 3 #define PLLP2 4 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRADC 0 #define PRSPI 2 #define PRTIM1 3 #define PRTIM0 5 #define PRTIM2 6 #define PRTWI 7 #define PRR1 _SFR_MEM8(0x65) #define PRUSART1 0 #define PRTIM3 3 #define PRUSB 7 #define OSCCAL _SFR_MEM8(0x66) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define EICRB _SFR_MEM8(0x6A) #define ISC40 0 #define ISC41 1 #define ISC50 2 #define ISC51 3 #define ISC60 4 #define ISC61 5 #define ISC70 6 #define ISC71 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define OCIE1C 3 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 #define OCIE2B 2 #define TIMSK3 _SFR_MEM8(0x71) #define TOIE3 0 #define OCIE3A 1 #define OCIE3B 2 #define OCIE3C 3 #define ICIE3 5 #define XMCRA _SFR_MEM8(0x74) #define SRW00 0 #define SRW01 1 #define SRW10 2 #define SRW11 3 #define SRL0 4 #define SRL1 5 #define SRL2 6 #define SRE 7 #define XMCRB _SFR_MEM8(0x75) #define XMM0 0 #define XMM1 1 #define XMM2 2 #define XMBK 7 #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_MEM8(0x79) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADHSM 7 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define WGM11 1 #define COM1C0 2 #define COM1C1 3 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1C 5 #define FOC1B 6 #define FOC1A 7 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1L0 0 #define ICR1L1 1 #define ICR1L2 2 #define ICR1L3 3 #define ICR1L4 4 #define ICR1L5 5 #define ICR1L6 6 #define ICR1L7 7 #define ICR1H _SFR_MEM8(0x87) #define ICR1H0 0 #define ICR1H1 1 #define ICR1H2 2 #define ICR1H3 3 #define ICR1H4 4 #define ICR1H5 5 #define ICR1H6 6 #define ICR1H7 7 #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AL0 0 #define OCR1AL1 1 #define OCR1AL2 2 #define OCR1AL3 3 #define OCR1AL4 4 #define OCR1AL5 5 #define OCR1AL6 6 #define OCR1AL7 7 #define OCR1AH _SFR_MEM8(0x89) #define OCR1AH0 0 #define OCR1AH1 1 #define OCR1AH2 2 #define OCR1AH3 3 #define OCR1AH4 4 #define OCR1AH5 5 #define OCR1AH6 6 #define OCR1AH7 7 #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BL0 0 #define OCR1BL1 1 #define OCR1BL2 2 #define OCR1BL3 3 #define OCR1BL4 4 #define OCR1BL5 5 #define OCR1BL6 6 #define OCR1BL7 7 #define OCR1BH _SFR_MEM8(0x8B) #define OCR1BH0 0 #define OCR1BH1 1 #define OCR1BH2 2 #define OCR1BH3 3 #define OCR1BH4 4 #define OCR1BH5 5 #define OCR1BH6 6 #define OCR1BH7 7 #define OCR1C _SFR_MEM16(0x8C) #define OCR1CL _SFR_MEM8(0x8C) #define OCR1CL0 0 #define OCR1CL1 1 #define OCR1CL2 2 #define OCR1CL3 3 #define OCR1CL4 4 #define OCR1CL5 5 #define OCR1CL6 6 #define OCR1CL7 7 #define OCR1CH _SFR_MEM8(0x8D) #define OCR1CH0 0 #define OCR1CH1 1 #define OCR1CH2 2 #define OCR1CH3 3 #define OCR1CH4 4 #define OCR1CH5 5 #define OCR1CH6 6 #define OCR1CH7 7 #define TCCR3A _SFR_MEM8(0x90) #define WGM30 0 #define WGM31 1 #define COM3C0 2 #define COM3C1 3 #define COM3B0 4 #define COM3B1 5 #define COM3A0 6 #define COM3A1 7 #define TCCR3B _SFR_MEM8(0x91) #define CS30 0 #define CS31 1 #define CS32 2 #define WGM32 3 #define WGM33 4 #define ICES3 6 #define ICNC3 7 #define TCCR3C _SFR_MEM8(0x92) #define FOC3C 5 #define FOC3B 6 #define FOC3A 7 #define TCNT3 _SFR_MEM16(0x94) #define TCNT3L _SFR_MEM8(0x94) #define TCNT3L0 0 #define TCNT3L1 1 #define TCNT3L2 2 #define TCNT3L3 3 #define TCNT3L4 4 #define TCNT3L5 5 #define TCNT3L6 6 #define TCNT3L7 7 #define TCNT3H _SFR_MEM8(0x95) #define TCNT3H0 0 #define TCNT3H1 1 #define TCNT3H2 2 #define TCNT3H3 3 #define TCNT3H4 4 #define TCNT3H5 5 #define TCNT3H6 6 #define TCNT3H7 7 #define ICR3 _SFR_MEM16(0x96) #define ICR3L _SFR_MEM8(0x96) #define ICR3L0 0 #define ICR3L1 1 #define ICR3L2 2 #define ICR3L3 3 #define ICR3L4 4 #define ICR3L5 5 #define ICR3L6 6 #define ICR3L7 7 #define ICR3H _SFR_MEM8(0x97) #define ICR3H0 0 #define ICR3H1 1 #define ICR3H2 2 #define ICR3H3 3 #define ICR3H4 4 #define ICR3H5 5 #define ICR3H6 6 #define ICR3H7 7 #define OCR3A _SFR_MEM16(0x98) #define OCR3AL _SFR_MEM8(0x98) #define OCR3AL0 0 #define OCR3AL1 1 #define OCR3AL2 2 #define OCR3AL3 3 #define OCR3AL4 4 #define OCR3AL5 5 #define OCR3AL6 6 #define OCR3AL7 7 #define OCR3AH _SFR_MEM8(0x99) #define OCR3AH0 0 #define OCR3AH1 1 #define OCR3AH2 2 #define OCR3AH3 3 #define OCR3AH4 4 #define OCR3AH5 5 #define OCR3AH6 6 #define OCR3AH7 7 #define OCR3B _SFR_MEM16(0x9A) #define OCR3BL _SFR_MEM8(0x9A) #define OCR3BL0 0 #define OCR3BL1 1 #define OCR3BL2 2 #define OCR3BL3 3 #define OCR3BL4 4 #define OCR3BL5 5 #define OCR3BL6 6 #define OCR3BL7 7 #define OCR3BH _SFR_MEM8(0x9B) #define OCR3BH0 0 #define OCR3BH1 1 #define OCR3BH2 2 #define OCR3BH3 3 #define OCR3BH4 4 #define OCR3BH5 5 #define OCR3BH6 6 #define OCR3BH7 7 #define OCR3C _SFR_MEM16(0x9C) #define OCR3CL _SFR_MEM8(0x9C) #define OCR3CL0 0 #define OCR3CL1 1 #define OCR3CL2 2 #define OCR3CL3 3 #define OCR3CL4 4 #define OCR3CL5 5 #define OCR3CL6 6 #define OCR3CL7 7 #define OCR3CH _SFR_MEM8(0x9D) #define OCR3CH0 0 #define OCR3CH1 1 #define OCR3CH2 2 #define OCR3CH3 3 #define OCR3CH4 4 #define OCR3CH5 5 #define OCR3CH6 6 #define OCR3CH7 7 #define TCCR2A _SFR_MEM8(0xB0) #define WGM20 0 #define WGM21 1 #define COM2B0 4 #define COM2B1 5 #define COM2A0 6 #define COM2A1 7 #define TCCR2B _SFR_MEM8(0xB1) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM22 3 #define FOC2B 6 #define FOC2A 7 #define TCNT2 _SFR_MEM8(0xB2) #define TCNT2_0 0 #define TCNT2_1 1 #define TCNT2_2 2 #define TCNT2_3 3 #define TCNT2_4 4 #define TCNT2_5 5 #define TCNT2_6 6 #define TCNT2_7 7 #define OCR2A _SFR_MEM8(0xB3) #define OCR2A_0 0 #define OCR2A_1 1 #define OCR2A_2 2 #define OCR2A_3 3 #define OCR2A_4 4 #define OCR2A_5 5 #define OCR2A_6 6 #define OCR2A_7 7 #define OCR2B _SFR_MEM8(0xB4) #define OCR2B_0 0 #define OCR2B_1 1 #define OCR2B_2 2 #define OCR2B_3 3 #define OCR2B_4 4 #define OCR2B_5 5 #define OCR2B_6 6 #define OCR2B_7 7 #define ASSR _SFR_MEM8(0xB6) #define TCR2BUB 0 #define TCR2AUB 1 #define OCR2BUB 2 #define OCR2AUB 3 #define TCN2UB 4 #define AS2 5 #define EXCLK 6 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define UCSR1A _SFR_MEM8(0xC8) #define MPCM1 0 #define U2X1 1 #define UPE1 2 #define DOR1 3 #define FE1 4 #define UDRE1 5 #define TXC1 6 #define RXC1 7 #define UCSR1B _SFR_MEM8(0xC9) #define TXB81 0 #define RXB81 1 #define UCSZ12 2 #define TXEN1 3 #define RXEN1 4 #define UDRIE1 5 #define TXCIE1 6 #define RXCIE1 7 #define UCSR1C _SFR_MEM8(0xCA) #define UCPOL1 0 #define UCSZ10 1 #define UCSZ11 2 #define USBS1 3 #define UPM10 4 #define UPM11 5 #define UMSEL10 6 #define UMSEL11 7 #define UBRR1 _SFR_MEM16(0xCC) #define UBRR1L _SFR_MEM8(0xCC) #define UBRR_0 0 #define UBRR_1 1 #define UBRR_2 2 #define UBRR_3 3 #define UBRR_4 4 #define UBRR_5 5 #define UBRR_6 6 #define UBRR_7 7 #define UBRR1H _SFR_MEM8(0xCD) #define UBRR_8 0 #define UBRR_9 1 #define UBRR_10 2 #define UBRR_11 3 #define UDR1 _SFR_MEM8(0xCE) #define UDR1_0 0 #define UDR1_1 1 #define UDR1_2 2 #define UDR1_3 3 #define UDR1_4 4 #define UDR1_5 5 #define UDR1_6 6 #define UDR1_7 7 #define UHWCON _SFR_MEM8(0xD7) #define UVREGE 0 #define UVCONE 4 #define UIDE 6 #define UIMOD 7 #define USBCON _SFR_MEM8(0xD8) #define VBUSTE 0 #define IDTE 1 #define OTGPADE 4 #define FRZCLK 5 #define HOST 6 #define USBE 7 #define USBSTA _SFR_MEM8(0xD9) #define VBUS 0 #define ID 1 #define SPEED 3 #define USBINT _SFR_MEM8(0xDA) #define VBUSTI 0 #define IDTI 1 #define UDCON _SFR_MEM8(0xE0) #define DETACH 0 #define RMWKUP 1 #define LSM 2 #define UDINT _SFR_MEM8(0xE1) #define SUSPI 0 #define SOFI 2 #define EORSTI 3 #define WAKEUPI 4 #define EORSMI 5 #define UPRSMI 6 #define UDIEN _SFR_MEM8(0xE2) #define SUSPE 0 #define SOFE 2 #define EORSTE 3 #define WAKEUPE 4 #define EORSME 5 #define UPRSME 6 #define UDADDR _SFR_MEM8(0xE3) #define UADD0 0 #define UADD1 1 #define UADD2 2 #define UADD3 3 #define UADD4 4 #define UADD5 5 #define UADD6 6 #define ADDEN 7 #define UDFNUM _SFR_MEM16(0xE4) #define UDFNUML _SFR_MEM8(0xE4) #define UDFNUML_0 0 #define UDFNUML_1 1 #define UDFNUML_2 2 #define UDFNUML_3 3 #define UDFNUML_4 4 #define UDFNUML_5 5 #define UDFNUML_6 6 #define UDFNUML_7 7 #define UDFNUMH _SFR_MEM8(0xE5) #define UDFNUMH_0 0 #define UDFNUMH_1 1 #define UDFNUMH_2 2 #define UDMFN _SFR_MEM8(0xE6) #define FNCERR 4 #define UEINTX _SFR_MEM8(0xE8) #define TXINI 0 #define STALLEDI 1 #define RXOUTI 2 #define RXSTPI 3 #define NAKOUTI 4 #define RWAL 5 #define NAKINI 6 #define FIFOCON 7 #define UENUM _SFR_MEM8(0xE9) #define UENUM_0 0 #define UENUM_1 1 #define UENUM_2 2 #define UERST _SFR_MEM8(0xEA) #define EPRST0 0 #define EPRST1 1 #define EPRST2 2 #define EPRST3 3 #define EPRST4 4 #define EPRST5 5 #define EPRST6 6 #define UECONX _SFR_MEM8(0xEB) #define EPEN 0 #define RSTDT 3 #define STALLRQC 4 #define STALLRQ 5 #define UECFG0X _SFR_MEM8(0xEC) #define EPDIR 0 #define EPTYPE0 6 #define EPTYPE1 7 #define UECFG1X _SFR_MEM8(0xED) #define ALLOC 1 #define EPBK0 2 #define EPBK1 3 #define EPSIZE0 4 #define EPSIZE1 5 #define EPSIZE2 6 #define UESTA0X _SFR_MEM8(0xEE) #define NBUSYBK0 0 #define NBUSYBK1 1 #define DTSEQ0 2 #define DTSEQ1 3 #define UNDERFI 5 #define OVERFI 6 #define CFGOK 7 #define UESTA1X _SFR_MEM8(0xEF) #define CURRBK0 0 #define CURRBK1 1 #define CTRLDIR 2 #define UEIENX _SFR_MEM8(0xF0) #define TXINE 0 #define STALLEDE 1 #define RXOUTE 2 #define RXSTPE 3 #define NAKOUTE 4 #define NAKINE 6 #define FLERRE 7 #define UEDATX _SFR_MEM8(0xF1) #define UEDATX_0 0 #define UEDATX_1 1 #define UEDATX_2 2 #define UEDATX_3 3 #define UEDATX_4 4 #define UEDATX_5 5 #define UEDATX_6 6 #define UEDATX_7 7 #define UEBCLX _SFR_MEM8(0xF2) #define UEBCLX_0 0 #define UEBCLX_1 1 #define UEBCLX_2 2 #define UEBCLX_3 3 #define UEBCLX_4 4 #define UEBCLX_5 5 #define UEBCLX_6 6 #define UEBCLX_7 7 #define UEBCHX _SFR_MEM8(0xF3) #define UEBCHX_0 0 #define UEBCHX_1 1 #define UEBCHX_2 2 #define UEINT _SFR_MEM8(0xF4) #define EPINT0 0 #define EPINT1 1 #define EPINT2 2 #define EPINT3 3 #define EPINT4 4 #define EPINT5 5 #define EPINT6 6 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ #define INT2_vect_num 3 #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ #define INT3_vect_num 4 #define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ #define INT4_vect_num 5 #define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ #define INT5_vect_num 6 #define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ #define INT6_vect_num 7 #define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ #define INT7_vect_num 8 #define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ #define PCINT0_vect_num 9 #define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ #define USB_GEN_vect_num 10 #define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ #define USB_COM_vect_num 11 #define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ #define WDT_vect_num 12 #define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ #define TIMER2_COMPA_vect_num 13 #define TIMER2_COMPA_vect _VECTOR(13) /* Timer/Counter2 Compare Match A */ #define TIMER2_COMPB_vect_num 14 #define TIMER2_COMPB_vect _VECTOR(14) /* Timer/Counter2 Compare Match B */ #define TIMER2_OVF_vect_num 15 #define TIMER2_OVF_vect _VECTOR(15) /* Timer/Counter2 Overflow */ #define TIMER1_CAPT_vect_num 16 #define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ #define TIMER1_COMPA_vect_num 17 #define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPB_vect_num 18 #define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPC_vect_num 19 #define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ #define TIMER1_OVF_vect_num 20 #define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ #define TIMER0_COMPA_vect_num 21 #define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ #define TIMER0_COMPB_vect_num 22 #define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ #define TIMER0_OVF_vect_num 23 #define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ #define SPI_STC_vect_num 24 #define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ #define USART1_RX_vect_num 25 #define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ #define USART1_UDRE_vect_num 26 #define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ #define USART1_TX_vect_num 27 #define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ #define ANALOG_COMP_vect_num 28 #define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ #define ADC_vect_num 29 #define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ #define EE_READY_vect_num 30 #define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ #define TIMER3_CAPT_vect_num 31 #define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ #define TIMER3_COMPA_vect_num 32 #define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ #define TIMER3_COMPB_vect_num 33 #define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ #define TIMER3_COMPC_vect_num 34 #define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ #define TIMER3_OVF_vect_num 35 #define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ #define TWI_vect_num 36 #define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ #define SPM_READY_vect_num 37 #define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (38 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (2560) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (0x2200) #define XRAMSIZE (65536) #define XRAMEND (XRAMSIZE - 1) #define E2END (0x3FF) #define E2PAGESIZE (4) #define FLASHEND (0x7FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ #define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x95 #define SIGNATURE_2 0x88 #endif /* _AVR_ATmega32U6_H_ */ avr-libc-1.8.0.orig/include/avr/iousb647.h0000644000000000000000000000665411732702554015033 0ustar /* Copyright (c) 2006 Anatoly Sokolov Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iousb647.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ /* avr/iousb647.h - definitions for AT90USB647 */ #ifndef _AVR_AT90USB647_H_ #define _AVR_AT90USB647_H_ 1 #include /* Constants */ #define SPM_PAGESIZE 256 #define RAMEND 0x10FF #define XRAMEND 0xFFFF #define E2END 0x7FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_HWBE (unsigned char)~_BV(3) #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x82 #endif /* _AVR_AT90USB647_H_ */ avr-libc-1.8.0.orig/include/avr/iotn40.h0000644000000000000000000003554511732702554014567 0ustar /* Copyright (c) 2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id$ */ /* avr/iotn40.h - definitions for ATtiny40 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn40.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny40_H_ #define _AVR_ATtiny40_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 #define PUEA _SFR_IO8(0x03) #define PUEA0 0 #define PUEA1 1 #define PUEA2 2 #define PUEA3 3 #define PUEA4 4 #define PUEA5 5 #define PUEA6 6 #define PUEA7 7 #define PINB _SFR_IO8(0x04) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x05) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x06) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PUEB _SFR_IO8(0x07) #define PUEB0 0 #define PUEB1 1 #define PUEB2 2 #define PUEB3 3 #define PORTCR _SFR_IO8(0x08) #define BBMA 0 #define BBMB 1 #define BBMC 2 #define ADC8D 4 #define ADC9D 5 #define ADC10D 6 #define ADC11D 7 #define PCMSK0 _SFR_IO8(0x09) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_IO8(0x0A) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define GIFR _SFR_IO8(0x0B) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define PCIF2 6 #define GIMSK _SFR_IO8(0x0C) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define PCIE2 6 #define DIDR0 _SFR_IO8(0x0D) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x0E) #endif #define ADCW _SFR_IO16(0x0E) #define ADCL _SFR_IO8(0x0E) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x0F) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADMUX _SFR_IO8(0x10) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define REFS 6 #define ADCSRB _SFR_IO8(0x11) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADLAR 3 #define ADCSRA _SFR_IO8(0x12) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ACSRB _SFR_IO8(0x13) #define ACME 2 #define HLEV 6 #define HSEL 7 #define ACSRA _SFR_IO8(0x14) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCR0B _SFR_IO8(0x15) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 #define OCR0A _SFR_IO8(0x16) #define OCR0_0 0 #define OCR0_1 1 #define OCR0_2 2 #define OCR0_3 3 #define OCR0_4 4 #define OCR0_5 5 #define OCR0_6 6 #define OCR0_7 7 #define TCNT0 _SFR_IO8(0x17) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0B _SFR_IO8(0x18) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define PSR 4 #define TSM 5 #define FOC0B 6 #define FOC0A 7 #define TCCR0A _SFR_IO8(0x19) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define PCMSK2 _SFR_IO8(0x1A) #define PCINT12 0 #define PCINT13 1 #define PCINT14 2 #define PCINT15 3 #define PCINT16 4 #define PCINT17 5 #define PINC _SFR_IO8(0x1B) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PINC5 5 #define DDRC _SFR_IO8(0x1C) #define DDC0 0 #define DDC1 1 #define DDC2 2 #define DDC3 3 #define DDC4 4 #define DDC5 5 #define PORTC _SFR_IO8(0x1D) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define PUEC _SFR_IO8(0x1E) #define PUEC0 0 #define PUEC1 1 #define PUEC2 2 #define PUEC3 3 #define PUEC4 4 #define PUEC5 5 #define RAMDR _SFR_IO8(0x1F) #define RAMDR0 0 #define RAMDR1 1 #define RAMDR2 2 #define RAMDR3 3 #define RAMDR4 4 #define RAMDR5 5 #define RAMDR6 6 #define RAMDR7 7 #define RAMAR _SFR_IO8(0x20) #define RAMAR0 0 #define RAMAR1 1 #define RAMAR2 2 #define RAMAR3 3 #define RAMAR4 4 #define RAMAR5 5 #define RAMAR6 6 #define RAMAR7 7 #define OCR1B _SFR_IO8(0x21) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define OCR1A _SFR_IO8(0x22) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define TCNT1L _SFR_IO8(0x23) #define TCNT1_0 0 #define TCNT1_1 1 #define TCNT1_2 2 #define TCNT1_3 3 #define TCNT1_4 4 #define TCNT1_5 5 #define TCNT1_6 6 #define TCNT1_7 7 #define TCCR1A _SFR_IO8(0x24) #define CS10 0 #define CS11 1 #define CS12 2 #define CTC1 3 #define ICES1 4 #define ICNC1 5 #define ICEN1 6 #define TCW1 7 #define TIFR _SFR_IO8(0x25) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TOV1 3 #define OCF1A 4 #define OCF1B 5 #define ICF1 7 #define TIMSK _SFR_IO8(0x26) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define TOIE1 3 #define OCIE1A 4 #define OCIE1B 5 #define ICIE1 7 #define TCNT1H _SFR_IO8(0x27) #define TCNT1_8 0 #define TCNT1_9 1 #define TCNT1_10 2 #define TCNT1_11 3 #define TCNT1_12 4 #define TCNT1_13 5 #define TCNT1_14 6 #define TCNT1_15 7 #define TWSD _SFR_IO8(0x28) #define TWSD0 0 #define TWSD1 1 #define TWSD2 2 #define TWSD3 3 #define TWSD4 4 #define TWSD5 5 #define TWSD6 6 #define TWSD7 7 #define TWSAM _SFR_IO8(0x29) #define TWAE 0 #define TWSAM1 1 #define TWSAM2 2 #define TWSAM3 3 #define TWSAM4 4 #define TWSAM5 5 #define TWSAM6 6 #define TWSAM7 7 #define TWSA _SFR_IO8(0x2A) #define TWSA0 0 #define TWSA1 1 #define TWSA2 2 #define TWSA3 3 #define TWSA4 4 #define TWSA5 5 #define TWSA6 6 #define TWSA7 7 #define TWSSRA _SFR_IO8(0x2B) #define TWAS 0 #define TWDIR 1 #define TWBE 2 #define TWC 3 #define TWRA 4 #define TWCH 5 #define TWASIF 6 #define TWDIF 7 #define TWSCRB _SFR_IO8(0x2C) #define TWCMD0 0 #define TWCMD1 1 #define TWAA 2 #define TWSCRA _SFR_IO8(0x2D) #define TWSME 0 #define TWPME 1 #define TWSIE 2 #define TWEN 3 #define TWASIE 4 #define TWDIE 5 #define TWSHE 7 #define SPDR _SFR_IO8(0x2E) #define SPSR _SFR_IO8(0x2F) #define SPCR _SFR_IO8(0x30) #define WDTCSR _SFR_IO8(0x31) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define NVMCSR _SFR_IO8(0x32) #define NVMBSY 7 #define NVMCMD _SFR_IO8(0x33) #define NVMCMD0 0 #define NVMCMD1 1 #define NVMCMD2 2 #define NVMCMD3 3 #define NVMCMD4 4 #define NVMCMD5 5 #define QTCSR _SFR_IO8(0x34) #define PRR _SFR_IO8(0x35) #define PRADC 0 #define PRTIM0 1 #define PRTIM1 2 #define PRSPI 3 #define PRTWI 4 #define CLKPSR _SFR_IO8(0x36) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKMSR _SFR_IO8(0x37) #define CLKMS0 0 #define CLKMS1 1 #define DWDR _SFR_IO8(0x38) #define OSCCAL _SFR_IO8(0x39) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define MCUCR _SFR_IO8(0x3A) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define BODS 4 #define ISC00 6 #define ISC01 7 #define RSTFLR _SFR_IO8(0x3B) #define PORF 0 #define EXTRF 1 #define WDRF 3 #define CCP _SFR_IO8(0x3C) #define CCP0 0 #define CCP1 1 #define CCP2 2 #define CCP3 3 #define CCP4 4 #define CCP5 5 #define CCP6 6 #define CCP7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ #define WDT_vect_num 4 #define WDT_vect _VECTOR(4) /* Watchdog Time-out */ #define TIM1_CAPT_vect_num 5 #define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Input Capture */ #define TIM1_COMPA_vect_num 6 #define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIM1_COMPB_vect_num 7 #define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ #define TIM1_OVF_vect_num 8 #define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIM0_COMPA_vect_num 9 #define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ #define TIM0_COMPB_vect_num 10 #define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ #define TIM0_OVF_vect_num 11 #define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ #define ANA_COMP_vect_num 12 #define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ #define ADC_ADC_vect_num 13 #define ADC_ADC_vect _VECTOR(13) /* Conversion Complete */ #define TWI_SLAVE_vect_num 14 #define TWI_SLAVE_vect _VECTOR(14) /* Two-Wire Interface */ #define SPI_vect_num 15 #define SPI_vect _VECTOR(15) /* Serial Peripheral Interface */ #define QTRIP_vect_num 16 #define QTRIP_vect _VECTOR(16) /* Touch Sensing */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (17 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (64) #define RAMSTART (0x40) #define RAMSIZE (256) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x0) #define E2PAGESIZE (0) #define FLASHEND (0xFFF) /* Fuses */ #define FUSE_MEMORY_SIZE 0 /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x0E /* Device Pin Definitions */ #define ADC6_DDR DDRCINT #define ADC6_PORT PORTCINT #define ADC6_PIN PINCINT #define ADC6_BIT INT6 #define ADC5_DDR DDRCINT #define ADC5_PORT PORTCINT #define ADC5_PIN PINCINT #define ADC5_BIT INT5 #define OC0B_DDR DDRCINT #define OC0B_PORT PORTCINT #define OC0B_PIN PINCINT #define OC0B_BIT INT5 #define ADC4_DDR DDRCINT #define ADC4_PORT PORTCINT #define ADC4_PIN PINCINT #define ADC4_BIT INT4 #define T0_DDR DDRCINT #define T0_PORT PORTCINT #define T0_PIN PINCINT #define T0_BIT INT4 #define ADC3_DDR DDRPCINT #define ADC3_PORT PORTPCINT #define ADC3_PIN PINPCINT #define ADC3_BIT PCINT3 #define ADC2_DDR DDRPCINT #define ADC2_PORT PORTPCINT #define ADC2_PIN PINPCINT #define ADC2_BIT PCINT2 #define AIN1_DDR DDRPCINT #define AIN1_PORT PORTPCINT #define AIN1_PIN PINPCINT #define AIN1_BIT PCINT2 #define ADC1_DDR DDRCINT #define ADC1_PORT PORTCINT #define ADC1_PIN PINCINT #define ADC1_BIT INT1 #define AIN0_DDR DDRCINT #define AIN0_PORT PORTCINT #define AIN0_PIN PINCINT #define AIN0_BIT INT1 #define ADC0_DDR DDRCINT #define ADC0_PORT PORTCINT #define ADC0_PIN PINCINT #define ADC0_BIT INT0 #define CLKI_DDR DDRCINT1 #define CLKI_PORT PORTCINT1 #define CLKI_PIN PINCINT1 #define CLKI_BIT INT17 #define SDA_DDR DDRMOSI #define SDA_PORT PORTMOSI #define SDA_PIN PINMOSI #define SDA_BIT MOSI #define PCINT16_DDR DDRMOSI #define PCINT16_PORT PORTMOSI #define PCINT16_PIN PINMOSI #define PCINT16_BIT MOSI #define PCINT15_DDR DDRRESET #define PCINT15_PORT PORTRESET #define PCINT15_PIN PINRESET #define PCINT15_BIT RESET #define CLKO_DDR DDRINT #define CLKO_PORT PORTINT #define CLKO_PIN PININT #define CLKO_BIT INT0 #define MISO_DDR DDRINT #define MISO_PORT PORTINT #define MISO_PIN PININT #define MISO_BIT INT0 #define PCINT14_DDR DDRINT #define PCINT14_PORT PORTINT #define PCINT14_PIN PININT #define PCINT14_BIT INT0 #define SCL_DDR DDRSCK #define SCL_PORT PORTSCK #define SCL_PIN PINSCK #define SCL_BIT SCK #define ICP1_DDR DDRSCK #define ICP1_PORT PORTSCK #define ICP1_PIN PINSCK #define ICP1_BIT SCK #define T1_DDR DDRSCK #define T1_PORT PORTSCK #define T1_PIN PINSCK #define T1_BIT SCK #define PCINT13_DDR DDRSCK #define PCINT13_PORT PORTSCK #define PCINT13_PIN PINSCK #define PCINT13_BIT SCK #define SS_DDR DDROC0A #define SS_PORT PORTOC0A #define SS_PIN PINOC0A #define SS_BIT OC0A #define PCINT12_DDR DDROC0A #define PCINT12_PORT PORTOC0A #define PCINT12_PIN PINOC0A #define PCINT12_BIT OC0A #define PCINT11_DDR DDRADC1 #define PCINT11_PORT PORTADC1 #define PCINT11_PIN PINADC1 #define PCINT11_BIT ADC11 #define PCINT10_DDR DDRADC1 #define PCINT10_PORT PORTADC1 #define PCINT10_PIN PINADC1 #define PCINT10_BIT ADC10 #define PCINT9_DDR DDRADC9 #define PCINT9_PORT PORTADC9 #define PCINT9_PIN PINADC9 #define PCINT9_BIT ADC9 #define PCINT8_DDR DDRADC #define PCINT8_PORT PORTADC #define PCINT8_PIN PINADC #define PCINT8_BIT ADC8 #define PCINT7_DDR DDRADC #define PCINT7_PORT PORTADC #define PCINT7_PIN PINADC #define PCINT7_BIT ADC7 #endif /* _AVR_ATtiny40_H_ */ avr-libc-1.8.0.orig/include/avr/iom16hvb.h0000644000000000000000000005145711732702554015105 0ustar /* Copyright (c) 2011 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom16hvb.h 2211 2011-02-14 14:04:25Z aboyapati $ */ /* avr/iom16hvb.h - definitions for ATmega16HVB */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom16hvb.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATmega16HVB_H_ #define _AVR_ATmega16HVB_H_ 1 /* Registers and associated bit numbers. */ #define PINA _SFR_IO8(0x00) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define DDRA _SFR_IO8(0x01) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define PORTA _SFR_IO8(0x02) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PINB _SFR_IO8(0x03) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x04) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x05) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINC _SFR_IO8(0x06) #define PINC0 0 #define PINC1 1 #define PINC2 2 #define PINC3 3 #define PINC4 4 #define PORTC _SFR_IO8(0x08) #define PORTC0 0 #define PORTC1 1 #define PORTC2 2 #define PORTC3 3 #define PORTC4 4 #define PORTC5 5 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 3 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 3 #define OSICSR _SFR_IO8(0x17) #define OSIEN 0 #define OSIST 1 #define OSISEL0 4 #define PCIFR _SFR_IO8(0x1B) #define PCIF0 0 #define PCIF1 1 #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define INTF1 1 #define INTF2 2 #define INTF3 3 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define INT1 1 #define INT2 2 #define INT3 3 #define GPIOR0 _SFR_IO8(0x1E) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 #define EEDR _SFR_IO8(0x20) #define EEDR0 0 #define EEDR1 1 #define EEDR2 2 #define EEDR3 3 #define EEDR4 4 #define EEDR5 5 #define EEDR6 6 #define EEDR7 7 #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEAR0 0 #define EEAR1 1 #define EEAR2 2 #define EEAR3 3 #define EEAR4 4 #define EEAR5 5 #define EEAR6 6 #define EEAR7 7 #define EEARH _SFR_IO8(0x22) #define EEAR8 0 #define EEAR9 1 #define GTCCR _SFR_IO8(0x23) #define PSRSYNC 0 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define WGM00 0 #define ICS0 3 #define ICES0 4 #define ICNC0 5 #define ICEN0 6 #define TCW0 7 #define TCCR0B _SFR_IO8(0x25) #define CS00 0 #define CS01 1 #define CS02 2 #define TCNT0 _SFR_IO16(0x26) #define TCNT0L _SFR_IO8(0x26) #define TCNT0L0 0 #define TCNT0L1 1 #define TCNT0L2 2 #define TCNT0L3 3 #define TCNT0L4 4 #define TCNT0L5 5 #define TCNT0L6 6 #define TCNT0L7 7 #define TCNT0H _SFR_IO8(0x27) #define TCNT0H0 0 #define TCNT0H1 1 #define TCNT0H2 2 #define TCNT0H3 3 #define TCNT0H4 4 #define TCNT0H5 5 #define TCNT0H6 6 #define TCNT0H7 7 #define OCR0A _SFR_IO8(0x28) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0B _SFR_IO8(0x29) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x2B) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0x2E) #define SPDR0 0 #define SPDR1 1 #define SPDR2 2 #define SPDR3 3 #define SPDR4 4 #define SPDR5 5 #define SPDR6 6 #define SPDR7 7 #define DWDR _SFR_IO8(0x31) #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BODRF 2 #define WDRF 3 #define OCDRF 4 #define MCUCR _SFR_IO8(0x35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define CKOE 5 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define LBSET 3 #define RWWSRE 4 #define SIGRD 5 #define RWWSB 6 #define SPMIE 7 #define WDTCSR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPCE 7 #define PRR0 _SFR_MEM8(0x64) #define PRVADC 0 #define PRTIM0 1 #define PRTIM1 2 #define PRSPI 3 #define PRVRM 5 #define PRTWI 6 #define FOSCCAL _SFR_MEM8(0x66) #define FCAL0 0 #define FCAL1 1 #define FCAL2 2 #define FCAL3 3 #define FCAL4 4 #define FCAL5 5 #define FCAL6 6 #define FCAL7 7 #define PCICR _SFR_MEM8(0x68) #define PCIE0 0 #define PCIE1 1 #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 #define ISC10 2 #define ISC11 3 #define ISC20 4 #define ISC21 5 #define ISC30 6 #define ISC31 7 #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT4 0 #define PCINT5 1 #define PCINT6 2 #define PCINT7 3 #define PCINT8 4 #define PCINT9 5 #define PCINT10 6 #define PCINT11 7 #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 3 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 3 #define VADC _SFR_MEM16(0x78) #define VADCL _SFR_MEM8(0x78) #define VADC0 0 #define VADC1 1 #define VADC2 2 #define VADC3 3 #define VADC4 4 #define VADC5 5 #define VADC6 6 #define VADC7 7 #define VADCH _SFR_MEM8(0x79) #define VADC8 0 #define VADC9 1 #define VADC10 2 #define VADC11 3 #define VADCSR _SFR_MEM8(0x7A) #define VADCCIE 0 #define VADCCIF 1 #define VADSC 2 #define VADEN 3 #define VADMUX _SFR_MEM8(0x7C) #define VADMUX0 0 #define VADMUX1 1 #define VADMUX2 2 #define VADMUX3 3 #define DIDR0 _SFR_MEM8(0x7E) #define PA0DID 0 #define PA1DID 1 #define TCCR1A _SFR_MEM8(0x80) #define WGM10 0 #define ICS1 3 #define ICES1 4 #define ICNC1 5 #define ICEN1 6 #define TCW1 7 #define TCCR1B _SFR_MEM8(0x81) #define CS10 0 #define CS11 1 #define CS12 2 #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1L0 0 #define TCNT1L1 1 #define TCNT1L2 2 #define TCNT1L3 3 #define TCNT1L4 4 #define TCNT1L5 5 #define TCNT1L6 6 #define TCNT1L7 7 #define TCNT1H _SFR_MEM8(0x85) #define TCNT1H0 0 #define TCNT1H1 1 #define TCNT1H2 2 #define TCNT1H3 3 #define TCNT1H4 4 #define TCNT1H5 5 #define TCNT1H6 6 #define TCNT1H7 7 #define OCR1A _SFR_MEM8(0x88) #define OCR1A0 0 #define OCR1A1 1 #define OCR1A2 2 #define OCR1A3 3 #define OCR1A4 4 #define OCR1A5 5 #define OCR1A6 6 #define OCR1A7 7 #define OCR1B _SFR_MEM8(0x89) #define OCR1B0 0 #define OCR1B1 1 #define OCR1B2 2 #define OCR1B3 3 #define OCR1B4 4 #define OCR1B5 5 #define OCR1B6 6 #define OCR1B7 7 #define TWBR _SFR_MEM8(0xB8) #define TWBR0 0 #define TWBR1 1 #define TWBR2 2 #define TWBR3 3 #define TWBR4 4 #define TWBR5 5 #define TWBR6 6 #define TWBR7 7 #define TWSR _SFR_MEM8(0xB9) #define TWPS0 0 #define TWPS1 1 #define TWS3 3 #define TWS4 4 #define TWS5 5 #define TWS6 6 #define TWS7 7 #define TWAR _SFR_MEM8(0xBA) #define TWGCE 0 #define TWA0 1 #define TWA1 2 #define TWA2 3 #define TWA3 4 #define TWA4 5 #define TWA5 6 #define TWA6 7 #define TWDR _SFR_MEM8(0xBB) #define TWD0 0 #define TWD1 1 #define TWD2 2 #define TWD3 3 #define TWD4 4 #define TWD5 5 #define TWD6 6 #define TWD7 7 #define TWCR _SFR_MEM8(0xBC) #define TWIE 0 #define TWEN 2 #define TWWC 3 #define TWSTO 4 #define TWSTA 5 #define TWEA 6 #define TWINT 7 #define TWAMR _SFR_MEM8(0xBD) #define TWAM0 1 #define TWAM1 2 #define TWAM2 3 #define TWAM3 4 #define TWAM4 5 #define TWAM5 6 #define TWAM6 7 #define TWBCSR _SFR_MEM8(0xBE) #define TWBCIP 0 #define TWBDT0 1 #define TWBDT1 2 #define TWBCIE 6 #define TWBCIF 7 #define ROCR _SFR_MEM8(0xC8) #define ROCWIE 0 #define ROCWIF 1 #define ROCD 4 #define ROCS 7 #define BGCCR _SFR_MEM8(0xD0) #define BGCC0 0 #define BGCC1 1 #define BGCC2 2 #define BGCC3 3 #define BGCC4 4 #define BGCC5 5 #define BGCRR _SFR_MEM8(0xD1) #define BGCR0 0 #define BGCR1 1 #define BGCR2 2 #define BGCR3 3 #define BGCR4 4 #define BGCR5 5 #define BGCR6 6 #define BGCR7 7 #define BGCSR _SFR_MEM8(0xD2) #define BGSCDIE 0 #define BGSCDIF 1 #define BGSCDE 4 #define BGD 5 #define CHGDCSR _SFR_MEM8(0xD4) #define CHGDIE 0 #define CHGDIF 1 #define CHGDISC0 2 #define CHGDISC1 3 #define BATTPVL 4 #define CADAC0 _SFR_MEM8(0xE0) #define CADAC00 0 #define CADAC01 1 #define CADAC02 2 #define CADAC03 3 #define CADAC04 4 #define CADAC05 5 #define CADAC06 6 #define CADAC07 7 #define CADAC1 _SFR_MEM8(0xE1) #define CADAC08 0 #define CADAC09 1 #define CADAC10 2 #define CADAC11 3 #define CADAC12 4 #define CADAC13 5 #define CADAC14 6 #define CADAC15 7 #define CADAC2 _SFR_MEM8(0xE2) #define CADAC16 0 #define CADAC17 1 #define CADAC18 2 #define CADAC19 3 #define CADAC20 4 #define CADAC21 5 #define CADAC22 6 #define CADAC23 7 #define CADAC3 _SFR_MEM8(0xE3) #define CADAC24 0 #define CADAC25 1 #define CADAC26 2 #define CADAC27 3 #define CADAC28 4 #define CADAC29 5 #define CADAC30 6 #define CADAC31 7 #define CADIC _SFR_MEM16(0xE4) #define CADICL _SFR_MEM8(0xE4) #define CADICL0 0 #define CADICL1 1 #define CADICL2 2 #define CADICL3 3 #define CADICL4 4 #define CADICL5 5 #define CADICL6 6 #define CADICL7 7 #define CADICH _SFR_MEM8(0xE5) #define CADICH0 0 #define CADICH1 1 #define CADICH2 2 #define CADICH3 3 #define CADICH4 4 #define CADICH5 5 #define CADICH6 6 #define CADICH7 7 #define CADCSRA _SFR_MEM8(0xE6) #define CADSE 0 #define CADSI0 1 #define CADSI1 2 #define CADAS0 3 #define CADAS1 4 #define CADUB 5 #define CADPOL 6 #define CADEN 7 #define CADCSRB _SFR_MEM8(0xE7) #define CADICIF 0 #define CADRCIF 1 #define CADACIF 2 #define CADICIE 4 #define CADRCIE 5 #define CADACIE 6 #define CADCSRC _SFR_MEM8(0xE8) #define CADVSE 0 #define CADRCC _SFR_MEM8(0xE9) #define CADRCC0 0 #define CADRCC1 1 #define CADRCC2 2 #define CADRCC3 3 #define CADRCC4 4 #define CADRCC5 5 #define CADRCC6 6 #define CADRCC7 7 #define CADRDC _SFR_MEM8(0xEA) #define CADRDC0 0 #define CADRDC1 1 #define CADRDC2 2 #define CADRDC3 3 #define CADRDC4 4 #define CADRDC5 5 #define CADRDC6 6 #define CADRDC7 7 #define FCSR _SFR_MEM8(0xF0) #define CFE 0 #define DFE 1 #define CPS 2 #define DUVRD 3 #define CBCR _SFR_MEM8(0xF1) #define CBE1 0 #define CBE2 1 #define CBE3 2 #define CBE4 3 #define BPIMSK _SFR_MEM8(0xF2) #define CHCIE 0 #define DHCIE 1 #define COCIE 2 #define DOCIE 3 #define SCIE 4 #define BPIFR _SFR_MEM8(0xF3) #define CHCIF 0 #define DHCIF 1 #define COCIF 2 #define DOCIF 3 #define SCIF 4 #define BPSCD _SFR_MEM8(0xF5) #define SCDL0 0 #define SCDL1 1 #define SCDL2 2 #define SCDL3 3 #define SCDL4 4 #define SCDL5 5 #define SCDL6 6 #define SCDL7 7 #define BPDOCD _SFR_MEM8(0xF6) #define DOCDL0 0 #define DOCDL1 1 #define DOCDL2 2 #define DOCDL3 3 #define DOCDL4 4 #define DOCDL5 5 #define DOCDL6 6 #define DOCDL7 7 #define BPCOCD _SFR_MEM8(0xF7) #define COCDL0 0 #define COCDL1 1 #define COCDL2 2 #define COCDL3 3 #define COCDL4 4 #define COCDL5 5 #define COCDL6 6 #define COCDL7 7 #define BPDHCD _SFR_MEM8(0xF8) #define DHCDL0 0 #define DHCDL1 1 #define DHCDL2 2 #define DHCDL3 3 #define DHCDL4 4 #define DHCDL5 5 #define DHCDL6 6 #define DHCDL7 7 #define BPCHCD _SFR_MEM8(0xF9) #define CHCDL0 0 #define CHCDL1 1 #define CHCDL2 2 #define CHCDL3 3 #define CHCDL4 4 #define CHCDL5 5 #define CHCDL6 6 #define CHCDL7 7 #define BPSCTR _SFR_MEM8(0xFA) #define SCPT0 0 #define SCPT1 1 #define SCPT2 2 #define SCPT3 3 #define SCPT4 4 #define SCPT5 5 #define SCPT6 6 #define BPOCTR _SFR_MEM8(0xFB) #define OCPT0 0 #define OCPT1 1 #define OCPT2 2 #define OCPT3 3 #define OCPT4 4 #define OCPT5 5 #define BPHCTR _SFR_MEM8(0xFC) #define HCPT0 0 #define HCPT1 1 #define HCPT2 2 #define HCPT3 3 #define HCPT4 4 #define HCPT5 5 #define BPCR _SFR_MEM8(0xFD) #define CHCD 0 #define DHCD 1 #define COCD 2 #define DOCD 3 #define SCD 4 #define EPID 5 #define BPPLR _SFR_MEM8(0xFE) #define BPPL 0 #define BPPLE 1 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define BPINT_vect_num 1 #define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ #define VREGMON_vect_num 2 #define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ #define INT0_vect_num 3 #define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ #define INT1_vect_num 4 #define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ #define INT2_vect_num 5 #define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ #define INT3_vect_num 6 #define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ #define PCINT0_vect_num 7 #define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ #define PCINT1_vect_num 8 #define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ #define WDT_vect_num 9 #define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ #define BGSCD_vect_num 10 #define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ #define CHDET_vect_num 11 #define CHDET_vect _VECTOR(11) /* Charger Detect */ #define TIMER1_IC_vect_num 12 #define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ #define TIMER1_COMPA_vect_num 13 #define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ #define TIMER1_COMPB_vect_num 14 #define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ #define TIMER1_OVF_vect_num 15 #define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ #define TIMER0_IC_vect_num 16 #define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ #define TIMER0_COMPA_vect_num 17 #define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ #define TIMER0_COMPB_vect_num 18 #define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ #define TIMER0_OVF_vect_num 19 #define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ #define TWIBUSCD_vect_num 20 #define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ #define TWI_vect_num 21 #define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ #define SPI_STC_vect_num 22 #define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ #define VADC_vect_num 23 #define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ #define CCADC_CONV_vect_num 24 #define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ #define CCADC_REG_CUR_vect_num 25 #define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ #define CCADC_ACC_vect_num 26 #define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ #define EE_READY_vect_num 27 #define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ #define SPM_vect_num 28 #define SPM_vect _VECTOR(28) /* SPM Ready */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (29 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (128) #define RAMSTART (0x100) #define RAMSIZE (1024) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (NA) #define XRAMEND (RAMEND) #define E2END (0x1FF) #define E2PAGESIZE (4) #define FLASHEND (0x3FFF) /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ #define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ #define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ #define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ #define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ #define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ #define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ #define FUSE_CKDIV (unsigned char)~_BV(4) /* Clock Divide Register */ #define HFUSE_DEFAULT (FUSE_CKDIV & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x0D /* Device Pin Definitions */ #define PV2_DDR DDRV #define PV2_PORT PORTV #define PV2_PIN PINV #define PV2_BIT 2 #define PV1_DDR DDRV #define PV1_PORT PORTV #define PV1_PIN PINV #define PV1_BIT 1 #define NV_DDR DDRNV #define NV_PORT PORTNV #define NV_PIN PINNV #define NV_BIT NV #define VFET_DDR DDRVFET #define VFET_PORT PORTVFET #define VFET_PIN PINVFET #define VFET_BIT VFET #define CF1P_DDR DDRCF1P #define CF1P_PORT PORTCF1P #define CF1P_PIN PINCF1P #define CF1P_BIT CF1P #define CF1N_DDR DDRCF1N #define CF1N_PORT PORTCF1N #define CF1N_PIN PINCF1N #define CF1N_BIT CF1N #define CF2P_DDR DDRCF2P #define CF2P_PORT PORTCF2P #define CF2P_PIN PINCF2P #define CF2P_BIT CF2P #define CF2N_DDR DDRCF2N #define CF2N_PORT PORTCF2N #define CF2N_PIN PINCF2N #define CF2N_BIT CF2N #define VREG_DDR DDRVREG #define VREG_PORT PORTVREG #define VREG_PIN PINVREG #define VREG_BIT VREG #define VREF_DDR DDRVREF #define VREF_PORT PORTVREF #define VREF_PIN PINVREF #define VREF_BIT VREF #define VREF_DDR DDRVREFGND #define VREF_PORT PORTVREFGND #define VREF_PIN PINVREFGND #define VREF_BIT VREFGND #define PI_DDR DDRI #define PI_PORT PORTI #define PI_PIN PINI #define PI_BIT #define NI_DDR DDRNI #define NI_PORT PORTNI #define NI_PIN PINNI #define NI_BIT NI #define PA0_DDR DDRA #define PA0_PORT PORTA #define PA0_PIN PINA #define PA0_BIT 0 #define PA1_DDR DDRA #define PA1_PORT PORTA #define PA1_PIN PINA #define PA1_BIT 1 #define PA2_DDR DDRA #define PA2_PORT PORTA #define PA2_PIN PINA #define PA2_BIT 2 #define PB0_DDR DDRB #define PB0_PORT PORTB #define PB0_PIN PINB #define PB0_BIT 0 #define PB1_DDR DDRB #define PB1_PORT PORTB #define PB1_PIN PINB #define PB1_BIT 1 #define PB2_DDR DDRB #define PB2_PORT PORTB #define PB2_PIN PINB #define PB2_BIT 2 #define PB3_DDR DDRB #define PB3_PORT PORTB #define PB3_PIN PINB #define PB3_BIT 3 #define PC0_DDR DDRC #define PC0_PORT PORTC #define PC0_PIN PINC #define PC0_BIT 0 #define BATT_DDR DDRBATT #define BATT_PORT PORTBATT #define BATT_PIN PINBATT #define BATT_BIT BATT #define OC_DDR DDROC #define OC_PORT PORTOC #define OC_PIN PINOC #define OC_BIT OC #endif /* _AVR_ATmega16HVB_H_ */ avr-libc-1.8.0.orig/include/avr/iox256a3.h0000644000000000000000000111151411732702554014722 0ustar /* Copyright (c) 2009-2010 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox256a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox256a3.h - definitions for ATxmega256A3 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox256a3.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATxmega256A3_H_ #define _AVR_ATxmega256A3_H_ 1 /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ /* Deprecated */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ } CLK_RTCSRC_t; /* -------------------------------------------------------------------------- SLEEP - Sleep Controller -------------------------------------------------------------------------- */ /* Sleep Controller */ typedef struct SLEEP_struct { register8_t CTRL; /* Control Register */ } SLEEP_t; /* Sleep Mode */ typedef enum SLEEP_SMODE_enum { SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ } SLEEP_SMODE_t; /* -------------------------------------------------------------------------- OSC - Oscillator -------------------------------------------------------------------------- */ /* Oscillator */ typedef struct OSC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ register8_t PLLCTRL; /* PLL Control REgister */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; /* Oscillator Frequency Range */ typedef enum OSC_FRQRANGE_enum { OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ } OSC_FRQRANGE_t; /* External Oscillator Selection and Startup Time */ typedef enum OSC_XOSCSEL_enum { OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ } OSC_XOSCSEL_t; /* PLL Clock Source */ typedef enum OSC_PLLSRC_enum { OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; /* -------------------------------------------------------------------------- DFLL - DFLL -------------------------------------------------------------------------- */ /* DFLL */ typedef struct DFLL_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t CALA; /* Calibration Register A */ register8_t CALB; /* Calibration Register B */ register8_t COMP0; /* Oscillator Compare Register 0 */ register8_t COMP1; /* Oscillator Compare Register 1 */ register8_t COMP2; /* Oscillator Compare Register 2 */ register8_t reserved_0x07; } DFLL_t; /* -------------------------------------------------------------------------- RST - Reset -------------------------------------------------------------------------- */ /* Reset */ typedef struct RST_struct { register8_t STATUS; /* Status Register */ register8_t CTRL; /* Control Register */ } RST_t; /* -------------------------------------------------------------------------- WDT - Watch-Dog Timer -------------------------------------------------------------------------- */ /* Watch-Dog Timer */ typedef struct WDT_struct { register8_t CTRL; /* Control */ register8_t WINCTRL; /* Windowed Mode Control */ register8_t STATUS; /* Status */ } WDT_t; /* Period setting */ typedef enum WDT_PER_enum { WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_PER_t; /* Closed window period */ typedef enum WDT_WPER_enum { WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ } WDT_WPER_t; /* -------------------------------------------------------------------------- MCU - MCU Control -------------------------------------------------------------------------- */ /* MCU Control */ typedef struct MCU_struct { register8_t DEVID0; /* Device ID byte 0 */ register8_t DEVID1; /* Device ID byte 1 */ register8_t DEVID2; /* Device ID byte 2 */ register8_t REVID; /* Revision ID */ register8_t JTAGUID; /* JTAG User ID */ register8_t reserved_0x05; register8_t MCUCR; /* MCU Control */ register8_t reserved_0x07; register8_t EVSYSLOCK; /* Event System Lock */ register8_t AWEXLOCK; /* AWEX Lock */ register8_t reserved_0x0A; register8_t reserved_0x0B; } MCU_t; /* -------------------------------------------------------------------------- PMIC - Programmable Multi-level Interrupt Controller -------------------------------------------------------------------------- */ /* Programmable Multi-level Interrupt Controller */ typedef struct PMIC_struct { register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ } PMIC_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Channel */ typedef struct DMA_CH_struct { register8_t CTRLA; /* Channel Control */ register8_t CTRLB; /* Channel Control */ register8_t ADDRCTRL; /* Address Control */ register8_t TRIGSRC; /* Channel Trigger Source */ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ register8_t REPCNT; /* Channel Repeat Count */ register8_t reserved_0x07; register8_t SRCADDR0; /* Channel Source Address 0 */ register8_t SRCADDR1; /* Channel Source Address 1 */ register8_t SRCADDR2; /* Channel Source Address 2 */ register8_t reserved_0x0B; register8_t DESTADDR0; /* Channel Destination Address 0 */ register8_t DESTADDR1; /* Channel Destination Address 1 */ register8_t DESTADDR2; /* Channel Destination Address 2 */ register8_t reserved_0x0F; } DMA_CH_t; /* -------------------------------------------------------------------------- DMA - DMA Controller -------------------------------------------------------------------------- */ /* DMA Controller */ typedef struct DMA_struct { register8_t CTRL; /* Control */ register8_t reserved_0x01; register8_t reserved_0x02; register8_t INTFLAGS; /* Transfer Interrupt Status */ register8_t STATUS; /* Status */ register8_t reserved_0x05; _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; DMA_CH_t CH0; /* DMA Channel 0 */ DMA_CH_t CH1; /* DMA Channel 1 */ DMA_CH_t CH2; /* DMA Channel 2 */ DMA_CH_t CH3; /* DMA Channel 3 */ } DMA_t; /* Burst mode */ typedef enum DMA_CH_BURSTLEN_enum { DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ } DMA_CH_BURSTLEN_t; /* Source address reload mode */ typedef enum DMA_CH_SRCRELOAD_enum { DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ } DMA_CH_SRCRELOAD_t; /* Source addressing mode */ typedef enum DMA_CH_SRCDIR_enum { DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ } DMA_CH_SRCDIR_t; /* Destination adress reload mode */ typedef enum DMA_CH_DESTRELOAD_enum { DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ } DMA_CH_DESTRELOAD_t; /* Destination adressing mode */ typedef enum DMA_CH_DESTDIR_enum { DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ } DMA_CH_DESTDIR_t; /* Transfer trigger source */ typedef enum DMA_CH_TRIGSRC_enum { DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ } DMA_CH_TRIGSRC_t; /* Double buffering mode */ typedef enum DMA_DBUFMODE_enum { DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ } DMA_DBUFMODE_t; /* Priority mode */ typedef enum DMA_PRIMODE_enum { DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ } DMA_PRIMODE_t; /* Interrupt level */ typedef enum DMA_CH_ERRINTLVL_enum { DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ } DMA_CH_ERRINTLVL_t; /* Interrupt level */ typedef enum DMA_CH_TRNINTLVL_enum { DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ } DMA_CH_TRNINTLVL_t; /* -------------------------------------------------------------------------- EVSYS - Event System -------------------------------------------------------------------------- */ /* Event System */ typedef struct EVSYS_struct { register8_t CH0MUX; /* Event Channel 0 Multiplexer */ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ register8_t CH0CTRL; /* Channel 0 Control Register */ register8_t CH1CTRL; /* Channel 1 Control Register */ register8_t CH2CTRL; /* Channel 2 Control Register */ register8_t CH3CTRL; /* Channel 3 Control Register */ register8_t CH4CTRL; /* Channel 4 Control Register */ register8_t CH5CTRL; /* Channel 5 Control Register */ register8_t CH6CTRL; /* Channel 6 Control Register */ register8_t CH7CTRL; /* Channel 7 Control Register */ register8_t STROBE; /* Event Strobe */ register8_t DATA; /* Event Data */ } EVSYS_t; /* Quadrature Decoder Index Recognition Mode */ typedef enum EVSYS_QDIRM_enum { EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ } EVSYS_QDIRM_t; /* Digital filter coefficient */ typedef enum EVSYS_DIGFILT_enum { EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ } EVSYS_DIGFILT_t; /* Event Channel multiplexer input selection */ typedef enum EVSYS_CHMUX_enum { EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ } EVSYS_CHMUX_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Non-volatile Memory Controller */ typedef struct NVM_struct { register8_t ADDR0; /* Address Register 0 */ register8_t ADDR1; /* Address Register 1 */ register8_t ADDR2; /* Address Register 2 */ register8_t reserved_0x03; register8_t DATA0; /* Data Register 0 */ register8_t DATA1; /* Data Register 1 */ register8_t DATA2; /* Data Register 2 */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t CMD; /* Command */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ register8_t LOCKBITS; /* Lock Bits */ } NVM_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { register8_t LOCKBITS; /* Lock Bits */ } NVM_LOCKBITS_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Fuses */ typedef struct NVM_FUSES_struct { register8_t FUSEBYTE0; /* JTAG User ID */ register8_t FUSEBYTE1; /* Watchdog Configuration */ register8_t FUSEBYTE2; /* Reset Configuration */ register8_t reserved_0x03; register8_t FUSEBYTE4; /* Start-up Configuration */ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ } NVM_FUSES_t; /* -------------------------------------------------------------------------- NVM - Non Volatile Memory Controller -------------------------------------------------------------------------- */ /* Production Signatures */ typedef struct NVM_PROD_SIGNATURES_struct { register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ register8_t reserved_0x01; register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t WAFNUM; /* Wafer Number */ register8_t reserved_0x11; register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ register8_t reserved_0x26; register8_t reserved_0x27; register8_t reserved_0x28; register8_t reserved_0x29; register8_t reserved_0x2A; register8_t reserved_0x2B; register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ register8_t reserved_0x34; register8_t reserved_0x35; register8_t reserved_0x36; register8_t reserved_0x37; register8_t reserved_0x38; register8_t reserved_0x39; register8_t reserved_0x3A; register8_t reserved_0x3B; register8_t reserved_0x3C; register8_t reserved_0x3D; register8_t reserved_0x3E; } NVM_PROD_SIGNATURES_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ typedef enum NVM_SPMLVL_enum { NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ } NVM_SPMLVL_t; /* EEPROM ready interrupt level */ typedef enum NVM_EELVL_enum { NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ } NVM_EELVL_t; /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ } NVM_LB_t; /* Boot Loader Section Reset Vector */ typedef enum BOOTRST_enum { BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ } BOOTRST_t; /* BOD operation */ typedef enum BOD_enum { BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ } BOD_t; /* Watchdog (Window) Timeout Period */ typedef enum WD_enum { WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ } WD_t; /* Start-up Time */ typedef enum SUT_enum { SUT_0MS_gc = (0x03<<2), /* 0 ms */ SUT_4MS_gc = (0x01<<2), /* 4 ms */ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; /* Brown Out Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ } BODLVL_t; /* -------------------------------------------------------------------------- AC - Analog Comparator -------------------------------------------------------------------------- */ /* Analog Comparator */ typedef struct AC_struct { register8_t AC0CTRL; /* Comparator 0 Control */ register8_t AC1CTRL; /* Comparator 1 Control */ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t WINCTRL; /* Window Mode Control */ register8_t STATUS; /* Status */ } AC_t; /* Interrupt mode */ typedef enum AC_INTMODE_enum { AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ } AC_INTMODE_t; /* Interrupt level */ typedef enum AC_INTLVL_enum { AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ } AC_INTLVL_t; /* Hysteresis mode selection */ typedef enum AC_HYSMODE_enum { AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ } AC_HYSMODE_t; /* Positive input multiplexer selection */ typedef enum AC_MUXPOS_enum { AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ } AC_MUXPOS_t; /* Negative input multiplexer selection */ typedef enum AC_MUXNEG_enum { AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ } AC_MUXNEG_t; /* Windows interrupt mode */ typedef enum AC_WINTMODE_enum { AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ } AC_WINTMODE_t; /* Window interrupt level */ typedef enum AC_WINTLVL_enum { AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ } AC_WINTLVL_t; /* Window mode state */ typedef enum AC_WSTATE_enum { AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ } AC_WSTATE_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* ADC Channel */ typedef struct ADC_CH_struct { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ register8_t INTCTRL; /* Channel Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ register8_t reserved_0x6; register8_t reserved_0x7; } ADC_CH_t; /* -------------------------------------------------------------------------- ADC - Analog/Digital Converter -------------------------------------------------------------------------- */ /* Analog-to-Digital Converter */ typedef struct ADC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t REFCTRL; /* Reference Control */ register8_t EVCTRL; /* Event Control */ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); /* Calibration Value */ register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); /* Channel 0 Result */ _WORDREGISTER(CH1RES); /* Channel 1 Result */ _WORDREGISTER(CH2RES); /* Channel 2 Result */ _WORDREGISTER(CH3RES); /* Channel 3 Result */ _WORDREGISTER(CMP); /* Compare Value */ register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; /* ADC Channel 0 */ ADC_CH_t CH1; /* ADC Channel 1 */ ADC_CH_t CH2; /* ADC Channel 2 */ ADC_CH_t CH3; /* ADC Channel 3 */ } ADC_t; /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ } ADC_CH_MUXPOS_t; /* Internal input multiplexer selections */ typedef enum ADC_CH_MUXINT_enum { ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ } ADC_CH_MUXINT_t; /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ } ADC_CH_MUXNEG_t; /* Input mode */ typedef enum ADC_CH_INPUTMODE_enum { ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ } ADC_CH_INPUTMODE_t; /* Gain factor */ typedef enum ADC_CH_GAIN_enum { ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ typedef enum ADC_RESOLUTION_enum { ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ } ADC_RESOLUTION_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ } ADC_REFSEL_t; /* Channel sweep selection */ typedef enum ADC_SWEEP_enum { ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ } ADC_SWEEP_t; /* Event channel input selection */ typedef enum ADC_EVSEL_enum { ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ } ADC_EVSEL_t; /* Event action selection */ typedef enum ADC_EVACT_enum { ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ } ADC_EVACT_t; /* Interupt mode */ typedef enum ADC_CH_INTMODE_enum { ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ } ADC_CH_INTMODE_t; /* Interrupt level */ typedef enum ADC_CH_INTLVL_enum { ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ } ADC_CH_INTLVL_t; /* DMA request selection */ typedef enum ADC_DMASEL_enum { ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ } ADC_DMASEL_t; /* Clock prescaler */ typedef enum ADC_PRESCALER_enum { ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ } ADC_PRESCALER_t; /* -------------------------------------------------------------------------- DAC - Digital/Analog Converter -------------------------------------------------------------------------- */ /* Digital-to-Analog Converter */ typedef struct DAC_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ register8_t TIMCTRL; /* Timing Control */ register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; register8_t GAINCAL; /* Gain Calibration */ register8_t OFFSETCAL; /* Offset Calibration */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; _WORDREGISTER(CH0DATA); /* Channel 0 Data */ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ } DAC_t; /* Output channel selection */ typedef enum DAC_CHSEL_enum { DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ } DAC_CHSEL_t; /* Reference voltage selection */ typedef enum DAC_REFSEL_enum { DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ } DAC_REFSEL_t; /* Event channel selection */ typedef enum DAC_EVSEL_enum { DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; /* Conversion interval */ typedef enum DAC_CONINTVAL_enum { DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ } DAC_CONINTVAL_t; /* Refresh rate */ typedef enum DAC_REFRESH_enum { DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ } DAC_REFRESH_t; /* -------------------------------------------------------------------------- RTC - Real-Time Clounter -------------------------------------------------------------------------- */ /* Real-Time Counter */ typedef struct RTC_struct { register8_t CTRL; /* Control Register */ register8_t STATUS; /* Status Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t TEMP; /* Temporary register */ register8_t reserved_0x05; register8_t reserved_0x06; register8_t reserved_0x07; _WORDREGISTER(CNT); /* Count Register */ _WORDREGISTER(PER); /* Period Register */ _WORDREGISTER(COMP); /* Compare Register */ } RTC_t; /* Prescaler Factor */ typedef enum RTC_PRESCALER_enum { RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ } RTC_PRESCALER_t; /* Compare Interrupt level */ typedef enum RTC_COMPINTLVL_enum { RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ } RTC_COMPINTLVL_t; /* Overflow Interrupt level */ typedef enum RTC_OVFINTLVL_enum { RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } RTC_OVFINTLVL_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* EBI Chip Select Module */ typedef struct EBI_CS_struct { register8_t CTRLA; /* Chip Select Control Register A */ register8_t CTRLB; /* Chip Select Control Register B */ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; /* -------------------------------------------------------------------------- EBI - External Bus Interface -------------------------------------------------------------------------- */ /* External Bus Interface */ typedef struct EBI_struct { register8_t CTRL; /* Control */ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ register8_t reserved_0x02; register8_t reserved_0x03; _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ register8_t reserved_0x0A; register8_t reserved_0x0B; register8_t reserved_0x0C; register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; EBI_CS_t CS0; /* Chip Select 0 */ EBI_CS_t CS1; /* Chip Select 1 */ EBI_CS_t CS2; /* Chip Select 2 */ EBI_CS_t CS3; /* Chip Select 3 */ } EBI_t; /* Chip Select adress space */ typedef enum EBI_CS_ASIZE_enum { EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ } EBI_CS_ASIZE_t; /* */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; /* Chip Select address mode */ typedef enum EBI_CS_MODE_enum { EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ } EBI_CS_MODE_t; /* Chip Select SDRAM mode */ typedef enum EBI_CS_SDMODE_enum { EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ } EBI_CS_SDMODE_t; /* */ typedef enum EBI_SDDATAW_enum { EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ } EBI_SDDATAW_t; /* */ typedef enum EBI_LPCMODE_enum { EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ } EBI_LPCMODE_t; /* */ typedef enum EBI_SRMODE_enum { EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ } EBI_SRMODE_t; /* */ typedef enum EBI_IFMODE_enum { EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ } EBI_IFMODE_t; /* */ typedef enum EBI_SDCOL_enum { EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; /* */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; /* */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; /* */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; /* */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; /* */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; /* */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_MASTER_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t STATUS; /* Status Register */ register8_t BAUD; /* Baurd Rate Control Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ } TWI_MASTER_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* */ typedef struct TWI_SLAVE_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t STATUS; /* Status Register */ register8_t ADDR; /* Address Register */ register8_t DATA; /* Data Register */ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; /* -------------------------------------------------------------------------- TWI - Two-Wire Interface -------------------------------------------------------------------------- */ /* Two-Wire Interface */ typedef struct TWI_struct { register8_t CTRL; /* TWI Common Control Register */ TWI_MASTER_t MASTER; /* TWI master module */ TWI_SLAVE_t SLAVE; /* TWI slave module */ } TWI_t; /* Master Interrupt Level */ typedef enum TWI_MASTER_INTLVL_enum { TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_MASTER_INTLVL_t; /* Inactive Timeout */ typedef enum TWI_MASTER_TIMEOUT_enum { TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ } TWI_MASTER_TIMEOUT_t; /* Master Command */ typedef enum TWI_MASTER_CMD_enum { TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ } TWI_MASTER_CMD_t; /* Master Bus State */ typedef enum TWI_MASTER_BUSSTATE_enum { TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ } TWI_MASTER_BUSSTATE_t; /* Slave Interrupt Level */ typedef enum TWI_SLAVE_INTLVL_enum { TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ } TWI_SLAVE_INTLVL_t; /* Slave Command */ typedef enum TWI_SLAVE_CMD_enum { TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O port Configuration */ typedef struct PORTCFG_struct { register8_t MPCMASK; /* Multi-pin Configuration Mask */ register8_t reserved_0x01; register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ } PORTCFG_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* Virtual Port */ typedef struct VPORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t OUT; /* I/O Port Output */ register8_t IN; /* I/O Port Input */ register8_t INTFLAGS; /* Interrupt Flag Register */ } VPORT_t; /* -------------------------------------------------------------------------- PORT - Port Configuration -------------------------------------------------------------------------- */ /* I/O Ports */ typedef struct PORT_struct { register8_t DIR; /* I/O Port Data Direction */ register8_t DIRSET; /* I/O Port Data Direction Set */ register8_t DIRCLR; /* I/O Port Data Direction Clear */ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ register8_t OUT; /* I/O Port Output */ register8_t OUTSET; /* I/O Port Output Set */ register8_t OUTCLR; /* I/O Port Output Clear */ register8_t OUTTGL; /* I/O Port Output Toggle */ register8_t IN; /* I/O port Input */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t INT0MASK; /* Port Interrupt 0 Mask */ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ register8_t PIN2CTRL; /* Pin 2 Control Register */ register8_t PIN3CTRL; /* Pin 3 Control Register */ register8_t PIN4CTRL; /* Pin 4 Control Register */ register8_t PIN5CTRL; /* Pin 5 Control Register */ register8_t PIN6CTRL; /* Pin 6 Control Register */ register8_t PIN7CTRL; /* Pin 7 Control Register */ } PORT_t; /* Virtual Port 0 Mapping */ typedef enum PORTCFG_VP0MAP_enum { PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP0MAP_t; /* Virtual Port 1 Mapping */ typedef enum PORTCFG_VP1MAP_enum { PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP1MAP_t; /* Virtual Port 2 Mapping */ typedef enum PORTCFG_VP2MAP_enum { PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ } PORTCFG_VP2MAP_t; /* Virtual Port 3 Mapping */ typedef enum PORTCFG_VP3MAP_enum { PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ } PORTCFG_VP3MAP_t; /* Clock Output Port */ typedef enum PORTCFG_CLKOUT_enum { PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ } PORTCFG_CLKOUT_t; /* Event Output Port */ typedef enum PORTCFG_EVOUT_enum { PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; /* Port Interrupt 0 Level */ typedef enum PORT_INT0LVL_enum { PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ } PORT_INT0LVL_t; /* Port Interrupt 1 Level */ typedef enum PORT_INT1LVL_enum { PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ } PORT_INT1LVL_t; /* Output/Pull Configuration */ typedef enum PORT_OPC_enum { PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ } PORT_OPC_t; /* Input/Sense Configuration */ typedef enum PORT_ISC_enum { PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ } PORT_ISC_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 0 */ typedef struct TC0_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ _WORDREGISTER(CCC); /* Compare or Capture C */ _WORDREGISTER(CCD); /* Compare or Capture D */ register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct { register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control register C */ register8_t CTRLD; /* Control Register D */ register8_t CTRLE; /* Control Register E */ register8_t reserved_0x05; register8_t INTCTRLA; /* Interrupt Control Register A */ register8_t INTCTRLB; /* Interrupt Control Register B */ register8_t CTRLFCLR; /* Control Register F Clear */ register8_t CTRLFSET; /* Control Register F Set */ register8_t CTRLGCLR; /* Control Register G Clear */ register8_t CTRLGSET; /* Control Register G Set */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; register8_t reserved_0x0E; register8_t TEMP; /* Temporary Register For 16-bit Access */ register8_t reserved_0x10; register8_t reserved_0x11; register8_t reserved_0x12; register8_t reserved_0x13; register8_t reserved_0x14; register8_t reserved_0x15; register8_t reserved_0x16; register8_t reserved_0x17; register8_t reserved_0x18; register8_t reserved_0x19; register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; _WORDREGISTER(CNT); /* Count */ register8_t reserved_0x22; register8_t reserved_0x23; register8_t reserved_0x24; register8_t reserved_0x25; _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CCA); /* Compare or Capture A */ _WORDREGISTER(CCB); /* Compare or Capture B */ register8_t reserved_0x2C; register8_t reserved_0x2D; register8_t reserved_0x2E; register8_t reserved_0x2F; register8_t reserved_0x30; register8_t reserved_0x31; register8_t reserved_0x32; register8_t reserved_0x33; register8_t reserved_0x34; register8_t reserved_0x35; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ } TC1_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* Advanced Waveform Extension */ typedef struct AWEX_struct { register8_t CTRL; /* Control Register */ register8_t reserved_0x01; register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x05; register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ register8_t DTHS; /* Dead Time High Side */ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ register8_t DTHSBUF; /* Dead Time High Side Buffer */ register8_t OUTOVEN; /* Output Override Enable */ } AWEX_t; /* -------------------------------------------------------------------------- TC - 16-bit Timer/Counter With PWM -------------------------------------------------------------------------- */ /* High-Resolution Extension */ typedef struct HIRES_struct { register8_t CTRLA; /* Control Register */ } HIRES_t; /* Clock Selection */ typedef enum TC_CLKSEL_enum { TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_CLKSEL_t; /* Waveform Generation Mode */ typedef enum TC_WGMODE_enum { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; /* Event Action */ typedef enum TC_EVACT_enum { TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ } TC_EVACT_t; /* Event Selection */ typedef enum TC_EVSEL_enum { TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ } TC_EVSEL_t; /* Error Interrupt Level */ typedef enum TC_ERRINTLVL_enum { TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_ERRINTLVL_t; /* Overflow Interrupt Level */ typedef enum TC_OVFINTLVL_enum { TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_OVFINTLVL_t; /* Compare or Capture D Interrupt Level */ typedef enum TC_CCDINTLVL_enum { TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ } TC_CCDINTLVL_t; /* Compare or Capture C Interrupt Level */ typedef enum TC_CCCINTLVL_enum { TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ } TC_CCCINTLVL_t; /* Compare or Capture B Interrupt Level */ typedef enum TC_CCBINTLVL_enum { TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ } TC_CCBINTLVL_t; /* Compare or Capture A Interrupt Level */ typedef enum TC_CCAINTLVL_enum { TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ } TC_CCAINTLVL_t; /* Timer/Counter Command */ typedef enum TC_CMD_enum { TC_CMD_NONE_gc = (0x00<<2), /* No Command */ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ } TC_CMD_t; /* Fault Detect Action */ typedef enum AWEX_FDACT_enum { AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ } AWEX_FDACT_t; /* High Resolution Enable */ typedef enum HIRES_HREN_enum { HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ } HIRES_HREN_t; /* -------------------------------------------------------------------------- USART - Universal Asynchronous Receiver-Transmitter -------------------------------------------------------------------------- */ /* Universal Synchronous/Asynchronous Receiver/Transmitter */ typedef struct USART_struct { register8_t DATA; /* Data Register */ register8_t STATUS; /* Status Register */ register8_t reserved_0x02; register8_t CTRLA; /* Control Register A */ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ } USART_t; /* Receive Complete Interrupt level */ typedef enum USART_RXCINTLVL_enum { USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ } USART_RXCINTLVL_t; /* Transmit Complete Interrupt level */ typedef enum USART_TXCINTLVL_enum { USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ } USART_TXCINTLVL_t; /* Data Register Empty Interrupt level */ typedef enum USART_DREINTLVL_enum { USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ } USART_DREINTLVL_t; /* Character Size */ typedef enum USART_CHSIZE_enum { USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ } USART_CHSIZE_t; /* Communication Mode */ typedef enum USART_CMODE_enum { USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ } USART_CMODE_t; /* Parity Mode */ typedef enum USART_PMODE_enum { USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ } USART_PMODE_t; /* -------------------------------------------------------------------------- SPI - Serial Peripheral Interface -------------------------------------------------------------------------- */ /* Serial Peripheral Interface */ typedef struct SPI_struct { register8_t CTRL; /* Control Register */ register8_t INTCTRL; /* Interrupt Control Register */ register8_t STATUS; /* Status Register */ register8_t DATA; /* Data Register */ } SPI_t; /* SPI Mode */ typedef enum SPI_MODE_enum { SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ } SPI_MODE_t; /* Prescaler setting */ typedef enum SPI_PRESCALER_enum { SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ } SPI_PRESCALER_t; /* Interrupt level */ typedef enum SPI_INTLVL_enum { SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ } SPI_INTLVL_t; /* -------------------------------------------------------------------------- IRCOM - IR Communication Module -------------------------------------------------------------------------- */ /* IR Communication Module */ typedef struct IRCOM_struct { register8_t CTRL; /* Control Register */ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ } IRCOM_t; /* Event channel selection */ typedef enum IRDA_EVSEL_enum { IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ } IRDA_EVSEL_t; /* -------------------------------------------------------------------------- AES - AES Module -------------------------------------------------------------------------- */ /* AES Module */ typedef struct AES_struct { register8_t CTRL; /* AES Control Register */ register8_t STATUS; /* AES Status Register */ register8_t STATE; /* AES State Register */ register8_t KEY; /* AES Key Register */ register8_t INTCTRL; /* AES Interrupt Control Register */ } AES_t; /* Interrupt level */ typedef enum AES_INTLVL_enum { AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ } AES_INTLVL_t; /* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ #define RST (*(RST_t *) 0x0078) /* Reset Controller */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ #define PORTA (*(PORT_t *) 0x0600) /* Port A */ #define PORTB (*(PORT_t *) 0x0620) /* Port B */ #define PORTC (*(PORT_t *) 0x0640) /* Port C */ #define PORTD (*(PORT_t *) 0x0660) /* Port D */ #define PORTE (*(PORT_t *) 0x0680) /* Port E */ #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ #endif /* !defined (__ASSEMBLER__) */ /* ========== Flattened fully qualified IO register names ========== */ /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) #define GPIO_GPIOR2 _SFR_MEM8(0x0002) #define GPIO_GPIOR3 _SFR_MEM8(0x0003) #define GPIO_GPIOR4 _SFR_MEM8(0x0004) #define GPIO_GPIOR5 _SFR_MEM8(0x0005) #define GPIO_GPIOR6 _SFR_MEM8(0x0006) #define GPIO_GPIOR7 _SFR_MEM8(0x0007) #define GPIO_GPIOR8 _SFR_MEM8(0x0008) #define GPIO_GPIOR9 _SFR_MEM8(0x0009) #define GPIO_GPIORA _SFR_MEM8(0x000A) #define GPIO_GPIORB _SFR_MEM8(0x000B) #define GPIO_GPIORC _SFR_MEM8(0x000C) #define GPIO_GPIORD _SFR_MEM8(0x000D) #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) /* Deprecated */ #define GPIO_GPIO0 _SFR_MEM8(0x0000) #define GPIO_GPIO1 _SFR_MEM8(0x0001) #define GPIO_GPIO2 _SFR_MEM8(0x0002) #define GPIO_GPIO3 _SFR_MEM8(0x0003) #define GPIO_GPIO4 _SFR_MEM8(0x0004) #define GPIO_GPIO5 _SFR_MEM8(0x0005) #define GPIO_GPIO6 _SFR_MEM8(0x0006) #define GPIO_GPIO7 _SFR_MEM8(0x0007) #define GPIO_GPIO8 _SFR_MEM8(0x0008) #define GPIO_GPIO9 _SFR_MEM8(0x0009) #define GPIO_GPIOA _SFR_MEM8(0x000A) #define GPIO_GPIOB _SFR_MEM8(0x000B) #define GPIO_GPIOC _SFR_MEM8(0x000C) #define GPIO_GPIOD _SFR_MEM8(0x000D) #define GPIO_GPIOE _SFR_MEM8(0x000E) #define GPIO_GPIOF _SFR_MEM8(0x000F) /* VPORT0 - Virtual Port 0 */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) /* VPORT1 - Virtual Port 1 */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) /* VPORT2 - Virtual Port 2 */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) /* VPORT3 - Virtual Port 3 */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) /* OCD - On-Chip Debug System */ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) /* CPU - CPU Registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) #define CPU_RAMPY _SFR_MEM8(0x003A) #define CPU_RAMPZ _SFR_MEM8(0x003B) #define CPU_EIND _SFR_MEM8(0x003C) #define CPU_SPL _SFR_MEM8(0x003D) #define CPU_SPH _SFR_MEM8(0x003E) #define CPU_SREG _SFR_MEM8(0x003F) /* CLK - Clock System */ #define CLK_CTRL _SFR_MEM8(0x0040) #define CLK_PSCTRL _SFR_MEM8(0x0041) #define CLK_LOCK _SFR_MEM8(0x0042) #define CLK_RTCCTRL _SFR_MEM8(0x0043) /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) /* OSC - Oscillator Control */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) #define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) /* PR - Power Reduction */ #define PR_PRGEN _SFR_MEM8(0x0070) #define PR_PRPA _SFR_MEM8(0x0071) #define PR_PRPB _SFR_MEM8(0x0072) #define PR_PRPC _SFR_MEM8(0x0073) #define PR_PRPD _SFR_MEM8(0x0074) #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) /* RST - Reset Controller */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) /* WDT - Watch-Dog Timer */ #define WDT_CTRL _SFR_MEM8(0x0080) #define WDT_WINCTRL _SFR_MEM8(0x0081) #define WDT_STATUS _SFR_MEM8(0x0082) /* MCU - MCU Control */ #define MCU_DEVID0 _SFR_MEM8(0x0090) #define MCU_DEVID1 _SFR_MEM8(0x0091) #define MCU_DEVID2 _SFR_MEM8(0x0092) #define MCU_REVID _SFR_MEM8(0x0093) #define MCU_JTAGUID _SFR_MEM8(0x0094) #define MCU_MCUCR _SFR_MEM8(0x0096) #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) /* PMIC - Programmable Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) /* PORTCFG - Port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) /* AES - AES Crypto Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) /* DMA - DMA Controller */ #define DMA_CTRL _SFR_MEM8(0x0100) #define DMA_INTFLAGS _SFR_MEM8(0x0103) #define DMA_STATUS _SFR_MEM8(0x0104) #define DMA_TEMP _SFR_MEM16(0x0106) #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) /* EVSYS - Event System */ #define EVSYS_CH0MUX _SFR_MEM8(0x0180) #define EVSYS_CH1MUX _SFR_MEM8(0x0181) #define EVSYS_CH2MUX _SFR_MEM8(0x0182) #define EVSYS_CH3MUX _SFR_MEM8(0x0183) #define EVSYS_CH4MUX _SFR_MEM8(0x0184) #define EVSYS_CH5MUX _SFR_MEM8(0x0185) #define EVSYS_CH6MUX _SFR_MEM8(0x0186) #define EVSYS_CH7MUX _SFR_MEM8(0x0187) #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) /* NVM - Non Volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) #define NVM_DATA0 _SFR_MEM8(0x01C4) #define NVM_DATA1 _SFR_MEM8(0x01C5) #define NVM_DATA2 _SFR_MEM8(0x01C6) #define NVM_CMD _SFR_MEM8(0x01CA) #define NVM_CTRLA _SFR_MEM8(0x01CB) #define NVM_CTRLB _SFR_MEM8(0x01CC) #define NVM_INTCTRL _SFR_MEM8(0x01CD) #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) /* ADCA - Analog to Digital Converter A */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) #define ADCA_EVCTRL _SFR_MEM8(0x0203) #define ADCA_PRESCALER _SFR_MEM8(0x0204) #define ADCA_INTFLAGS _SFR_MEM8(0x0206) #define ADCA_CAL _SFR_MEM16(0x020C) #define ADCA_CH0RES _SFR_MEM16(0x0210) #define ADCA_CH1RES _SFR_MEM16(0x0212) #define ADCA_CH2RES _SFR_MEM16(0x0214) #define ADCA_CH3RES _SFR_MEM16(0x0216) #define ADCA_CMP _SFR_MEM16(0x0218) #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) /* ADCB - Analog to Digital Converter B */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) #define ADCB_EVCTRL _SFR_MEM8(0x0243) #define ADCB_PRESCALER _SFR_MEM8(0x0244) #define ADCB_INTFLAGS _SFR_MEM8(0x0246) #define ADCB_CAL _SFR_MEM16(0x024C) #define ADCB_CH0RES _SFR_MEM16(0x0250) #define ADCB_CH1RES _SFR_MEM16(0x0252) #define ADCB_CH2RES _SFR_MEM16(0x0254) #define ADCB_CH3RES _SFR_MEM16(0x0256) #define ADCB_CMP _SFR_MEM16(0x0258) #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) /* DACB - Digital to Analog Converter B */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) #define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_GAINCAL _SFR_MEM8(0x0328) #define DACB_OFFSETCAL _SFR_MEM8(0x0329) #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) /* ACA - Analog Comparator A */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) #define ACA_CTRLA _SFR_MEM8(0x0384) #define ACA_CTRLB _SFR_MEM8(0x0385) #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) /* ACB - Analog Comparator B */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) #define ACB_CTRLA _SFR_MEM8(0x0394) #define ACB_CTRLB _SFR_MEM8(0x0395) #define ACB_WINCTRL _SFR_MEM8(0x0396) #define ACB_STATUS _SFR_MEM8(0x0397) /* RTC - Real-Time Counter */ #define RTC_CTRL _SFR_MEM8(0x0400) #define RTC_STATUS _SFR_MEM8(0x0401) #define RTC_INTCTRL _SFR_MEM8(0x0402) #define RTC_INTFLAGS _SFR_MEM8(0x0403) #define RTC_TEMP _SFR_MEM8(0x0404) #define RTC_CNT _SFR_MEM16(0x0408) #define RTC_PER _SFR_MEM16(0x040A) #define RTC_COMP _SFR_MEM16(0x040C) /* TWIC - Two-Wire Interface C */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) /* TWIE - Two-Wire Interface E */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) /* PORTA - Port A */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) #define PORTA_DIRTGL _SFR_MEM8(0x0603) #define PORTA_OUT _SFR_MEM8(0x0604) #define PORTA_OUTSET _SFR_MEM8(0x0605) #define PORTA_OUTCLR _SFR_MEM8(0x0606) #define PORTA_OUTTGL _SFR_MEM8(0x0607) #define PORTA_IN _SFR_MEM8(0x0608) #define PORTA_INTCTRL _SFR_MEM8(0x0609) #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) /* PORTB - Port B */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) #define PORTB_DIRTGL _SFR_MEM8(0x0623) #define PORTB_OUT _SFR_MEM8(0x0624) #define PORTB_OUTSET _SFR_MEM8(0x0625) #define PORTB_OUTCLR _SFR_MEM8(0x0626) #define PORTB_OUTTGL _SFR_MEM8(0x0627) #define PORTB_IN _SFR_MEM8(0x0628) #define PORTB_INTCTRL _SFR_MEM8(0x0629) #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) /* PORTC - Port C */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) #define PORTC_DIRTGL _SFR_MEM8(0x0643) #define PORTC_OUT _SFR_MEM8(0x0644) #define PORTC_OUTSET _SFR_MEM8(0x0645) #define PORTC_OUTCLR _SFR_MEM8(0x0646) #define PORTC_OUTTGL _SFR_MEM8(0x0647) #define PORTC_IN _SFR_MEM8(0x0648) #define PORTC_INTCTRL _SFR_MEM8(0x0649) #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) /* PORTD - Port D */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) #define PORTD_DIRTGL _SFR_MEM8(0x0663) #define PORTD_OUT _SFR_MEM8(0x0664) #define PORTD_OUTSET _SFR_MEM8(0x0665) #define PORTD_OUTCLR _SFR_MEM8(0x0666) #define PORTD_OUTTGL _SFR_MEM8(0x0667) #define PORTD_IN _SFR_MEM8(0x0668) #define PORTD_INTCTRL _SFR_MEM8(0x0669) #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) /* PORTE - Port E */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) #define PORTE_DIRTGL _SFR_MEM8(0x0683) #define PORTE_OUT _SFR_MEM8(0x0684) #define PORTE_OUTSET _SFR_MEM8(0x0685) #define PORTE_OUTCLR _SFR_MEM8(0x0686) #define PORTE_OUTTGL _SFR_MEM8(0x0687) #define PORTE_IN _SFR_MEM8(0x0688) #define PORTE_INTCTRL _SFR_MEM8(0x0689) #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) /* PORTF - Port F */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) #define PORTF_DIRTGL _SFR_MEM8(0x06A3) #define PORTF_OUT _SFR_MEM8(0x06A4) #define PORTF_OUTSET _SFR_MEM8(0x06A5) #define PORTF_OUTCLR _SFR_MEM8(0x06A6) #define PORTF_OUTTGL _SFR_MEM8(0x06A7) #define PORTF_IN _SFR_MEM8(0x06A8) #define PORTF_INTCTRL _SFR_MEM8(0x06A9) #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) /* PORTR - Port R */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) #define PORTR_DIRTGL _SFR_MEM8(0x07E3) #define PORTR_OUT _SFR_MEM8(0x07E4) #define PORTR_OUTSET _SFR_MEM8(0x07E5) #define PORTR_OUTCLR _SFR_MEM8(0x07E6) #define PORTR_OUTTGL _SFR_MEM8(0x07E7) #define PORTR_IN _SFR_MEM8(0x07E8) #define PORTR_INTCTRL _SFR_MEM8(0x07E9) #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) /* TCC0 - Timer/Counter C0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) #define TCC0_CTRLD _SFR_MEM8(0x0803) #define TCC0_CTRLE _SFR_MEM8(0x0804) #define TCC0_INTCTRLA _SFR_MEM8(0x0806) #define TCC0_INTCTRLB _SFR_MEM8(0x0807) #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) #define TCC0_CTRLFSET _SFR_MEM8(0x0809) #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) #define TCC0_CTRLGSET _SFR_MEM8(0x080B) #define TCC0_INTFLAGS _SFR_MEM8(0x080C) #define TCC0_TEMP _SFR_MEM8(0x080F) #define TCC0_CNT _SFR_MEM16(0x0820) #define TCC0_PER _SFR_MEM16(0x0826) #define TCC0_CCA _SFR_MEM16(0x0828) #define TCC0_CCB _SFR_MEM16(0x082A) #define TCC0_CCC _SFR_MEM16(0x082C) #define TCC0_CCD _SFR_MEM16(0x082E) #define TCC0_PERBUF _SFR_MEM16(0x0836) #define TCC0_CCABUF _SFR_MEM16(0x0838) #define TCC0_CCBBUF _SFR_MEM16(0x083A) #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) /* TCC1 - Timer/Counter C1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) #define TCC1_CTRLD _SFR_MEM8(0x0843) #define TCC1_CTRLE _SFR_MEM8(0x0844) #define TCC1_INTCTRLA _SFR_MEM8(0x0846) #define TCC1_INTCTRLB _SFR_MEM8(0x0847) #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) #define TCC1_CTRLFSET _SFR_MEM8(0x0849) #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) #define TCC1_CTRLGSET _SFR_MEM8(0x084B) #define TCC1_INTFLAGS _SFR_MEM8(0x084C) #define TCC1_TEMP _SFR_MEM8(0x084F) #define TCC1_CNT _SFR_MEM16(0x0860) #define TCC1_PER _SFR_MEM16(0x0866) #define TCC1_CCA _SFR_MEM16(0x0868) #define TCC1_CCB _SFR_MEM16(0x086A) #define TCC1_PERBUF _SFR_MEM16(0x0876) #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) /* AWEXC - Advanced Waveform Extension C */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) #define AWEXC_DTHS _SFR_MEM8(0x0889) #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) /* HIRESC - High-Resolution Extension C */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) #define USARTC0_CTRLB _SFR_MEM8(0x08A4) #define USARTC0_CTRLC _SFR_MEM8(0x08A5) #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) #define USARTC1_CTRLB _SFR_MEM8(0x08B4) #define USARTC1_CTRLC _SFR_MEM8(0x08B5) #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) /* SPIC - Serial Peripheral Interface C */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) #define SPIC_DATA _SFR_MEM8(0x08C3) /* IRCOM - IR Communication Module */ #define IRCOM_CTRL _SFR_MEM8(0x08F8) #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) /* TCD0 - Timer/Counter D0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) #define TCD0_CTRLD _SFR_MEM8(0x0903) #define TCD0_CTRLE _SFR_MEM8(0x0904) #define TCD0_INTCTRLA _SFR_MEM8(0x0906) #define TCD0_INTCTRLB _SFR_MEM8(0x0907) #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) #define TCD0_CTRLFSET _SFR_MEM8(0x0909) #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) #define TCD0_CTRLGSET _SFR_MEM8(0x090B) #define TCD0_INTFLAGS _SFR_MEM8(0x090C) #define TCD0_TEMP _SFR_MEM8(0x090F) #define TCD0_CNT _SFR_MEM16(0x0920) #define TCD0_PER _SFR_MEM16(0x0926) #define TCD0_CCA _SFR_MEM16(0x0928) #define TCD0_CCB _SFR_MEM16(0x092A) #define TCD0_CCC _SFR_MEM16(0x092C) #define TCD0_CCD _SFR_MEM16(0x092E) #define TCD0_PERBUF _SFR_MEM16(0x0936) #define TCD0_CCABUF _SFR_MEM16(0x0938) #define TCD0_CCBBUF _SFR_MEM16(0x093A) #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) /* TCD1 - Timer/Counter D1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) #define TCD1_CTRLD _SFR_MEM8(0x0943) #define TCD1_CTRLE _SFR_MEM8(0x0944) #define TCD1_INTCTRLA _SFR_MEM8(0x0946) #define TCD1_INTCTRLB _SFR_MEM8(0x0947) #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) #define TCD1_CTRLFSET _SFR_MEM8(0x0949) #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) #define TCD1_CTRLGSET _SFR_MEM8(0x094B) #define TCD1_INTFLAGS _SFR_MEM8(0x094C) #define TCD1_TEMP _SFR_MEM8(0x094F) #define TCD1_CNT _SFR_MEM16(0x0960) #define TCD1_PER _SFR_MEM16(0x0966) #define TCD1_CCA _SFR_MEM16(0x0968) #define TCD1_CCB _SFR_MEM16(0x096A) #define TCD1_PERBUF _SFR_MEM16(0x0976) #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) /* HIRESD - High-Resolution Extension D */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) #define USARTD0_CTRLB _SFR_MEM8(0x09A4) #define USARTD0_CTRLC _SFR_MEM8(0x09A5) #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) #define USARTD1_CTRLB _SFR_MEM8(0x09B4) #define USARTD1_CTRLC _SFR_MEM8(0x09B5) #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) /* SPID - Serial Peripheral Interface D */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) /* TCE0 - Timer/Counter E0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) #define TCE0_CTRLD _SFR_MEM8(0x0A03) #define TCE0_CTRLE _SFR_MEM8(0x0A04) #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) #define TCE0_TEMP _SFR_MEM8(0x0A0F) #define TCE0_CNT _SFR_MEM16(0x0A20) #define TCE0_PER _SFR_MEM16(0x0A26) #define TCE0_CCA _SFR_MEM16(0x0A28) #define TCE0_CCB _SFR_MEM16(0x0A2A) #define TCE0_CCC _SFR_MEM16(0x0A2C) #define TCE0_CCD _SFR_MEM16(0x0A2E) #define TCE0_PERBUF _SFR_MEM16(0x0A36) #define TCE0_CCABUF _SFR_MEM16(0x0A38) #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) /* TCE1 - Timer/Counter E1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) #define TCE1_CTRLD _SFR_MEM8(0x0A43) #define TCE1_CTRLE _SFR_MEM8(0x0A44) #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) #define TCE1_TEMP _SFR_MEM8(0x0A4F) #define TCE1_CNT _SFR_MEM16(0x0A60) #define TCE1_PER _SFR_MEM16(0x0A66) #define TCE1_CCA _SFR_MEM16(0x0A68) #define TCE1_CCB _SFR_MEM16(0x0A6A) #define TCE1_PERBUF _SFR_MEM16(0x0A76) #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) /* AWEXE - Advanced Waveform Extension E */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) #define AWEXE_DTHS _SFR_MEM8(0x0A89) #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) /* HIRESE - High-Resolution Extension E */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) /* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) #define USARTE1_CTRLB _SFR_MEM8(0x0AB4) #define USARTE1_CTRLC _SFR_MEM8(0x0AB5) #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) /* SPIE - Serial Peripheral Interface E */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) /* TCF0 - Timer/Counter F0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) #define TCF0_CTRLD _SFR_MEM8(0x0B03) #define TCF0_CTRLE _SFR_MEM8(0x0B04) #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) #define TCF0_TEMP _SFR_MEM8(0x0B0F) #define TCF0_CNT _SFR_MEM16(0x0B20) #define TCF0_PER _SFR_MEM16(0x0B26) #define TCF0_CCA _SFR_MEM16(0x0B28) #define TCF0_CCB _SFR_MEM16(0x0B2A) #define TCF0_CCC _SFR_MEM16(0x0B2C) #define TCF0_CCD _SFR_MEM16(0x0B2E) #define TCF0_PERBUF _SFR_MEM16(0x0B36) #define TCF0_CCABUF _SFR_MEM16(0x0B38) #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) /* HIRESF - High-Resolution Extension F */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) /* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) #define USARTF1_CTRLB _SFR_MEM8(0x0BB4) #define USARTF1_CTRLC _SFR_MEM8(0x0BB5) #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) /* SPIF - Serial Peripheral Interface F */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) #define SPIF_DATA _SFR_MEM8(0x0BC3) /*================== Bitfield Definitions ================== */ /* XOCD - On-Chip Debug System */ /* OCD.OCDR1 bit masks and bit positions */ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ #define CPU_CCP_gp 0 /* CCP signature group position. */ #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ #define CPU_T_bp 6 /* Transfer Bit bit position. */ #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ #define CPU_H_bp 5 /* Half Carry Flag bit position. */ #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ #define CPU_N_bp 2 /* Negative Flag bit position. */ #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ #define CPU_Z_bp 1 /* Zero Flag bit position. */ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_AES_bm 0x10 /* AES bit mask. */ #define PR_AES_bp 4 /* AES bit position. */ #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ #define PR_EBI_bp 3 /* External Bus Interface bit position. */ #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ #define PR_RTC_bp 2 /* Real-time Counter bit position. */ #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ #define PR_EVSYS_bp 1 /* Event System bit position. */ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ #define PR_ADC_bp 1 /* Port A ADC bit position. */ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ /* PR.PRPB bit masks and bit positions */ /* PR_DAC_bm Predefined. */ /* PR_DAC_bp Predefined. */ /* PR_ADC_bm Predefined. */ /* PR_ADC_bp Predefined. */ /* PR_AC_bm Predefined. */ /* PR_AC_bp Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ #define PR_USART1_bp 5 /* Port C USART1 bit position. */ #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ #define PR_USART0_bp 4 /* Port C USART0 bit position. */ #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ #define PR_SPI_bp 3 /* Port C SPI bit position. */ #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPE bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* PR.PRPF bit masks and bit positions */ /* PR_TWI_bm Predefined. */ /* PR_TWI_bp Predefined. */ /* PR_USART1_bm Predefined. */ /* PR_USART1_bp Predefined. */ /* PR_USART0_bm Predefined. */ /* PR_USART0_bp Predefined. */ /* PR_SPI_bm Predefined. */ /* PR_SPI_bp Predefined. */ /* PR_HIRES_bm Predefined. */ /* PR_HIRES_bp Predefined. */ /* PR_TC1_bm Predefined. */ /* PR_TC1_bp Predefined. */ /* PR_TC0_bm Predefined. */ /* PR_TC0_bp Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ /* OSC.DFLLCTRL bit masks and bit positions */ #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ #define WDT_PER_gp 2 /* Period group position. */ #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ #define WDT_PER0_bp 2 /* Period bit 0 position. */ #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ #define WDT_PER1_bp 3 /* Period bit 1 position. */ #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ #define WDT_PER2_bp 4 /* Period bit 2 position. */ #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ #define WDT_PER3_bp 5 /* Period bit 3 position. */ #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ #define WDT_ENABLE_bp 1 /* Enable bit position. */ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ /* MCU.AWEXLOCK bit masks and bit positions */ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ #define DMA_RESET_bp 6 /* Software Reset bit position. */ #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ /* EVSYS.CH1MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ /* EVSYS_CHMUX_gm Predefined. */ /* EVSYS_CHMUX_gp Predefined. */ /* EVSYS_CHMUX0_bm Predefined. */ /* EVSYS_CHMUX0_bp Predefined. */ /* EVSYS_CHMUX1_bm Predefined. */ /* EVSYS_CHMUX1_bp Predefined. */ /* EVSYS_CHMUX2_bm Predefined. */ /* EVSYS_CHMUX2_bp Predefined. */ /* EVSYS_CHMUX3_bm Predefined. */ /* EVSYS_CHMUX3_bp Predefined. */ /* EVSYS_CHMUX4_bm Predefined. */ /* EVSYS_CHMUX4_bp Predefined. */ /* EVSYS_CHMUX5_bm Predefined. */ /* EVSYS_CHMUX5_bp Predefined. */ /* EVSYS_CHMUX6_bm Predefined. */ /* EVSYS_CHMUX6_bp Predefined. */ /* EVSYS_CHMUX7_bm Predefined. */ /* EVSYS_CHMUX7_bp Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ /* EVSYS.CH1CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH3CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ /* EVSYS_QDIRM_gm Predefined. */ /* EVSYS_QDIRM_gp Predefined. */ /* EVSYS_QDIRM0_bm Predefined. */ /* EVSYS_QDIRM0_bp Predefined. */ /* EVSYS_QDIRM1_bm Predefined. */ /* EVSYS_QDIRM1_bp Predefined. */ /* EVSYS_QDIEN_bm Predefined. */ /* EVSYS_QDIEN_bp Predefined. */ /* EVSYS_QDEN_bm Predefined. */ /* EVSYS_QDEN_bp Predefined. */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH5CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH6CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ /* EVSYS_DIGFILT_gm Predefined. */ /* EVSYS_DIGFILT_gp Predefined. */ /* EVSYS_DIGFILT0_bm Predefined. */ /* EVSYS_DIGFILT0_bp Predefined. */ /* EVSYS_DIGFILT1_bm Predefined. */ /* EVSYS_DIGFILT1_bp Predefined. */ /* EVSYS_DIGFILT2_bm Predefined. */ /* EVSYS_DIGFILT2_bp Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ #define NVM_CMD_gm 0xFF /* Command group mask. */ #define NVM_CMD_gp 0 /* Command group position. */ #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define NVM_CMD0_bp 0 /* Command bit 0 position. */ #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define NVM_CMD1_bp 1 /* Command bit 1 position. */ #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ #define NVM_CMD2_bp 2 /* Command bit 2 position. */ #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ #define NVM_CMD3_bp 3 /* Command bit 3 position. */ #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ #define NVM_CMD4_bp 4 /* Command bit 4 position. */ #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ #define NVM_CMD5_bp 5 /* Command bit 5 position. */ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ #define NVM_CMD7_bp 7 /* Command bit 7 position. */ /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LB_gp 0 /* Lock Bits group position. */ #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ #define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ #define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ #define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ #define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ #define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ #define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ #define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ #define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ #define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ #define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ #define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ #define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ #define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ #define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ #define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ #define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ #define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ #define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ #define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ #define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ /* AC.AC1CTRL bit masks and bit positions */ /* AC_INTMODE_gm Predefined. */ /* AC_INTMODE_gp Predefined. */ /* AC_INTMODE0_bm Predefined. */ /* AC_INTMODE0_bp Predefined. */ /* AC_INTMODE1_bm Predefined. */ /* AC_INTMODE1_bp Predefined. */ /* AC_INTLVL_gm Predefined. */ /* AC_INTLVL_gp Predefined. */ /* AC_INTLVL0_bm Predefined. */ /* AC_INTLVL0_bp Predefined. */ /* AC_INTLVL1_bm Predefined. */ /* AC_INTLVL1_bp Predefined. */ /* AC_HSMODE_bm Predefined. */ /* AC_HSMODE_bp Predefined. */ /* AC_HYSMODE_gm Predefined. */ /* AC_HYSMODE_gp Predefined. */ /* AC_HYSMODE0_bm Predefined. */ /* AC_HYSMODE0_bp Predefined. */ /* AC_HYSMODE1_bm Predefined. */ /* AC_HYSMODE1_bp Predefined. */ /* AC_ENABLE_bm Predefined. */ /* AC_ENABLE_bp Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ /* AC.AC1MUXCTRL bit masks and bit positions */ /* AC_MUXPOS_gm Predefined. */ /* AC_MUXPOS_gp Predefined. */ /* AC_MUXPOS0_bm Predefined. */ /* AC_MUXPOS0_bp Predefined. */ /* AC_MUXPOS1_bm Predefined. */ /* AC_MUXPOS1_bp Predefined. */ /* AC_MUXPOS2_bm Predefined. */ /* AC_MUXPOS2_bp Predefined. */ /* AC_MUXNEG_gm Predefined. */ /* AC_MUXNEG_gp Predefined. */ /* AC_MUXNEG0_bm Predefined. */ /* AC_MUXNEG0_bp Predefined. */ /* AC_MUXNEG1_bm Predefined. */ /* AC_MUXNEG1_bp Predefined. */ /* AC_MUXNEG2_bm Predefined. */ /* AC_MUXNEG2_bp Predefined. */ /* AC.CTRLA bit masks and bit positions */ #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ /* ADC.CTRLB bit masks and bit positions */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ #define ADC_EVACT_gp 0 /* Event Action Select group position. */ #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ /* DAC.TIMCTRL bit masks and bit positions */ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ /* RTC - Real-Time Clounter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ /* TWI_MASTER.CTRLB bit masks and bit positions */ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ #define TWI_MASTER_CMD_gp 0 /* Command group position. */ #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ /* TWI.CTRL bit masks and bit positions */ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ /* PORT - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ /* VPORT.INTFLAGS bit masks and bit positions */ #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ /* PORT.PIN1CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ /* PORT_SRLEN_bm Predefined. */ /* PORT_SRLEN_bp Predefined. */ /* PORT_INVEN_bm Predefined. */ /* PORT_INVEN_bp Predefined. */ /* PORT_OPC_gm Predefined. */ /* PORT_OPC_gp Predefined. */ /* PORT_OPC0_bm Predefined. */ /* PORT_OPC0_bp Predefined. */ /* PORT_OPC1_bm Predefined. */ /* PORT_OPC1_bp Predefined. */ /* PORT_OPC2_bm Predefined. */ /* PORT_OPC2_bp Predefined. */ /* PORT_ISC_gm Predefined. */ /* PORT_ISC_gp Predefined. */ /* PORT_ISC0_bm Predefined. */ /* PORT_ISC0_bp Predefined. */ /* PORT_ISC1_bm Predefined. */ /* PORT_ISC1_bp Predefined. */ /* PORT_ISC2_bm Predefined. */ /* PORT_ISC2_bp Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC0.CTRLE bit masks and bit positions */ #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC0_CMD0_bp 2 /* Command bit 0 position. */ #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC0_CMD1_bp 3 /* Command bit 1 position. */ #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC0_LUPD_bp 1 /* Lock Update bit position. */ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ /* TC0.CTRLFSET bit masks and bit positions */ /* TC0_CMD_gm Predefined. */ /* TC0_CMD_gp Predefined. */ /* TC0_CMD0_bm Predefined. */ /* TC0_CMD0_bp Predefined. */ /* TC0_CMD1_bm Predefined. */ /* TC0_CMD1_bp Predefined. */ /* TC0_LUPD_bm Predefined. */ /* TC0_LUPD_bp Predefined. */ /* TC0_DIR_bm Predefined. */ /* TC0_DIR_bp Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC0.CTRLGSET bit masks and bit positions */ /* TC0_CCDBV_bm Predefined. */ /* TC0_CCDBV_bp Predefined. */ /* TC0_CCCBV_bm Predefined. */ /* TC0_CCCBV_bp Predefined. */ /* TC0_CCBBV_bm Predefined. */ /* TC0_CCBBV_bp Predefined. */ /* TC0_CCABV_bm Predefined. */ /* TC0_CCABV_bp Predefined. */ /* TC0_PERBV_bm Predefined. */ /* TC0_PERBV_bp Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ /* TC1.CTRLE bit masks and bit positions */ #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ #define TC1_CMD0_bp 2 /* Command bit 0 position. */ #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ #define TC1_CMD1_bp 3 /* Command bit 1 position. */ #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ #define TC1_LUPD_bp 1 /* Lock Update bit position. */ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ /* TC1.CTRLFSET bit masks and bit positions */ /* TC1_CMD_gm Predefined. */ /* TC1_CMD_gp Predefined. */ /* TC1_CMD0_bm Predefined. */ /* TC1_CMD0_bp Predefined. */ /* TC1_CMD1_bm Predefined. */ /* TC1_CMD1_bp Predefined. */ /* TC1_LUPD_bm Predefined. */ /* TC1_LUPD_bp Predefined. */ /* TC1_DIR_bm Predefined. */ /* TC1_DIR_bp Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ /* TC1.CTRLGSET bit masks and bit positions */ /* TC1_CCBBV_bm Predefined. */ /* TC1_CCBBV_bp Predefined. */ /* TC1_CCABV_bm Predefined. */ /* TC1_CCABV_bp Predefined. */ /* TC1_PERBV_bm Predefined. */ /* TC1_PERBV_bp Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ /* AWEX.CTRL bit masks and bit positions */ #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ /* HIRES.CTRL bit masks and bit positions */ #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ #define USART_FERR_bp 4 /* Frame Error bit position. */ #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ #define USART_PERR_bp 2 /* Parity Error bit position. */ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ #define USART_PMODE_gp 4 /* Parity Mode group position. */ #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ #define USART_CHSIZE_gp 0 /* Character Size group position. */ #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ /* USART_BSEL_gm Predefined. */ /* USART_BSEL_gp Predefined. */ /* USART_BSEL0_bm Predefined. */ /* USART_BSEL0_bp Predefined. */ /* USART_BSEL1_bm Predefined. */ /* USART_BSEL1_bp Predefined. */ /* USART_BSEL2_bm Predefined. */ /* USART_BSEL2_bp Predefined. */ /* USART_BSEL3_bm Predefined. */ /* USART_BSEL3_bp Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ #define SPI_MODE_gp 2 /* SPI Mode group position. */ #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ #define AES_START_bm 0x80 /* Start/Run bit mask. */ #define AES_START_bp 7 /* Start/Run bit position. */ #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ #define AES_RESET_bp 5 /* AES Software Reset bit position. */ #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ // Generic Port Pins #define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 #define PIN2_bm 0x04 #define PIN2_bp 2 #define PIN3_bm 0x08 #define PIN3_bp 3 #define PIN4_bm 0x10 #define PIN4_bp 4 #define PIN5_bm 0x20 #define PIN5_bp 5 #define PIN6_bm 0x40 #define PIN6_bp 6 #define PIN7_bm 0x80 #define PIN7_bp 7 /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ /* OSC interrupt vectors */ #define OSC_XOSCF_vect_num 1 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ /* PORTC interrupt vectors */ #define PORTC_INT0_vect_num 2 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ #define PORTC_INT1_vect_num 3 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ /* PORTR interrupt vectors */ #define PORTR_INT0_vect_num 4 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ #define PORTR_INT1_vect_num 5 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ /* DMA interrupt vectors */ #define DMA_CH0_vect_num 6 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ #define DMA_CH1_vect_num 7 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ #define DMA_CH2_vect_num 8 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ #define DMA_CH3_vect_num 9 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ /* RTC interrupt vectors */ #define RTC_OVF_vect_num 10 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ #define RTC_COMP_vect_num 11 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ /* TWIC interrupt vectors */ #define TWIC_TWIS_vect_num 12 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ #define TWIC_TWIM_vect_num 13 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ #define TCC1_ERR_vect_num 21 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ #define TCC1_CCA_vect_num 22 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ #define TCC1_CCB_vect_num 23 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ /* SPIC interrupt vectors */ #define SPIC_INT_vect_num 24 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ /* USARTC0 interrupt vectors */ #define USARTC0_RXC_vect_num 25 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ #define USARTC0_DRE_vect_num 26 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ #define USARTC0_TXC_vect_num 27 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ /* USARTC1 interrupt vectors */ #define USARTC1_RXC_vect_num 28 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ #define USARTC1_DRE_vect_num 29 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ #define USARTC1_TXC_vect_num 30 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ /* AES interrupt vectors */ #define AES_INT_vect_num 31 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ /* NVM interrupt vectors */ #define NVM_EE_vect_num 32 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ #define NVM_SPM_vect_num 33 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ /* PORTB interrupt vectors */ #define PORTB_INT0_vect_num 34 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ #define PORTB_INT1_vect_num 35 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ /* ACB interrupt vectors */ #define ACB_AC0_vect_num 36 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ #define ACB_AC1_vect_num 37 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ #define ACB_ACW_vect_num 38 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ /* ADCB interrupt vectors */ #define ADCB_CH0_vect_num 39 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ #define ADCB_CH1_vect_num 40 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ #define ADCB_CH2_vect_num 41 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ #define ADCB_CH3_vect_num 42 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ /* PORTE interrupt vectors */ #define PORTE_INT0_vect_num 43 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ #define PORTE_INT1_vect_num 44 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ /* TWIE interrupt vectors */ #define TWIE_TWIS_vect_num 45 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ #define TWIE_TWIM_vect_num 46 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ #define TCE1_ERR_vect_num 54 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ #define TCE1_CCA_vect_num 55 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ #define TCE1_CCB_vect_num 56 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ /* SPIE interrupt vectors */ #define SPIE_INT_vect_num 57 #define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ /* USARTE0 interrupt vectors */ #define USARTE0_RXC_vect_num 58 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ #define USARTE0_DRE_vect_num 59 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ #define USARTE0_TXC_vect_num 60 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ /* USARTE1 interrupt vectors */ #define USARTE1_RXC_vect_num 61 #define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ #define USARTE1_DRE_vect_num 62 #define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ #define USARTE1_TXC_vect_num 63 #define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ /* PORTD interrupt vectors */ #define PORTD_INT0_vect_num 64 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ #define PORTD_INT1_vect_num 65 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ /* PORTA interrupt vectors */ #define PORTA_INT0_vect_num 66 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ #define PORTA_INT1_vect_num 67 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ /* ACA interrupt vectors */ #define ACA_AC0_vect_num 68 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ #define ACA_AC1_vect_num 69 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ #define ACA_ACW_vect_num 70 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ /* ADCA interrupt vectors */ #define ADCA_CH0_vect_num 71 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ #define ADCA_CH1_vect_num 72 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ #define ADCA_CH2_vect_num 73 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ #define ADCA_CH3_vect_num 74 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ #define TCD1_ERR_vect_num 84 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ #define TCD1_CCA_vect_num 85 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ #define TCD1_CCB_vect_num 86 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ /* SPID interrupt vectors */ #define SPID_INT_vect_num 87 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ /* USARTD0 interrupt vectors */ #define USARTD0_RXC_vect_num 88 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ #define USARTD0_DRE_vect_num 89 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ #define USARTD0_TXC_vect_num 90 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ /* USARTD1 interrupt vectors */ #define USARTD1_RXC_vect_num 91 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ #define USARTD1_DRE_vect_num 92 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ #define USARTD1_TXC_vect_num 93 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ /* PORTF interrupt vectors */ #define PORTF_INT0_vect_num 104 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ #define PORTF_INT1_vect_num 105 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ /* USARTF0 interrupt vectors */ #define USARTF0_RXC_vect_num 119 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ #define USARTF0_DRE_vect_num 120 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ #define USARTF0_TXC_vect_num 121 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ #define _VECTOR_SIZE 4 /* Size of individual vector. */ #define _VECTORS_SIZE (122 * _VECTOR_SIZE) /* ========== Constants ========== */ #define PROGMEM_START (0x0000) #define PROGMEM_SIZE (270336) #define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) #define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (262144) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) #define APPTABLE_SECTION_START (0x3E000) #define APPTABLE_SECTION_SIZE (8192) #define APPTABLE_SECTION_PAGE_SIZE (512) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) #define BOOT_SECTION_START (0x40000) #define BOOT_SECTION_SIZE (8192) #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (24576) #define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) #define IO_SIZE (4096) #define IO_PAGE_SIZE (0) #define IO_END (IO_START + IO_SIZE - 1) #define MAPPED_EEPROM_START (0x1000) #define MAPPED_EEPROM_SIZE (4096) #define MAPPED_EEPROM_PAGE_SIZE (0) #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) #define INTERNAL_SRAM_START (0x2000) #define INTERNAL_SRAM_SIZE (16384) #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) #define EEPROM_START (0x0000) #define EEPROM_SIZE (4096) #define EEPROM_PAGE_SIZE (32) #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define FUSE_START (0x0000) #define FUSE_SIZE (6) #define FUSE_PAGE_SIZE (0) #define FUSE_END (FUSE_START + FUSE_SIZE - 1) #define LOCKBIT_START (0x0000) #define LOCKBIT_SIZE (1) #define LOCKBIT_PAGE_SIZE (0) #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) #define USER_SIGNATURES_PAGE_SIZE (0) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) #define PROD_SIGNATURES_SIZE (52) #define PROD_SIGNATURES_PAGE_SIZE (0) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) #define FLASHEND PROGMEM_END #define SPM_PAGESIZE PROGMEM_PAGE_SIZE #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END #define XRAMSTART EXTERNAL_SRAM_START #define XRAMSIZE EXTERNAL_SRAM_SIZE #define XRAMEND INTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ #define FUSE_MEMORY_SIZE 6 /* Fuse Byte 0 */ #define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ #define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ #define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ #define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ #define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ #define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ #define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ #define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ #define FUSE0_DEFAULT (0xFF) /* Fuse Byte 1 */ #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ #define FUSE1_DEFAULT (0xFF) /* Fuse Byte 2 */ #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ #define FUSE2_DEFAULT (0xFF) /* Fuse Byte 3 Reserved */ /* Fuse Byte 4 */ #define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ #define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x98 #define SIGNATURE_2 0x42 #endif /* _AVR_ATxmega256A3_H_ */ avr-libc-1.8.0.orig/include/avr/iotn5.h0000644000000000000000000002436111732702554014502 0ustar /* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn5.h 2063 2009-11-18 22:06:28Z arcanum $ */ /* avr/iotn5.h - definitions for ATtiny5 */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn5.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_ATtiny5_H_ #define _AVR_ATtiny5_H_ 1 /* Registers and associated bit numbers. */ #define PINB _SFR_IO8(0x00) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define DDRB _SFR_IO8(0x01) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define PORTB _SFR_IO8(0x02) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PUEB _SFR_IO8(0x03) #define PUEB0 0 #define PUEB1 1 #define PUEB2 2 #define PUEB3 3 #define PORTCR _SFR_IO8(0x0C) #define BBMB 1 #define PCMSK _SFR_IO8(0x10) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCIFR _SFR_IO8(0x11) #define PCIF0 0 #define PCICR _SFR_IO8(0x12) #define PCIE0 0 #define EIMSK _SFR_IO8(0x13) #define INT0 0 #define EIFR _SFR_IO8(0x14) #define INTF0 0 #define EICRA _SFR_IO8(0x15) #define ISC00 0 #define ISC01 1 #define DIDR0 _SFR_IO8(0x17) #define ADC0D 0 #define AIN0D 0 #define ADC1D 1 #define AIN1D 1 #define ADC2D 2 #define ADC3D 3 #define ADCL _SFR_IO8(0x19) #define ADC0 0 #define ADC1 1 #define ADC2 2 #define ADC3 3 #define ADC4 4 #define ADC5 5 #define ADC6 6 #define ADC7 7 #define ADMUX _SFR_IO8(0x1B) #define MUX0 0 #define MUX1 1 #define ADCSRB _SFR_IO8(0x1C) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADCSRA _SFR_IO8(0x1D) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ACSR _SFR_IO8(0x1F) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACD 7 #define ICR0 _SFR_IO16(0x22) #define ICR0L _SFR_IO8(0x22) #define ICR0_0 0 #define ICR0_1 1 #define ICR0_2 2 #define ICR0_3 3 #define ICR0_4 4 #define ICR0_5 5 #define ICR0_6 6 #define ICR0_7 7 #define ICR0H _SFR_IO8(0x23) #define ICR0_8 0 #define ICR0_9 1 #define ICR0_10 2 #define ICR0_11 3 #define ICR0_12 4 #define ICR0_13 5 #define ICR0_14 6 #define ICR0_15 7 #define OCR0B _SFR_IO16(0x24) #define OCR0BL _SFR_IO8(0x24) #define OCR0B0 0 #define OCR0B1 1 #define OCR0B2 2 #define OCR0B3 3 #define OCR0B4 4 #define OCR0B5 5 #define OCR0B6 6 #define OCR0B7 7 #define OCR0BH _SFR_IO8(0x25) #define OCR0B8 0 #define OCR0B9 1 #define OCR0B10 2 #define OCR0B11 3 #define OCR0B12 4 #define OCR0B13 5 #define OCR0B14 6 #define OCR0B15 7 #define OCR0A _SFR_IO16(0x26) #define OCR0AL _SFR_IO8(0x26) #define OCR0A0 0 #define OCR0A1 1 #define OCR0A2 2 #define OCR0A3 3 #define OCR0A4 4 #define OCR0A5 5 #define OCR0A6 6 #define OCR0A7 7 #define OCR0AH _SFR_IO8(0x27) #define OCR0A8 0 #define OCR0A9 1 #define OCR0A10 2 #define OCR0A11 3 #define OCR0A12 4 #define OCR0A13 5 #define OCR0A14 6 #define OCR0A15 7 #define TCNT0 _SFR_IO16(0x28) #define TCNT0L _SFR_IO8(0x28) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCNT0H _SFR_IO8(0x29) #define TCNT0_8 0 #define TCNT0_9 1 #define TCNT0_10 2 #define TCNT0_11 3 #define TCNT0_12 4 #define TCNT0_13 5 #define TCNT0_14 6 #define TCNT0_15 7 #define TIFR0 _SFR_IO8(0x2A) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define ICF0 5 #define TIMSK0 _SFR_IO8(0x2B) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define ICIE0 5 #define TCCR0C _SFR_IO8(0x2C) #define FOC0B 6 #define FOC0A 7 #define TCCR0B _SFR_IO8(0x2D) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define WGM03 4 #define ICES0 6 #define ICNC0 7 #define TCCR0A _SFR_IO8(0x2E) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define GTCCR _SFR_IO8(0x2F) #define PSR 0 #define TSM 7 #define WDTCSR _SFR_IO8(0x31) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDP3 5 #define WDIE 6 #define WDIF 7 #define NVMCSR _SFR_IO8(0x32) #define NVMBSY 7 #define NVMCMD _SFR_IO8(0x33) #define NVMCMD0 0 #define NVMCMD1 1 #define NVMCMD2 2 #define NVMCMD3 3 #define NVMCMD4 4 #define NVMCMD5 5 #define VLMCSR _SFR_IO8(0x34) #define VLM0 0 #define VLM1 1 #define VLM2 2 #define VLMIE 6 #define VLMF 7 #define PRR _SFR_IO8(0x35) #define PRTIM0 0 #define PRADC 1 #define CLKPSR _SFR_IO8(0x36) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKMSR _SFR_IO8(0x37) #define CLKMS0 0 #define CLKMS1 1 #define OSCCAL _SFR_IO8(0x39) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define SMCR _SFR_IO8(0x3A) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define RSTFLR _SFR_IO8(0x3B) #define PORF 0 #define EXTRF 1 #define WDRF 3 #define CCP _SFR_IO8(0x3C) #define CCP0 0 #define CCP1 1 #define CCP2 2 #define CCP3 3 #define CCP4 4 #define CCP5 5 #define CCP6 6 #define CCP7 7 /* Interrupt vectors */ /* Vector 0 is the reset vector */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ #define TIM0_CAPT_vect_num 3 #define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ #define TIM0_OVF_vect_num 4 #define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ #define TIM0_COMPA_vect_num 5 #define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ #define TIM0_COMPB_vect_num 6 #define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ #define ANA_COMP_vect_num 7 #define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ #define WDT_vect_num 8 #define WDT_vect _VECTOR(8) /* Watchdog Time-out */ #define VLM_vect_num 9 #define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ #define ADC_vect_num 10 #define ADC_vect _VECTOR(10) /* ADC Conversion Complete */ #define _VECTOR_SIZE 2 /* Size of individual vector. */ #define _VECTORS_SIZE (11 * _VECTOR_SIZE) /* Constants */ #define SPM_PAGESIZE (32) #define RAMSTART (0x40) #define RAMSIZE (32) #define RAMEND (RAMSTART + RAMSIZE - 1) #define XRAMSTART (NA) #define XRAMSIZE (0) #define XRAMEND (RAMEND) #define E2END (0x0) #define E2PAGESIZE (0) #define FLASHEND (0x1FF) /* Fuses */ #define FUSE_MEMORY_SIZE 0 /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x09 /* Device Pin Definitions */ #define SPDATA_DDR DDRCINT #define SPDATA_PORT PORTCINT #define SPDATA_PIN PINCINT #define SPDATA_BIT INT0 #define OC0A_DDR DDRCINT #define OC0A_PORT PORTCINT #define OC0A_PIN PINCINT #define OC0A_BIT INT0 #define ADC0_DDR DDRCINT #define ADC0_PORT PORTCINT #define ADC0_PIN PINCINT #define ADC0_BIT INT0 #define AIN0_DDR DDRCINT #define AIN0_PORT PORTCINT #define AIN0_PIN PINCINT #define AIN0_BIT INT0 #define PB0_DDR DDRCINT #define PB0_PORT PORTCINT #define PB0_PIN PINCINT #define PB0_BIT INT0 #define SPCLK_DDR DDRCINT #define SPCLK_PORT PORTCINT #define SPCLK_PIN PINCINT #define SPCLK_BIT INT1 #define CLKI_DDR DDRCINT #define CLKI_PORT PORTCINT #define CLKI_PIN PINCINT #define CLKI_BIT INT1 #define ICP0_DDR DDRCINT #define ICP0_PORT PORTCINT #define ICP0_PIN PINCINT #define ICP0_BIT INT1 #define OC0B_DDR DDRCINT #define OC0B_PORT PORTCINT #define OC0B_PIN PINCINT #define OC0B_BIT INT1 #define ADC1_DDR DDRCINT #define ADC1_PORT PORTCINT #define ADC1_PIN PINCINT #define ADC1_BIT INT1 #define AIN1_DDR DDRCINT #define AIN1_PORT PORTCINT #define AIN1_PIN PINCINT #define AIN1_BIT INT1 #define PB1_DDR DDRCINT #define PB1_PORT PORTCINT #define PB1_PIN PINCINT #define PB1_BIT INT1 #define CLKO_DDR DDRT #define CLKO_PORT PORTT #define CLKO_PIN PINT #define CLKO_BIT T0 #define PCINT2_DDR DDRT #define PCINT2_PORT PORTT #define PCINT2_PIN PINT #define PCINT2_BIT T0 #define INT0_DDR DDRT #define INT0_PORT PORTT #define INT0_PIN PINT #define INT0_BIT T0 #define ADC2_DDR DDRT #define ADC2_PORT PORTT #define ADC2_PIN PINT #define ADC2_BIT T0 #define PB2_DDR DDRT #define PB2_PORT PORTT #define PB2_PIN PINT #define PB2_BIT T0 #define PCINT3_DDR DDRRESET #define PCINT3_PORT PORTRESET #define PCINT3_PIN PINRESET #define PCINT3_BIT RESET #define ADC3_DDR DDRRESET #define ADC3_PORT PORTRESET #define ADC3_PIN PINRESET #define ADC3_BIT RESET #define PB3_DDR DDRRESET #define PB3_PORT PORTRESET #define PB3_PIN PINRESET #define PB3_BIT RESET #endif /* _AVR_ATtiny5_H_ */ avr-libc-1.8.0.orig/include/avr/iotn15.h0000644000000000000000000001704411732702554014563 0ustar /* Copyright (c) 2002,2005 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn15.h 2236 2011-03-17 21:53:39Z arcanum $ */ /* avr/iotn15.h - definitions for ATtiny15 */ #ifndef _AVR_IOTN15_H_ #define _AVR_IOTN15_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn15.h" #else # error "Attempt to include more than one file." #endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" #endif /* I/O registers */ /* 0x00..0x03 reserved */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16 (0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSR _SFR_IO8(0x06) #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* 0x09..0x15 reserved */ /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* 0x19..0x1B reserved */ /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO8(0x1E) #define EEARL _SFR_IO8(0x1E) /* 0x1F..0x20 reserved */ /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* 0x22..0x2B reserved */ #define SFIOR _SFR_IO8(0x2C) #define OCR1B _SFR_IO8(0x2D) #define OCR1A _SFR_IO8(0x2E) #define TCNT1 _SFR_IO8(0x2F) #define TCCR1 _SFR_IO8(0x30) /* Oscillator Calibration Register */ #define OSCCAL _SFR_IO8(0x31) /* Timer/Counter0 (8-bit) */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* 0x36..0x37 reserved */ /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK Register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3C..0x3E reserved */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 0 */ #define IO_PINS_vect_num 2 #define IO_PINS_vect _VECTOR(2) #define SIG_PIN _VECTOR(2) #define SIG_PIN_CHANGE _VECTOR(2) /* Timer/Counter1 Compare Match */ #define TIMER1_COMP_vect_num 3 #define TIMER1_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE1A _VECTOR(3) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 4 #define TIMER1_OVF_vect _VECTOR(4) #define SIG_OVERFLOW1 _VECTOR(4) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 5 #define TIMER0_OVF_vect _VECTOR(5) #define SIG_OVERFLOW0 _VECTOR(5) /* EEPROM Ready */ #define EE_RDY_vect_num 6 #define EE_RDY_vect _VECTOR(6) #define SIG_EEPROM_READY _VECTOR(6) /* Analog Comparator */ #define ANA_COMP_vect_num 7 #define ANA_COMP_vect _VECTOR(7) #define SIG_COMPARATOR _VECTOR(7) /* ADC Conversion Ready */ #define ADC_vect_num 8 #define ADC_vect _VECTOR(8) #define SIG_ADC _VECTOR(8) #define _VECTORS_SIZE 18 /* Bit numbers */ /* GIMSK */ #define INT0 6 #define PCIE 5 /* GIFR */ #define INTF0 6 #define PCIF 5 /* TIMSK */ #define OCIE1 6 #define TOIE1 2 #define TOIE0 1 /* TIFR */ #define OCF1 6 #define TOV1 2 #define TOV0 1 /* MCUCR */ #define PUD 6 #define SE 5 #define SM1 4 #define SM0 3 #define ISC01 1 #define ISC00 0 /* MCUSR */ #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* TCCR0 */ #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR1 */ #define CTC1 7 #define PWM1 6 #define COM1A1 5 #define COM1A0 4 #define CS13 3 #define CS12 2 #define CS11 1 #define CS10 0 /* SFIOR */ #define FOC1A 2 #define PSR1 1 #define PSR0 0 /* WDTCR */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PB5 = RESET# / ADC0 PB4 = ADC3 PB3 = ADC2 PB2 = SCK / ADC1 / T0 / INT0 PB1 = MISO / AIN1 / OCP PB0 = MOSI / AIN0 / AREF */ /* PORTB */ #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* ACSR */ #define ACD 7 #define GREF 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIS1 1 #define ACIS0 0 /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* ADCSR */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Last memory addresses */ #define RAMEND 0x1F #define XRAMEND 0x0 #define E2END 0x3F #define E2PAGESIZE 2 #define FLASHEND 0x3FF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_RSTDISBL (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x06 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN #pragma GCC poison SIG_PIN_CHANGE #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOTN15_H_ */ avr-libc-1.8.0.orig/include/avr/iom645.h0000644000000000000000000004420511732702554014466 0ustar /* Copyright (c) 2004,2005,2006 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom645.h 2235 2011-03-17 04:13:14Z arcanum $ */ /* avr/iom645.h - definitions for ATmega645 */ #ifndef _AVR_IOM645_H_ #define _AVR_IOM645_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom645.h" #else # error "Attempt to include more than one file." #endif /* Registers and associated bit numbers */ #define PINA _SFR_IO8(0x00) #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 #define DDRA _SFR_IO8(0x01) #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 #define PINB _SFR_IO8(0x03) #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 #define DDRB _SFR_IO8(0x04) #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 #define PINC _SFR_IO8(0x06) #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 #define DDRC _SFR_IO8(0x07) #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 #define PORTC _SFR_IO8(0x08) #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 #define PIND _SFR_IO8(0x09) #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 #define DDRD _SFR_IO8(0x0A) #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 #define PINE _SFR_IO8(0x0C) #define PINE7 7 #define PINE6 6 #define PINE5 5 #define PINE4 4 #define PINE3 3 #define PINE2 2 #define PINE1 1 #define PINE0 0 #define DDRE _SFR_IO8(0x0D) #define DDE7 7 #define DDE6 6 #define DDE5 5 #define DDE4 4 #define DDE3 3 #define DDE2 2 #define DDE1 1 #define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PE7 7 #define PE6 6 #define PE5 5 #define PE4 4 #define PE3 3 #define PE2 2 #define PE1 1 #define PE0 0 #define PINF _SFR_IO8(0x0F) #define PINF7 7 #define PINF6 6 #define PINF5 5 #define PINF4 4 #define PINF3 3 #define PINF2 2 #define PINF1 1 #define PINF0 0 #define DDRF _SFR_IO8(0x10) #define DDF7 7 #define DDF6 6 #define DDF5 5 #define DDF4 4 #define DDF3 3 #define DDF2 2 #define DDF1 1 #define DDF0 0 #define PORTF _SFR_IO8(0x11) #define PF7 7 #define PF6 6 #define PF5 5 #define PF4 4 #define PF3 3 #define PF2 2 #define PF1 1 #define PF0 0 #define PING _SFR_IO8(0x12) #define PING5 5 #define PING4 4 #define PING3 3 #define PING2 2 #define PING1 1 #define PING0 0 #define DDRG _SFR_IO8(0x13) #define DDG4 4 #define DDG3 3 #define DDG2 2 #define DDG1 1 #define DDG0 0 #define PORTG _SFR_IO8(0x14) #define PG4 4 #define PG3 3 #define PG2 2 #define PG1 1 #define PG0 0 #define TIFR0 _SFR_IO8(0x15) #define TOV0 0 #define OCF0A 1 #define TIFR1 _SFR_IO8(0x16) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define ICF1 5 #define TIFR2 _SFR_IO8(0x17) #define TOV2 0 #define OCF2A 1 /* Reserved [0x18..0x1B] */ #define EIFR _SFR_IO8(0x1C) #define INTF0 0 #define PCIF0 4 #define PCIF1 5 #define EIMSK _SFR_IO8(0x1D) #define INT0 0 #define PCIE0 4 #define PCIE1 5 #define GPIOR0 _SFR_IO8(0x1E) #define EECR _SFR_IO8(0x1F) #define EERE 0 #define EEWE 1 #define EEMWE 2 #define EERIE 3 #define EEDR _SFR_IO8(0X20) /* Combine EEARL and EEARH */ #define EEAR _SFR_IO16(0x21) #define EEARL _SFR_IO8(0x21) #define EEARH _SFR_IO8(0X22) /* 6-char sequence denoting where to find the EEPROM registers in memory space. Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM subroutines. First two letters: EECR address. Second two letters: EEDR address. Last two letters: EEAR address. */ #define __EEPROM_REG_LOCATIONS__ 1F2021 #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define PSR2 1 #define TSM 7 #define TCCR0A _SFR_IO8(0x24) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM01 3 #define COM0A0 4 #define COM0A1 5 #define WGM00 6 #define FOC0A 7 /* Reserved [0x25] */ #define TCNT0 _SFR_IO8(0X26) #define OCR0A _SFR_IO8(0X27) /* Reserved [0x28..0x29] */ #define GPIOR1 _SFR_IO8(0x2A) #define GPIOR2 _SFR_IO8(0x2B) #define SPCR _SFR_IO8(0x2C) #define SPR0 0 #define SPR1 1 #define CPHA 2 #define CPOL 3 #define MSTR 4 #define DORD 5 #define SPE 6 #define SPIE 7 #define SPSR _SFR_IO8(0x2D) #define SPI2X 0 #define WCOL 6 #define SPIF 7 #define SPDR _SFR_IO8(0X2E) /* Reserved [0x2F] */ #define ACSR _SFR_IO8(0x30) #define ACIS0 0 #define ACIS1 1 #define ACIC 2 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 #define OCDR _SFR_IO8(0x31) #define OCDR0 0 #define OCDR1 1 #define OCDR2 2 #define OCDR3 3 #define OCDR4 4 #define OCDR5 5 #define OCDR6 6 #define OCDR7 7 #define IDRD 7 /* Reserved [0x32] */ #define SMCR _SFR_IO8(0x33) #define SE 0 #define SM0 1 #define SM1 2 #define SM2 3 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define JTRF 4 #define MCUCR _SFR_IO8(0X35) #define IVCE 0 #define IVSEL 1 #define PUD 4 #define JTD 7 /* Reserved [0x36] */ #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define BLBSET 3 #define RWWSRE 4 #define RWWSB 6 #define SPMIE 7 /* Reserved [0x38..0x3C] */ /* SP [0x3D..0x3E] */ /* SREG [0x3F] */ #define WDTCR _SFR_MEM8(0x60) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define CLKPR _SFR_MEM8(0x61) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x62..0x63] */ #define PRR _SFR_MEM8(0x64) #define PRADC 0 #define PRUSART0 1 #define PRSPI 2 #define PRTIM1 3 /* Reserved [0x65] */ #define OSCCAL _SFR_MEM8(0x66) /* Reserved [0x67..0x68] */ #define EICRA _SFR_MEM8(0x69) #define ISC00 0 #define ISC01 1 /* Reserved [0x6A] */ #define PCMSK0 _SFR_MEM8(0x6B) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define PCMSK1 _SFR_MEM8(0x6C) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define PCINT12 4 #define PCINT13 5 #define PCINT14 6 #define PCINT15 7 /* Reserved [0x6D] */ #define TIMSK0 _SFR_MEM8(0x6E) #define TOIE0 0 #define OCIE0A 1 #define TIMSK1 _SFR_MEM8(0x6F) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define ICIE1 5 #define TIMSK2 _SFR_MEM8(0x70) #define TOIE2 0 #define OCIE2A 1 /* Reserved [0x71..0x77] */ /* Combine ADCL and ADCH */ #ifndef __ASSEMBLER__ #define ADC _SFR_MEM16(0x78) #endif #define ADCW _SFR_MEM16(0x78) #define ADCL _SFR_MEM8(0x78) #define ADCH _SFR_MEM8(0x79) #define ADCSRA _SFR_MEM8(0x7A) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADCSRB _SFR_MEM8(0x7B) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ACME 6 #define ADMUX _SFR_MEM8(0x7C) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define MUX3 3 #define MUX4 4 #define ADLAR 5 #define REFS0 6 #define REFS1 7 /* Reserved [0x7D] */ #define DIDR0 _SFR_MEM8(0x7E) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define ADC4D 4 #define ADC5D 5 #define ADC6D 6 #define ADC7D 7 #define DIDR1 _SFR_MEM8(0x7F) #define AIN0D 0 #define AIN1D 1 #define TCCR1A _SFR_MEM8(0X80) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR1B _SFR_MEM8(0X81) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define WGM13 4 #define ICES1 6 #define ICNC1 7 #define TCCR1C _SFR_MEM8(0x82) #define FOC1B 6 #define FOC1A 7 /* Reserved [0x83] */ /* Combine TCNT1L and TCNT1H */ #define TCNT1 _SFR_MEM16(0x84) #define TCNT1L _SFR_MEM8(0x84) #define TCNT1H _SFR_MEM8(0x85) /* Combine ICR1L and ICR1H */ #define ICR1 _SFR_MEM16(0x86) #define ICR1L _SFR_MEM8(0x86) #define ICR1H _SFR_MEM8(0x87) /* Combine OCR1AL and OCR1AH */ #define OCR1A _SFR_MEM16(0x88) #define OCR1AL _SFR_MEM8(0x88) #define OCR1AH _SFR_MEM8(0x89) /* Combine OCR1BL and OCR1BH */ #define OCR1B _SFR_MEM16(0x8A) #define OCR1BL _SFR_MEM8(0x8A) #define OCR1BH _SFR_MEM8(0x8B) /* Reserved [0x8C..0xAF] */ #define TCCR2A _SFR_MEM8(0xB0) #define CS20 0 #define CS21 1 #define CS22 2 #define WGM21 3 #define COM2A0 4 #define COM2A1 5 #define WGM20 6 #define FOC2A 7 /* Reserved [0xB1] */ #define TCNT2 _SFR_MEM8(0xB2) #define OCR2A _SFR_MEM8(0xB3) /* Reserved [0xB4..0xB5] */ #define ASSR _SFR_MEM8(0xB6) #define TCR2UB 0 #define OCR2UB 1 #define TCN2UB 2 #define AS2 3 #define EXCLK 4 /* Reserved [0xB7] */ #define USICR _SFR_MEM8(0xB8) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_MEM8(0xB9) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_MEM8(0xBA) /* Reserved [0xBB..0xBF] */ #define UCSR0A _SFR_MEM8(0xC0) #define MPCM0 0 #define U2X0 1 #define UPE0 2 #define DOR0 3 #define FE0 4 #define UDRE0 5 #define TXC0 6 #define RXC0 7 #define UCSR0B _SFR_MEM8(0XC1) #define TXB80 0 #define RXB80 1 #define UCSZ02 2 #define TXEN0 3 #define RXEN0 4 #define UDRIE0 5 #define TXCIE0 6 #define RXCIE0 7 #define UCSR0C _SFR_MEM8(0xC2) #define UCPOL0 0 #define UCSZ00 1 #define UCSZ01 2 #define USBS0 3 #define UPM00 4 #define UPM01 5 #define UMSEL0 6 /* Reserved [0xC3] */ /* Combine UBRR0L and UBRR0H */ #define UBRR0 _SFR_MEM16(0xC4) #define UBRR0L _SFR_MEM8(0xC4) #define UBRR0H _SFR_MEM8(0xC5) #define UDR0 _SFR_MEM8(0XC6) /* Reserved [0xC7..0xFF] */ /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) #define SIG_PIN_CHANGE0 _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) #define SIG_PIN_CHANGE1 _VECTOR(3) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 4 #define TIMER2_COMP_vect _VECTOR(4) #define SIG_OUTPUT_COMPARE2 _VECTOR(4) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 5 #define TIMER2_OVF_vect _VECTOR(5) #define SIG_OVERFLOW2 _VECTOR(5) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 6 #define TIMER1_CAPT_vect _VECTOR(6) #define SIG_INPUT_CAPTURE1 _VECTOR(6) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 7 #define TIMER1_COMPA_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1A _VECTOR(7) /* Timer/Counter Compare Match B */ #define TIMER1_COMPB_vect_num 8 #define TIMER1_COMPB_vect _VECTOR(8) #define SIG_OUTPUT_COMPARE1B _VECTOR(8) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 9 #define TIMER1_OVF_vect _VECTOR(9) #define SIG_OVERFLOW1 _VECTOR(9) /* Timer/Counter0 Compare Match */ #define TIMER0_COMP_vect_num 10 #define TIMER0_COMP_vect _VECTOR(10) #define SIG_OUTPUT_COMPARE0 _VECTOR(10) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 11 #define TIMER0_OVF_vect _VECTOR(11) #define SIG_OVERFLOW0 _VECTOR(11) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 12 #define SPI_STC_vect _VECTOR(12) #define SIG_SPI _VECTOR(12) /* USART0, Rx Complete */ #define USART0_RX_vect_num 13 #define USART0_RX_vect _VECTOR(13) #define SIG_UART_RECV _VECTOR(13) /* USART0 Data register Empty */ #define USART0_UDRE_vect_num 14 #define USART0_UDRE_vect _VECTOR(14) #define SIG_UART_DATA _VECTOR(14) /* USART0, Tx Complete */ #define USART0_TX_vect_num 15 #define USART0_TX_vect _VECTOR(15) #define SIG_UART_TRANS _VECTOR(15) /* USI Start Condition */ #define USI_START_vect_num 16 #define USI_START_vect _VECTOR(16) #define SIG_USI_START _VECTOR(16) /* USI Overflow */ #define USI_OVERFLOW_vect_num 17 #define USI_OVERFLOW_vect _VECTOR(17) #define SIG_USI_OVERFLOW _VECTOR(17) /* Analog Comparator */ #define ANALOG_COMP_vect_num 18 #define ANALOG_COMP_vect _VECTOR(18) #define SIG_COMPARATOR _VECTOR(18) /* ADC Conversion Complete */ #define ADC_vect_num 19 #define ADC_vect _VECTOR(19) #define SIG_ADC _VECTOR(19) /* EEPROM Ready */ #define EE_READY_vect_num 20 #define EE_READY_vect _VECTOR(20) #define SIG_EEPROM_READY _VECTOR(20) /* Store Program Memory Read */ #define SPM_READY_vect_num 21 #define SPM_READY_vect _VECTOR(21) #define SIG_SPM_READY _VECTOR(21) /* Vector 22 is Reserved */ #define _VECTORS_SIZE 92 /* Constants */ #define SPM_PAGESIZE 256 #define RAMSTART (0x100) #define RAMEND 0x10FF #define XRAMEND RAMEND #define E2END 0x7FF #define E2PAGESIZE 8 #define FLASHEND 0xFFFF /* Fuses */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_JTAGEN (unsigned char)~_BV(6) #define FUSE_OCDEN (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) /* Extended Fuse Byte */ #define FUSE_RSTDISBL (unsigned char)~_BV(0) #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 #define SIGNATURE_2 0x05 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN_CHANGE0 #pragma GCC poison SIG_PIN_CHANGE1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_USI_START #pragma GCC poison SIG_USI_OVERFLOW #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM645_H_ */ avr-libc-1.8.0.orig/include/avr/iotn11.h0000644000000000000000000001272011732702554014553 0ustar /* Copyright (c) 2002,2005 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn11.h 2236 2011-03-17 21:53:39Z arcanum $ */ /* avr/iotn11.h - definitions for ATtiny10/11 */ #ifndef _AVR_IOTN11_H_ #define _AVR_IOTN11_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn11.h" #else # error "Attempt to include more than one file." #endif #ifndef __ASSEMBLER__ # warning "MCU not supported by the C compiler" #endif /* I/O registers */ /* 0x00..0x07 reserved */ /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* 0x09..0x15 reserved */ /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* 0x19..0x20 reserved */ /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* 0x22..0x31 reserved */ /* Timer/Counter0 (8-bit) */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU general Status Register */ #define MCUSR _SFR_IO8(0x34) /* MCU general Control Register */ #define MCUCR _SFR_IO8(0x35) /* 0x36..0x37 reserved */ /* Timer/Counter Interrupt Flag Register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK Register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GIMSK _SFR_IO8(0x3B) /* 0x3C..0x3E reserved */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 0 */ #define IO_PINS_vect_num 2 #define IO_PINS_vect _VECTOR(2) #define SIG_PIN _VECTOR(2) #define SIG_PIN_CHANGE _VECTOR(2) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 3 #define TIMER0_OVF_vect _VECTOR(3) #define SIG_OVERFLOW0 _VECTOR(3) /* Analog Comparator */ #define ANA_COMP_vect_num 4 #define ANA_COMP_vect _VECTOR(4) #define SIG_COMPARATOR _VECTOR(4) #define _VECTORS_SIZE 10 /* Bit numbers */ /* GIMSK */ #define INT0 6 #define PCIE 5 /* GIFR */ #define INTF0 6 #define PCIF 5 /* TIMSK */ #define TOIE0 1 /* TIFR */ #define TOV0 1 /* MCUCR */ #define SE 5 #define SM 4 #define ISC01 1 #define ISC00 0 /* TCCR0 */ #define CS02 2 #define CS01 1 #define CS00 0 /* WDTCR */ #define WDTOE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* PB5 = RESET# PB4 = XTAL2 PB3 = XTAL1 PB2 = T0 PB1 = INT0 / AIN1 PB0 = AIN0 */ /* PORTB */ #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* ACSR */ #define ACD 7 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIS1 1 #define ACIS0 0 /* Last memory addresses */ #define RAMEND 0x1F #define XRAMEND 0x0 #define E2END 0x0 #define E2PAGESIZE 2 #define FLASHEND 0x3FF /* Fuses */ #define FUSE_MEMORY_SIZE 1 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_RSTDISBL (unsigned char)~_BV(3) #define FUSE_FSTRT (unsigned char)~_BV(4) #define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x90 #define SIGNATURE_2 0x04 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_PIN #pragma GCC poison SIG_PIN_CHANGE #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_COMPARATOR #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOTN11_H_ */ avr-libc-1.8.0.orig/include/avr/iom8.h0000644000000000000000000003260611732702554014321 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom8.h 2235 2011-03-17 04:13:14Z arcanum $ */ /* avr/iom8.h - definitions for ATmega8 */ #ifndef _AVR_IOM8_H_ #define _AVR_IOM8_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom8.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWAR _SFR_IO8(0x02) #define TWDR _SFR_IO8(0x03) /* ADC */ #define ADCW _SFR_IO16(0x04) #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) #define ADCSR _SFR_IO8(0x06) #define ADCSRA _SFR_IO8(0x06) /* Changed in 2486H-AVR-09/02 */ #define ADMUX _SFR_IO8(0x07) /* analog comparator */ #define ACSR _SFR_IO8(0x08) /* USART */ #define UBRRL _SFR_IO8(0x09) #define UCSRB _SFR_IO8(0x0A) #define UCSRA _SFR_IO8(0x0B) #define UDR _SFR_IO8(0x0C) /* SPI */ #define SPCR _SFR_IO8(0x0D) #define SPSR _SFR_IO8(0x0E) #define SPDR _SFR_IO8(0x0F) /* Port D */ #define PIND _SFR_IO8(0x10) #define DDRD _SFR_IO8(0x11) #define PORTD _SFR_IO8(0x12) /* Port C */ #define PINC _SFR_IO8(0x13) #define DDRC _SFR_IO8(0x14) #define PORTC _SFR_IO8(0x15) /* Port B */ #define PINB _SFR_IO8(0x16) #define DDRB _SFR_IO8(0x17) #define PORTB _SFR_IO8(0x18) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) #define UCSRC _SFR_IO8(0x20) #define UBRRH _SFR_IO8(0x20) #define WDTCR _SFR_IO8(0x21) #define ASSR _SFR_IO8(0x22) /* Timer 2 */ #define OCR2 _SFR_IO8(0x23) #define TCNT2 _SFR_IO8(0x24) #define TCCR2 _SFR_IO8(0x25) /* Timer 1 */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) #define TCCR1B _SFR_IO8(0x2E) #define TCCR1A _SFR_IO8(0x2F) #define SFIOR _SFR_IO8(0x30) #define OSCCAL _SFR_IO8(0x31) /* Timer 0 */ #define TCNT0 _SFR_IO8(0x32) #define TCCR0 _SFR_IO8(0x33) #define MCUCSR _SFR_IO8(0x34) #define MCUSR _SFR_IO8(0x34) /* Defined as an alias for MCUCSR. */ #define MCUCR _SFR_IO8(0x35) #define TWCR _SFR_IO8(0x36) #define SPMCR _SFR_IO8(0x37) #define TIFR _SFR_IO8(0x38) #define TIMSK _SFR_IO8(0x39) #define GIFR _SFR_IO8(0x3A) #define GIMSK _SFR_IO8(0x3B) #define GICR _SFR_IO8(0x3B) /* Changed in 2486H-AVR-09/02 */ /* 0x3C reserved (OCR0?) */ /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt Request 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 3 #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 4 #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 5 #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 6 #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 7 #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 8 #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 9 #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) /* Serial Transfer Complete */ #define SPI_STC_vect_num 10 #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) /* USART, Rx Complete */ #define USART_RXC_vect_num 11 #define USART_RXC_vect _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) /* USART Data Register Empty */ #define USART_UDRE_vect_num 12 #define USART_UDRE_vect _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) /* USART, Tx Complete */ #define USART_TXC_vect_num 13 #define USART_TXC_vect _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) /* ADC Conversion Complete */ #define ADC_vect_num 14 #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) /* EEPROM Ready */ #define EE_RDY_vect_num 15 #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) /* Analog Comparator */ #define ANA_COMP_vect_num 16 #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) /* 2-wire Serial Interface */ #define TWI_vect_num 17 #define TWI_vect _VECTOR(17) #define SIG_2WIRE_SERIAL _VECTOR(17) /* Store Program Memory Ready */ #define SPM_RDY_vect_num 18 #define SPM_RDY_vect _VECTOR(18) #define SIG_SPM_READY _VECTOR(18) #define _VECTORS_SIZE 38 /* Bit numbers */ /* GIMSK / GICR */ #define INT1 7 #define INT0 6 #define IVSEL 1 #define IVCE 0 /* GIFR */ #define INTF1 7 #define INTF0 6 /* TIMSK */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 /* bit 1 reserved (OCIE0?) */ #define TOIE0 0 /* TIFR */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 /* bit 1 reserved (OCF0?) */ #define TOV0 0 /* SPMCR */ #define SPMIE 7 #define RWWSB 6 /* bit 5 reserved */ #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* TWCR */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 /* bit 1 reserved (TWI_TST?) */ #define TWIE 0 /* TWAR */ #define TWA6 7 #define TWA5 6 #define TWA4 5 #define TWA3 4 #define TWA2 3 #define TWA1 2 #define TWA0 1 #define TWGCE 0 /* TWSR */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 /* bit 2 reserved */ #define TWPS1 1 #define TWPS0 0 /* MCUCR */ #define SE 7 #define SM2 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* MCUCSR */ /* bits 7-4 reserved */ #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ /* SFIOR */ /* bits 7-5 reserved */ #define ACME 3 #define PUD 2 #define PSR2 1 #define PSR10 0 /* TCCR0 */ /* bits 7-3 reserved */ #define CS02 2 #define CS01 1 #define CS00 0 /* TCCR2 */ #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* ASSR */ /* bits 7-4 reserved */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* TCCR1A */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define WGM11 1 #define WGM10 0 /* TCCR1B */ #define ICNC1 7 #define ICES1 6 /* bit 5 reserved */ #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* WDTCR */ /* bits 7-5 reserved */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* UBRRH */ #define URSEL 7 /* UCSRC */ #define URSEL 7 #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* PORTB */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* DDRB */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* PINB */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* PORTC */ #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* DDRC */ #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* PINC */ #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* PORTD */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* DDRD */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* PIND */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPSR */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPCR */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* UCSRA */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define PE 2 #define U2X 1 #define MPCM 0 /* UCSRB */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 /* ACSR */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADCSR / ADCSRA */ #define ADEN 7 #define ADSC 6 #define ADFR 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* ADMUX */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 /* bit 4 reserved */ #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x60) #define RAMEND 0x45F #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_WDTON (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x07 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_2WIRE_SERIAL #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM8_H_ */ avr-libc-1.8.0.orig/include/avr/iotn43u.h0000644000000000000000000002740011732702554014746 0ustar /* Copyright (c) 2007 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iotn43u.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iotn43u.h - definitions for ATtiny43U */ /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iotn43u.h" #else # error "Attempt to include more than one file." #endif #ifndef _AVR_IOTN43U_H_ #define _AVR_IOTN43U_H_ 1 /* Registers and associated bit numbers */ #define PRR _SFR_IO8(0x00) #define PRADC 0 #define PRUSI 1 #define PRTIM0 2 #define PRTIM1 3 #define DIDR0 _SFR_IO8(0x01) #define ADC0D 0 #define ADC1D 1 #define ADC2D 2 #define ADC3D 3 #define AIN0D 4 #define AIN1D 5 /* Reserved [0x02] */ #define ADCSRB _SFR_IO8(0x03) #define ADTS0 0 #define ADTS1 1 #define ADTS2 2 #define ADLAR 4 #define ACME 6 #ifndef _ASSEMBLER_ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCL0 0 #define ADCL1 1 #define ADCL2 2 #define ADCL3 3 #define ADCL4 4 #define ADCL5 5 #define ADCL6 6 #define ADCL7 7 #define ADCH _SFR_IO8(0x05) #define ADCH0 0 #define ADCH1 1 #define ADCH2 2 #define ADCH3 3 #define ADCH4 4 #define ADCH5 5 #define ADCH6 6 #define ADCH7 7 #define ADCSRA _SFR_IO8(0x06) #define ADPS0 0 #define ADPS1 1 #define ADPS2 2 #define ADIE 3 #define ADIF 4 #define ADATE 5 #define ADSC 6 #define ADEN 7 #define ADMUX _SFR_IO8(0x07) #define MUX0 0 #define MUX1 1 #define MUX2 2 #define REFS0 6 #define ACSR _SFR_IO8(0x08) #define ACIS0 0 #define ACIS1 1 #define ACIE 3 #define ACI 4 #define ACO 5 #define ACBG 6 #define ACD 7 /* Reserved [0x09], [0x0A] */ #define TIFR1 _SFR_IO8(0x0B) #define TOV1 0 #define OCF1A 1 #define OCF1B 2 #define TIMSK1 _SFR_IO8(0x0C) #define TOIE1 0 #define OCIE1A 1 #define OCIE1B 2 #define USICR _SFR_IO8(0x0D) #define USITC 0 #define USICLK 1 #define USICS0 2 #define USICS1 3 #define USIWM0 4 #define USIWM1 5 #define USIOIE 6 #define USISIE 7 #define USISR _SFR_IO8(0x0E) #define USICNT0 0 #define USICNT1 1 #define USICNT2 2 #define USICNT3 3 #define USIDC 4 #define USIPF 5 #define USIOIF 6 #define USISIF 7 #define USIDR _SFR_IO8(0x0F) #define USIDR0 0 #define USIDR1 1 #define USIDR2 2 #define USIDR3 3 #define USIDR4 4 #define USIDR5 5 #define USIDR6 6 #define USIDR7 7 #define USIBR _SFR_IO8(0x10) #define USIBR0 0 #define USIBR1 1 #define USIBR2 2 #define USIBR3 3 #define USIBR4 4 #define USIBR5 5 #define USIBR6 6 #define USIBR7 7 /* Reserved [0x11] */ #define PCMSK0 _SFR_IO8(0x12) #define PCINT0 0 #define PCINT1 1 #define PCINT2 2 #define PCINT3 3 #define PCINT4 4 #define PCINT5 5 #define PCINT6 6 #define PCINT7 7 #define GPIOR0 _SFR_IO8(0x13) #define GPIOR00 0 #define GPIOR01 1 #define GPIOR02 2 #define GPIOR03 3 #define GPIOR04 4 #define GPIOR05 5 #define GPIOR06 6 #define GPIOR07 7 #define GPIOR1 _SFR_IO8(0x14) #define GPIOR10 0 #define GPIOR11 1 #define GPIOR12 2 #define GPIOR13 3 #define GPIOR14 4 #define GPIOR15 5 #define GPIOR16 6 #define GPIOR17 7 #define GPIOR2 _SFR_IO8(0x15) #define GPIOR20 0 #define GPIOR21 1 #define GPIOR22 2 #define GPIOR23 3 #define GPIOR24 4 #define GPIOR25 5 #define GPIOR26 6 #define GPIOR27 7 #define PINB _SFR_IO8(0x16) #define PINB0 0 #define PINB1 1 #define PINB2 2 #define PINB3 3 #define PINB4 4 #define PINB5 5 #define PINB6 6 #define PINB7 7 #define DDRB _SFR_IO8(0x17) #define DDB0 0 #define DDB1 1 #define DDB2 2 #define DDB3 3 #define DDB4 4 #define DDB5 5 #define DDB6 6 #define DDB7 7 #define PORTB _SFR_IO8(0x18) #define PORTB0 0 #define PORTB1 1 #define PORTB2 2 #define PORTB3 3 #define PORTB4 4 #define PORTB5 5 #define PORTB6 6 #define PORTB7 7 #define PINA _SFR_IO8(0x19) #define PINA0 0 #define PINA1 1 #define PINA2 2 #define PINA3 3 #define PINA4 4 #define PINA5 5 #define PINA6 6 #define PINA7 7 #define DDRA _SFR_IO8(0x1A) #define DDA0 0 #define DDA1 1 #define DDA2 2 #define DDA3 3 #define DDA4 4 #define DDA5 5 #define DDA6 6 #define DDA7 7 #define PORTA _SFR_IO8(0x1B) #define PORTA0 0 #define PORTA1 1 #define PORTA2 2 #define PORTA3 3 #define PORTA4 4 #define PORTA5 5 #define PORTA6 6 #define PORTA7 7 /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) #define EERE 0 #define EEPE 1 #define EEMPE 2 #define EERIE 3 #define EEPM0 4 #define EEPM1 5 /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEARL _SFR_IO8(0x1E) /* Reserved [0x1F] */ #define PCMSK1 _SFR_IO8(0x20) #define PCINT8 0 #define PCINT9 1 #define PCINT10 2 #define PCINT11 3 #define WDTCSR _SFR_IO8(0x21) #define WDP0 0 #define WDP1 1 #define WDP2 2 #define WDE 3 #define WDCE 4 #define WDP3 5 #define WDIE 6 #define WDIF 7 /* Reserved [0x22] */ #define GTCCR _SFR_IO8(0x23) #define PSR10 0 #define TSM 7 /* Reserved [0x24], [0x25] */ #define CLKPR _SFR_IO8(0x26) #define CLKPS0 0 #define CLKPS1 1 #define CLKPS2 2 #define CLKPS3 3 #define CLKPCE 7 /* Reserved [0x27],[0x28],[0x29],[0x2A] */ #define OCR1B _SFR_IO8(0x2B) #define OCR1B_0 0 #define OCR1B_1 1 #define OCR1B_2 2 #define OCR1B_3 3 #define OCR1B_4 4 #define OCR1B_5 5 #define OCR1B_6 6 #define OCR1B_7 7 #define OCR1A _SFR_IO8(0x2C) #define OCR1A_0 0 #define OCR1A_1 1 #define OCRA1_2 2 #define OCRA1_3 3 #define OCRA1_4 4 #define OCRA1_5 5 #define OCRA1_6 6 #define OCRA1_7 7 #define TCNT1 _SFR_IO8(0x2D) #define TCNT1_0 0 #define TCNT1_1 1 #define TCNT1_2 2 #define TCNT1_3 3 #define TCNT1_4 4 #define TCNT1_5 5 #define TCNT1_6 6 #define TCNT1_7 7 #define TCCR1B _SFR_IO8(0x2E) #define CS10 0 #define CS11 1 #define CS12 2 #define WGM12 3 #define FOC1B 6 #define FOC1A 7 #define TCCR1A _SFR_IO8(0x2F) #define WGM10 0 #define WGM11 1 #define COM1B0 4 #define COM1B1 5 #define COM1A0 6 #define COM1A1 7 #define TCCR0A _SFR_IO8(0x30) #define WGM00 0 #define WGM01 1 #define COM0B0 4 #define COM0B1 5 #define COM0A0 6 #define COM0A1 7 #define OSCCAL _SFR_IO8(0x31) #define CAL0 0 #define CAL1 1 #define CAL2 2 #define CAL3 3 #define CAL4 4 #define CAL5 5 #define CAL6 6 #define CAL7 7 #define TCNT0 _SFR_IO8(0x32) #define TCNT0_0 0 #define TCNT0_1 1 #define TCNT0_2 2 #define TCNT0_3 3 #define TCNT0_4 4 #define TCNT0_5 5 #define TCNT0_6 6 #define TCNT0_7 7 #define TCCR0B _SFR_IO8(0x33) #define CS00 0 #define CS01 1 #define CS02 2 #define WGM02 3 #define FOC0B 6 #define FOC0A 7 #define MCUSR _SFR_IO8(0x34) #define PORF 0 #define EXTRF 1 #define BORF 2 #define WDRF 3 #define MCUCR _SFR_IO8(0x35) #define ISC00 0 #define ISC01 1 #define BODSE 2 #define SM0 3 #define SM1 4 #define SE 5 #define PUD 6 #define BODS 7 #define OCR0A _SFR_IO8(0x36) #define OCR0A_0 0 #define OCR0A_1 1 #define OCR0A_2 2 #define OCR0A_3 3 #define OCR0A_4 4 #define OCR0A_5 5 #define OCR0A_6 6 #define OCR0A_7 7 #define SPMCSR _SFR_IO8(0x37) #define SPMEN 0 #define PGERS 1 #define PGWRT 2 #define RFLB 3 #define CTPB 4 #define TIFR0 _SFR_IO8(0x38) #define TOV0 0 #define OCF0A 1 #define OCF0B 2 #define TIMSK0 _SFR_IO8(0x39) #define TOIE0 0 #define OCIE0A 1 #define OCIE0B 2 #define GIFR _SFR_IO8(0x3A) #define PCIF0 4 #define PCIF1 5 #define INTF0 6 #define GIMSK _SFR_IO8(0x3B) #define PCIE0 4 #define PCIE1 5 #define INT0 6 #define OCR0B _SFR_IO8(0x3C) #define OCR0B_0 0 #define OCR0B_1 1 #define OCR0B_2 2 #define OCR0B_3 3 #define OCR0B_4 4 #define OCR0B_5 5 #define OCR0B_6 6 #define OCR0B_7 7 /* Interrupt Vectors */ /* Interrupt vector 0 is the reset vector. */ /* External Interrupt Request 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) /* Pin Change Interrupt Request 0 */ #define PCINT0_vect_num 2 #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 1 */ #define PCINT1_vect_num 3 #define PCINT1_vect _VECTOR(3) /* Watchdog Time-out */ #define WDT_vect_num 4 #define WDT_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */ #define TIM1_COMPA_vect_num 5 #define TIM1_COMPA_vect _VECTOR(5) /* Timer/Counter1 Compare Match B */ #define TIM1_COMPB_vect_num 6 #define TIM1_COMPB_vect _VECTOR(6) /* Timer/Counter1 Overflow */ #define TIM1_OVF_vect_num 7 #define TIM1_OVF_vect _VECTOR(7) /* Timer/Counter0 Compare Match A */ #define TIM0_COMPA_vect_num 8 #define TIM0_COMPA_vect _VECTOR(8) /* Timer/Counter0 Compare Match B */ #define TIM0_COMPB_vect_num 9 #define TIM0_COMPB_vect _VECTOR(9) /* Timer/Counter0 Overflow */ #define TIM0_OVF_vect_num 10 #define TIM0_OVF_vect _VECTOR(10) /* Analog Comparator */ #define ANA_COMP_vect_num 11 #define ANA_COMP_vect _VECTOR(11) /* ADC Conversion Complete */ #define ADC_vect_num 12 #define ADC_vect _VECTOR(12) /* EEPROM Ready */ #define EE_RDY_vect_num 13 #define EE_RDY_vect _VECTOR(13) /* USI START */ #define USI_START_vect_num 14 #define USI_START_vect _VECTOR(14) /* USI Overflow */ #define USI_OVF_vect_num 15 #define USI_OVF_vect _VECTOR(15) #define _VECTORS_SIZE 32 /* Constants */ #define SPM_PAGESIZE 64 #define RAMEND 0x15F #define XRAMEND RAMEND #define E2END 0x3F #define E2PAGESIZE 4 #define FLASHEND 0xFFF /* Fuse Information */ #define FUSE_MEMORY_SIZE 3 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_WDTON (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_SPIEN) /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) #define EFUSE_DEFAULT (0xFF) /* Lock Bits */ #define __LOCK_BITS_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x0C #endif /* _AVR_IOTN43U_H_ */ avr-libc-1.8.0.orig/include/avr/iom8535.h0000644000000000000000000004635611732702554014565 0ustar /* Copyright (c) 2002, Steinar Haugen All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iom8535.h 2235 2011-03-17 04:13:14Z arcanum $ */ /* avr/iom8535.h - definitions for ATmega8535 */ #ifndef _AVR_IOM8535_H_ #define _AVR_IOM8535_H_ 1 /* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iom8535.h" #else # error "Attempt to include more than one file." #endif /* I/O registers */ /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ #define TWBR _SFR_IO8(0x00) #define TWSR _SFR_IO8(0x01) #define TWAR _SFR_IO8(0x02) #define TWDR _SFR_IO8(0x03) /* ADC Data register */ #ifndef __ASSEMBLER__ #define ADC _SFR_IO16(0x04) #endif #define ADCW _SFR_IO16(0x04) #define ADCL _SFR_IO8(0x04) #define ADCH _SFR_IO8(0x05) /* ADC Control and Status Register */ #define ADCSRA _SFR_IO8(0x06) /* ADC MUX */ #define ADMUX _SFR_IO8(0x07) /* Analog Comparator Control and Status Register */ #define ACSR _SFR_IO8(0x08) /* USART Baud Rate Register */ #define UBRRL _SFR_IO8(0x09) /* USART Control and Status Register B */ #define UCSRB _SFR_IO8(0x0A) /* USART Control and Status Register A */ #define UCSRA _SFR_IO8(0x0B) /* USART I/O Data Register */ #define UDR _SFR_IO8(0x0C) /* SPI Control Register */ #define SPCR _SFR_IO8(0x0D) /* SPI Status Register */ #define SPSR _SFR_IO8(0x0E) /* SPI I/O Data Register */ #define SPDR _SFR_IO8(0x0F) /* Input Pins, Port D */ #define PIND _SFR_IO8(0x10) /* Data Direction Register, Port D */ #define DDRD _SFR_IO8(0x11) /* Data Register, Port D */ #define PORTD _SFR_IO8(0x12) /* Input Pins, Port C */ #define PINC _SFR_IO8(0x13) /* Data Direction Register, Port C */ #define DDRC _SFR_IO8(0x14) /* Data Register, Port C */ #define PORTC _SFR_IO8(0x15) /* Input Pins, Port B */ #define PINB _SFR_IO8(0x16) /* Data Direction Register, Port B */ #define DDRB _SFR_IO8(0x17) /* Data Register, Port B */ #define PORTB _SFR_IO8(0x18) /* Input Pins, Port A */ #define PINA _SFR_IO8(0x19) /* Data Direction Register, Port A */ #define DDRA _SFR_IO8(0x1A) /* Data Register, Port A */ #define PORTA _SFR_IO8(0x1B) /* EEPROM Control Register */ #define EECR _SFR_IO8(0x1C) /* EEPROM Data Register */ #define EEDR _SFR_IO8(0x1D) /* EEPROM Address Register */ #define EEAR _SFR_IO16(0x1E) #define EEARL _SFR_IO8(0x1E) #define EEARH _SFR_IO8(0x1F) /* USART Baud Rate Register HI */ /* USART Control and Status Register C */ #define UBRRH _SFR_IO8(0x20) #define UCSRC UBRRH /* Watchdog Timer Control Register */ #define WDTCR _SFR_IO8(0x21) /* Asynchronous mode Status Register */ #define ASSR _SFR_IO8(0x22) /* Timer/Counter2 Output Compare Register */ #define OCR2 _SFR_IO8(0x23) /* Timer/Counter 2 */ #define TCNT2 _SFR_IO8(0x24) /* Timer/Counter 2 Control Register */ #define TCCR2 _SFR_IO8(0x25) /* T/C 1 Input Capture Register */ #define ICR1 _SFR_IO16(0x26) #define ICR1L _SFR_IO8(0x26) #define ICR1H _SFR_IO8(0x27) /* Timer/Counter1 Output Compare Register B */ #define OCR1B _SFR_IO16(0x28) #define OCR1BL _SFR_IO8(0x28) #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register A */ #define OCR1A _SFR_IO16(0x2A) #define OCR1AL _SFR_IO8(0x2A) #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 */ #define TCNT1 _SFR_IO16(0x2C) #define TCNT1L _SFR_IO8(0x2C) #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 Control and Status Register */ #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register */ #define TCCR1A _SFR_IO8(0x2F) /* Special Function IO Register */ #define SFIOR _SFR_IO8(0x30) /* Oscillator Calibration Register */ #define OSCCAL _SFR_IO8(0x31) /* Timer/Counter 0 */ #define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 Control Register */ #define TCCR0 _SFR_IO8(0x33) /* MCU Control and Status Register */ #define MCUCSR _SFR_IO8(0x34) /* MCU Control Register */ #define MCUCR _SFR_IO8(0x35) /* TWI Control Register */ #define TWCR _SFR_IO8(0x36) /* Store Program Memory Control Register */ #define SPMCR _SFR_IO8(0x37) /* Timer/Counter Interrupt Flag register */ #define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt MaSK register */ #define TIMSK _SFR_IO8(0x39) /* General Interrupt Flag Register */ #define GIFR _SFR_IO8(0x3A) /* General Interrupt MaSK register */ #define GICR _SFR_IO8(0x3B) /* Timer/Counter 0 Output Compare Register */ #define OCR0 _SFR_IO8(0x3C) /* 0x3D..0x3E SP */ /* 0x3F SREG */ /* Interrupt vectors */ /* External Interrupt 0 */ #define INT0_vect_num 1 #define INT0_vect _VECTOR(1) #define SIG_INTERRUPT0 _VECTOR(1) /* External Interrupt 1 */ #define INT1_vect_num 2 #define INT1_vect _VECTOR(2) #define SIG_INTERRUPT1 _VECTOR(2) /* Timer/Counter2 Compare Match */ #define TIMER2_COMP_vect_num 3 #define TIMER2_COMP_vect _VECTOR(3) #define SIG_OUTPUT_COMPARE2 _VECTOR(3) /* Timer/Counter2 Overflow */ #define TIMER2_OVF_vect_num 4 #define TIMER2_OVF_vect _VECTOR(4) #define SIG_OVERFLOW2 _VECTOR(4) /* Timer/Counter1 Capture Event */ #define TIMER1_CAPT_vect_num 5 #define TIMER1_CAPT_vect _VECTOR(5) #define SIG_INPUT_CAPTURE1 _VECTOR(5) /* Timer/Counter1 Compare Match A */ #define TIMER1_COMPA_vect_num 6 #define TIMER1_COMPA_vect _VECTOR(6) #define SIG_OUTPUT_COMPARE1A _VECTOR(6) /* Timer/Counter1 Compare Match B */ #define TIMER1_COMPB_vect_num 7 #define TIMER1_COMPB_vect _VECTOR(7) #define SIG_OUTPUT_COMPARE1B _VECTOR(7) /* Timer/Counter1 Overflow */ #define TIMER1_OVF_vect_num 8 #define TIMER1_OVF_vect _VECTOR(8) #define SIG_OVERFLOW1 _VECTOR(8) /* Timer/Counter0 Overflow */ #define TIMER0_OVF_vect_num 9 #define TIMER0_OVF_vect _VECTOR(9) #define SIG_OVERFLOW0 _VECTOR(9) /* SPI Serial Transfer Complete */ #define SPI_STC_vect_num 10 #define SPI_STC_vect _VECTOR(10) #define SIG_SPI _VECTOR(10) /* USART, RX Complete */ #define USART_RX_vect_num 11 #define USART_RX_vect _VECTOR(11) #define SIG_UART_RECV _VECTOR(11) /* USART Data Register Empty */ #define USART_UDRE_vect_num 12 #define USART_UDRE_vect _VECTOR(12) #define SIG_UART_DATA _VECTOR(12) /* USART, TX Complete */ #define USART_TX_vect_num 13 #define USART_TX_vect _VECTOR(13) #define SIG_UART_TRANS _VECTOR(13) /* ADC Conversion Complete */ #define ADC_vect_num 14 #define ADC_vect _VECTOR(14) #define SIG_ADC _VECTOR(14) /* EEPROM Ready */ #define EE_RDY_vect_num 15 #define EE_RDY_vect _VECTOR(15) #define SIG_EEPROM_READY _VECTOR(15) /* Analog Comparator */ #define ANA_COMP_vect_num 16 #define ANA_COMP_vect _VECTOR(16) #define SIG_COMPARATOR _VECTOR(16) /* Two-wire Serial Interface */ #define TWI_vect_num 17 #define TWI_vect _VECTOR(17) #define SIG_2WIRE_SERIAL _VECTOR(17) /* External Interrupt Request 2 */ #define INT2_vect_num 18 #define INT2_vect _VECTOR(18) #define SIG_INTERRUPT2 _VECTOR(18) /* TimerCounter0 Compare Match */ #define TIMER0_COMP_vect_num 19 #define TIMER0_COMP_vect _VECTOR(19) #define SIG_OUTPUT_COMPARE0 _VECTOR(19) /* Store Program Memory Read */ #define SPM_RDY_vect_num 20 #define SPM_RDY_vect _VECTOR(20) #define SIG_SPM_READY _VECTOR(20) #define _VECTORS_SIZE 42 /* The Register Bit names are represented by their bit number (0-7). */ /* General Interrupt Control Register */ #define INT1 7 #define INT0 6 #define INT2 5 #define IVSEL 1 #define IVCE 0 /* General Interrupt Flag Register */ #define INTF1 7 #define INTF0 6 #define INTF2 5 /* Timer/Counter Interrupt MaSK register */ #define OCIE2 7 #define TOIE2 6 #define TICIE1 5 #define OCIE1A 4 #define OCIE1B 3 #define TOIE1 2 #define OCIE0 1 #define TOIE0 0 /* Timer/Counter Interrupt Flag register */ #define OCF2 7 #define TOV2 6 #define ICF1 5 #define OCF1A 4 #define OCF1B 3 #define TOV1 2 #define OCF0 1 #define TOV0 0 /* Store Program Memory Control Register */ #define SPMIE 7 #define RWWSB 6 #define RWWSRE 4 #define BLBSET 3 #define PGWRT 2 #define PGERS 1 #define SPMEN 0 /* TWI Control Register */ #define TWINT 7 #define TWEA 6 #define TWSTA 5 #define TWSTO 4 #define TWWC 3 #define TWEN 2 #define TWIE 0 /* MCU Control Register */ #define SM2 7 #define SE 6 #define SM1 5 #define SM0 4 #define ISC11 3 #define ISC10 2 #define ISC01 1 #define ISC00 0 /* MCU Control and Status Register */ #define ISC2 6 #define WDRF 3 #define BORF 2 #define EXTRF 1 #define PORF 0 /* Timer/Counter 0 Control Register */ #define FOC0 7 #define WGM00 6 #define COM01 5 #define COM00 4 #define WGM01 3 #define CS02 2 #define CS01 1 #define CS00 0 /* The ADHSM bit has been removed from all documentation, as being not needed at all since the comparator has proven to be fast enough even without feeding it more power. */ /* Special Function IO Register */ #define ADTS2 7 #define ADTS1 6 #define ADTS0 5 #define ACME 3 #define PUD 2 #define PSR2 1 #define PSR10 0 /* Timer/Counter 1 Control Register */ #define COM1A1 7 #define COM1A0 6 #define COM1B1 5 #define COM1B0 4 #define FOC1A 3 #define FOC1B 2 #define WGM11 1 #define WGM10 0 /* Timer/Counter 1 Control and Status Register */ #define ICNC1 7 #define ICES1 6 #define WGM13 4 #define WGM12 3 #define CS12 2 #define CS11 1 #define CS10 0 /* Timer/Counter 2 Control Register */ #define FOC2 7 #define WGM20 6 #define COM21 5 #define COM20 4 #define WGM21 3 #define CS22 2 #define CS21 1 #define CS20 0 /* Asynchronous mode Status Register */ #define AS2 3 #define TCN2UB 2 #define OCR2UB 1 #define TCR2UB 0 /* Watchdog Timer Control Register */ #define WDCE 4 #define WDE 3 #define WDP2 2 #define WDP1 1 #define WDP0 0 /* USART Control and Status Register C */ #define URSEL 7 #define UMSEL 6 #define UPM1 5 #define UPM0 4 #define USBS 3 #define UCSZ1 2 #define UCSZ0 1 #define UCPOL 0 /* Data Register, Port A */ #define PA7 7 #define PA6 6 #define PA5 5 #define PA4 4 #define PA3 3 #define PA2 2 #define PA1 1 #define PA0 0 /* Data Direction Register, Port A */ #define DDA7 7 #define DDA6 6 #define DDA5 5 #define DDA4 4 #define DDA3 3 #define DDA2 2 #define DDA1 1 #define DDA0 0 /* Input Pins, Port A */ #define PINA7 7 #define PINA6 6 #define PINA5 5 #define PINA4 4 #define PINA3 3 #define PINA2 2 #define PINA1 1 #define PINA0 0 /* Data Register, Port B */ #define PB7 7 #define PB6 6 #define PB5 5 #define PB4 4 #define PB3 3 #define PB2 2 #define PB1 1 #define PB0 0 /* Data Direction Register, Port B */ #define DDB7 7 #define DDB6 6 #define DDB5 5 #define DDB4 4 #define DDB3 3 #define DDB2 2 #define DDB1 1 #define DDB0 0 /* Input Pins, Port B */ #define PINB7 7 #define PINB6 6 #define PINB5 5 #define PINB4 4 #define PINB3 3 #define PINB2 2 #define PINB1 1 #define PINB0 0 /* Data Register, Port C */ #define PC7 7 #define PC6 6 #define PC5 5 #define PC4 4 #define PC3 3 #define PC2 2 #define PC1 1 #define PC0 0 /* Data Direction Register, Port C */ #define DDC7 7 #define DDC6 6 #define DDC5 5 #define DDC4 4 #define DDC3 3 #define DDC2 2 #define DDC1 1 #define DDC0 0 /* Input Pins, Port C */ #define PINC7 7 #define PINC6 6 #define PINC5 5 #define PINC4 4 #define PINC3 3 #define PINC2 2 #define PINC1 1 #define PINC0 0 /* Data Register, Port D */ #define PD7 7 #define PD6 6 #define PD5 5 #define PD4 4 #define PD3 3 #define PD2 2 #define PD1 1 #define PD0 0 /* Data Direction Register, Port D */ #define DDD7 7 #define DDD6 6 #define DDD5 5 #define DDD4 4 #define DDD3 3 #define DDD2 2 #define DDD1 1 #define DDD0 0 /* Input Pins, Port D */ #define PIND7 7 #define PIND6 6 #define PIND5 5 #define PIND4 4 #define PIND3 3 #define PIND2 2 #define PIND1 1 #define PIND0 0 /* SPI Status Register */ #define SPIF 7 #define WCOL 6 #define SPI2X 0 /* SPI Control Register */ #define SPIE 7 #define SPE 6 #define DORD 5 #define MSTR 4 #define CPOL 3 #define CPHA 2 #define SPR1 1 #define SPR0 0 /* USART Control and Status Register A */ #define RXC 7 #define TXC 6 #define UDRE 5 #define FE 4 #define DOR 3 #define PE 2 #define U2X 1 #define MPCM 0 /* USART Control and Status Register B */ #define RXCIE 7 #define TXCIE 6 #define UDRIE 5 #define RXEN 4 #define TXEN 3 #define UCSZ2 2 #define RXB8 1 #define TXB8 0 /* Analog Comparator Control and Status Register */ #define ACD 7 #define ACBG 6 #define ACO 5 #define ACI 4 #define ACIE 3 #define ACIC 2 #define ACIS1 1 #define ACIS0 0 /* ADC Multiplexer Selection Register */ #define REFS1 7 #define REFS0 6 #define ADLAR 5 #define MUX4 4 #define MUX3 3 #define MUX2 2 #define MUX1 1 #define MUX0 0 /* ADC Control and Status Register */ #define ADEN 7 #define ADSC 6 #define ADATE 5 #define ADIF 4 #define ADIE 3 #define ADPS2 2 #define ADPS1 1 #define ADPS0 0 /* TWI (Slave) Address Register */ #define TWGCE 0 /* TWI Status Register */ #define TWS7 7 #define TWS6 6 #define TWS5 5 #define TWS4 4 #define TWS3 3 #define TWPS1 1 #define TWPS0 0 /* EEPROM Control Register */ #define EERIE 3 #define EEMWE 2 #define EEWE 1 #define EERE 0 /* Constants */ #define SPM_PAGESIZE 64 #define RAMSTART (0x60) #define RAMEND 0x25F /* Last On-Chip SRAM Location */ #define XRAMEND RAMEND #define E2END 0x1FF #define E2PAGESIZE 4 #define FLASHEND 0x1FFF /* Fuses */ #define FUSE_MEMORY_SIZE 2 /* Low Fuse Byte */ #define FUSE_CKSEL0 (unsigned char)~_BV(0) #define FUSE_CKSEL1 (unsigned char)~_BV(1) #define FUSE_CKSEL2 (unsigned char)~_BV(2) #define FUSE_CKSEL3 (unsigned char)~_BV(3) #define FUSE_SUT0 (unsigned char)~_BV(4) #define FUSE_SUT1 (unsigned char)~_BV(5) #define FUSE_BODEN (unsigned char)~_BV(6) #define FUSE_BODLEVEL (unsigned char)~_BV(7) #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1) /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) #define FUSE_EESAVE (unsigned char)~_BV(3) #define FUSE_CKOPT (unsigned char)~_BV(4) #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_WDTON (unsigned char)~_BV(6) #define FUSE_S8535C (unsigned char)~_BV(7) #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) /* Lock Bits */ #define __LOCK_BITS_EXIST #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST /* Signature */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x08 /* Deprecated items */ #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) #pragma GCC system_header #pragma GCC poison SIG_INTERRUPT0 #pragma GCC poison SIG_INTERRUPT1 #pragma GCC poison SIG_OUTPUT_COMPARE2 #pragma GCC poison SIG_OVERFLOW2 #pragma GCC poison SIG_INPUT_CAPTURE1 #pragma GCC poison SIG_OUTPUT_COMPARE1A #pragma GCC poison SIG_OUTPUT_COMPARE1B #pragma GCC poison SIG_OVERFLOW1 #pragma GCC poison SIG_OVERFLOW0 #pragma GCC poison SIG_SPI #pragma GCC poison SIG_UART_RECV #pragma GCC poison SIG_UART_DATA #pragma GCC poison SIG_UART_TRANS #pragma GCC poison SIG_ADC #pragma GCC poison SIG_EEPROM_READY #pragma GCC poison SIG_COMPARATOR #pragma GCC poison SIG_2WIRE_SERIAL #pragma GCC poison SIG_INTERRUPT2 #pragma GCC poison SIG_OUTPUT_COMPARE0 #pragma GCC poison SIG_SPM_READY #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ #endif /* _AVR_IOM8535_H_ */ avr-libc-1.8.0.orig/include/string.h0000644000000000000000000001321311732702554014154 0ustar /* Copyright (c) 2002,2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: string.h 1831 2008-12-21 02:27:49Z dmix $ */ /* string.h Contributors: Created by Marek Michalkiewicz */ #ifndef _STRING_H_ #define _STRING_H_ 1 #define __need_NULL #define __need_size_t #include #ifndef __ATTR_PURE__ #define __ATTR_PURE__ __attribute__((__pure__)) #endif #ifndef __ATTR_CONST__ # define __ATTR_CONST__ __attribute__((__const__)) #endif #ifdef __cplusplus extern "C" { #endif /** \file */ /** \defgroup avr_string : Strings \code #include \endcode The string functions perform string operations on NULL terminated strings. \note If the strings you are working on resident in program space (flash), you will need to use the string functions described in \ref avr_pgmspace. */ /** \ingroup avr_string This macro finds the first (least significant) bit set in the input value. This macro is very similar to the function ffs() except that it evaluates its argument at compile-time, so it should only be applied to compile-time constant expressions where it will reduce to a constant itself. Application of this macro to expressions that are not constant at compile-time is not recommended, and might result in a huge amount of code generated. \returns The _FFS() macro returns the position of the first (least significant) bit set in the word val, or 0 if no bits are set. The least significant bit is position 1. Only 16 bits of argument are evaluted. */ #if defined(__DOXYGEN__) #define _FFS(x) #else /* !DOXYGEN */ #define _FFS(x) \ (1 \ + (((x) & 1) == 0) \ + (((x) & 3) == 0) \ + (((x) & 7) == 0) \ + (((x) & 017) == 0) \ + (((x) & 037) == 0) \ + (((x) & 077) == 0) \ + (((x) & 0177) == 0) \ + (((x) & 0377) == 0) \ + (((x) & 0777) == 0) \ + (((x) & 01777) == 0) \ + (((x) & 03777) == 0) \ + (((x) & 07777) == 0) \ + (((x) & 017777) == 0) \ + (((x) & 037777) == 0) \ + (((x) & 077777) == 0) \ - (((x) & 0177777) == 0) * 16) #endif /* DOXYGEN */ extern int ffs (int __val) __ATTR_CONST__; extern int ffsl (long __val) __ATTR_CONST__; extern int ffsll (long long __val) __ATTR_CONST__; extern void *memccpy(void *, const void *, int, size_t); extern void *memchr(const void *, int, size_t) __ATTR_PURE__; extern int memcmp(const void *, const void *, size_t) __ATTR_PURE__; extern void *memcpy(void *, const void *, size_t); extern void *memmem(const void *, size_t, const void *, size_t) __ATTR_PURE__; extern void *memmove(void *, const void *, size_t); extern void *memrchr(const void *, int, size_t) __ATTR_PURE__; extern void *memset(void *, int, size_t); extern char *strcat(char *, const char *); extern char *strchr(const char *, int) __ATTR_PURE__; extern char *strchrnul(const char *, int) __ATTR_PURE__; extern int strcmp(const char *, const char *) __ATTR_PURE__; extern char *strcpy(char *, const char *); extern int strcasecmp(const char *, const char *) __ATTR_PURE__; extern char *strcasestr(const char *, const char *) __ATTR_PURE__; extern size_t strcspn(const char *__s, const char *__reject) __ATTR_PURE__; extern char *strdup(const char *s1); extern size_t strlcat(char *, const char *, size_t); extern size_t strlcpy(char *, const char *, size_t); extern size_t strlen(const char *) __ATTR_PURE__; extern char *strlwr(char *); extern char *strncat(char *, const char *, size_t); extern int strncmp(const char *, const char *, size_t) __ATTR_PURE__; extern char *strncpy(char *, const char *, size_t); extern int strncasecmp(const char *, const char *, size_t) __ATTR_PURE__; extern size_t strnlen(const char *, size_t) __ATTR_PURE__; extern char *strpbrk(const char *__s, const char *__accept) __ATTR_PURE__; extern char *strrchr(const char *, int) __ATTR_PURE__; extern char *strrev(char *); extern char *strsep(char **, const char *); extern size_t strspn(const char *__s, const char *__accept) __ATTR_PURE__; extern char *strstr(const char *, const char *) __ATTR_PURE__; extern char *strtok(char *, const char *); extern char *strtok_r(char *, const char *, char **); extern char *strupr(char *); #ifdef __cplusplus } #endif #endif /* _STRING_H_ */ avr-libc-1.8.0.orig/doc/0000755000000000000000000000000011732702554011617 5ustar avr-libc-1.8.0.orig/doc/api/0000755000000000000000000000000011732702554012370 5ustar avr-libc-1.8.0.orig/doc/api/vectortable.dox0000644000000000000000000011522511732702554015424 0ustar /* Note: this file has been automatically generated. */ /* DO NOT EDIT, or your changes WILL BE LOST! */ /* Copyright (c) 2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vectortable.dox 1530 2007-12-20 20:43:54Z joerg_wunsch $ */ /** \addtogroup avr_interrupts @{ \anchor avr_signames
Vector name Old vector name Description Applicable for device
ADC_vect SIG_ADC ADC Conversion Complete AT90S2333, AT90S4433, AT90S4434, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATtiny13, ATtiny15, ATtiny26, ATtiny43U, ATtiny48, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
ANALOG_COMP_0_vect SIG_COMPARATOR0 Analog Comparator 0 AT90PWM3, AT90PWM2, AT90PWM1
ANALOG_COMP_1_vect SIG_COMPARATOR1 Analog Comparator 1 AT90PWM3, AT90PWM2, AT90PWM1
ANALOG_COMP_2_vect SIG_COMPARATOR2 Analog Comparator 2 AT90PWM3, AT90PWM2, AT90PWM1
ANALOG_COMP_vect SIG_COMPARATOR Analog Comparator AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
ANA_COMP_vect SIG_COMPARATOR Analog Comparator AT90S1200, AT90S2313, AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, ATmega16, ATmega161, ATmega162, ATmega163, ATmega32, ATmega323, ATmega8, ATmega8515, ATmega8535, ATtiny11, ATtiny12, ATtiny13, ATtiny15, ATtiny2313, ATtiny26, ATtiny28, ATtiny43U, ATtiny48, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861
CANIT_vect SIG_CAN_INTERRUPT1 CAN Transfer Complete or Error AT90CAN128, AT90CAN32, AT90CAN64
EEPROM_READY_vect SIG_EEPROM_READY, SIG_EE_READY ATtiny2313
EE_RDY_vect SIG_EEPROM_READY EEPROM Ready AT90S2333, AT90S4433, AT90S4434, AT90S8535, ATmega16, ATmega161, ATmega162, ATmega163, ATmega32, ATmega323, ATmega8, ATmega8515, ATmega8535, ATtiny12, ATtiny13, ATtiny15, ATtiny26, ATtiny43U, ATtiny48, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861
EE_READY_vect SIG_EEPROM_READY EEPROM Ready AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega406, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
EXT_INT0_vect SIG_INTERRUPT0 External Interrupt Request 0 ATtiny24, ATtiny44, ATtiny84
INT0_vect SIG_INTERRUPT0 External Interrupt 0 AT90S1200, AT90S2313, AT90S2323, AT90S2333, AT90S2343, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega406, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8515, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny11, ATtiny12, ATtiny13, ATtiny15, ATtiny22, ATtiny2313, ATtiny26, ATtiny28, ATtiny43U, ATtiny48, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
INT1_vect SIG_INTERRUPT1 External Interrupt Request 1 AT90S2313, AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega168P, ATmega32, ATmega323, ATmega328P, ATmega32HVB, ATmega406, ATmega48P, ATmega64, ATmega8, ATmega8515, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny2313, ATtiny28, ATtiny48, ATtiny261, ATtiny461, ATtiny861, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
INT2_vect SIG_INTERRUPT2 External Interrupt Request 2 AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega32, ATmega323, ATmega32HVB, ATmega406, ATmega64, ATmega8515, ATmega8535, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
INT3_vect SIG_INTERRUPT3 External Interrupt Request 3 AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega32HVB, ATmega406, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
INT4_vect SIG_INTERRUPT4 External Interrupt Request 4 AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
INT5_vect SIG_INTERRUPT5 External Interrupt Request 5 AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
INT6_vect SIG_INTERRUPT6 External Interrupt Request 6 AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
INT7_vect SIG_INTERRUPT7 External Interrupt Request 7 AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
IO_PINS_vect SIG_PIN, SIG_PIN_CHANGE External Interrupt Request 0 ATtiny11, ATtiny12, ATtiny15, ATtiny26
LCD_vect SIG_LCD LCD Start of Frame ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega3290P, ATmega649, ATmega6490
LOWLEVEL_IO_PINS_vect SIG_PIN Low-level Input on Port B ATtiny28
OVRIT_vect SIG_CAN_OVERFLOW1 CAN Timer Overrun AT90CAN128, AT90CAN32, AT90CAN64
PCINT0_vect SIG_PIN_CHANGE0 Pin Change Interrupt Request 0 ATmega162, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega406, ATmega48P, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATtiny13, ATtiny43U, ATtiny48, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
PCINT1_vect SIG_PIN_CHANGE1 Pin Change Interrupt Request 1 ATmega162, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega406, ATmega48P, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATtiny43U, ATtiny48, ATtiny24, ATtiny44, ATtiny84, AT90USB162, AT90USB82
PCINT2_vect SIG_PIN_CHANGE2 Pin Change Interrupt Request 2 ATmega3250, ATmega3250P, ATmega328P, ATmega3290, ATmega3290P, ATmega48P, ATmega6450, ATmega6490, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATtiny48
PCINT3_vect SIG_PIN_CHANGE3 Pin Change Interrupt Request 3 ATmega3250, ATmega3250P, ATmega3290, ATmega3290P, ATmega6450, ATmega6490, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATtiny48
PCINT_vect SIG_PIN_CHANGE, SIG_PCINT ATtiny2313, ATtiny261, ATtiny461, ATtiny861
PSC0_CAPT_vect SIG_PSC0_CAPTURE PSC0 Capture Event AT90PWM3, AT90PWM2, AT90PWM1
PSC0_EC_vect SIG_PSC0_END_CYCLE PSC0 End Cycle AT90PWM3, AT90PWM2, AT90PWM1
PSC1_CAPT_vect SIG_PSC1_CAPTURE PSC1 Capture Event AT90PWM3, AT90PWM2, AT90PWM1
PSC1_EC_vect SIG_PSC1_END_CYCLE PSC1 End Cycle AT90PWM3, AT90PWM2, AT90PWM1
PSC2_CAPT_vect SIG_PSC2_CAPTURE PSC2 Capture Event AT90PWM3, AT90PWM2, AT90PWM1
PSC2_EC_vect SIG_PSC2_END_CYCLE PSC2 End Cycle AT90PWM3, AT90PWM2, AT90PWM1
SPI_STC_vect SIG_SPI Serial Transfer Complete AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8515, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny48, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
SPM_RDY_vect SIG_SPM_READY Store Program Memory Ready ATmega16, ATmega162, ATmega32, ATmega323, ATmega8, ATmega8515, ATmega8535
SPM_READY_vect SIG_SPM_READY Store Program Memory Read AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega406, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIM0_COMPA_vect SIG_OUTPUT_COMPARE0A Timer/Counter Compare Match A ATtiny13, ATtiny43U, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85
TIM0_COMPB_vect SIG_OUTPUT_COMPARE0B Timer/Counter Compare Match B ATtiny13, ATtiny43U, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85
TIM0_OVF_vect SIG_OVERFLOW0 Timer/Counter0 Overflow ATtiny13, ATtiny43U, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85
TIM1_CAPT_vect SIG_INPUT_CAPTURE1 Timer/Counter1 Capture Event ATtiny24, ATtiny44, ATtiny84
TIM1_COMPA_vect SIG_OUTPUT_COMPARE1A Timer/Counter1 Compare Match A ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85
TIM1_COMPB_vect SIG_OUTPUT_COMPARE1B Timer/Counter1 Compare Match B ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85
TIM1_OVF_vect SIG_OVERFLOW1 Timer/Counter1 Overflow ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85
TIMER0_CAPT_vect SIG_INPUT_CAPTURE0 ADC Conversion Complete ATtiny261, ATtiny461, ATtiny861
TIMER0_COMPA_vect SIG_OUTPUT_COMPARE0A TimerCounter0 Compare Match A ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny2313, ATtiny48, ATtiny261, ATtiny461, ATtiny861, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER0_COMPB_vect SIG_OUTPUT_COMPARE0B, SIG_OUTPUT_COMPARE0_B Timer Counter 0 Compare Match B AT90PWM3, AT90PWM2, AT90PWM1, ATmega1284P, ATmega168P, ATmega328P, ATmega32HVB, ATmega48P, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny2313, ATtiny48, ATtiny261, ATtiny461, ATtiny861, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER0_COMP_A_vect SIG_OUTPUT_COMPARE0A, SIG_OUTPUT_COMPARE0_A Timer/Counter0 Compare Match A AT90PWM3, AT90PWM2, AT90PWM1
TIMER0_COMP_vect SIG_OUTPUT_COMPARE0 Timer/Counter0 Compare Match AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega16, ATmega161, ATmega162, ATmega165, ATmega165P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega329, ATmega3290, ATmega3290P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8515, ATmega8535
TIMER0_OVF0_vect SIG_OVERFLOW0 Timer/Counter0 Overflow AT90S2313, AT90S2323, AT90S2343, ATtiny22, ATtiny26
TIMER0_OVF_vect SIG_OVERFLOW0 Timer/Counter0 Overflow AT90S1200, AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8515, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny11, ATtiny12, ATtiny15, ATtiny2313, ATtiny28, ATtiny48, ATtiny261, ATtiny461, ATtiny861, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER1_CAPT1_vect SIG_INPUT_CAPTURE1 Timer/Counter1 Capture Event AT90S2313
TIMER1_CAPT_vect SIG_INPUT_CAPTURE1 Timer/Counter Capture Event AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8515, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATtiny2313, ATtiny48, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER1_CMPA_vect SIG_OUTPUT_COMPARE1A Timer/Counter1 Compare Match 1A ATtiny26
TIMER1_CMPB_vect SIG_OUTPUT_COMPARE1B Timer/Counter1 Compare Match 1B ATtiny26
TIMER1_COMP1_vect SIG_OUTPUT_COMPARE1A Timer/Counter1 Compare Match AT90S2313
TIMER1_COMPA_vect SIG_OUTPUT_COMPARE1A Timer/Counter1 Compare Match A AT90S4414, AT90S4434, AT90S8515, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8515, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny2313, ATtiny48, ATtiny261, ATtiny461, ATtiny861, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER1_COMPB_vect SIG_OUTPUT_COMPARE1B Timer/Counter1 Compare MatchB AT90S4414, AT90S4434, AT90S8515, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8515, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny2313, ATtiny48, ATtiny261, ATtiny461, ATtiny861, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER1_COMPC_vect SIG_OUTPUT_COMPARE1C Timer/Counter1 Compare Match C AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER1_COMPD_vect SIG_OUTPUT_COMPARE0D Timer/Counter1 Compare Match D ATtiny261, ATtiny461, ATtiny861
TIMER1_COMP_vect SIG_OUTPUT_COMPARE1A Timer/Counter1 Compare Match AT90S2333, AT90S4433, ATtiny15
TIMER1_OVF1_vect SIG_OVERFLOW1 Timer/Counter1 Overflow AT90S2313, ATtiny26
TIMER1_OVF_vect SIG_OVERFLOW1 Timer/Counter1 Overflow AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, AT90PWM216, AT90PWM2B, AT90PWM316, AT90PWM3B, AT90PWM3, AT90PWM2, AT90PWM1, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega32HVB, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8515, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny15, ATtiny2313, ATtiny48, ATtiny261, ATtiny461, ATtiny861, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER2_COMPA_vect SIG_OUTPUT_COMPARE2A Timer/Counter2 Compare Match A ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER2_COMPB_vect SIG_OUTPUT_COMPARE2B Timer/Counter2 Compare Match A ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER2_COMP_vect SIG_OUTPUT_COMPARE2 Timer/Counter2 Compare Match AT90S4434, AT90S8535, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega329, ATmega3290, ATmega3290P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8535
TIMER2_OVF_vect SIG_OVERFLOW2 Timer/Counter2 Overflow AT90S4434, AT90S8535, AT90CAN128, AT90CAN32, AT90CAN64, ATmega103, ATmega128, ATmega1284P, ATmega16, ATmega161, ATmega162, ATmega163, ATmega165, ATmega165P, ATmega168P, ATmega169, ATmega169P, ATmega32, ATmega323, ATmega325, ATmega3250, ATmega3250P, ATmega328P, ATmega329, ATmega3290, ATmega3290P, ATmega48P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega8, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER3_CAPT_vect SIG_INPUT_CAPTURE3 Timer/Counter3 Capture Event AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega162, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER3_COMPA_vect SIG_OUTPUT_COMPARE3A Timer/Counter3 Compare Match A AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega162, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER3_COMPB_vect SIG_OUTPUT_COMPARE3B Timer/Counter3 Compare Match B AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega162, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER3_COMPC_vect SIG_OUTPUT_COMPARE3C Timer/Counter3 Compare Match C AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER3_OVF_vect SIG_OVERFLOW3 Timer/Counter3 Overflow AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega162, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TIMER4_CAPT_vect SIG_INPUT_CAPTURE4 Timer/Counter4 Capture Event ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TIMER4_COMPA_vect SIG_OUTPUT_COMPARE4A Timer/Counter4 Compare Match A ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TIMER4_COMPB_vect SIG_OUTPUT_COMPARE4B Timer/Counter4 Compare Match B ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TIMER4_COMPC_vect SIG_OUTPUT_COMPARE4C Timer/Counter4 Compare Match C ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TIMER4_OVF_vect SIG_OVERFLOW4 Timer/Counter4 Overflow ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TIMER5_CAPT_vect SIG_INPUT_CAPTURE5 Timer/Counter5 Capture Event ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TIMER5_COMPA_vect SIG_OUTPUT_COMPARE5A Timer/Counter5 Compare Match A ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TIMER5_COMPB_vect SIG_OUTPUT_COMPARE5B Timer/Counter5 Compare Match B ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TIMER5_COMPC_vect SIG_OUTPUT_COMPARE5C Timer/Counter5 Compare Match C ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TIMER5_OVF_vect SIG_OVERFLOW5 Timer/Counter5 Overflow ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
TWI_vect SIG_2WIRE_SERIAL 2-wire Serial Interface AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega16, ATmega163, ATmega168P, ATmega32, ATmega323, ATmega328P, ATmega32HVB, ATmega406, ATmega48P, ATmega64, ATmega8, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATtiny48, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
TXDONE_vect SIG_TXDONE Transmission Done, Bit Timer Flag 2 Interrupt AT86RF401
TXEMPTY_vect SIG_TXBE Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt AT86RF401
UART0_RX_vect SIG_UART0_RECV UART0, Rx Complete ATmega161
UART0_TX_vect SIG_UART0_TRANS UART0, Tx Complete ATmega161
UART0_UDRE_vect SIG_UART0_DATA UART0 Data Register Empty ATmega161
UART1_RX_vect SIG_UART1_RECV UART1, Rx Complete ATmega161
UART1_TX_vect SIG_UART1_TRANS UART1, Tx Complete ATmega161
UART1_UDRE_vect SIG_UART1_DATA UART1 Data Register Empty ATmega161
UART_RX_vect SIG_UART_RECV UART, Rx Complete AT90S2313, AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, ATmega103, ATmega163, ATmega8515
UART_TX_vect SIG_UART_TRANS UART, Tx Complete AT90S2313, AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, ATmega103, ATmega163, ATmega8515
UART_UDRE_vect SIG_UART_DATA UART Data Register Empty AT90S2313, AT90S2333, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, ATmega103, ATmega163, ATmega8515
USART0_RXC_vect SIG_USART0_RECV USART0, Rx Complete ATmega162
USART0_RX_vect SIG_UART0_RECV USART0, Rx Complete AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega165, ATmega165P, ATmega169, ATmega169P, ATmega325, ATmega329, ATmega64, ATmega645, ATmega649, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644
USART0_TXC_vect SIG_USART0_TRANS USART0, Tx Complete ATmega162
USART0_TX_vect SIG_UART0_TRANS USART0, Tx Complete AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega165, ATmega165P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega329, ATmega3290, ATmega3290P, ATmega64, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644
USART0_UDRE_vect SIG_UART0_DATA USART0 Data Register Empty AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega162, ATmega165, ATmega165P, ATmega169, ATmega169P, ATmega325, ATmega329, ATmega64, ATmega645, ATmega649, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644
USART1_RXC_vect SIG_USART1_RECV USART1, Rx Complete ATmega162
USART1_RX_vect SIG_UART1_RECV USART1, Rx Complete AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
USART1_TXC_vect SIG_USART1_TRANS USART1, Tx Complete ATmega162
USART1_TX_vect SIG_UART1_TRANS USART1, Tx Complete AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
USART1_UDRE_vect SIG_UART1_DATA USART1, Data Register Empty AT90CAN128, AT90CAN32, AT90CAN64, ATmega128, ATmega1284P, ATmega162, ATmega64, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
USART2_RX_vect SIG_USART2_RECV USART2, Rx Complete ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
USART2_TX_vect SIG_USART2_TRANS USART2, Tx Complete ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
USART2_UDRE_vect SIG_USART2_DATA USART2 Data register Empty ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
USART3_RX_vect SIG_USART3_RECV USART3, Rx Complete ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
USART3_TX_vect SIG_USART3_TRANS USART3, Tx Complete ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
USART3_UDRE_vect SIG_USART3_DATA USART3 Data register Empty ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561
USART_RXC_vect SIG_USART_RECV, SIG_UART_RECV USART, Rx Complete ATmega16, ATmega32, ATmega323, ATmega8
USART_RX_vect SIG_USART_RECV, SIG_UART_RECV USART, Rx Complete AT90PWM3, AT90PWM2, AT90PWM1, ATmega168P, ATmega3250, ATmega3250P, ATmega328P, ATmega3290, ATmega3290P, ATmega48P, ATmega6450, ATmega6490, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATtiny2313
USART_TXC_vect SIG_USART_TRANS, SIG_UART_TRANS USART, Tx Complete ATmega16, ATmega32, ATmega323, ATmega8
USART_TX_vect SIG_USART_TRANS, SIG_UART_TRANS USART, Tx Complete AT90PWM3, AT90PWM2, AT90PWM1, ATmega168P, ATmega328P, ATmega48P, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATtiny2313
USART_UDRE_vect SIG_USART_DATA, SIG_UART_DATA USART Data Register Empty AT90PWM3, AT90PWM2, AT90PWM1, ATmega16, ATmega168P, ATmega32, ATmega323, ATmega3250, ATmega3250P, ATmega328P, ATmega3290, ATmega3290P, ATmega48P, ATmega6450, ATmega6490, ATmega8, ATmega8535, ATmega88P, ATmega168, ATmega48, ATmega88, ATtiny2313
USI_OVERFLOW_vect SIG_USI_OVERFLOW USI Overflow ATmega165, ATmega165P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega329, ATmega3290, ATmega3290P, ATmega645, ATmega6450, ATmega649, ATmega6490, ATtiny2313
USI_OVF_vect SIG_USI_OVERFLOW USI Overflow ATtiny26, ATtiny43U, ATtiny24, ATtiny44, ATtiny84, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861
USI_START_vect SIG_USI_START USI Start Condition ATmega165, ATmega165P, ATmega169, ATmega169P, ATmega325, ATmega3250, ATmega3250P, ATmega329, ATmega3290, ATmega3290P, ATmega645, ATmega6450, ATmega649, ATmega6490, ATtiny2313, ATtiny43U, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861
USI_STRT_vect SIG_USI_START USI Start ATtiny26
USI_STR_vect SIG_USI_START USI START ATtiny24, ATtiny44, ATtiny84
WATCHDOG_vect SIG_WATCHDOG_TIMEOUT Watchdog Time-out ATtiny24, ATtiny44, ATtiny84
WDT_OVERFLOW_vect SIG_WATCHDOG_TIMEOUT, SIG_WDT_OVERFLOW Watchdog Timer Overflow ATtiny2313
WDT_vect SIG_WDT, SIG_WATCHDOG_TIMEOUT Watchdog Timeout Interrupt AT90PWM3, AT90PWM2, AT90PWM1, ATmega1284P, ATmega168P, ATmega328P, ATmega32HVB, ATmega406, ATmega48P, ATmega88P, ATmega168, ATmega48, ATmega88, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega324P, ATmega164P, ATmega644P, ATmega644, ATmega16HVA, ATtiny13, ATtiny43U, ATtiny48, ATtiny45, ATtiny25, ATtiny85, ATtiny261, ATtiny461, ATtiny861, AT90USB162, AT90USB82, AT90USB1287, AT90USB1286, AT90USB647, AT90USB646
@}*/ avr-libc-1.8.0.orig/doc/api/assembler.dox0000644000000000000000000003006311732702554015063 0ustar /* Copyright (c) 2002,2004,2005,2009 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: assembler.dox 1876 2009-02-11 18:57:36Z joerg_wunsch $ */ /** \page assembler avr-libc and assembler programs \section ass_intro Introduction There might be several reasons to write code for AVR microcontrollers using plain assembler source code. Among them are: - Code for devices that do not have RAM and are thus not supported by the C compiler. - Code for very time-critical applications. - Special tweaks that cannot be done in C. Usually, all but the first could probably be done easily using the \ref inline_asm "inline assembler" facility of the compiler. Although avr-libc is primarily targeted to support programming AVR microcontrollers using the C (and C++) language, there's limited support for direct assembler usage as well. The benefits of it are: - Use of the C preprocessor and thus the ability to use the same symbolic constants that are available to C programs, as well as a flexible macro concept that can use any valid C identifier as a macro (whereas the assembler's macro concept is basically targeted to use a macro in place of an assembler instruction). - Use of the runtime framework like automatically assigning interrupt vectors. For devices that have RAM, \ref sec_dot_init "initializing the RAM variables" can also be utilized. \section ass_tools Invoking the compiler For the purpose described in this document, the assembler and linker are usually not invoked manually, but rather using the C compiler frontend (\c avr-gcc) that in turn will call the assembler and linker as required. This approach has the following advantages: - There is basically only one program to be called directly, \c avr-gcc, regardless of the actual source language used. - The invokation of the C preprocessor will be automatic, and will include the appropriate options to locate required include files in the filesystem. - The invokation of the linker will be automatic, and will include the appropriate options to locate additional libraries as well as the application start-up code (crtXXX.o) and linker script. Note that the invokation of the C preprocessor will be automatic when the filename provided for the assembler file ends in \c .S (the capital letter "s"). This would even apply to operating systems that use case-insensitive filesystems since the actual decision is made based on the case of the filename suffix given on the command-line, not based on the actual filename from the file system. Alternatively, the language can explicitly be specified using the -x assembler-with-cpp option. \section ass_example Example program The following annotated example features a simple 100 kHz square wave generator using an AT90S1200 clocked with a 10.7 MHz crystal. Pin PD6 will be used for the square wave output. \code #include ; Note [1] work = 16 ; Note [2] tmp = 17 inttmp = 19 intsav = 0 SQUARE = PD6 ; Note [3] ; Note [4]: tmconst= 10700000 / 200000 ; 100 kHz => 200000 edges/s fuzz= 8 ; # clocks in ISR until TCNT0 is set .section .text .global main ; Note [5] main: rcall ioinit 1: rjmp 1b ; Note [6] .global TIMER0_OVF_vect ; Note [7] TIMER0_OVF_vect: ldi inttmp, 256 - tmconst + fuzz out _SFR_IO_ADDR(TCNT0), inttmp ; Note [8] in intsav, _SFR_IO_ADDR(SREG) ; Note [9] sbic _SFR_IO_ADDR(PORTD), SQUARE rjmp 1f sbi _SFR_IO_ADDR(PORTD), SQUARE rjmp 2f 1: cbi _SFR_IO_ADDR(PORTD), SQUARE 2: out _SFR_IO_ADDR(SREG), intsav reti ioinit: sbi _SFR_IO_ADDR(DDRD), SQUARE ldi work, _BV(TOIE0) out _SFR_IO_ADDR(TIMSK), work ldi work, _BV(CS00) ; tmr0: CK/1 out _SFR_IO_ADDR(TCCR0), work ldi work, 256 - tmconst out _SFR_IO_ADDR(TCNT0), work sei ret .global __vector_default ; Note [10] __vector_default: reti .end \endcode \par Note [1] As in C programs, this includes the central processor-specific file containing the IO port definitions for the device. Note that not all include files can be included into assembler sources. \par Note [2] Assignment of registers to symbolic names used locally. Another option would be to use a C preprocessor macro instead: \code #define work 16 \endcode \par Note [3] Our bit number for the square wave output. Note that the right-hand side consists of a CPP macro which will be substituted by its value (6 in this case) before actually being passed to the assembler. \par Note [4] The assembler uses integer operations in the host-defined integer size (32 bits or longer) when evaluating expressions. This is in contrast to the C compiler that uses the C type \c int by default in order to calculate constant integer expressions.
In order to get a 100 kHz output, we need to toggle the PD6 line 200000 times per second. Since we use timer 0 without any prescaling options in order to get the desired frequency and accuracy, we already run into serious timing considerations: while accepting and processing the timer overflow interrupt, the timer already continues to count. When pre-loading the \c TCCNT0 register, we therefore have to account for the number of clock cycles required for interrupt acknowledge and for the instructions to reload \c TCCNT0 (4 clock cycles for interrupt acknowledge, 2 cycles for the jump from the interrupt vector, 2 cycles for the 2 instructions that reload \c TCCNT0). This is what the constant \c fuzz is for. \par Note [5] External functions need to be declared to be \c .global. \c main is the application entry point that will be jumped to from the ininitalization routine in \c crts1200.o. \par Note [6] The main loop is just a single jump back to itself. Square wave generation itself is completely handled by the timer 0 overflow interrupt service. A \c sleep instruction (using idle mode) could be used as well, but probably would not conserve much energy anyway since the interrupt service is executed quite frequently. \par Note [7] Interrupt functions can get the \ref avr_signames "usual names" that are also available to C programs. The linker will then put them into the appropriate interrupt vector slots. Note that they must be declared \c .global in order to be acceptable for this purpose. This will only work if <avr/io.h> has been included. Note that the assembler or linker have no chance to check the correct spelling of an interrupt function, so it should be double-checked. (When analyzing the resulting object file using \c avr-objdump or \c avr-nm, a name like __vector_N should appear, with \e N being a small integer number.) \par Note [8] As explained in the section about \ref avr_sfr_notes "special function registers", the actual IO port address should be obtained using the macro \c _SFR_IO_ADDR. (The AT90S1200 does not have RAM thus the memory-mapped approach to access the IO registers is not available. It would be slower than using \c in / \c out instructions anyway.)
Since the operation to reload \c TCCNT0 is time-critical, it is even performed before saving \c SREG. Obviously, this requires that the instructions involved would not change any of the flag bits in \c SREG. \anchor ass_isr \par Note [9] Interrupt routines must not clobber the global CPU state. Thus, it is usually necessary to save at least the state of the flag bits in \c SREG. (Note that this serves as an example here only since actually, all the following instructions would not modify \c SREG either, but that's not commonly the case.)
Also, it must be made sure that registers used inside the interrupt routine do not conflict with those used outside. In the case of a RAM-less device like the AT90S1200, this can only be done by agreeing on a set of registers to be used exclusively inside the interrupt routine; there would not be any other chance to "save" a register anywhere.
If the interrupt routine is to be linked together with C modules, care must be taken to follow the \ref faq_reg_usage "register usage guidelines" imposed by the C compiler. Also, any register modified inside the interrupt sevice needs to be saved, usually on the stack. \par Note [10] As explained in \ref avr_interrupts "Interrupts", a global "catch-all" interrupt handler that gets all unassigned interrupt vectors can be installed using the name \c __vector_default. This must be \c .global, and obviously, should end in a \c reti instruction. (By default, a jump to location 0 would be implied instead.) \section ass_pseudoops Pseudo-ops and operators The available pseudo-ops in the assembler are described in the GNU assembler (gas) manual. The manual can be found online as part of the current binutils release under http://sources.redhat.com/binutils/. As gas comes from a Unix origin, its pseudo-op and overall assembler syntax is slightly different than the one being used by other assemblers. Numeric constants follow the C notation (prefix \c 0x for hexadecimal constants), expressions use a C-like syntax. Some common pseudo-ops include: - \c .byte allocates single byte constants - \c .ascii allocates a non-terminated string of characters - \c .asciz allocates a \\0-terminated string of characters (C string) - \c .data switches to the .data section (initialized RAM variables) - \c .text switches to the .text section (code and ROM constants) - \c .set declares a symbol as a constant expression (identical to \c .equ) - \c .global (or \c .globl) declares a public symbol that is visible to the linker (e. g. function entry point, global variable) - \c .extern declares a symbol to be externally defined; this is effectively a comment only, as gas treats all undefined symbols it encounters as globally undefined anyway Note that \c .org is available in gas as well, but is a fairly pointless pseudo-op in an assembler environment that uses relocatable object files, as it is the linker that determines the final position of some object in ROM or RAM. Along with the architecture-independent standard operators, there are some AVR-specific operators available which are unfortunately not yet described in the official documentation. The most notable operators are: - \c lo8 Takes the least significant 8 bits of a 16-bit integer - \c hi8 Takes the most significant 8 bits of a 16-bit integer - \c pm Takes a program-memory (ROM) address, and converts it into a RAM address. This implies a division by 2 as the AVR handles ROM addresses as 16-bit words (e.g. in an \c IJMP or \c ICALL instruction), and can also handle relocatable symbols on the right-hand side. Example: \verbatim ldi r24, lo8(pm(somefunc)) ldi r25, hi8(pm(somefunc)) call something \endverbatim This passes the address of function \c somefunc as the first parameter to function \c something. */ avr-libc-1.8.0.orig/doc/api/malloc-x2.fig0000644000000000000000000000623611732702554014664 0ustar #FIG 3.2 Landscape Center Metric A4 100.00 Single -2 1200 2 0 32 #cfcfcf 0 33 #fff7be 2 1 0 2 0 7 50 0 -1 0.000 0 0 -1 1 0 2 1 1 2.00 120.00 240.00 4050 2250 3375 2250 2 2 0 0 0 26 100 0 20 0.000 0 0 -1 0 0 5 3375 3150 4185 3150 4185 1800 3375 1800 3375 3150 2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 450 1800 7200 1800 7200 3150 450 3150 450 1800 2 2 0 0 0 3 100 0 20 0.000 0 0 -1 0 0 5 450 3150 1350 3150 1350 1800 450 1800 450 3150 2 2 0 0 0 14 100 0 20 0.000 0 0 -1 0 0 5 1350 3150 2250 3150 2250 1800 1350 1800 1350 3150 2 2 0 0 0 32 100 0 20 0.000 0 0 -1 0 0 5 2250 3150 3375 3150 3375 1800 2250 1800 2250 3150 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 2700 4140 2250 4140 2250 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 2700 4410 1350 4410 1350 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 2700 4725 450 4725 450 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 3060 3600 3375 3600 3375 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 3645 3870 4140 3870 4140 3285 2 2 0 0 0 23 100 0 20 0.000 0 0 -1 0 0 5 4995 3150 5895 3150 5895 1800 4995 1800 4995 3150 2 1 0 2 0 7 50 0 -1 0.000 0 0 -1 1 0 2 1 1 2.00 120.00 240.00 5130 2250 5850 2250 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 6345 3870 5895 3870 5895 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 6345 4140 4995 4140 4995 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 6525 3600 6300 3600 6300 3285 2 2 0 0 0 33 100 0 20 0.000 0 0 -1 0 0 5 4185 3150 4995 3150 4995 1800 4185 1800 4185 3150 2 2 0 0 0 32 100 0 20 0.000 0 0 -1 0 0 5 5895 3150 6300 3150 6300 1800 5895 1800 5895 3150 2 2 0 0 0 33 100 0 20 0.000 0 0 -1 0 0 5 6300 3150 7200 3150 7200 1800 6300 1800 6300 3150 2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2 4185 1800 4185 3150 4 0 0 50 0 16 12 1.5708 4 135 645 4140 1665 0x10FF\001 4 0 0 50 0 16 12 1.5708 4 135 615 630 1620 0x0100\001 4 0 0 50 0 16 12 0.0000 4 135 435 3555 2700 stack\001 4 0 0 50 0 16 18 0.0000 4 210 1815 1305 1530 on-board RAM\001 4 0 0 50 0 16 12 1.5708 4 135 615 4410 1665 0x1100\001 4 0 0 50 0 16 12 1.5708 4 135 675 7155 1665 0xFFFF\001 4 0 0 50 0 16 12 0.0000 4 135 405 675 2430 .data\001 4 0 0 50 0 16 12 0.0000 4 135 765 1440 2700 variables\001 4 0 0 50 0 16 12 0.0000 4 135 765 540 2700 variables\001 4 0 0 50 0 16 12 0.0000 4 135 330 1620 2430 .bss\001 4 0 0 100 0 16 12 0.0000 4 135 240 2745 3645 SP\001 4 0 0 100 0 16 12 0.0000 4 135 810 2745 3915 RAMEND\001 4 0 0 100 0 16 12 0.0000 4 165 915 2835 4185 __bss_end\001 4 0 0 100 0 16 12 0.0000 4 165 2265 2835 4455 __data_end == __bss_start\001 4 0 0 100 0 16 12 0.0000 4 165 1020 2835 4770 __data_start\001 4 0 0 50 0 16 12 0.0000 4 180 420 5175 2700 heap\001 4 0 0 50 0 16 12 1.5708 4 135 615 5085 1665 0x2000\001 4 0 0 50 0 16 18 0.0000 4 210 1650 4815 945 external RAM\001 4 0 0 50 0 16 12 1.5708 4 135 660 6345 1665 0x3FFF\001 4 0 0 100 0 16 12 0.0000 4 180 3270 6615 3645 *(__malloc_heap_end) == __heap_end\001 4 0 0 100 0 16 12 0.0000 4 180 915 6480 3915 *(__brkval)\001 4 0 0 100 0 16 12 0.0000 4 180 3330 6435 4185 *(__malloc_heap_start) == __heap_start\001 avr-libc-1.8.0.orig/doc/api/using-avrprog.dox0000644000000000000000000001144411732702554015713 0ustar /* Copyright (c) 2002, Brian Dean All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: using-avrprog.dox 291 2003-02-27 18:32:46Z troth $ */ /** \page using_avrprog Using the avrdude program \addindex avrprog, usage \addindex avrdude, usage \note This section was contributed by Brian Dean [ bsd@bsdhome.com ]. \note The avrdude program was previously called avrprog. The name was changed to avoid confusion with the avrprog program that Atmel ships with AvrStudio. \c avrdude is a program that is used to update or read the flash and EEPROM memories of Atmel AVR microcontrollers on FreeBSD Unix. It supports the Atmel serial programming protocol using the PC's parallel port and can upload either a raw binary file or an Intel Hex format file. It can also be used in an interactive mode to individually update EEPROM cells, fuse bits, and/or lock bits (if their access is supported by the Atmel serial programming protocol.) The main flash instruction memory of the AVR can also be programmed in interactive mode, however this is not very useful because one can only turn bits off. The only way to turn flash bits on is to erase the entire memory (using avrdude's \c -e option). \c avrdude is part of the FreeBSD ports system. To install it, simply do the following: \verbatim # cd /usr/ports/devel/avrdude # make install \endverbatim Once installed, \c avrdude can program processors using the contents of the \c .hex file specified on the command line. In this example, the file \c main.hex is burned into the flash memory: \verbatim # avrdude -p 2313 -e -m flash -i main.hex avrdude: AVR device initialized and ready to accept instructions avrdude: Device signature = 0x1e9101 avrdude: erasing chip avrdude: done. avrdude: reading input file "main.hex" avrdude: input file main.hex auto detected as Intel Hex avrdude: writing flash: 1749 0x00 avrdude: 1750 bytes of flash written avrdude: verifying flash memory against main.hex: avrdude: reading on-chip flash data: 1749 0x00 avrdude: verifying ... avrdude: 1750 bytes of flash verified avrdude done. Thank you. \endverbatim The -p 2313 option lets \c avrdude know that we are operating on an AT90S2313 chip. This option specifies the device id and is matched up with the device of the same id in avrdude's configuration file ( \c /usr/local/etc/avrdude.conf ). To list valid parts, specify the \c -v option. The \c -e option instructs \c avrdude to perform a chip-erase before programming; this is almost always necessary before programming the flash. The -m flash option indicates that we want to upload data into the flash memory, while -i main.hex specifies the name of the input file. The EEPROM is uploaded in the same way, the only difference is that you would use -m eeprom instead of -m flash. To use interactive mode, use the -t option: \verbatim # avrdude -p 2313 -t avrdude: AVR device initialized and ready to accept instructions avrdude: Device signature = 0x1e9101 avrdude> The '?' command displays a list of valid commands: avrdude> ? >>> ? Valid commands: dump : dump memory : dump read : alias for dump write : write memory : write ... erase : perform a chip erase sig : display device signature bytes part : display the current part information send : send a raw command : send help : help ? : help quit : quit Use the 'part' command to display valid memory types for use with the 'dump' and 'write' commands. avrdude> \endverbatim */ avr-libc-1.8.0.orig/doc/api/doxygen.config.in0000644000000000000000000020013711732702554015644 0ustar # $Id: doxygen.config.in 2158 2010-06-10 15:48:28Z joerg_wunsch $ # @configure_input@ # Doxygen configuration file for the avr-libc project. # Doxyfile 1.5.7 # This file describes the settings to be used by the documentation system # doxygen (www.doxygen.org) for a project # # All text after a hash (#) is considered a comment and will be ignored # The format is: # TAG = value [value, ...] # For lists items can also be appended using: # TAG += value [value, ...] # Values that contain spaces should be placed between quotes (" ") #--------------------------------------------------------------------------- # Project related configuration options #--------------------------------------------------------------------------- # This tag specifies the encoding used for all characters in the config file # that follow. The default is UTF-8 which is also the encoding used for all # text before the first occurrence of this tag. Doxygen uses libiconv (or the # iconv built into libc) for the transcoding. See # http://www.gnu.org/software/libiconv for the list of possible encodings. DOXYFILE_ENCODING = iso-8859-1 # The PROJECT_NAME tag is a single word (or a sequence of words surrounded # by quotes) that should identify the project. PROJECT_NAME = avr-libc # The PROJECT_NUMBER tag can be used to enter a project or revision number. # This could be handy for archiving the generated documentation or # if some version control system is used. PROJECT_NUMBER = @VERSION@ # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. # If a relative path is entered, it will be relative to the location # where doxygen was started. If left blank the current directory will be used. OUTPUT_DIRECTORY = # If the CREATE_SUBDIRS tag is set to YES, then doxygen will create # 4096 sub-directories (in 2 levels) under the output directory of each output # format and will distribute the generated files over these directories. # Enabling this option can be useful when feeding doxygen a huge amount of # source files, where putting all generated files in the same directory would # otherwise cause performance problems for the file system. CREATE_SUBDIRS = NO # The OUTPUT_LANGUAGE tag is used to specify the language in which all # documentation generated by doxygen is written. Doxygen will use this # information to generate all constant output in the proper language. # The default language is English, other supported languages are: # Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, # Croatian, Czech, Danish, Dutch, Farsi, Finnish, French, German, Greek, # Hungarian, Italian, Japanese, Japanese-en (Japanese with English messages), # Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, Polish, # Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, Slovene, # Spanish, Swedish, and Ukrainian. OUTPUT_LANGUAGE = English # If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will # include brief member descriptions after the members that are listed in # the file and class documentation (similar to JavaDoc). # Set to NO to disable this. BRIEF_MEMBER_DESC = NO # If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend # the brief description of a member or function before the detailed description. # Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the # brief descriptions will be completely suppressed. REPEAT_BRIEF = YES # This tag implements a quasi-intelligent brief description abbreviator # that is used to form the text in various listings. Each string # in this list, if found as the leading text of the brief description, will be # stripped from the text and the result after processing the whole list, is # used as the annotated text. Otherwise, the brief description is used as-is. # If left blank, the following values are used ("$name" is automatically # replaced with the name of the entity): "The $name class" "The $name widget" # "The $name file" "is" "provides" "specifies" "contains" # "represents" "a" "an" "the" ABBREVIATE_BRIEF = # If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then # Doxygen will generate a detailed section even if there is only a brief # description. ALWAYS_DETAILED_SEC = YES # If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all # inherited members of a class in the documentation of that class as if those # members were ordinary class members. Constructors, destructors and assignment # operators of the base classes will not be shown. INLINE_INHERITED_MEMB = NO # If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full # path before files name in the file list and in the header files. If set # to NO the shortest path that makes the file name unique will be used. FULL_PATH_NAMES = NO # If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag # can be used to strip a user-defined part of the path. Stripping is # only done if one of the specified strings matches the left-hand part of # the path. The tag can be used to show relative paths in the file list. # If left blank the directory from which doxygen is run is used as the # path to strip. STRIP_FROM_PATH = # The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of # the path mentioned in the documentation of a class, which tells # the reader which header file to include in order to use a class. # If left blank only the name of the header file containing the class # definition is used. Otherwise one should specify the include paths that # are normally passed to the compiler using the -I flag. STRIP_FROM_INC_PATH = # If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter # (but less readable) file names. This can be useful is your file systems # doesn't support long names like on DOS, Mac, or CD-ROM. SHORT_NAMES = NO # If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen # will interpret the first line (until the first dot) of a JavaDoc-style # comment as the brief description. If set to NO, the JavaDoc # comments will behave just like regular Qt-style comments # (thus requiring an explicit @brief command for a brief description.) JAVADOC_AUTOBRIEF = NO # If the QT_AUTOBRIEF tag is set to YES then Doxygen will # interpret the first line (until the first dot) of a Qt-style # comment as the brief description. If set to NO, the comments # will behave just like regular Qt-style comments (thus requiring # an explicit \brief command for a brief description.) QT_AUTOBRIEF = NO # The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen # treat a multi-line C++ special comment block (i.e. a block of //! or /// # comments) as a brief description. This used to be the default behaviour. # The new default is to treat a multi-line C++ comment block as a detailed # description. Set this tag to YES if you prefer the old behaviour instead. MULTILINE_CPP_IS_BRIEF = NO # If the INHERIT_DOCS tag is set to YES (the default) then an undocumented # member inherits the documentation from any documented member that it # re-implements. INHERIT_DOCS = YES # If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce # a new page for each member. If set to NO, the documentation of a member will # be part of the file/class/namespace that contains it. SEPARATE_MEMBER_PAGES = NO # The TAB_SIZE tag can be used to set the number of spaces in a tab. # Doxygen uses this value to replace tabs by spaces in code fragments. TAB_SIZE = 8 # This tag can be used to specify a number of aliases that acts # as commands in the documentation. An alias has the form "name=value". # For example adding "sideeffect=\par Side Effects:\n" will allow you to # put the command \sideeffect (or @sideeffect) in the documentation, which # will result in a user-defined paragraph with heading "Side Effects:". # You can put \n's in the value part of an alias to insert newlines. ALIASES = # Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C # sources only. Doxygen will then generate output that is more tailored for C. # For instance, some of the names that are used will be different. The list # of all members will be omitted, etc. OPTIMIZE_OUTPUT_FOR_C = YES # Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java # sources only. Doxygen will then generate output that is more tailored for # Java. For instance, namespaces will be presented as packages, qualified # scopes will look different, etc. OPTIMIZE_OUTPUT_JAVA = NO # Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran # sources only. Doxygen will then generate output that is more tailored for # Fortran. OPTIMIZE_FOR_FORTRAN = NO # Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL # sources. Doxygen will then generate output that is tailored for # VHDL. OPTIMIZE_OUTPUT_VHDL = NO # If you use STL classes (i.e. std::string, std::vector, etc.) but do not want # to include (a tag file for) the STL sources as input, then you should # set this tag to YES in order to let doxygen match functions declarations and # definitions whose arguments contain STL classes (e.g. func(std::string); v.s. # func(std::string) {}). This also make the inheritance and collaboration # diagrams that involve STL classes more complete and accurate. BUILTIN_STL_SUPPORT = NO # If you use Microsoft's C++/CLI language, you should set this option to YES to # enable parsing support. CPP_CLI_SUPPORT = NO # If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC # tag is set to YES, then doxygen will reuse the documentation of the first # member in the group (if any) for the other members of the group. By default # all members of a group must be documented explicitly. DISTRIBUTE_GROUP_DOC = NO # Set the SUBGROUPING tag to YES (the default) to allow class member groups of # the same type (for instance a group of public functions) to be put as a # subgroup of that type (e.g. under the Public Functions section). Set it to # NO to prevent subgrouping. Alternatively, this can be done per class using # the \nosubgrouping command. SUBGROUPING = YES # When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum # is documented as struct, union, or enum with the name of the typedef. So # typedef struct TypeS {} TypeT, will appear in the documentation as a struct # with name TypeT. When disabled the typedef will appear as a member of a file, # namespace, or class. And the struct will be named TypeS. This can typically # be useful for C code in case the coding convention dictates that all compound # types are typedef'ed and only the typedef is referenced, never the tag name. TYPEDEF_HIDES_STRUCT = NO # The SYMBOL_CACHE_SIZE determines the size of the internal cache use to # determine which symbols to keep in memory and which to flush to disk. # When the cache is full, less often used symbols will be written to disk. # For small to medium size projects (<1000 input files) the default value is # probably good enough. For larger projects a too small cache size can cause # doxygen to be busy swapping symbols to and from disk most of the time # causing a significant performance penality. # If the system has enough physical memory increasing the cache will improve the # performance by keeping more symbols in memory. Note that the value works on # a logarithmic scale so increasing the size by one will rougly double the # memory usage. The cache size is given by this formula: # 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, # corresponding to a cache size of 2^16 = 65536 symbols SYMBOL_CACHE_SIZE = 0 #--------------------------------------------------------------------------- # Build related configuration options #--------------------------------------------------------------------------- # If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in # documentation are documented, even if no documentation was available. # Private class members and static file members will be hidden unless # the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES EXTRACT_ALL = NO # If the EXTRACT_PRIVATE tag is set to YES all private members of a class # will be included in the documentation. EXTRACT_PRIVATE = NO # If the EXTRACT_STATIC tag is set to YES all static members of a file # will be included in the documentation. EXTRACT_STATIC = YES # If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) # defined locally in source files will be included in the documentation. # If set to NO only classes defined in header files are included. EXTRACT_LOCAL_CLASSES = YES # This flag is only useful for Objective-C code. When set to YES local # methods, which are defined in the implementation section but not in # the interface are included in the documentation. # If set to NO (the default) only methods in the interface are included. EXTRACT_LOCAL_METHODS = NO # If this flag is set to YES, the members of anonymous namespaces will be # extracted and appear in the documentation as a namespace called # 'anonymous_namespace{file}', where file will be replaced with the base # name of the file that contains the anonymous namespace. By default # anonymous namespace are hidden. EXTRACT_ANON_NSPACES = NO # If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all # undocumented members of documented classes, files or namespaces. # If set to NO (the default) these members will be included in the # various overviews, but no documentation section is generated. # This option has no effect if EXTRACT_ALL is enabled. HIDE_UNDOC_MEMBERS = NO # If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all # undocumented classes that are normally visible in the class hierarchy. # If set to NO (the default) these classes will be included in the various # overviews. This option has no effect if EXTRACT_ALL is enabled. HIDE_UNDOC_CLASSES = NO # If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all # friend (class|struct|union) declarations. # If set to NO (the default) these declarations will be included in the # documentation. HIDE_FRIEND_COMPOUNDS = NO # If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any # documentation blocks found inside the body of a function. # If set to NO (the default) these blocks will be appended to the # function's detailed documentation block. HIDE_IN_BODY_DOCS = NO # The INTERNAL_DOCS tag determines if documentation # that is typed after a \internal command is included. If the tag is set # to NO (the default) then the documentation will be excluded. # Set it to YES to include the internal documentation. INTERNAL_DOCS = NO # If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate # file names in lower-case letters. If set to YES upper-case letters are also # allowed. This is useful if you have classes or files whose names only differ # in case and if your file system supports case sensitive file names. Windows # and Mac users are advised to set this option to NO. CASE_SENSE_NAMES = YES # If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen # will show members with their full class and namespace scopes in the # documentation. If set to YES the scope will be hidden. HIDE_SCOPE_NAMES = NO # If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen # will put a list of the files that are included by a file in the documentation # of that file. SHOW_INCLUDE_FILES = NO # If the INLINE_INFO tag is set to YES (the default) then a tag [inline] # is inserted in the documentation for inline members. INLINE_INFO = NO # If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen # will sort the (detailed) documentation of file and class members # alphabetically by member name. If set to NO the members will appear in # declaration order. SORT_MEMBER_DOCS = YES # If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the # brief documentation of file, namespace and class members alphabetically # by member name. If set to NO (the default) the members will appear in # declaration order. SORT_BRIEF_DOCS = NO # If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the # hierarchy of group names into alphabetical order. If set to NO (the default) # the group names will appear in their defined order. SORT_GROUP_NAMES = NO # If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be # sorted by fully-qualified names, including namespaces. If set to # NO (the default), the class list will be sorted only by class name, # not including the namespace part. # Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. # Note: This option applies only to the class list, not to the # alphabetical list. SORT_BY_SCOPE_NAME = NO # The GENERATE_TODOLIST tag can be used to enable (YES) or # disable (NO) the todo list. This list is created by putting \todo # commands in the documentation. GENERATE_TODOLIST = YES # The GENERATE_TESTLIST tag can be used to enable (YES) or # disable (NO) the test list. This list is created by putting \test # commands in the documentation. GENERATE_TESTLIST = YES # The GENERATE_BUGLIST tag can be used to enable (YES) or # disable (NO) the bug list. This list is created by putting \bug # commands in the documentation. GENERATE_BUGLIST = YES # The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or # disable (NO) the deprecated list. This list is created by putting # \deprecated commands in the documentation. GENERATE_DEPRECATEDLIST= YES # The ENABLED_SECTIONS tag can be used to enable conditional # documentation sections, marked by \if sectionname ... \endif. ENABLED_SECTIONS = # The MAX_INITIALIZER_LINES tag determines the maximum number of lines # the initial value of a variable or define consists of for it to appear in # the documentation. If the initializer consists of more lines than specified # here it will be hidden. Use a value of 0 to hide initializers completely. # The appearance of the initializer of individual variables and defines in the # documentation can be controlled using \showinitializer or \hideinitializer # command in the documentation regardless of this setting. MAX_INITIALIZER_LINES = 30 # Set the SHOW_USED_FILES tag to NO to disable the list of files generated # at the bottom of the documentation of classes and structs. If set to YES the # list will mention the files that were used to generate the documentation. SHOW_USED_FILES = YES # If the sources in your project are distributed over multiple directories # then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy # in the documentation. The default is NO. SHOW_DIRECTORIES = NO # Set the SHOW_FILES tag to NO to disable the generation of the Files page. # This will remove the Files entry from the Quick Index and from the # Folder Tree View (if specified). The default is YES. SHOW_FILES = YES # Set the SHOW_NAMESPACES tag to NO to disable the generation of the # Namespaces page. This will remove the Namespaces entry from the Quick Index # and from the Folder Tree View (if specified). The default is YES. SHOW_NAMESPACES = YES # The FILE_VERSION_FILTER tag can be used to specify a program or script that # doxygen should invoke to get the current version for each file (typically from # the version control system). Doxygen will invoke the program by executing (via # popen()) the command , where is the value of # the FILE_VERSION_FILTER tag, and is the name of an input file # provided by doxygen. Whatever the program writes to standard output # is used as the file version. See the manual for examples. FILE_VERSION_FILTER = # The LAYOUT_FILE tag can be used to specify a layout file which will be parsed by # doxygen. The layout file controls the global structure of the generated output files # in an output format independent way. The create the layout file that represents # doxygen's defaults, run doxygen with the -l option. You can optionally specify a # file name after the option, if omitted DoxygenLayout.xml will be used as the name # of the layout file. LAYOUT_FILE = #--------------------------------------------------------------------------- # configuration options related to warning and progress messages #--------------------------------------------------------------------------- # The QUIET tag can be used to turn on/off the messages that are generated # by doxygen. Possible values are YES and NO. If left blank NO is used. QUIET = NO # The WARNINGS tag can be used to turn on/off the warning messages that are # generated by doxygen. Possible values are YES and NO. If left blank # NO is used. WARNINGS = YES # If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings # for undocumented members. If EXTRACT_ALL is set to YES then this flag will # automatically be disabled. WARN_IF_UNDOCUMENTED = YES # If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for # potential errors in the documentation, such as not documenting some # parameters in a documented function, or documenting parameters that # don't exist or using markup commands wrongly. WARN_IF_DOC_ERROR = YES # This WARN_NO_PARAMDOC option can be abled to get warnings for # functions that are documented, but have no documentation for their parameters # or return value. If set to NO (the default) doxygen will only warn about # wrong or incomplete parameter documentation, but not about the absence of # documentation. WARN_NO_PARAMDOC = NO # The WARN_FORMAT tag determines the format of the warning messages that # doxygen can produce. The string should contain the $file, $line, and $text # tags, which will be replaced by the file and line number from which the # warning originated and the warning text. Optionally the format may contain # $version, which will be replaced by the version of the file (if it could # be obtained via FILE_VERSION_FILTER) WARN_FORMAT = "$file:$line: $text" # The WARN_LOGFILE tag can be used to specify a file to which warning # and error messages should be written. If left blank the output is written # to stderr. WARN_LOGFILE = #--------------------------------------------------------------------------- # configuration options related to the input files #--------------------------------------------------------------------------- # The INPUT tag can be used to specify the files and/or directories that contain # documented source files. You may enter file names like "myfile.cpp" or # directories like "/usr/src/myproject". Separate the files or directories # with spaces. # Individual files are listed here to force a particular order in the # resulting documentation. # For the Reference the order is: system headers, avr/ headers, util/ headers, # compat/ headers, then demo projects. # For the User Manual, it is whatever chapter order seems sensible. INPUT = @top_srcdir@/include/alloca.h \ @top_srcdir@/include/assert.h \ @top_srcdir@/include/ctype.h \ @top_srcdir@/include/errno.h \ @top_srcdir@/include/inttypes.h \ @top_srcdir@/include/math.h \ @top_srcdir@/include/setjmp.h \ @top_srcdir@/include/stdint.h \ @top_srcdir@/include/stdio.h \ @top_srcdir@/include/stdlib.h \ @top_srcdir@/include/string.h \ @top_srcdir@/libc \ @top_srcdir@/include/avr/boot.h \ @top_srcdir@/include/avr/cpufunc.h \ @top_srcdir@/include/avr/eeprom.h \ @top_srcdir@/include/avr/fuse.h \ @top_srcdir@/include/avr/interrupt.h \ @top_srcdir@/doc/api/interrupts.dox \ @top_srcdir@/doc/api/vectortable.dox \ @top_srcdir@/include/avr/io.h \ @top_srcdir@/include/avr/lock.h \ @top_srcdir@/include/avr/pgmspace.h \ @top_srcdir@/include/avr/portpins.h \ @top_srcdir@/include/avr/power.h \ @top_srcdir@/include/avr/sfr_defs.h \ @top_srcdir@/doc/api/sfr.dox \ @top_srcdir@/include/avr/signal.h \ @top_srcdir@/include/avr/signature.h \ @top_srcdir@/include/avr/sleep.h \ @top_srcdir@/include/avr/version.h \ @top_srcdir@/include/avr/wdt.h \ @top_srcdir@/include/util \ @top_srcdir@/include/compat \ @top_srcdir@/doc/api/overview.dox \ @top_srcdir@/doc/api/malloc.dox \ @top_srcdir@/doc/api/sections.dox \ @top_srcdir@/doc/api/pgmspace.dox \ @top_srcdir@/doc/api/assembler.dox \ @top_srcdir@/doc/api/inline_asm.dox \ @top_srcdir@/doc/api/library.dox \ @top_srcdir@/doc/api/bench.dox \ @top_srcdir@/doc/api/bench-libc.dox \ @top_srcdir@/doc/api/bench-libm.dox \ @top_srcdir@/doc/api/porting.dox \ @top_srcdir@/doc/api/faq.dox \ @top_srcdir@/doc/api/tools-install.dox \ @top_srcdir@/doc/api/using-tools.dox \ @top_srcdir@/doc/api/optimize.dox \ @top_srcdir@/doc/api/using-avrprog.dox \ @top_srcdir@/doc/api/rel-method.dox \ @top_srcdir@/doc/api/acknowledge.dox \ @top_srcdir@/doc/api/main_page.dox \ @top_srcdir@/doc/examples \ @top_srcdir@/doc/examples/demo \ @top_srcdir@/doc/examples/largedemo \ @top_srcdir@/doc/examples/stdiodemo \ @top_srcdir@/doc/examples/twitest # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is # also the default input encoding. Doxygen uses libiconv (or the iconv built # into libc) for the transcoding. See http://www.gnu.org/software/libiconv for # the list of possible encodings. INPUT_ENCODING = iso-8859-1 # If the value of the INPUT tag contains directories, you can use the # FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp # and *.h) to filter out the source-files in the directories. If left # blank the following patterns are tested: # *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx # *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py FILE_PATTERNS = *.c \ *.h \ *.S \ *.dox # The RECURSIVE tag can be used to turn specify whether or not subdirectories # should be searched for input files as well. Possible values are YES and NO. # If left blank NO is used. RECURSIVE = YES # The EXCLUDE tag can be used to specify files and/or directories that should # excluded from the INPUT source files. This way you can easily exclude a # subdirectory from a directory tree whose root is specified with the INPUT tag. EXCLUDE = # The EXCLUDE_SYMLINKS tag can be used select whether or not files or # directories that are symbolic links (a Unix filesystem feature) are excluded # from the input. EXCLUDE_SYMLINKS = NO # If the value of the INPUT tag contains directories, you can use the # EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude # certain files from those directories. Note that the wildcards are matched # against the file with absolute path, so to exclude all test directories # for example use the pattern */test/* EXCLUDE_PATTERNS = *CVS* # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names # (namespaces, classes, functions, etc.) that should be excluded from the # output. The symbol name can be a fully qualified name, a word, or if the # wildcard * is used, a substring. Examples: ANamespace, AClass, # AClass::ANamespace, ANamespace::*Test EXCLUDE_SYMBOLS = # The EXAMPLE_PATH tag can be used to specify one or more files or # directories that contain example code fragments that are included (see # the \include command). EXAMPLE_PATH = \ @top_srcdir@/doc/examples/largedemo \ @top_srcdir@/doc/examples/stdiodemo \ @top_srcdir@/doc/examples/twitest \ @top_srcdir@/doc/examples/demo # If the value of the EXAMPLE_PATH tag contains directories, you can use the # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp # and *.h) to filter out the source-files in the directories. If left # blank all files are included. EXAMPLE_PATTERNS = # If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be # searched for input files to be used with the \include or \dontinclude # commands irrespective of the value of the RECURSIVE tag. # Possible values are YES and NO. If left blank NO is used. EXAMPLE_RECURSIVE = NO # The IMAGE_PATH tag can be used to specify one or more files or # directories that contain image that are included in the documentation (see # the \image command). IMAGE_PATH = @top_srcdir@/doc/examples/demo \ @top_srcdir@/doc/examples/largedemo \ @top_srcdir@/doc/examples/stdiodemo \ @top_srcdir@/doc/api \ @top_builddir@/doc/api # The INPUT_FILTER tag can be used to specify a program that doxygen should # invoke to filter for each input file. Doxygen will invoke the filter program # by executing (via popen()) the command , where # is the value of the INPUT_FILTER tag, and is the name of an # input file. Doxygen will then use the output that the filter program writes # to standard output. If FILTER_PATTERNS is specified, this tag will be # ignored. INPUT_FILTER = # The FILTER_PATTERNS tag can be used to specify filters on a per file pattern # basis. Doxygen will compare the file name with each pattern and apply the # filter if there is a match. The filters are a list of the form: # pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further # info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER # is applied to all files. FILTER_PATTERNS = # If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using # INPUT_FILTER) will be used to filter the input files when producing source # files to browse (i.e. when SOURCE_BROWSER is set to YES). FILTER_SOURCE_FILES = NO #--------------------------------------------------------------------------- # configuration options related to source browsing #--------------------------------------------------------------------------- # If the SOURCE_BROWSER tag is set to YES then a list of source files will # be generated. Documented entities will be cross-referenced with these sources. # Note: To get rid of all source code in the generated output, make sure also # VERBATIM_HEADERS is set to NO. SOURCE_BROWSER = NO # Setting the INLINE_SOURCES tag to YES will include the body # of functions and classes directly in the documentation. INLINE_SOURCES = NO # Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct # doxygen to hide any special comment blocks from generated source code # fragments. Normal C and C++ comments will always remain visible. STRIP_CODE_COMMENTS = NO # If the REFERENCED_BY_RELATION tag is set to YES # then for each documented function all documented # functions referencing it will be listed. REFERENCED_BY_RELATION = NO # If the REFERENCES_RELATION tag is set to YES # then for each documented function all documented entities # called/used by that function will be listed. REFERENCES_RELATION = NO # If the REFERENCES_LINK_SOURCE tag is set to YES (the default) # and SOURCE_BROWSER tag is set to YES, then the hyperlinks from # functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will # link to the source code. Otherwise they will link to the documentstion. REFERENCES_LINK_SOURCE = YES # If the USE_HTAGS tag is set to YES then the references to source code # will point to the HTML generated by the htags(1) tool instead of doxygen # built-in source browser. The htags tool is part of GNU's global source # tagging system (see http://www.gnu.org/software/global/global.html). You # will need version 4.8.6 or higher. USE_HTAGS = NO # If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen # will generate a verbatim copy of the header file for each class for # which an include is specified. Set to NO to disable this. VERBATIM_HEADERS = YES #--------------------------------------------------------------------------- # configuration options related to the alphabetical class index #--------------------------------------------------------------------------- # If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then # the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns # in which this list will be split (can be a number in the range [1..20]) COLS_IN_ALPHA_INDEX = 4 # In case all classes in a project start with a common prefix, all # classes will be put under the same header in the alphabetical index. # The IGNORE_PREFIX tag can be used to specify one or more prefixes that # should be ignored while generating the index headers. IGNORE_PREFIX = #--------------------------------------------------------------------------- # configuration options related to the HTML output #--------------------------------------------------------------------------- # If the GENERATE_HTML tag is set to YES (the default) Doxygen will # generate HTML output. GENERATE_HTML = YES # The HTML_OUTPUT tag is used to specify where the HTML docs will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `html' will be used as the default path. HTML_OUTPUT = @AVR_LIBC_USER_MANUAL@ # The HTML_FILE_EXTENSION tag can be used to specify the file extension for # each generated HTML page (for example: .htm,.php,.asp). If it is left blank # doxygen will generate files with .html extension. HTML_FILE_EXTENSION = .html # The HTML_HEADER tag can be used to specify a personal HTML header for # each generated HTML page. If it is left blank doxygen will generate a # standard header. HTML_HEADER = @srcdir@/dox_html_header # The HTML_FOOTER tag can be used to specify a personal HTML footer for # each generated HTML page. If it is left blank doxygen will generate a # standard footer. HTML_FOOTER = @srcdir@/dox_html_footer # The HTML_STYLESHEET tag can be used to specify a user-defined cascading # style sheet that is used by each HTML page. It can be used to # fine-tune the look of the HTML output. If the tag is left blank doxygen # will generate a default style sheet. Note that doxygen will try to copy # the style sheet file to the HTML output directory, so don't put your own # stylesheet in the HTML output directory as well, or it will be erased! HTML_STYLESHEET = @srcdir@/dox.css # If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, # files or namespaces will be aligned in HTML using tables. If set to # NO a bullet list will be used. HTML_ALIGN_MEMBERS = YES # If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML # documentation will contain sections that can be hidden and shown after the # page has loaded. For this to work a browser that supports # JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox # Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). HTML_DYNAMIC_SECTIONS = NO # If the GENERATE_DOCSET tag is set to YES, additional index files # will be generated that can be used as input for Apple's Xcode 3 # integrated development environment, introduced with OSX 10.5 (Leopard). # To create a documentation set, doxygen will generate a Makefile in the # HTML output directory. Running make will produce the docset in that # directory and running "make install" will install the docset in # ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find # it at startup. # See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html for more information. GENERATE_DOCSET = NO # When GENERATE_DOCSET tag is set to YES, this tag determines the name of the # feed. A documentation feed provides an umbrella under which multiple # documentation sets from a single provider (such as a company or product suite) # can be grouped. DOCSET_FEEDNAME = "Doxygen generated docs" # When GENERATE_DOCSET tag is set to YES, this tag specifies a string that # should uniquely identify the documentation set bundle. This should be a # reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen # will append .docset to the name. DOCSET_BUNDLE_ID = org.doxygen.Project # If the GENERATE_HTMLHELP tag is set to YES, additional index files # will be generated that can be used as input for tools like the # Microsoft HTML help workshop to generate a compiled HTML help file (.chm) # of the generated HTML documentation. GENERATE_HTMLHELP = NO # If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can # be used to specify the file name of the resulting .chm file. You # can add a path in front of the file if the result should not be # written to the html output directory. CHM_FILE = # If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can # be used to specify the location (absolute path including file name) of # the HTML help compiler (hhc.exe). If non-empty doxygen will try to run # the HTML help compiler on the generated index.hhp. HHC_LOCATION = # If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag # controls if a separate .chi index file is generated (YES) or that # it should be included in the master .chm file (NO). GENERATE_CHI = NO # If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING # is used to encode HtmlHelp index (hhk), content (hhc) and project file # content. CHM_INDEX_ENCODING = # If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag # controls whether a binary table of contents is generated (YES) or a # normal table of contents (NO) in the .chm file. BINARY_TOC = NO # The TOC_EXPAND flag can be set to YES to add extra items for group members # to the contents of the HTML help documentation and to the tree view. TOC_EXPAND = NO # If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and QHP_VIRTUAL_FOLDER # are set, an additional index file will be generated that can be used as input for # Qt's qhelpgenerator to generate a Qt Compressed Help (.qch) of the generated # HTML documentation. GENERATE_QHP = NO # If the QHG_LOCATION tag is specified, the QCH_FILE tag can # be used to specify the file name of the resulting .qch file. # The path specified is relative to the HTML output folder. QCH_FILE = # The QHP_NAMESPACE tag specifies the namespace to use when generating # Qt Help Project output. For more information please see # Qt Help Project / Namespace. QHP_NAMESPACE = org.doxygen.Project # The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating # Qt Help Project output. For more information please see # Qt Help Project / Virtual Folders. QHP_VIRTUAL_FOLDER = doc # If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can # be used to specify the location of Qt's qhelpgenerator. # If non-empty doxygen will try to run qhelpgenerator on the generated # .qhp file . QHG_LOCATION = # The DISABLE_INDEX tag can be used to turn on/off the condensed index at # top of each HTML page. The value NO (the default) enables the index and # the value YES disables it. DISABLE_INDEX = YES # This tag can be used to set the number of enum values (range [1..20]) # that doxygen will group on one line in the generated HTML documentation. ENUM_VALUES_PER_LINE = 4 # The GENERATE_TREEVIEW tag is used to specify whether a tree-like index # structure should be generated to display hierarchical information. # If the tag value is set to FRAME, a side panel will be generated # containing a tree-like index structure (just like the one that # is generated for HTML Help). For this to work a browser that supports # JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, # Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are # probably better off using the HTML help feature. Other possible values # for this tag are: HIERARCHIES, which will generate the Groups, Directories, # and Class Hierarchy pages using a tree view instead of an ordered list; # ALL, which combines the behavior of FRAME and HIERARCHIES; and NONE, which # disables this behavior completely. For backwards compatibility with previous # releases of Doxygen, the values YES and NO are equivalent to FRAME and NONE # respectively. GENERATE_TREEVIEW = NONE # If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be # used to set the initial width (in pixels) of the frame in which the tree # is shown. TREEVIEW_WIDTH = 250 # Use this tag to change the font size of Latex formulas included # as images in the HTML documentation. The default is 10. Note that # when you change the font size after a successful doxygen run you need # to manually remove any form_*.png images from the HTML output directory # to force them to be regenerated. FORMULA_FONTSIZE = 10 #--------------------------------------------------------------------------- # configuration options related to the LaTeX output #--------------------------------------------------------------------------- # If the GENERATE_LATEX tag is set to YES (the default) Doxygen will # generate Latex output. GENERATE_LATEX = YES # The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `latex' will be used as the default path. LATEX_OUTPUT = latex_src # The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be # invoked. If left blank `latex' will be used as the default command name. LATEX_CMD_NAME = latex # The MAKEINDEX_CMD_NAME tag can be used to specify the command name to # generate index for LaTeX. If left blank `makeindex' will be used as the # default command name. MAKEINDEX_CMD_NAME = makeindex # If the COMPACT_LATEX tag is set to YES Doxygen generates more compact # LaTeX documents. This may be useful for small projects and may help to # save some trees in general. COMPACT_LATEX = YES # The PAPER_TYPE tag can be used to set the paper type that is used # by the printer. Possible values are: a4, a4wide, letter, legal and # executive. If left blank a4wide will be used. PAPER_TYPE = letter # The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX # packages that should be included in the LaTeX output. EXTRA_PACKAGES = # The LATEX_HEADER tag can be used to specify a personal LaTeX header for # the generated latex document. The header should contain everything until # the first chapter. If it is left blank doxygen will generate a # standard header. Notice: only use this tag if you know what you are doing! LATEX_HEADER = # If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated # is prepared for conversion to pdf (using ps2pdf). The pdf file will # contain links (just like the HTML output) instead of page references # This makes the output suitable for online browsing using a pdf viewer. PDF_HYPERLINKS = YES # If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of # plain latex in the generated Makefile. Set this option to YES to get a # higher quality PDF documentation. USE_PDFLATEX = YES # If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. # command to the generated LaTeX files. This will instruct LaTeX to keep # running if errors occur, instead of asking the user for help. # This option is also used when generating formulas in HTML. LATEX_BATCHMODE = YES # If LATEX_HIDE_INDICES is set to YES then doxygen will not # include the index chapters (such as File Index, Compound Index, etc.) # in the output. LATEX_HIDE_INDICES = NO #--------------------------------------------------------------------------- # configuration options related to the RTF output #--------------------------------------------------------------------------- # If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output # The RTF output is optimized for Word 97 and may not look very pretty with # other RTF readers or editors. GENERATE_RTF = NO # The RTF_OUTPUT tag is used to specify where the RTF docs will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `rtf' will be used as the default path. RTF_OUTPUT = rtf # If the COMPACT_RTF tag is set to YES Doxygen generates more compact # RTF documents. This may be useful for small projects and may help to # save some trees in general. COMPACT_RTF = NO # If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated # will contain hyperlink fields. The RTF file will # contain links (just like the HTML output) instead of page references. # This makes the output suitable for online browsing using WORD or other # programs which support those fields. # Note: wordpad (write) and others do not support links. RTF_HYPERLINKS = NO # Load stylesheet definitions from file. Syntax is similar to doxygen's # config file, i.e. a series of assignments. You only have to provide # replacements, missing definitions are set to their default value. RTF_STYLESHEET_FILE = # Set optional variables used in the generation of an rtf document. # Syntax is similar to doxygen's config file. RTF_EXTENSIONS_FILE = #--------------------------------------------------------------------------- # configuration options related to the man page output #--------------------------------------------------------------------------- # If the GENERATE_MAN tag is set to YES (the default) Doxygen will # generate man pages GENERATE_MAN = YES # The MAN_OUTPUT tag is used to specify where the man pages will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `man' will be used as the default path. MAN_OUTPUT = man # The MAN_EXTENSION tag determines the extension that is added to # the generated man pages (default is the subroutine's section .3) MAN_EXTENSION = .3 # If the MAN_LINKS tag is set to YES and Doxygen generates man output, # then it will generate one additional man file for each entity # documented in the real man page(s). These additional files # only source the real man page, but without them the man command # would be unable to find the correct page. The default is NO. MAN_LINKS = YES #--------------------------------------------------------------------------- # configuration options related to the XML output #--------------------------------------------------------------------------- # If the GENERATE_XML tag is set to YES Doxygen will # generate an XML file that captures the structure of # the code including all documentation. GENERATE_XML = NO # The XML_OUTPUT tag is used to specify where the XML pages will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `xml' will be used as the default path. XML_OUTPUT = xml # The XML_SCHEMA tag can be used to specify an XML schema, # which can be used by a validating XML parser to check the # syntax of the XML files. XML_SCHEMA = # The XML_DTD tag can be used to specify an XML DTD, # which can be used by a validating XML parser to check the # syntax of the XML files. XML_DTD = # If the XML_PROGRAMLISTING tag is set to YES Doxygen will # dump the program listings (including syntax highlighting # and cross-referencing information) to the XML output. Note that # enabling this will significantly increase the size of the XML output. XML_PROGRAMLISTING = YES #--------------------------------------------------------------------------- # configuration options for the AutoGen Definitions output #--------------------------------------------------------------------------- # If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will # generate an AutoGen Definitions (see autogen.sf.net) file # that captures the structure of the code including all # documentation. Note that this feature is still experimental # and incomplete at the moment. GENERATE_AUTOGEN_DEF = NO #--------------------------------------------------------------------------- # configuration options related to the Perl module output #--------------------------------------------------------------------------- # If the GENERATE_PERLMOD tag is set to YES Doxygen will # generate a Perl module file that captures the structure of # the code including all documentation. Note that this # feature is still experimental and incomplete at the # moment. GENERATE_PERLMOD = NO # If the PERLMOD_LATEX tag is set to YES Doxygen will generate # the necessary Makefile rules, Perl scripts and LaTeX code to be able # to generate PDF and DVI output from the Perl module output. PERLMOD_LATEX = NO # If the PERLMOD_PRETTY tag is set to YES the Perl module output will be # nicely formatted so it can be parsed by a human reader. This is useful # if you want to understand what is going on. On the other hand, if this # tag is set to NO the size of the Perl module output will be much smaller # and Perl will parse it just the same. PERLMOD_PRETTY = YES # The names of the make variables in the generated doxyrules.make file # are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. # This is useful so different doxyrules.make files included by the same # Makefile don't overwrite each other's variables. PERLMOD_MAKEVAR_PREFIX = #--------------------------------------------------------------------------- # Configuration options related to the preprocessor #--------------------------------------------------------------------------- # If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will # evaluate all C-preprocessor directives found in the sources and include # files. ENABLE_PREPROCESSING = YES # If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro # names in the source code. If set to NO (the default) only conditional # compilation will be performed. Macro expansion can be done in a controlled # way by setting EXPAND_ONLY_PREDEF to YES. MACRO_EXPANSION = YES # If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES # then the macro expansion is limited to the macros specified with the # PREDEFINED and EXPAND_AS_DEFINED tags. EXPAND_ONLY_PREDEF = YES # If the SEARCH_INCLUDES tag is set to YES (the default) the includes files # in the INCLUDE_PATH (see below) will be search if a #include is found. SEARCH_INCLUDES = YES # The INCLUDE_PATH tag can be used to specify one or more directories that # contain include files that are not input files but should be processed by # the preprocessor. INCLUDE_PATH = # You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard # patterns (like *.h and *.hpp) to filter out the header-files in the # directories. If left blank, the patterns specified with FILE_PATTERNS will # be used. INCLUDE_FILE_PATTERNS = # The PREDEFINED tag can be used to specify one or more macro names that # are defined before the preprocessor is started (similar to the -D option of # gcc). The argument of the tag is a list of macros of the form: name # or name=definition (no spaces). If the definition and the = are # omitted =1 is assumed. To prevent a macro definition from being # undefined via #undef or recursively expanded use the := operator # instead of the = operator. PREDEFINED = __DOXYGEN__ \ __ATTR_CONST__= \ ATTRIBUTE_CLIB_SECTION= # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then # this tag can be used to specify a list of macro names that should be expanded. # The macro definition that is found in the sources will be used. # Use the PREDEFINED tag if you want to use a different macro definition. EXPAND_AS_DEFINED = # If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then # doxygen's preprocessor will remove all function-like macros that are alone # on a line, have an all uppercase name, and do not end with a semicolon. Such # function macros are typically used for boiler-plate code, and will confuse # the parser if not removed. SKIP_FUNCTION_MACROS = YES #--------------------------------------------------------------------------- # Configuration::additions related to external references #--------------------------------------------------------------------------- # The TAGFILES option can be used to specify one or more tagfiles. # Optionally an initial location of the external documentation # can be added for each tagfile. The format of a tag file without # this location is as follows: # TAGFILES = file1 file2 ... # Adding location for the tag files is done as follows: # TAGFILES = file1=loc1 "file2 = loc2" ... # where "loc1" and "loc2" can be relative or absolute paths or # URLs. If a location is present for each tag, the installdox tool # does not have to be run to correct the links. # Note that each tag file must have a unique name # (where the name does NOT include the path) # If a tag file is not located in the directory in which doxygen # is run, you must also specify the path to the tagfile here. TAGFILES = # When a file name is specified after GENERATE_TAGFILE, doxygen will create # a tag file that is based on the input files it reads. GENERATE_TAGFILE = # If the ALLEXTERNALS tag is set to YES all external classes will be listed # in the class index. If set to NO only the inherited external classes # will be listed. ALLEXTERNALS = NO # If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed # in the modules index. If set to NO, only the current project's groups will # be listed. EXTERNAL_GROUPS = YES # The PERL_PATH should be the absolute path and name of the perl script # interpreter (i.e. the result of `which perl'). PERL_PATH = /usr/bin/perl #--------------------------------------------------------------------------- # Configuration options related to the dot tool #--------------------------------------------------------------------------- # If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will # generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base # or super classes. Setting the tag to NO turns the diagrams off. Note that # this option is superseded by the HAVE_DOT option below. This is only a # fallback. It is recommended to install and use dot, since it yields more # powerful graphs. CLASS_DIAGRAMS = YES # You can define message sequence charts within doxygen comments using the \msc # command. Doxygen will then run the mscgen tool (see # http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the # documentation. The MSCGEN_PATH tag allows you to specify the directory where # the mscgen tool resides. If left empty the tool is assumed to be found in the # default search path. MSCGEN_PATH = # If set to YES, the inheritance and collaboration graphs will hide # inheritance and usage relations if the target is undocumented # or is not a class. HIDE_UNDOC_RELATIONS = YES # If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is # available from the path. This tool is part of Graphviz, a graph visualization # toolkit from AT&T and Lucent Bell Labs. The other options in this section # have no effect if this option is set to NO (the default) HAVE_DOT = NO # By default doxygen will write a font called FreeSans.ttf to the output # directory and reference it in all dot files that doxygen generates. This # font does not include all possible unicode characters however, so when you need # these (or just want a differently looking font) you can specify the font name # using DOT_FONTNAME. You need need to make sure dot is able to find the font, # which can be done by putting it in a standard location or by setting the # DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory # containing the font. DOT_FONTNAME = FreeSans # By default doxygen will tell dot to use the output directory to look for the # FreeSans.ttf font (which doxygen will put there itself). If you specify a # different font using DOT_FONTNAME you can set the path where dot # can find it using this tag. DOT_FONTPATH = # If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen # will generate a graph for each documented class showing the direct and # indirect inheritance relations. Setting this tag to YES will force the # the CLASS_DIAGRAMS tag to NO. CLASS_GRAPH = YES # If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen # will generate a graph for each documented class showing the direct and # indirect implementation dependencies (inheritance, containment, and # class references variables) of the class with other documented classes. COLLABORATION_GRAPH = YES # If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen # will generate a graph for groups, showing the direct groups dependencies GROUP_GRAPHS = YES # If the UML_LOOK tag is set to YES doxygen will generate inheritance and # collaboration diagrams in a style similar to the OMG's Unified Modeling # Language. UML_LOOK = NO # If set to YES, the inheritance and collaboration graphs will show the # relations between templates and their instances. TEMPLATE_RELATIONS = NO # If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT # tags are set to YES then doxygen will generate a graph for each documented # file showing the direct and indirect include dependencies of the file with # other documented files. INCLUDE_GRAPH = YES # If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and # HAVE_DOT tags are set to YES then doxygen will generate a graph for each # documented header file showing the documented files that directly or # indirectly include this file. INCLUDED_BY_GRAPH = YES # If the CALL_GRAPH and HAVE_DOT options are set to YES then # doxygen will generate a call dependency graph for every global function # or class method. Note that enabling this option will significantly increase # the time of a run. So in most cases it will be better to enable call graphs # for selected functions only using the \callgraph command. CALL_GRAPH = NO # If the CALLER_GRAPH and HAVE_DOT tags are set to YES then # doxygen will generate a caller dependency graph for every global function # or class method. Note that enabling this option will significantly increase # the time of a run. So in most cases it will be better to enable caller # graphs for selected functions only using the \callergraph command. CALLER_GRAPH = NO # If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen # will graphical hierarchy of all classes instead of a textual one. GRAPHICAL_HIERARCHY = YES # If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES # then doxygen will show the dependencies a directory has on other directories # in a graphical way. The dependency relations are determined by the #include # relations between the files in the directories. DIRECTORY_GRAPH = YES # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images # generated by dot. Possible values are png, jpg, or gif # If left blank png will be used. DOT_IMAGE_FORMAT = png # The tag DOT_PATH can be used to specify the path where the dot tool can be # found. If left blank, it is assumed the dot tool can be found in the path. DOT_PATH = # The DOTFILE_DIRS tag can be used to specify one or more directories that # contain dot files that are included in the documentation (see the # \dotfile command). DOTFILE_DIRS = # The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of # nodes that will be shown in the graph. If the number of nodes in a graph # becomes larger than this value, doxygen will truncate the graph, which is # visualized by representing a node as a red box. Note that doxygen if the # number of direct children of the root node in a graph is already larger than # DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note # that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. DOT_GRAPH_MAX_NODES = 50 # The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the # graphs generated by dot. A depth value of 3 means that only nodes reachable # from the root by following a path via at most 3 edges will be shown. Nodes # that lay further from the root node will be omitted. Note that setting this # option to 1 or 2 may greatly reduce the computation time needed for large # code bases. Also note that the size of a graph can be further restricted by # DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. MAX_DOT_GRAPH_DEPTH = 0 # Set the DOT_TRANSPARENT tag to YES to generate images with a transparent # background. This is disabled by default, because dot on Windows does not # seem to support this out of the box. Warning: Depending on the platform used, # enabling this option may lead to badly anti-aliased labels on the edges of # a graph (i.e. they become hard to read). DOT_TRANSPARENT = NO # Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output # files in one run (i.e. multiple -o and -T options on the command line). This # makes dot run faster, but since only newer versions of dot (>1.8.10) # support this, this feature is disabled by default. DOT_MULTI_TARGETS = NO # If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will # generate a legend page explaining the meaning of the various boxes and # arrows in the dot generated graphs. GENERATE_LEGEND = YES # If the DOT_CLEANUP tag is set to YES (the default) Doxygen will # remove the intermediate dot files that are used to generate # the various graphs. DOT_CLEANUP = YES #--------------------------------------------------------------------------- # Configuration::additions related to the search engine #--------------------------------------------------------------------------- # The SEARCHENGINE tag specifies whether or not a search engine should be # used. If set to NO the values of all tags below this one will be ignored. SEARCHENGINE = NO avr-libc-1.8.0.orig/doc/api/dox_html_header0000644000000000000000000000215511732702554015444 0ustar $title
AVR Libc Home Page AVRs AVR Libc Development Pages
Main Page User Manual Library Reference FAQ Alphabetical Index Example Projects
avr-libc-1.8.0.orig/doc/api/tools-install.dox0000644000000000000000000006531111732702554015716 0ustar /* Copyright (c) 2002,2005, Theodore Roth Copyright (c) 2006, Joerg Wunsch Copyright (c) 2007, 2010 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: tools-install.dox 2221 2011-02-22 21:30:28Z arcanum $ */ /** \page install_tools Building and Installing the GNU Tool Chain \addindex installation This chapter shows how to build and install, from source code, a complete development environment for the AVR processors using the GNU toolset. There are two main sections, one for Linux, FreeBSD, and other Unix-like operating systems, and another section for Windows. \section install_unix Building and Installing under Linux, FreeBSD, and Others The default behaviour for most of these tools is to install every thing under the \c /usr/local directory. In order to keep the AVR tools separate from the base system, it is usually better to install everything into /usr/local/avr. If the \c /usr/local/avr directory does not exist, you should create it before trying to install anything. You will need root access to install there. If you don't have root access to the system, you can alternatively install in your home directory, for example, in $HOME/local/avr. Where you install is a completely arbitrary decision, but should be consistent for all the tools. You specify the installation directory by using the --prefix=dir option with the \c configure script. It is important to install all the AVR tools in the same directory or some of the tools will not work correctly. To ensure consistency and simplify the discussion, we will use \c $PREFIX to refer to whatever directory you wish to install in. You can set this as an environment variable if you wish as such (using a Bourne-like shell): \addindex $PREFIX \addindex --prefix \verbatim $ PREFIX=$HOME/local/avr $ export PREFIX \endverbatim \addindex $PATH \anchor path \note Be sure that you have your \c PATH environment variable set to search the directory you install everything in \e before you start installing anything. For example, if you use --prefix=$PREFIX, you must have \c $PREFIX/bin in your exported PATH. As such: \verbatim $ PATH=$PATH:$PREFIX/bin $ export PATH \endverbatim \warning If you have \c CC set to anything other than \c avr-gcc in your environment, this will cause the configure script to fail. It is best to not have \c CC set at all. \note It is usually the best to use the latest released version of each of the tools. \section required_tools Required Tools \addindex tools, required - GNU Binutils
http://sources.redhat.com/binutils/
\ref install_avr_binutils "Installation" - GCC
http://gcc.gnu.org/
\ref install_avr_gcc "Installation" - AVR LibC
http://savannah.gnu.org/projects/avr-libc/
\ref install_avr_libc "Installation"
\section optional_tools Optional Tools \addindex tools, optional You can develop programs for AVR devices without the following tools. They may or may not be of use for you. - AVRDUDE
http://savannah.nongnu.org/projects/avrdude/
\ref install_avrprog "Installation"
\ref using_avrprog "Usage Notes" - GDB
http://sources.redhat.com/gdb/
\ref install_gdb "Installation"
- SimulAVR
http://savannah.gnu.org/projects/simulavr/
\ref install_simulavr "Installation" - AVaRICE
http://avarice.sourceforge.net/
\ref install_avarice "Installation"
\section install_avr_binutils GNU Binutils for the AVR target \addindex installation, binutils The binutils package provides all the low-level utilities needed in building and manipulating object files. Once installed, your environment will have an AVR assembler (avr-as), linker (avr-ld), and librarian (avr-ar and avr-ranlib). In addition, you get tools which extract data from object files (avr-objcopy), dissassemble object file information (avr-objdump), and strip information from object files (avr-strip). Before we can build the C compiler, these tools need to be in place. Download and unpack the source files: \verbatim $ bunzip2 -c binutils-.tar.bz2 | tar xf - $ cd binutils- \endverbatim \note Replace \c <version> with the version of the package you downloaded. \note If you obtained a gzip compressed file (.gz), use gunzip instead of bunzip2. It is usually a good idea to configure and build binutils in a subdirectory so as not to pollute the source with the compiled files. This is recommended by the binutils developers. \verbatim $ mkdir obj-avr $ cd obj-avr \endverbatim The next step is to configure and build the tools. This is done by supplying arguments to the configure script that enable the AVR-specific options. \verbatim $ ../configure --prefix=$PREFIX --target=avr --disable-nls \endverbatim If you don't specify the --prefix option, the tools will get installed in the \c /usr/local hierarchy (i.e. the binaries will get installed in /usr/local/bin, the info pages get installed in /usr/local/info, etc.) Since these tools are changing frequently, It is preferrable to put them in a location that is easily removed. When configure is run, it generates a lot of messages while it determines what is available on your operating system. When it finishes, it will have created several Makefiles that are custom tailored to your platform. At this point, you can build the project. \verbatim $ make \endverbatim \note BSD users should note that the project's Makefile uses GNU make syntax. This means FreeBSD users may need to build the tools by using gmake. If the tools compiled cleanly, you're ready to install them. If you specified a destination that isn't owned by your account, you'll need root access to install them. To install: \verbatim $ make install \endverbatim You should now have the programs from binutils installed into $PREFIX/bin. Don't forget to \ref path "set your PATH" environment variable before going to build avr-gcc. \note The official version of binutils might lack support for recent AVR devices. A patch that adds more AVR types can be found at http://www.freebsd.org/cgi/cvsweb.cgi/ports/devel/avr-binutils/files/patch-newdevices \section install_avr_gcc GCC for the AVR target \addindex installation, gcc \warning You must install \ref install_avr_binutils "avr-binutils" and make sure your \ref path "path is set" properly before installing avr-gcc. The steps to build \c avr-gcc are essentially same as for \ref install_avr_binutils "binutils": \verbatim $ bunzip2 -c gcc-.tar.bz2 | tar xf - $ cd gcc- $ mkdir obj-avr $ cd obj-avr $ ../configure --prefix=$PREFIX --target=avr --enable-languages=c,c++ \ --disable-nls --disable-libssp --with-dwarf2 $ make $ make install \endverbatim To save your self some download time, you can alternatively download only the gcc-core-\.tar.bz2 and gcc-c++-\.tar.bz2 parts of the gcc. Also, if you don't need C++ support, you only need the core part and should only enable the C language support. \note Early versions of these tools did not support C++. \note The stdc++ libs are not included with C++ for AVR due to the size limitations of the devices. \note The official version of GCC might lack support for recent AVR devices. A patch that adds more AVR types can be found at http://www.freebsd.org/cgi/cvsweb.cgi/ports/devel/avr-gcc/files/patch-newdevices \section install_avr_libc AVR LibC \addindex installation, avr-libc \warning You must install \ref install_avr_binutils "avr-binutils", \ref install_avr_gcc "avr-gcc" and make sure your \ref path "path is set" properly before installing avr-libc. \note If you have obtained the latest avr-libc from cvs, you will have to run the \c bootstrap script before using either of the build methods described below. To build and install avr-libc: \verbatim $ gunzip -c avr-libc-.tar.gz | tar xf - $ cd avr-libc- $ ./configure --prefix=$PREFIX --build=`./config.guess` --host=avr $ make $ make install \endverbatim \section install_avrprog AVRDUDE \addindex installation, avrprog \addindex installation, avrdude \note It has been ported to windows (via MinGW or cygwin), Linux and Solaris. Other Unix systems should be trivial to port to. avrdude is part of the FreeBSD ports system. To install it, simply do the following: \verbatim # cd /usr/ports/devel/avrdude # make install \endverbatim \note Installation into the default location usually requires root permissions. However, running the program only requires access permissions to the appropriate \c ppi(4) device. Building and installing on other systems should use the \c configure system, as such: \verbatim $ gunzip -c avrdude-.tar.gz | tar xf - $ cd avrdude- $ mkdir obj-avr $ cd obj-avr $ ../configure --prefix=$PREFIX $ make $ make install \endverbatim \section install_gdb GDB for the AVR target \addindex Installation, gdb GDB also uses the \c configure system, so to build and install: \verbatim $ bunzip2 -c gdb-.tar.bz2 | tar xf - $ cd gdb- $ mkdir obj-avr $ cd obj-avr $ ../configure --prefix=$PREFIX --target=avr $ make $ make install \endverbatim \note If you are planning on using avr-gdb, you will probably want to install either \ref install_simulavr "simulavr" or \ref install_avarice "avarice" since avr-gdb needs one of these to run as a a remote target backend. \section install_simulavr SimulAVR \addindex installation, simulavr SimulAVR also uses the \c configure system, so to build and install: \verbatim $ gunzip -c simulavr-.tar.gz | tar xf - $ cd simulavr- $ mkdir obj-avr $ cd obj-avr $ ../configure --prefix=$PREFIX $ make $ make install \endverbatim \note You might want to have already installed \ref install_avr_binutils "avr-binutils", \ref install_avr_gcc "avr-gcc" and \ref install_avr_libc "avr-libc" if you want to have the test programs built in the simulavr source. \section install_avarice AVaRICE \addindex installation, avarice \note These install notes are not applicable to avarice-1.5 or older. You probably don't want to use anything that old anyways since there have been many improvements and bug fixes since the 1.5 release. AVaRICE also uses the \c configure system, so to build and install: \verbatim $ gunzip -c avarice-.tar.gz | tar xf - $ cd avarice- $ mkdir obj-avr $ cd obj-avr $ ../configure --prefix=$PREFIX $ make $ make install \endverbatim \note AVaRICE uses the BFD library for accessing various binary file formats. You may need to tell the configure script where to find the lib and headers for the link to work. This is usually done by invoking the configure script like this (Replace \ with the path to the \c bfd.h file on your system. Replace \ with the path to \c libbfd.a on your system.): \verbatim $ CPPFLAGS=-I LDFLAGS=-L ../configure --prefix=$PREFIX \endverbatim \section install_windows Building and Installing under Windows Building and installing the toolchain under Windows requires more effort because all of the tools required for building, and the programs themselves, are mainly designed for running under a POSIX environment such as Unix and Linux. Windows does not natively provide such an environment. There are two projects available that provide such an environment, Cygwin and MinGW. There are advantages and disadvantages to both. Cygwin provides a very complete POSIX environment that allows one to build many Linux based tools from source with very little or no source modifications. However, POSIX functionality is provided in the form of a DLL that is linked to the application. This DLL has to be redistributed with your application and there are issues if the Cygwin DLL already exists on the installation system and different versions of the DLL. On the other hand, MinGW can compile code as native Win32 applications. However, this means that programs designed for Unix and Linux (i.e. that use POSIX functionality) will not compile as MinGW does not provide that POSIX layer for you. Therefore most programs that compile on both types of host systems, usually must provide some sort of abstraction layer to allow an application to be built cross-platform. MinGW does provide somewhat of a POSIX environment, called MSYS, that allows you to build Unix and Linux applications as they woud normally do, with a \c configure step and a \c make step. Cygwin also provides such an environment. This means that building the AVR toolchain is very similar to how it is built in Linux, described above. The main differences are in what the PATH environment variable gets set to, pathname differences, and the tools that are required to build the projects under Windows. We'll take a look at the tools next. \section install_windows_tools Tools Required for Building the Toolchain for Windows These are the tools that are currently used to build an AVR tool chain. This list may change, either the version of the tools, or the tools themselves, as improvements are made. - MinGW
Download the MinGW Automated Installer, 20100909 (or later) - Run mingw-get-inst-20100909.exe - In the installation wizard, keep the default values and press the "Next" button for all installer pages except for the pages explicitly listed below. - In the installer page "Repository Catalogues", select the "Download latest repository catalogues" radio button, and press the "Next" button - In the installer page "License Agreement", select the "I accept the agreement" radio button, and press the "Next" button - In the installer page "Select Components", be sure to select these items: - C compiler (default checked) - C++ compiler - Ada compiler - MinGW Developer Toolkit (which includes "MSYS Basic System"). - Install. - Install Cygwin
- Install everything, all users, UNIX line endings. This will take a *long* time. A fat internet pipe is highly recommended. It is also recommended that you download all to a directory first, and then install from that directory to your machine. \note GMP, MPFR, and MPC are required to build GCC. \note GMP is a prequisite for building MPFR. Build GMP first. \note MPFR is a prerequisite for building MPC. Build MPFR second. - Build GMP for MinGW
- Latest Version - - Build script: \verbatim ./configure 2>&1 | tee gmp-configure.log make 2>&1 | tee gmp-make.log make check 2>&1 | tee gmp-make-check.log make install 2>&1 | tee gmp-make-install.log \endverbatim - GMP headers will be installed under /usr/local/include and library installed under /usr/local/lib. - Build MPFR for MinGW
- Latest Version - - Build script: \verbatim ./configure --with-gmp=/usr/local --disable-shared 2>&1 | tee mpfr-configure.log make 2>&1 | tee mpfr-make.log make check 2>&1 | tee mpfr-make-check.log make install 2>&1 | tee mpfr-make-install.log \endverbatim - MPFR headers will be installed under /usr/local/include and library installed under /usr/local/lib. - Build MPC for MinGW
- Latest Version - - Build script: \verbatim ./configure --with-gmp=/usr/local --with-mpfr=/usr/local --disable-shared 2>&1 | tee mpfr-configure.log make 2>&1 | tee mpfr-make.log make check 2>&1 | tee mpfr-make-check.log make install 2>&1 | tee mpfr-make-install.log \endverbatim - MPFR headers will be installed under /usr/local/include and library installed under /usr/local/lib. \note Doxygen is required to build AVR-LibC documentation. - Install Doxygen
- Version 1.7.2 - - Download and install. \note NetPBM is required to build graphics in the AVR-LibC documentation. - Install NetPBM
- Version 10.27.0 - From the GNUWin32 project: - Download and install. \note fig2dev is required to build graphics in the AVR-LibC documentation. - Install fig2dev
- Version 3.2 patchlevel 5c - From WinFig 4.62: - Download the zip file version of WinFig - Unzip the download file and install fig2dev.exe in a location of your choice, somewhere in the PATH. - You may have to unzip and install related DLL files for fig2dev. In the version above, you have to install QtCore4.dll and QtGui4.dll. \note MikTeX is required to build various documentation. - Install MiKTeX
- Version 2.9 - - Download and install. \note Ghostscript is required to build various documentation. - Install Ghostscript
- Version 9.00 - - Download and install. - In the \\bin subdirectory of the installaion, copy gswin32c.exe to gs.exe. - Set the TEMP and TMP environment variables to c:\\temp or to the short filename version. This helps to avoid NTVDM errors during building. \section install_windows_building Building the Toolchain for Windows All directories in the PATH enviornment variable should be specified using their short filename (8.3) version. This will also help to avoid NTVDM errors during building. These short filenames can be specific to each machine. Build the tools below in MinGW/MSYS. - Binutils
- Open source code pacakge and patch as necessary. - Configure and build in a directory outside of the source code tree. - Set PATH, in order: - \ - \ - /usr/local/bin - /usr/bin - /bin - /mingw/bin - c:/cygwin/bin - \/bin - Configure \verbatim CFLAGS=-D__USE_MINGW_ACCESS \ ../$archivedir/configure \ --prefix=$installdir \ --target=avr \ --disable-nls \ --enable-doc \ --datadir=$installdir/doc/binutils \ --with-gmp=/usr/local \ --with-mpfr=/usr/local \ 2>&1 | tee binutils-configure.log \endverbatim - Make \verbatim make all html install install-html 2>&1 | tee binutils-make.log \endverbatim - Manually change documentation location. - GCC
- Open source code pacakge and patch as necessary. - Configure and build in a directory outside of the source code tree. - Set PATH, in order: - \ - \ - /usr/local/bin - /usr/bin - /bin - /mingw/bin - c:/cygwin/bin - \/bin - Configure \verbatim LDFLAGS='-L /usr/local/lib -R /usr/local/lib' \ CFLAGS='-D__USE_MINGW_ACCESS' \ ../gcc-$version/configure \ --with-gmp=/usr/local \ --with-mpfr=/usr/local \ --with-mpc=/usr/local \ --prefix=$installdir \ --target=$target \ --enable-languages=c,c++ \ --with-dwarf2 \ --enable-doc \ --with-docdir=$installdir/doc/$project \ --disable-shared \ --disable-libada \ --disable-libssp \ 2>&1 | tee $project-configure.log \endverbatim - Make \verbatim make all html install 2>&1 | tee $package-make.log \endverbatim - avr-libc
- Open source code package. - Configure and build at the top of the source code tree. - Set PATH, in order: - /usr/local/bin - /mingw/bin - /bin - \ - \/bin - \ - \ - \ - \ - c:/cygwin/bin - Configure \verbatim ./configure \ --host=avr \ --prefix=$installdir \ --enable-doc \ --disable-versioned-doc \ --enable-html-doc \ --enable-pdf-doc \ --enable-man-doc \ --mandir=$installdir/man \ --datadir=$installdir \ 2>&1 | tee $package-configure.log \endverbatim - Make \verbatim make all install 2>&1 | tee $package-make.log \endverbatim - Manually change location of man page documentation. - Move the examples to the top level of the install tree. - Convert line endings in examples to Windows line endings. - Convert line endings in header files to Windows line endings. - AVRDUDE
- Open source code package. - Configure and build at the top of the source code tree. - Set PATH, in order: - \ - /usr/local/bin - /usr/bin - /bin - /mingw/bin - c:/cygwin/bin - \/bin - Set location of LibUSB headers and libraries \verbatim export CPPFLAGS="-I../../libusb-win32-device-bin-$libusb_version/include" export CFLAGS="-I../../libusb-win32-device-bin-$libusb_version/include" export LDFLAGS="-L../../libusb-win32-device-bin-$libusb_version/lib/gcc" \endverbatim - Configure \verbatim ./configure \ --prefix=$installdir \ --datadir=$installdir \ --sysconfdir=$installdir/bin \ --enable-doc \ --disable-versioned-doc \ 2>&1 | tee $package-configure.log \endverbatim - Make \verbatim make -k all install 2>&1 | tee $package-make.log \endverbatim - Convert line endings in avrdude config file to Windows line endings. - Delete backup copy of avrdude config file in install directory if exists. - Insight/GDB
- Open source code pacakge and patch as necessary. - Configure and build in a directory outside of the source code tree. - Set PATH, in order: - \ - /usr/local/bin - /usr/bin - /bin - /mingw/bin - c:/cygwin/bin - \/bin - Configure \verbatim CFLAGS=-D__USE_MINGW_ACCESS \ LDFLAGS='-static' \ ../$archivedir/configure \ --prefix=$installdir \ --target=avr \ --with-gmp=/usr/local \ --with-mpfr=/usr/local \ --enable-doc \ 2>&1 | tee insight-configure.log \endverbatim - Make \verbatim make all install 2>&1 | tee $package-make.log \endverbatim - SRecord
- Open source code package. - Configure and build at the top of the source code tree. - Set PATH, in order: - \ - /usr/local/bin - /usr/bin - /bin - /mingw/bin - c:/cygwin/bin - \/bin - Configure \verbatim ./configure \ --prefix=$installdir \ --infodir=$installdir/info \ --mandir=$installdir/man \ 2>&1 | tee $package-configure.log \endverbatim - Make \verbatim make all install 2>&1 | tee $package-make.log \endverbatim Build the tools below in Cygwin. - AVaRICE
- Open source code package. - Configure and build in a directory outside of the source code tree. - Set PATH, in order: - \ - /usr/local/bin - /usr/bin - /bin - \/bin - Set location of LibUSB headers and libraries \verbatim export CPPFLAGS=-I$startdir/libusb-win32-device-bin-$libusb_version/include export CFLAGS=-I$startdir/libusb-win32-device-bin-$libusb_version/include export LDFLAGS="-static -L$startdir/libusb-win32-device-bin-$libusb_version/lib/gcc " \endverbatim - Configure \verbatim ../$archivedir/configure \ --prefix=$installdir \ --datadir=$installdir/doc \ --mandir=$installdir/man \ --infodir=$installdir/info \ 2>&1 | tee avarice-configure.log \endverbatim - Make \verbatim make all install 2>&1 | tee avarice-make.log \endverbatim - SimulAVR
- Open source code package. - Configure and build in a directory outside of the source code tree. - Set PATH, in order: - \ - /usr/local/bin - /usr/bin - /bin - \/bin - Configure \verbatim export LDFLAGS="-static" ../$archivedir/configure \ --prefix=$installdir \ --datadir=$installdir \ --disable-tests \ --disable-versioned-doc \ 2>&1 | tee simulavr-configure.log \endverbatim - Make \verbatim make -k all install 2>&1 | tee simulavr-make.log make pdf install-pdf 2>&1 | tee simulavr-pdf-make.log \endverbatim */ avr-libc-1.8.0.orig/doc/api/sfr.dox0000644000000000000000000000712111732702554013677 0ustar /* Copyright (c) 2002, Joerg Wunsch Copyright (c) 2008, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: sfr.dox 1631 2008-03-17 17:59:10Z arcanum $ */ /** \defgroup avr_sfr : Special function registers When working with microcontrollers, many tasks usually consist of controlling internal peripherals, or external peripherals that are connected to the device. The entire IO address space is made available as memory-mapped IO, i.e. it can be accessed using all the MCU instructions that are applicable to normal data memory. For most AVR devices, the IO register space is mapped into the data memory address space with an offset of 0x20 since the bottom of this space is reserved for direct access to the MCU registers. (Actual SRAM is available only behind the IO register area, starting at some specific address depending on the device.) For example the user can access memory-mapped IO registers as if they were globally defined variables like this: \code PORTA = 0x33; unsigned char foo = PINA; \endcode The compiler will choose the correct instruction sequence to generate based on the address of the register being accessed. The advantage of using the memory-mapped registers in C programs is that it makes the programs more portable to other C compilers for the AVR platform. Note that special care must be taken when accessing some of the 16-bit timer IO registers where access from both the main program and within an interrupt context can happen. See \ref faq_16bitio. \par Porting programs that use the deprecated sbi/cbi macros Access to the AVR single bit set and clear instructions are provided via the standard C bit manipulation commands. The sbi and cbi macros are no longer directly supported. sbi (sfr,bit) can be replaced by sfr |= _BV(bit) . i.e.: sbi(PORTB, PB1); is now PORTB |= _BV(PB1); This actually is more flexible than having sbi directly, as the optimizer will use a hardware sbi if appropriate, or a read/or/write operation if not appropriate. You do not need to keep track of which registers sbi/cbi will operate on. Likewise, cbi (sfr,bit) is now sfr &= ~(_BV(bit)); */ avr-libc-1.8.0.orig/doc/api/malloc-std.fig0000644000000000000000000000531311732702554015120 0ustar #FIG 3.2 Landscape Center Metric A4 100.00 Single -2 1200 2 0 32 #cfcfcf 2 1 0 2 0 7 50 0 -1 0.000 0 0 -1 1 0 2 1 1 2.00 120.00 240.00 2385 2250 3105 2250 2 1 0 2 0 7 50 0 -1 0.000 0 0 -1 1 0 2 1 1 2.00 120.00 240.00 4050 2250 3375 2250 2 2 0 0 0 26 100 0 20 0.000 0 0 -1 0 0 5 3375 3150 4185 3150 4185 1800 3375 1800 3375 3150 2 2 0 0 0 3 100 0 20 0.000 0 0 -1 0 0 5 450 3150 1350 3150 1350 1800 450 1800 450 3150 2 2 0 0 0 14 100 0 20 0.000 0 0 -1 0 0 5 1350 3150 2250 3150 2250 1800 1350 1800 1350 3150 2 2 0 0 0 23 100 0 20 0.000 0 0 -1 0 0 5 2250 3150 3150 3150 3150 1800 2250 1800 2250 3150 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 4500 3600 4140 3600 4140 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 3690 3600 3375 3600 3375 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 3600 3915 3150 3915 3150 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 3600 4230 2250 4230 2250 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 2700 4770 1350 4770 1350 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 2700 5085 450 5085 450 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 2700 4500 2250 4500 2250 4230 2 2 0 0 0 32 100 0 20 0.000 0 0 -1 0 0 5 3150 3150 3375 3150 3375 1800 3150 1800 3150 3150 2 2 0 1 0 7 49 0 -1 0.000 0 0 -1 0 0 5 450 1800 4185 1800 4185 3150 450 3150 450 1800 2 2 0 1 0 32 150 0 20 0.000 0 0 -1 0 0 5 4185 1800 7200 1800 7200 3150 4185 3150 4185 1800 4 0 0 50 0 16 12 0.0000 4 135 765 540 2700 variables\001 4 0 0 50 0 16 12 0.0000 4 135 405 675 2430 .data\001 4 0 0 50 0 16 12 0.0000 4 135 765 1440 2700 variables\001 4 0 0 50 0 16 12 0.0000 4 135 330 1620 2430 .bss\001 4 0 0 50 0 16 12 1.5708 4 135 645 4140 1665 0x10FF\001 4 0 0 50 0 16 12 1.5708 4 135 615 630 1620 0x0100\001 4 0 0 50 0 16 12 0.0000 4 180 420 2385 2700 heap\001 4 0 0 50 0 16 12 0.0000 4 135 435 3555 2700 stack\001 4 0 0 50 0 16 18 0.0000 4 210 1815 1305 1530 on-board RAM\001 4 0 4 100 0 16 48 0.0000 4 525 195 3150 2565 !\001 4 0 0 100 0 16 12 0.0000 4 165 915 2835 4545 __bss_end\001 4 0 0 100 0 16 12 0.0000 4 165 2265 2835 4815 __data_end == __bss_start\001 4 0 0 100 0 16 12 0.0000 4 165 1020 2835 5130 __data_start\001 4 0 0 100 0 16 12 0.0000 4 135 810 4590 3645 RAMEND\001 4 0 0 100 0 16 12 0.0000 4 135 240 3780 3645 SP\001 4 0 0 50 0 16 18 0.0000 4 210 1650 4815 1530 external RAM\001 4 0 0 50 0 16 12 1.5708 4 135 615 4365 1665 0x1100\001 4 0 0 50 0 16 12 1.5708 4 135 675 7155 1665 0xFFFF\001 4 0 0 100 0 16 12 0.0000 4 180 3330 3690 4275 *(__malloc_heap_start) == __heap_start\001 4 0 0 100 0 16 12 0.0000 4 180 3480 3735 3960 *(__brkval) (<= *SP - *(__malloc_margin))\001 avr-libc-1.8.0.orig/doc/api/dox.css0000644000000000000000000000413111732702554013673 0ustar BODY { background-color: #feffe2 } H1 { text-align: center; } A.qindex {} A.qindexRef {} A.el { text-decoration: none; font-weight: bold } A.elRef { font-weight: bold } A.code { text-decoration: none; font-weight: normal; color: #4444ee } A.codeRef { font-weight: normal; color: #4444ee } A:hover { text-decoration: none; color: #600000; background-color: #ffffff } DL.el { margin-left: -1cm } DIV.fragment { border-style: solid; border-color: black; border-width: thin; color: #5000a0; background-color: #fffff0; padding-left: 5px; margin-right: 5px; } DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px } TD.memname { color: #0050a0; font-weight: bold; white-space: nowrap; } TD.memitem { color: #0050a0; font-weight: bold; white-space: nowrap; } .memproto { border-style: solid; border-color: black; border-width: thin; background-color: #fdfff8; padding-left: 5px; margin-right: 5px; padding-top: 5px; padding-bottom: 5px; width: 50%; } TD.paramtype { font-weight: bold; color: #0050a0; white-space: nowrap; } TD.paramname { font-weight: bold; color: #702020; white-space: nowrap; } TD.mdRow { background-color: #feffe2; font-weight: bold; } TD.md { background-color: #feffe2; color: #0050a0; font-weight: bold; } TD.mdname1 { background-color: #feffe2; font-weight: bold; color: #702020; } TD.mdname { background-color: #feffe2; font-weight: bold; color: #702020; width: 600px; } DIV.groupHeader { margin-left: 16px; margin-top: 12px; margin-bottom: 6px; font-weight: bold } DIV.groupText { margin-left: 16px; font-style: italic; font-size: smaller } FONT.keyword { color: #008000 } FONT.keywordtype { color: #604020 } FONT.keywordflow { color: #e08000 } FONT.comment { color: #800000 } FONT.preprocessor { color: #806020 } FONT.stringliteral { color: #002080 } FONT.charliteral { color: #008080 } avr-libc-1.8.0.orig/doc/api/porting.dox0000644000000000000000000002145211732702554014572 0ustar /* Copyright (c) 2007 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: porting.dox 1526 2007-12-20 14:17:56Z joerg_wunsch $ */ /** \page porting Porting From IAR to AVR GCC \section iar_porting_intro Introduction C language was designed to be a portable language. There two main types of porting activities: porting an application to a different platform (OS and/or processor), and porting to a different compiler. Porting to a different compiler can be exacerbated when the application is an embedded system. For example, the C language Standard, strangely, does not specify a standard for declaring and defining Interrupt Service Routines (ISRs). Different compilers have different ways of defining registers, some of which use non-standard language constructs. This chapter describes some methods and pointers on porting an AVR application built with the IAR compiler to the GNU toolchain (AVR GCC). Note that this may not be an exhaustive list. \section iar_porting_register Registers IO header files contain identifiers for all the register names and bit names for a particular processor. IAR has individual header files for each processor and they must be included when registers are being used in the code. For example: \code #include \endcode \note IAR does not always use the same register names or bit names that are used in the AVR datasheet. AVR GCC also has individual IO header files for each processor. However, the actual processor type is specified as a command line flag to the compiler. (Using the \c -mmcu=processor flag.) This is usually done in the Makefile. This allows you to specify only a single header file for any processor type: \code #include \endcode \note The forward slash in the file name that is used to separate subdirectories can be used on Windows distributions of the toolchain and is the recommended method of including this file. The compiler knows the processor type and through the single header file above, it can pull in and include the correct individual IO header file. This has the advantage that you only have to specify one generic header file, and you can easily port your application to another processor type without having to change every file to include the new IO header file. The AVR toolchain tries to adhere to the exact names of the registers and names of the bits found in the AVR datasheet. There may be some descrepencies between the register names found in the IAR IO header files and the AVR GCC IO header files. \section iar_porting_isr Interrupt Service Routines (ISRs) As mentioned above, the C language Standard, strangely, does not specify a standard way of declaring and defining an ISR. Hence, every compiler seems to have their own special way of doing so. IAR declares an ISR like so: \code #pragma vector=TIMER0_OVF_vect __interrupt void MotorPWMBottom() { // code } \endcode In AVR GCC, you declare an ISR like so: \code ISR(PCINT1_vect) { //code } \endcode AVR GCC uses the \c ISR macro to define an ISR. This macro requries the header file: \code #include \endcode The names of the various interrupt vectors are found in the individual processor IO header files that you must include with \c . \note The names of the interrupt vectors in AVR GCC has been changed to match the names of the vectors in IAR. This significantly helps in porting applications from IAR to AVR GCC. \section iar_porting_intrinsic Intrinsic Routines IAR has a number of intrinsic routine such as \c __enable_interrupts() \c __disable_interrupts() \c __watchdog_reset() These intrinsic functions compile to specific AVR opcodes (SEI, CLI, WDR). There are equivalent macros that are used in AVR GCC, however they are not located in a single include file. AVR GCC has \c sei() for \c __enable_interrupts(), and \c cli() for \c __disable_interrupts(). Both of these macros are located in \c . AVR GCC has the macro \c wdt_reset() in place of \c __watchdog_reset(). However, there is a whole Watchdog Timer API available in AVR GCC that can be found in \c . \section iar_porting_flash Flash Variables The C language was not designed for Harvard architecture processors with separate memory spaces. This means that there are various non-standard ways to define a variable whose data resides in the Program Memory (Flash). IAR uses a non-standard keyword to declare a variable in Program Memory: \code __flash int mydata[] = .... \endcode AVR GCC uses Variable Attributes to achieve the same effect: \code int mydata[] __attribute__((progmem)) \endcode \note See the GCC User Manual for more information about Variable Attributes. avr-libc provides a convenience macro for the Variable Attribute: \code #include . . . int mydata[] PROGMEM = .... \endcode \note The PROGMEM macro expands to the Variable Attribute of \c progmem. This macro requires that you include \c . This is the canonical method for defining a variable in Program Space. To read back flash data, use the \c pgm_read_*() macros defined in \c . All Program Memory handling macros are defined there. There is also a way to create a method to define variables in Program Memory that is common between the two compilers (IAR and AVR GCC). Create a header file that has these definitions: \code #if defined(__ICCAVR__) // IAR C Compiler #define FLASH_DECLARE(x) __flash x #endif #if defined(__GNUC__) // GNU Compiler #define FLASH_DECLARE(x) x __attribute__((__progmem__)) #endif \endcode This code snippet checks for the IAR compiler or for the GCC compiler and defines a macro \c FLASH_DECLARE(x) that will declare a variable in Program Memory using the appropriate method based on the compiler that is being used. Then you would used it like so: \code FLASH_DECLARE(int mydata[] = ...); \endcode \section iar_porting_non_returning_main Non-Returning main() To declare main() to be a non-returning function in IAR, it is done like this: \code __C_task void main(void) { // code } \endcode To do the equivalent in AVR GCC, do this: \code void main(void) __attribute__((noreturn)); void main(void) { //... } \endcode \note See the GCC User Manual for more information on Function Attributes. In AVR GCC, a prototype for main() is required so you can declare the function attribute to specify that the main() function is of type "noreturn". Then, define main() as normal. Note that the return type for main() is now \c void. \section iar_porting_locking Locking Registers The IAR compiler allows a user to lock general registers from r15 and down by using compiler options and this keyword syntax: \code __regvar __no_init volatile unsigned int filteredTimeSinceCommutation @14; \endcode This line locks r14 for use only when explicitly referenced in your code thorugh the var name "filteredTimeSinceCommutation". This means that the compiler cannot dispose of it at its own will. To do this in AVR GCC, do this: \code register unsigned char counter asm("r3"); \endcode Typically, it should be possible to use r2 through r15 that way. \note Do not reserve r0 or r1 as these are used internally by the compiler for a temporary register and for a zero value. \note Locking registers is not recommended in AVR GCC as it removes this register from the control of the compiler, which may make code generation worse. Use at your own risk. */ avr-libc-1.8.0.orig/doc/api/Makefile.in0000644000000000000000000004423211732702554014442 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ subdir = doc/api DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = SOURCES = DIST_SOURCES = DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = @ACLOCAL@ AMTAR = @AMTAR@ AR = @AR@ AS = @AS@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AVR_LIBC_MAJOR = @AVR_LIBC_MAJOR@ AVR_LIBC_MINOR = @AVR_LIBC_MINOR@ AVR_LIBC_RELDATE = @AVR_LIBC_RELDATE@ AVR_LIBC_REVISION = @AVR_LIBC_REVISION@ AVR_LIBC_USER_MANUAL = @AVR_LIBC_USER_MANUAL@ AVR_LIBC_VERSION = @AVR_LIBC_VERSION@ AVR_LIBC_VERSION_NUMERIC = @AVR_LIBC_VERSION_NUMERIC@ AWK = @AWK@ CC = @CC@ CCAS = @CCAS@ CCASDEPMODE = @CCASDEPMODE@ CCASFLAGS = @CCASFLAGS@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ CPPFLAGS = @CPPFLAGS@ CYGPATH_W = @CYGPATH_W@ DEFS = @DEFS@ DEPDIR = @DEPDIR@ DOCSDIR = @DOCSDIR@ DOC_INST_DIR = @DOC_INST_DIR@ ECHO_C = @ECHO_C@ ECHO_N = @ECHO_N@ ECHO_T = @ECHO_T@ EXEEXT = @EXEEXT@ FNO_JUMP_TABLES = @FNO_JUMP_TABLES@ HAS_DELAY_CYCLES = @HAS_DELAY_CYCLES@ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_DOX_HTML = @INSTALL_DOX_HTML@ INSTALL_DOX_MAN = @INSTALL_DOX_MAN@ INSTALL_DOX_PDF = @INSTALL_DOX_PDF@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_SCRIPT = @INSTALL_SCRIPT@ INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ LDFLAGS = @LDFLAGS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAKEINFO = @MAKEINFO@ MKDIR_P = @MKDIR_P@ OBJEXT = @OBJEXT@ PACKAGE = @PACKAGE@ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ PACKAGE_NAME = @PACKAGE_NAME@ PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_URL = @PACKAGE_URL@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ PNGTOPNM = @PNGTOPNM@ PNMTOPNG = @PNMTOPNG@ RANLIB = @RANLIB@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ TARGET_DOX_HTML = @TARGET_DOX_HTML@ TARGET_DOX_PDF = @TARGET_DOX_PDF@ VERSION = @VERSION@ abs_builddir = @abs_builddir@ abs_srcdir = @abs_srcdir@ abs_top_builddir = @abs_top_builddir@ abs_top_srcdir = @abs_top_srcdir@ ac_ct_CC = @ac_ct_CC@ am__include = @am__include@ am__leading_dot = @am__leading_dot@ am__quote = @am__quote@ am__tar = @am__tar@ am__untar = @am__untar@ bindir = @bindir@ build = @build@ build_alias = @build_alias@ build_cpu = @build_cpu@ build_os = @build_os@ build_vendor = @build_vendor@ builddir = @builddir@ datadir = @datadir@ datarootdir = @datarootdir@ docdir = @docdir@ dvidir = @dvidir@ exec_prefix = @exec_prefix@ host = @host@ host_alias = @host_alias@ host_cpu = @host_cpu@ host_os = @host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ # # Copyright (c) 2002, 2003, 2005, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # 3. The name of the author may not be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN # NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED # TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR # PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Author: Theodore A. Roth # # Contributors: # # $Id: Makefile.am 2224 2011-02-23 19:25:28Z joerg_wunsch $ # MAINTAINERCLEANFILES = Makefile.in stamp-vti CLEANFILES = *.html *.pdf *.ma *.mas \ *.png *.eps fix_png \ doxygen.config doxygen-pdf.config EXTRA_DIST = dox.css dox_html_header dox_html_footer \ doxygen.config.in \ main_page.dox \ assembler.dox \ inline_asm.dox \ interrupts.dox \ acknowledge.dox \ malloc.dox \ $(IMAGE_SRC) \ sections.dox \ sfr.dox \ tools-install.dox \ using-avrprog.dox \ using-tools.dox \ faq.dox \ rel-method.dox \ bench.dox \ bench-libc.dox \ bench-libm.dox \ porting.dox \ overview.dox \ pgmspace.dox \ library.dox \ vectortable.dox SUFFIXES = .pdf .fig .png .eps USER_MANUAL = @AVR_LIBC_USER_MANUAL@ # As avr-gcc must have been installed already, we can reference its # library by a -l option. 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Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: library.dox 1553 2008-01-03 19:33:15Z arcanum $ */ /** \page library How to Build a Library \section library_intro Introduction So you keep reusing the same functions that you created over and over? Tired of cut and paste going from one project to the next? Would you like to reduce your maintenance overhead? Then you're ready to create your own library! Code reuse is a very laudable goal. With some upfront investment, you can save time and energy on future projects by having ready-to-go libraries. This chapter describes some background information, design considerations, and practical knowledge that you will need to create and use your own libraries. \section library_linker How the Linker Works The compiler compiles a single high-level language file (C language, for example) into a single object module file. The linker (ld) can only work with object modules to link them together. Object modules are the smallest unit that the linker works with. Typically, on the linker command line, you will specify a set of object modules (that has been previously compiled) and then a list of libraries, including the Standard C Library. The linker takes the set of object modules that you specify on the command line and links them together. Afterwards there will probably be a set of "undefined references". A reference is essentially a function call. An undefined reference is a function call, with no defined function to match the call. The linker will then go through the libraries, in order, to match the undefined references with function definitions that are found in the libraries. If it finds the function that matches the call, the linker will then link in the object module in which the function is located. This part is important: the linker links in THE ENTIRE OBJECT MODULE in which the function is located. Remember, the linker knows nothing about the functions internal to an object module, other than symbol names (such as function names). The smallest unit the linker works with is object modules. When there are no more undefined references, the linker has linked everything and is done and outputs the final application. \section library_design How to Design a Library How the linker behaves is very important in designing a library. Ideally, you want to design a library where only the functions that are called are the only functions to be linked into the final application. This helps keep the code size to a minimum. In order to do this, with the way the linker works, is to only write one function per code module. This will compile to one function per object module. This is usually a very different way of doing things than writing an application! There are always exceptions to the rule. There are generally two cases where you would want to have more than one function per object module. The first is when you have very complementary functions that it doesn't make much sense to split them up. For example, malloc() and free(). If someone is going to use malloc(), they will very likely be using free() (or at least should be using free()). In this case, it makes more sense to aggregate those two functions in the same object module. The second case is when you want to have an Interrupt Service Routine (ISR) in your library that you want to link in. The problem in this case is that the linker looks for unresolved references and tries to resolve them with code in libraries. A reference is the same as a function call. But with ISRs, there is no function call to initiate the ISR. The ISR is placed in the Interrupt Vector Table (IVT), hence no call, no reference, and no linking in of the ISR. In order to do this, you have to trick the linker in a way. Aggregate the ISR, with another function in the same object module, but have the other function be something that is required for the user to call in order to use the ISR, like perhaps an initialization function for the subsystem, or perhaps a function that enables the ISR in the first place. \section library_creating Creating a Library The librarian program is called \c ar (for "archiver") and is found in the GNU Binutils project. This program will have been built for the AVR target and will therefore be named \c avr-ar. The job of the librarian program is simple: aggregate a list of object modules into a single library (archive) and create an index for the linker to use. The name that you create for the library filename must follow a specific pattern: libname.a. The name part is the unique part of the filename that you create. It makes it easier if the name part relates to what the library is about. This name part must be prefixed by "lib", and it must have a file extension of .a, for "archive". The reason for the special form of the filename is for how the library gets used by the toolchain, as we will see later on. \note The filename is case-sensitive. Use a lowercase "lib" prefix, and a lowercase ".a" as the file extension. The command line is fairly simple: \code avr-ar rcs \endcode The \c r command switch tells the program to insert the object modules into the archive with replacement. The \c c command line switch tells the program to create the archive. And the \c s command line switch tells the program to write an object-file index into the archive, or update an existing one. This last switch is very important as it helps the linker to find what it needs to do its job. \note The command line switches are case sensitive! There are uppercase switches that have completely different actions. \note MFile and the WinAVR distribution contain a Makefile Template that includes the necessary command lines to build a library. You will have to manually modify the template to switch it over to build a library instead of an application. See the GNU Binutils manual for more information on the \c ar program. \section library_using Using a Library To use a library, use the \c -l switch on your linker command line. The string immediately following the \c -l is the unique part of the library filename that the linker will link in. For example, if you use: \code -lm \endcode this will expand to the library filename: \code libm.a \endcode which happens to be the math library included in avr-libc. If you use this on your linker command line: \code -lprintf_flt \endcode then the linker will look for a library called: \code libprintf_flt.a \endcode This is why naming your library is so important when you create it! The linker will search libraries in the order that they appear on the command line. Whichever function is found first that matches the undefined reference, it will be linked in. There are also command line switches that tell GCC which directory to look in (\c -L) for the libraries that are specified to be linke in with \c -l. See the GNU Binutils manual for more information on the GNU linker (ld) program. */ avr-libc-1.8.0.orig/doc/api/malloc.dox0000644000000000000000000003062411732702554014360 0ustar /* Copyright (c) 2002, 2009 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: malloc.dox 2143 2010-06-08 21:19:51Z joerg_wunsch $ */ /** \page malloc Memory Areas and Using malloc() \section malloc_intro Introduction Many of the devices that are possible targets of avr-libc have a minimal amount of RAM. The smallest parts supported by the C environment come with 128 bytes of RAM. This needs to be shared between initialized and uninitialized variables (\ref mem_sections "sections" \c .data and \c .bss), the dynamic memory allocator, and the stack that is used for calling subroutines and storing local (automatic) variables. Also, unlike larger architectures, there is no hardware-supported memory management which could help in separating the mentioned RAM regions from being overwritten by each other. The standard RAM layout is to place \c .data variables first, from the beginning of the internal RAM, followed by \c .bss. The stack is started from the top of internal RAM, growing downwards. The so-called "heap" available for the dynamic memory allocator will be placed beyond the end of \c .bss. Thus, there's no risk that dynamic memory will ever collide with the RAM variables (unless there were bugs in the implementation of the allocator). There is still a risk that the heap and stack could collide if there are large requirements for either dynamic memory or stack space. The former can even happen if the allocations aren't all that large but dynamic memory allocations get fragmented over time such that new requests don't quite fit into the "holes" of previously freed regions. Large stack space requirements can arise in a C function containing large and/or numerous local variables or when recursively calling function. \note The pictures shown in this document represent typical situations where the RAM locations refer to an ATmega128. The memory addresses used are not displayed in a linear scale. \image html malloc-std.png "RAM map of a device with internal RAM" \image latex malloc-std.eps "RAM map of a device with internal RAM" width=7.5cm On a simple device like a microcontroller it is a challenge to implement a dynamic memory allocator that is simple enough so the code size requirements will remain low, yet powerful enough to avoid unnecessary memory fragmentation and to get it all done with reasonably few CPU cycles. Microcontrollers are often low on space and also run at much lower speeds than the typical PC these days. The memory allocator implemented in avr-libc tries to cope with all of these constraints, and offers some tuning options that can be used if there are more resources available than in the default configuration. \section malloc_where Internal vs. external RAM Obviously, the constraints are much harder to satisfy in the default configuration where only internal RAM is available. Extreme care must be taken to avoid a stack-heap collision, both by making sure functions aren't nesting too deeply, and don't require too much stack space for local variables, as well as by being cautious with allocating too much dynamic memory. If external RAM is available, it is strongly recommended to move the heap into the external RAM, regardless of whether or not the variables from the \c .data and \c .bss sections are also going to be located there. The stack should always be kept in internal RAM. Some devices even require this, and in general, internal RAM can be accessed faster since no extra wait states are required. When using dynamic memory allocation and stack and heap are separated in distinct memory areas, this is the safest way to avoid a stack-heap collision. \section malloc_tunables Tunables for malloc() There are a number of variables that can be tuned to adapt the behavior of malloc() to the expected requirements and constraints of the application. Any changes to these tunables should be made before the very first call to malloc(). Note that some library functions might also use dynamic memory (notably those from the \ref avr_stdio), so make sure the changes will be done early enough in the startup sequence. The variables \c __malloc_heap_start and \c __malloc_heap_end can be used to restrict the malloc() function to a certain memory region. These variables are statically initialized to point to \c __heap_start and \c __heap_end, respectively, where \c __heap_start is filled in by the linker to point just beyond \c .bss, and \c __heap_end is set to 0 which makes malloc() assume the heap is below the stack. If the heap is going to be moved to external RAM, \c __malloc_heap_end \e must be adjusted accordingly. This can either be done at run-time, by writing directly to this variable, or it can be done automatically at link-time, by adjusting the value of the symbol \c __heap_end. \anchor malloc_extram The following example shows a linker command to relocate the entire \c .data and \c .bss segments, and the heap to location 0x1100 in external RAM. The heap will extend up to address 0xffff. \code avr-gcc ... -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff ... \endcode \note See \ref harvard_arch "explanation" for offset 0x800000. See the chapter about \ref gcc_minusW "using gcc" for the \c -Wl options. \note The ld (linker) user manual states that using -Tdata=<x> is equivalent to using --section-start,.data=<x>. However, you have to use --section-start as above because the GCC frontend also sets the -Tdata option for all MCU types where the SRAM doesn't start at 0x800060. Thus, the linker is being faced with two -Tdata options. Sarting with binutils 2.16, the linker changed the preference, and picks the "wrong" option in this situation. \image html malloc-x1.png "Internal RAM: stack only, external RAM: variables and heap" \image latex malloc-x1.eps "Internal RAM: stack only, external RAM: variables and heap" width=12cm If dynamic memory should be placed in external RAM, while keeping the variables in internal RAM, something like the following could be used. Note that for demonstration purposes, the assignment of the various regions has not been made adjacent in this example, so there are "holes" below and above the heap in external RAM that remain completely unaccessible by regular variables or dynamic memory allocations (shown in light bisque color in the picture below). \code avr-gcc ... -Wl,--defsym=__heap_start=0x802000,--defsym=__heap_end=0x803fff ... \endcode \image html malloc-x2.png "Internal RAM: variables and stack, external RAM: heap" \image latex malloc-x2.eps "Internal RAM: variables and stack, external RAM: heap" width=12cm If \c __malloc_heap_end is 0, the allocator attempts to detect the bottom of stack in order to prevent a stack-heap collision when extending the actual size of the heap to gain more space for dynamic memory. It will not try to go beyond the current stack limit, decreased by \c __malloc_margin bytes. Thus, all possible stack frames of interrupt routines that could interrupt the current function, plus all further nested function calls must not require more stack space, or they will risk colliding with the data segment. The default value of \c __malloc_margin is set to 32. \section malloc_impl Implementation details Dynamic memory allocation requests will be returned with a two-byte header prepended that records the size of the allocation. This is later used by free(). The returned address points just beyond that header. Thus, if the application accidentally writes before the returned memory region, the internal consistency of the memory allocator is compromised. The implementation maintains a simple freelist that accounts for memory blocks that have been returned in previous calls to free(). Note that all of this memory is considered to be successfully added to the heap already, so no further checks against stack-heap collisions are done when recycling memory from the freelist. The freelist itself is not maintained as a separate data structure, but rather by modifying the contents of the freed memory to contain pointers chaining the pieces together. That way, no additional memory is reqired to maintain this list except for a variable that keeps track of the lowest memory segment available for reallocation. Since both, a chain pointer and the size of the chunk need to be recorded in each chunk, the minimum chunk size on the freelist is four bytes. When allocating memory, first the freelist is walked to see if it could satisfy the request. If there's a chunk available on the freelist that will fit the request exactly, it will be taken, disconnected from the freelist, and returned to the caller. If no exact match could be found, the closest match that would just satisfy the request will be used. The chunk will normally be split up into one to be returned to the caller, and another (smaller) one that will remain on the freelist. In case this chunk was only up to two bytes larger than the request, the request will simply be altered internally to also account for these additional bytes since no separate freelist entry could be split off in that case. If nothing could be found on the freelist, heap extension is attempted. This is where \c __malloc_margin will be considered if the heap is operating below the stack, or where \c __malloc_heap_end will be verified otherwise. If the remaining memory is insufficient to satisfy the request, \c NULL will eventually be returned to the caller. When calling free(), a new freelist entry will be prepared. An attempt is then made to aggregate the new entry with possible adjacent entries, yielding a single larger entry available for further allocations. That way, the potential for heap fragmentation is hopefully reduced. When deallocating the topmost chunk of memory, the size of the heap is reduced. A call to realloc() first determines whether the operation is about to grow or shrink the current allocation. When shrinking, the case is easy: the existing chunk is split, and the tail of the region that is no longer to be used is passed to the standard free() function for insertion into the freelist. Checks are first made whether the tail chunk is large enough to hold a chunk of its own at all, otherwise realloc() will simply do nothing, and return the original region. When growing the region, it is first checked whether the existing allocation can be extended in-place. If so, this is done, and the original pointer is returned without copying any data contents. As a side-effect, this check will also record the size of the largest chunk on the freelist. If the region cannot be extended in-place, but the old chunk is at the top of heap, and the above freelist walk did not reveal a large enough chunk on the freelist to satisfy the new request, an attempt is made to quickly extend this topmost chunk (and thus the heap), so no need arises to copy over the existing data. If there's no more space available in the heap (same check is done as in malloc()), the entire request will fail. Otherwise, malloc() will be called with the new request size, the existing data will be copied over, and free() will be called on the old region. */ avr-libc-1.8.0.orig/doc/api/faq.dox0000644000000000000000000017534711732702554013674 0ustar /* Copyright (c) 2002-2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: faq.dox 2259 2011-10-19 11:07:02Z joerg_wunsch $ */ /** \page FAQ Frequently Asked Questions \section faq_index FAQ Index \addindex FAQ -# \ref faq_volatile -# \ref faq_libm -# \ref faq_regbind -# \ref faq_startup -# \ref faq_use_bv -# \ref faq_cplusplus -# \ref faq_varinit -# \ref faq_16bitio -# \ref faq_asmconst "How do I use a \#define'd constant in an asm statement?" -# \ref faq_gdboptimize -# \ref faq_asmstabs -# \ref faq_port_pass -# \ref faq_reg_usage -# \ref faq_rom_array -# \ref faq_ext_ram -# \ref faq_optflags -# \ref faq_reloc_code -# \ref faq_fuses -# \ref faq_flashstrings -# \ref faq_intpromote -# \ref faq_ramoverlap -# \ref faq_tinyavr_c -# \ref faq_clockskew -# \ref faq_intbits -# \ref faq_fuselow -# \ref faq_asmops -# \ref faq_spman -# \ref faq_linkerscripts -# \ref faq_binarydata -# \ref faq_softreset -# \ref faq_math -# \ref faq_reentrant -# \ref faq_eeprom_corruption -# \ref faq_wrong_baud_rate -# \ref faq_funcptr_gt128kib -# \ref faq_assign_chain \section faq_volatile My program doesn't recognize a variable updated within an interrupt routine When using the optimizer, in a loop like the following one: \code uint8_t flag; ... ISR(SOME_vect) { flag = 1; } ... while (flag == 0) { ... } \endcode the compiler will typically access \c flag only once, and optimize further accesses completely away, since its code path analysis shows that nothing inside the loop could change the value of \c flag anyway. To tell the compiler that this variable could be changed outside the scope of its code path analysis (e. g. from within an interrupt routine), the variable needs to be declared like: \code volatile uint8_t flag; \endcode Back to \ref faq_index. \section faq_libm I get "undefined reference to..." for functions like "sin()" In order to access the mathematical functions that are declared in \, the linker needs to be told to also link the mathematical library, libm.a. Typically, system libraries like libm.a are given to the final C compiler command line that performs the linking step by adding a flag -lm at the end. (That is, the initial \a lib and the filename suffix from the library are written immediately after a \a -l flag. So for a libfoo.a library, -lfoo needs to be provided.) This will make the linker search the library in a path known to the system. An alternative would be to specify the full path to the libm.a file at the same place on the command line, i. e. \a after all the object files (*.o). However, since this requires knowledge of where the build system will exactly find those library files, this is deprecated for system libraries. Back to \ref faq_index. \section faq_regbind How to permanently bind a variable to a register? This can be done with \code register unsigned char counter asm("r3"); \endcode Typically, it should be safe to use r2 through r7 that way. Registers r8 through r15 can be used for argument passing by the compiler in case many or long arguments are being passed to callees. If this is not the case throughout the entire application, these registers could be used for register variables as well. Extreme care should be taken that the entire application is compiled with a consistent set of register-allocated variables, including possibly used library functions. See \ref c_names_in_asm for more details. Back to \ref faq_index. \section faq_startup How to modify MCUCR or WDTCR early? The method of early initialization (MCUCR, WDTCR or anything else) is different (and more flexible) in the current version. Basically, write a small assembler file which looks like this: \code ;; begin xram.S #include .section .init1,"ax",@progbits ldi r16,_BV(SRE) | _BV(SRW) out _SFR_IO_ADDR(MCUCR),r16 ;; end xram.S \endcode Assemble it, link the resulting xram.o with other files in your program, and this piece of code will be inserted in initialization code, which is run right after reset. See the linker script for comments about the new .initN sections (which one to use, etc.). The advantage of this method is that you can insert any initialization code you want (just remember that this is very early startup -- no stack and no __zero_reg__ yet), and no program memory space is wasted if this feature is not used. There should be no need to modify linker scripts anymore, except for some very special cases. It is best to leave __stack at its default value (end of internal SRAM -- faster, and required on some devices like ATmega161 because of errata), and add -Wl,-Tdata,0x801100 to start the data section above the stack. For more information on using sections, see \ref mem_sections. There is also an example for \ref c_sections. Note that in C code, any such function would preferably be placed into section \c .init3 as the code in \c .init2 ensures the internal register __zero_reg__ is already cleared. Back to \ref faq_index. \section faq_use_bv What is all this _BV() stuff about? When performing low-level output work, which is a very central point in microcontroller programming, it is quite common that a particular bit needs to be set or cleared in some IO register. While the device documentation provides mnemonic names for the various bits in the IO registers, and the \ref avr_io "AVR device-specific IO definitions" reflect these names in definitions for numerical constants, a way is needed to convert a bit number (usually within a byte register) into a byte value that can be assigned directly to the register. However, sometimes the direct bit numbers are needed as well (e. g. in an SBI() instruction), so the definitions cannot usefully be made as byte values in the first place. So in order to access a particular bit number as a byte value, use the _BV() macro. Of course, the implementation of this macro is just the usual bit shift (which is done by the compiler anyway, thus doesn't impose any run-time penalty), so the following applies: \code _BV(3) => 1 << 3 => 0x08 \endcode However, using the macro often makes the program better readable. "BV" stands for "bit value", in case someone might ask you. :-) Example: clock timer 2 with full IO clock (CS2x = 0b001), toggle OC2 output on compare match (COM2x = 0b01), and clear timer on compare match (CTC2 = 1). Make OC2 (PD7) an output. \code TCCR2 = _BV(COM20)|_BV(CTC2)|_BV(CS20); DDRD = _BV(PD7); \endcode Back to \ref faq_index. \section faq_cplusplus Can I use C++ on the AVR? Basically yes, C++ is supported (assuming your compiler has been configured and compiled to support it, of course). Source files ending in \c .cc, \c .cpp or \c .C will automatically cause the compiler frontend to invoke the C++ compiler. Alternatively, the C++ compiler could be explicitly called by the name \c avr-c++. However, there's currently no support for \c libstdc++, the standard support library needed for a complete C++ implementation. This imposes a number of restrictions on the C++ programs that can be compiled. Among them are: - Obviously, none of the C++ related standard functions, classes, and template classes are available. - The operators \c new and \c delete are not implemented, attempting to use them will cause the linker to complain about undefined external references. (This could perhaps be fixed.) - Some of the supplied include files are not C++ safe, i. e. they need to be wrapped into \code extern "C" { . . . } \endcode (This could certainly be fixed, too.) - Exceptions are not supported. Since exceptions are enabled by default in the C++ frontend, they explicitly need to be turned off using \c -fno-exceptions in the compiler options. Failing this, the linker will complain about an undefined external reference to \c __gxx_personality_sj0. Constructors and destructors \e are supported though, including global ones. When programming C++ in space- and runtime-sensitive environments like microcontrollers, extra care should be taken to avoid unwanted side effects of the C++ calling conventions like implied copy constructors that could be called upon function invocation etc. These things could easily add up into a considerable amount of time and program memory wasted. Thus, casual inspection of the generated assembler code (using the \c -S compiler option) seems to be warranted. Back to \ref faq_index. \section faq_varinit Shouldn't I initialize all my variables? Global and static variables are guaranteed to be initialized to 0 by the C standard. \c avr-gcc does this by placing the appropriate code into section \c .init4 (see \ref sec_dot_init). With respect to the standard, this sentence is somewhat simplified (because the standard allows for machines where the actual bit pattern used differs from all bits being 0), but for the AVR target, in general, all integer-type variables are set to 0, all pointers to a NULL pointer, and all floating-point variables to 0.0. As long as these variables are not initialized (i. e. they don't have an equal sign and an initialization expression to the right within the definition of the variable), they go into the \ref sec_dot_bss ".bss" section of the file. This section simply records the size of the variable, but otherwise doesn't consume space, neither within the object file nor within flash memory. (Of course, being a variable, it will consume space in the target's SRAM.) In contrast, global and static variables that have an initializer go into the \ref sec_dot_data ".data" section of the file. This will cause them to consume space in the object file (in order to record the initializing value), \e and in the flash ROM of the target device. The latter is needed since the flash ROM is the only way that the compiler can tell the target device the value this variable is going to be initialized to. Now if some programmer "wants to make doubly sure" their variables really get a 0 at program startup, and adds an initializer just containing 0 on the right-hand side, they waste space. While this waste of space applies to virtually any platform C is implemented on, it's usually not noticeable on larger machines like PCs, while the waste of flash ROM storage can be very painful on a small microcontroller like the AVR. So in general, variables should only be explicitly initialized if the initial value is non-zero. \note Recent versions of GCC are now smart enough to detect this situation, and revert variables that are explicitly initialized to 0 to the .bss section. Still, other compilers might not do that optimization, and as the C standard guarantees the initialization, it is safe to rely on it. Back to \ref faq_index. \section faq_16bitio Why do some 16-bit timer registers sometimes get trashed? Some of the timer-related 16-bit IO registers use a temporary register (called TEMP in the Atmel datasheet) to guarantee an atomic access to the register despite the fact that two separate 8-bit IO transfers are required to actually move the data. Typically, this includes access to the current timer/counter value register (TCNTn), the input capture register (ICRn), and write access to the output compare registers (OCRnM). Refer to the actual datasheet for each device's set of registers that involves the TEMP register. When accessing one of the registers that use TEMP from the main application, and possibly any other one from within an interrupt routine, care must be taken that no access from within an interrupt context could clobber the TEMP register data of an in-progress transaction that has just started elsewhere. To protect interrupt routines against other interrupt routines, it's usually best to use the ISR() macro when declaring the interrupt function, and to ensure that interrupts are still disabled when accessing those 16-bit timer registers. Within the main program, access to those registers could be encapsulated in calls to the cli() and sei() macros. If the status of the global interrupt flag before accessing one of those registers is uncertain, something like the following example code can be used. \code uint16_t read_timer1(void) { uint8_t sreg; uint16_t val; sreg = SREG; cli(); val = TCNT1; SREG = sreg; return val; } \endcode Back to \ref faq_index. \section faq_asmconst How do I use a \#define'd constant in an asm statement? So you tried this: \code asm volatile("sbi 0x18,0x07;"); \endcode Which works. When you do the same thing but replace the address of the port by its macro name, like this: \code asm volatile("sbi PORTB,0x07;"); \endcode you get a compilation error: "Error: constant value required". \c PORTB is a precompiler definition included in the processor specific file included in \c avr/io.h. As you may know, the precompiler will not touch strings and PORTB, instead of 0x18, gets passed to the assembler. One way to avoid this problem is: \code asm volatile("sbi %0, 0x07" : "I" (_SFR_IO_ADDR(PORTB)):); \endcode \note For C programs, rather use the standard C bit operators instead, so the above would be expressed as PORTB |= (1 << 7). The optimizer will take care to transform this into a single SBI instruction, assuming the operands allow for this. Back to \ref faq_index. \section faq_gdboptimize Why does the PC randomly jump around when single-stepping through my program in avr-gdb? When compiling a program with both optimization (\c -O) and debug information (\c -g) which is fortunately possible in \c avr-gcc, the code watched in the debugger is optimized code. While it is not guaranteed, very often this code runs with the exact same optimizations as it would run without the \c -g switch. This can have unwanted side effects. Since the compiler is free to reorder code execution as long as the semantics do not change, code is often rearranged in order to make it possible to use a single branch instruction for conditional operations. Branch instructions can only cover a short range for the target PC (-63 through +64 words from the current PC). If a branch instruction cannot be used directly, the compiler needs to work around it by combining a skip instruction together with a relative jump (\c rjmp) instruction, which will need one additional word of ROM. Another side effect of optimization is that variable usage is restricted to the area of code where it is actually used. So if a variable was placed in a register at the beginning of some function, this same register can be re-used later on if the compiler notices that the first variable is no longer used inside that function, even though the variable is still in lexical scope. When trying to examine the variable in \c avr-gdb, the displayed result will then look garbled. So in order to avoid these side effects, optimization can be turned off while debugging. However, some of these optimizations might also have the side effect of uncovering bugs that would otherwise not be obvious, so it must be noted that turning off optimization can easily change the bug pattern. In most cases, you are better off leaving optimizations enabled while debugging. Back to \ref faq_index. \section faq_asmstabs How do I trace an assembler file in avr-gdb? When using the \c -g compiler option, avr-gcc only generates line number and other debug information for C (and C++) files that pass the compiler. Functions that don't have line number information will be completely skipped by a single \c step command in \c gdb. This includes functions linked from a standard library, but by default also functions defined in an assembler source file, since the \c -g compiler switch does not apply to the assembler. So in order to debug an assembler input file (possibly one that has to be passed through the C preprocessor), it's the assembler that needs to be told to include line-number information into the output file. (Other debug information like data types and variable allocation cannot be generated, since unlike a compiler, the assembler basically doesn't know about this.) This is done using the (GNU) assembler option \c --gstabs. Example: \verbatim $ avr-as -mmcu=atmega128 --gstabs -o foo.o foo.s \endverbatim When the assembler is not called directly but through the C compiler frontend (either implicitly by passing a source file ending in \c .S, or explicitly using -x assembler-with-cpp), the compiler frontend needs to be told to pass the \c --gstabs option down to the assembler. This is done using -Wa,--gstabs. Please take care to \e only pass this option when compiling an assembler input file. Otherwise, the assembler code that results from the C compilation stage will also get line number information, which confuses the debugger. \note You can also use -Wa,-gstabs since the compiler will add the extra \c '-' for you. Example: \verbatim $ EXTRA_OPTS="-Wall -mmcu=atmega128 -x assembler-with-cpp" $ avr-gcc -Wa,--gstabs ${EXTRA_OPTS} -c -o foo.o foo.S \endverbatim Also note that the debugger might get confused when entering a piece of code that has a non-local label before, since it then takes this label as the name of a new function that appears to have been entered. Thus, the best practice to avoid this confusion is to only use non-local labels when declaring a new function, and restrict anything else to local labels. Local labels consist just of a number only. References to these labels consist of the number, followed by the letter \b b for a backward reference, or \b f for a forward reference. These local labels may be re-used within the source file, references will pick the closest label with the same number and given direction. Example: \code myfunc: push r16 push r17 push r18 push YL push YH ... eor r16, r16 ; start loop ldi YL, lo8(sometable) ldi YH, hi8(sometable) rjmp 2f ; jump to loop test at end 1: ld r17, Y+ ; loop continues here ... breq 1f ; return from myfunc prematurely ... inc r16 2: cmp r16, r18 brlo 1b ; jump back to top of loop 1: pop YH pop YL pop r18 pop r17 pop r16 ret \endcode Back to \ref faq_index. \section faq_port_pass How do I pass an IO port as a parameter to a function? Consider this example code: \code #include #include void set_bits_func_wrong (volatile uint8_t port, uint8_t mask) { port |= mask; } void set_bits_func_correct (volatile uint8_t *port, uint8_t mask) { *port |= mask; } #define set_bits_macro(port,mask) ((port) |= (mask)) int main (void) { set_bits_func_wrong (PORTB, 0xaa); set_bits_func_correct (&PORTB, 0x55); set_bits_macro (PORTB, 0xf0); return (0); } \endcode The first function will generate object code which is not even close to what is intended. The major problem arises when the function is called. When the compiler sees this call, it will actually pass the value of the \c PORTB register (using an \c IN instruction), instead of passing the address of \c PORTB (e.g. memory mapped io addr of \c 0x38, io port \c 0x18 for the mega128). This is seen clearly when looking at the disassembly of the call: \verbatim set_bits_func_wrong (PORTB, 0xaa); 10a: 6a ea ldi r22, 0xAA ; 170 10c: 88 b3 in r24, 0x18 ; 24 10e: 0e 94 65 00 call 0xca \endverbatim So, the function, once called, only sees the value of the port register and knows nothing about which port it came from. At this point, whatever object code is generated for the function by the compiler is irrelevant. The interested reader can examine the full disassembly to see that the function's body is completely fubar. The second function shows how to pass (by reference) the memory mapped address of the io port to the function so that you can read and write to it in the function. Here's the object code generated for the function call: \verbatim set_bits_func_correct (&PORTB, 0x55); 112: 65 e5 ldi r22, 0x55 ; 85 114: 88 e3 ldi r24, 0x38 ; 56 116: 90 e0 ldi r25, 0x00 ; 0 118: 0e 94 7c 00 call 0xf8 \endverbatim You can clearly see that \c 0x0038 is correctly passed for the address of the io port. Looking at the disassembled object code for the body of the function, we can see that the function is indeed performing the operation we intended: \verbatim void set_bits_func_correct (volatile uint8_t *port, uint8_t mask) { f8: fc 01 movw r30, r24 *port |= mask; fa: 80 81 ld r24, Z fc: 86 2b or r24, r22 fe: 80 83 st Z, r24 } 100: 08 95 ret \endverbatim Notice that we are accessing the io port via the \c LD and \c ST instructions. The \c port parameter must be volatile to avoid a compiler warning. \note Because of the nature of the \c IN and \c OUT assembly instructions, they can not be used inside the function when passing the port in this way. Readers interested in the details should consult the Instruction Set datasheet. Finally we come to the macro version of the operation. In this contrived example, the macro is the most efficient method with respect to both execution speed and code size: \verbatim set_bits_macro (PORTB, 0xf0); 11c: 88 b3 in r24, 0x18 ; 24 11e: 80 6f ori r24, 0xF0 ; 240 120: 88 bb out 0x18, r24 ; 24 \endverbatim Of course, in a real application, you might be doing a lot more in your function which uses a passed by reference io port address and thus the use of a function over a macro could save you some code space, but still at a cost of execution speed. Care should be taken when such an indirect port access is going to one of the 16-bit IO registers where the order of write access is critical (like some timer registers). All versions of avr-gcc up to 3.3 will generate instructions that use the wrong access order in this situation (since with normal memory operands where the order doesn't matter, this sometimes yields shorter code). See http://mail.nongnu.org/archive/html/avr-libc-dev/2003-01/msg00044.html for a possible workaround. avr-gcc versions after 3.3 have been fixed in a way where this optimization will be disabled if the respective pointer variable is declared to be \c volatile, so the correct behaviour for 16-bit IO ports can be forced that way. Back to \ref faq_index. \section faq_reg_usage What registers are used by the C compiler? - Data types:
\c char is 8 bits, \c int is 16 bits, \c long is 32 bits, \c long long is 64 bits, \c float and \c double are 32 bits (this is the only supported floating point format), pointers are 16 bits (function pointers are word addresses, to allow addressing up to 128K program memory space). There is a \c -mint8 option (see \ref using_avr_gcc) to make \c int 8 bits, but that is not supported by avr-libc and violates C standards (\c int \e must be at least 16 bits). It may be removed in a future release. - Call-used registers (r18-r27, r30-r31):
May be allocated by gcc for local data. You \e may use them freely in assembler subroutines. Calling C subroutines can clobber any of them - the caller is responsible for saving and restoring. - Call-saved registers (r2-r17, r28-r29):
May be allocated by gcc for local data. Calling C subroutines leaves them unchanged. Assembler subroutines are responsible for saving and restoring these registers, if changed. r29:r28 (Y pointer) is used as a frame pointer (points to local data on stack) if necessary. The requirement for the callee to save/preserve the contents of these registers even applies in situations where the compiler assigns them for argument passing. - Fixed registers (r0, r1):
Never allocated by gcc for local data, but often used for fixed purposes:

r0 - temporary register, can be clobbered by any C code (except interrupt handlers which save it), \e may be used to remember something for a while within one piece of assembler code

r1 - assumed to be always zero in any C code, \e may be used to remember something for a while within one piece of assembler code, but \e must then be cleared after use (clr r1). This includes any use of the [f]mul[s[u]] instructions, which return their result in r1:r0. Interrupt handlers save and clear r1 on entry, and restore r1 on exit (in case it was non-zero).

- Function call conventions:
Arguments - allocated left to right, r25 to r8. All arguments are aligned to start in even-numbered registers (odd-sized arguments, including \c char, have one free register above them). This allows making better use of the \c movw instruction on the enhanced core.

If too many, those that don't fit are passed on the stack.

Return values: 8-bit in r24 (not r25!), 16-bit in r25:r24, up to 32 bits in r22-r25, up to 64 bits in r18-r25. 8-bit return values are zero/sign-extended to 16 bits by the called function (unsigned char is more efficient than signed char - just clr r25). Arguments to functions with variable argument lists (printf etc.) are all passed on stack, and \c char is extended to \c int.

\warning There was no such alignment before 2000-07-01, including the old patches for gcc-2.95.2. Check your old assembler subroutines, and adjust them accordingly. Back to \ref faq_index. \section faq_rom_array How do I put an array of strings completely in ROM? There are times when you may need an array of strings which will never be modified. In this case, you don't want to waste ram storing the constant strings. The most obvious (and incorrect) thing to do is this: \code #include PGM_P array[2] PROGMEM = { "Foo", "Bar" }; int main (void) { char buf[32]; strcpy_P (buf, array[1]); return 0; } \endcode The result is not what you want though. What you end up with is the array stored in ROM, while the individual strings end up in RAM (in the \c .data section). To work around this, you need to do something like this: \code #include const char foo[] PROGMEM = "Foo"; const char bar[] PROGMEM = "Bar"; PGM_P array[2] PROGMEM = { foo, bar }; int main (void) { char buf[32]; PGM_P p; int i; memcpy_P(&p, &array[i], sizeof(PGM_P)); strcpy_P(buf, p); return 0; } \endcode Looking at the disassembly of the resulting object file we see that array is in flash as such: \code 00000026 : 26: 2e 00 .word 0x002e ; ???? 28: 2a 00 .word 0x002a ; ???? 0000002a : 2a: 42 61 72 00 Bar. 0000002e : 2e: 46 6f 6f 00 Foo. \endcode \c foo is at addr 0x002e.
\c bar is at addr 0x002a.
\c array is at addr 0x0026.
Then in main we see this: \code memcpy_P(&p, &array[i], sizeof(PGM_P)); 70: 66 0f add r22, r22 72: 77 1f adc r23, r23 74: 6a 5d subi r22, 0xDA ; 218 76: 7f 4f sbci r23, 0xFF ; 255 78: 42 e0 ldi r20, 0x02 ; 2 7a: 50 e0 ldi r21, 0x00 ; 0 7c: ce 01 movw r24, r28 7e: 81 96 adiw r24, 0x21 ; 33 80: 08 d0 rcall .+16 ; 0x92 \endcode This code reads the pointer to the desired string from the ROM table \c array into a register pair. The value of \c i (in r22:r23) is doubled to accommodate for the word offset required to access array[], then the address of array (0x26) is added, by subtracting the negated address (0xffda). The address of variable \c p is computed by adding its offset within the stack frame (33) to the Y pointer register, and memcpy_P is called. \code strcpy_P(buf, p); 82: 69 a1 ldd r22, Y+33 ; 0x21 84: 7a a1 ldd r23, Y+34 ; 0x22 86: ce 01 movw r24, r28 88: 01 96 adiw r24, 0x01 ; 1 8a: 0c d0 rcall .+24 ; 0xa4 \endcode This will finally copy the ROM string into the local buffer \c buf. Variable \c p (located at Y+33) is read, and passed together with the address of buf (Y+1) to strcpy_P. This will copy the string from ROM to \c buf. Note that when using a compile-time constant index, omitting the first step (reading the pointer from ROM via memcpy_P) usually remains unnoticed, since the compiler would then optimize the code for accessing \c array at compile-time. Back to \ref faq_index. \section faq_ext_ram How to use external RAM? Well, there is no universal answer to this question; it depends on what the external RAM is going to be used for. Basically, the bit \c SRE (SRAM enable) in the \c MCUCR register needs to be set in order to enable the external memory interface. Depending on the device to be used, and the application details, further registers affecting the external memory operation like \c XMCRA and \c XMCRB, and/or further bits in \c MCUCR might be configured. Refer to the datasheet for details. If the external RAM is going to be used to store the variables from the C program (i. e., the \c .data and/or \c .bss segment) in that memory area, it is essential to set up the external memory interface early during the \ref sec_dot_init "device initialization" so the initialization of these variable will take place. Refer to \ref faq_startup for a description how to do this using few lines of assembler code, or to the chapter about memory sections for an \ref c_sections "example written in C". The explanation of malloc() contains a \ref malloc_where "discussion" about the use of internal RAM vs. external RAM in particular with respect to the various possible locations of the \e heap (area reserved for malloc()). It also explains the linker command-line options that are required to move the memory regions away from their respective standard locations in internal RAM. Finally, if the application simply wants to use the additional RAM for private data storage kept outside the domain of the C compiler (e. g. through a char * variable initialized directly to a particular address), it would be sufficient to defer the initialization of the external RAM interface to the beginning of main(), so no tweaking of the \c .init3 section is necessary. The same applies if only the heap is going to be located there, since the application start-up code does not affect the heap. It is not recommended to locate the stack in external RAM. In general, accessing external RAM is slower than internal RAM, and errata of some AVR devices even prevent this configuration from working properly at all. Back to \ref faq_index. \section faq_optflags Which -O flag to use? There's a common misconception that larger numbers behind the \c -O option might automatically cause "better" optimization. First, there's no universal definition for "better", with optimization often being a speed vs. code size trade off. See the \ref gcc_optO "detailed discussion" for which option affects which part of the code generation. A test case was run on an ATmega128 to judge the effect of compiling the library itself using different optimization levels. The following table lists the results. The test case consisted of around 2 KB of strings to sort. Test \#1 used qsort() using the standard library strcmp(), test \#2 used a function that sorted the strings by their size (thus had two calls to strlen() per invocation). When comparing the resulting code size, it should be noted that a floating point version of fvprintf() was linked into the binary (in order to print out the time elapsed) which is entirely not affected by the different optimization levels, and added about 2.5 KB to the code.
Optimization flags Size of .text Time for test \#1 Time for test \#2
-O3 6898 903 µs 19.7 ms
-O2 6666 972 µs 20.1 ms
-Os 6618 955 µs 20.1 ms
-Os -mcall-prologues 6474 972 µs 20.1 ms
(The difference between 955 µs and 972 µs was just a single timer-tick, so take this with a grain of salt.) So generally, it seems -Os -mcall-prologues is the most universal "best" optimization level. Only applications that need to get the last few percent of speed benefit from using \c -O3. Back to \ref faq_index. \section faq_reloc_code How do I relocate code to a fixed address? First, the code should be put into a new \ref mem_sections "named section". This is done with a section attribute: \code __attribute__ ((section (".bootloader"))) \endcode In this example, \c .bootloader is the name of the new section. This attribute needs to be placed after the prototype of any function to force the function into the new section. \code void boot(void) __attribute__ ((section (".bootloader"))); \endcode To relocate the section to a fixed address the linker flag \c --section-start is used. This option can be passed to the linker using the \ref gcc_minusW "-Wl compiler option": \code -Wl,--section-start=.bootloader=0x1E000 \endcode The name after section-start is the name of the section to be relocated. The number after the section name is the beginning address of the named section. Back to \ref faq_index. \section faq_fuses My UART is generating nonsense! My ATmega128 keeps crashing! Port F is completely broken! Well, certain odd problems arise out of the situation that the AVR devices as shipped by Atmel often come with a default fuse bit configuration that doesn't match the user's expectations. Here is a list of things to care for: - All devices that have an internal RC oscillator ship with the fuse enabled that causes the device to run off this oscillator, instead of an external crystal. This often remains unnoticed until the first attempt is made to use something critical in timing, like UART communication. - The ATmega128 ships with the fuse enabled that turns this device into ATmega103 compatibility mode. This means that some ports are not fully usable, and in particular that the internal SRAM is located at lower addresses. Since by default, the stack is located at the top of internal SRAM, a program compiled for an ATmega128 running on such a device will immediately crash upon the first function call (or rather, upon the first function return). - Devices with a JTAG interface have the \c JTAGEN fuse programmed by default. This will make the respective port pins that are used for the JTAG interface unavailable for regular IO. Back to \ref faq_index. \section faq_flashstrings Why do all my "foo...bar" strings eat up the SRAM? By default, all strings are handled as all other initialized variables: they occupy RAM (even though the compiler might warn you when it detects write attempts to these RAM locations), and occupy the same amount of flash ROM so they can be initialized to the actual string by startup code. The compiler can optimize multiple identical strings into a single one, but obviously only for one compilation unit (i. e., a single C source file). That way, any string literal will be a valid argument to any C function that expects a const char * argument. Of course, this is going to waste a lot of SRAM. In \ref avr_pgmspace "Program Space String Utilities", a method is described how such constant data can be moved out to flash ROM. However, a constant string located in flash ROM is no longer a valid argument to pass to a function that expects a const char *-type string, since the AVR processor needs the special instruction \c LPM to access these strings. Thus, separate functions are needed that take this into account. Many of the standard C library functions have equivalents available where one of the string arguments can be located in flash ROM. Private functions in the applications need to handle this, too. For example, the following can be used to implement simple debugging messages that will be sent through a UART: \code #include #include #include int uart_putchar(char c) { if (c == '\n') uart_putchar('\r'); loop_until_bit_is_set(USR, UDRE); UDR = c; return 0; /* so it could be used for fdevopen(), too */ } void debug_P(const char *addr) { char c; while ((c = pgm_read_byte(addr++))) uart_putchar(c); } int main(void) { ioinit(); /* initialize UART, ... */ debug_P(PSTR("foo was here\n")); return 0; } \endcode \note By convention, the suffix \b _P to the function name is used as an indication that this function is going to accept a "program-space string". Note also the use of the PSTR() macro. Back to \ref faq_index. \section faq_intpromote Why does the compiler compile an 8-bit operation that uses bitwise operators into a 16-bit operation in assembly? Bitwise operations in Standard C will automatically promote their operands to an int, which is (by default) 16 bits in avr-gcc. To work around this use typecasts on the operands, including literals, to declare that the values are to be 8 bit operands. This may be especially important when clearing a bit: \code var &= ~mask; /* wrong way! */ \endcode The bitwise "not" operator (\c ~) will also promote the value in \c mask to an int. To keep it an 8-bit value, typecast before the "not" operator: \code var &= (unsigned char)~mask; \endcode Back to \ref faq_index. \section faq_ramoverlap How to detect RAM memory and variable overlap problems? You can simply run avr-nm on your output (ELF) file. Run it with the -n option, and it will sort the symbols numerically (by default, they are sorted alphabetically). Look for the symbol \c _end, that's the first address in RAM that is not allocated by a variable. (avr-gcc internally adds 0x800000 to all data/bss variable addresses, so please ignore this offset.) Then, the run-time initialization code initializes the stack pointer (by default) to point to the last available address in (internal) SRAM. Thus, the region between \c _end and the end of SRAM is what is available for stack. (If your application uses malloc(), which e. g. also can happen inside printf(), the heap for dynamic memory is also located there. See \ref malloc.) The amount of stack required for your application cannot be determined that easily. For example, if you recursively call a function and forget to break that recursion, the amount of stack required is infinite. :-) You can look at the generated assembler code (avr-gcc ... -S), there's a comment in each generated assembler file that tells you the frame size for each generated function. That's the amount of stack required for this function, you have to add up that for all functions where you know that the calls could be nested. Back to \ref faq_index. \section faq_tinyavr_c Is it really impossible to program the ATtinyXX in C? While some small AVRs are not directly supported by the C compiler since they do not have a RAM-based stack (and some do not even have RAM at all), it is possible anyway to use the general-purpose registers as a RAM replacement since they are mapped into the data memory region. Bruce D. Lightner wrote an excellent description of how to do this, and offers this together with a toolkit on his web page: http://lightner.net/avr/ATtinyAvrGcc.html Back to \ref faq_index. \section faq_clockskew What is this "clock skew detected" message? It's a known problem of the MS-DOS FAT file system. Since the FAT file system has only a granularity of 2 seconds for maintaining a file's timestamp, and it seems that some MS-DOS derivative (Win9x) perhaps rounds up the current time to the next second when calculating the timestamp of an updated file in case the current time cannot be represented in FAT's terms, this causes a situation where \c make sees a "file coming from the future". Since all make decisions are based on file timestamps, and their dependencies, make warns about this situation. Solution: don't use inferior file systems / operating systems. Neither Unix file systems nor HPFS (aka NTFS) do experience that problem. Workaround: after saving the file, wait a second before starting \c make. Or simply ignore the warning. If you are paranoid, execute a make clean all to make sure everything gets rebuilt. In networked environments where the files are accessed from a file server, this message can also happen if the file server's clock differs too much from the network client's clock. In this case, the solution is to use a proper time keeping protocol on both systems, like NTP. As a workaround, synchronize the client's clock frequently with the server's clock. Back to \ref faq_index. \section faq_intbits Why are (many) interrupt flags cleared by writing a logical 1? Usually, each interrupt has its own interrupt flag bit in some control register, indicating the specified interrupt condition has been met by representing a logical 1 in the respective bit position. When working with interrupt handlers, this interrupt flag bit usually gets cleared automatically in the course of processing the interrupt, sometimes by just calling the handler at all, sometimes (e. g. for the U[S]ART) by reading a particular hardware register that will normally happen anyway when processing the interrupt. From the hardware's point of view, an interrupt is asserted as long as the respective bit is set, while global interrupts are enabled. Thus, it is essential to have the bit cleared before interrupts get re-enabled again (which usually happens when returning from an interrupt handler). Only few subsystems require an explicit action to clear the interrupt request when using interrupt handlers. (The notable exception is the TWI interface, where clearing the interrupt indicates to proceed with the TWI bus hardware handshake, so it's never done automatically.) However, if no normal interrupt handlers are to be used, or in order to make extra sure any pending interrupt gets cleared before re-activating global interrupts (e. g. an external edge-triggered one), it can be necessary to explicitly clear the respective hardware interrupt bit by software. This is usually done by writing a logical 1 into this bit position. This seems to be illogical at first, the bit position already carries a logical 1 when reading it, so why does writing a logical 1 to it clear the interrupt bit? The solution is simple: writing a logical 1 to it requires only a single \c OUT instruction, and it is clear that only this single interrupt request bit will be cleared. There is no need to perform a read-modify-write cycle (like, an \c SBI instruction), since all bits in these control registers are interrupt bits, and writing a logical 0 to the remaining bits (as it is done by the simple \c OUT instruction) will not alter them, so there is no risk of any race condition that might accidentally clear another interrupt request bit. So instead of writing \code TIFR |= _BV(TOV0); /* wrong! */ \endcode simply use \code TIFR = _BV(TOV0); \endcode Back to \ref faq_index. \section faq_fuselow Why have "programmed" fuses the bit value 0? Basically, fuses are just a bit in a special EEPROM area. For technical reasons, erased E[E]PROM cells have all bits set to the value 1, so unprogrammed fuses also have a logical 1. Conversely, programmed fuse cells read out as bit value 0. Back to \ref faq_index. \section faq_asmops Which AVR-specific assembler operators are available? See \ref ass_pseudoops. Back to \ref faq_index. \section faq_spman Why are interrupts re-enabled in the middle of writing the stack pointer? When setting up space for local variables on the stack, the compiler generates code like this: \code /* prologue: frame size=20 */ push r28 push r29 in r28,__SP_L__ in r29,__SP_H__ sbiw r28,20 in __tmp_reg__,__SREG__ cli out __SP_H__,r29 out __SREG__,__tmp_reg__ out __SP_L__,r28 /* prologue end (size=10) */ \endcode It reads the current stack pointer value, decrements it by the required amount of bytes, then disables interrupts, writes back the high part of the stack pointer, writes back the saved \c SREG (which will eventually re-enable interrupts if they have been enabled before), and finally writes the low part of the stack pointer. At the first glance, there's a race between restoring \c SREG, and writing \c SPL. However, after enabling interrupts (either explicitly by setting the \c I flag, or by restoring it as part of the entire \c SREG), the AVR hardware executes (at least) the next instruction still with interrupts disabled, so the write to \c SPL is guaranteed to be executed with interrupts disabled still. Thus, the emitted sequence ensures interrupts will be disabled only for the minimum time required to guarantee the integrity of this operation. Back to \ref faq_index. \section faq_linkerscripts Why are there five different linker scripts? From a comment in the source code: Which one of the five linker script files is actually used depends on command line options given to ld. A .x script file is the default script A .xr script is for linking without relocation (-r flag) A .xu script is like .xr but *do* create constructors (-Ur flag) A .xn script is for linking with -n flag (mix text and data on same page). A .xbn script is for linking with -N flag (mix text and data on same page). Back to \ref faq_index. \section faq_binarydata How to add a raw binary image to linker output? The GNU linker avr-ld cannot handle binary data directly. However, there's a companion tool called avr-objcopy. This is already known from the output side: it's used to extract the contents of the linked ELF file into an Intel Hex load file. avr-objcopy can create a relocatable object file from arbitrary binary input, like \code avr-objcopy -I binary -O elf32-avr foo.bin foo.o \endcode This will create a file named foo.o, with the contents of foo.bin. The contents will default to section .data, and two symbols will be created named \c _binary_foo_bin_start and \c _binary_foo_bin_end. These symbols can be referred to inside a C source to access these data. If the goal is to have those data go to flash ROM (similar to having used the PROGMEM attribute in C source code), the sections have to be renamed while copying, and it's also useful to set the section flags: \code avr-objcopy --rename-section .data=.progmem.data,contents,alloc,load,readonly,data -I binary -O elf32-avr foo.bin foo.o \endcode Note that all this could be conveniently wired into a Makefile, so whenever foo.bin changes, it will trigger the recreation of foo.o, and a subsequent relink of the final ELF file. Below are two Makefile fragments that provide rules to convert a .txt file to an object file, and to convert a .bin file to an object file: \code $(OBJDIR)/%.o : %.txt @echo Converting $< @cp $(<) $(*).tmp @echo -n 0 | tr 0 '\000' >> $(*).tmp @$(OBJCOPY) -I binary -O elf32-avr \ --rename-section .data=.progmem.data,contents,alloc,load,readonly,data \ --redefine-sym _binary_$*_tmp_start=$* \ --redefine-sym _binary_$*_tmp_end=$*_end \ --redefine-sym _binary_$*_tmp_size=$*_size_sym \ $(*).tmp $(@) @echo "extern const char" $(*)"[] PROGMEM;" > $(*).h @echo "extern const char" $(*)_end"[] PROGMEM;" >> $(*).h @echo "extern const char" $(*)_size_sym"[];" >> $(*).h @echo "#define $(*)_size ((int)$(*)_size_sym)" >> $(*).h @rm $(*).tmp $(OBJDIR)/%.o : %.bin @echo Converting $< @$(OBJCOPY) -I binary -O elf32-avr \ --rename-section .data=.progmem.data,contents,alloc,load,readonly,data \ --redefine-sym _binary_$*_bin_start=$* \ --redefine-sym _binary_$*_bin_end=$*_end \ --redefine-sym _binary_$*_bin_size=$*_size_sym \ $(<) $(@) @echo "extern const char" $(*)"[] PROGMEM;" > $(*).h @echo "extern const char" $(*)_end"[] PROGMEM;" >> $(*).h @echo "extern const char" $(*)_size_sym"[];" >> $(*).h @echo "#define $(*)_size ((int)$(*)_size_sym)" >> $(*).h \endcode Back to \ref faq_index. \section faq_softreset How do I perform a software reset of the AVR? The canonical way to perform a software reset of non-XMega AVR's is to use the watchdog timer. Enable the watchdog timer to the shortest timeout setting, then go into an infinite, do-nothing loop. The watchdog will then reset the processor. XMega parts have a specific bit RST_SWRST_bm in the RST.CTRL register, that generates a hardware reset. RST_SWRST_bm is protected by the XMega Configuration Change Protection system. The reason why using the watchdog timer or RST_SWRST_bm is preferable over jumping to the reset vector, is that when the watchdog or RST_SWRST_bm resets the AVR, the registers will be reset to their known, default settings. Whereas jumping to the reset vector will leave the registers in their previous state, which is generally not a good idea. CAUTION! Older AVRs will have the watchdog timer disabled on a reset. For these older AVRs, doing a soft reset by enabling the watchdog is easy, as the watchdog will then be disabled after the reset. On newer AVRs, once the watchdog is enabled, then it stays enabled, even after a reset! For these newer AVRs a function needs to be added to the .init3 section (i.e. during the startup code, before main()) to disable the watchdog early enough so it does not continually reset the AVR. Here is some example code that creates a macro that can be called to perform a soft reset: \code #include ... #define soft_reset() \ do \ { \ wdt_enable(WDTO_15MS); \ for(;;) \ { \ } \ } while(0) \endcode For newer AVRs (such as the ATmega1281) also add this function to your code to then disable the watchdog after a reset (e.g., after a soft reset): \code #include ... // Function Pototype void wdt_init(void) __attribute__((naked)) __attribute__((section(".init3"))); ... // Function Implementation void wdt_init(void) { MCUSR = 0; wdt_disable(); return; } \endcode Back to \ref faq_index. \section faq_math I am using floating point math. Why is the compiled code so big? Why does my code not work? You are not linking in the math library from AVR-LibC. GCC has a library that is used for floating point operations, but it is not optimized for the AVR, and so it generates big code, or it could be incorrect. This can happen even when you are not using any floating point math functions from the Standard C library, but you are just doing floating point math operations. When you link in the math library from AVR-LibC, those routines get replaced by hand-optimized AVR assembly and it produces much smaller code. See \ref faq_libm for more details on how to link in the math library. Back to \ref faq_index. \section faq_reentrant What pitfalls exist when writing reentrant code? Reentrant code means the ability for a piece of code to be called simultaneously from two or more threads. Attention to re-enterability is needed when using a multi-tasking operating system, or when using interrupts since an interrupt is really a temporary thread. The code generated natively by gcc is reentrant. But, only some of the libraries in avr-libc are explicitly reentrant, and some are known not to be reentrant. In general, any library call that reads and writes global variables (including I/O registers) is not reentrant. This is because more than one thread could read or write the same storage at the same time, unaware that other threads are doing the same, and create inconsistent and/or erroneous results. A library call that is known not to be reentrant will work if it is used only within one thread and no other thread makes use of a library call that shares common storage with it. Below is a table of library calls with known issues.
Library call Reentrant Issue Workaround/Alternative
rand(), random() Uses global variables to keep state information. Use special reentrant versions: rand_r(), random_r().
strtod(), strtol(), strtoul() Uses the global variable \c errno to return success/failure. Ignore \c errno, or protect calls with cli()/sei() or ATOMIC_BLOCK() if the application can tolerate it. Or use sccanf() or sccanf_P() if possible.
malloc(), realloc(), calloc(), free() Uses the stack pointer and global variables to allocate and free memory. Protect calls with cli()/sei() or ATOMIC_BLOCK() if the application can tolerate it. If using an OS, use the OS provided memory allocator since the OS is likely modifying the stack pointer anyway.
fdevopen(), fclose() Uses calloc() and free(). Protect calls with cli()/sei() or ATOMIC_BLOCK() if the application can tolerate it. Or use fdev_setup_stream() or FDEV_SETUP_STREAM().
Note: fclose() will only call free() if the stream has been opened with fdevopen().
eeprom_*(), boot_*() Accesses I/O registers. Protect calls with cli()/sei(), ATOMIC_BLOCK(), or use OS locking.
pgm_*_far() Accesses I/O register RAMPZ. Starting with GCC 4.3, RAMPZ is automatically saved for ISRs, so nothing further is needed if only using interrupts.
Some OSes may automatically preserve RAMPZ during context switching. Check the OS documentation before assuming it does.
Otherwise, protect calls with cli()/sei(), ATOMIC_BLOCK(), or use explicit OS locking.
printf(), printf_P(), vprintf(), vprintf_P(), puts(), puts_P() Alters flags and character count in global FILE \c stdout. Use only in one thread. Or if returned character count is unimportant, do not use the *_P versions.
Note: Formatting to a string output, e.g. sprintf(), sprintf_P(), snprintf(), snprintf_P(), vsprintf(), vsprintf_P(), vsnprintf(), vsnprintf_P(), is thread safe. The formatted string could then be followed by an fwrite() which simply calls the lower layer to send the string.
fprintf(), fprintf_P(), vfprintf(), vfprintf_P(), fputs(), fputs_P() Alters flags and character count in the FILE argument. Problems can occur if a global FILE is used from multiple threads. Assign each thread its own FILE for output. Or if returned character count is unimportant, do not use the *_P versions.
assert() Contains an embedded fprintf(). See above for fprintf(). See above for fprintf().
clearerr() Alters flags in the FILE argument. Assign each thread its own FILE for output.
getchar(), gets() Alters flags, character count, and unget buffer in global FILE \c stdin. Use only in one thread. ***
fgetc(), ungetc(), fgets(), scanf(), scanf_P(), fscanf(), fscanf_P(), vscanf(), vfscanf(), vfscanf_P(), fread() Alters flags, character count, and unget buffer in the FILE argument. Assign each thread its own FILE for input. ***
Note: Scanning from a string, e.g. sscanf() and sscanf_P(), are thread safe.
\note It's not clear one would ever want to do character input simultaneously from more than one thread anyway, but these entries are included for completeness. An effort will be made to keep this table up to date if any new issues are discovered or introduced. Back to \ref faq_index. \section faq_eeprom_corruption Why are some addresses of the EEPROM corrupted (usually address zero)? The two most common reason for EEPROM corruption is either writing to the EEPROM beyond the datasheet endurance specification, or resetting the AVR while an EEPROM write is in progress. EEPROM writes can take up to tens of milliseconds to complete. So that the CPU is not tied up for that long of time, an internal state-machine handles EEPROM write requests. The EEPROM state-machine expects to have all of the EEPROM registers setup, then an EEPROM write request to start the process. Once the EEPROM state-machine has started, changing EEPROM related registers during an EEPROM write is guaranteed to corrupt the EEPROM write process. The datasheet always shows the proper way to tell when a write is in progress, so that the registers are not changed by the user's program. The EEPROM state-machine will \b always complete the write in progress unless power is removed from the device. As with all EEPROM technology, if power fails during an EEPROM write the state of the byte being written is undefined. In older generation AVRs the EEPROM Address Register (EEAR) is initialized to zero on reset, be it from Brown Out Detect, Watchdog or the Reset Pin. If an EEPROM write has just started at the time of the reset, the write will be completed, but now at address zero instead of the requested address. If the reset occurs later in the write process both the requested address and address zero may be corrupted. To distinguish which AVRs may exhibit the corrupt of address zero while a write is in process during a reset, look at the "initial value" section for the EEPROM Address Register. If EEAR shows the initial value as 0x00 or 0x0000, then address zero and possibly the one being written will be corrupted. Newer parts show the initial value as "undefined", these will not corrupt address zero during a reset (unless it was address zero that was being written). EEPROMs have limited write endurance. The datasheet specifies the number of EEPROM writes that are guaranteed to function across the full temperature specification of the AVR, for a given byte. A read should always be performed before a write, to see if the value in the EEPROM actually needs to be written, so not to cause unnecessary EEPROM wear. The failure mechanism for an overwritten byte is generally one of "stuck" bits, i. e. a bit will stay at a one or zero state regardless of the byte written. Also a write followed by a read may return the correct data, but the data will change with the passage of time, due the EEPROM's inability to hold a charge from the excessive write wear. Back to \ref faq_index. \section faq_wrong_baud_rate Why is my baud rate wrong? Some AVR datasheets give the following formula for calculating baud rates: \code (F_CPU/(UART_BAUD_RATE*16L)-1) \endcode Unfortunately that formula does not work with all combinations of clock speeds and baud rates due to integer truncation during the division operator. When doing integer division it is usually better to round to the nearest integer, rather than to the lowest. To do this add 0.5 (i. e. half the value of the denominator) to the numerator before the division, resulting in the formula: \code ((F_CPU + UART_BAUD_RATE * 8L) / (UART_BAUD_RATE * 16L) - 1) \endcode This is also the way it is implemented in \ref util_setbaud. Back to \ref faq_index. \section faq_funcptr_gt128kib On a device with more than 128 KiB of flash, how to make function pointers work? Function pointers beyond the "magical" 128 KiB barrier(s) on larger devices are supposed to be resolved through so-called trampolines by the linker, so the actual pointers used in the code can remain 16 bits wide. In order for this to work, the option -mrelax must be given on the compiler command-line that is used to link the final ELF file. (Older compilers did not implement this option for the AVR, use -Wl,--relax instead.) Back to \ref faq_index. \section faq_assign_chain Why is assigning ports in a "chain" a bad idea? Suppose a number of IO port registers should get the value \c 0xff assigned. Conveniently, it is implemented like this: \code DDRB = DDRD = 0xff; \endcode According to the rules of the C language, this causes 0xff to be assigned to \c DDRD, then \c DDRD is read back, and the value is assigned to \c DDRB. The compiler stands no chance to optimize the readback away, as an IO port register is declared "volatile". Thus, chaining that kind of IO port assignments would better be avoided, using explicit assignments instead: \code DDRB = 0xff; DDRD = 0xff; \endcode Even worse ist this, e. g. on an ATmega1281: \code DDRA = DDRB = DDRC = DDRD = DDRE = DDRF = DDRG = 0xff; \endcde The same happens as outlined above. However, when reading back register \c DDRG, this register only implements 6 out of the 8 bits, so the two topmost (unimplemented) bits read back as 0! Consequently, all remaining DDRx registers get assigned the value 0x3f, which does not match the intention of the developer in any way. Back to \ref faq_index. */ avr-libc-1.8.0.orig/doc/api/bench-libc.dox0000644000000000000000000001116711732702554015100 0ustar /* Note: this file has been automatically generated. DO NOT EDIT, or your changes WILL BE LOST! */ /* $Id: bench-libc.dox 1604 2008-02-24 01:27:22Z dmix $ */ /** \page benchmarks \section bench_libc A few of libc functions. Avr-gcc version is 4.2.3 The size of function is given in view of all picked up functions. By default Avr-libc is compiled with \c -mcall-prologues option. In brackets the size without taking into account modules of a prologue and an epilogue is resulted. Both of the size can coincide, if function does not cause a prologue/epilogue.
Function Units Avr2 Avr25 Avr4
atoi ("12345") Flash bytes
Stack bytes
MCU clocks		 82 (82)
2
155		 78 (78)

 74 (74)
2
149
atol ("12345") Flash bytes
Stack bytes
MCU clocks		 122 (122)
2
221		 118 (118)

 118 (118)
2
219
dtostre (1.2345, s, 6, 0) Flash bytes
Stack bytes
MCU clocks		 1184 (1072)
17
1313		 1088 (978)

 1088 (978)
17
1152
dtostrf (1.2345, 15, 6, s) Flash bytes
Stack bytes
MCU clocks		 1676 (1564)
36
1608		 1548 (1438)

 1548 (1438)
36
1443
itoa (12345, s, 10) Flash bytes
Stack bytes
MCU clocks		 150 (150)
4
1172		 134 (134)

 134 (134)
4
1152
ltoa (12345L, s, 10) Flash bytes
Stack bytes
MCU clocks		 220 (220)
9
3174		 200 (200)

 200 (200)
9
3136
malloc (1) Flash bytes
Stack bytes
MCU clocks		 554 (554)
4
196		 506 (506)

 506 (506)
4
178
realloc ((void *)0, 1) Flash bytes
Stack bytes
MCU clocks		 1152 (1040)
20
303		 1042 (932)

 1042 (932)
20
280
qsort (s, sizeof(s), 1, cmp) Flash bytes
Stack bytes
MCU clocks		 1242 (1130)
38
20914		 990 (880)

 1008 (898)
38
16678
sprintf_min (s, "%d", 12345) Flash bytes
Stack bytes
MCU clocks		 1216 (1104)
59
1846		 1090 (980)

 1086 (976)
59
1711
sprintf (s, "%d", 12345) Flash bytes
Stack bytes
MCU clocks		 1674 (1562)
58
1610		 1542 (1432)

 1498 (1388)
58
1528
sprintf_flt (s, "%e", 1.2345) Flash bytes
Stack bytes
MCU clocks		 3334 (3222)
66
2513		 3084 (2974)

 3040 (2930)
66
2297
sscanf_min ("12345", "%d", &i) Flash bytes
Stack bytes
MCU clocks		 1540 (1428)
55
1339		 1354 (1244)

 1354 (1244)
55
1240
sscanf ("12345", "%d", &i) Flash bytes
Stack bytes
MCU clocks		 1950 (1838)
53
1334		 1704 (1594)

 1704 (1594)
53
1235
sscanf ("point,color", "%[a-z]", s) Flash bytes
Stack bytes
MCU clocks		 1950 (1838)
87
2878		 1704 (1594)

 1704 (1594)
87
2718
sscanf_flt ("1.2345", "%e", &x) Flash bytes
Stack bytes
MCU clocks		 3298 (3186)
63
2187		 2934 (2824)

 2918 (2808)
63
1833
strtod ("1.2345", &p) Flash bytes
Stack bytes
MCU clocks		 1570 (1458)
22
1237		 1472 (1362)

 1456 (1346)
22
971
strtol ("12345", &p, 0) Flash bytes
Stack bytes
MCU clocks		 942 (830)
29
1074		 874 (764)

 808 (698)
21
722
*/ avr-libc-1.8.0.orig/doc/api/rel-method.dox0000644000000000000000000001613611732702554015153 0ustar /* Copyright (c) 2003,2005,2007 Theodore Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: rel-method.dox 2196 2010-11-24 03:57:03Z arcanum $ */ /** \page release_method Release Numbering and Methodology \section version_info Release Version Numbering Scheme Release numbers consist of three parts, a major number, a minor number, and a revision number, each separated by a dot. The major number is currently 1 (and has always been). It will only be bumped in case a new version offers a major change in the API that is not backwards compatible. In the past (up to 1.6.x), even minor numbers have been used to indicate "stable" releases, and odd minor numbers have been reserved for development branches/versions. As the latter has never really been used, and maintaining a stable branch that eventually became effectively the same as the development version has proven to be just a cumbersome and tedious job, this scheme has given up in early 2010, so starting with 1.7.0, every minor number will be used. Minor numbers will be bumped upon judgement of the development team, whenever it seems appropriate, but at least in cases where some API was changed. Starting with version 1.4.0, a file indicates the library version of an installed library tree. \section release_info Releasing AVR Libc The information in this section is only relevant to AVR Libc developers and can be ignored by end users. \note In what follows, I assume you know how to use SVN and how to checkout multiple source trees in a single directory without having them clobber each other. If you don't know how to do this, you probably shouldn't be making releases or cutting branches. \subsection release_branch Creating an SVN branch The following steps should be taken to cut a branch in SVN (assuming $username is set to your savannah username): -# Check out a fresh source tree from SVN trunk. -# Update the NEWS file with pending release number and commit to SVN trunk:
Change Changes since avr-libc-\: to Changes in avr-libc-\. -# Set the branch-point tag (setting \ and \ accordingly):
svn copy svn+ssh://$username\@svn.savannah.nongnu.org/avr-libc/trunk svn+ssh://$username\@svn.savannah.nongnu.org/avr-libc/tags/avr-libc-\<major\>_\<minor\>-branchpoint -# Create the branch:
svn copy svn+ssh://$username\@svn.savannah.nongnu.org/avr-libc/trunk svn+ssh://$username\@svn.savannah.nongnu.org/avr-libc/branches/avr-libc-\<major\>_\<minor\>-branch -# Update the package version in configure.ac and commit configure.ac to SVN trunk:
Change minor number to next odd value. -# Update the NEWS file and commit to SVN trunk:
Add Changes since avr-libc-\: -# Check out a new tree for the branch:
svn co svn+ssh://$username\@svn.savannah.nongnu.org/avr-libc/branches/avr-libc-\<major\>_\<minor\>-branch -# Update the package version in configure.ac and commit configure.ac to SVN branch:
Change the patch number to 90 to denote that this now a branch leading up to a release. Be sure to leave the \ part of the version. -# Bring the build system up to date by running bootstrap and configure. -# Perform a 'make distcheck' and make sure it succeeds. This will create the snapshot source tarball. This should be considered the first release candidate. -# Upload the snapshot tarball to savannah. -# Update the bug tracker interface on Savannah: Bugs —> Edit field values —> Release / Fixed Release -# Announce the branch and the branch tag to the avr-libc-dev list so other developers can checkout the branch. \subsection release_rolling Making a release A stable release will only be done on a branch, not from the SVN trunk. The following steps should be taken when making a release: -# Make sure the source tree you are working from is on the correct branch:
svn switch svn+ssh://$username\@svn.savannah.nongnu.org/avr-libc/branches/avr-libc-\<major\>_\<minor\>-branch -# Update the package version in configure.ac and commit it to SVN. -# Update the gnu tool chain version requirements in the README and commit to SVN. -# Update the ChangeLog file to note the release and commit to SVN on the branch:
Add Released avr-libc-\. -# Update the NEWS file with pending release number and commit to SVN:
Change Changes since avr-libc-\: to Changes in avr-libc-\:. -# Bring the build system up to date by running bootstrap and configure. -# Perform a 'make distcheck' and make sure it succeeds. This will create the source tarball. -# Tag the release:
svn copy . svn+ssh://$username\@svn.savannah.nongnu.org/avr-libc/tags/avr-libc-\<major\>_\<minor\>_\<patch\>-release
or
svn copy svn+ssh://$username\@svn.savannah.nongnu.org/avr-libc/branches/avr-libc-\<major\>_\<minor\>-branch svn+ssh://$username\@svn.savannah.nongnu.org/avr-libc/tags/avr-libc-\<major\>_\<minor\>_\<patch\>-release -# Upload the tarball to savannah. -# Update the NEWS file, and commit to SVN:
Add Changes since avr-libc-\_\_\: -# Update the bug tracker interface on Savannah: Bugs —> Edit field values —> Release / Fixed Release -# Generate the latest documentation and upload to savannah. -# Announce the release. The following hypothetical diagram should help clarify version and branch relationships. \image html releases.png "Release tree" \image latex releases.eps "Release tree" width=5in */ avr-libc-1.8.0.orig/doc/api/main_page.dox0000644000000000000000000002434211732702554015031 0ustar /* Copyright (c) 2002, Theodore Roth Copyright (c) 2004,2005,2006,2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: main_page.dox 2211 2011-02-14 14:04:25Z aboyapati $ */ /** \mainpage AVR Libc \section avr_libc_intro Introduction The latest version of this document is always available from http://savannah.nongnu.org/projects/avr-libc/ The AVR Libc package provides a subset of the standard C library for Atmel AVR 8-bit RISC microcontrollers. In addition, the library provides the basic startup code needed by most applications. There is a wealth of information in this document which goes beyond simply describing the interfaces and routines provided by the library. We hope that this document provides enough information to get a new AVR developer up to speed quickly using the freely available development tools: binutils, gcc avr-libc and many others. If you find yourself stuck on a problem which this document doesn't quite address, you may wish to post a message to the avr-gcc mailing list. Most of the developers of the AVR binutils and gcc ports in addition to the devleopers of avr-libc subscribe to the list, so you will usually be able to get your problem resolved. You can subscribe to the list at http://lists.nongnu.org/mailman/listinfo/avr-gcc-list . Before posting to the list, you might want to try reading the \ref FAQ chapter of this document. \note If you think you've found a bug, or have a suggestion for an improvement, either in this documentation or in the library itself, please use the bug tracker at https://savannah.nongnu.org/bugs/?group=avr-libc to ensure the issue won't be forgotten. \section avr_libc_general General information about this library In general, it has been the goal to stick as best as possible to established standards while implementing this library. Commonly, this refers to the C library as described by the ANSI X3.159-1989 and ISO/IEC 9899:1990 ("ANSI-C") standard, as well as parts of their successor ISO/IEC 9899:1999 ("C99"). Some additions have been inspired by other standards like IEEE Std 1003.1-1988 ("POSIX.1"), while other extensions are purely AVR-specific (like the entire program-space string interface). Unless otherwise noted, functions of this library are not guaranteed to be reentrant. In particular, any functions that store local state are known to be non-reentrant, as well as functions that manipulate IO registers like the EEPROM access routines. If these functions are used within both standard and interrupt contexts undefined behaviour will result. See the FAQ for a more detailed discussion. \section supp_devices Supported Devices \addindex supported devices The following is a list of AVR devices currently supported by the library. Note that actual support for some newer devices depends on the ability of the compiler/assembler to support these devices at library compile-time. \par megaAVR Devices: - atmega103 - atmega128 - atmega1280 - atmega1281 - atmega1284p - atmega16 - atmega161 - atmega162 - atmega163 - atmega164a - atmega164p - atmega165 - atmega165a - atmega165p - atmega168 - atmega168a - atmega168p - atmega16a - atmega2560 - atmega2561 - atmega32 - atmega323 - atmega324a - atmega324p - atmega324pa - atmega325 - atmega325a - atmega325p - atmega3250 - atmega3250a - atmega3250p - atmega328 - atmega328p - atmega48 - atmega48a - atmega48p - atmega64 - atmega640 - atmega644 - atmega644a - atmega644p - atmega644pa - atmega645 - atmega645a - atmega645p - atmega6450 - atmega6450a - atmega6450p - atmega8 - atmega88 - atmega88a - atmega88p - atmega88pa - atmega8515 - atmega8535 \par tinyAVR Devices: - attiny4 - attiny5 - attiny10 - attiny11 \ref supp_dev_footnote_one "[1]" - attiny12 \ref supp_dev_footnote_one "[1]" - attiny13 - attiny13a - attiny15 \ref supp_dev_footnote_one "[1]" - attiny20 - attiny22 - attiny24 - attiny24a - attiny25 - attiny26 - attiny261 - attiny261a - attiny28 \ref supp_dev_footnote_one "[1]" - attiny2313 - attiny2313a - attiny40 - attiny4313 - attiny43u - attiny44 - attiny44a - attiny45 - attiny461 - attiny461a - attiny48 - attiny84 - attiny84a - attiny85 - attiny861 - attiny861a - attiny87 - attiny88 \par Automotive AVR Devices: - atmega16m1 - atmega32c1 - atmega32m1 - atmega64c1 - atmega64m1 - attiny167 \par CAN AVR Devices: - at90can32 - at90can64 - at90can128 \par LCD AVR Devices: - atmega169 - atmega169a - atmega169p - atmega169pa - atmega329 - atmega329a - atmega329p - atmega329pa - atmega3290 - atmega3290a - atmega3290p - atmega649 - atmega649a - atmega6490 - atmega6490a - atmega6490p - atmega649p \par Lighting AVR Devices: - at90pwm1 - at90pwm2 - at90pwm2b - at90pwm216 - at90pwm3 - at90pwm3b - at90pwm316 - at90pwm81 \par Smart Battery AVR Devices: - atmega8hva - atmega16hva - atmega16hva2 - atmega16hvb - atmega16hvbrevb - atmega32hvb - atmega32hvbrevb - atmega64hve - atmega406 \par USB AVR Devices: - at90usb82 - at90usb162 - at90usb646 - at90usb647 - at90usb1286 - at90usb1287 - atmega8u2 - atmega16u2 - atmega16u4 - atmega32u2 - atmega32u4 - atmega32u6 \par XMEGA Devices: - atxmega16a4 - atxmega16d4 - atxmega32a4 - atxmega32d4 - atxmega64a1 - atxmega64a1u - atxmega64a3 - atxmega64d3 - atxmega128a1 - atxmega128a1u - atxmega128a3 - atxmega128d3 - atxmega192a3 - atxmega192d3 - atxmega256a3 - atxmega256a3b - atxmega256d3 \par Miscellaneous Devices: - at94K \ref supp_dev_footnote_two "[2]" - at76c711 \ref supp_dev_footnote_three "[3]" - at43usb320 - at43usb355 - at86rf401 - at90scr100 - ata6289 - m3000 \ref supp_dev_footnote_four "[4]" \par Classic AVR Devices: - at90s1200 \ref supp_dev_footnote_one "[1]" - at90s2313 - at90s2323 - at90s2333 - at90s2343 - at90s4414 - at90s4433 - at90s4434 - at90s8515 - at90c8534 - at90s8535 \anchor supp_dev_footnote_one \note [1] Assembly only. There is no direct support for these devices to be programmed in C since they do not have a RAM based stack. Still, it could be possible to program them in C, see the \ref faq_tinyavr_c "FAQ" for an option. \anchor supp_dev_footnote_two \note [2] The at94K devices are a combination of FPGA and AVR microcontroller. [TRoth-2002/11/12: Not sure of the level of support for these. More information would be welcomed.] \anchor supp_dev_footnote_three \note [3] The at76c711 is a USB to fast serial interface bridge chip using an AVR core. \anchor supp_dev_footnote_four \note [4] The m3000 is a motor controller AVR ASIC from Intelligent Motion Systems (IMS) / Schneider Electric. \section license avr-libc License avr-libc can be freely used and redistributed, provided the following license conditions are met. \verbatim Portions of avr-libc are Copyright (c) 1999-2010 Werner Boellmann, Dean Camera, Pieter Conradie, Brian Dean, Keith Gudger, Wouter van Gulik, Bjoern Haase, Steinar Haugen, Peter Jansen, Reinhard Jessich, Magnus Johansson, Harald Kipp, Carlos Lamas, Cliff Lawson, Artur Lipowski, Marek Michalkiewicz, Todd C. Miller, Rich Neswold, Colin O'Flynn, Bob Paddock, Andrey Pashchenko, Reiner Patommel, Florin-Viorel Petrov, Alexander Popov, Michael Rickman, Theodore A. Roth, Juergen Schilling, Philip Soeberg, Anatoly Sokolov, Nils Kristian Strom, Michael Stumpf, Stefan Swanepoel, Helmut Wallner, Eric B. Weddington, Joerg Wunsch, Dmitry Xmelkov, Atmel Corporation, egnite Software GmbH, The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \endverbatim */ avr-libc-1.8.0.orig/doc/api/interrupts.dox0000644000000000000000000002243611732702554015332 0ustar /* Copyright (c) 1999, 2000, 2001, 2002, 2005 Rich Neswold All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: interrupts.dox 1455 2007-10-29 14:01:18Z joerg_wunsch $ */ /** \defgroup avr_interrupts : Interrupts \note This discussion of interrupts was originally taken from Rich Neswold's document. See \ref acks.

Introduction to avr-libc's interrupt handling

It's nearly impossible to find compilers that agree on how to handle interrupt code. Since the C language tries to stay away from machine dependent details, each compiler writer is forced to design their method of support. In the AVR-GCC environment, the vector table is predefined to point to interrupt routines with predetermined names. By using the appropriate name, your routine will be called when the corresponding interrupt occurs. The device library provides a set of default interrupt routines, which will get used if you don't define your own. Patching into the vector table is only one part of the problem. The compiler uses, by convention, a set of registers when it's normally executing compiler-generated code. It's important that these registers, as well as the status register, get saved and restored. The extra code needed to do this is enabled by tagging the interrupt function with __attribute__((signal)). These details seem to make interrupt routines a little messy, but all these details are handled by the Interrupt API. An interrupt routine is defined with ISR(). This macro register and mark the routine as an interrupt handler for the specified peripheral. The following is an example definition of a handler for the ADC interrupt. \code #include ISR(ADC_vect) { // user code here } \endcode Refer to the chapter explaining \ref ass_isr "assembler programming" for an explanation about interrupt routines written solely in assembler language.

Catch-all interrupt vector

If an unexpected interrupt occurs (interrupt is enabled and no handler is installed, which usually indicates a bug), then the default action is to reset the device by jumping to the reset vector. You can override this by supplying a function named \c BADISR_vect which should be defined with ISR() as such. (The name BADISR_vect is actually an alias for __vector_default. The latter must be used inside assembly code in case is not included.) \code #include ISR(BADISR_vect) { // user code here } \endcode

Nested interrupts

The AVR hardware clears the global interrupt flag in SREG before entering an interrupt vector. Thus, normally interrupts will remain disabled inside the handler until the handler exits, where the RETI instruction (that is emitted by the compiler as part of the normal function epilogue for an interrupt handler) will eventually re-enable further interrupts. For that reason, interrupt handlers normally do not nest. For most interrupt handlers, this is the desired behaviour, for some it is even required in order to prevent infinitely recursive interrupts (like UART interrupts, or level-triggered external interrupts). In rare circumstances though it might be desired to re-enable the global interrupt flag as early as possible in the interrupt handler, in order to not defer any other interrupt more than absolutely needed. This could be done using an sei() instruction right at the beginning of the interrupt handler, but this still leaves few instructions inside the compiler-generated function prologue to run with global interrupts disabled. The compiler can be instructed to insert an SEI instruction right at the beginning of an interrupt handler by declaring the handler the following way: \anchor attr_interrupt \code ISR(XXX_vect, ISR_NOBLOCK) { ... } \endcode where \c XXX_vect is the name of a valid interrupt vector for the MCU type in question, as explained below.

Two vectors sharing the same code

In some circumstances, the actions to be taken upon two different interrupts might be completely identical so a single implementation for the ISR would suffice. For example, pin-change interrupts arriving from two different ports could logically signal an event that is independent from the actual port (and thus interrupt vector) where it happened. Sharing interrupt vector code can be accomplished using the ISR_ALIASOF() attribute to the ISR macro: \code ISR(PCINT0_vect) { ... // Code to handle the event. } ISR(PCINT1_vect, ISR_ALIASOF(PCINT0_vect)); \endcode \note There is no body to the aliased ISR. Note that the ISR_ALIASOF() feature requires GCC 4.2 or above (or a patched version of GCC 4.1.x). See the documentation of the ISR_ALIAS() macro for an implementation which is less elegant but could be applied to all compiler versions.

Empty interrupt service routines

In rare circumstances, in interrupt vector does not need any code to be implemented at all. The vector must be declared anyway, so when the interrupt triggers it won't execute the BADISR_vect code (which by default restarts the application). This could for example be the case for interrupts that are solely enabled for the purpose of getting the controller out of sleep_mode(). A handler for such an interrupt vector can be declared using the EMPTY_INTERRUPT() macro: \code EMPTY_INTERRUPT(ADC_vect); \endcode \note There is no body to this macro.

Manually defined ISRs

In some circumstances, the compiler-generated prologue and epilogue of the ISR might not be optimal for the job, and a manually defined ISR could be considered particularly to speedup the interrupt handling. One solution to this could be to implement the entire ISR as manual assembly code in a separate (assembly) file. See \ref asmdemo for an example of how to implement it that way. Another solution is to still implement the ISR in C language but take over the compiler's job of generating the prologue and epilogue. This can be done using the ISR_NAKED attribute to the ISR() macro. Note that the compiler does not generate \e anything as prologue or epilogue, so the final reti() must be provided by the actual implementation. SREG must be manually saved if the ISR code modifies it, and the compiler-implied assumption of \c __zero_reg__ always being 0 could be wrong (e. g. when interrupting right after of a MUL instruction). \code ISR(TIMER1_OVF_vect, ISR_NAKED) { PORTB |= _BV(0); // results in SBI which does not affect SREG reti(); } \endcode

Choosing the vector: Interrupt vector names

The interrupt is chosen by supplying one of the symbols in following table. There are currently two different styles present for naming the vectors. One form uses names starting with \c SIG_, followed by a relatively verbose but arbitrarily chosen name describing the interrupt vector. This has been the only available style in avr-libc up to version 1.2.x. Starting with avr-libc version 1.4.0, a second style of interrupt vector names has been added, where a short phrase for the vector description is followed by \c _vect. The short phrase matches the vector name as described in the datasheet of the respective device (and in Atmel's XML files), with spaces replaced by an underscore and other non-alphanumeric characters dropped. Using the suffix \c _vect is intented to improve portability to other C compilers available for the AVR that use a similar naming convention. The historical naming style might become deprecated in a future release, so it is not recommended for new projects. \note The ISR() macro cannot really spell-check the argument passed to them. Thus, by misspelling one of the names below in a call to ISR(), a function will be created that, while possibly being usable as an interrupt function, is not actually wired into the interrupt vector table. The compiler will generate a warning if it detects a suspiciously looking name of a ISR() function (i.e. one that after macro replacement does not start with "__vector_"). */ avr-libc-1.8.0.orig/doc/api/acknowledge.dox0000644000000000000000000000677511732702554015406 0ustar /* Copyright (c) 2002 Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** \page acks Acknowledgments This document tries to tie together the labors of a large group of people. Without these individuals' efforts, we wouldn't have a terrific, free set of tools to develop AVR projects. We all owe thanks to: - The GCC Team, which produced a very capable set of development tools for an amazing number of platforms and processors. - Denis Chertykov [ denisc@overta.ru ] for making the AVR-specific changes to the GNU tools. - Denis Chertykov and Marek Michalkiewicz [ marekm@linux.org.pl ] for developing the standard libraries and startup code for \b AVR-GCC. - Uros Platise for developing the AVR programmer tool, \b uisp. - Joerg Wunsch [ joerg@FreeBSD.ORG ] for adding all the AVR development tools to the FreeBSD [ http://www.freebsd.org ] ports tree and for providing the basics for the \ref demo_project "demo project". - Brian Dean [ bsd@bsdhome.com ] for developing \b avrdude (an alternative to uisp) and for contributing \ref using_avrprog "documentation" which describes how to use it. \b Avrdude was previously called \b avrprog. - Eric Weddington [ eweddington@cso.atmel.com ] for maintaining the \b WinAVR package and thus making the continued improvements to the open source AVR toolchain available to many users. - Rich Neswold for writing the original avr-tools document (which he graciously allowed to be merged into this document) and his improvements to the \ref demo_project "demo project". - Theodore A. Roth for having been a long-time maintainer of many of the tools (\b AVR-Libc, the AVR port of \b GDB, \b AVaRICE, \b uisp, \b avrdude). - All the people who currently maintain the tools, and/or have submitted suggestions, patches and bug reports. (See the AUTHORS files of the various tools.) - And lastly, all the users who use the software. If nobody used the software, we would probably not be very motivated to continue to develop it. Keep those bug reports coming. ;-) */ avr-libc-1.8.0.orig/doc/api/inline_asm.dox0000644000000000000000000007151211732702554015230 0ustar /* Copyright (c) 2001, 2002, Harald Kipp Copyright (c) 2007 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** \page inline_asm Inline Assembler Cookbook AVR-GCC
Inline Assembler Cookbook About this Document The GNU C compiler for Atmel AVR RISC processors offers, to embed assembly language code into C programs. This cool feature may be used for manually optimizing time critical parts of the software or to use specific processor instruction, which are not available in the C language. Because of a lack of documentation, especially for the AVR version of the compiler, it may take some time to figure out the implementation details by studying the compiler and assembler source code. There are also a few sample programs available in the net. Hopefully this document will help to increase their number. It's assumed, that you are familiar with writing AVR assembler programs, because this is not an AVR assembler programming tutorial. It's not a C language tutorial either. Note that this document does not cover file written completely in assembler language, refer to \ref assembler for this. Copyright (C) 2001-2002 by egnite Software GmbH Permission is granted to copy and distribute verbatim copies of this manual provided that the copyright notice and this permission notice are preserved on all copies. Permission is granted to copy and distribute modified versions of this manual provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one. This document describes version 3.3 of the compiler. There may be some parts, which hadn't been completely understood by the author himself and not all samples had been tested so far. Because the author is German and not familiar with the English language, there are definitely some typos and syntax errors in the text. As a programmer the author knows, that a wrong documentation sometimes might be worse than none. Anyway, he decided to offer his little knowledge to the public, in the hope to get enough response to improve this document. Feel free to contact the author via e-mail. For the latest release check http://www.ethernut.de/. Herne, 17th of May 2002 Harald Kipp harald.kipp-at-egnite.de \note As of 26th of July 2002, this document has been merged into the documentation for avr-libc. The latest version is now available at http://savannah.nongnu.org/projects/avr-libc/. \section gcc_asm GCC asm Statement Let's start with a simple example of reading a value from port D: \code asm("in %0, %1" : "=r" (value) : "I" (_SFR_IO_ADDR(PORTD)) ); \endcode Each \c asm statement is devided by colons into (up to) four parts: -# The assembler instructions, defined as a single string constant: \code "in %0, %1" \endcode -# A list of output operands, separated by commas. Our example uses just one: \code "=r" (value) \endcode -# A comma separated list of input operands. Again our example uses one operand only: \code "I" (_SFR_IO_ADDR(PORTD)) \endcode -# Clobbered registers, left empty in our example. You can write assembler instructions in much the same way as you would write assembler programs. However, registers and constants are used in a different way if they refer to expressions of your C program. The connection between registers and C operands is specified in the second and third part of the asm instruction, the list of input and output operands, respectively. The general form is \code asm(code : output operand list : input operand list [: clobber list]); \endcode In the code section, operands are referenced by a percent sign followed by a single digit. \c %0 refers to the first \c %1 to the second operand and so forth. From the above example: \c %0 refers to "=r" (value) and
\c %1 refers to "I" (_SFR_IO_ADDR(PORTD)). This may still look a little odd now, but the syntax of an operand list will be explained soon. Let us first examine the part of a compiler listing which may have been generated from our example: \code lds r24,value /* #APP */ in r24, 12 /* #NOAPP */ sts value,r24 \endcode The comments have been added by the compiler to inform the assembler that the included code was not generated by the compilation of C statements, but by inline assembler statements. The compiler selected register \c r24 for storage of the value read from PORTD. The compiler could have selected any other register, though. It may not explicitely load or store the value and it may even decide not to include your assembler code at all. All these decisions are part of the compiler's optimization strategy. For example, if you never use the variable value in the remaining part of the C program, the compiler will most likely remove your code unless you switched off optimization. To avoid this, you can add the volatile attribute to the \c asm statement: \code asm volatile("in %0, %1" : "=r" (value) : "I" (_SFR_IO_ADDR(PORTD))); \endcode Alternatively, operands can be given names. The name is prepended in brackets to the constraints in the operand list, and references to the named operand use the bracketed name instead of a number after the % sign. Thus, the above example could also be written as \code asm("in %[retval], %[port]" : [retval] "=r" (value) : [port] "I" (_SFR_IO_ADDR(PORTD)) ); \endcode The last part of the \c asm instruction, the clobber list, is mainly used to tell the compiler about modifications done by the assembler code. This part may be omitted, all other parts are required, but may be left empty. If your assembler routine won't use any input or output operand, two colons must still follow the assembler code string. A good example is a simple statement to disable interrupts: \code asm volatile("cli"::); \endcode \section asm_code Assembler Code You can use the same assembler instruction mnemonics as you'd use with any other AVR assembler. And you can write as many assembler statements into one code string as you like and your flash memory is able to hold. \note The available assembler directives vary from one assembler to another. To make it more readable, you should put each statement on a seperate line: \code asm volatile("nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" ::); \endcode The linefeed and tab characters will make the assembler listing generated by the compiler more readable. It may look a bit odd for the first time, but that's the way the compiler creates it's own assembler code. You may also make use of some special registers.
Symbol Register
__SREG__ Status register at address 0x3F
__SP_H__ Stack pointer high byte at address 0x3E
__SP_L__ Stack pointer low byte at address 0x3D
__tmp_reg__ Register r0, used for temporary storage
__zero_reg__ Register r1, always zero
Register \c r0 may be freely used by your assembler code and need not be restored at the end of your code. It's a good idea to use \c __tmp_reg__ and \c __zero_reg__ instead of \c r0 or \c r1, just in case a new compiler version changes the register usage definitions. \section io_ops Input and Output Operands Each input and output operand is described by a constraint string followed by a C expression in parantheses. AVR-GCC 3.3 knows the following constraint characters: \note The most up-to-date and detailed information on contraints for the avr can be found in the gcc manual. \note The \c x register is \c r27:r26, the \c y register is \c r29:r28, and the \c z register is r31:r30
ConstraintUsed forRange
aSimple upper registersr16 to r23
bBase pointer registers pairsy, z
dUpper registerr16 to r31
ePointer register pairsx, y, z
qStack pointer registerSPH:SPL
rAny registerr0 to r31
tTemporary registerr0
wSpecial upper register pairsr24, r26, r28, r30
xPointer register pair Xx (r27:r26)
yPointer register pair Yy (r29:r28)
zPointer register pair Zz (r31:r30)
GFloating point constant0.0
I6-bit positive integer constant0 to 63
J6-bit negative integer constant-63 to 0
KInteger constant2
LInteger constant0
lLower registersr0 to r15
M8-bit integer constant0 to 255
NInteger constant-1
OInteger constant8, 16, 24
PInteger constant1
Q(GCC >= 4.2.x) A memory address based on Y or Z pointer with displacement. 
R(GCC >= 4.3.x) Integer constant.-6 to 5
The selection of the proper contraint depends on the range of the constants or registers, which must be acceptable to the AVR instruction they are used with. The C compiler doesn't check any line of your assembler code. But it is able to check the constraint against your C expression. However, if you specify the wrong constraints, then the compiler may silently pass wrong code to the assembler. And, of course, the assembler will fail with some cryptic output or internal errors. For example, if you specify the constraint \c "r" and you are using this register with an \c "ori" instruction in your assembler code, then the compiler may select any register. This will fail, if the compiler chooses r2 to \c r15. (It will never choose \c r0 or \c r1, because these are uses for special purposes.) That's why the correct constraint in that case is "d". On the other hand, if you use the constraint "M", the compiler will make sure that you don't pass anything else but an 8-bit value. Later on we will see how to pass multibyte expression results to the assembler code. The following table shows all AVR assembler mnemonics which require operands, and the related contraints. Because of the improper constraint definitions in version 3.3, they aren't strict enough. There is, for example, no constraint, which restricts integer constants to the range 0 to 7 for bit set and bit clear operations.
Mnemonic Constraints Mnemonic Constraints
adc r,r add r,r
adiw w,I and r,r
andi d,M asr r
bclr I bld r,I
brbc I,label brbs I,label
bset I bst r,I
cbi I,I cbr d,I
com r cp r,r
cpc r,r cpi d,M
cpse r,r dec r
elpm t,z eor r,r
in r,I inc r
ld r,e ldd r,b
ldi d,M lds r,label
lpm t,z lsl r
lsr r mov r,r
movw r,r mul r,r
neg r or r,r
ori d,M out I,r
pop r push r
rol r ror r
sbc r,r sbci d,M
sbi I,I sbic I,I
sbiw w,I sbr d,M
sbrc r,I sbrs r,I
ser d st e,r
std b,r sts label,r
sub r,r subi d,M
swap r
Constraint characters may be prepended by a single constraint modifier. Contraints without a modifier specify read-only operands. Modifiers are:
Modifier Specifies
= Write-only operand, usually used for all output operands.
+ Read-write operand
& Register should be used for output only
Output operands must be write-only and the C expression result must be an lvalue, which means that the operands must be valid on the left side of assignments. Note, that the compiler will not check if the operands are of reasonable type for the kind of operation used in the assembler instructions. Input operands are, you guessed it, read-only. But what if you need the same operand for input and output? As stated above, read-write operands are not supported in inline assembler code. But there is another solution. For input operators it is possible to use a single digit in the constraint string. Using digit n tells the compiler to use the same register as for the n-th operand, starting with zero. Here is an example: \code asm volatile("swap %0" : "=r" (value) : "0" (value)); \endcode This statement will swap the nibbles of an 8-bit variable named value. Constraint \c "0" tells the compiler, to use the same input register as for the first operand. Note however, that this doesn't automatically imply the reverse case. The compiler may choose the same registers for input and output, even if not told to do so. This is not a problem in most cases, but may be fatal if the output operator is modified by the assembler code before the input operator is used. In the situation where your code depends on different registers used for input and output operands, you must add the \c & constraint modifier to your output operand. The following example demonstrates this problem: \code asm volatile("in %0,%1" "\n\t" "out %1, %2" "\n\t" : "=&r" (input) : "I" (_SFR_IO_ADDR(port)), "r" (output) ); \endcode In this example an input value is read from a port and then an output value is written to the same port. If the compiler would have choosen the same register for input and output, then the output value would have been destroyed on the first assembler instruction. Fortunately, this example uses the \c & constraint modifier to instruct the compiler not to select any register for the output value, which is used for any of the input operands. Back to swapping. Here is the code to swap high and low byte of a 16-bit value: \code asm volatile("mov __tmp_reg__, %A0" "\n\t" "mov %A0, %B0" "\n\t" "mov %B0, __tmp_reg__" "\n\t" : "=r" (value) : "0" (value) ); \endcode First you will notice the usage of register __tmp_reg__, which we listed among other special registers in the \ref asm_code section. You can use this register without saving its contents. Completely new are those letters A and \c B in \%A0 and \%B0. In fact they refer to two different 8-bit registers, both containing a part of value. Another example to swap bytes of a 32-bit value: \code asm volatile("mov __tmp_reg__, %A0" "\n\t" "mov %A0, %D0" "\n\t" "mov %D0, __tmp_reg__" "\n\t" "mov __tmp_reg__, %B0" "\n\t" "mov %B0, %C0" "\n\t" "mov %C0, __tmp_reg__" "\n\t" : "=r" (value) : "0" (value) ); \endcode Instead of listing the same operand as both, input and output operand, it can also be declared as a read-write operand. This must be applied to an output operand, and the respective input operand list remains empty: \code asm volatile("mov __tmp_reg__, %A0" "\n\t" "mov %A0, %D0" "\n\t" "mov %D0, __tmp_reg__" "\n\t" "mov __tmp_reg__, %B0" "\n\t" "mov %B0, %C0" "\n\t" "mov %C0, __tmp_reg__" "\n\t" : "+r" (value)); \endcode If operands do not fit into a single register, the compiler will automatically assign enough registers to hold the entire operand. In the assembler code you use \%A0 to refer to the lowest byte of the first operand, \%A1 to the lowest byte of the second operand and so on. The next byte of the first operand will be \%B0, the next byte \%C0 and so on. This also implies, that it is often neccessary to cast the type of an input operand to the desired size. A final problem may arise while using pointer register pairs. If you define an input operand \code "e" (ptr) \endcode and the compiler selects register \c Z \c (r30:r31), then \%A0 refers to \c r30 and
\%B0 refers to \c r31. But both versions will fail during the assembly stage of the compiler, if you explicitely need \c Z, like in \code ld r24,Z \endcode If you write \code ld r24, %a0 \endcode with a lower case \c a following the percent sign, then the compiler will create the proper assembler line. \section clobbers Clobbers As stated previously, the last part of the \c asm statement, the list of clobbers, may be omitted, including the colon seperator. However, if you are using registers, which had not been passed as operands, you need to inform the compiler about this. The following example will do an atomic increment. It increments an 8-bit value pointed to by a pointer variable in one go, without being interrupted by an interrupt routine or another thread in a multithreaded environment. Note, that we must use a pointer, because the incremented value needs to be stored before interrupts are enabled. \code asm volatile( "cli" "\n\t" "ld r24, %a0" "\n\t" "inc r24" "\n\t" "st %a0, r24" "\n\t" "sei" "\n\t" : : "e" (ptr) : "r24" ); \endcode The compiler might produce the following code: \code cli ld r24, Z inc r24 st Z, r24 sei \endcode One easy solution to avoid clobbering register \c r24 is, to make use of the special temporary register \c __tmp_reg__ defined by the compiler. \code asm volatile( "cli" "\n\t" "ld __tmp_reg__, %a0" "\n\t" "inc __tmp_reg__" "\n\t" "st %a0, __tmp_reg__" "\n\t" "sei" "\n\t" : : "e" (ptr) ); \endcode The compiler is prepared to reload this register next time it uses it. Another problem with the above code is, that it should not be called in code sections, where interrupts are disabled and should be kept disabled, because it will enable interrupts at the end. We may store the current status, but then we need another register. Again we can solve this without clobbering a fixed, but let the compiler select it. This could be done with the help of a local C variable. \code { uint8_t s; asm volatile( "in %0, __SREG__" "\n\t" "cli" "\n\t" "ld __tmp_reg__, %a1" "\n\t" "inc __tmp_reg__" "\n\t" "st %a1, __tmp_reg__" "\n\t" "out __SREG__, %0" "\n\t" : "=&r" (s) : "e" (ptr) ); } \endcode Now every thing seems correct, but it isn't really. The assembler code modifies the variable, that \c ptr points to. The compiler will not recognize this and may keep its value in any of the other registers. Not only does the compiler work with the wrong value, but the assembler code does too. The C program may have modified the value too, but the compiler didn't update the memory location for optimization reasons. The worst thing you can do in this case is: \code { uint8_t s; asm volatile( "in %0, __SREG__" "\n\t" "cli" "\n\t" "ld __tmp_reg__, %a1" "\n\t" "inc __tmp_reg__" "\n\t" "st %a1, __tmp_reg__" "\n\t" "out __SREG__, %0" "\n\t" : "=&r" (s) : "e" (ptr) : "memory" ); } \endcode The special clobber "memory" informs the compiler that the assembler code may modify any memory location. It forces the compiler to update all variables for which the contents are currently held in a register before executing the assembler code. And of course, everything has to be reloaded again after this code. In most situations, a much better solution would be to declare the pointer destination itself volatile: \code volatile uint8_t *ptr; \endcode This way, the compiler expects the value pointed to by \c ptr to be changed and will load it whenever used and store it whenever modified. Situations in which you need clobbers are very rare. In most cases there will be better ways. Clobbered registers will force the compiler to store their values before and reload them after your assembler code. Avoiding clobbers gives the compiler more freedom while optimizing your code. \section asm_macros Assembler Macros In order to reuse your assembler language parts, it is useful to define them as macros and put them into include files. AVR Libc comes with a bunch of them, which could be found in the directory \c avr/include. Using such include files may produce compiler warnings, if they are used in modules, which are compiled in strict ANSI mode. To avoid that, you can write \c __asm__ instead of \c asm and \c __volatile__ instead of \c volatile. These are equivalent aliases. Another problem with reused macros arises if you are using labels. In such cases you may make use of the special pattern \c %=, which is replaced by a unique number on each \c asm statement. The following code had been taken from avr/include/iomacros.h: \verbatim#define loop_until_bit_is_clear(port,bit) \ __asm__ __volatile__ ( \ "L_%=: " "sbic %0, %1" "\n\t" \ "rjmp L_%=" \ : /* no outputs */ \ : "I" (_SFR_IO_ADDR(port)), \ "I" (bit) \ ) \endverbatim When used for the first time, \c L_%= may be translated to \c L_1404, the next usage might create \c L_1405 or whatever. In any case, the labels became unique too. Another option is to use Unix-assembler style numeric labels. They are explained in \ref faq_asmstabs. The above example would then look like: \verbatim#define loop_until_bit_is_clear(port,bit) \ __asm__ __volatile__ ( \ "1: " "sbic %0, %1" "\n\t" \ "rjmp 1b" \ : /* no outputs */ \ : "I" (_SFR_IO_ADDR(port)), \ "I" (bit) \ ) \endverbatim \section asm_c_stubs C Stub Functions Macro definitions will include the same assembler code whenever they are referenced. This may not be acceptable for larger routines. In this case you may define a C stub function, containing nothing other than your assembler code. \code void delay(uint8_t ms) { uint16_t cnt; asm volatile ( "\n" "L_dl1%=:" "\n\t" "mov %A0, %A2" "\n\t" "mov %B0, %B2" "\n" "L_dl2%=:" "\n\t" "sbiw %A0, 1" "\n\t" "brne L_dl2%=" "\n\t" "dec %1" "\n\t" "brne L_dl1%=" "\n\t" : "=&w" (cnt) : "r" (ms), "r" (delay_count) ); } \endcode The purpose of this function is to delay the program execution by a specified number of milliseconds using a counting loop. The global 16 bit variable delay_count must contain the CPU clock frequency in Hertz divided by 4000 and must have been set before calling this routine for the first time. As described in the \ref clobbers "clobber" section, the routine uses a local variable to hold a temporary value. Another use for a local variable is a return value. The following function returns a 16 bit value read from two successive port addresses. \code uint16_t inw(uint8_t port) { uint16_t result; asm volatile ( "in %A0,%1" "\n\t" "in %B0,(%1) + 1" : "=r" (result) : "I" (_SFR_IO_ADDR(port)) ); return result; } \endcode \note inw() is supplied by avr-libc. \section c_names_in_asm C Names Used in Assembler Code By default \c AVR-GCC uses the same symbolic names of functions or variables in C and assembler code. You can specify a different name for the assembler code by using a special form of the \c asm statement: \code unsigned long value asm("clock") = 3686400; \endcode This statement instructs the compiler to use the symbol name clock rather than value. This makes sense only for external or static variables, because local variables do not have symbolic names in the assembler code. However, local variables may be held in registers. With \c AVR-GCC you can specify the use of a specific register: \code void Count(void) { register unsigned char counter asm("r3"); ... some code... asm volatile("clr r3"); ... more code... } \endcode The assembler instruction, "clr r3", will clear the variable counter. \c AVR-GCC will not completely reserve the specified register. If the optimizer recognizes that the variable will not be referenced any longer, the register may be re-used. But the compiler is not able to check wether this register usage conflicts with any predefined register. If you reserve too many registers in this way, the compiler may even run out of registers during code generation. In order to change the name of a function, you need a prototype declaration, because the compiler will not accept the \c asm keyword in the function definition: \code extern long Calc(void) asm ("CALCULATE"); \endcode Calling the function \c Calc() will create assembler instructions to call the function \c CALCULATE. \section links Links For a more thorough discussion of inline assembly usage, see the gcc user manual. The latest version of the gcc manual is always available here: http://gcc.gnu.org/onlinedocs/ */ avr-libc-1.8.0.orig/doc/api/dox_html_footer0000644000000000000000000000017011732702554015505 0ustar

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It is difficult to modify GCC to create new extensions to the C language syntax, so instead, avr-libc has created macros to retrieve the data from the Program Space. These macros are also found in the \c system header file. \section pgmspace_const A Note On const Many users bring up the idea of using C's keyword \c const as a means of declaring data to be in Program Space. Doing this would be an abuse of the intended meaning of the \c const keyword. \c const is used to tell the compiler that the data is to be "read-only". It is used to help make it easier for the compiler to make certain transformations, or to help the compiler check for incorrect usage of those variables. For example, the const keyword is commonly used in many functions as a modifier on the parameter type. This tells the compiler that the function will only use the parameter as read-only and will not modify the contents of the parameter variable. \c const was intended for uses such as this, not as a means to identify where the data should be stored. If it were used as a means to define data storage, then it loses its correct meaning (changes its semantics) in other situations such as in the function parameter example. \section pgmspace_data Storing and Retrieving Data in the Program Space Let's say you have some global data: \code unsigned char mydata[11][10] = { {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09}, {0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13}, {0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D}, {0x1E,0x1F,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27}, {0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,0x30,0x31}, {0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B}, {0x3C,0x3D,0x3E,0x3F,0x40,0x41,0x42,0x43,0x44,0x45}, {0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F}, {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59}, {0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,0x60,0x61,0x62,0x63}, {0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D} }; \endcode and later in your code you access this data in a function and store a single byte into a variable like so: \code byte = mydata[i][j]; \endcode Now you want to store your data in Program Memory. Use the \c PROGMEM macro found in \c and put it after the declaration of the variable, but before the initializer, like so: \code #include . . . unsigned char mydata[11][10] PROGMEM = { {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09}, {0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13}, {0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D}, {0x1E,0x1F,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27}, {0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,0x30,0x31}, {0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B}, {0x3C,0x3D,0x3E,0x3F,0x40,0x41,0x42,0x43,0x44,0x45}, {0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F}, {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59}, {0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,0x60,0x61,0x62,0x63}, {0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D} }; \endcode That's it! Now your data is in the Program Space. You can compile, link, and check the map file to verify that \c mydata is placed in the correct section. Now that your data resides in the Program Space, your code to access (read) the data will no longer work. The code that gets generated will retrieve the data that is located at the address of the \c mydata array, plus offsets indexed by the \c i and \c j variables. However, the final address that is calculated where to the retrieve the data points to the Data Space! Not the Program Space where the data is actually located. It is likely that you will be retrieving some garbage. The problem is that AVR GCC does not intrinsically know that the data resides in the Program Space. The solution is fairly simple. The "rule of thumb" for accessing data stored in the Program Space is to access the data as you normally would (as if the variable is stored in Data Space), like so: \code byte = mydata[i][j]; \endcode then take the address of the data: \code byte = &(mydata[i][j]); \endcode then use the appropriate \c pgm_read_* macro, and the address of your data becomes the parameter to that macro: \code byte = pgm_read_byte(&(mydata[i][j])); \endcode The \c pgm_read_* macros take an address that points to the Program Space, and retrieves the data that is stored at that address. This is why you take the address of the offset into the array. This address becomes the parameter to the macro so it can generate the correct code to retrieve the data from the Program Space. There are different \c pgm_read_* macros to read different sizes of data at the address given. \section pgmspace_strings Storing and Retrieving Strings in the Program Space Now that you can successfully store and retrieve simple data from Program Space you want to store and retrive strings from Program Space. And specifically you want to store and array of strings to Program Space. So you start off with your array, like so: \code char *string_table[] = { "String 1", "String 2", "String 3", "String 4", "String 5" }; \endcode and then you add your PROGMEM macro to the end of the declaration: \code char *string_table[] PROGMEM = { "String 1", "String 2", "String 3", "String 4", "String 5" }; \endcode Right? WRONG! Unfortunately, with GCC attributes, they affect only the declaration that they are attached to. So in this case, we successfully put the \c string_table variable, the array itself, in the Program Space. This DOES NOT put the actual strings themselves into Program Space. At this point, the strings are still in the Data Space, which is probably not what you want. In order to put the strings in Program Space, you have to have explicit declarations for each string, and put each string in Program Space: \code char string_1[] PROGMEM = "String 1"; char string_2[] PROGMEM = "String 2"; char string_3[] PROGMEM = "String 3"; char string_4[] PROGMEM = "String 4"; char string_5[] PROGMEM = "String 5"; \endcode Then use the new symbols in your table, like so: \code PGM_P string_table[] PROGMEM = { string_1, string_2, string_3, string_4, string_5 }; \endcode Now this has the effect of putting \c string_table in Program Space, where \c string_table is an array of pointers to characters (strings), where each pointer is a pointer to the Program Space, where each string is also stored. The \c PGM_P type above is also a macro that defined as a pointer to a character in the Program Space. Retrieving the strings are a different matter. You probably don't want to pull the string out of Program Space, byte by byte, using the \c pgm_read_byte() macro. There are other functions declared in the header file that work with strings that are stored in the Program Space. For example if you want to copy the string from Program Space to a buffer in RAM (like an automatic variable inside a function, that is allocated on the stack), you can do this: \code void foo(void) { char buffer[10]; for (unsigned char i = 0; i < 5; i++) { strcpy_P(buffer, (PGM_P)pgm_read_word(&(string_table[i]))); // Display buffer on LCD. } return; } \endcode Here, the \c string_table array is stored in Program Space, so we access it normally, as if were stored in Data Space, then take the address of the location we want to access, and use the address as a parameter to \c pgm_read_word. We use the \c pgm_read_word macro to read the string pointer out of the \c string_table array. Remember that a pointer is 16-bits, or word size. The \c pgm_read_word macro will return a 16-bit unsigned integer. We then have to typecast it as a true pointer to program memory, \c PGM_P. This pointer is an address in Program Space pointing to the string that we want to copy. This pointer is then used as a parameter to the function \c strcpy_P. The function \c strcpy_P is just like the regular \c strcpy function, except that it copies a string from Program Space (the second parameter) to a buffer in the Data Space (the first parameter). There are many string functions available that work with strings located in Program Space. All of these special string functions have a suffix of \c _P in the function name, and are declared in the header file. \section pgmspace_caveats Caveats The macros and functions used to retrieve data from the Program Space have to generate some extra code in order to actually load the data from the Program Space. This incurs some extra overhead in terms of code space (extra opcodes) and execution time. Usually, both the space and time overhead is minimal compared to the space savings of putting data in Program Space. But you should be aware of this so you can minimize the number of calls within a single function that gets the same piece of data from Program Space. It is always instructive to look at the resulting disassembly from the compiler. */ avr-libc-1.8.0.orig/doc/api/Makefile.am0000644000000000000000000002140011732702554014421 0ustar # # Copyright (c) 2002, 2003, 2005, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # 3. The name of the author may not be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 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Roth # # Contributors: # # $Id: Makefile.am 2224 2011-02-23 19:25:28Z joerg_wunsch $ # MAINTAINERCLEANFILES = Makefile.in stamp-vti CLEANFILES = *.html *.pdf *.ma *.mas \ *.png *.eps fix_png \ doxygen.config doxygen-pdf.config EXTRA_DIST = dox.css dox_html_header dox_html_footer \ doxygen.config.in \ main_page.dox \ assembler.dox \ inline_asm.dox \ interrupts.dox \ acknowledge.dox \ malloc.dox \ $(IMAGE_SRC) \ sections.dox \ sfr.dox \ tools-install.dox \ using-avrprog.dox \ using-tools.dox \ faq.dox \ rel-method.dox \ bench.dox \ bench-libc.dox \ bench-libm.dox \ porting.dox \ overview.dox \ pgmspace.dox \ library.dox \ vectortable.dox SUFFIXES = .pdf .fig .png .eps DOC_INST_DIR = @DOC_INST_DIR@ USER_MANUAL = @AVR_LIBC_USER_MANUAL@ DEMO_LIBS = $(shell cd $(top_srcdir) && find `pwd` \( -name crtm8.o -o -name exit.o \) -print | grep avr4) # As avr-gcc must have been installed already, we can reference its # library by a -l option. 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Note that there are some nasty things # going on here: the string "Vector Name" in the table heading is used # as a magic string in order to replace the \\ at the end of the table # heading by \endhead so longtable will know what heading to repeat in # table continuations. # # The last sed command replaces the \renewcommand for \cftchapfont and # \cftchappagefont, respectively, by a \newcommand, to fix a LaTeX # error. latex_src/refman.tex: doxygen.config $(IMAGE_EPS) $(IMAGE_PNG) doxygen doxygen.config cp $(top_srcdir)/doc/api/avrs.png-save $(AVR_LIBC_USER_MANUAL)/avrs.png cd latex_src && \ sed -e '/tocdepth/s/1/2/' \ -e '/usepackage{doxygen}/s/$$/\\usepackage{longtable}/' \ refman.tex > tmp.$$ && \ mv -f tmp.$$ refman.tex cd latex_src && \ sed -e '/{TabularC}{.}/s/{TabularC}{.}/{longtable}{|p{1.7cm}|p{1.7cm}|p{2cm}|p{5cm}|}/' \ -e '/TabularC/s/TabularC/longtable/' \ -e '/Vector name/,/^[^ ]/s/\\\\\\hline/\\endhead\\hline/' \ group__avr__interrupts.tex > tmp.$$ && \ mv -f tmp.$$ group__avr__interrupts.tex cd latex_src && \ if [ -f using_tools.tex ] ; then \ UT=using_tools.tex; else \ UT=using__tools.tex; fi; \ sed -e '/{TabularC}{3}/s/{TabularC}{3}/{longtable}{|l|>{\PBS}p{5cm}|>{\PBS}p{3.5cm}|}/' \ -e '/begin{longtable}/,/TabularC/s/TabularC/longtable/' \ -e '/Architecture/s/\\\\\\hline/\\endhead\\hline/' \ -e '/MCU types are currently/,/Architecture/s/>.*|/l|l|/' \ $$UT > tmp.$$ && \ mv -f tmp.$$ $$UT cd latex_src && \ sed -e '/renewcommand.*cftchap.*font/s/renew/new/' \ doxygen.sty > tmp.$$ && \ mv -f tmp.$$ doxygen.sty #doxygen.config: doxygen.config.in $(top_srcdir)/stamp-h1 doxygen.config: doxygen.config.in sed \ -e 's,[@]VERSION[@],$(VERSION),g' \ -e 's,[@]top_srcdir[@],$(top_srcdir),g' \ -e 's,[@]top_builddir[@],$(top_builddir),g' \ -e 's,[@]AVR_LIBC_USER_MANUAL[@],$(AVR_LIBC_USER_MANUAL),g' \ -e 's,[@]srcdir[@],$(srcdir),g' \ < $(srcdir)/doxygen.config.in > doxygen.config ||\ { rm -f doxygen.config; exit 1; } # XXX currently, HTML and LaTeX documentation will always be built # together. HTML doesn't need any postprocessing, while latex is only # a prerequisite for ps. dox-html: demo demodox fix_png $(USER_MANUAL)/index.html $(USER_MANUAL)/index.html: latex_src/refman.tex dox-pdf: $(USER_MANUAL).pdf $(USER_MANUAL).pdf: latex_src/refman.tex cd latex_src && ${MAKE} refman.pdf cp latex_src/refman.pdf $(USER_MANUAL).pdf # Install rules for the various documentation parts. The actual # access to those rules is from the install-data-local target above, # where the toplevel configure decides which of them will become a # prerequisite of install-data-local. install-dox-html: dox-html $(mkinstalldirs) $(DOC_INST_DIR)/$(USER_MANUAL) @list='$(wildcard $(USER_MANUAL)/*.html $(USER_MANUAL)/*.css \ $(USER_MANUAL)/*.jpg $(USER_MANUAL)/*.png)'; \ for file in $$list ; do \ echo " $(INSTALL_DATA) $$file $(DOC_INST_DIR)/$$file"; \ $(INSTALL_DATA) $$file $(DOC_INST_DIR)/$$file; \ done install-dox-pdf: dox-pdf $(mkinstalldirs) $(DOC_INST_DIR) $(INSTALL_DATA) $(USER_MANUAL).pdf $(DOC_INST_DIR)/$(USER_MANUAL).pdf install-dox-man: dox-html $(mkinstalldirs) $(DESTDIR)$(mandir)/man3 $(INSTALL_DATA) man/man3/*.3 $(DESTDIR)$(mandir)/man3 .PHONY: html latex pdf demo demodox \ dox-html dox-pdf install-pdf install-html \ install-dox-html install-dox-pdf \ install-dox-man avr-libc-1.8.0.orig/doc/api/sections.dox0000644000000000000000000001753411732702554014745 0ustar /* Copyright (c) 2002,2005, Theodore Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: sections.dox 845 2005-09-06 18:17:43Z joerg_wunsch $ */ /** \page mem_sections Memory Sections \remarks Need to list all the sections which are available to the avr. \par Weak Bindings FIXME: need to discuss the .weak directive. The following describes the various sections available. \section sec_dot_text The .text Section The .text section contains the actual machine instructions which make up your program. This section is further subdivided by the .initN and .finiN sections dicussed below. \note The \c avr-size program (part of binutils), coming from a Unix background, doesn't account for the .data initialization space added to the .text section, so in order to know how much flash the final program will consume, one needs to add the values for both, .text and .data (but not .bss), while the amount of pre-allocated SRAM is the sum of .data and .bss. \section sec_dot_data The .data Section This section contains static data which was defined in your code. Things like the following would end up in .data: \code char err_str[] = "Your program has died a horrible death!"; struct point pt = { 1, 1 }; \endcode It is possible to tell the linker the SRAM address of the beginning of the .data section. This is accomplished by adding -Wl,-Tdata,addr to the \c avr-gcc command used to the link your program. Not that addr must be offset by adding 0x800000 the to real SRAM address so that the linker knows that the address is in the SRAM memory space. Thus, if you want the .data section to start at 0x1100, pass 0x801100 at the address to the linker. [offset \ref harvard_arch "explained"] \note When using \c malloc() in the application (which could even happen inside library calls), \ref malloc_extram "additional adjustments" are required. \section sec_dot_bss The .bss Section Uninitialized global or static variables end up in the .bss section. \section sec_dot_eeprom The .eeprom Section This is where eeprom variables are stored. \section sec_dot_noinit The .noinit Section This sections is a part of the .bss section. What makes the .noinit section special is that variables which are defined as such: \code int foo __attribute__ ((section (".noinit"))); \endcode will not be initialized to zero during startup as would normal .bss data. Only uninitialized variables can be placed in the .noinit section. Thus, the following code will cause \c avr-gcc to issue an error: \code int bar __attribute__ ((section (".noinit"))) = 0xaa; \endcode It is possible to tell the linker explicitly where to place the .noinit section by adding -Wl,--section-start=.noinit=0x802000 to the avr-gcc command line at the linking stage. For example, suppose you wish to place the .noinit section at SRAM address 0x2000: \verbatim $ avr-gcc ... -Wl,--section-start=.noinit=0x802000 ... \endverbatim \anchor harvard_arch \note Because of the Harvard architecture of the AVR devices, you must manually add 0x800000 to the address you pass to the linker as the start of the section. Otherwise, the linker thinks you want to put the .noinit section into the .text section instead of .data/.bss and will complain. Alternatively, you can write your own linker script to automate this. [FIXME: need an example or ref to dox for writing linker scripts.] \section sec_dot_init The .initN Sections These sections are used to define the startup code from reset up through the start of main(). These all are subparts of the \ref sec_dot_text ".text section". The purpose of these sections is to allow for more specific placement of code within your program. \note Sometimes, it is convenient to think of the .initN and .finiN sections as functions, but in reality they are just symbolic names which tell the linker where to stick a chunk of code which is \em not a function. Notice that the examples for \ref asm_sections "asm" and \ref c_sections "C" can not be called as functions and should not be jumped into. The .initN sections are executed in order from 0 to 9. \par .init0: Weakly bound to __init(). If user defines __init(), it will be jumped into immediately after a reset. \par .init1: Unused. User definable. \par .init2: In C programs, weakly bound to initialize the stack, and to clear __zero_reg__ (r1). \par .init3: Unused. User definable. \par .init4: For devices with > 64 KB of ROM, .init4 defines the code which takes care of copying the contents of .data from the flash to SRAM. For all other devices, this code as well as the code to zero out the .bss section is loaded from libgcc.a. \par .init5: Unused. User definable. \par .init6: Unused for C programs, but used for constructors in C++ programs. \par .init7: Unused. User definable. \par .init8: Unused. User definable. \par .init9: Jumps into main(). \section sec_dot_fini The .finiN Sections These sections are used to define the exit code executed after return from main() or a call to exit(). These all are subparts of the \ref sec_dot_text ".text section". The .finiN sections are executed in descending order from 9 to 0. \par .finit9: Unused. User definable. This is effectively where _exit() starts. \par .fini8: Unused. User definable. \par .fini7: Unused. User definable. \par .fini6: Unused for C programs, but used for destructors in C++ programs. \par .fini5: Unused. User definable. \par .fini4: Unused. User definable. \par .fini3: Unused. User definable. \par .fini2: Unused. User definable. \par .fini1: Unused. User definable. \par .fini0: Goes into an infinite loop after program termination and completion of any _exit() code (execution of code in the .fini9 -> .fini1 sections). \section asm_sections Using Sections in Assembler Code Example: \code #include .section .init1,"ax",@progbits ldi r0, 0xff out _SFR_IO_ADDR(PORTB), r0 out _SFR_IO_ADDR(DDRB), r0 \endcode \note The ,"ax",\@progbits tells the assembler that the section is allocatable ("a"), executable ("x") and contains data ("@progbits"). For more detailed information on the .section directive, see the gas user manual. \section c_sections Using Sections in C Code Example: \code #include void my_init_portb (void) __attribute__ ((naked)) \ __attribute__ ((section (".init3"))); void my_init_portb (void) { PORTB = 0xff; DDRB = 0xff; } \endcode \note Section .init3 is used in this example, as this ensures the inernal __zero_reg__ has already been set up. The code generated by the compiler might blindly rely on __zero_reg__ being really 0. */ avr-libc-1.8.0.orig/doc/api/malloc-x1.fig0000644000000000000000000000560711732702554014664 0ustar #FIG 3.2 Landscape Center Metric A4 100.00 Single -2 1200 2 0 32 #cfcfcf 6 4185 1800 6885 3150 2 1 0 2 0 7 50 0 -1 0.000 0 0 -1 1 0 2 1 1 2.00 120.00 240.00 6120 2250 6840 2250 2 2 0 0 0 3 100 0 20 0.000 0 0 -1 0 0 5 4185 3150 5085 3150 5085 1800 4185 1800 4185 3150 2 2 0 0 0 14 100 0 20 0.000 0 0 -1 0 0 5 5085 3150 5985 3150 5985 1800 5085 1800 5085 3150 2 2 0 0 0 23 100 0 20 0.000 0 0 -1 0 0 5 5985 3150 6885 3150 6885 1800 5985 1800 5985 3150 4 0 0 50 0 16 12 0.0000 4 135 765 4275 2700 variables\001 4 0 0 50 0 16 12 0.0000 4 135 405 4410 2430 .data\001 4 0 0 50 0 16 12 0.0000 4 135 765 5175 2700 variables\001 4 0 0 50 0 16 12 0.0000 4 135 330 5355 2430 .bss\001 4 0 0 50 0 16 12 0.0000 4 180 420 6120 2700 heap\001 -6 2 1 0 2 0 7 50 0 -1 0.000 0 0 -1 1 0 2 1 1 2.00 120.00 240.00 4050 2250 3375 2250 2 2 0 0 0 32 100 0 20 0.000 0 0 -1 0 0 5 450 3150 3375 3150 3375 1800 450 1800 450 3150 2 2 0 0 0 32 100 0 20 0.000 0 0 -1 0 0 5 6885 3150 7200 3150 7200 1800 6885 1800 6885 3150 2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 450 1800 7200 1800 7200 3150 450 3150 450 1800 2 2 0 0 0 26 100 0 20 0.000 0 0 -1 0 0 5 3375 3150 4185 3150 4185 1800 3375 1800 3375 3150 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 3645 3870 4140 3870 4140 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 3060 3600 3375 3600 3375 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 7335 3870 6885 3870 6885 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 7335 4140 5985 4140 5985 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 6435 4410 5985 4410 5985 4140 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 6435 4680 5085 4680 5085 3285 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 6435 4995 4185 4995 4185 3870 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 1.00 60.00 120.00 7335 3600 7110 3600 7110 3285 2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2 4185 1800 4185 3150 4 0 0 50 0 16 18 0.0000 4 210 1650 4815 1530 external RAM\001 4 0 0 50 0 16 12 1.5708 4 135 645 4140 1665 0x10FF\001 4 0 0 50 0 16 12 1.5708 4 135 615 630 1620 0x0100\001 4 0 0 50 0 16 12 0.0000 4 135 435 3555 2700 stack\001 4 0 0 50 0 16 18 0.0000 4 210 1815 1305 1530 on-board RAM\001 4 0 0 50 0 16 12 1.5708 4 135 615 4410 1665 0x1100\001 4 0 0 50 0 16 12 1.5708 4 135 675 7155 1665 0xFFFF\001 4 0 0 100 0 16 12 0.0000 4 135 240 2745 3645 SP\001 4 0 0 100 0 16 12 0.0000 4 135 810 2745 3915 RAMEND\001 4 0 0 100 0 16 12 0.0000 4 165 915 6570 4455 __bss_end\001 4 0 0 100 0 16 12 0.0000 4 165 2265 6570 4725 __data_end == __bss_start\001 4 0 0 100 0 16 12 0.0000 4 165 1020 6570 5040 __data_start\001 4 0 0 100 0 16 12 0.0000 4 180 3270 7470 3645 *(__malloc_heap_end) == __heap_end\001 4 0 0 100 0 16 12 0.0000 4 180 3330 7425 4185 *(__malloc_heap_start) == __heap_start\001 4 0 0 100 0 16 12 0.0000 4 180 915 7470 3915 *(__brkval)\001 avr-libc-1.8.0.orig/doc/api/bench-libm.dox0000644000000000000000000000575211732702554015115 0ustar /* Note: this file has been automatically generated. DO NOT EDIT, or your changes WILL BE LOST! */ /* $Id: bench-libm.dox 1965 2009-05-24 06:18:18Z dmix $ */ /** \page benchmarks \section bench_libm Math functions. The table contains the number of MCU clocks to calculate a function with a given argument(s). The main reason of a big difference between Avr2 and Avr4 is a hardware multiplication.
Function Avr2 Avr4
__addsf3 (1.234, 5.678) 113 108
__mulsf3 (1.234, 5.678) 375 138
__divsf3 (1.234, 5.678) 466 465
acos (0.54321) 4411 2455
asin (0.54321) 4517 2556
atan (0.54321) 4710 2271
atan2 (1.234, 5.678) 5270 2857
cbrt (1.2345) 2684 2555
ceil (1.2345) 177 177
cos (1.2345) 3387 1671
cosh (1.2345) 4922 2979
exp (1.2345) 4708 2765
fdim (5.678, 1.234) 111 111
floor (1.2345) 180 180
fmax (1.234, 5.678) 39 37
fmin (1.234, 5.678) 35 35
fmod (5.678, 1.234) 131 131
frexp (1.2345, 0) 42 41
hypot (1.234, 5.678) 1341 866
ldexp (1.2345, 6) 42 42
log (1.2345) 4142 2134
log10 (1.2345) 4498 2260
modf (1.2345, 0) 433 429
pow (1.234, 5.678) 9293 5047
round (1.2345) 150 150
sin (1.2345) 3353 1653
sinh (1.2345) 4946 3003
sqrt (1.2345) 494 492
tan (1.2345) 4381 2426
tanh (1.2345) 5126 3173
trunc (1.2345) 178 178
*/ avr-libc-1.8.0.orig/doc/api/using-tools.dox0000644000000000000000000010527111732702554015375 0ustar /* Copyright (c) 2002,2004,2005,2006,2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: using-tools.dox 2211 2011-02-14 14:04:25Z aboyapati $ */ /** \page using_tools Using the GNU tools This is a short summary of the AVR-specific aspects of using the GNU tools. Normally, the generic documentation of these tools is fairly large and maintained in \c texinfo files. Command-line options are explained in detail in the manual page. \section using_avr_gcc Options for the C compiler avr-gcc \subsection using_avr_gcc_mach_opt Machine-specific options for the AVR The following machine-specific options are recognized by the C compiler frontend. In addition to the preprocessor macros indicated in the tables below, the preprocessor will define the macros __AVR and __AVR__ (to the value 1) when compiling for an AVR target. The macro AVR will be defined as well when using the standard levels gnu89 (default) and gnu99 but not with c89 and c99. - -mmcu=architecture

Compile code for \e architecture. Currently known architectures are

Architecture Macros Description
avr1 __AVR_ARCH__=1
__AVR_ASM_ONLY__
__AVR_2_BYTE_PC__ [2] 		Simple CPU core, only assembler support
avr2 __AVR_ARCH__=2
__AVR_2_BYTE_PC__ [2] 		"Classic" CPU core, up to 8 KB of ROM
avr25 [1] __AVR_ARCH__=25
__AVR_HAVE_MOVW__ [1]
__AVR_HAVE_LPMX__ [1]
__AVR_2_BYTE_PC__ [2] 		"Classic" CPU core with 'MOVW' and 'LPM Rx, Z[+]' instruction, up to 8 KB of ROM
avr3 __AVR_ARCH__=3
__AVR_MEGA__ [5]
__AVR_HAVE_JMP_CALL__ [4]
__AVR_2_BYTE_PC__ [2] 		"Classic" CPU core, 16 KB to 64 KB of ROM
avr31 __AVR_ARCH__=31
__AVR_MEGA__ [5]
__AVR_HAVE_JMP_CALL__ [4]
__AVR_HAVE_RAMPZ__ [4]
__AVR_HAVE_ELPM__ [4]
__AVR_2_BYTE_PC__ [2] 		"Classic" CPU core, 128 KB of ROM
avr35 [3] __AVR_ARCH__=35
__AVR_MEGA__ [5]
__AVR_HAVE_JMP_CALL__ [4]
__AVR_HAVE_MOVW__ [1]
__AVR_HAVE_LPMX__ [1]
__AVR_2_BYTE_PC__ [2] 		"Classic" CPU core with 'MOVW' and 'LPM Rx, Z[+]' instruction, 16 KB to 64 KB of ROM
avr4 __AVR_ARCH__=4
__AVR_ENHANCED__ [5]
__AVR_HAVE_MOVW__ [1]
__AVR_HAVE_LPMX__ [1]
__AVR_HAVE_MUL__ [1]
__AVR_2_BYTE_PC__ [2] 		"Enhanced" CPU core, up to 8 KB of ROM
avr5 __AVR_ARCH__=5
__AVR_MEGA__ [5]
__AVR_ENHANCED__ [5]
__AVR_HAVE_JMP_CALL__ [4]
__AVR_HAVE_MOVW__ [1]
__AVR_HAVE_LPMX__ [1]
__AVR_HAVE_MUL__ [1]
__AVR_2_BYTE_PC__ [2] 		"Enhanced" CPU core, 16 KB to 64 KB of ROM
avr51 __AVR_ARCH__=51
__AVR_MEGA__ [5]
__AVR_ENHANCED__ [5]
__AVR_HAVE_JMP_CALL__ [4]
__AVR_HAVE_MOVW__ [1]
__AVR_HAVE_LPMX__ [1]
__AVR_HAVE_MUL__ [1]
__AVR_HAVE_RAMPZ__ [4]
__AVR_HAVE_ELPM__ [4]
__AVR_HAVE_ELPMX__ [4]
__AVR_2_BYTE_PC__ [2] 		"Enhanced" CPU core, 128 KB of ROM
avr6 [2] __AVR_ARCH__=6
__AVR_MEGA__ [5]
__AVR_ENHANCED__ [5]
__AVR_HAVE_JMP_CALL__ [4]
__AVR_HAVE_MOVW__ [1]
__AVR_HAVE_LPMX__ [1]
__AVR_HAVE_MUL__ [1]
__AVR_HAVE_RAMPZ__ [4]
__AVR_HAVE_ELPM__ [4]
__AVR_HAVE_ELPMX__ [4]
__AVR_3_BYTE_PC__ [2] 		"Enhanced" CPU core, 256 KB of ROM

[1] New in GCC 4.2
[2] Unofficial patch for GCC 4.1
[3] New in GCC 4.2.3
[4] New in GCC 4.3
[5] Obsolete.

By default, code is generated for the avr2 architecture.

Note that when only using -mmcu=architecture but no -mmcu=MCU type, including the file <avr/io.h> cannot work since it cannot decide which device's definitions to select.

- -mmcu=MCU type

The following MCU types are currently understood by avr-gcc. The table matches them against the corresponding avr-gcc architecture name, and shows the preprocessor symbol declared by the \c -mmcu option.

ArchitectureMCU nameMacro
avr1at90s1200__AVR_AT90S1200__
avr1attiny11__AVR_ATtiny11__
avr1attiny12__AVR_ATtiny12__
avr1attiny15__AVR_ATtiny15__
avr1attiny28__AVR_ATtiny28__
avr2at90s2313__AVR_AT90S2313__
avr2at90s2323__AVR_AT90S2323__
avr2at90s2333__AVR_AT90S2333__
avr2at90s2343__AVR_AT90S2343__
avr2attiny22__AVR_ATtiny22__
avr2attiny26__AVR_ATtiny26__
avr2at90s4414__AVR_AT90S4414__
avr2at90s4433__AVR_AT90S4433__
avr2at90s4434__AVR_AT90S4434__
avr2at90s8515__AVR_AT90S8515__
avr2at90c8534__AVR_AT90C8534__
avr2at90s8535__AVR_AT90S8535__
avr2/avr25 [1]at86rf401__AVR_AT86RF401__
avr2/avr25 [1]ata6289__AVR_ATA6289__
avr2/avr25 [1]attiny13__AVR_ATtiny13__
avr2/avr25 [1]attiny13a__AVR_ATtiny13A__
avr2/avr25 [1]attiny2313__AVR_ATtiny2313__
avr2/avr25 [1]attiny2313a__AVR_ATtiny2313A__
avr2/avr25 [1]attiny24__AVR_ATtiny24__
avr2/avr25 [1]attiny24a__AVR_ATtiny24A__
avr2/avr25 [1]attiny25__AVR_ATtiny25__
avr2/avr25 [1]attiny261__AVR_ATtiny261__
avr2/avr25 [1]attiny261a__AVR_ATtiny261A__
avr2/avr25 [1]attiny4313__AVR_ATtiny4313__
avr2/avr25 [1]attiny43u__AVR_ATtiny43U__
avr2/avr25 [1]attiny44__AVR_ATtiny44__
avr2/avr25 [1]attiny44a__AVR_ATtiny44A__
avr2/avr25 [1]attiny45__AVR_ATtiny45__
avr2/avr25 [1]attiny461__AVR_ATtiny461__
avr2/avr25 [1]attiny461a__AVR_ATtiny461A__
avr2/avr25 [1]attiny48__AVR_ATtiny48__
avr2/avr25 [1]attiny84__AVR_ATtiny84__
avr2/avr25 [1]attiny84a__AVR_ATtiny84A__
avr2/avr25 [1]attiny85__AVR_ATtiny85__
avr2/avr25 [1]attiny861__AVR_ATtiny861__
avr2/avr25 [1]attiny861a__AVR_ATtiny861A__
avr2/avr25 [1]attiny87__AVR_ATtiny87__
avr2/avr25 [1]attiny88__AVR_ATtiny88__
avr3atmega603__AVR_ATmega603__
avr3at43usb355__AVR_AT43USB355__
avr3/avr31 [3]atmega103__AVR_ATmega103__
avr3/avr31 [3]at43usb320__AVR_AT43USB320__
avr3/avr35 [2]at90usb82__AVR_AT90USB82__
avr3/avr35 [2]at90usb162__AVR_AT90USB162__
avr3/avr35 [2]atmega8u2__AVR_ATmega8U2__
avr3/avr35 [2]atmega16u2__AVR_ATmega16U2__
avr3/avr35 [2]atmega32u2__AVR_ATmega32U2__
avr3/avr35 [2]attiny167__AVR_ATtiny167__
avr3at76c711__AVR_AT76C711__
avr4atmega48__AVR_ATmega48__
avr4atmega48a__AVR_ATmega48A__
avr4atmega48p__AVR_ATmega48P__
avr4atmega8__AVR_ATmega8__
avr4atmega8515__AVR_ATmega8515__
avr4atmega8535__AVR_ATmega8535__
avr4atmega88__AVR_ATmega88__
avr4atmega88a__AVR_ATmega88A__
avr4atmega88p__AVR_ATmega88P__
avr4atmega88pa__AVR_ATmega88PA__
avr4atmega8hva__AVR_ATmega8HVA__
avr4at90pwm1__AVR_AT90PWM1__
avr4at90pwm2__AVR_AT90PWM2__
avr4at90pwm2b__AVR_AT90PWM2B__
avr4at90pwm3__AVR_AT90PWM3__
avr4at90pwm3b__AVR_AT90PWM3B__
avr4at90pwm81__AVR_AT90PWM81__
avr5at90can32__AVR_AT90CAN32__
avr5at90can64__AVR_AT90CAN64__
avr5at90pwm216__AVR_AT90PWM216__
avr5at90pwm316__AVR_AT90PWM316__
avr5at90scr100__AVR_AT90SCR100__
avr5at90usb646__AVR_AT90USB646__
avr5at90usb647__AVR_AT90USB647__
avr5at94k__AVR_AT94K__
avr5atmega16__AVR_ATmega16__
avr5atmega161__AVR_ATmega161__
avr5atmega162__AVR_ATmega162__
avr5atmega163__AVR_ATmega163__
avr5atmega164a__AVR_ATmega164A__
avr5atmega164p__AVR_ATmega164P__
avr5atmega165__AVR_ATmega165__
avr5atmega165a__AVR_ATmega165A__
avr5atmega165p__AVR_ATmega165P__
avr5atmega168__AVR_ATmega168__
avr5atmega168a__AVR_ATmega168A__
avr5atmega168p__AVR_ATmega168P__
avr5atmega169__AVR_ATmega169__
avr5atmega169a__AVR_ATmega169A__
avr5atmega169p__AVR_ATmega169P__
avr5atmega169pa__AVR_ATmega169PA__
avr5atmega16a__AVR_ATmega16A__
avr5atmega16hva__AVR_ATmega16HVA__
avr5atmega16hva2__AVR_ATmega16HVA2__
avr5atmega16hvb__AVR_ATmega16HVB__
avr5atmega16hvbrevb__AVR_ATmega16HVBREVB__
avr5atmega16m1__AVR_ATmega16M1__
avr5atmega16u4__AVR_ATmega16U4__
avr5atmega32__AVR_ATmega32__
avr5atmega323__AVR_ATmega323__
avr5atmega324a__AVR_ATmega324A__
avr5atmega324p__AVR_ATmega324P__
avr5atmega324pa__AVR_ATmega324PA__
avr5atmega325__AVR_ATmega325__
avr5atmega325a__AVR_ATmega325A__
avr5atmega325p__AVR_ATmega325P__
avr5atmega3250__AVR_ATmega3250__
avr5atmega3250a__AVR_ATmega3250A__
avr5atmega3250p__AVR_ATmega3250P__
avr5atmega328__AVR_ATmega328__
avr5atmega328p__AVR_ATmega328P__
avr5atmega329__AVR_ATmega329__
avr5atmega329a__AVR_ATmega329A__
avr5atmega329p__AVR_ATmega329P__
avr5atmega329pa__AVR_ATmega329PA__
avr5atmega3290__AVR_ATmega3290__
avr5atmega3290a__AVR_ATmega3290A__
avr5atmega3290p__AVR_ATmega3290P__
avr5atmega32c1__AVR_ATmega32C1__
avr5atmega32hvb__AVR_ATmega32HVB__
avr5atmega32hvbrevb__AVR_ATmega32HVBREVB__
avr5atmega32m1__AVR_ATmega32M1__
avr5atmega32u4__AVR_ATmega32U4__
avr5atmega32u6__AVR_ATmega32U6__
avr5atmega406__AVR_ATmega406__
avr5atmega64__AVR_ATmega64__
avr5atmega640__AVR_ATmega640__
avr5atmega644__AVR_ATmega644__
avr5atmega644a__AVR_ATmega644A__
avr5atmega644p__AVR_ATmega644P__
avr5atmega644pa__AVR_ATmega644PA__
avr5atmega645__AVR_ATmega645__
avr5atmega645a__AVR_ATmega645A__
avr5atmega645p__AVR_ATmega645P__
avr5atmega6450__AVR_ATmega6450__
avr5atmega6450a__AVR_ATmega6450A__
avr5atmega6450p__AVR_ATmega6450P__
avr5atmega649__AVR_ATmega649__
avr5atmega649a__AVR_ATmega649A__
avr5atmega6490__AVR_ATmega6490__
avr5atmega6490a__AVR_ATmega6490A__
avr5atmega6490p__AVR_ATmega6490P__
avr5atmega649p__AVR_ATmega649P__
avr5atmega64c1__AVR_ATmega64C1__
avr5atmega64hve__AVR_ATmega64HVE__
avr5atmega64m1__AVR_ATmega64M1__
avr5m3000__AVR_M3000__
avr5/avr51 [3]at90can128__AVR_AT90CAN128__
avr5/avr51 [3]at90usb1286__AVR_AT90USB1286__
avr5/avr51 [3]at90usb1287__AVR_AT90USB1287__
avr5/avr51 [3]atmega128__AVR_ATmega128__
avr5/avr51 [3]atmega1280__AVR_ATmega1280__
avr5/avr51 [3]atmega1281__AVR_ATmega1281__
avr5/avr51 [3]atmega1284p__AVR_ATmega1284P__
avr6atmega2560__AVR_ATmega2560__
avr6atmega2561__AVR_ATmega2561__
avrxmega2atxmega16a4__AVR_ATxmega16A4__
avrxmega2atxmega16d4__AVR_ATxmega16D4__
avrxmega2atxmega32a4__AVR_ATxmega32A4__
avrxmega2atxmega32d4__AVR_ATxmega32D4__
avrxmega4atxmega64a3__AVR_ATxmega64A3__
avrxmega4atxmega64d3__AVR_ATxmega64D3__
avrxmega5atxmega64a1__AVR_ATxmega64A1__
avrxmega5atxmega64a1u__AVR_ATxmega64A1U__
avrxmega6atxmega128a3__AVR_ATxmega128A3__
avrxmega6atxmega128d3__AVR_ATxmega128D3__
avrxmega6atxmega192a3__AVR_ATxmega192A3__
avrxmega6atxmega192d3__AVR_ATxmega192D3__
avrxmega6atxmega256a3__AVR_ATxmega256A3__
avrxmega6atxmega256a3b__AVR_ATxmega256A3B__
avrxmega6atxmega256d3__AVR_ATxmega256D3__
avrxmega7atxmega128a1__AVR_ATxmega128A1__
avrxmega7atxmega128a1u__AVR_ATxmega128A1U__
avrtiny10attiny4__AVR_ATtiny4__
avrtiny10attiny5__AVR_ATtiny5__
avrtiny10attiny9__AVR_ATtiny9__
avrtiny10attiny10__AVR_ATtiny10__
avrtiny10attiny20__AVR_ATtiny20__
avrtiny10attiny40__AVR_ATtiny40__

[1] 'avr25' architecture is new in GCC 4.2
[2] 'avr35' architecture is new in GCC 4.2.3
[3] 'avr31' and 'avr51' architectures is new in GCC 4.3

- \c -morder1 - \c -morder2

Change the order of register assignment. The default is

r24, r25, r18, r19, r20, r21, r22, r23, r30, r31, r26, r27, r28, r29, r17, r16, r15, r14, r13, r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r0, r1

Order 1 uses

r18, r19, r20, r21, r22, r23, r24, r25, r30, r31, r26, r27, r28, r29, r17, r16, r15, r14, r13, r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r0, r1

Order 2 uses

r25, r24, r23, r22, r21, r20, r19, r18, r30, r31, r26, r27, r28, r29, r17, r16, r15, r14, r13, r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0

- \c -mint8

Assume \c int to be an 8-bit integer. Note that this is not really supported by \c avr-libc, so it should normally not be used. The default is to use 16-bit integers.

- \c -mno-interrupts

Generates code that changes the stack pointer without disabling interrupts. Normally, the state of the status register \c SREG is saved in a temporary register, interrupts are disabled while changing the stack pointer, and \c SREG is restored.

Specifying this option will define the preprocessor macro \c __NO_INTERRUPTS__ to the value 1.

- \c -mcall-prologues

Use subroutines for function prologue/epilogue. For complex functions that use many registers (that needs to be saved/restored on function entry/exit), this saves some space at the cost of a slightly increased execution time.

- \c -mtiny-stack

Change only the low 8 bits of the stack pointer.

- \c -mno-tablejump

Deprecated, use \c -fno-jump-tables instead.

- \c -mshort-calls

Use \c rjmp/rcall (limited range) on >8K devices. On \c avr2 and \c avr4 architectures (less than 8 KB or flash memory), this is always the case. On \c avr3 and \c avr5 architectures, calls and jumps to targets outside the current function will by default use \c jmp/call instructions that can cover the entire address range, but that require more flash ROM and execution time.

- \c -mrtl

Dump the internal compilation result called "RTL" into comments in the generated assembler code. Used for debugging avr-gcc.

- \c -msize

Dump the address, size, and relative cost of each statement into comments in the generated assembler code. Used for debugging avr-gcc.

- \c -mdeb

Generate lots of debugging information to \c stderr.

\subsection using_sel_gcc_opts Selected general compiler options The following general gcc options might be of some interest to AVR users. - -On

\anchor gcc_optO Optimization level \e n. Increasing \e n is meant to optimize more, an optimization level of 0 means no optimization at all, which is the default if no \c -O option is present. The special option \c -Os is meant to turn on all \c -O2 optimizations that are not expected to increase code size.

Note that at \c -O3, gcc attempts to inline all "simple" functions. For the AVR target, this will normally constitute a large pessimization due to the code increasement. The only other optimization turned on with \c -O3 is \c -frename-registers, which could rather be enabled manually instead.

A simple \c -O option is equivalent to \c -O1.

Note also that turning off all optimizations will prevent some warnings from being issued since the generation of those warnings depends on code analysis steps that are only performed when optimizing (unreachable code, unused variables).

See also the \ref faq_gdboptimize "appropriate FAQ entry" for issues regarding debugging optimized code.

- -Wa,assembler-options - -Wl,linker-options

\anchor gcc_minusW Pass the listed options to the assembler, or linker, respectively.

- \c -g

Generate debugging information that can be used by avr-gdb.

- \c -ffreestanding

Assume a "freestanding" environment as per the C standard. This turns off automatic builtin functions (though they can still be reached by prepending \c __builtin_ to the actual function name). It also makes the compiler not complain when \c main() is declared with a \c void return type which makes some sense in a microcontroller environment where the application cannot meaningfully provide a return value to its environment (in most cases, \c main() won't even return anyway). However, this also turns off all optimizations normally done by the compiler which assume that functions known by a certain name behave as described by the standard. E. g., applying the function strlen() to a literal string will normally cause the compiler to immediately replace that call by the actual length of the string, while with \c -ffreestanding, it will always call strlen() at run-time.

- \c -funsigned-char

Make any unqualfied \c char type an unsigned char. Without this option, they default to a signed char.

- \c -funsigned-bitfields

Make any unqualified bitfield type unsigned. By default, they are signed.

- \c -fshort-enums

Allocate to an \c enum type only as many bytes as it needs for the declared range of possible values. Specifically, the enum type will be equivalent to the smallest integer type which has enough room.

- \c -fpack-struct

Pack all structure members together without holes.

- \c -fno-jump-tables

Do not generate tablejump instructions. By default, jump tables can be used to optimize \c switch statements. When turned off, sequences of compare statements are used instead. Jump tables are usually faster to execute on average, but in particular for \c switch statements, where most of the jumps would go to the default label, they might waste a bit of flash memory.

NOTE: The tablejump instructions use the LPM assembler instruction for access to jump tables. Always use \c -fno-jump-tables switch, if compiling a bootloader for devices with more than 64 KB of code memory.

\section using_avr_as Options for the assembler avr-as \subsection using_avr_as_mach_opts Machine-specific assembler options - -mmcu=architecture - -mmcu=MCU name

avr-as understands the same \c -mmcu= options as \ref using_avr_gcc "avr-gcc". By default, avr2 is assumed, but this can be altered by using the appropriate \c .arch pseudo-instruction inside the assembler source file.

- \c -mall-opcodes

Turns off opcode checking for the actual MCU type, and allows any possible AVR opcode to be assembled.

- \c -mno-skip-bug

Don't emit a warning when trying to skip a 2-word instruction with a CPSE/SBIC/SBIS/SBRC/SBRS instruction. Early AVR devices suffered from a hardware bug where these instructions could not be properly skipped.

- \c -mno-wrap

For RJMP/RCALL instructions, don't allow the target address to wrap around for devices that have more than 8 KB of memory.

- \c --gstabs

Generate \c .stabs debugging symbols for assembler source lines. This enables avr-gdb to trace through assembler source files. This option must not be used when assembling sources that have been generated by the C compiler; these files already contain the appropriate line number information from the C source files.

- -a[cdhlmns=file]

Turn on the assembler listing. The sub-options are:

  • \c c omit false conditionals
  • \c d omit debugging directives
  • \c h include high-level source
  • \c l include assembly
  • \c m include macro expansions
  • \c n omit forms processing
  • \c s include symbols
  • =file set the name of the listing file

The various sub-options can be combined into a single \c -a option list; \e =file must be the last one in that case.

\subsection using_avr_example Examples for assembler options passed through the C compiler Remember that assembler options can be passed from the C compiler frontend using \c -Wa (see \ref gcc_minusW "above"), so in order to include the C source code into the assembler listing in file \c foo.lst, when compiling \c foo.c, the following compiler command-line can be used: \verbatim $ avr-gcc -c -O foo.c -o foo.o -Wa,-ahls=foo.lst \endverbatim In order to pass an assembler file through the C preprocessor first, and have the assembler generate line number debugging information for it, the following command can be used: \verbatim $ avr-gcc -c -x assembler-with-cpp -o foo.o foo.S -Wa,--gstabs \endverbatim Note that on Unix systems that have case-distinguishing file systems, specifying a file name with the suffix \c .S (upper-case letter S) will make the compiler automatically assume -x assembler-with-cpp, while using \c .s would pass the file directly to the assembler (no preprocessing done). \section using_avr_ld Controlling the linker avr-ld \subsection using_sel_ld_opts Selected linker options While there are no machine-specific options for avr-ld, a number of the standard options might be of interest to AVR users. - -lname

Locate the archive library named libname.a, and use it to resolve currently unresolved symbols from it. The library is searched along a path that consists of builtin pathname entries that have been specified at compile time (e. g. \c /usr/local/avr/lib on Unix systems), possibly extended by pathname entries as specified by \c -L options (that must precede the \c -l options on the command-line).

- -Lpath

Additional location to look for archive libraries requested by \c -l options.

- --defsym symbol=expr

Define a global symbol \e symbol using \e expr as the value.

- \c -M

Print a linker map to \c stdout.

- -Map mapfile

Print a linker map to \e mapfile.

- \c --cref

Output a cross reference table to the map file (in case \c -Map is also present), or to \c stdout.

- --section-start sectionname=org

Start section \e sectionname at absolute address \e org.

- -Tbss org - -Tdata org - -Ttext org

Start the \c bss, \c data, or \c text section at \e org, respectively.

- -T scriptfile

Use \e scriptfile as the linker script, replacing the default linker script. Default linker scripts are stored in a system-specific location (e. g. under \c /usr/local/avr/lib/ldscripts on Unix systems), and consist of the AVR architecture name (avr2 through avr5) with the suffix \c .x appended. They describe how the various \ref mem_sections "memory sections" will be linked together.

\subsection using_pass_ld_opts Passing linker options from the C compiler By default, all unknown non-option arguments on the avr-gcc command-line (i. e., all filename arguments that don't have a suffix that is handled by avr-gcc) are passed straight to the linker. Thus, all files ending in \c .o (object files) and \c .a (object libraries) are provided to the linker. System libraries are usually not passed by their explicit filename but rather using the \c -l option which uses an abbreviated form of the archive filename (see above). avr-libc ships two system libraries, \c libc.a, and \c libm.a. While the standard library \c libc.a will always be searched for unresolved references when the linker is started using the C compiler frontend (i. e., there's always at least one implied \c -lc option), the mathematics library \c libm.a needs to be explicitly requested using \c -lm. See also the \ref faq_libm "entry in the FAQ" explaining this. Conventionally, Makefiles use the \c make macro \c LDLIBS to keep track of \c -l (and possibly \c -L) options that should only be appended to the C compiler command-line when linking the final binary. In contrast, the macro \c LDFLAGS is used to store other command-line options to the C compiler that should be passed as options during the linking stage. The difference is that options are placed early on the command-line, while libraries are put at the end since they are to be used to resolve global symbols that are still unresolved at this point. Specific linker flags can be passed from the C compiler command-line using the \c -Wl compiler option, see \ref gcc_minusW "above". This option requires that there be no spaces in the appended linker option, while some of the linker options above (like \c -Map or \c --defsym) would require a space. In these situations, the space can be replaced by an equal sign as well. For example, the following command-line can be used to compile \c foo.c into an executable, and also produce a link map that contains a cross-reference list in the file \c foo.map: \verbatim $ avr-gcc -O -o foo.out -Wl,-Map=foo.map -Wl,--cref foo.c \endverbatim Alternatively, a comma as a placeholder will be replaced by a space before passing the option to the linker. So for a device with external SRAM, the following command-line would cause the linker to place the data segment at address 0x2000 in the SRAM: \verbatim $ avr-gcc -mmcu=atmega128 -o foo.out -Wl,-Tdata,0x802000 \endverbatim See the explanation of the \ref sec_dot_data "data section" for why 0x800000 needs to be added to the actual value. Note that the stack will still remain in internal RAM, through the symbol \c __stack that is provided by the run-time startup code. This is probably a good idea anyway (since internal RAM access is faster), and even required for some early devices that had hardware bugs preventing them from using a stack in external RAM. Note also that the heap for \c malloc() will still be placed after all the variables in the data section, so in this situation, no stack/heap collision can occur. In order to relocate the stack from its default location at the top of interns RAM, the value of the symbol \c __stack can be changed on the linker command-line. As the linker is typically called from the compiler frontend, this can be achieved using a compiler option like \code -Wl,--defsym=__stack=0x8003ff \endcode The above will make the code use stack space from RAM address 0x3ff downwards. The amount of stack space available then depends on the bottom address of internal RAM for a particular device. It is the responsibility of the application to ensure the stack does not grow out of bounds, as well as to arrange for the stack to not collide with variable allocations made by the compiler (sections .data and .bss). */ avr-libc-1.8.0.orig/doc/api/overview.dox0000644000000000000000000003112511732702554014754 0ustar /* Copyright (c) 2007 Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: overview.dox 1526 2007-12-20 14:17:56Z joerg_wunsch $ */ /** \page overview Toolchain Overview \section overview_introduction Introduction Welcome to the open source software development toolset for the Atmel AVR! There is not a single tool that provides everything needed to develop software for the AVR. It takes many tools working together. Collectively, the group of tools are called a toolset, or commonly a toolchain, as the tools are chained together to produce the final executable application for the AVR microcontroller. The following sections provide an overview of all of these tools. You may be used to cross-compilers that provide everything with a GUI front-end, and not know what goes on "underneath the hood". You may be coming from a desktop or server computer background and not used to embedded systems. Or you may be just learning about the most common software development toolchain available on Unix and Linux systems. Hopefully the following overview will be helpful in putting everything in perspective. \section overview_fsf_and_gnu FSF and GNU According to its website, "the Free Software Foundation (FSF), established in 1985, is dedicated to promoting computer users' rights to use, study, copy, modify, and redistribute computer programs. The FSF promotes the development and use of free software, particularly the GNU operating system, used widely in its GNU/Linux variant." The FSF remains the primary sponsor of the GNU project. The GNU Project was launched in 1984 to develop a complete Unix-like operating system which is free software: the GNU system. GNU is a recursive acronym for ğGNU's Not UnixĞ; it is pronounced guh-noo, approximately like canoe. One of the main projects of the GNU system is the GNU Compiler Collection, or GCC, and its sister project, GNU Binutils. These two open source projects provide a foundation for a software development toolchain. Note that these projects were designed to originally run on Unix-like systems. \section overview_gcc GCC GCC stands for GNU Compiler Collection. GCC is highly flexible compiler system. It has different compiler front-ends for different languages. It has many back-ends that generate assembly code for many different processors and host operating systems. All share a common "middle-end", containing the generic parts of the compiler, including a lot of optimizations. In GCC, a \e host system is the system (processor/OS) that the compiler runs on. A \e target system is the system that the compiler compiles code for. And, a \e build system is the system that the compiler is built (from source code) on. If a compiler has the same system for \e host and for \e target, it is known as a \e native compiler. If a compiler has different systems for \e host and \e target, it is known as a cross-compiler. (And if all three, \e build, \e host, and \e target systems are different, it is known as a Canadian cross compiler, but we won't discuss that here.) When GCC is built to execute on a \e host system such as FreeBSD, Linux, or Windows, and it is built to generate code for the AVR microcontroller \e target, then it is a cross compiler, and this version of GCC is commonly known as "AVR GCC". In documentation, or discussion, AVR GCC is used when referring to GCC targeting specifically the AVR, or something that is AVR specific about GCC. The term "GCC" is usually used to refer to something generic about GCC, or about GCC as a whole. GCC is different from most other compilers. GCC focuses on translating a high-level language to the target assembly only. AVR GCC has three available compilers for the AVR: C language, C++, and Ada. The compiler itself does not assemble or link the final code. GCC is also known as a "driver" program, in that it knows about, and drives other programs seamlessly to create the final output. The assembler, and the linker are part of another open source project called GNU Binutils. GCC knows how to drive the GNU assembler (gas) to assemble the output of the compiler. GCC knows how to drive the GNU linker (ld) to link all of the object modules into a final executable. The two projects, GCC and Binutils, are very much interrelated and many of the same volunteers work on both open source projects. When GCC is built for the AVR target, the actual program names are prefixed with "avr-". So the actual executable name for AVR GCC is: avr-gcc. The name "avr-gcc" is used in documentation and discussion when referring to the program itself and not just the whole AVR GCC system. See the GCC Web Site and GCC User Manual for more information about GCC. \section overview_binutils GNU Binutils The name GNU Binutils stands for "Binary Utilities". It contains the GNU assembler (gas), and the GNU linker (ld), but also contains many other utilities that work with binary files that are created as part of the software development toolchain. Again, when these tools are built for the AVR target, the actual program names are prefixed with "avr-". For example, the assembler program name, for a native assembler is "as" (even though in documentation the GNU assembler is commonly referred to as "gas"). But when built for an AVR target, it becomes "avr-as". Below is a list of the programs that are included in Binutils: \par avr-as The Assembler. \par avr-ld The Linker. \par avr-ar Create, modify, and extract from libraries (archives). \par avr-ranlib Generate index to library (archive) contents. \par avr-objcopy Copy and translate object files to different formats. \par avr-objdump Display information from object files including disassembly. \par avr-size List section sizes and total size. \par avr-nm List symbols from object files. \par avr-strings List printable strings from files. \par avr-strip Discard symbols from files. \par avr-readelf Display the contents of ELF format files. \par avr-addr2line Convert addresses to file and line. \par avr-c++filt Filter to demangle encoded C++ symbols. \section overview_avr-libc avr-libc GCC and Binutils provides a lot of the tools to develop software, but there is one critical component that they do not provide: a Standard C Library. There are different open source projects that provide a Standard C Library depending upon your system time, whether for a native compiler (GNU Libc), for some other embedded system (newlib), or for some versions of Linux (uCLibc). The open source AVR toolchain has its own Standard C Library project: avr-libc. AVR-Libc provides many of the same functions found in a regular Standard C Library and many additional library functions that is specific to an AVR. Some of the Standard C Library functions that are commonly used on a PC environment have limitations or additional issues that a user needs to be aware of when used on an embedded system. AVR-Libc also contains the most documentation about the whole AVR toolchain. \section overview_building_software Building Software Even though GCC, Binutils, and avr-libc are the core projects that are used to build software for the AVR, there is another piece of software that ties it all together: Make. GNU Make is a program that makes things, and mainly software. Make interprets and executes a Makefile that is written for a project. A Makefile contains dependency rules, showing which output files are dependent upon which input files, and instructions on how to build output files from input files. Some distributions of the toolchains, and other AVR tools such as MFile, contain a Makefile template written for the AVR toolchain and AVR applications that you can copy and modify for your application. See the GNU Make User Manual for more information. \section overview_avrdude AVRDUDE After creating your software, you'll want to program your device. You can do this by using the program AVRDUDE which can interface with various hardware devices to program your processor. AVRDUDE is a very flexible package. All the information about AVR processors and various hardware programmers is stored in a text database. This database can be modified by any user to add new hardware or to add an AVR processor if it is not already listed. \section overview_gdb_insight_ddd GDB / Insight / DDD The GNU Debugger (GDB) is a command-line debugger that can be used with the rest of the AVR toolchain. Insight is GDB plus a GUI written in Tcl/Tk. Both GDB and Insight are configured for the AVR and the main executables are prefixed with the target name: avr-gdb, and avr-insight. There is also a "text mode" GUI for GDB: avr-gdbtui. DDD (Data Display Debugger) is another popular GUI front end to GDB, available on Unix and Linux systems. \section overview_avarice AVaRICE AVaRICE is a back-end program to AVR GDB and interfaces to the Atmel JTAG In-Circuit Emulator (ICE), to provide emulation capabilities. \section overview_simulavr SimulAVR SimulAVR is an AVR simulator used as a back-end with AVR GDB. Unfortunately, this project is currently unmaintained and could use some help. \section overview_utilities Utilities There are also other optional utilities available that may be useful to add to your toolset. \c SRecord is a collection of powerful tools for manipulating EPROM load files. It reads and writes numerous EPROM file formats, and can perform many different manipulations. \c MFile is a simple Makefile generator is meant as an aid to quickly customize a Makefile to use for your AVR application. \section overview_distros Toolchain Distributions (Distros) All of the various open source projects that comprise the entire toolchain are normally distributed as source code. It is left up to the user to build the tool application from its source code. This can be a very daunting task to any potential user of these tools. Luckily there are people who help out in this area. Volunteers take the time to build the application from source code on particular host platforms and sometimes packaging the tools for convenient installation by the end user. These packages contain the binary executables of the tools, pre-made and ready to use. These packages are known as "distributions" of the AVR toolchain, or by a more shortened name, "distros". AVR toolchain distros are available on FreeBSD, Windows, Mac OS X, and certain flavors of Linux. \section overview_open_source Open Source All of these tools, from the original source code in the multitude of projects, to the various distros, are put together by many, many volunteers. All of these projects could always use more help from other people who are willing to volunteer some of their time. There are many different ways to help, for people with varying skill levels, abilities, and available time. You can help to answer questions in mailing lists such as the avr-gcc-list, or on forums at the AVR Freaks website. This helps many people new to the open source AVR tools. If you think you found a bug in any of the tools, it is always a big help to submit a good bug report to the proper project. A good bug report always helps other volunteers to analyze the problem and to get it fixed for future versions of the software. You can also help to fix bugs in various software projects, or to add desirable new features. Volunteers are always welcome! :-) */ avr-libc-1.8.0.orig/doc/INSTALL0000644000000000000000000000252511732702554012654 0ustar Installation instructions: 1. Build and install the current released version of binutils, version 2.16 (releases older than 2.13 are not supported), for AVR target (configure --target=avr). See http://sources.redhat.com/binutils/ . 2. Build and install the current released version of GCC, version 3.4.4 (older releases older than 3.3 are not supported), for AVR target (configure --target=avr --enable-languages=c,c++). C++ support is still experimental and incomplete (no libstdc++), and needs testing. 3. Now you can build and install avr-libc - type ./configure --build=`./config.guess` --host=avr && make then (as root, or user with write permissions to the installation directory) make install Note that GNU make is required, so if GNU make is installed under a different name on your system (e.g. gmake), change that appropriately above. By default, everything is installed under /usr/local - you can change that if you execute ./configure ... --prefix=/location. There are other configure options if you like. Type "./configure --help" to see them. Note: If you obtained avr-libc directly from cvs, you will need to run the bootstrap script. Be sure to use recent versions of autoconf and automake. automake version 1.7 and autoconf version 2.57 or above are required (1.9, and 2.59 resp. are recommended). avr-libc-1.8.0.orig/doc/Makefile.in0000644000000000000000000004416411732702554013675 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # # Copyright (c) 2002 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # 3. The name of the author may not be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 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Needs some rewriting to update for newer tools. (explanation of start code) * gcrt1.S * how to pre-program the EEPROM. * how to roll your own crt*.o - Figure out how to remove __ prefix from function args in dox. [Ted has workaround [5].] - fix signed/unsigned gcc warnings (qsort.c). [Joerg has patch [1] for this that just needs some love before it's committed.] - Write for avr-libc [3] : stddef.h, sys/types.h, limits.h, sys/systemcfg.h? - Add : smallest common denominator for IO port declarations. [7] - Hunt down and fix broken links in html dox. Linklint is a useful tool for that. [http://www.linklint.org/] [1] http://mail.nongnu.org/archive/html/avr-libc-dev/2002-08/msg00054.html [3] http://mail.nongnu.org/archive/html/avr-libc-dev/2002-08/msg00117.html [5] http://mail.nongnu.org/archive/html/avr-libc-dev/2002-12/msg00034.html [7] http://mail.nongnu.org/archive/html/avr-libc-dev/2003-01/msg00077.html avr-libc-1.8.0.orig/doc/examples/0000755000000000000000000000000011732702554013435 5ustar avr-libc-1.8.0.orig/doc/examples/twitest/0000755000000000000000000000000011732702554015140 5ustar avr-libc-1.8.0.orig/doc/examples/twitest/Makefile0000644000000000000000000000117311732702554016602 0ustar # # $Id: Makefile 233 2002-12-18 22:35:38Z joerg_wunsch $ # CC= avr-gcc #MCU=atmega8 #MCU=atmega16 #MCU=atmega32 #MCU=atmega163 #MCU=atmega323 MCU=atmega128 CFLAGS= -O -g -Wall -ffreestanding -mmcu=$(MCU) .SUFFIXES: .s .bin .out .hex .srec .c.s: $(CC) $(CFLAGS) -S $< .S.o: $(CC) $(ASFLAGS) -c $< .o.out: $(CC) $(CFLAGS) -o $@ $< .out.bin: avr-objcopy -O binary $< $@ .out.hex: avr-objcopy -O ihex $< $@ .out.srec: avr-objcopy -O srec $< $@ all: twitest.bin OBJS=twitest.o twitest.out: $(OBJS) $(CC) -o twitest.out $(CFLAGS) $(LDFLAGS) $(OBJS) $(LDLIBS) clean: rm -f *~ *.out *.bin *.hex *.srec *.s *.o *.pdf *core avr-libc-1.8.0.orig/doc/examples/twitest/twitest.dox0000644000000000000000000003067411732702554017371 0ustar /* Copyright (c) 2002, 2010 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: twitest.dox 2202 2010-12-16 23:11:37Z arcanum $ */ /** \defgroup twi_demo Example using the two-wire interface (TWI) \ingroup demos Some newer devices of the ATmega series contain builtin support for interfacing the microcontroller to a two-wire bus, called TWI. This is essentially the same called I2C by Philips, but that term is avoided in Atmel's documentation due to patenting issues. For further documentation, see: http://www.nxp.com/documents/user_manual/UM10204.pdf \section twi_demo_intro Introduction into TWI The two-wire interface consists of two signal lines named \e SDA (serial data) and \e SCL (serial clock) (plus a ground line, of course). All devices participating in the bus are connected together, using open-drain driver circuitry, so the wires must be terminated using appropriate pullup resistors. The pullups must be small enough to recharge the line capacity in short enough time compared to the desired maximal clock frequency, yet large enough so all drivers will not be overloaded. There are formulas in the datasheet that help selecting the pullups. Devices can either act as a master to the bus (i. e., they initiate a transfer), or as a slave (they only act when being called by a master). The bus is multi-master capable, and a particular device implementation can act as either master or slave at different times. Devices are addressed using a 7-bit address (coordinated by Philips) transfered as the first byte after the so-called start condition. The LSB of that byte is R/~W, i. e. it determines whether the request to the slave is to read or write data during the next cycles. (There is also an option to have devices using 10-bit addresses but that is not covered by this example.) \section twi_demo_project The TWI example project The ATmega TWI hardware supports both, master and slave operation. This example will only demonstrate how to use an AVR microcontroller as TWI master. The implementation is kept simple in order to concentrate on the steps that are required to talk to a TWI slave, so all processing is done in polled-mode, waiting for the TWI interface to indicate that the next processing step is due (by setting the TWINT interrupt bit). If it is desired to have the entire TWI communication happen in "background", all this can be implemented in an interrupt-controlled way, where only the start condition needs to be triggered from outside the interrupt routine. There is a variety of slave devices available that can be connected to a TWI bus. For the purpose of this example, an EEPROM device out of the industry-standard 24Cxx series has been chosen (where \e xx can be one of \b 01, \b 02, \b 04, \b 08, or 16) which are available from various vendors. The choice was almost arbitrary, mainly triggered by the fact that an EEPROM device is being talked to in both directions, reading and writing the slave device, so the example will demonstrate the details of both. Usually, there is probably not much need to add more EEPROM to an ATmega system that way: the smallest possible AVR device that offers hardware TWI support is the ATmega8 which comes with 512 bytes of EEPROM, which is equivalent to an 24C04 device. The ATmega128 already comes with twice as much EEPROM as the 24C16 would offer. One exception might be to use an externally connected EEPROM device that is removable; e. g. SDRAM PC memory comes with an integrated TWI EEPROM that carries the RAM configuration information. \section twi_demo_src The Source Code \htmlonly Source file: twitest.c \endhtmlonly \latexonly The source code is installed under \texttt{\$prefix/share/doc/avr-libc/examples/twitest/twitest.c}, where \texttt{\$prefix} is a configuration option. For Unix systems, it is usually set to either \texttt{/usr} or \texttt{/usr/local}. \endlatexonly \par Note [1] The header file <util/twi.h> contains some macro definitions for symbolic constants used in the TWI status register. These definitions match the names used in the Atmel datasheet except that all names have been prefixed with \c TW_. \par Note [2] The clock is used in timer calculations done by the compiler, for the UART baud rate and the TWI clock rate. \par Note [3] The address assigned for the 24Cxx EEPROM consists of 1010 in the upper four bits. The following three bits are normally available as slave sub-addresses, allowing to operate more than one device of the same type on a single bus, where the actual subaddress used for each device is configured by hardware strapping. However, since the next data packet following the device selection only allows for 8 bits that are used as an EEPROM address, devices that require more than 8 address bits (24C04 and above) "steal" subaddress bits and use them for the EEPROM cell address bits 9 to 11 as required. This example simply assumes all subaddress bits are 0 for the smaller devices, so the E0, E1, and E2 inputs of the 24Cxx must be grounded. \par Note [3a] EEPROMs of type 24C32 and above cannot be addressed anymore even with the subaddress bit trick. Thus, they require the upper address bits being sent separately on the bus. When activating the \c WORD_ADDRESS_16BIT define, the algorithm implements that auxiliary address byte transmission. \par Note [4] For slow clocks, enable the 2 x U[S]ART clock multiplier, to improve the baud rate error. This will allow a 9600 Bd communication using the standard 1 MHz calibrated RC oscillator. See also the Baud rate tables in the datasheets. \par Note [5] The datasheet explains why a minimum TWBR value of 10 should be maintained when running in master mode. Thus, for system clocks below 3.6 MHz, we cannot run the bus at the intented clock rate of 100 kHz but have to slow down accordingly. \par Note [6] This function is used by the standard output facilities that are utilized in this example for debugging and demonstration purposes. \par Note [7] In order to shorten the data to be sent over the TWI bus, the 24Cxx EEPROMs support multiple data bytes transfered within a single request, maintaining an internal address counter that is updated after each data byte transfered successfully. When reading data, one request can read the entire device memory if desired (the counter would wrap around and start back from 0 when reaching the end of the device). \par Note [8] When reading the EEPROM, a first device selection must be made with write intent (R/~W bit set to 0 indicating a write operation) in order to transfer the EEPROM address to start reading from. This is called master transmitter mode. Each completion of a particular step in TWI communication is indicated by an asserted TWINT bit in TWCR. (An interrupt would be generated if allowed.) After performing any actions that are needed for the next communication step, the interrupt condition must be manually cleared by \e setting the TWINT bit. Unlike with many other interrupt sources, this would even be required when using a true interrupt routine, since as soon as TWINT is re-asserted, the next bus transaction will start. \par Note [9] Since the TWI bus is multi-master capable, there is potential for a bus contention when one master starts to access the bus. Normally, the TWI bus interface unit will detect this situation, and will not initiate a start condition while the bus is busy. However, in case two masters were starting at exactly the same time, the way bus arbitration works, there is always a chance that one master could lose arbitration of the bus during any transmit operation. A master that has lost arbitration is required by the protocol to immediately cease talking on the bus; in particular it must not initiate a stop condition in order to not corrupt the ongoing transfer from the active master. In this example, upon detecting a lost arbitration condition, the entire transfer is going to be restarted. This will cause a new start condition to be initiated, which will normally be delayed until the currently active master has released the bus. \par Note [10] Next, the device slave is going to be reselected (using a so-called repeated start condition which is meant to guarantee that the bus arbitration will remain at the current master) using the same slave address (SLA), but this time with read intent (R/~W bit set to 1) in order to request the device slave to start transfering data from the slave to the master in the next packet. \par Note [11] If the EEPROM device is still busy writing one or more cells after a previous write request, it will simply leave its bus interface drivers at high impedance, and does not respond to a selection in any way at all. The master selecting the device will see the high level at SDA after transfering the SLA+R/W packet as a NACK to its selection request. Thus, the select process is simply started over (effectively causing a repeated start condition), until the device will eventually respond. This polling procedure is recommended in the 24Cxx datasheet in order to minimize the busy wait time when writing. Note that in case a device is broken and never responds to a selection (e. g. since it is no longer present at all), this will cause an infinite loop. Thus the maximal number of iterations made until the device is declared to be not responding at all, and an error is returned, will be limited to MAX_ITER. \par Note [12] This is called master receiver mode: the bus master still supplies the SCL clock, but the device slave drives the SDA line with the appropriate data. After 8 data bits, the master responds with an ACK bit (SDA driven low) in order to request another data transfer from the slave, or it can leave the SDA line high (NACK), indicating to the slave that it is going to stop the transfer now. Assertion of ACK is handled by setting the TWEA bit in TWCR when starting the current transfer. \par Note [13] The control word sent out in order to initiate the transfer of the next data packet is initially set up to assert the TWEA bit. During the last loop iteration, TWEA is de-asserted so the client will get informed that no further transfer is desired. \par Note [14] Except in the case of lost arbitration, all bus transactions must properly be terminated by the master initiating a stop condition. \par Note [15] Writing to the EEPROM device is simpler than reading, since only a master transmitter mode transfer is needed. Note that the first packet after the SLA+W selection is always considered to be the EEPROM address for the next operation. (This packet is exactly the same as the one above sent before starting to read the device.) In case a master transmitter mode transfer is going to send more than one data packet, all following packets will be considered data bytes to write at the indicated address. The internal address pointer will be incremented after each write operation. \par Note [16] 24Cxx devices can become write-protected by strapping their ~WC pin to logic high. (Leaving it unconnected is explicitly allowed, and constitutes logic low level, i. e. no write protection.) In case of a write protected device, all data transfer attempts will be NACKed by the device. Note that some devices might not implement this. */ avr-libc-1.8.0.orig/doc/examples/twitest/twitest.c0000644000000000000000000003401111732702554017006 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- */ /* * ---------------------------------------------------------------------------- * Updated to handle larger devices having 16-bit addresses * (2007-09-05) Ruwan Jayanetti * ---------------------------------------------------------------------------- */ /* $Id: twitest.c 2244 2011-05-12 03:33:42Z arcanum $ */ /* * Simple demo program that talks to a 24Cxx I²C EEPROM using the * builtin TWI interface of an ATmega device. */ #include #include #include #include #include /* Note [1] */ #define DEBUG 1 /* * System clock in Hz. */ #define F_CPU 14745600UL /* Note [2] */ /* * Compatibility defines. This should work on ATmega8, ATmega16, * ATmega163, ATmega323 and ATmega128 (IOW: on all devices that * provide a builtin TWI interface). * * On the 128, it defaults to USART 1. */ #ifndef UCSRB # ifdef UCSR1A /* ATmega128 */ # define UCSRA UCSR1A # define UCSRB UCSR1B # define UBRR UBRR1L # define UDR UDR1 # else /* ATmega8 */ # define UCSRA USR # define UCSRB UCR # endif #endif #ifndef UBRR # define UBRR UBRRL #endif /* * Note [3] * TWI address for 24Cxx EEPROM: * * 1 0 1 0 E2 E1 E0 R/~W 24C01/24C02 * 1 0 1 0 E2 E1 A8 R/~W 24C04 * 1 0 1 0 E2 A9 A8 R/~W 24C08 * 1 0 1 0 A10 A9 A8 R/~W 24C16 */ #define TWI_SLA_24CXX 0xa0 /* E2 E1 E0 = 0 0 0 */ /* * Note [3a] * Device word address length for 24Cxx EEPROM * Larger EEPROM devices (from 24C32) have 16-bit address * Define or undefine according to the used device */ //#define WORD_ADDRESS_16BIT /* * Maximal number of iterations to wait for a device to respond for a * selection. Should be large enough to allow for a pending write to * complete, but low enough to properly abort an infinite loop in case * a slave is broken or not present at all. With 100 kHz TWI clock, * transfering the start condition and SLA+R/W packet takes about 10 * µs. The longest write period is supposed to not exceed ~ 10 ms. * Thus, normal operation should not require more than 100 iterations * to get the device to respond to a selection. */ #define MAX_ITER 200 /* * Number of bytes that can be written in a row, see comments for * ee24xx_write_page() below. Some vendor's devices would accept 16, * but 8 seems to be the lowest common denominator. * * Note that the page size must be a power of two, this simplifies the * page boundary calculations below. */ #define PAGE_SIZE 8 /* * Saved TWI status register, for error messages only. We need to * save it in a variable, since the datasheet only guarantees the TWSR * register to have valid contents while the TWINT bit in TWCR is set. */ uint8_t twst; /* * Do all the startup-time peripheral initializations: UART (for our * debug/test output), and TWI clock. */ void ioinit(void) { #if F_CPU <= 1000000UL /* * Note [4] * Slow system clock, double Baud rate to improve rate error. */ UCSRA = _BV(U2X); UBRR = (F_CPU / (8 * 9600UL)) - 1; /* 9600 Bd */ #else UBRR = (F_CPU / (16 * 9600UL)) - 1; /* 9600 Bd */ #endif UCSRB = _BV(TXEN); /* tx enable */ /* initialize TWI clock: 100 kHz clock, TWPS = 0 => prescaler = 1 */ #if defined(TWPS0) /* has prescaler (mega128 & newer) */ TWSR = 0; #endif #if F_CPU < 3600000UL TWBR = 10; /* smallest TWBR value, see note [5] */ #else TWBR = (F_CPU / 100000UL - 16) / 2; #endif } /* * Note [6] * Send character c down the UART Tx, wait until tx holding register * is empty. */ int uart_putchar(char c, FILE *unused) { if (c == '\n') uart_putchar('\r', 0); loop_until_bit_is_set(UCSRA, UDRE); UDR = c; return 0; } /* * Note [7] * * Read "len" bytes from EEPROM starting at "eeaddr" into "buf". * * This requires two bus cycles: during the first cycle, the device * will be selected (master transmitter mode), and the address * transfered. * Address bits exceeding 256 are transfered in the * E2/E1/E0 bits (subaddress bits) of the device selector. * Address is sent in two dedicated 8 bit transfers * for 16 bit address devices (larger EEPROM devices) * * The second bus cycle will reselect the device (repeated start * condition, going into master receiver mode), and transfer the data * from the device to the TWI master. Multiple bytes can be * transfered by ACKing the client's transfer. The last transfer will * be NACKed, which the client will take as an indication to not * initiate further transfers. */ int ee24xx_read_bytes(uint16_t eeaddr, int len, uint8_t *buf) { uint8_t sla, twcr, n = 0; int rv = 0; #ifndef WORD_ADDRESS_16BIT /* patch high bits of EEPROM address into SLA */ sla = TWI_SLA_24CXX | (((eeaddr >> 8) & 0x07) << 1); #else /* 16-bit address devices need only TWI Device Address */ sla = TWI_SLA_24CXX; #endif /* * Note [8] * First cycle: master transmitter mode */ restart: if (n++ >= MAX_ITER) return -1; begin: TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN); /* send start condition */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_REP_START: /* OK, but should not happen */ case TW_START: break; case TW_MT_ARB_LOST: /* Note [9] */ goto begin; default: return -1; /* error: not in start condition */ /* NB: do /not/ send stop condition */ } /* Note [10] */ /* send SLA+W */ TWDR = sla | TW_WRITE; TWCR = _BV(TWINT) | _BV(TWEN); /* clear interrupt to start transmission */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_MT_SLA_ACK: break; case TW_MT_SLA_NACK: /* nack during select: device busy writing */ /* Note [11] */ goto restart; case TW_MT_ARB_LOST: /* re-arbitrate */ goto begin; default: goto error; /* must send stop condition */ } #ifdef WORD_ADDRESS_16BIT TWDR = (eeaddr >> 8); /* 16-bit word address device, send high 8 bits of addr */ TWCR = _BV(TWINT) | _BV(TWEN); /* clear interrupt to start transmission */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_MT_DATA_ACK: break; case TW_MT_DATA_NACK: goto quit; case TW_MT_ARB_LOST: goto begin; default: goto error; /* must send stop condition */ } #endif TWDR = eeaddr; /* low 8 bits of addr */ TWCR = _BV(TWINT) | _BV(TWEN); /* clear interrupt to start transmission */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_MT_DATA_ACK: break; case TW_MT_DATA_NACK: goto quit; case TW_MT_ARB_LOST: goto begin; default: goto error; /* must send stop condition */ } /* * Note [12] * Next cycle(s): master receiver mode */ TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN); /* send (rep.) start condition */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_START: /* OK, but should not happen */ case TW_REP_START: break; case TW_MT_ARB_LOST: goto begin; default: goto error; } /* send SLA+R */ TWDR = sla | TW_READ; TWCR = _BV(TWINT) | _BV(TWEN); /* clear interrupt to start transmission */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_MR_SLA_ACK: break; case TW_MR_SLA_NACK: goto quit; case TW_MR_ARB_LOST: goto begin; default: goto error; } for (twcr = _BV(TWINT) | _BV(TWEN) | _BV(TWEA) /* Note [13] */; len > 0; len--) { if (len == 1) twcr = _BV(TWINT) | _BV(TWEN); /* send NAK this time */ TWCR = twcr; /* clear int to start transmission */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_MR_DATA_NACK: len = 0; /* force end of loop */ /* FALLTHROUGH */ case TW_MR_DATA_ACK: *buf++ = TWDR; rv++; if(twst == TW_MR_DATA_NACK) goto quit; break; default: goto error; } } quit: /* Note [14] */ TWCR = _BV(TWINT) | _BV(TWSTO) | _BV(TWEN); /* send stop condition */ return rv; error: rv = -1; goto quit; } /* * Write "len" bytes into EEPROM starting at "eeaddr" from "buf". * * This is a bit simpler than the previous function since both, the * address and the data bytes will be transfered in master transmitter * mode, thus no reselection of the device is necessary. However, the * EEPROMs are only capable of writing one "page" simultaneously, so * care must be taken to not cross a page boundary within one write * cycle. The amount of data one page consists of varies from * manufacturer to manufacturer: some vendors only use 8-byte pages * for the smaller devices, and 16-byte pages for the larger devices, * while other vendors generally use 16-byte pages. We thus use the * smallest common denominator of 8 bytes per page, declared by the * macro PAGE_SIZE above. * * The function simply returns after writing one page, returning the * actual number of data byte written. It is up to the caller to * re-invoke it in order to write further data. */ int ee24xx_write_page(uint16_t eeaddr, int len, uint8_t *buf) { uint8_t sla, n = 0; int rv = 0; uint16_t endaddr; if (eeaddr + len <= (eeaddr | (PAGE_SIZE - 1))) endaddr = eeaddr + len; else endaddr = (eeaddr | (PAGE_SIZE - 1)) + 1; len = endaddr - eeaddr; #ifndef WORD_ADDRESS_16BIT /* patch high bits of EEPROM address into SLA */ sla = TWI_SLA_24CXX | (((eeaddr >> 8) & 0x07) << 1); #else /* 16-bit address devices need only TWI Device Address */ sla = TWI_SLA_24CXX; #endif restart: if (n++ >= MAX_ITER) return -1; begin: /* Note [15] */ TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN); /* send start condition */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_REP_START: /* OK, but should not happen */ case TW_START: break; case TW_MT_ARB_LOST: goto begin; default: return -1; /* error: not in start condition */ /* NB: do /not/ send stop condition */ } /* send SLA+W */ TWDR = sla | TW_WRITE; TWCR = _BV(TWINT) | _BV(TWEN); /* clear interrupt to start transmission */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_MT_SLA_ACK: break; case TW_MT_SLA_NACK: /* nack during select: device busy writing */ goto restart; case TW_MT_ARB_LOST: /* re-arbitrate */ goto begin; default: goto error; /* must send stop condition */ } #ifdef WORD_ADDRESS_16BIT TWDR = (eeaddr>>8); /* 16 bit word address device, send high 8 bits of addr */ TWCR = _BV(TWINT) | _BV(TWEN); /* clear interrupt to start transmission */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_MT_DATA_ACK: break; case TW_MT_DATA_NACK: goto quit; case TW_MT_ARB_LOST: goto begin; default: goto error; /* must send stop condition */ } #endif TWDR = eeaddr; /* low 8 bits of addr */ TWCR = _BV(TWINT) | _BV(TWEN); /* clear interrupt to start transmission */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_MT_DATA_ACK: break; case TW_MT_DATA_NACK: goto quit; case TW_MT_ARB_LOST: goto begin; default: goto error; /* must send stop condition */ } for (; len > 0; len--) { TWDR = *buf++; TWCR = _BV(TWINT) | _BV(TWEN); /* start transmission */ while ((TWCR & _BV(TWINT)) == 0) ; /* wait for transmission */ switch ((twst = TW_STATUS)) { case TW_MT_DATA_NACK: goto error; /* device write protected -- Note [16] */ case TW_MT_DATA_ACK: rv++; break; default: goto error; } } quit: TWCR = _BV(TWINT) | _BV(TWSTO) | _BV(TWEN); /* send stop condition */ return rv; error: rv = -1; goto quit; } /* * Wrapper around ee24xx_write_page() that repeats calling this * function until either an error has been returned, or all bytes * have been written. */ int ee24xx_write_bytes(uint16_t eeaddr, int len, uint8_t *buf) { int rv, total; total = 0; do { #if DEBUG printf("Calling ee24xx_write_page(%d, %d, %p)", eeaddr, len, buf); #endif rv = ee24xx_write_page(eeaddr, len, buf); #if DEBUG printf(" => %d\n", rv); #endif if (rv == -1) return -1; eeaddr += rv; len -= rv; buf += rv; total += rv; } while (len > 0); return total; } void error(void) { printf("error: TWI status %#x\n", twst); exit(0); } FILE mystdout = FDEV_SETUP_STREAM(uart_putchar, NULL, _FDEV_SETUP_WRITE); void main(void) { uint16_t a; int rv; uint8_t b[16]; uint8_t x; ioinit(); stdout = &mystdout; for (a = 0; a < 256;) { printf("%#04x: ", a); rv = ee24xx_read_bytes(a, 16, b); if (rv <= 0) error(); if (rv < 16) printf("warning: short read %d\n", rv); a += rv; for (x = 0; x < rv; x++) printf("%02x ", b[x]); putchar('\n'); } #define EE_WRITE(addr, str) ee24xx_write_bytes(addr, sizeof(str)-1, str) rv = EE_WRITE(55, "The quick brown fox jumps over the lazy dog."); if (rv < 0) error(); printf("Wrote %d bytes.\n", rv); for (a = 0; a < 256;) { printf("%#04x: ", a); rv = ee24xx_read_bytes(a, 16, b); if (rv <= 0) error(); if (rv < 16) printf("warning: short read %d\n", rv); a += rv; for (x = 0; x < rv; x++) printf("%02x ", b[x]); putchar('\n'); } printf("done.\n"); } avr-libc-1.8.0.orig/doc/examples/demo/0000755000000000000000000000000011732702554014361 5ustar avr-libc-1.8.0.orig/doc/examples/demo/Makefile0000644000000000000000000000643411732702554016030 0ustar PRG = demo OBJ = demo.o #MCU_TARGET = at90s2313 #MCU_TARGET = at90s2333 #MCU_TARGET = at90s4414 #MCU_TARGET = at90s4433 #MCU_TARGET = at90s4434 #MCU_TARGET = at90s8515 #MCU_TARGET = at90s8535 #MCU_TARGET = atmega128 #MCU_TARGET = atmega1280 #MCU_TARGET = atmega1281 #MCU_TARGET = atmega1284p #MCU_TARGET = atmega16 #MCU_TARGET = atmega163 #MCU_TARGET = atmega164p #MCU_TARGET = atmega165 #MCU_TARGET = atmega165p #MCU_TARGET = atmega168 #MCU_TARGET = atmega169 #MCU_TARGET = atmega169p #MCU_TARGET = atmega2560 #MCU_TARGET = atmega2561 #MCU_TARGET = atmega32 #MCU_TARGET = atmega324p #MCU_TARGET = atmega325 #MCU_TARGET = atmega3250 #MCU_TARGET = atmega329 #MCU_TARGET = atmega3290 #MCU_TARGET = atmega48 #MCU_TARGET = atmega64 #MCU_TARGET = atmega640 #MCU_TARGET = atmega644 #MCU_TARGET = atmega644p #MCU_TARGET = atmega645 #MCU_TARGET = atmega6450 #MCU_TARGET = atmega649 #MCU_TARGET = atmega6490 MCU_TARGET = atmega8 #MCU_TARGET = atmega8515 #MCU_TARGET = atmega8535 #MCU_TARGET = atmega88 #MCU_TARGET = attiny2313 #MCU_TARGET = attiny24 #MCU_TARGET = attiny25 #MCU_TARGET = attiny26 #MCU_TARGET = attiny261 #MCU_TARGET = attiny44 #MCU_TARGET = attiny45 #MCU_TARGET = attiny461 #MCU_TARGET = attiny84 #MCU_TARGET = attiny85 #MCU_TARGET = attiny861 OPTIMIZE = -O2 DEFS = LIBS = # You should not have to change anything below here. CC = avr-gcc # Override is only needed by avr-lib build system. override CFLAGS = -g -Wall $(OPTIMIZE) -mmcu=$(MCU_TARGET) $(DEFS) override LDFLAGS = -Wl,-Map,$(PRG).map OBJCOPY = avr-objcopy OBJDUMP = avr-objdump all: $(PRG).elf lst text eeprom $(PRG).elf: $(OBJ) $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS) # dependency: demo.o: demo.c iocompat.h clean: rm -rf *.o $(PRG).elf *.eps *.png *.pdf *.bak rm -rf *.lst *.map $(EXTRA_CLEAN_FILES) lst: $(PRG).lst %.lst: %.elf $(OBJDUMP) -h -S $< > $@ # Rules for building the .text rom images text: hex bin srec hex: $(PRG).hex bin: $(PRG).bin srec: $(PRG).srec %.hex: %.elf $(OBJCOPY) -j .text -j .data -O ihex $< $@ %.srec: %.elf $(OBJCOPY) -j .text -j .data -O srec $< $@ %.bin: %.elf $(OBJCOPY) -j .text -j .data -O binary $< $@ # Rules for building the .eeprom rom images eeprom: ehex ebin esrec ehex: $(PRG)_eeprom.hex ebin: $(PRG)_eeprom.bin esrec: $(PRG)_eeprom.srec %_eeprom.hex: %.elf $(OBJCOPY) -j .eeprom --change-section-lma .eeprom=0 -O ihex $< $@ \ || { echo empty $@ not generated; exit 0; } %_eeprom.srec: %.elf $(OBJCOPY) -j .eeprom --change-section-lma .eeprom=0 -O srec $< $@ \ || { echo empty $@ not generated; exit 0; } %_eeprom.bin: %.elf $(OBJCOPY) -j .eeprom --change-section-lma .eeprom=0 -O binary $< $@ \ || { echo empty $@ not generated; exit 0; } # Every thing below here is used by avr-libc's build system and can be ignored # by the casual user. FIG2DEV = fig2dev EXTRA_CLEAN_FILES = *.hex *.bin *.srec dox: eps png pdf eps: $(PRG).eps png: $(PRG).png pdf: $(PRG).pdf %.eps: %.fig $(FIG2DEV) -L eps $< $@ %.pdf: %.fig $(FIG2DEV) -L pdf $< $@ %.png: %.fig $(FIG2DEV) -L png $< $@ avr-libc-1.8.0.orig/doc/examples/demo/demo.dox0000644000000000000000000003240111732702554016021 0ustar /* Copyright (c) 2002,2005,2006 Theodore Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: demo.dox 1195 2007-01-22 23:34:24Z joerg_wunsch $ */ /** \defgroup demo_project A simple project \ingroup demos At this point, you should have the GNU tools configured, built, and installed on your system. In this chapter, we present a simple example of using the GNU tools in an AVR project. After reading this chapter, you should have a better feel as to how the tools are used and how a \c Makefile can be configured. \section demo_project_desc The Project This project will use the pulse-width modulator (\c PWM) to ramp an LED on and off every two seconds. An AT90S2313 processor will be used as the controller. The circuit for this demonstration is shown in the \ref demo_project_schematic "schematic diagram". If you have a development kit, you should be able to use it, rather than build the circuit, for this project. \note Meanwhile, the AT90S2313 became obsolete. Either use its successor, the (pin-compatible) ATtiny2313 for the project, or perhaps the ATmega8 or one of its successors (ATmega48/88/168) which have become quite popular since the original demo project had been established. For all these more modern devices, it is no longer necessary to use an external crystal for clocking as they ship with the internal 1 MHz oscillator enabled, so C1, C2, and Q1 can be omitted. Normally, for this experiment, the external circuitry on /RESET (R1, C3) can be omitted as well, leaving only the AVR, the LED, the bypass capacitor C4, and perhaps R2. For the ATmega8/48/88/168, use PB1 (pin 15 at the DIP-28 package) to connect the LED to. Additionally, this demo has been ported to many different other AVRs. The location of the respective OC pin varies between different AVRs, and it is mandated by the AVR hardware. \anchor demo_project_schematic \image html demo.png "Schematic of circuit for demo project" \image latex demo.eps "Schematic of circuit for demo project" width=4in The source code is given in \ref demo_project_src "demo.c". For the sake of this example, create a file called \c demo.c containing this source code. Some of the more important parts of the code are: \par Note [1]: As the AVR microcontroller series has been developed during the past years, new features have been added over time. Even though the basic concepts of the timer/counter1 are still the same as they used to be back in early 2001 when this simple demo was written initially, the names of registers and bits have been changed slightly to reflect the new features. Also, the port and pin mapping of the output compare match 1A (or 1 for older devices) pin which is used to control the LED varies between different AVRs. The file iocompat.h tries to abstract between all this differences using some preprocessor \c \#ifdef statements, so the actual program itself can operate on a common set of symbolic names. The macros defined by that file are: - \c OCR the name of the OCR register used to control the PWM (usually either OCR1 or OCR1A) - \c DDROC the name of the DDR (data direction register) for the OC output - \c OC1 the pin number of the OC1[A] output within its port - \c TIMER1_TOP the TOP value of the timer used for the PWM (1023 for 10-bit PWMs, 255 for devices that can only handle an 8-bit PWM) - \c TIMER1_PWM_INIT the initialization bits to be set into control register 1A in order to setup 10-bit (or 8-bit) phase and frequency correct PWM mode - \c TIMER1_CLOCKSOURCE the clock bits to set in the respective control register to start the PWM timer; usually the timer runs at full CPU clock for 10-bit PWMs, while it runs on a prescaled clock for 8-bit PWMs \par Note [2]: ISR() is a macro that marks the function as an interrupt routine. In this case, the function will get called when timer 1 overflows. Setting up interrupts is explained in greater detail in \ref avr_interrupts. \par Note [3]: The \c PWM is being used in 10-bit mode, so we need a 16-bit variable to remember the current value. \par Note [4]: This section determines the new value of the \c PWM. \par Note [5]: Here's where the newly computed value is loaded into the \c PWM register. Since we are in an interrupt routine, it is safe to use a 16-bit assignment to the register. Outside of an interrupt, the assignment should only be performed with interrupts disabled if there's a chance that an interrupt routine could also access this register (or another register that uses \c TEMP), see the appropriate \ref faq_16bitio "FAQ entry". \par Note [6]: This routine gets called after a reset. It initializes the \c PWM and enables interrupts. \par Note [7]: The main loop of the program does nothing -- all the work is done by the interrupt routine! The sleep_mode() puts the processor on sleep until the next interrupt, to conserve power. Of course, that probably won't be noticable as we are still driving a LED, it is merely mentioned here to demonstrate the basic principle. \par Note [8]: Early AVR devices saturate their outputs at rather low currents when sourcing current, so the LED can be connected directly, the resulting current through the LED will be about 15 mA. For modern parts (at least for the ATmega 128), however Atmel has drastically increased the IO source capability, so when operating at 5 V Vcc, R2 is needed. Its value should be about 150 Ohms. When operating the circuit at 3 V, it can still be omitted though. \section demo_project_src The Source Code \include demo.c \section demo_project_compile Compiling and Linking This first thing that needs to be done is compile the source. When compiling, the compiler needs to know the processor type so the \c -mmcu option is specified. The \c -Os option will tell the compiler to optimize the code for efficient space usage (at the possible expense of code execution speed). The \c -g is used to embed debug info. The debug info is useful for disassemblies and doesn't end up in the \c .hex files, so I usually specify it. Finally, the \c -c tells the compiler to compile and stop -- don't link. This demo is small enough that we could compile and link in one step. However, real-world projects will have several modules and will typically need to break up the building of the project into several compiles and one link. \verbatim $ avr-gcc -g -Os -mmcu=atmega8 -c demo.c \endverbatim The compilation will create a \c demo.o file. Next we link it into a binary called \c demo.elf. \verbatim $ avr-gcc -g -mmcu=atmega8 -o demo.elf demo.o \endverbatim It is important to specify the MCU type when linking. The compiler uses the \c -mmcu option to choose start-up files and run-time libraries that get linked together. If this option isn't specified, the compiler defaults to the 8515 processor environment, which is most certainly what you didn't want. \section demo_project_obj Examining the Object File \addindex disassembling Now we have a binary file. Can we do anything useful with it (besides put it into the processor?) The GNU Binutils suite is made up of many useful tools for manipulating object files that get generated. One tool is \c avr-objdump, which takes information from the object file and displays it in many useful ways. Typing the command by itself will cause it to list out its options. For instance, to get a feel of the application's size, the \c -h option can be used. The output of this option shows how much space is used in each of the sections (the \c .stab and \c .stabstr sections hold the debugging information and won't make it into the ROM file). An even more useful option is \c -S. This option disassembles the binary file and intersperses the source code in the output! This method is much better, in my opinion, than using the \c -S with the compiler because this listing includes routines from the libraries and the vector table contents. Also, all the "fix-ups" have been satisfied. In other words, the listing generated by this option reflects the actual code that the processor will run. \verbatim $ avr-objdump -h -S demo.elf > demo.lst \endverbatim Here's the output as saved in the \c demo.lst file: \verbinclude demo.lst \section demo_project_map Linker Map Files \c avr-objdump is very useful, but sometimes it's necessary to see information about the link that can only be generated by the linker. A map file contains this information. A map file is useful for monitoring the sizes of your code and data. It also shows where modules are loaded and which modules were loaded from libraries. It is yet another view of your application. To get a map file, I usually add -Wl,-Map,demo.map to my link command. Relink the application using the following command to generate \c demo.map (a portion of which is shown below). \verbatim $ avr-gcc -g -mmcu=atmega8 -Wl,-Map,demo.map -o demo.elf demo.o \endverbatim \dontinclude demo.map Some points of interest in the \c demo.map file are: \skip .rela.plt \until __ctors_start The \c .text segment (where program instructions are stored) starts at location 0x0. \skipline *(.fini2) \until __eeprom_end The last address in the \c .text segment is location \c 0x114 ( denoted by \c _etext ), so the instructions use up 276 bytes of FLASH. The \c .data segment (where initialized static variables are stored) starts at location \c 0x60, which is the first address after the register bank on an ATmega8 processor. The next available address in the \c .data segment is also location \c 0x60, so the application has no initialized data. The \c .bss segment (where uninitialized data is stored) starts at location \c 0x60. The next available address in the \c .bss segment is location 0x63, so the application uses 3 bytes of uninitialized data. The \c .eeprom segment (where EEPROM variables are stored) starts at location 0x0. The next available address in the \c .eeprom segment is also location 0x0, so there aren't any EEPROM variables. \section demo_ihex Generating Intel Hex Files We have a binary of the application, but how do we get it into the processor? Most (if not all) programmers will not accept a GNU executable as an input file, so we need to do a little more processing. The next step is to extract portions of the binary and save the information into \c .hex files. The GNU utility that does this is called \c avr-objcopy. The ROM contents can be pulled from our project's binary and put into the file demo.hex using the following command: \verbatim $ avr-objcopy -j .text -j .data -O ihex demo.elf demo.hex \endverbatim The resulting \c demo.hex file contains: \verbinclude demo.hex The \c -j option indicates that we want the information from the \c .text and \c .data segment extracted. If we specify the EEPROM segment, we can generate a \c .hex file that can be used to program the EEPROM: \verbatim $ avr-objcopy -j .eeprom --change-section-lma .eeprom=0 -O ihex demo.elf demo_eeprom.hex \endverbatim There is no \c demo_eeprom.hex file written, as that file would be empty. Starting with version 2.17 of the GNU binutils, the \c avr-objcopy command that used to generate the empty EEPROM files now aborts because of the empty input section \c .eeprom, so these empty files are not generated. It also signals an error to the Makefile which will be caught there, and makes it print a message about the empty file not being generated. \section demo_make Letting Make Build the Project Rather than type these commands over and over, they can all be placed in a make file. To build the demo project using \c make, save the following in a file called \c Makefile. \note This \c Makefile can only be used as input for the GNU version of \c make. \include demo/Makefile \section demo_sourceref Reference to the source code \htmlonly \endhtmlonly \latexonly The source code is installed under \texttt{\$prefix/share/doc/avr-libc/examples/demo/}, where \texttt{\$prefix} is a configuration option. For Unix systems, it is usually set to either \texttt{/usr} or \texttt{/usr/local}. \endlatexonly */ avr-libc-1.8.0.orig/doc/examples/demo/iocompat.h0000644000000000000000000001277211732702554016356 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * IO feature compatibility definitions for various AVRs. * * $Id: iocompat.h 1638 2008-03-17 21:52:00Z joerg_wunsch $ */ #if !defined(IOCOMPAT_H) #define IOCOMPAT_H 1 /* * Device-specific adjustments: * * Supply definitions for the location of the OCR1[A] port/pin, the * name of the OCR register controlling the PWM, and adjust interrupt * vector names that differ from the one used in demo.c * [TIMER1_OVF_vect]. */ #if defined(__AVR_AT90S2313__) # define OC1 PB3 # define OCR OCR1 # define DDROC DDRB # define TIMER1_OVF_vect TIMER1_OVF1_vect #elif defined(__AVR_AT90S2333__) || defined(__AVR_AT90S4433__) # define OC1 PB1 # define DDROC DDRB # define OCR OCR1 #elif defined(__AVR_AT90S4414__) || defined(__AVR_AT90S8515__) || \ defined(__AVR_AT90S4434__) || defined(__AVR_AT90S8535__) || \ defined(__AVR_ATmega163__) || defined(__AVR_ATmega8515__) || \ defined(__AVR_ATmega8535__) || \ defined(__AVR_ATmega164P__) || defined(__AVR_ATmega324P__) || \ defined(__AVR_ATmega644__) || defined(__AVR_ATmega644P__) || \ defined(__AVR_ATmega1284P__) # define OC1 PD5 # define DDROC DDRD # define OCR OCR1A # if !defined(TIMSK) /* new ATmegas */ # define TIMSK TIMSK1 # endif #elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega48__) || \ defined(__AVR_ATmega88__) || defined(__AVR_ATmega168__) # define OC1 PB1 # define DDROC DDRB # define OCR OCR1A # if !defined(TIMSK) /* ATmega48/88/168 */ # define TIMSK TIMSK1 # endif /* !defined(TIMSK) */ #elif defined(__AVR_ATtiny2313__) # define OC1 PB3 # define OCR OCR1A # define DDROC DDRB #elif defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || \ defined(__AVR_ATtiny84__) # define OC1 PA6 # define DDROC DDRA # if !defined(OCR1A) # /* work around misspelled name in avr-libc 1.4.[0..1] */ # define OCR OCRA1 # else # define OCR OCR1A # endif # define TIMSK TIMSK1 # define TIMER1_OVF_vect TIM1_OVF_vect /* XML and datasheet mismatch */ #elif defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || \ defined(__AVR_ATtiny85__) /* Timer 1 is only an 8-bit timer on these devices. */ # define OC1 PB1 # define DDROC DDRB # define OCR OCR1A # define TCCR1A TCCR1 # define TCCR1B TCCR1 # define TIMER1_OVF_vect TIM1_OVF_vect # define TIMER1_TOP 255 /* only 8-bit PWM possible */ # define TIMER1_PWM_INIT _BV(PWM1A) | _BV(COM1A1) # define TIMER1_CLOCKSOURCE _BV(CS12) /* use 1/8 prescaler */ #elif defined(__AVR_ATtiny26__) /* Rather close to ATtinyX5 but different enough for its own section. */ # define OC1 PB1 # define DDROC DDRB # define OCR OCR1A # define TIMER1_OVF_vect TIMER1_OVF1_vect # define TIMER1_TOP 255 /* only 8-bit PWM possible */ # define TIMER1_PWM_INIT _BV(PWM1A) | _BV(COM1A1) # define TIMER1_CLOCKSOURCE _BV(CS12) /* use 1/8 prescaler */ /* * Without setting OCR1C to TOP, the ATtiny26 does not trigger an * overflow interrupt in PWM mode. */ # define TIMER1_SETUP_HOOK() OCR1C = 255 #elif defined(__AVR_ATtiny261__) || defined(__AVR_ATtiny461__) || \ defined(__AVR_ATtiny861__) # define OC1 PB1 # define DDROC DDRB # define OCR OCR1A # define TIMER1_PWM_INIT _BV(WGM10) | _BV(PWM1A) | _BV(COM1A1) /* * While timer 1 could be operated in 10-bit mode on these devices, * the handling of the 10-bit IO registers is more complicated than * that of the 16-bit registers of other AVR devices (no combined * 16-bit IO operations possible), so we restrict this demo to 8-bit * mode which is pretty standard. */ # define TIMER1_TOP 255 # define TIMER1_CLOCKSOURCE _BV(CS12) /* use 1/8 prescaler */ #elif defined(__AVR_ATmega32__) || defined(__AVR_ATmega16__) # define OC1 PD5 # define DDROC DDRD # define OCR OCR1A #elif defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__) || \ defined(__AVR_ATmega165__) || defined(__AVR_ATmega169__) || \ defined(__AVR_ATmega325__) || defined(__AVR_ATmega3250__) || \ defined(__AVR_ATmega645__) || defined(__AVR_ATmega6450__) || \ defined(__AVR_ATmega329__) || defined(__AVR_ATmega3290__) || \ defined(__AVR_ATmega649__) || defined(__AVR_ATmega6490__) || \ defined(__AVR_ATmega640__) || \ defined(__AVR_ATmega1280__) || defined(__AVR_ATmega1281__) || \ defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__) # define OC1 PB5 # define DDROC DDRB # define OCR OCR1A # if !defined(PB5) /* work around missing bit definition */ # define PB5 5 # endif # if !defined(TIMSK) /* new ATmegas */ # define TIMSK TIMSK1 # endif #else # error "Don't know what kind of MCU you are compiling for" #endif /* * Map register names for older AVRs here. */ #if !defined(COM1A1) # define COM1A1 COM11 #endif #if !defined(WGM10) # define WGM10 PWM10 # define WGM11 PWM11 #endif /* * Provide defaults for device-specific macros unless overridden * above. */ #if !defined(TIMER1_TOP) # define TIMER1_TOP 1023 /* 10-bit PWM */ #endif #if !defined(TIMER1_PWM_INIT) # define TIMER1_PWM_INIT _BV(WGM10) | _BV(WGM11) | _BV(COM1A1) #endif #if !defined(TIMER1_CLOCKSOURCE) # define TIMER1_CLOCKSOURCE _BV(CS10) /* full clock */ #endif #endif /* !defined(IOCOMPAT_H) */ avr-libc-1.8.0.orig/doc/examples/demo/demo.fig0000644000000000000000000002127711732702554016005 0ustar #FIG 3.2 Landscape Center Inches Letter 100.00 Single -2 1200 2 0 32 #727272 1 4 0 1 18 7 50 0 -1 0.000 1 0.0000 4275 2250 75 75 4350 2250 4200 2250 1 3 0 1 12 12 49 0 20 0.000 1 0.0000 2400 3750 40 40 2400 3750 2440 3750 1 3 0 1 12 12 49 0 20 0.000 1 0.0000 1200 3525 40 40 1200 3525 1240 3525 1 3 0 1 12 12 49 0 20 0.000 1 0.0000 1200 2250 40 40 1200 2250 1240 2250 1 3 0 1 12 12 49 0 20 0.000 1 0.0000 2400 2250 40 40 2400 2250 2440 2250 1 3 0 1 12 12 49 0 20 0.000 1 0.0000 2400 2775 40 40 2400 2775 2440 2775 1 3 0 1 12 12 49 0 20 0.000 1 0.0000 2400 3150 40 40 2400 3150 2440 3150 1 3 0 1 12 12 49 0 20 0.000 1 0.0000 3675 3150 40 40 3675 3150 3715 3150 1 3 0 1 12 12 49 0 20 0.000 1 0.0000 3675 2775 40 40 3675 2775 3715 2775 2 2 0 1 18 7 50 0 -1 0.000 0 0 7 0 0 5 4350 1950 6300 1950 6300 5550 4350 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17\001 4 0 32 50 0 14 12 0.0000 4 120 210 6450 2775 16\001 4 0 32 50 0 14 12 0.0000 4 120 210 6450 3000 15\001 4 0 32 50 0 14 12 0.0000 4 120 210 6450 3225 14\001 4 0 32 50 0 14 12 0.0000 4 120 210 6450 3450 13\001 4 0 32 50 0 14 12 0.0000 4 120 210 6450 3675 12\001 4 0 32 50 0 14 12 0.0000 4 120 210 6450 4050 11\001 4 0 32 50 0 14 12 0.0000 4 120 105 6450 4275 9\001 4 0 32 50 0 14 12 0.0000 4 120 105 6450 4500 8\001 4 0 32 50 0 14 12 0.0000 4 120 105 6450 4725 7\001 4 0 32 50 0 14 12 0.0000 4 120 105 6450 4950 6\001 4 0 32 50 0 14 12 0.0000 4 120 105 6450 5175 3\001 4 0 32 50 0 14 12 0.0000 4 120 105 6450 5400 2\001 4 1 32 50 0 14 12 0.0000 4 120 1050 5325 5700 AT90S2313P\001 4 2 32 50 0 14 12 0.0000 4 135 840 6225 5475 (RXD)PD0\001 4 2 32 50 0 14 12 0.0000 4 135 840 6225 5250 (TXD)PD1\001 4 2 32 50 0 14 12 0.0000 4 135 945 6225 5025 (INT0)PD2\001 4 2 32 50 0 14 12 0.0000 4 135 945 6225 4800 (INT1)PD3\001 4 2 32 50 0 14 12 0.0000 4 135 735 6225 4575 (T0)PD4\001 4 2 32 50 0 14 12 0.0000 4 135 735 6225 4350 (T1)PD5\001 4 2 32 50 0 14 12 0.0000 4 135 840 6225 4125 (ICP)PD6\001 4 2 32 50 0 14 12 0.0000 4 135 945 6225 3750 (AIN0)PB0\001 4 2 32 50 0 14 12 0.0000 4 135 945 6225 3525 (AIN1)PB1\001 4 2 32 50 0 14 12 0.0000 4 120 315 6225 3300 PB2\001 4 2 32 50 0 14 12 0.0000 4 135 840 6225 3075 (OCI)PB3\001 4 2 32 50 0 14 12 0.0000 4 120 315 6225 2850 PB4\001 4 2 32 50 0 14 12 0.0000 4 135 945 6225 2400 (MISO)PB6\001 4 2 32 50 0 14 12 0.0000 4 135 840 6225 2175 (SCK)PB7\001 4 0 32 50 0 14 12 0.0000 4 105 525 4425 2325 RESET\001 4 0 32 50 0 14 12 0.0000 4 120 525 4425 2850 XTAL2\001 4 0 32 50 0 14 12 0.0000 4 120 525 4425 3225 XTAL1\001 4 0 32 50 0 14 12 0.0000 4 105 315 4425 3600 VCC\001 4 0 32 50 0 14 12 0.0000 4 105 315 4425 3825 GND\001 4 2 32 50 0 14 12 0.0000 4 135 945 6225 2625 (MOSI)PB5\001 4 0 32 50 0 14 12 1.5708 4 150 210 3600 2775 Q1\001 4 0 32 50 0 14 12 1.5708 4 120 420 3900 2775 4mhz\001 4 1 32 50 0 14 12 0.0000 4 105 315 1200 4950 GND\001 4 1 32 50 0 14 12 0.0000 4 105 315 2400 4425 GND\001 4 1 32 50 0 14 12 1.5708 4 120 420 1500 4050 .1uf\001 4 1 32 50 0 14 12 1.5708 4 120 210 975 4050 C4\001 4 1 32 50 0 14 12 0.0000 4 105 315 1200 1575 VCC\001 4 1 32 50 0 14 12 0.0000 4 120 210 1800 2100 R1\001 4 1 32 50 0 14 12 0.0000 4 120 315 1800 2550 20K\001 4 1 32 50 0 14 12 1.5708 4 120 525 2700 2550 .01uf\001 4 1 32 50 0 14 12 1.5708 4 120 210 2175 2550 C3\001 4 1 32 50 0 14 12 0.0000 4 150 420 3225 3075 18pf\001 4 1 32 50 0 14 12 0.0000 4 120 210 3225 2550 C2\001 4 1 32 50 0 14 12 0.0000 4 150 420 2775 3450 18pf\001 4 1 32 50 0 14 12 0.0000 4 120 210 2775 2925 C1\001 4 1 32 50 0 14 12 0.0000 4 75 105 7500 2775 *\001 4 1 32 50 0 14 12 0.0000 4 135 1260 7650 3300 See note [8]\001 4 1 32 50 0 14 12 0.0000 4 120 210 7350 2850 R2\001 4 1 32 50 0 14 12 0.0000 4 120 630 8475 2700 LED5MM\001 4 1 32 50 0 14 12 0.0000 4 120 210 8475 2850 D1\001 4 1 32 50 0 14 12 0.0000 4 105 315 9150 3600 GND\001 avr-libc-1.8.0.orig/doc/examples/demo/demo.c0000644000000000000000000000412011732702554015446 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * Simple AVR demonstration. Controls a LED that can be directly * connected from OC1/OC1A to GND. The brightness of the LED is * controlled with the PWM. After each period of the PWM, the PWM * value is either incremented or decremented, that's all. * * $Id: demo.c 1637 2008-03-17 21:49:41Z joerg_wunsch $ */ #include #include #include #include #include "iocompat.h" /* Note [1] */ enum { UP, DOWN }; ISR (TIMER1_OVF_vect) /* Note [2] */ { static uint16_t pwm; /* Note [3] */ static uint8_t direction; switch (direction) /* Note [4] */ { case UP: if (++pwm == TIMER1_TOP) direction = DOWN; break; case DOWN: if (--pwm == 0) direction = UP; break; } OCR = pwm; /* Note [5] */ } void ioinit (void) /* Note [6] */ { /* Timer 1 is 10-bit PWM (8-bit PWM on some ATtinys). */ TCCR1A = TIMER1_PWM_INIT; /* * Start timer 1. * * NB: TCCR1A and TCCR1B could actually be the same register, so * take care to not clobber it. */ TCCR1B |= TIMER1_CLOCKSOURCE; /* * Run any device-dependent timer 1 setup hook if present. */ #if defined(TIMER1_SETUP_HOOK) TIMER1_SETUP_HOOK(); #endif /* Set PWM value to 0. */ OCR = 0; /* Enable OC1 as output. */ DDROC = _BV (OC1); /* Enable timer 1 overflow interrupt. */ TIMSK = _BV (TOIE1); sei (); } int main (void) { ioinit (); /* loop forever, the interrupts are doing the rest */ for (;;) /* Note [7] */ sleep_mode(); return (0); } avr-libc-1.8.0.orig/doc/examples/largedemo/0000755000000000000000000000000011732702554015374 5ustar avr-libc-1.8.0.orig/doc/examples/largedemo/largedemo-setup.jpg0000644000000000000000000021407611732702554021205 0ustar ˙Ĝ˙àJFIFHH˙ŝlargdemo setup˙ÛC    $.' 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CC = avr-gcc # Override is only needed by avr-lib build system. override CFLAGS = -g -Wall $(OPTIMIZE) -mmcu=$(MCU_TARGET) $(DEFS) override LDFLAGS = -Wl,-Map,$(PRG).map OBJCOPY = avr-objcopy OBJDUMP = avr-objdump all: $(PRG).elf lst text eeprom $(PRG).elf: $(OBJ) $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS) clean: rm -rf *.o $(PRG).elf *.eps *.png *.pdf *.bak rm -rf *.lst *.map $(EXTRA_CLEAN_FILES) lst: $(PRG).lst %.lst: %.elf $(OBJDUMP) -h -S $< > $@ # Rules for building the .text rom images text: hex bin srec hex: $(PRG).hex bin: $(PRG).bin srec: $(PRG).srec %.hex: %.elf $(OBJCOPY) -j .text -j .data -O ihex $< $@ %.srec: %.elf $(OBJCOPY) -j .text -j .data -O srec $< $@ %.bin: %.elf $(OBJCOPY) -j .text -j .data -O binary $< $@ # Rules for building the .eeprom rom images eeprom: ehex ebin esrec ehex: $(PRG)_eeprom.hex ebin: $(PRG)_eeprom.bin esrec: $(PRG)_eeprom.srec %_eeprom.hex: %.elf $(OBJCOPY) -j .eeprom --change-section-lma .eeprom=0 -O ihex $< $@ %_eeprom.srec: %.elf $(OBJCOPY) -j .eeprom --change-section-lma .eeprom=0 -O srec $< $@ %_eeprom.bin: %.elf $(OBJCOPY) -j .eeprom --change-section-lma .eeprom=0 -O binary $< $@ # Every thing below here is used by avr-libc's build system and can be ignored # by the casual user. JPEGFILES = largedemo-setup.jpg largedemo-wiring.jpg \ largedemo-wiring2.jpg JPEG2PNM = jpegtopnm PNM2EPS = pnmtops JPEGRESOLUTION = 180 EXTRA_CLEAN_FILES = *.hex *.bin *.srec *.eps dox: ${JPEGFILES:.jpg=.eps} %.eps: %.jpg $(JPEG2PNM) $< |\ $(PNM2EPS) -noturn -dpi $(JPEGRESOLUTION) -equalpixels \ > $@ avr-libc-1.8.0.orig/doc/examples/largedemo/largedemo.dox0000644000000000000000000004213711732702554020056 0ustar /* Copyright (c) 2005,2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: largedemo.dox 1190 2007-01-19 22:17:10Z joerg_wunsch $ */ /** \defgroup largedemo A more sophisticated project \ingroup demos This project extends the basic idea of the \ref demo_project "simple project" to control a LED with a PWM output, but adds methods to adjust the LED brightness. It employs a lot of the basic concepts of avr-libc to achieve that goal. Understanding this project assumes the simple project has been understood in full, as well as being acquainted with the basic hardware concepts of an AVR microcontroller. \section largedemo_hw Hardware setup The demo is set up in a way so it can be run on the ATmega16 that ships with the STK500 development kit. The only external part needed is a potentiometer attached to the ADC. It is connected to a 10-pin ribbon cable for port A, both ends of the potentiometer to pins 9 (GND) and 10 (VCC), and the wiper to pin 1 (port A0). A bypass capacitor from pin 1 to pin 9 (like 47 nF) is recommendable. \image html largedemo-setup.jpg "Setup of the STK500" \image latex largedemo-setup.eps "Setup of the STK500" width=12cm The coloured patch cables are used to provide various interconnections. As there are only four of them in the STK500, there are two options to connect them for this demo. The second option for the yellow-green cable is shown in parenthesis in the table. Alternatively, the "squid" cable from the JTAG ICE kit can be used if available.
PortHeaderColorFunctionConnect to
D0 1 brown RxD RXD of the RS-232 header
D1 2 grey TxD TXD of the RS-232 header
D2 3 black button "down" SW0 (pin 1 switches header)
D3 4 red button "up" SW1 (pin 2 switches header)
D4 5 green button "ADC" SW2 (pin 3 switches header)
D5 6 blue LED LED0 (pin 1 LEDs header)
D6 7 (green)clock out LED1 (pin 2 LEDs header)
D7 8 white 1-second flashLED2 (pin 3 LEDs header)
GND9 unused
VCC10 unused
\image html largedemo-wiring.jpg "Wiring of the STK500" \image latex largedemo-wiring.eps "Wiring of the STK500" width=12cm The following picture shows the alternate wiring where LED1 is connected but SW2 is not: \image html largedemo-wiring2.jpg "Wiring option #2 of the STK500" \image latex largedemo-wiring2.eps "Wiring option #2 of the STK500" width=12cm As an alternative, this demo can also be run on the popular ATmega8 controller, or its successor ATmega88 as well as the ATmega48 and ATmega168 variants of the latter. These controllers do not have a port named "A", so their ADC inputs are located on port C instead, thus the potentiometer needs to be attached to port C. Likewise, the OC1A output is not on port D pin 5 but on port B pin 1 (PB1). Thus, the above cabling scheme needs to be changed so that PB1 connects to the LED0 pin. (PD6 remains unconnected.) When using the STK500, use one of the jumper cables for this connection. All other port D pins should be connected the same way as described for the ATmega16 above. When not using an STK500 starter kit, attach the LEDs through some resistor to Vcc (low-active LEDs), and attach pushbuttons from the respective input pins to GND. The internal pull-up resistors are enabled for the pushbutton pins, so no external resistors are needed. Finally, the demo has been ported to the ATtiny2313 as well. As this AVR does not offer an ADC, everything related to handling the ADC is disabled in the code for that MCU type. Also, port D of this controller type only features 6 pins, so the 1-second flash LED had to be moved from PD6 to PD4. (PD4 is used as the ADC control button on the other MCU types, but that is not needed here.) OC1A is located at PB3 on this device. The \c MCU_TARGET macro in the Makefile needs to be adjusted appropriately for the alternative controller types. The flash ROM and RAM consumption of this demo are way below the resources of even an ATmega48, and still well within the capabilities of an ATtiny2313. The major advantage of experimenting with the ATmega16 (in addition that it ships together with an STK500 anyway) is that it can be debugged online via JTAG. Likewise, the ATmega48/88/168 and ATtiny2313 devices can be debugged through debugWire, using the Atmel JTAG ICE mkII or the low-cost AVR Dragon. Note that in the explanation below, all port/pin names are applicable to the ATmega16 setup. \section largedemo_overview Functional overview PD6 will be toggled with each internal clock tick (approx. 10 ms). PD7 will flash once per second. PD0 and PD1 are configured as UART IO, and can be used to connect the demo kit to a PC (9600 Bd, 8N1 frame format). The demo application talks to the serial port, and it can be controlled from the serial port. PD2 through PD4 are configured as inputs, and control the application unless control has been taken over by the serial port. Shorting PD2 to GND will decrease the current PWM value, shorting PD3 to GND will increase it. While PD4 is shorted to GND, one ADC conversion for channel 0 (ADC input is on PA0) will be triggered each internal clock tick, and the resulting value will be used as the PWM value. So the brightness of the LED follows the analog input value on PC0. VAREF on the STK500 should be set to the same value as VCC. When running in serial control mode, the function of the watchdog timer can be demonstrated by typing an `r'. This will make the demo application run in a tight loop without retriggering the watchdog so after some seconds, the watchdog will reset the MCU. This situation can be figured out on startup by reading the MCUCSR register. The current value of the PWM is backed up in an EEPROM cell after about 3 seconds of idle time after the last change. If that EEPROM cell contains a reasonable (i. e. non-erased) value at startup, it is taken as the initial value for the PWM. This virtually preserves the last value across power cycles. By not updating the EEPROM immmediately but only after a timeout, EEPROM wear is reduced considerably compared to immediately writing the value at each change. \section largedemo_code A code walkthrough This section explains the ideas behind individual parts of the code. The \ref largedemo_src "source code" has been divided into numbered parts, and the following subsections explain each of these parts. \subsection largedemo_code_p1 Part 1: Macro definitions A number of preprocessor macros are defined to improve readability and/or portability of the application. The first macros describe the IO pins our LEDs and pushbuttons are connected to. This provides some kind of mini-HAL (hardware abstraction layer) so should some of the connections be changed, they don't need to be changed inside the code but only on top. Note that the location of the PWM output itself is mandated by the hardware, so it cannot be easily changed. As the ATmega48/88/168 controllers belong to a more recent generation of AVRs, a number of register and bit names have been changed there, so they are mapped back to their ATmega8/16 equivalents to keep the actual program code portable. The name \c F_CPU is the conventional name to describe the CPU clock frequency of the controller. This demo project just uses the internal calibrated 1 MHz RC oscillator that is enabled by default. Note that when using the <util/delay.h> functions, \c F_CPU needs to be defined before including that file. The remaining macros have their own comments in the source code. The macro \c TMR1_SCALE shows how to use the preprocessor and the compiler's constant expression computation to calculate the value of timer 1's post-scaler in a way so it only depends on \c F_CPU and the desired software clock frequency. While the formula looks a bit complicated, using a macro offers the advantage that the application will automatically scale to new target softclock or master CPU frequencies without having to manually re-calculate hardcoded constants. \subsection largedemo_code_p2 Part 2: Variable definitions The \c intflags structure demonstrates a way to allocate bit variables in memory. Each of the interrupt service routines just sets one bit within that structure, and the application's main loop then monitors the bits in order to act appropriately. Like all variables that are used to communicate values between an interrupt service routine and the main application, it is declared \ref faq_volatile "volatile". The variable \c ee_pwm is not a variable in the classical C sense that could be used as an lvalue or within an expression to obtain its value. Instead, the \code __attribute__((section(".eeprom"))) \endcode marks it as belonging to the \ref sec_dot_eeprom "EEPROM section". This section is merely used as a placeholder so the compiler can arrange for each individual variable's location in EEPROM. The compiler will also keep track of initial values assigned, and usually the Makefile is arranged to extract these initial values into a separate load file (\c largedemo_eeprom.* in this case) that can be used to initialize the EEPROM. The actual EEPROM IO must be performed manually. Similarly, the variable \c mcucsr is kept in the \ref sec_dot_noinit ".noinit" section in order to prevent it from being cleared upon application startup. \subsection largedemo_code_p3 Part 3: Interrupt service routines The ISR to handle timer 1's overflow interrupt arranges for the software clock. While timer 1 runs the PWM, it calls its overflow handler rather frequently, so the \c TMR1_SCALE value is used as a postscaler to reduce the internal software clock frequency further. If the software clock triggers, it sets the \c tmr_int bitfield, and defers all further tasks to the main loop. The ADC ISR just fetches the value from the ADC conversion, disables the ADC interrupt again, and announces the presence of the new value in the \c adc_int bitfield. The interrupt is kept disabled while not needed, because the ADC will also be triggered by executing the SLEEP instruction in idle mode (which is the default sleep mode). Another option would be to turn off the ADC completely here, but that increases the ADC's startup time (not that it would matter much for this application). \subsection largedemo_code_p4 Part 4: Auxiliary functions The function \c handle_mcucsr() uses two \c __attribute__ declarators to achieve specific goals. First, it will instruct the compiler to place the generated code into the \ref sec_dot_init ".init3" section of the output. Thus, it will become part of the application initialization sequence. This is done in order to fetch (and clear) the reason of the last hardware reset from \c MCUCSR as early as possible. There is a short period of time where the next reset could already trigger before the current reason has been evaluated. This also explains why the variable \c mcucsr that mirrors the register's value needs to be placed into the .noinit section, because otherwise the default initialization (which happens after .init3) would blank the value again. As the initialization code is not called using CALL/RET instructions but rather concatenated together, the compiler needs to be instructed to omit the entire function prologue and epilogue. This is performed by the \e naked attribute. So while syntactically, \c handle_mcucsr() is a function to the compiler, the compiler will just emit the instructions for it without setting up any stack frame, and not even a RET instruction at the end. Function \c ioinit() centralizes all hardware setup. The very last part of that function demonstrates the use of the EEPROM variable \c ee_pwm to obtain an EEPROM address that can in turn be applied as an argument to \c eeprom_read_word(). The following functions handle UART character and string output. (UART input is handled by an ISR.) There are two string output functions, \c printstr() and \c printstr_p(). The latter function fetches the string from \ref avr_pgmspace "program memory". Both functions translate a newline character into a carriage return/newline sequence, so a simple \c \\n can be used in the source code. The function \c set_pwm() propagates the new PWM value to the PWM, performing range checking. When the value has been changed, the new percentage will be announced on the serial link. The current value is mirrored in the variable \c pwm so others can use it in calculations. In order to allow for a simple calculation of a percentage value without requiring floating-point mathematics, the maximal value of the PWM is restricted to 1000 rather than 1023, so a simple division by 10 can be used. Due to the nature of the human eye, the difference in LED brightness between 1000 and 1023 is not noticable anyway. \subsection largedemo_code_p5 Part 5: main() At the start of \c main(), a variable \c mode is declared to keep the current mode of operation. An enumeration is used to improve the readability. By default, the compiler would allocate a variable of type \e int for an enumeration. The \e packed attribute declarator instructs the compiler to use the smallest possible integer type (which would be an 8-bit type here). After some initialization actions, the application's main loop follows. In an embedded application, this is normally an infinite loop as there is nothing an application could "exit" into anyway. At the beginning of the loop, the watchdog timer will be retriggered. If that timer is not triggered for about 2 seconds, it will issue a hardware reset. Care needs to be taken that no code path blocks longer than this, or it needs to frequently perform watchdog resets of its own. An example of such a code path would be the string IO functions: for an overly large string to print (about 2000 characters at 9600 Bd), they might block for too long. The loop itself then acts on the interrupt indication bitfields as appropriate, and will eventually put the CPU on sleep at its end to conserve power. The first interrupt bit that is handled is the (software) timer, at a frequency of approximately 100 Hz. The \c CLOCKOUT pin will be toggled here, so e. g. an oscilloscope can be used on that pin to measure the accuracy of our software clock. Then, the LED flasher for LED2 ("We are alive"-LED) is built. It will flash that LED for about 50 ms, and pause it for another 950 ms. Various actions depending on the operation mode follow. Finally, the 3-second backup timer is implemented that will write the PWM value back to EEPROM once it is not changing anymore. The ADC interrupt will just adjust the PWM value only. Finally, the UART Rx interrupt will dispatch on the last character received from the UART. All the string literals that are used as informational messages within \c main() are placed in \ref avr_pgmspace "program memory" so no SRAM needs to be allocated for them. This is done by using the PSTR macro, and passing the string to \c printstr_p(). \section largedemo_src The source code \htmlonly Source file: largedemo.c \endhtmlonly \latexonly The source code is installed under \texttt{\$prefix/share/doc/avr-libc/examples/largedemo/largedemo.c}, where \texttt{\$prefix} is a configuration option. For Unix systems, it is usually set to either \texttt{/usr} or \texttt{/usr/local}. \endlatexonly */ avr-libc-1.8.0.orig/doc/examples/largedemo/largedemo-wiring.jpg0000644000000000000000000013120711732702554021336 0ustar ˙Ĝ˙àJFIFHH˙ŝlargedemo wiring option #1˙ÛC    $.' ",#(7),01444'9=82<.342˙ÛC  2!!22222222222222222222222222222222222222222222222222˙À! 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ÊÊHA'˙İÛ÷óĞEñúÖVUWŜY¤˙Ùavr-libc-1.8.0.orig/doc/examples/largedemo/largedemo.c0000644000000000000000000002765011732702554017511 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * More advanced AVR demonstration. Controls a LED attached to OCR1A. * The brightness of the LED is controlled with the PWM. A number of * methods are implemented to control that PWM. * * $Id: largedemo.c 1190 2007-01-19 22:17:10Z joerg_wunsch $ */ #include #include #include #include #include #include #include #include /* Part 1: Macro definitions */ #define CONTROL_PORT PORTD #define CONTROL_DDR DDRD #if defined(__AVR_ATtiny2313__) /* no PD7 and no ADC available on ATtiny2313 */ # define TRIGGER_DOWN PD2 # define TRIGGER_UP PD3 # define FLASH PD4 # define CLOCKOUT PD6 #else # define TRIGGER_DOWN PD2 # define TRIGGER_UP PD3 # define TRIGGER_ADC PD4 # define CLOCKOUT PD6 # define FLASH PD7 #endif #if defined(__AVR_ATmega16__) # define PWMDDR DDRD # define PWMOUT PD5 #elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega48__) ||\ defined(__AVR_ATmega88__) || defined(__AVR_ATmega168__) # define PWMDDR DDRB # define PWMOUT PB1 #elif defined(__AVR_ATtiny2313__) # define PWMDDR DDRB # define PWMOUT PB3 # define HAVE_ADC 0 # define USART_RXC_vect USART_RX_vect # define MCUCSR MCUSR #else # error "Unsupported MCU type" #endif #if defined(__AVR_ATmega48__) || defined(__AVR_ATmega88__) ||\ defined(__AVR_ATmega168__) /* map ATmega8/16 names to ATmegaX8 names */ # define USART_RXC_vect USART_RX_vect # define UDR UDR0 # define UCSRA UCSR0A # define UCSRB UCSR0B # define FE FE0 # define TXEN TXEN0 # define RXEN RXEN0 # define RXCIE RXCIE0 # define UDRE UDRE0 # define U2X U2X0 # define UBRRL UBRR0L # define TIMSK TIMSK1 # define MCUCSR MCUSR #endif #if !defined(HAVE_ADC) # define HAVE_ADC 1 #endif #define F_CPU 1000000UL /* CPU clock in Hertz */ #define SOFTCLOCK_FREQ 100 /* internal software clock */ /* * Timeout to wait after last PWM change till updating the EEPROM. * Measured in internal clock ticks (approx. 100 Hz). */ #define EE_UPDATE_TIME (3 * SOFTCLOCK_FREQ) /* ca. 3 seconds */ /* * Timer1 overflow interrupt will be called with F_CPU / 2048 * frequency. This interrupt routine further divides that value, * resulting in an internal update interval of approx. 10 ms. * (The complicated looking scaling by 10 / addition of 9 is * poor man's fixed-point rounding algorithm...) */ #define TMR1_SCALE ((F_CPU * 10) / (2048UL * SOFTCLOCK_FREQ) + 9) / 10 /* Part 2: Variable definitions */ /* * Bits that are set inside interrupt routines, and watched outside in * the program's main loop. */ volatile struct { uint8_t tmr_int: 1; uint8_t adc_int: 1; uint8_t rx_int: 1; } intflags; /* * Last character read from the UART. */ volatile char rxbuff; /* * Last value read from ADC. */ volatile uint16_t adcval; /* * Where to store the PWM value in EEPROM. This is used in order * to remember the value across a RESET or power cycle. */ uint16_t ee_pwm __attribute__((section(".eeprom"))) = 42; /* * Current value of the PWM. */ int16_t pwm; /* * EEPROM backup timer. Bumped by the PWM update routine. If it * expires, the current PWM value will be written to EEPROM. */ int16_t pwm_backup_tmr; /* * Mirror of the MCUCSR register, taken early during startup. */ uint8_t mcucsr __attribute__((section(".noinit"))); /* Part 3: Interrupt service routines */ ISR(TIMER1_OVF_vect) { static uint8_t scaler = TMR1_SCALE; if (--scaler == 0) { scaler = TMR1_SCALE; intflags.tmr_int = 1; } } #if HAVE_ADC /* * ADC conversion complete. Fetch the 10-bit value, and feed the * PWM with it. */ ISR(ADC_vect) { adcval = ADCW; ADCSRA &= ~_BV(ADIE); /* disable ADC interrupt */ intflags.adc_int = 1; } #endif /* HAVE_ADC */ /* * UART receive interrupt. Fetch the character received and buffer * it, unless there was a framing error. Note that the main loop * checks the received character only once per 10 ms. */ ISR(USART_RXC_vect) { uint8_t c; c = UDR; if (bit_is_clear(UCSRA, FE)) { rxbuff = c; intflags.rx_int = 1; } } /* Part 4: Auxiliary functions */ /* * Read out and reset MCUCSR early during startup. */ void handle_mcucsr(void) __attribute__((section(".init3"))) __attribute__((naked)); void handle_mcucsr(void) { mcucsr = MCUCSR; MCUCSR = 0; } /* * Do all the startup-time peripheral initializations. */ static void ioinit(void) { uint16_t pwm_from_eeprom; /* * Set up the 16-bit timer 1. * * Timer 1 will be set up as a 10-bit phase-correct PWM (WGM10 and * WGM11 bits), with OC1A used as PWM output. OC1A will be set when * up-counting, and cleared when down-counting (COM1A1|COM1A0), this * matches the behaviour needed by the STK500's low-active LEDs. * The timer will runn on full MCU clock (1 MHz, CS10 in TCCR1B). */ TCCR1A = _BV(WGM10) | _BV(WGM11) | _BV(COM1A1) | _BV(COM1A0); TCCR1B = _BV(CS10); OCR1A = 0; /* set PWM value to 0 */ /* enable pull-ups for pushbuttons */ #if HAVE_ADC CONTROL_PORT = _BV(TRIGGER_DOWN) | _BV(TRIGGER_UP) | _BV(TRIGGER_ADC); #else CONTROL_PORT = _BV(TRIGGER_DOWN) | _BV(TRIGGER_UP); #endif /* * Enable Port D outputs: PD6 for the clock output, PD7 for the LED * flasher. PD1 is UART TxD but not DDRD setting is provided for * that, as enabling the UART transmitter will automatically turn * this pin into an output. */ CONTROL_DDR = _BV(CLOCKOUT) | _BV(FLASH); /* * As the location of OC1A differs between supported MCU types, we * enable that output separately here. Note that the DDRx register * *might* be the same as CONTROL_DDR above, so make sure to not * clobber it. */ PWMDDR |= _BV(PWMOUT); UCSRA = _BV(U2X); /* improves baud rate error @ F_CPU = 1 MHz */ UCSRB = _BV(TXEN)|_BV(RXEN)|_BV(RXCIE); /* tx/rx enable, rx complete intr */ UBRRL = (F_CPU / (8 * 9600UL)) - 1; /* 9600 Bd */ #if HAVE_ADC /* * enable ADC, select ADC clock = F_CPU / 8 (i.e. 125 kHz) */ ADCSRA = _BV(ADEN) | _BV(ADPS1) | _BV(ADPS0); #endif TIMSK = _BV(TOIE1); sei(); /* enable interrupts */ /* * Enable the watchdog with the largest prescaler. Will cause a * watchdog reset after approximately 2 s @ Vcc = 5 V */ wdt_enable(WDTO_2S); /* * Read the value from EEPROM. If it is not 0xffff (erased cells), * use it as the starting value for the PWM. */ if ((pwm_from_eeprom = eeprom_read_word(&ee_pwm)) != 0xffff) OCR1A = (pwm = pwm_from_eeprom); } /* * Some simple UART IO functions. */ /* * Send character c down the UART Tx, wait until tx holding register * is empty. */ static void putchr(char c) { loop_until_bit_is_set(UCSRA, UDRE); UDR = c; } /* * Send a C (NUL-terminated) string down the UART Tx. */ static void printstr(const char *s) { while (*s) { if (*s == '\n') putchr('\r'); putchr(*s++); } } /* * Same as above, but the string is located in program memory, * so "lpm" instructions are needed to fetch it. */ static void printstr_p(const char *s) { char c; for (c = pgm_read_byte(s); c; ++s, c = pgm_read_byte(s)) { if (c == '\n') putchr('\r'); putchr(c); } } /* * Update the PWM value. If it has changed, send the new value down * the serial line. */ static void set_pwm(int16_t new) { char s[8]; if (new < 0) new = 0; else if (new > 1000) new = 1000; if (new != pwm) { OCR1A = (pwm = new); /* * Calculate a "percentage". We just divide by 10, as we * limited the max value of the PWM to 1000 above. */ new /= 10; itoa(new, s, 10); printstr(s); putchr(' '); pwm_backup_tmr = EE_UPDATE_TIME; } } /* Part 5: main() */ int main(void) { /* * Our modus of operation. MODE_UPDOWN means we watch out for * either PD2 or PD3 being low, and increase or decrease the * PWM value accordingly. This is the default. * MODE_ADC means the PWM value follows the value of ADC0 (PA0). * This is enabled by applying low level to PC1. * MODE_SERIAL means we get commands via the UART. This is * enabled by sending a valid V.24 character at 9600 Bd to the * UART. */ enum { MODE_UPDOWN, MODE_ADC, MODE_SERIAL } __attribute__((packed)) mode = MODE_UPDOWN; uint8_t flash = 0; ioinit(); if ((mcucsr & _BV(WDRF)) == _BV(WDRF)) printstr_p(PSTR("\nOoops, the watchdog bit me!")); printstr_p(PSTR("\nHello, this is the avr-gcc/libc " "demo running on an " #if defined(__AVR_ATmega16__) "ATmega16" #elif defined(__AVR_ATmega8__) "ATmega8" #elif defined(__AVR_ATmega48__) "ATmega48" #elif defined(__AVR_ATmega88__) "ATmega88" #elif defined(__AVR_ATmega168__) "ATmega168" #elif defined(__AVR_ATtiny2313__) "ATtiny2313" #else "unknown AVR" #endif "\n")); for (;;) { wdt_reset(); if (intflags.tmr_int) { /* * Our periodic 10 ms interrupt happened. See what we can * do about it. */ intflags.tmr_int = 0; /* * toggle PD6, just to show the internal clock; should * yield ~ 48 Hz on PD6 */ CONTROL_PORT ^= _BV(CLOCKOUT); /* * flash LED on PD7, approximately once per second */ flash++; if (flash == 5) CONTROL_PORT |= _BV(FLASH); else if (flash == 100) { flash = 0; CONTROL_PORT &= ~_BV(FLASH); } switch (mode) { case MODE_SERIAL: /* * In serial mode, there's nothing to do anymore here. */ break; case MODE_UPDOWN: /* * Query the pushbuttons. * * NB: watch out to use PINx for reading, as opposed * to using PORTx which would be the mirror of the * _output_ latch register (resp. pullup configuration * bit for input pins)! */ if (bit_is_clear(PIND, TRIGGER_DOWN)) set_pwm(pwm - 10); else if (bit_is_clear(PIND, TRIGGER_UP)) set_pwm(pwm + 10); #if HAVE_ADC else if (bit_is_clear(PIND, TRIGGER_ADC)) mode = MODE_ADC; #endif break; case MODE_ADC: #if HAVE_ADC if (bit_is_set(PIND, TRIGGER_ADC)) mode = MODE_UPDOWN; else { /* * Start one conversion. */ ADCSRA |= _BV(ADIE); ADCSRA |= _BV(ADSC); } #endif /* HAVE_ADC */ break; } if (pwm_backup_tmr && --pwm_backup_tmr == 0) { /* * The EEPROM backup timer expired. Save the current * PWM value in EEPROM. Note that this function might * block for a few milliseconds (after writing the * first byte). */ eeprom_write_word(&ee_pwm, pwm); printstr_p(PSTR("[EEPROM updated] ")); } } #if HAVE_ADC if (intflags.adc_int) { intflags.adc_int = 0; set_pwm(adcval); } #endif /* HAVE_ADC */ if (intflags.rx_int) { intflags.rx_int = 0; if (rxbuff == 'q') { printstr_p(PSTR("\nThank you for using serial mode." " Good-bye!\n")); mode = MODE_UPDOWN; } else { if (mode != MODE_SERIAL) { printstr_p(PSTR("\nWelcome at serial control, " "type +/- to adjust, or 0/1 to turn on/off\n" "the LED, q to quit serial mode, " "r to demonstrate a watchdog reset\n")); mode = MODE_SERIAL; } switch (rxbuff) { case '+': set_pwm(pwm + 10); break; case '-': set_pwm(pwm - 10); break; case '0': set_pwm(0); break; case '1': set_pwm(1000); break; case 'r': printstr_p(PSTR("\nzzzz... zzz...")); for (;;) ; } } } sleep_mode(); } } avr-libc-1.8.0.orig/doc/examples/all-demos.dox0000644000000000000000000001117411732702554016032 0ustar /* Copyright (c) 2004-2006 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: all-demos.dox 1124 2006-08-29 19:45:06Z joerg_wunsch $ */ /** \defgroup demos Demo projects Various small demo projects are provided to illustrate several aspects of using the opensource utilities for the AVR controller series. It should be kept in mind that these demos serve mainly educational purposes, and are normally not directly suitable for use in any production environment. Usually, they have been kept as simple as sufficient to demonstrate one particular feature. The \ref demo_project "simple project" is somewhat like the "Hello world!" application for a microcontroller, about the most simple project that can be done. It is explained in good detail, to allow the reader to understand the basic concepts behind using the tools on an AVR microcontroller. The \ref largedemo "more sophisticated demo project" builds on top of that simple project, and adds some controls to it. It touches a number of avr-libc's basic concepts on its way. A \ref stdiodemo "comprehensive example on using the standard IO facilities" intends to explain that complex topic, using a practical microcontroller peripheral setup with one RS-232 connection, and an HD44780-compatible industry-standard LCD display. The \ref twi_demo project explains the use of the two-wire hardware interface (also known as "I2C") that is present on many AVR controllers. Finally, the \ref asmdemo demo shows how C and assembly language source files can collaborate within one project. While the overall project is managed by a C program part for easy maintenance, time-critical parts are written directly in manually optimized assembly language for shortest execution times possible. Naturally, this kind of project is very closely tied to the hardware design, thus it is custom-tailored to a particular controller type and peripheral setup. As an alternative to the assembly-language solution, this project also offers a C-only implementation (deploying the exact same peripheral setup) based on a more sophisticated (and thus more expensive) but pin-compatible controller. While the simple demo is meant to run on about any AVR setup possible where a LED could be connected to the OCR1[A] output, the \ref largedemo "large" and \ref stdiodemo "stdio" demos are mainly targeted to the Atmel STK500 starter kit, and the \ref twi_demo "TWI" example requires a controller where some 24Cxx two-wire EEPPROM can be connected to. For the STK500 demos, the default CPU (either an AT90S8515 or an ATmega8515) should be removed from its socket, and the ATmega16 that ships with the kit should be inserted into socket SCKT3100A3. The ATmega16 offers an on-board ADC that is used in the \ref largedemo "large" demo, and all AVRs with an ADC feature a different pinout than the industry-standard compatible devices. In order to fully utilize the \ref largedemo "large" demo, a female 10-pin header with cable, connecting to a 10 kOhm potentiometer will be useful. For the \ref stdiodemo "stdio" demo, an industry-standard HD44780-compatible LCD display of at least 16x1 characters will be needed. Among other things, the LCD4Linux project page describes many things around these displays, including common pinouts. */ avr-libc-1.8.0.orig/doc/examples/Makefile.in0000644000000000000000000003251511732702554015510 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # # Copyright (c) 2002,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # 3. The name of the author may not be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN # NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED # TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR # PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Author: Theodore A. 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do \ $(mkinstalldirs) $(DOC_INST_DIR)/examples/$$dir; \ done for file in $(DEMO_SRCS) ; do \ echo "Installing $$file into $(DOC_INST_DIR)/examples/$$file"; \ $(INSTALL_DATA) $(top_srcdir)/doc/examples/$$file \ $(DOC_INST_DIR)/examples/$$file; \ done uninstall-local: for file in $(DEMO_SRCS) ; do \ echo "Removing $(DOC_INST_DIR)/examples/$$file"; \ rm -f $(DOC_INST_DIR)/examples/$$file; \ done for dir in $(DEMO_DIRS) ; do \ rmdir $(DOC_INST_DIR)/examples/$$dir || \ echo "rmdir $(DOC_INST_DIR)/examples/$$dir failed."; \ done rmdir $(DOC_INST_DIR)/examples ||\ echo "rmdir $(DOC_INST_DIR)/examples failed." # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: avr-libc-1.8.0.orig/doc/examples/stdiodemo/0000755000000000000000000000000011732702554015424 5ustar avr-libc-1.8.0.orig/doc/examples/stdiodemo/stdiodemo.c0000644000000000000000000000402111732702554017554 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * Stdio demo * * $Id: stdiodemo.c 1008 2005-12-28 21:38:59Z joerg_wunsch $ */ #include "defines.h" #include #include #include #include #include #include #include "lcd.h" #include "uart.h" /* * Do all the startup-time peripheral initializations. */ static void ioinit(void) { uart_init(); lcd_init(); } FILE uart_str = FDEV_SETUP_STREAM(uart_putchar, uart_getchar, _FDEV_SETUP_RW); FILE lcd_str = FDEV_SETUP_STREAM(lcd_putchar, NULL, _FDEV_SETUP_WRITE); static void delay_1s(void) { uint8_t i; for (i = 0; i < 100; i++) _delay_ms(10); } int main(void) { uint8_t i; char buf[20], s[20]; ioinit(); stdout = stdin = &uart_str; stderr = &lcd_str; fprintf(stderr, "Hello world!\n"); for (;;) { printf_P(PSTR("Enter command: ")); if (fgets(buf, sizeof buf - 1, stdin) == NULL) break; if (tolower(buf[0]) == 'q') break; switch (tolower(buf[0])) { default: printf("Unknown command: %s\n", buf); break; case 'l': if (sscanf(buf, "%*s %s", s) > 0) { fprintf(&lcd_str, "Got %s\n", s); printf("OK\n"); } else { printf("sscanf() failed\n"); } break; case 'u': if (sscanf(buf, "%*s %s", s) > 0) { fprintf(&uart_str, "Got %s\n", s); printf("OK\n"); } else { printf("sscanf() failed\n"); } break; } } fprintf(stderr, "Bye-bye"); delay_1s(); for (i = 0; i < 3; i++) { putc('.', stderr); delay_1s(); } fprintf(stderr, "\n "); return 0; } avr-libc-1.8.0.orig/doc/examples/stdiodemo/uart.c0000644000000000000000000001016711732702554016550 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * Stdio demo, UART implementation * * $Id: uart.c 1008 2005-12-28 21:38:59Z joerg_wunsch $ */ #include "defines.h" #include #include #include #include "uart.h" /* * Initialize the UART to 9600 Bd, tx/rx, 8N1. */ void uart_init(void) { #if F_CPU < 2000000UL && defined(U2X) UCSRA = _BV(U2X); /* improve baud rate error by using 2x clk */ UBRRL = (F_CPU / (8UL * UART_BAUD)) - 1; #else UBRRL = (F_CPU / (16UL * UART_BAUD)) - 1; #endif UCSRB = _BV(TXEN) | _BV(RXEN); /* tx/rx enable */ } /* * Send character c down the UART Tx, wait until tx holding register * is empty. */ int uart_putchar(char c, FILE *stream) { if (c == '\a') { fputs("*ring*\n", stderr); return 0; } if (c == '\n') uart_putchar('\r', stream); loop_until_bit_is_set(UCSRA, UDRE); UDR = c; return 0; } /* * Receive a character from the UART Rx. * * This features a simple line-editor that allows to delete and * re-edit the characters entered, until either CR or NL is entered. * Printable characters entered will be echoed using uart_putchar(). * * Editing characters: * * . \b (BS) or \177 (DEL) delete the previous character * . ^u kills the entire input buffer * . ^w deletes the previous word * . ^r sends a CR, and then reprints the buffer * . \t will be replaced by a single space * * All other control characters will be ignored. * * The internal line buffer is RX_BUFSIZE (80) characters long, which * includes the terminating \n (but no terminating \0). If the buffer * is full (i. e., at RX_BUFSIZE-1 characters in order to keep space for * the trailing \n), any further input attempts will send a \a to * uart_putchar() (BEL character), although line editing is still * allowed. * * Input errors while talking to the UART will cause an immediate * return of -1 (error indication). Notably, this will be caused by a * framing error (e. g. serial line "break" condition), by an input * overrun, and by a parity error (if parity was enabled and automatic * parity recognition is supported by hardware). * * Successive calls to uart_getchar() will be satisfied from the * internal buffer until that buffer is emptied again. */ int uart_getchar(FILE *stream) { uint8_t c; char *cp, *cp2; static char b[RX_BUFSIZE]; static char *rxp; if (rxp == 0) for (cp = b;;) { loop_until_bit_is_set(UCSRA, RXC); if (UCSRA & _BV(FE)) return _FDEV_EOF; if (UCSRA & _BV(DOR)) return _FDEV_ERR; c = UDR; /* behaviour similar to Unix stty ICRNL */ if (c == '\r') c = '\n'; if (c == '\n') { *cp = c; uart_putchar(c, stream); rxp = b; break; } else if (c == '\t') c = ' '; if ((c >= (uint8_t)' ' && c <= (uint8_t)'\x7e') || c >= (uint8_t)'\xa0') { if (cp == b + RX_BUFSIZE - 1) uart_putchar('\a', stream); else { *cp++ = c; uart_putchar(c, stream); } continue; } switch (c) { case 'c' & 0x1f: return -1; case '\b': case '\x7f': if (cp > b) { uart_putchar('\b', stream); uart_putchar(' ', stream); uart_putchar('\b', stream); cp--; } break; case 'r' & 0x1f: uart_putchar('\r', stream); for (cp2 = b; cp2 < cp; cp2++) uart_putchar(*cp2, stream); break; case 'u' & 0x1f: while (cp > b) { uart_putchar('\b', stream); uart_putchar(' ', stream); uart_putchar('\b', stream); cp--; } break; case 'w' & 0x1f: while (cp > b && cp[-1] != ' ') { uart_putchar('\b', stream); uart_putchar(' ', stream); uart_putchar('\b', stream); cp--; } break; } } c = *rxp++; if (c == '\n') rxp = 0; return c; } avr-libc-1.8.0.orig/doc/examples/stdiodemo/stdiodemo.dox0000644000000000000000000005240011732702554020130 0ustar /* Copyright (c) 2005,2006 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id*/ /** \defgroup stdiodemo Using the standard IO facilities \ingroup demos This project illustrates how to use the standard IO facilities (stdio) provided by this library. It assumes a basic knowledge of how the stdio subsystem is used in standard C applications, and concentrates on the differences in this library's implementation that mainly result from the differences of the microcontroller environment, compared to a hosted environment of a standard computer. This demo is meant to supplement the \ref avr_stdio "documentation", not to replace it. \section stdiodemo_hw Hardware setup The demo is set up in a way so it can be run on the ATmega16 that ships with the STK500 development kit. The UART port needs to be connected to the RS-232 "spare" port by a jumper cable that connects PD0 to RxD and PD1 to TxD. The RS-232 channel is set up as standard input (\c stdin) and standard output (\c stdout), respectively. In order to have a different device available for a standard error channel (\c stderr), an industry-standard LCD display with an HD44780-compatible LCD controller has been chosen. This display needs to be connected to port A of the STK500 in the following way:
PortHeaderFunction
A0 1 LCD D4
A1 2 LCD D5
A2 3 LCD D6
A3 4 LCD D7
A4 5 LCD R/~W
A5 6 LCD E
A6 7 LCD RS
A7 8 unused
GND9 GND
VCC10Vcc
\image html stdiodemo-setup.jpg "Wiring of the STK500" \image latex stdiodemo-setup.eps "Wiring of the STK500" width=12cm The LCD controller is used in 4-bit mode, including polling the "busy" flag so the R/~W line from the LCD controller needs to be connected. Note that the LCD controller has yet another supply pin that is used to adjust the LCD's contrast (V5). Typically, that pin connects to a potentiometer between Vcc and GND. Often, it might work to just connect that pin to GND, while leaving it unconnected usually yields an unreadable display. Port A has been chosen as 7 pins are needed to connect the LCD, yet all other ports are already partially in use: port B has the pins for in-system programming (ISP), port C has the ports for JTAG (can be used for debugging), and port D is used for the UART connection. \section stdiodemo_overview Functional overview The project consists of the following files: - \c stdiodemo.c This is the main example file. - \c defines.h Contains some global defines, like the LCD wiring - \c hd44780.c Implementation of an HD44780 LCD display driver - \c hd44780.h Interface declarations for the HD44780 driver - \c lcd.c Implementation of LCD character IO on top of the HD44780 driver - \c lcd.h Interface declarations for the LCD driver - \c uart.c Implementation of a character IO driver for the internal UART - \c uart.h Interface declarations for the UART driver \section stdiodemo_code A code walkthrough \subsection stdiodemo_main stdiodemo.c As usual, include files go first. While conventionally, system header files (those in angular brackets \c < ... \c >) go before application-specific header files (in double quotes), \c defines.h comes as the first header file here. The main reason is that this file defines the value of \c F_CPU which needs to be known before including <utils/delay.h>. The function \c ioinit() summarizes all hardware initialization tasks. As this function is declared to be module-internal only (\c static), the compiler will notice its simplicity, and with a reasonable optimization level in effect, it will inline that function. That needs to be kept in mind when debugging, because the inlining might cause the debugger to "jump around wildly" at a first glance when single-stepping. The definitions of \c uart_str and \c lcd_str set up two stdio streams. The initialization is done using the \c FDEV_SETUP_STREAM() initializer template macro, so a static object can be constructed that can be used for IO purposes. This initializer macro takes three arguments, two function macros to connect the corresponding output and input functions, respectively, the third one describes the intent of the stream (read, write, or both). Those functions that are not required by the specified intent (like the input function for \c lcd_str which is specified to only perform output operations) can be given as \c NULL. The stream \c uart_str corresponds to input and output operations performed over the RS-232 connection to a terminal (e.g. from/to a PC running a terminal program), while the \c lcd_str stream provides a method to display character data on the LCD text display. The function \c delay_1s() suspends program execution for approximately one second. This is done using the \c _delay_ms() function from <util/delay.h> which in turn needs the \c F_CPU macro in order to adjust the cycle counts. As the \c _delay_ms() function has a limited range of allowable argument values (depending on \c F_CPU), a value of 10 ms has been chosen as the base delay which would be safe for CPU frequencies of up to about 26 MHz. This function is then called 100 times to accomodate for the actual one-second delay. In a practical application, long delays like this one were better be handled by a hardware timer, so the main CPU would be free for other tasks while waiting, or could be put on sleep. At the beginning of \c main(), after initializing the peripheral devices, the default stdio streams \c stdin, \c stdout, and \c stderr are set up by using the existing static \c FILE stream objects. While this is not mandatory, the availability of \c stdin and \c stdout allows to use the shorthand functions (e.g. \c printf() instead of \c fprintf()), and \c stderr can mnemonically be referred to when sending out diagnostic messages. Just for demonstration purposes, \c stdin and \c stdout are connected to a stream that will perform UART IO, while \c stderr is arranged to output its data to the LCD text display. Finally, a main loop follows that accepts simple "commands" entered via the RS-232 connection, and performs a few simple actions based on the commands. First, a prompt is sent out using \c printf_P() (which takes a \ref avr_pgmspace "program space string"). The string is read into an internal buffer as one line of input, using \c fgets(). While it would be also possible to use \c gets() (which implicitly reads from \c stdin), \c gets() has no control that the user's input does not overflow the input buffer provided so it should never be used at all. If \c fgets() fails to read anything, the main loop is left. Of course, normally the main loop of a microcontroller application is supposed to never finish, but again, for demonstrational purposes, this explains the error handling of stdio. \c fgets() will return NULL in case of an input error or end-of-file condition on input. Both these conditions are in the domain of the function that is used to establish the stream, \c uart_putchar() in this case. In short, this function returns EOF in case of a serial line "break" condition (extended start condition) has been recognized on the serial line. Common PC terminal programs allow to assert this condition as some kind of out-of-band signalling on an RS-232 connection. When leaving the main loop, a goodbye message is sent to standard error output (i.e. to the LCD), followed by three dots in one-second spacing, followed by a sequence that will clear the LCD. Finally, \c main() will be terminated, and the library will add an infinite loop, so only a CPU reset will be able to restart the application. There are three "commands" recognized, each determined by the first letter of the line entered (converted to lower case): - The 'q' (quit) command has the same effect of leaving the main loop. - The 'l' (LCD) command takes its second argument, and sends it to the LCD. - The 'u' (UART) command takes its second argument, and sends it back to the UART connection. Command recognition is done using \c sscanf() where the first format in the format string just skips over the command itself (as the assignment suppression modifier \c * is given). \subsection stdiodemo_defines defines.h This file just contains a few peripheral definitions. The \c F_CPU macro defines the CPU clock frequency, to be used in delay loops, as well as in the UART baud rate calculation. The macro \c UART_BAUD defines the RS-232 baud rate. Depending on the actual CPU frequency, only a limited range of baud rates can be supported. The remaining macros customize the IO port and pins used for the HD44780 LCD driver. Each definition consists of a letter naming the port this pin is attached to, and a respective bit number. For accessing the data lines, only the first data line gets its own macro (line D4 on the HD44780, lines D0 through D3 are not used in 4-bit mode), all other data lines are expected to be in ascending order next to D4. \subsection stdiodemo_hd44780_h hd44780.h This file describes the public interface of the low-level LCD driver that interfaces to the HD44780 LCD controller. Public functions are available to initialize the controller into 4-bit mode, to wait for the controller's busy bit to be clear, and to read or write one byte from or to the controller. As there are two different forms of controller IO, one to send a command or receive the controller status (RS signal clear), and one to send or receive data to/from the controller's SRAM (RS asserted), macros are provided that build on the mentioned function primitives. Finally, macros are provided for all the controller commands to allow them to be used symbolically. The HD44780 datasheet explains these basic functions of the controller in more detail. \subsection stdiodemo_hd44780_c hd44780.c This is the implementation of the low-level HD44780 LCD controller driver. On top, a few preprocessor glueing tricks are used to establish symbolic access to the hardware port pins the LCD controller is attached to, based on the application's definitions made in \ref stdiodemo_defines. The \c hd44780_pulse_e() function asserts a short pulse to the controller's E (enable) pin. Since reading back the data asserted by the LCD controller needs to be performed while E is active, this function reads and returns the input data if the parameter \c readback is true. When called with a compile-time constant parameter that is false, the compiler will completely eliminate the unused readback operation, as well as the return value as part of its optimizations. As the controller is used in 4-bit interface mode, all byte IO to/from the controller needs to be handled as two nibble IOs. The functions \c hd44780_outnibble() and \c hd44780_innibble() implement this. They do not belong to the public interface, so they are declared static. Building upon these, the public functions \c hd44780_outbyte() and \c hd44780_inbyte() transfer one byte to/from the controller. The function \c hd44780_wait_ready() waits for the controller to become ready, by continuously polling the controller's status (which is read by performing a byte read with the RS signal cleard), and examining the BUSY flag within the status byte. This function needs to be called before performing any controller IO. Finally, \c hd44780_init() initializes the LCD controller into 4-bit mode, based on the initialization sequence mandated by the datasheet. As the BUSY flag cannot be examined yet at this point, this is the only part of this code where timed delays are used. While the controller can perform a power-on reset when certain constraints on the power supply rise time are met, always calling the software initialization routine at startup ensures the controller will be in a known state. This function also puts the interface into 4-bit mode (which would not be done automatically after a power-on reset). \subsection stdiodemo_lcd_h lcd.h This function declares the public interface of the higher-level (character IO) LCD driver. \subsection stdiodemo_lcd_c lcd.c The implementation of the higher-level LCD driver. This driver builds on top of the HD44780 low-level LCD controller driver, and offers a character IO interface suitable for direct use by the standard IO facilities. Where the low-level HD44780 driver deals with setting up controller SRAM addresses, writing data to the controller's SRAM, and controlling display functions like clearing the display, or moving the cursor, this high-level driver allows to just write a character to the LCD, in the assumption this will somehow show up on the display. Control characters can be handled at this level, and used to perform specific actions on the LCD. Currently, there is only one control character that is being dealt with: a newline character (\c \\n) is taken as an indication to clear the display and set the cursor into its initial position upon reception of the next character, so a "new line" of text can be displayed. Therefore, a received newline character is remembered until more characters have been sent by the application, and will only then cause the display to be cleared before continuing. This provides a convenient abstraction where full lines of text can be sent to the driver, and will remain visible at the LCD until the next line is to be displayed. Further control characters could be implemented, e. g. using a set of escape sequences. That way, it would be possible to implement self-scrolling display lines etc. The public function \c lcd_init() first calls the initialization entry point of the lower-level HD44780 driver, and then sets up the LCD in a way we'd like to (display cleared, non-blinking cursor enabled, SRAM addresses are increasing so characters will be written left to right). The public function \c lcd_putchar() takes arguments that make it suitable for being passed as a \c put() function pointer to the stdio stream initialization functions and macros (\c fdevopen(), \c FDEV_SETUP_STREAM() etc.). Thus, it takes two arguments, the character to display itself, and a reference to the underlying stream object, and it is expected to return 0 upon success. This function remembers the last unprocessed newline character seen in the function-local static variable \c nl_seen. If a newline character is encountered, it will simply set this variable to a true value, and return to the caller. As soon as the first non-newline character is to be displayed with \c nl_seen still true, the LCD controller is told to clear the display, put the cursor home, and restart at SRAM address 0. All other characters are sent to the display. The single static function-internal variable \c nl_seen works for this purpose. If multiple LCDs should be controlled using the same set of driver functions, that would not work anymore, as a way is needed to distinguish between the various displays. This is where the second parameter can be used, the reference to the stream itself: instead of keeping the state inside a private variable of the function, it can be kept inside a private object that is attached to the stream itself. A reference to that private object can be attached to the stream (e.g. inside the function \c lcd_init() that then also needs to be passed a reference to the stream) using \c fdev_set_udata(), and can be accessed inside \c lcd_putchar() using fdev_get_udata(). \subsection stdiodemo_uart_h uart.h Public interface definition for the RS-232 UART driver, much like in \ref stdiodemo_lcd_h "lcd.h" except there is now also a character input function available. As the RS-232 input is line-buffered in this example, the macro \c RX_BUFSIZE determines the size of that buffer. \subsection stdiodemo_uart_c uart.c This implements an stdio-compatible RS-232 driver using an AVR's standard UART (or USART in asynchronous operation mode). Both, character output as well as character input operations are implemented. Character output takes care of converting the internal newline \c \\n into its external representation carriage return/line feed (\\r\\n). Character input is organized as a line-buffered operation that allows to minimally edit the current line until it is "sent" to the application when either a carriage return (\c \\r) or newline (\c \\n) character is received from the terminal. The line editing functions implemented are: - \c \\b (back space) or \c \\177 (delete) deletes the previous character - ^u (control-U, ASCII NAK) deletes the entire input buffer - ^w (control-W, ASCII ETB) deletes the previous input word, delimited by white space - ^r (control-R, ASCII DC2) sends a \c \\r, then reprints the buffer (refresh) - \c \\t (tabulator) will be replaced by a single space The function \c uart_init() takes care of all hardware initialization that is required to put the UART into a mode with 8 data bits, no parity, one stop bit (commonly referred to as 8N1) at the baud rate configured in \ref stdiodemo_defines "defines.h". At low CPU clock frequencies, the \c U2X bit in the UART is set, reducing the oversampling from 16x to 8x, which allows for a 9600 Bd rate to be achieved with tolerable error using the default 1 MHz RC oscillator. The public function \c uart_putchar() again has suitable arguments for direct use by the stdio stream interface. It performs the \c \\n into \c \\r\\n translation by recursively calling itself when it sees a \c \\n character. Just for demonstration purposes, the \c \\a (audible bell, ASCII BEL) character is implemented by sending a string to \c stderr, so it will be displayed on the LCD. The public function \c uart_getchar() implements the line editor. If there are characters available in the line buffer (variable \c rxp is not \c NULL), the next character will be returned from the buffer without any UART interaction. If there are no characters inside the line buffer, the input loop will be entered. Characters will be read from the UART, and processed accordingly. If the UART signalled a framing error (\c FE bit set), typically caused by the terminal sending a line break condition (start condition held much longer than one character period), the function will return an end-of-file condition using \c _FDEV_EOF. If there was a data overrun condition on input (\c DOR bit set), an error condition will be returned as \c _FDEV_ERR. Line editing characters are handled inside the loop, potentially modifying the buffer status. If characters are attempted to be entered beyond the size of the line buffer, their reception is refused, and a \c \\a character is sent to the terminal. If a \c \\r or \c \\n character is seen, the variable \c rxp (receive pointer) is set to the beginning of the buffer, the loop is left, and the first character of the buffer will be returned to the application. (If no other characters have been entered, this will just be the newline character, and the buffer is marked as being exhausted immediately again.) \section stdiodemo_src The source code \htmlonly

  • stdiodemo.c
  • defines.h
  • hd44780.h
  • hd44780.c
  • lcd.h
  • lcd.c
  • uart.h
  • uart.c
    • \endhtmlonly \latexonly The source code is installed under \texttt{\$prefix/share/doc/avr-libc/examples/stdiodemo/}, where \texttt{\$prefix} is a configuration option. For Unix systems, it is usually set to either \texttt{/usr} or \texttt{/usr/local}. \endlatexonly */ avr-libc-1.8.0.orig/doc/examples/stdiodemo/hd44780.h0000644000000000000000000000536311732702554016606 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * HD44780 LCD display driver * * $Id: hd44780.h 2002 2009-06-25 20:21:16Z joerg_wunsch $ */ /* * Send byte b to the LCD. rs is the RS signal (register select), 0 * selects instruction register, 1 selects the data register. */ void hd44780_outbyte(uint8_t b, uint8_t rs); /* * Read one byte from the LCD controller. rs is the RS signal, 0 * selects busy flag (bit 7) and address counter, 1 selects the data * register. */ uint8_t hd44780_inbyte(uint8_t rs); /* * Wait for the busy flag to clear. */ void hd44780_wait_ready(bool islong); /* * Initialize the LCD controller hardware. */ void hd44780_init(void); /* * Prepare the LCD controller pins for powerdown. */ void hd44780_powerdown(void); /* Send a command to the LCD controller. */ #define hd44780_outcmd(n) hd44780_outbyte((n), 0) /* Send a data byte to the LCD controller. */ #define hd44780_outdata(n) hd44780_outbyte((n), 1) /* Read the address counter and busy flag from the LCD. */ #define hd44780_incmd() hd44780_inbyte(0) /* Read the current data byte from the LCD. */ #define hd44780_indata() hd44780_inbyte(1) /* Clear LCD display command. */ #define HD44780_CLR \ 0x01 /* Home cursor command. */ #define HD44780_HOME \ 0x02 /* * Select the entry mode. inc determines whether the address counter * auto-increments, shift selects an automatic display shift. */ #define HD44780_ENTMODE(inc, shift) \ (0x04 | ((inc)? 0x02: 0) | ((shift)? 1: 0)) /* * Selects disp[lay] on/off, cursor on/off, cursor blink[ing] * on/off. */ #define HD44780_DISPCTL(disp, cursor, blink) \ (0x08 | ((disp)? 0x04: 0) | ((cursor)? 0x02: 0) | ((blink)? 1: 0)) /* * With shift = 1, shift display right or left. * With shift = 0, move cursor right or left. */ #define HD44780_SHIFT(shift, right) \ (0x10 | ((shift)? 0x08: 0) | ((right)? 0x04: 0)) /* * Function set. if8bit selects an 8-bit data path, twoline arranges * for a two-line display, font5x10 selects the 5x10 dot font (5x8 * dots if clear). */ #define HD44780_FNSET(if8bit, twoline, font5x10) \ (0x20 | ((if8bit)? 0x10: 0) | ((twoline)? 0x08: 0) | \ ((font5x10)? 0x04: 0)) /* * Set the next character generator address to addr. */ #define HD44780_CGADDR(addr) \ (0x40 | ((addr) & 0x3f)) /* * Set the next display address to addr. */ #define HD44780_DDADDR(addr) \ (0x80 | ((addr) & 0x7f)) avr-libc-1.8.0.orig/doc/examples/stdiodemo/lcd.h0000644000000000000000000000131711732702554016341 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * Stdio demo, upper layer of LCD driver. * * $Id: lcd.h 1008 2005-12-28 21:38:59Z joerg_wunsch $ */ /* * Initialize LCD controller. Performs a software reset. */ void lcd_init(void); /* * Send one character to the LCD. */ int lcd_putchar(char c, FILE *stream); avr-libc-1.8.0.orig/doc/examples/stdiodemo/Makefile0000644000000000000000000000343111732702554017065 0ustar PRG = stdiodemo OBJ = stdiodemo.o hd44780.o lcd.o uart.o MCU_TARGET = atmega16 OPTIMIZE = -Os DEFS = LIBS = # You should not have to change anything below here. CC = avr-gcc CFLAGS = -g -Wall $(OPTIMIZE) -mmcu=$(MCU_TARGET) $(DEFS) LDFLAGS = -Wl,-Map,$(PRG).map OBJCOPY = avr-objcopy OBJDUMP = avr-objdump #all: $(PRG).elf lst text eeprom all: $(PRG).elf lst text $(PRG).elf: $(OBJ) $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS) clean: rm -rf *.o $(PRG).elf *.eps *.png *.pdf *.bak rm -rf *.lst *.map $(EXTRA_CLEAN_FILES) lst: $(PRG).lst %.lst: %.elf $(OBJDUMP) -h -S $< > $@ # Rules for building the .text rom images text: hex bin srec hex: $(PRG).hex bin: $(PRG).bin srec: $(PRG).srec %.hex: %.elf $(OBJCOPY) -j .text -j .data -O ihex $< $@ %.srec: %.elf $(OBJCOPY) -j .text -j .data -O srec $< $@ %.bin: %.elf $(OBJCOPY) -j .text -j .data -O binary $< $@ # Rules for building the .eeprom rom images eeprom: ehex ebin esrec ehex: $(PRG)_eeprom.hex ebin: $(PRG)_eeprom.bin esrec: $(PRG)_eeprom.srec %_eeprom.hex: %.elf $(OBJCOPY) -j .eeprom --change-section-lma .eeprom=0 -O ihex $< $@ %_eeprom.srec: %.elf $(OBJCOPY) -j .eeprom --change-section-lma .eeprom=0 -O srec $< $@ %_eeprom.bin: %.elf $(OBJCOPY) -j .eeprom --change-section-lma .eeprom=0 -O binary $< $@ # Every thing below here is used by avr-libc's build system and can be ignored # by the casual user. JPEGFILES = stdiodemo-setup.jpg JPEG2PNM = jpegtopnm PNM2EPS = pnmtops JPEGRESOLUTION = 180 EXTRA_CLEAN_FILES = *.hex *.bin *.srec *.eps dox: ${JPEGFILES:.jpg=.eps} %.eps: %.jpg $(JPEG2PNM) $< |\ $(PNM2EPS) -noturn -dpi $(JPEGRESOLUTION) -equalpixels \ > $@ avr-libc-1.8.0.orig/doc/examples/stdiodemo/uart.h0000644000000000000000000000171611732702554016555 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * Stdio demo, UART declarations * * $Id: uart.h 1008 2005-12-28 21:38:59Z joerg_wunsch $ */ /* * Perform UART startup initialization. */ void uart_init(void); /* * Send one character to the UART. */ int uart_putchar(char c, FILE *stream); /* * Size of internal line buffer used by uart_getchar(). */ #define RX_BUFSIZE 80 /* * Receive one character from the UART. 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1à‡4]6ˆs9T˘‘Ü1ħ`ġƤ‘£ğvM³›m6µ×?âNŬ™A/TÒı,˙#ÉóóÄ=\q¤taToao1ŝgŠŠó1Âö‚|úáĠ\qŠİF€.-ŭü NJ;R˘ó eT;dqĥ3ĥÌxùa†E4È$Ù+ĝĤ-f#qħë끁†à™ş„­MI¤™ D{ݸŜmÄMl4Ê睨Ş÷M#X-ÄŝÀÀĝR•`5 .;á×ċ‚ÂJĵáIaé΂­Éz"{Îż²FĠ“ĦĈk—çœ Ni•-€\àïf˘1Ħ‘·İÚp00[ŞCŞ=;4q‘ŬÓkóƒIöÉL&ûAĵüúzà`ax§àŸ XZ×üħ\jšˆdC Dħ•EXv|)J“ŠY&î–YA~Œoċ†³GĵÁcU¸kĜ{Œ F uQòŠFÓsÈÏ ™š"ÌMúÜà`bÑŞP€f pǧŻÏ Ğ‹‚X’=NPèžÀîônŒìʨ6‚ní{aŒà|CqċˆĠ ´eQFg‰LhTÚâÜtĊ‚š–”Öm4‘Ŭb‚×°ç98Ñ?ôë;m‚!ǒ RU‹˙Ùavr-libc-1.8.0.orig/doc/examples/stdiodemo/defines.h0000644000000000000000000000165611732702554017222 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * General stdiodemo defines * * $Id: defines.h 2186 2010-09-22 10:25:15Z aboyapati $ */ /* CPU frequency */ #define F_CPU 1000000UL /* UART baud rate */ #define UART_BAUD 9600 /* HD44780 LCD port connections */ #define HD44780_RS A, 6 #define HD44780_RW A, 4 #define HD44780_E A, 5 /* The data bits have to be not only in ascending order but also consecutive. */ #define HD44780_D4 A, 0 /* Whether to read the busy flag, or fall back to worst-time delays. */ #define USE_BUSY_BIT 1 avr-libc-1.8.0.orig/doc/examples/stdiodemo/lcd.c0000644000000000000000000000371111732702554016334 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * Stdio demo, upper layer of LCD driver. * * $Id: lcd.c 2265 2011-12-28 21:28:29Z joerg_wunsch $ */ #include "defines.h" #include #include #include #include #include #include "hd44780.h" #include "lcd.h" /* * Setup the LCD controller. First, call the hardware initialization * function, then adjust the display attributes we want. */ void lcd_init(void) { hd44780_init(); /* * Clear the display. */ hd44780_outcmd(HD44780_CLR); hd44780_wait_ready(true); /* * Entry mode: auto-increment address counter, no display shift in * effect. */ hd44780_outcmd(HD44780_ENTMODE(1, 0)); hd44780_wait_ready(false); /* * Enable display, activate non-blinking cursor. */ hd44780_outcmd(HD44780_DISPCTL(1, 1, 0)); hd44780_wait_ready(false); } /* * Send character c to the LCD display. After a '\n' has been seen, * the next character will first clear the display. */ int lcd_putchar(char c, FILE *unused) { static bool nl_seen; if (nl_seen && c != '\n') { /* * First character after newline, clear display and home cursor. */ hd44780_wait_ready(false); hd44780_outcmd(HD44780_CLR); hd44780_wait_ready(false); hd44780_outcmd(HD44780_HOME); hd44780_wait_ready(true); hd44780_outcmd(HD44780_DDADDR(0)); nl_seen = false; } if (c == '\n') { nl_seen = true; } else { hd44780_wait_ready(false); hd44780_outdata(c); } return 0; } avr-libc-1.8.0.orig/doc/examples/stdiodemo/hd44780.c0000644000000000000000000001231011732702554016567 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * HD44780 LCD display driver * * The LCD controller is used in 4-bit mode with a full bi-directional * interface (i.e. R/~W is connected) so the busy flag can be read. * * $Id: hd44780.c 2002 2009-06-25 20:21:16Z joerg_wunsch $ */ #include "defines.h" #include #include #include #include #include "hd44780.h" #define GLUE(a, b) a##b /* single-bit macros, used for control bits */ #define SET_(what, p, m) GLUE(what, p) |= (1 << (m)) #define CLR_(what, p, m) GLUE(what, p) &= ~(1 << (m)) #define GET_(/* PIN, */ p, m) GLUE(PIN, p) & (1 << (m)) #define SET(what, x) SET_(what, x) #define CLR(what, x) CLR_(what, x) #define GET(/* PIN, */ x) GET_(x) /* nibble macros, used for data path */ #define ASSIGN_(what, p, m, v) GLUE(what, p) = (GLUE(what, p) & \ ~((1 << (m)) | (1 << ((m) + 1)) | \ (1 << ((m) + 2)) | (1 << ((m) + 3)))) | \ ((v) << (m)) #define READ_(what, p, m) (GLUE(what, p) & ((1 << (m)) | (1 << ((m) + 1)) | \ (1 << ((m) + 2)) | (1 << ((m) + 3)))) >> (m) #define ASSIGN(what, x, v) ASSIGN_(what, x, v) #define READ(what, x) READ_(what, x) #define HD44780_BUSYFLAG 0x80 /* * Send one pulse to the E signal (enable). Mind the timing * constraints. If readback is set to true, read the HD44780 data * pins right before the falling edge of E, and return that value. */ static inline uint8_t hd44780_pulse_e(bool readback) __attribute__((always_inline)); static inline uint8_t hd44780_pulse_e(bool readback) { uint8_t x; SET(PORT, HD44780_E); /* * Guarantee at least 500 ns of pulse width. For high CPU * frequencies, a delay loop is used. For lower frequencies, NOPs * are used, and at or below 1 MHz, the native pulse width will * already be 1 us or more so no additional delays are needed. */ #if F_CPU > 4000000UL _delay_us(0.5); #else /* * When reading back, we need one additional NOP, as the value read * back from the input pin is sampled close to the beginning of a * CPU clock cycle, while the previous edge on the output pin is * generated towards the end of a CPU clock cycle. */ if (readback) __asm__ volatile("nop"); # if F_CPU > 1000000UL __asm__ volatile("nop"); # if F_CPU > 2000000UL __asm__ volatile("nop"); __asm__ volatile("nop"); # endif /* F_CPU > 2000000UL */ # endif /* F_CPU > 1000000UL */ #endif if (readback) x = READ(PIN, HD44780_D4); else x = 0; CLR(PORT, HD44780_E); return x; } /* * Send one nibble out to the LCD controller. */ static void hd44780_outnibble(uint8_t n, uint8_t rs) { CLR(PORT, HD44780_RW); if (rs) SET(PORT, HD44780_RS); else CLR(PORT, HD44780_RS); ASSIGN(PORT, HD44780_D4, n); (void)hd44780_pulse_e(false); } /* * Send one byte to the LCD controller. As we are in 4-bit mode, we * have to send two nibbles. */ void hd44780_outbyte(uint8_t b, uint8_t rs) { hd44780_outnibble(b >> 4, rs); hd44780_outnibble(b & 0xf, rs); } /* * Read one nibble from the LCD controller. */ static uint8_t hd44780_innibble(uint8_t rs) { uint8_t x; SET(PORT, HD44780_RW); ASSIGN(DDR, HD44780_D4, 0x00); if (rs) SET(PORT, HD44780_RS); else CLR(PORT, HD44780_RS); x = hd44780_pulse_e(true); ASSIGN(DDR, HD44780_D4, 0x0F); CLR(PORT, HD44780_RW); return x; } /* * Read one byte (i.e. two nibbles) from the LCD controller. */ uint8_t hd44780_inbyte(uint8_t rs) { uint8_t x; x = hd44780_innibble(rs) << 4; x |= hd44780_innibble(rs); return x; } /* * Wait until the busy flag is cleared. */ void hd44780_wait_ready(bool longwait) { #if USE_BUSY_BIT while (hd44780_incmd() & HD44780_BUSYFLAG) ; #else if (longwait) _delay_ms(1.52); else _delay_us(37); #endif } /* * Initialize the LCD controller. * * The initialization sequence has a mandatory timing so the * controller can safely recognize the type of interface desired. * This is the only area where timed waits are really needed as * the busy flag cannot be probed initially. */ void hd44780_init(void) { SET(DDR, HD44780_RS); SET(DDR, HD44780_RW); SET(DDR, HD44780_E); ASSIGN(DDR, HD44780_D4, 0x0F); _delay_ms(15); /* 40 ms needed for Vcc = 2.7 V */ hd44780_outnibble(HD44780_FNSET(1, 0, 0) >> 4, 0); _delay_ms(4.1); hd44780_outnibble(HD44780_FNSET(1, 0, 0) >> 4, 0); _delay_ms(0.1); hd44780_outnibble(HD44780_FNSET(1, 0, 0) >> 4, 0); _delay_us(37); hd44780_outnibble(HD44780_FNSET(0, 1, 0) >> 4, 0); hd44780_wait_ready(false); hd44780_outcmd(HD44780_FNSET(0, 1, 0)); hd44780_wait_ready(false); hd44780_outcmd(HD44780_DISPCTL(0, 0, 0)); hd44780_wait_ready(false); } /* * Prepare the LCD controller pins for powerdown. */ void hd44780_powerdown(void) { ASSIGN(PORT, HD44780_D4, 0); CLR(PORT, HD44780_RS); CLR(PORT, HD44780_RW); CLR(PORT, HD44780_E); } avr-libc-1.8.0.orig/doc/examples/asmdemo/0000755000000000000000000000000011732702554015062 5ustar avr-libc-1.8.0.orig/doc/examples/asmdemo/isrs.S0000644000000000000000000000602711732702554016173 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * Joerg Wunsch wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * Demo combining C and assembly source files. * * $Id: isrs.S 1124 2006-08-29 19:45:06Z joerg_wunsch $ */ /* * This file contains the interrupt service routine implementations * when compiling the project for the ATtiny13 target. */ #include #include "project.h" #if defined(__AVR_ATtiny13__) /* * Timer 0 hit TOP (0xff), i.e. it turns from up-counting * into down-counting direction. */ .global TIM0_COMPA_vect TIM0_COMPA_vect: in sreg_save, _SFR_IO_ADDR(SREG) inc counter_hi clr flags out _SFR_IO_ADDR(SREG), sreg_save reti /* * Timer 0 hit BOTTOM (0x00), i.e. it turns from down-counting * into up-counting direction. */ .global TIM0_OVF_vect TIM0_OVF_vect: in sreg_save, _SFR_IO_ADDR(SREG) inc counter_hi ser flags out _SFR_IO_ADDR(SREG), sreg_save reti ;;; one 16-bit word to store our rising edge's timestamp .lcomm starttime.0, 2 .extern pwm_incoming .extern intbits .global PCINT0_vect PCINT0_vect: in sreg_save, _SFR_IO_ADDR(SREG) ;; save our working registers push r18 push r19 push r20 push r21 ;; Now that we are ready to fetch the current ;; value of TCNT0, allow interrupts for a ;; moment. As the effect of the SEI will be ;; deferred by one instruction, any possible ;; rollover of TCNT0 (hitting BOTTOM when ;; counting down, or MAX when counting up) will ;; allow the above ISRs to trigger right here, ;; and update their status, so our combined ;; 16-bit time from [counter_hi, TCNT0] will ;; be correct. sei in r20, _SFR_IO_ADDR(TCNT0) cli ;; Now, make our working copy of the status, ;; so we can re-enable interrupts again. mov r21, counter_hi mov r19, flags sei ;; what direction were we counting? sbrs r19, 0 ;; we are down-counting, invert TCNT0 com r20 ;; at this point, r21:20 has our current ;; 16-bit time ;; now, look which of the edges triggered ;; our pin-change interrupt sbis _SFR_IO_ADDR(PINB), 4 rjmp 10f ;; rising edge detected, just record starttime sts (starttime.0) + 1, r21 sts starttime.0, r20 rjmp 99f ; we are done here ;; Falling edge: compute pulse width, store it ;; into pwm_incoming, disable pin-change ;; interrupt until the upper layers had a chance ;; to fetch the result. 10: in r18, _SFR_IO_ADDR(GIMSK) andi r18, ~(1 << PCIE) out _SFR_IO_ADDR(GIMSK), r18 ;; pwm_incoming = current_time - starttime lds r19, (starttime.0) + 1 lds r18, starttime.0 sub r20, r18 sbc r21, r19 sts (pwm_incoming) + 1, r21 sts pwm_incoming, r20 ;; signal upper layer lds r18, intbits ori r18, 1 sts intbits, r18 99: pop r21 pop r20 pop r19 pop r18 out _SFR_IO_ADDR(SREG), sreg_save reti #endif /* ATtiny13 */ avr-libc-1.8.0.orig/doc/examples/asmdemo/asmdemo.dox0000644000000000000000000002620011732702554017223 0ustar /* Copyright (c) 2006, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: asmdemo.dox 1368 2007-05-06 05:05:02Z arcanum $ */ /** \defgroup asmdemo Combining C and assembly source files \ingroup demos For time- or space-critical applications, it can often be desirable to combine C code (for easy maintenance) and assembly code (for maximal speed or minimal code size) together. This demo provides an example of how to do that. The objective of the demo is to decode radio-controlled model PWM signals, and control an output PWM based on the current input signal's value. The incoming PWM pulses follow a standard encoding scheme where a pulse width of 920 microseconds denotes one end of the scale (represented as 0 % pulse width on output), and 2120 microseconds mark the other end (100 % output PWM). Normally, multiple channels would be encoded that way in subsequent pulses, followed by a larger gap, so the entire frame will repeat each 14 through 20 ms, but this is ignored for the purpose of the demo, so only a single input PWM channel is assumed. The basic challenge is to use the cheapest controller available for the task, an ATtiny13 that has only a single timer channel. As this timer channel is required to run the outgoing PWM signal generation, the incoming PWM decoding had to be adjusted to the constraints set by the outgoing PWM. As PWM generation toggles the counting direction of timer 0 between up and down after each 256 timer cycles, the current time cannot be deduced by reading TCNT0 only, but the current counting direction of the timer needs to be considered as well. This requires servicing interrupts whenever the timer hits \e TOP (255) and \e BOTTOM (0) to learn about each change of the counting direction. For PWM generation, it is usually desired to run it at the highest possible speed so filtering the PWM frequency from the modulated output signal is made easy. Thus, the PWM timer runs at full CPU speed. This causes the overflow and compare match interrupts to be triggered each 256 CPU clocks, so they must run with the minimal number of processor cycles possible in order to not impose a too high CPU load by these interrupt service routines. This is the main reason to implement the entire interrupt handling in fine-tuned assembly code rather than in C. In order to verify parts of the algorithm, and the underlying hardware, the demo has been set up in a way so the pin-compatible but more expensive ATtiny45 (or its siblings ATtiny25 and ATtiny85) could be used as well. In that case, no separate assembly code is required, as two timer channels are avaible. \section asmdemo_hw Hardware setup The incoming PWM pulse train is fed into PB4. It will generate a pin change interrupt there on eache edge of the incoming signal. The outgoing PWM is generated through OC0B of timer channel 0 (PB1). For demonstration purposes, a LED should be connected to that pin (like, one of the LEDs of an STK500). The controllers run on their internal calibrated RC oscillators, 1.2 MHz on the ATtiny13, and 1.0 MHz on the ATtiny45. \section asmdemo_code A code walkthrough \subsection asmdemo_main asmdemo.c After the usual include files, two variables are defined. The first one, \c pwm_incoming is used to communicate the most recent pulse width detected by the incoming PWM decoder up to the main loop. The second variable actually only constitutes of a single bit, intbits.pwm_received. This bit will be set whenever the incoming PWM decoder has updated pwm_incoming. Both variables are marked \e volatile to ensure their readers will always pick up an updated value, as both variables will be set by interrupt service routines. The function \c ioinit() initializes the microcontroller peripheral devices. In particular, it starts timer 0 to generate the outgoing PWM signal on OC0B. Setting OCR0A to 255 (which is the \e TOP value of timer 0) is used to generate a timer 0 overflow A interrupt on the ATtiny13. This interrupt is used to inform the incoming PWM decoder that the counting direction of channel 0 is just changing from up to down. Likewise, an overflow interrupt will be generated whenever the countdown reached \e BOTTOM (value 0), where the counter will again alter its counting direction to upwards. This information is needed in order to know whether the current counter value of \c TCNT0 is to be evaluated from bottom or top. Further, \c ioinit() activates the pin-change interrupt \c PCINT0 on any edge of PB4. Finally, PB1 (OC0B) will be activated as an output pin, and global interrupts are being enabled. In the ATtiny45 setup, the C code contains an ISR for \c PCINT0. At each pin-change interrupt, it will first be analyzed whether the interrupt was caused by a rising or a falling edge. In case of the rising edge, timer 1 will be started with a prescaler of 16 after clearing the current timer value. Then, at the falling edge, the current timer value will be recorded (and timer 1 stopped), the pin-change interrupt will be suspended, and the upper layer will be notified that the incoming PWM measurement data is available. Function \c main() first initializes the hardware by calling \c ioinit(), and then waits until some incoming PWM value is available. If it is, the output PWM will be adjusted by computing the relative value of the incoming PWM. Finally, the pin-change interrupt is re-enabled, and the CPU is put to sleep. \subsection asmdemo_project project.h In order for the interrupt service routines to be as fast as possible, some of the CPU registers are set aside completely for use by these routines, so the compiler would not use them for C code. This is arranged for in project.h. The file is divided into one section that will be used by the assembly source code, and another one to be used by C code. The assembly part is distinguished by the preprocessing macro \c __ASSEMBLER__ (which will be automatically set by the compiler front-end when preprocessing an assembly-language file), and it contains just macros that give symbolic names to a number of CPU registers. The preprocessor will then replace the symbolic names by their right-hand side definitions before calling the assembler. In C code, the compiler needs to see variable declarations for these objects. This is done by using declarations that bind a variable permanently to a CPU register (see \ref faq_regbind). Even in case the C code never has a need to access these variables, declaring the register binding that way causes the compiler to not use these registers in C code at all. The \c flags variable needs to be in the range of r16 through r31 as it is the target of a load immediate (or \c SER) instruction that is not applicable to the entire register file. \subsection asmdemo_isrs isrs.S This file is a preprocessed assembly source file. The C preprocessor will be run by the compiler front-end first, resolving all \c \#include, \c \#define etc. directives. The resulting program text will then be passed on to the assembler. As the C preprocessor strips all C-style comments, preprocessed assembly source files can have both, C-style (/* ... */, // ...) as well as assembly-style (; ...) comments. At the top, the IO register definition file avr/io.h and the project declaration file project.h are included. The remainder of the file is conditionally assembled only if the target MCU type is an ATtiny13, so it will be completely ignored for the ATtiny45 option. Next are the two interrupt service routines for timer 0 compare A match (timer 0 hits \e TOP, as OCR0A is set to 255) and timer 0 overflow (timer 0 hits \e BOTTOM). As discussed above, these are kept as short as possible. They only save \c SREG (as the flags will be modified by the \c INC instruction), increment the \c counter_hi variable which forms the high part of the current time counter (the low part is formed by querying \c TCNT0 directly), and clear or set the variable \c flags, respectively, in order to note the current counting direction. The \c RETI instruction terminates these interrupt service routines. Total cycle count is 8 CPU cycles, so together with the 4 CPU cycles needed for interrupt setup, and the 2 cycles for the RJMP from the interrupt vector to the handler, these routines will require 14 out of each 256 CPU cycles, or about 5 % of the overall CPU time. The pin-change interrupt \c PCINT0 will be handled in the final part of this file. The basic algorithm is to quickly evaluate the current system time by fetching the current timer value of \c TCNT0, and combining it with the overflow part in \c counter_hi. If the counter is currently counting down rather than up, the value fetched from \c TCNT0 must be negated. Finally, if this pin-change interrupt was triggered by a rising edge, the time computed will be recorded as the start time only. Then, at the falling edge, this start time will be subracted from the current time to compute the actual pulse width seen (left in \c pwm_incoming), and the upper layers are informed of the new value by setting bit 0 in the \c intbits flags. At the same time, this pin-change interrupt will be disabled so no new measurement can be performed until the upper layer had a chance to process the current value. \section asmdemo_src The source code \htmlonly \endhtmlonly \latexonly The source code is installed under \texttt{\$prefix/share/doc/avr-libc/examples/asmdemo/}, where \texttt{\$prefix} is a configuration option. For Unix systems, it is usually set to either \texttt{/usr} or \texttt{/usr/local}. \endlatexonly */ avr-libc-1.8.0.orig/doc/examples/asmdemo/Makefile0000644000000000000000000001247211732702554016530 0ustar # Hey Emacs, this is a -*- makefile -*- # AVR-GCC Makefile template, derived from the WinAVR template (which # is public domain), believed to be neutral to any flavor of "make" # (GNU make, BSD make, SysV make) MCU = attiny13 #MCU = attiny45 FORMAT = ihex TARGET = asmdemo SRC = $(TARGET).c ASRC = isrs.S OPT = s # Name of this Makefile (used for "make depend"). MAKEFILE = Makefile # Compiler flag to set the C Standard level. # c89 - "ANSI" C # gnu89 - c89 plus GCC extensions # c99 - ISO C99 standard (not yet fully implemented) # gnu99 - c99 plus GCC extensions CSTANDARD = -std=gnu99 # Place -D or -U options here CDEFS = # Place -I options here CINCS = CDEBUG = -g CWARN = -Wall -Wstrict-prototypes CTUNING = -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums #CEXTRA = -Wa,-adhlns=$(<:.c=.lst) CFLAGS = $(CDEBUG) $(CDEFS) $(CINCS) -O$(OPT) $(CWARN) $(CSTANDARD) $(CEXTRA) #ASFLAGS = -Wa,-adhlns=$(<:.S=.lst),-gstabs #Additional libraries. # Minimalistic printf version PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min # Floating point printf version (requires MATH_LIB = -lm below) PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt PRINTF_LIB = # Minimalistic scanf version SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min # Floating point + %[ scanf version (requires MATH_LIB = -lm below) SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt SCANF_LIB = MATH_LIB = -lm # External memory options # 64 KB of external RAM, starting after internal RAM (ATmega128!), # used for variables (.data/.bss) and heap (malloc()). #EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff # 64 KB of external RAM, starting after internal RAM (ATmega128!), # only used for heap (malloc()). #EXTMEMOPTS = -Wl,--defsym=__heap_start=0x801100,--defsym=__heap_end=0x80ffff EXTMEMOPTS = #LDMAP = $(LDFLAGS) -Wl,-Map=$(TARGET).map,--cref LDFLAGS = $(EXTMEMOPTS) $(LDMAP) $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB) # Programming support using avrdude. Settings and variables. AVRDUDE_PROGRAMMER = stk500v2 AVRDUDE_PORT = /dev/cuaa1 AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex #AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep # Uncomment the following if you want avrdude's erase cycle counter. # Note that this counter needs to be initialized first using -Yn, # see avrdude manual. #AVRDUDE_ERASE_COUNTER = -y # Uncomment the following if you do /not/ wish a verification to be # performed after programming the device. #AVRDUDE_NO_VERIFY = -V # Increase verbosity level. Please use this when submitting bug # reports about avrdude. See # to submit bug reports. #AVRDUDE_VERBOSE = -v -v AVRDUDE_BASIC = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) AVRDUDE_FLAGS = $(AVRDUDE_BASIC) $(AVRDUDE_NO_VERIFY) $(AVRDUDE_VERBOSE) $(AVRDUDE_ERASE_COUNTER) CC = avr-gcc OBJCOPY = avr-objcopy OBJDUMP = avr-objdump SIZE = avr-size NM = avr-nm AVRDUDE = avrdude REMOVE = rm -f MV = mv -f # Define all object files. OBJ = $(SRC:.c=.o) $(ASRC:.S=.o) # Define all listing files. LST = $(ASRC:.S=.lst) $(SRC:.c=.lst) # Combine all necessary flags and optional flags. # Add target processor to flags. ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) # Default target. all: build build: elf hex eep elf: $(TARGET).elf hex: $(TARGET).hex eep: $(TARGET).eep lss: $(TARGET).lss sym: $(TARGET).sym # Program the device. program: $(TARGET).hex $(TARGET).eep $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) # Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB. COFFCONVERT=$(OBJCOPY) --debugging \ --change-section-address .data-0x800000 \ --change-section-address .bss-0x800000 \ --change-section-address .noinit-0x800000 \ --change-section-address .eeprom-0x810000 coff: $(TARGET).elf $(COFFCONVERT) -O coff-avr $(TARGET).elf $(TARGET).cof extcoff: $(TARGET).elf $(COFFCONVERT) -O coff-ext-avr $(TARGET).elf $(TARGET).cof .SUFFIXES: .elf .hex .eep .lss .sym .elf.hex: $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ .elf.eep: -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ --change-section-lma .eeprom=0 -O $(FORMAT) $< $@ # Create extended listing file from ELF output file. .elf.lss: $(OBJDUMP) -h -S $< > $@ # Create a symbol table from ELF output file. .elf.sym: $(NM) -n $< > $@ # Link: create ELF output file from object files. $(TARGET).elf: $(OBJ) $(CC) $(ALL_CFLAGS) $(OBJ) --output $@ $(LDFLAGS) # Compile: create object files from C source files. .c.o: $(CC) -c $(ALL_CFLAGS) $< -o $@ # Compile: create assembler files from C source files. .c.s: $(CC) -S $(ALL_CFLAGS) $< -o $@ # Assemble: create object files from assembler source files. .S.o: $(CC) -c $(ALL_ASFLAGS) $< -o $@ # Target: clean project. clean: $(REMOVE) $(TARGET).hex $(TARGET).eep $(TARGET).cof $(TARGET).elf \ $(TARGET).map $(TARGET).sym $(TARGET).lss \ $(OBJ) $(LST) $(SRC:.c=.s) $(SRC:.c=.d) depend: if grep '^# DO NOT DELETE' $(MAKEFILE) >/dev/null; \ then \ sed -e '/^# DO NOT DELETE/,$$d' $(MAKEFILE) > \ $(MAKEFILE).$$$$ && \ $(MV) $(MAKEFILE).$$$$ $(MAKEFILE); \ fi echo '# DO NOT DELETE THIS LINE -- make depend depends on it.' \ >> $(MAKEFILE); \ $(CC) -M -mmcu=$(MCU) $(CDEFS) $(CINCS) $(SRC) $(ASRC) >> $(MAKEFILE) .PHONY: all build elf hex eep lss sym program coff extcoff clean depend avr-libc-1.8.0.orig/doc/examples/asmdemo/project.h0000644000000000000000000000154711732702554016710 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * Joerg Wunsch wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * Demo combining C and assembly source files. * * $Id: project.h 1124 2006-08-29 19:45:06Z joerg_wunsch $ */ /* * Global register variables. */ #ifdef __ASSEMBLER__ # define sreg_save r2 # define flags r16 # define counter_hi r4 #else /* !ASSEMBLER */ #include register uint8_t sreg_save asm("r2"); register uint8_t flags asm("r16"); register uint8_t counter_hi asm("r4"); #endif /* ASSEMBLER */ avr-libc-1.8.0.orig/doc/examples/asmdemo/asmdemo.c0000644000000000000000000000716711732702554016666 0ustar /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * Joerg Wunsch wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch * ---------------------------------------------------------------------------- * * Demo combining C and assembly source files. * * This demo implements an RC model type PWM decoder. The incoming * PWM signal consists of a pulse sequence with a pulse width of 920 * microseconds up to 2120 microseconds (1520 microseconds being the * neutral point). Depending on the value of the decoded incoming * PWM, an outgoing PWM is controlled between 0 and 100 %. * * The project is intented to be run on an ATtiny13 that has only one * timer channel (timer 0), so both the incoming signal discrimination * as well as the outgoing PWM need to run on the same timer. * * For verification purposes, the same project can also be run on an * ATtiny25/45/85, where timer 1 can be used to evaluate the incoming * PWM signal, and timer 0 to generate the outgoing PWM. In that * case, no additional assembly code is needed. * * $Id: asmdemo.c 1124 2006-08-29 19:45:06Z joerg_wunsch $ */ /* * This is the main C source file for the demo. */ #include #include #include #include "project.h" volatile uint16_t pwm_incoming; volatile struct { uint8_t pwm_received: 1; } intbits; void ioinit(void) { counter_hi = 0; flags = 0; /* * Timer 0 runs as phase-correct PWM at full clock, OC0B connects to * the PWM engine. */ TCCR0A = (1 << COM0B1) | (1 << WGM00); TCCR0B = (1 << CS00); OCR0A = 255; #if defined(__AVR_ATtiny13__) TIMSK0 = (1 << TOIE0) | (1 << OCIE0A); # define F_CPU 1200000ul /* Minimal PWM pulse width is 920 us. */ # define MIN_PWM_VAL ((920ul * F_CPU) / 1000000ul) /* Maximal PWM pulse width is 2120 us */ # define MAX_PWM_VAL ((2120ul * F_CPU) / 1000000ul) #elif defined(__AVR_ATtiny25__) ||\ defined(__AVR_ATtiny45__) ||\ defined(__AVR_ATtiny85__) # define F_CPU 1000000ul /* * We use a prescaler of 16 here to avoid the 32-bit calculations * below. */ /* Minimal PWM pulse width is 920 us. */ # define MIN_PWM_VAL ((920ul * F_CPU) / 16 / 1000000ul) /* Maximal PWM pulse width is 2120 us */ # define MAX_PWM_VAL ((2120ul * F_CPU) / 16 / 1000000ul) #else # error "Don't know how to run on your MCU_TYPE." #endif PCMSK = (1 << 4); GIFR = (1 << PCIF); GIMSK = (1 << PCIE); DDRB = (1 << PB1); PORTB = 0; sei(); } #if defined(__AVR_ATtiny25__) ||\ defined(__AVR_ATtiny45__) ||\ defined(__AVR_ATtiny85__) ISR(PCINT0_vect) { uint8_t tcnt1; if (PINB & (1 << 4)) { /* Start timer 1 with a prescaler of 16. */ TCNT1 = 0; TCCR1 = (1 << CS12) | (1 << CS10); return; } /* Stop timer 1, current value is pulse width. */ tcnt1 = TCNT1; TCCR1 = 0; GIMSK &= ~(1 << PCIE); pwm_incoming = tcnt1; intbits.pwm_received = 1; } #endif /* ATtinyX5 */ int main(void) { ioinit(); for (;;) { if (intbits.pwm_received) { intbits.pwm_received = 0; #if defined(__AVR_ATtiny13__) if (pwm_incoming < MIN_PWM_VAL) pwm_incoming = MIN_PWM_VAL; else if (pwm_incoming > MAX_PWM_VAL) pwm_incoming = MAX_PWM_VAL; OCR0B = (pwm_incoming - MIN_PWM_VAL) * 255ul / (MAX_PWM_VAL - MIN_PWM_VAL); #else OCR0B = (pwm_incoming - MIN_PWM_VAL) * 255u / (MAX_PWM_VAL - MIN_PWM_VAL); #endif GIFR = (1 << PCIF); GIMSK |= (1 << PCIE); } sleep_mode(); } } avr-libc-1.8.0.orig/doc/examples/Makefile.am0000644000000000000000000000763011732702554015477 0ustar # # Copyright (c) 2002,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # 3. The name of the author may not be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN # NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED # TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR # PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Author: Theodore A. Roth # # Contributors: # # $Id: Makefile.am 1124 2006-08-29 19:45:06Z joerg_wunsch $ # MAINTAINERCLEANFILES = Makefile.in DEMO_SRCS = \ asmdemo/Makefile \ asmdemo/asmdemo.c \ asmdemo/isrs.S \ asmdemo/project.h \ demo/Makefile \ demo/demo.c \ demo/iocompat.h \ largedemo/Makefile \ largedemo/largedemo.c \ stdiodemo/Makefile \ stdiodemo/defines.h \ stdiodemo/hd44780.c \ stdiodemo/hd44780.h \ stdiodemo/lcd.c \ stdiodemo/lcd.h \ stdiodemo/stdiodemo.c \ stdiodemo/uart.c \ stdiodemo/uart.h \ twitest/Makefile \ twitest/twitest.c DEMO_DIRS = asmdemo \ demo \ largedemo \ stdiodemo \ twitest EXTRA_DIST = ${DEMO_SRCS} \ all-demos.dox \ asmdemo/asmdemo.dox \ demo/demo.fig \ demo/demo.dox \ largedemo/largedemo-setup.jpg \ largedemo/largedemo-wiring.jpg \ largedemo/largedemo-wiring2.jpg \ largedemo/largedemo.dox \ stdiodemo/stdiodemo-setup.jpg \ stdiodemo/stdiodemo.dox \ twitest/twitest.dox # Install demo source files. install-data-local: $(mkinstalldirs) $(DOC_INST_DIR)/examples for dir in $(DEMO_DIRS) ; do \ $(mkinstalldirs) $(DOC_INST_DIR)/examples/$$dir; \ done for file in $(DEMO_SRCS) ; do \ echo "Installing $$file into $(DOC_INST_DIR)/examples/$$file"; \ $(INSTALL_DATA) $(top_srcdir)/doc/examples/$$file \ $(DOC_INST_DIR)/examples/$$file; \ done uninstall-local: for file in $(DEMO_SRCS) ; do \ echo "Removing $(DOC_INST_DIR)/examples/$$file"; \ rm -f $(DOC_INST_DIR)/examples/$$file; \ done for dir in $(DEMO_DIRS) ; do \ rmdir $(DOC_INST_DIR)/examples/$$dir || \ echo "rmdir $(DOC_INST_DIR)/examples/$$dir failed."; \ done rmdir $(DOC_INST_DIR)/examples ||\ echo "rmdir $(DOC_INST_DIR)/examples failed." avr-libc-1.8.0.orig/doc/Makefile.am0000644000000000000000000000332611732702554013657 0ustar # # Copyright (c) 2002 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # 3. The name of the author may not be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN # NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED # TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR # PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Author: Theodore A. Roth # # Contributors: # # $Id: Makefile.am 1018 2005-12-31 18:42:02Z joerg_wunsch $ # MAINTAINERCLEANFILES = Makefile.in SUBDIRS = examples @DOCSDIR@ DIST_SUBDIRS = examples api EXTRA_DIST = CHANGES.old ChangeLog INSTALL TODO avr-libc-1.8.0.orig/doc/ChangeLog0000644000000000000000000000010611732702554013366 0ustar Please put all new ChangeLog entries in the top level ChangeLog File. avr-libc-1.8.0.orig/doc/CHANGES.old0000644000000000000000000001706711732702554013402 0ustar PLEASE read doc/INSTALL first for installation instructions. Changes: avr-libc-20011208 Add ATmega8 support (not yet enabled), thanks to Pieter Conradie. Add missing UCSR1C and fix INT_VECT_SIZE in iom128.h. ===== avr-libc-20011126 Changes to support ATmega128 (for now commented out in Makefile until the necessary changes are made to gcc and binutils) and make it easier to add other new devices (cleaned up gcrt1.S interrupt vectors), thanks to Peter Jansen . Note: I haven't tested anything yet, other than it compiles ;) ===== avr-libc-20011029 Fix strtod() link error (fp_zero -> __fp_zero). Split eeprom.o into 4 object files (one function in each file). ===== Changes: avr-libc-20011007 Add avr-libc-reference.html document. Use "install -c" (ignored by GNU fileutils, needed on FreeBSD). Add isblank(). ===== avr-libc-20010821 Add atan2() and new atan(), thanks to Reiner Patommel. ===== avr-libc-20010717 Remember to update version in Makefile this time, this only matters for Makefile-win32 which has some known bugs, please help fix them. Update fplib license, now GPL + exception as in gcrt1.S and libgcc, now OK for proprietary applications too, thanks to Michael Stumpf. Fix strtod() whitespace handling, as in atoi(). More atoi() changes (now it's smaller) by Jochen Pernsteiner. ===== avr-libc-20010708 Add atan(), contributed by Reiner Patommel. Fix atoi() whitespace handling, reported by Jochen Pernsteiner. Alternative version of bit_is_set/bit_is_clear macros that can make better optimized code, suggested by Thomas Husterer. Fix bug in __fixsfsi for numbers <1.0, thanks to Michael Stumpf. Fix fplib/strtod.S and stdlib/atoi.S to not call __mulhi3, call a new optimized function __mulhi_const_10 instead. Use XCALL to call any external functions (might not be reachable for RCALL on >8K devices). ===== avr-libc-20010701 Add a few more asm string functions, thanks to Reiner Patommel (atoi, strcasecmp, strcasecmp_P, strcat_P, strncasecmp, strncasecmp_P, strlwr, strrev, strupr), changed by me to use standard (glibc, BSD) instead of DOS (stricmp etc.) names. ===== avr-libc-20010616 Tested with gcc 3.0 20010526 and binutils 010609 snapshots. Add strstr() (in assembler), thanks to Jochen Pernsteiner. Fix fplib/asin.S (P3 value), thanks to Dean Ferreyra. Fix itoa() again... even tested it this time ;). Fix div() and ldiv() to call the new libgcc functions, too. Fix gnu/qsort.c to compile without . Separate Makefile-win32 for now (patches welcome and probably needed, it's just that I don't want them to break the Linux/*BSD Makefile in subtle unexpected ways that only show up on the first "make install" so I didn't catch them), help needed from someone who is good at writing portable Makefiles as I'm not :(. Move README to doc/CHANGES as that's what it really is. ===== avr-libc-20010331 Updated itoa() to work with current CVS libgcc (use __udivmodhi4). Updated iotn15.h (ATtiny15 I/O registers defines). ===== avr-libc-20010303 Merged some Makefile changes for win32 support (don't ask me how it works :), thanks to Gunnar.Henne@gmx.de (http://combio.de/avr/). ===== avr-libc-20010211 Minor changes (there are no bugs :), added new parity_even_bit() macro. Now available from http://www.amelek.gda.pl/avr/ (the previous URL - http://www.itnet.pl/amelektr/avr/ - will be available for some time). ===== avr-libc-20001125 More fplib bug fixes (can't depend on r1 being 0 in fp_split, fixsfsi should correctly return 0 for very small numbers, dtostre fixes). Again thanks to Kovesdi Gyorgy. ===== avr-libc-20001118 Some fplib fixes (compare return values changed to match what GCC expects; fp_split does not set the "hidden bit" if exponent is 0). Thanks to Kovesdi Gyorgy . Updated ATmega163 defines (iom163.h) now that the official datasheet is released. Added preliminary AT76C711 defines (io76c711.h). Added copyright information (doc/LICENSE), released the files written by me as public domain (they have always been open source, but the wording of the copyright was a bit unfortunate). ===== avr-libc-20000730 Added multilib support for latest CVS avr-gcc changes. Renamed gcrt1-*.o to crt*.o (unique on 8.3 filesystems). Many other changes. ===== avr-libc-20000514 Minor tweaks, _end_of_ram_ -> __bss_end in malloc (please test - I've never had to use malloc on AVR yet), added -mcall-prologues so big C functions are smaller (prologue/epilogue only pulled in from libgcc if any of these functions are used - in this case it is a win to compile everything else with -mcall-prologues too), made strtod() use libgcc prologue/epilogue instead of its own. ===== avr-libc-20000503 More optimized asm string functions, more gcrt1.S hacks, added almost-IAR-compatible and . Please test with current CVS binutils and gcc - thanks. Marek ===== README for avr-libc-20000402 OK, approved :) - finally found some time and made some more cleanups, added early MCUCR and WDTCR initialization in gcrt1.S - for example, to enable WDT with maximum timeout and enable slow external SRAM, add these options to linker command line (via avr-gcc -Wl,...): --defsym __init_wdtcr__=0x0F --defsym __init_mcucr__=0xC0 Marek ===== README for additions / changes in avr-libc-20000207 as compared to avr-libc-20000201 which have not been tested or approved by Marek Michalkiewicz yet. These additions were done with the Win32 port of avr-gcc. Thus Linux users may have to change CR/LFs to CRs tune the Makefile to their needs Makefile: The new Makefile is needed to build all the additions to the lib. I tried to make it compatible with both Linux and Win32. Mareks original Makefile has been renamed to Makefile.orig. libm: Michael Stumpfs FPlib3.0 ported to avr-as Michael Stumpfs strtod function ported to avr-as but not tested yet libc: Michael Stumpfs ctype routines ported to avr-as non-ANSI C standard additions: dtostre (stdlib.h, libm.a) largely rewritten, Unix-like itoa (stdlib.h, libc.a), Windows / OS2-like changes to macros.inc added FARCALL (rcall / call) in analogy to VECTOR (rjmp / jmp) changes to progmem.h disabled #define PRG_RDB(addr) __elpm_inline(addr) because of too many complaints by mega103 users. If you use > 64kB program memory, try experimenting with __elpm_inline directly. Michael Rickmann ===== README for avr-libc-20000201 This release fixes a few little bugs in the previous release. Most important: should work on ATmega103 now - gcrt1.S uses "jmp" instead of "rjmp" to jump to main(). ===== README for avr-libc-19991224 This release requires the latest avr-binutils and avr-gcc versions. Use of AVA assembler and linker is no longer supported (sorry, right now I'm extremely busy and backward compatibility was too much work - when finished, everyone would have been using binutils for years anyway :). Warning: this is work in progress. Not all features of previous avr-libc releases are supported yet: - fplib (needs to be ported to binutils first) - early MCUCR (required for external SRAM) and WDTCR initialization - optimized asm string functions (slightly larger/slower C versions available for now) - anything else I forgot? If you need support for AVA and/or any of the missing features, please use the older avr-libc-19991010 release, or help me by sending patches to implement features you need. Installation instructions are in doc/INSTALL. I have tested this version a little with AT90S8535 (used in the project I'm working on). Please test it more. Suggestions, bug reports, patches and new code are welcome. Thanks! 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" >&6; } has_pngtopnm=`pngtopnm --version 2>&1 | grep -c -i Version` if test "$has_pngtopnm" = "1"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } PNGTOPNM="pngtopnm" else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } PNGTOPNM="cat" fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking for pnmtopng" >&5 $as_echo_n "checking for pnmtopng... " >&6; } has_pnmtopng=`pnmtopng --version 2>&1 | grep -c -i Version` if test "$has_pnmtopng" = "1"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } PNMTOPNG="pnmtopng" else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } PNMTOPNG="cat" PNGTOPNM="cat" fi if test "$versioned_doc" = "yes"; then DOC_INST_DIR='${DESTDIR}${datadir}/doc/avr-libc-$(VERSION)' AVR_LIBC_USER_MANUAL="avr-libc-user-manual-${VERSION}" else DOC_INST_DIR='${DESTDIR}${datadir}/doc/avr-libc' AVR_LIBC_USER_MANUAL="avr-libc-user-manual" fi if test "$enable_doc" = "yes"; then DOCSDIR='api' else DOCSDIR='' fi FNO_JUMP_TABLES="" HAS_DELAY_CYCLES=0 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mno-tablejump" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${CC} supports -mno-tablejump" >&5 $as_echo_n "checking whether ${CC} supports -mno-tablejump... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_mno_tablejump=yes else has_mno_tablejump=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_mno_tablejump" = "xyes" then FNO_JUMP_TABLES="-mno-tablejump" fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_mno_tablejump" >&5 $as_echo "$has_mno_tablejump" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-fno-jump-tables" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${CC} supports -fno-jump-tables" >&5 $as_echo_n "checking whether ${CC} supports -fno-jump-tables... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_fno_jump_tables=yes else has_fno_jump_tables=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_fno_jump_tables" = "xyes" then FNO_JUMP_TABLES="-fno-jump-tables" fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_fno_jump_tables" >&5 $as_echo "$has_fno_jump_tables" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${CC} supports __builtin_avr_delay_cycles" >&5 $as_echo_n "checking whether ${CC} supports __builtin_avr_delay_cycles... " >&6; } echo "extern void __builtin_avr_delay_cycles(unsigned long);\ int main(void) { __builtin_avr_delay_cycles(42); return 0; }" |\ ${CC} -S -xc -o- - |\ grep __builtin_avr_delay_cycles >/dev/null if test "$?" != "0" then HAS_DELAY_CYCLES=1 has_delay_cycles="yes" else has_delay_cycles="no" fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_delay_cycles" >&5 $as_echo "$has_delay_cycles" >&6; } CC=${old_CC} # avr1 if true; then HAS_avr1_TRUE= HAS_avr1_FALSE='#' else HAS_avr1_TRUE='#' HAS_avr1_FALSE= fi if true; then HAS_at90s1200_TRUE= HAS_at90s1200_FALSE='#' else HAS_at90s1200_TRUE='#' HAS_at90s1200_FALSE= fi if true; then HAS_attiny11_TRUE= HAS_attiny11_FALSE='#' else HAS_attiny11_TRUE='#' HAS_attiny11_FALSE= fi if true; then HAS_attiny12_TRUE= HAS_attiny12_FALSE='#' else HAS_attiny12_TRUE='#' HAS_attiny12_FALSE= fi if true; then HAS_attiny15_TRUE= HAS_attiny15_FALSE='#' else HAS_attiny15_TRUE='#' HAS_attiny15_FALSE= fi if true; then HAS_attiny28_TRUE= HAS_attiny28_FALSE='#' else HAS_attiny28_TRUE='#' HAS_attiny28_FALSE= fi # avr2 if true; then HAS_avr2_TRUE= HAS_avr2_FALSE='#' else HAS_avr2_TRUE='#' HAS_avr2_FALSE= fi if true; then HAS_at90s2313_TRUE= HAS_at90s2313_FALSE='#' else HAS_at90s2313_TRUE='#' HAS_at90s2313_FALSE= fi if true; then HAS_at90s2323_TRUE= HAS_at90s2323_FALSE='#' else HAS_at90s2323_TRUE='#' HAS_at90s2323_FALSE= fi if true; then HAS_at90s2333_TRUE= HAS_at90s2333_FALSE='#' else HAS_at90s2333_TRUE='#' HAS_at90s2333_FALSE= fi if true; then HAS_at90s2343_TRUE= HAS_at90s2343_FALSE='#' else HAS_at90s2343_TRUE='#' HAS_at90s2343_FALSE= fi if true; then HAS_at90s4414_TRUE= HAS_at90s4414_FALSE='#' else HAS_at90s4414_TRUE='#' HAS_at90s4414_FALSE= fi if true; then HAS_at90s4433_TRUE= HAS_at90s4433_FALSE='#' else HAS_at90s4433_TRUE='#' HAS_at90s4433_FALSE= fi if true; then HAS_at90s4434_TRUE= HAS_at90s4434_FALSE='#' else HAS_at90s4434_TRUE='#' HAS_at90s4434_FALSE= fi if true; then HAS_at90s8515_TRUE= HAS_at90s8515_FALSE='#' else HAS_at90s8515_TRUE='#' HAS_at90s8515_FALSE= fi if true; then HAS_at90c8534_TRUE= HAS_at90c8534_FALSE='#' else HAS_at90c8534_TRUE='#' HAS_at90c8534_FALSE= fi if true; then HAS_at90s8535_TRUE= HAS_at90s8535_FALSE='#' else HAS_at90s8535_TRUE='#' HAS_at90s8535_FALSE= fi if true; then HAS_attiny22_TRUE= HAS_attiny22_FALSE='#' else HAS_attiny22_TRUE='#' HAS_attiny22_FALSE= fi if true; then HAS_attiny26_TRUE= HAS_attiny26_FALSE='#' else HAS_attiny26_TRUE='#' HAS_attiny26_FALSE= fi #avr25 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avr25" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr25" >&5 $as_echo_n "checking if ${CC} has support for avr25... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avr25=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avr25" = "xyes"; then HAS_avr25_TRUE= HAS_avr25_FALSE='#' else HAS_avr25_TRUE='#' HAS_avr25_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=ata6289" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6289" >&5 $as_echo_n "checking if ${CC} has support for ata6289... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_ata6289=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_ata6289" = "xyes"; then HAS_ata6289_TRUE= HAS_ata6289_FALSE='#' else HAS_ata6289_TRUE='#' HAS_ata6289_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny13" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny13" >&5 $as_echo_n "checking if ${CC} has support for attiny13... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny13=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny13" = "xyes"; then HAS_attiny13_TRUE= HAS_attiny13_FALSE='#' else HAS_attiny13_TRUE='#' HAS_attiny13_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny13a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny13a" >&5 $as_echo_n "checking if ${CC} has support for attiny13a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny13a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny13a" = "xyes"; then HAS_attiny13a_TRUE= HAS_attiny13a_FALSE='#' else HAS_attiny13a_TRUE='#' HAS_attiny13a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny2313" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny2313" >&5 $as_echo_n "checking if ${CC} has support for attiny2313... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny2313=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny2313" = "xyes"; then HAS_attiny2313_TRUE= HAS_attiny2313_FALSE='#' else HAS_attiny2313_TRUE='#' HAS_attiny2313_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny2313a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny2313a" >&5 $as_echo_n "checking if ${CC} has support for attiny2313a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny2313a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny2313a" = "xyes"; then HAS_attiny2313a_TRUE= HAS_attiny2313a_FALSE='#' else HAS_attiny2313a_TRUE='#' HAS_attiny2313a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny24" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny24" >&5 $as_echo_n "checking if ${CC} has support for attiny24... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny24=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny24" = "xyes"; then HAS_attiny24_TRUE= HAS_attiny24_FALSE='#' else HAS_attiny24_TRUE='#' HAS_attiny24_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny24a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny24a" >&5 $as_echo_n "checking if ${CC} has support for attiny24a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny24a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny24a" = "xyes"; then HAS_attiny24a_TRUE= HAS_attiny24a_FALSE='#' else HAS_attiny24a_TRUE='#' HAS_attiny24a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny25" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny25" >&5 $as_echo_n "checking if ${CC} has support for attiny25... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny25=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny25" = "xyes"; then HAS_attiny25_TRUE= HAS_attiny25_FALSE='#' else HAS_attiny25_TRUE='#' HAS_attiny25_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny261" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny261" >&5 $as_echo_n "checking if ${CC} has support for attiny261... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny261=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny261" = "xyes"; then HAS_attiny261_TRUE= HAS_attiny261_FALSE='#' else HAS_attiny261_TRUE='#' HAS_attiny261_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny261a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny261a" >&5 $as_echo_n "checking if ${CC} has support for attiny261a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny261a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny261a" = "xyes"; then HAS_attiny261a_TRUE= HAS_attiny261a_FALSE='#' else HAS_attiny261a_TRUE='#' HAS_attiny261a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny43u" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny43u" >&5 $as_echo_n "checking if ${CC} has support for attiny43u... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny43u=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny43u" = "xyes"; then HAS_attiny43u_TRUE= HAS_attiny43u_FALSE='#' else HAS_attiny43u_TRUE='#' HAS_attiny43u_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny4313" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny4313" >&5 $as_echo_n "checking if ${CC} has support for attiny4313... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny4313=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny4313" = "xyes"; then HAS_attiny4313_TRUE= HAS_attiny4313_FALSE='#' else HAS_attiny4313_TRUE='#' HAS_attiny4313_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny44" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny44" >&5 $as_echo_n "checking if ${CC} has support for attiny44... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny44=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny44" = "xyes"; then HAS_attiny44_TRUE= HAS_attiny44_FALSE='#' else HAS_attiny44_TRUE='#' HAS_attiny44_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny44a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny44a" >&5 $as_echo_n "checking if ${CC} has support for attiny44a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny44a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny44a" = "xyes"; then HAS_attiny44a_TRUE= HAS_attiny44a_FALSE='#' else HAS_attiny44a_TRUE='#' HAS_attiny44a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny45" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny45" >&5 $as_echo_n "checking if ${CC} has support for attiny45... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny45=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny45" = "xyes"; then HAS_attiny45_TRUE= HAS_attiny45_FALSE='#' else HAS_attiny45_TRUE='#' HAS_attiny45_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny461" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny461" >&5 $as_echo_n "checking if ${CC} has support for attiny461... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny461=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny461" = "xyes"; then HAS_attiny461_TRUE= HAS_attiny461_FALSE='#' else HAS_attiny461_TRUE='#' HAS_attiny461_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny461a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny461a" >&5 $as_echo_n "checking if ${CC} has support for attiny461a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny461a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny461a" = "xyes"; then HAS_attiny461a_TRUE= HAS_attiny461a_FALSE='#' else HAS_attiny461a_TRUE='#' HAS_attiny461a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny48" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny48" >&5 $as_echo_n "checking if ${CC} has support for attiny48... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny48=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny48" = "xyes"; then HAS_attiny48_TRUE= HAS_attiny48_FALSE='#' else HAS_attiny48_TRUE='#' HAS_attiny48_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny84" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny84" >&5 $as_echo_n "checking if ${CC} has support for attiny84... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny84=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny84" = "xyes"; then HAS_attiny84_TRUE= HAS_attiny84_FALSE='#' else HAS_attiny84_TRUE='#' HAS_attiny84_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny84a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny84a" >&5 $as_echo_n "checking if ${CC} has support for attiny84a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny84a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny84a" = "xyes"; then HAS_attiny84a_TRUE= HAS_attiny84a_FALSE='#' else HAS_attiny84a_TRUE='#' HAS_attiny84a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny85" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny85" >&5 $as_echo_n "checking if ${CC} has support for attiny85... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny85=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny85" = "xyes"; then HAS_attiny85_TRUE= HAS_attiny85_FALSE='#' else HAS_attiny85_TRUE='#' HAS_attiny85_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny861" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny861" >&5 $as_echo_n "checking if ${CC} has support for attiny861... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny861=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny861" = "xyes"; then HAS_attiny861_TRUE= HAS_attiny861_FALSE='#' else HAS_attiny861_TRUE='#' HAS_attiny861_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny861a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny861a" >&5 $as_echo_n "checking if ${CC} has support for attiny861a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny861a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny861a" = "xyes"; then HAS_attiny861a_TRUE= HAS_attiny861a_FALSE='#' else HAS_attiny861a_TRUE='#' HAS_attiny861a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny87" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny87" >&5 $as_echo_n "checking if ${CC} has support for attiny87... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny87=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny87" = "xyes"; then HAS_attiny87_TRUE= HAS_attiny87_FALSE='#' else HAS_attiny87_TRUE='#' HAS_attiny87_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny88" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny88" >&5 $as_echo_n "checking if ${CC} has support for attiny88... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny88=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny88" = "xyes"; then HAS_attiny88_TRUE= HAS_attiny88_FALSE='#' else HAS_attiny88_TRUE='#' HAS_attiny88_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at86rf401" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at86rf401" >&5 $as_echo_n "checking if ${CC} has support for at86rf401... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at86rf401=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at86rf401" = "xyes"; then HAS_at86rf401_TRUE= HAS_at86rf401_FALSE='#' else HAS_at86rf401_TRUE='#' HAS_at86rf401_FALSE= fi # avr3 if true; then HAS_avr3_TRUE= HAS_avr3_FALSE='#' else HAS_avr3_TRUE='#' HAS_avr3_FALSE= fi if true; then HAS_at43usb320_TRUE= HAS_at43usb320_FALSE='#' else HAS_at43usb320_TRUE='#' HAS_at43usb320_FALSE= fi if true; then HAS_at43usb355_TRUE= HAS_at43usb355_FALSE='#' else HAS_at43usb355_TRUE='#' HAS_at43usb355_FALSE= fi if true; then HAS_at76c711_TRUE= HAS_at76c711_FALSE='#' else HAS_at76c711_TRUE='#' HAS_at76c711_FALSE= fi #avr31 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avr31" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr31" >&5 $as_echo_n "checking if ${CC} has support for avr31... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avr31=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avr31" = "xyes"; then HAS_avr31_TRUE= HAS_avr31_FALSE='#' else HAS_avr31_TRUE='#' HAS_avr31_FALSE= fi if true; then HAS_atmega103_TRUE= HAS_atmega103_FALSE='#' else HAS_atmega103_TRUE='#' HAS_atmega103_FALSE= fi #avr35 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avr35" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr35" >&5 $as_echo_n "checking if ${CC} has support for avr35... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avr35=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avr35" = "xyes"; then HAS_avr35_TRUE= HAS_avr35_FALSE='#' else HAS_avr35_TRUE='#' HAS_avr35_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90usb82" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb82" >&5 $as_echo_n "checking if ${CC} has support for at90usb82... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90usb82=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90usb82" = "xyes"; then HAS_at90usb82_TRUE= HAS_at90usb82_FALSE='#' else HAS_at90usb82_TRUE='#' HAS_at90usb82_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90usb162" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb162" >&5 $as_echo_n "checking if ${CC} has support for at90usb162... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90usb162=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90usb162" = "xyes"; then HAS_at90usb162_TRUE= HAS_at90usb162_FALSE='#' else HAS_at90usb162_TRUE='#' HAS_at90usb162_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega8u2" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega8u2" >&5 $as_echo_n "checking if ${CC} has support for atmega8u2... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega8u2=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega8u2" = "xyes"; then HAS_atmega8u2_TRUE= HAS_atmega8u2_FALSE='#' else HAS_atmega8u2_TRUE='#' HAS_atmega8u2_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega16u2" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16u2" >&5 $as_echo_n "checking if ${CC} has support for atmega16u2... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega16u2=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega16u2" = "xyes"; then HAS_atmega16u2_TRUE= HAS_atmega16u2_FALSE='#' else HAS_atmega16u2_TRUE='#' HAS_atmega16u2_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega32u2" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32u2" >&5 $as_echo_n "checking if ${CC} has support for atmega32u2... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega32u2=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega32u2" = "xyes"; then HAS_atmega32u2_TRUE= HAS_atmega32u2_FALSE='#' else HAS_atmega32u2_TRUE='#' HAS_atmega32u2_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny167" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny167" >&5 $as_echo_n "checking if ${CC} has support for attiny167... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny167=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny167" = "xyes"; then HAS_attiny167_TRUE= HAS_attiny167_FALSE='#' else HAS_attiny167_TRUE='#' HAS_attiny167_FALSE= fi # avr4 if true; then HAS_avr4_TRUE= HAS_avr4_FALSE='#' else HAS_avr4_TRUE='#' HAS_avr4_FALSE= fi if true; then HAS_atmega8_TRUE= HAS_atmega8_FALSE='#' else HAS_atmega8_TRUE='#' HAS_atmega8_FALSE= fi if true; then HAS_atmega8515_TRUE= HAS_atmega8515_FALSE='#' else HAS_atmega8515_TRUE='#' HAS_atmega8515_FALSE= fi if true; then HAS_atmega8535_TRUE= HAS_atmega8535_FALSE='#' else HAS_atmega8535_TRUE='#' HAS_atmega8535_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega48" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48" >&5 $as_echo_n "checking if ${CC} has support for atmega48... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega48=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega48" = "xyes"; then HAS_atmega48_TRUE= HAS_atmega48_FALSE='#' else HAS_atmega48_TRUE='#' HAS_atmega48_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega48a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48a" >&5 $as_echo_n "checking if ${CC} has support for atmega48a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega48a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega48a" = "xyes"; then HAS_atmega48a_TRUE= HAS_atmega48a_FALSE='#' else HAS_atmega48a_TRUE='#' HAS_atmega48a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega48p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48p" >&5 $as_echo_n "checking if ${CC} has support for atmega48p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega48p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega48p" = "xyes"; then HAS_atmega48p_TRUE= HAS_atmega48p_FALSE='#' else HAS_atmega48p_TRUE='#' HAS_atmega48p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega88" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88" >&5 $as_echo_n "checking if ${CC} has support for atmega88... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega88=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega88" = "xyes"; then HAS_atmega88_TRUE= HAS_atmega88_FALSE='#' else HAS_atmega88_TRUE='#' HAS_atmega88_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega88a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88a" >&5 $as_echo_n "checking if ${CC} has support for atmega88a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega88a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega88a" = "xyes"; then HAS_atmega88a_TRUE= HAS_atmega88a_FALSE='#' else HAS_atmega88a_TRUE='#' HAS_atmega88a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega88p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88p" >&5 $as_echo_n "checking if ${CC} has support for atmega88p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega88p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega88p" = "xyes"; then HAS_atmega88p_TRUE= HAS_atmega88p_FALSE='#' else HAS_atmega88p_TRUE='#' HAS_atmega88p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega88pa" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88pa" >&5 $as_echo_n "checking if ${CC} has support for atmega88pa... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega88pa=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega88pa" = "xyes"; then HAS_atmega88pa_TRUE= HAS_atmega88pa_FALSE='#' else HAS_atmega88pa_TRUE='#' HAS_atmega88pa_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega8hva" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega8hva" >&5 $as_echo_n "checking if ${CC} has support for atmega8hva... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega8hva=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega8hva" = "xyes"; then HAS_atmega8hva_TRUE= HAS_atmega8hva_FALSE='#' else HAS_atmega8hva_TRUE='#' HAS_atmega8hva_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90pwm1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm1" >&5 $as_echo_n "checking if ${CC} has support for at90pwm1... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90pwm1=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90pwm1" = "xyes"; then HAS_at90pwm1_TRUE= HAS_at90pwm1_FALSE='#' else HAS_at90pwm1_TRUE='#' HAS_at90pwm1_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90pwm2" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm2" >&5 $as_echo_n "checking if ${CC} has support for at90pwm2... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90pwm2=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90pwm2" = "xyes"; then HAS_at90pwm2_TRUE= HAS_at90pwm2_FALSE='#' else HAS_at90pwm2_TRUE='#' HAS_at90pwm2_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90pwm2b" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm2b" >&5 $as_echo_n "checking if ${CC} has support for at90pwm2b... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90pwm2b=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90pwm2b" = "xyes"; then HAS_at90pwm2b_TRUE= HAS_at90pwm2b_FALSE='#' else HAS_at90pwm2b_TRUE='#' HAS_at90pwm2b_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90pwm3" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm3" >&5 $as_echo_n "checking if ${CC} has support for at90pwm3... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90pwm3=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90pwm3" = "xyes"; then HAS_at90pwm3_TRUE= HAS_at90pwm3_FALSE='#' else HAS_at90pwm3_TRUE='#' HAS_at90pwm3_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90pwm3b" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm3b" >&5 $as_echo_n "checking if ${CC} has support for at90pwm3b... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90pwm3b=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90pwm3b" = "xyes"; then HAS_at90pwm3b_TRUE= HAS_at90pwm3b_FALSE='#' else HAS_at90pwm3b_TRUE='#' HAS_at90pwm3b_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90pwm81" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm81" >&5 $as_echo_n "checking if ${CC} has support for at90pwm81... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90pwm81=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90pwm81" = "xyes"; then HAS_at90pwm81_TRUE= HAS_at90pwm81_FALSE='#' else HAS_at90pwm81_TRUE='#' HAS_at90pwm81_FALSE= fi # avr5 if true; then HAS_avr5_TRUE= HAS_avr5_FALSE='#' else HAS_avr5_TRUE='#' HAS_avr5_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90can32" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90can32" >&5 $as_echo_n "checking if ${CC} has support for at90can32... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90can32=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90can32" = "xyes"; then HAS_at90can32_TRUE= HAS_at90can32_FALSE='#' else HAS_at90can32_TRUE='#' HAS_at90can32_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90can64" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90can64" >&5 $as_echo_n "checking if ${CC} has support for at90can64... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90can64=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90can64" = "xyes"; then HAS_at90can64_TRUE= HAS_at90can64_FALSE='#' else HAS_at90can64_TRUE='#' HAS_at90can64_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90scr100" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90scr100" >&5 $as_echo_n "checking if ${CC} has support for at90scr100... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90scr100=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90scr100" = "xyes"; then HAS_at90scr100_TRUE= HAS_at90scr100_FALSE='#' else HAS_at90scr100_TRUE='#' HAS_at90scr100_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90usb646" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb646" >&5 $as_echo_n "checking if ${CC} has support for at90usb646... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90usb646=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90usb646" = "xyes"; then HAS_at90usb646_TRUE= HAS_at90usb646_FALSE='#' else HAS_at90usb646_TRUE='#' HAS_at90usb646_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90usb647" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb647" >&5 $as_echo_n "checking if ${CC} has support for at90usb647... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90usb647=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90usb647" = "xyes"; then HAS_at90usb647_TRUE= HAS_at90usb647_FALSE='#' else HAS_at90usb647_TRUE='#' HAS_at90usb647_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90pwm316" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm316" >&5 $as_echo_n "checking if ${CC} has support for at90pwm316... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90pwm316=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90pwm316" = "xyes"; then HAS_at90pwm316_TRUE= HAS_at90pwm316_FALSE='#' else HAS_at90pwm316_TRUE='#' HAS_at90pwm316_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90pwm216" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm216" >&5 $as_echo_n "checking if ${CC} has support for at90pwm216... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90pwm216=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90pwm216" = "xyes"; then HAS_at90pwm216_TRUE= HAS_at90pwm216_FALSE='#' else HAS_at90pwm216_TRUE='#' HAS_at90pwm216_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at94k" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at94k" >&5 $as_echo_n "checking if ${CC} has support for at94k... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at94k=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at94k" = "xyes"; then HAS_at94k_TRUE= HAS_at94k_FALSE='#' else HAS_at94k_TRUE='#' HAS_at94k_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega16" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16" >&5 $as_echo_n "checking if ${CC} has support for atmega16... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega16=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega16" = "xyes"; then HAS_atmega16_TRUE= HAS_atmega16_FALSE='#' else HAS_atmega16_TRUE='#' HAS_atmega16_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega16a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16a" >&5 $as_echo_n "checking if ${CC} has support for atmega16a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega16a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega16a" = "xyes"; then HAS_atmega16a_TRUE= HAS_atmega16a_FALSE='#' else HAS_atmega16a_TRUE='#' HAS_atmega16a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega161" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega161" >&5 $as_echo_n "checking if ${CC} has support for atmega161... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega161=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega161" = "xyes"; then HAS_atmega161_TRUE= HAS_atmega161_FALSE='#' else HAS_atmega161_TRUE='#' HAS_atmega161_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega162" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega162" >&5 $as_echo_n "checking if ${CC} has support for atmega162... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega162=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega162" = "xyes"; then HAS_atmega162_TRUE= HAS_atmega162_FALSE='#' else HAS_atmega162_TRUE='#' HAS_atmega162_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega163" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega163" >&5 $as_echo_n "checking if ${CC} has support for atmega163... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega163=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega163" = "xyes"; then HAS_atmega163_TRUE= HAS_atmega163_FALSE='#' else HAS_atmega163_TRUE='#' HAS_atmega163_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega164a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega164a" >&5 $as_echo_n "checking if ${CC} has support for atmega164a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega164a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega164a" = "xyes"; then HAS_atmega164a_TRUE= HAS_atmega164a_FALSE='#' else HAS_atmega164a_TRUE='#' HAS_atmega164a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega164p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega164p" >&5 $as_echo_n "checking if ${CC} has support for atmega164p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega164p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega164p" = "xyes"; then HAS_atmega164p_TRUE= HAS_atmega164p_FALSE='#' else HAS_atmega164p_TRUE='#' HAS_atmega164p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega165" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165" >&5 $as_echo_n "checking if ${CC} has support for atmega165... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega165=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega165" = "xyes"; then HAS_atmega165_TRUE= HAS_atmega165_FALSE='#' else HAS_atmega165_TRUE='#' HAS_atmega165_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega165a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165a" >&5 $as_echo_n "checking if ${CC} has support for atmega165a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega165a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega165a" = "xyes"; then HAS_atmega165a_TRUE= HAS_atmega165a_FALSE='#' else HAS_atmega165a_TRUE='#' HAS_atmega165a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega165p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165p" >&5 $as_echo_n "checking if ${CC} has support for atmega165p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega165p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega165p" = "xyes"; then HAS_atmega165p_TRUE= HAS_atmega165p_FALSE='#' else HAS_atmega165p_TRUE='#' HAS_atmega165p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega168" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168" >&5 $as_echo_n "checking if ${CC} has support for atmega168... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega168=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega168" = "xyes"; then HAS_atmega168_TRUE= HAS_atmega168_FALSE='#' else HAS_atmega168_TRUE='#' HAS_atmega168_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega168a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168a" >&5 $as_echo_n "checking if ${CC} has support for atmega168a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega168a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega168a" = "xyes"; then HAS_atmega168a_TRUE= HAS_atmega168a_FALSE='#' else HAS_atmega168a_TRUE='#' HAS_atmega168a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega168p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168p" >&5 $as_echo_n "checking if ${CC} has support for atmega168p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega168p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega168p" = "xyes"; then HAS_atmega168p_TRUE= HAS_atmega168p_FALSE='#' else HAS_atmega168p_TRUE='#' HAS_atmega168p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega169" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169" >&5 $as_echo_n "checking if ${CC} has support for atmega169... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega169=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega169" = "xyes"; then HAS_atmega169_TRUE= HAS_atmega169_FALSE='#' else HAS_atmega169_TRUE='#' HAS_atmega169_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega169a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169a" >&5 $as_echo_n "checking if ${CC} has support for atmega169a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega169a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega169a" = "xyes"; then HAS_atmega169a_TRUE= HAS_atmega169a_FALSE='#' else HAS_atmega169a_TRUE='#' HAS_atmega169a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega169p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169p" >&5 $as_echo_n "checking if ${CC} has support for atmega169p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega169p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega169p" = "xyes"; then HAS_atmega169p_TRUE= HAS_atmega169p_FALSE='#' else HAS_atmega169p_TRUE='#' HAS_atmega169p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega169pa" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169pa" >&5 $as_echo_n "checking if ${CC} has support for atmega169pa... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega169pa=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega169pa" = "xyes"; then HAS_atmega169pa_TRUE= HAS_atmega169pa_FALSE='#' else HAS_atmega169pa_TRUE='#' HAS_atmega169pa_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega16hva" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hva" >&5 $as_echo_n "checking if ${CC} has support for atmega16hva... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega16hva=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega16hva" = "xyes"; then HAS_atmega16hva_TRUE= HAS_atmega16hva_FALSE='#' else HAS_atmega16hva_TRUE='#' HAS_atmega16hva_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega16hva2" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hva2" >&5 $as_echo_n "checking if ${CC} has support for atmega16hva2... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega16hva2=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega16hva2" = "xyes"; then HAS_atmega16hva2_TRUE= HAS_atmega16hva2_FALSE='#' else HAS_atmega16hva2_TRUE='#' HAS_atmega16hva2_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega16hvb" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hvb" >&5 $as_echo_n "checking if ${CC} has support for atmega16hvb... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega16hvb=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega16hvb" = "xyes"; then HAS_atmega16hvb_TRUE= HAS_atmega16hvb_FALSE='#' else HAS_atmega16hvb_TRUE='#' HAS_atmega16hvb_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega16hvbrevb" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hvbrevb" >&5 $as_echo_n "checking if ${CC} has support for atmega16hvbrevb... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega16hvbrevb=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega16hvbrevb" = "xyes"; then HAS_atmega16hvbrevb_TRUE= HAS_atmega16hvbrevb_FALSE='#' else HAS_atmega16hvbrevb_TRUE='#' HAS_atmega16hvbrevb_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega16m1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16m1" >&5 $as_echo_n "checking if ${CC} has support for atmega16m1... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega16m1=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega16m1" = "xyes"; then HAS_atmega16m1_TRUE= HAS_atmega16m1_FALSE='#' else HAS_atmega16m1_TRUE='#' HAS_atmega16m1_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega16u4" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16u4" >&5 $as_echo_n "checking if ${CC} has support for atmega16u4... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega16u4=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega16u4" = "xyes"; then HAS_atmega16u4_TRUE= HAS_atmega16u4_FALSE='#' else HAS_atmega16u4_TRUE='#' HAS_atmega16u4_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega32" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32" >&5 $as_echo_n "checking if ${CC} has support for atmega32... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega32=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega32" = "xyes"; then HAS_atmega32_TRUE= HAS_atmega32_FALSE='#' else HAS_atmega32_TRUE='#' HAS_atmega32_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega323" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega323" >&5 $as_echo_n "checking if ${CC} has support for atmega323... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega323=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega323" = "xyes"; then HAS_atmega323_TRUE= HAS_atmega323_FALSE='#' else HAS_atmega323_TRUE='#' HAS_atmega323_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega324a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega324a" >&5 $as_echo_n "checking if ${CC} has support for atmega324a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega324a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega324a" = "xyes"; then HAS_atmega324a_TRUE= HAS_atmega324a_FALSE='#' else HAS_atmega324a_TRUE='#' HAS_atmega324a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega324p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega324p" >&5 $as_echo_n "checking if ${CC} has support for atmega324p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega324p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega324p" = "xyes"; then HAS_atmega324p_TRUE= HAS_atmega324p_FALSE='#' else HAS_atmega324p_TRUE='#' HAS_atmega324p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega324pa" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega324pa" >&5 $as_echo_n "checking if ${CC} has support for atmega324pa... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega324pa=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega324pa" = "xyes"; then HAS_atmega324pa_TRUE= HAS_atmega324pa_FALSE='#' else HAS_atmega324pa_TRUE='#' HAS_atmega324pa_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega325" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325" >&5 $as_echo_n "checking if ${CC} has support for atmega325... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega325=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega325" = "xyes"; then HAS_atmega325_TRUE= HAS_atmega325_FALSE='#' else HAS_atmega325_TRUE='#' HAS_atmega325_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega325a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325a" >&5 $as_echo_n "checking if ${CC} has support for atmega325a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega325a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega325a" = "xyes"; then HAS_atmega325a_TRUE= HAS_atmega325a_FALSE='#' else HAS_atmega325a_TRUE='#' HAS_atmega325a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega325p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325p" >&5 $as_echo_n "checking if ${CC} has support for atmega325p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega325p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega325p" = "xyes"; then HAS_atmega325p_TRUE= HAS_atmega325p_FALSE='#' else HAS_atmega325p_TRUE='#' HAS_atmega325p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega3250" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250" >&5 $as_echo_n "checking if ${CC} has support for atmega3250... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega3250=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega3250" = "xyes"; then HAS_atmega3250_TRUE= HAS_atmega3250_FALSE='#' else HAS_atmega3250_TRUE='#' HAS_atmega3250_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega3250a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250a" >&5 $as_echo_n "checking if ${CC} has support for atmega3250a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega3250a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega3250a" = "xyes"; then HAS_atmega3250a_TRUE= HAS_atmega3250a_FALSE='#' else HAS_atmega3250a_TRUE='#' HAS_atmega3250a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega3250p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250p" >&5 $as_echo_n "checking if ${CC} has support for atmega3250p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega3250p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega3250p" = "xyes"; then HAS_atmega3250p_TRUE= HAS_atmega3250p_FALSE='#' else HAS_atmega3250p_TRUE='#' HAS_atmega3250p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega328" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega328" >&5 $as_echo_n "checking if ${CC} has support for atmega328... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega328=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega328" = "xyes"; then HAS_atmega328_TRUE= HAS_atmega328_FALSE='#' else HAS_atmega328_TRUE='#' HAS_atmega328_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega328p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega328p" >&5 $as_echo_n "checking if ${CC} has support for atmega328p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega328p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega328p" = "xyes"; then HAS_atmega328p_TRUE= HAS_atmega328p_FALSE='#' else HAS_atmega328p_TRUE='#' HAS_atmega328p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega329" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329" >&5 $as_echo_n "checking if ${CC} has support for atmega329... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega329=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega329" = "xyes"; then HAS_atmega329_TRUE= HAS_atmega329_FALSE='#' else HAS_atmega329_TRUE='#' HAS_atmega329_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega329a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329a" >&5 $as_echo_n "checking if ${CC} has support for atmega329a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega329a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega329a" = "xyes"; then HAS_atmega329a_TRUE= HAS_atmega329a_FALSE='#' else HAS_atmega329a_TRUE='#' HAS_atmega329a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega329p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329p" >&5 $as_echo_n "checking if ${CC} has support for atmega329p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega329p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega329p" = "xyes"; then HAS_atmega329p_TRUE= HAS_atmega329p_FALSE='#' else HAS_atmega329p_TRUE='#' HAS_atmega329p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega329pa" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329pa" >&5 $as_echo_n "checking if ${CC} has support for atmega329pa... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega329pa=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega329pa" = "xyes"; then HAS_atmega329pa_TRUE= HAS_atmega329pa_FALSE='#' else HAS_atmega329pa_TRUE='#' HAS_atmega329pa_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega3290" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290" >&5 $as_echo_n "checking if ${CC} has support for atmega3290... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega3290=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega3290" = "xyes"; then HAS_atmega3290_TRUE= HAS_atmega3290_FALSE='#' else HAS_atmega3290_TRUE='#' HAS_atmega3290_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega3290a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290a" >&5 $as_echo_n "checking if ${CC} has support for atmega3290a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega3290a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega3290a" = "xyes"; then HAS_atmega3290a_TRUE= HAS_atmega3290a_FALSE='#' else HAS_atmega3290a_TRUE='#' HAS_atmega3290a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega3290p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290p" >&5 $as_echo_n "checking if ${CC} has support for atmega3290p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega3290p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega3290p" = "xyes"; then HAS_atmega3290p_TRUE= HAS_atmega3290p_FALSE='#' else HAS_atmega3290p_TRUE='#' HAS_atmega3290p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega32c1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32c1" >&5 $as_echo_n "checking if ${CC} has support for atmega32c1... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega32c1=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega32c1" = "xyes"; then HAS_atmega32c1_TRUE= HAS_atmega32c1_FALSE='#' else HAS_atmega32c1_TRUE='#' HAS_atmega32c1_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega32hvb" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32hvb" >&5 $as_echo_n "checking if ${CC} has support for atmega32hvb... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega32hvb=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega32hvb" = "xyes"; then HAS_atmega32hvb_TRUE= HAS_atmega32hvb_FALSE='#' else HAS_atmega32hvb_TRUE='#' HAS_atmega32hvb_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega32hvbrevb" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32hvbrevb" >&5 $as_echo_n "checking if ${CC} has support for atmega32hvbrevb... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega32hvbrevb=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega32hvbrevb" = "xyes"; then HAS_atmega32hvbrevb_TRUE= HAS_atmega32hvbrevb_FALSE='#' else HAS_atmega32hvbrevb_TRUE='#' HAS_atmega32hvbrevb_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega32m1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32m1" >&5 $as_echo_n "checking if ${CC} has support for atmega32m1... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega32m1=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega32m1" = "xyes"; then HAS_atmega32m1_TRUE= HAS_atmega32m1_FALSE='#' else HAS_atmega32m1_TRUE='#' HAS_atmega32m1_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega32u4" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32u4" >&5 $as_echo_n "checking if ${CC} has support for atmega32u4... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega32u4=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega32u4" = "xyes"; then HAS_atmega32u4_TRUE= HAS_atmega32u4_FALSE='#' else HAS_atmega32u4_TRUE='#' HAS_atmega32u4_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega32u6" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32u6" >&5 $as_echo_n "checking if ${CC} has support for atmega32u6... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega32u6=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega32u6" = "xyes"; then HAS_atmega32u6_TRUE= HAS_atmega32u6_FALSE='#' else HAS_atmega32u6_TRUE='#' HAS_atmega32u6_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega406" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega406" >&5 $as_echo_n "checking if ${CC} has support for atmega406... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega406=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega406" = "xyes"; then HAS_atmega406_TRUE= HAS_atmega406_FALSE='#' else HAS_atmega406_TRUE='#' HAS_atmega406_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega64" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64" >&5 $as_echo_n "checking if ${CC} has support for atmega64... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega64=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega64" = "xyes"; then HAS_atmega64_TRUE= HAS_atmega64_FALSE='#' else HAS_atmega64_TRUE='#' HAS_atmega64_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega640" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega640" >&5 $as_echo_n "checking if ${CC} has support for atmega640... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega640=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega640" = "xyes"; then HAS_atmega640_TRUE= HAS_atmega640_FALSE='#' else HAS_atmega640_TRUE='#' HAS_atmega640_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega644" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644" >&5 $as_echo_n "checking if ${CC} has support for atmega644... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega644=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega644" = "xyes"; then HAS_atmega644_TRUE= HAS_atmega644_FALSE='#' else HAS_atmega644_TRUE='#' HAS_atmega644_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega644a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644a" >&5 $as_echo_n "checking if ${CC} has support for atmega644a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega644a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega644a" = "xyes"; then HAS_atmega644a_TRUE= HAS_atmega644a_FALSE='#' else HAS_atmega644a_TRUE='#' HAS_atmega644a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega644p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644p" >&5 $as_echo_n "checking if ${CC} has support for atmega644p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega644p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega644p" = "xyes"; then HAS_atmega644p_TRUE= HAS_atmega644p_FALSE='#' else HAS_atmega644p_TRUE='#' HAS_atmega644p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega644pa" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644pa" >&5 $as_echo_n "checking if ${CC} has support for atmega644pa... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega644pa=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega644pa" = "xyes"; then HAS_atmega644pa_TRUE= HAS_atmega644pa_FALSE='#' else HAS_atmega644pa_TRUE='#' HAS_atmega644pa_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega645" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega645" >&5 $as_echo_n "checking if ${CC} has support for atmega645... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega645=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega645" = "xyes"; then HAS_atmega645_TRUE= HAS_atmega645_FALSE='#' else HAS_atmega645_TRUE='#' HAS_atmega645_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega645a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega645a" >&5 $as_echo_n "checking if ${CC} has support for atmega645a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega645a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega645a" = "xyes"; then HAS_atmega645a_TRUE= HAS_atmega645a_FALSE='#' else HAS_atmega645a_TRUE='#' HAS_atmega645a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega645p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega645p" >&5 $as_echo_n "checking if ${CC} has support for atmega645p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega645p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega645p" = "xyes"; then HAS_atmega645p_TRUE= HAS_atmega645p_FALSE='#' else HAS_atmega645p_TRUE='#' HAS_atmega645p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega6450" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6450" >&5 $as_echo_n "checking if ${CC} has support for atmega6450... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega6450=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega6450" = "xyes"; then HAS_atmega6450_TRUE= HAS_atmega6450_FALSE='#' else HAS_atmega6450_TRUE='#' HAS_atmega6450_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega6450a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6450a" >&5 $as_echo_n "checking if ${CC} has support for atmega6450a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega6450a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega6450a" = "xyes"; then HAS_atmega6450a_TRUE= HAS_atmega6450a_FALSE='#' else HAS_atmega6450a_TRUE='#' HAS_atmega6450a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega6450p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6450p" >&5 $as_echo_n "checking if ${CC} has support for atmega6450p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega6450p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega6450p" = "xyes"; then HAS_atmega6450p_TRUE= HAS_atmega6450p_FALSE='#' else HAS_atmega6450p_TRUE='#' HAS_atmega6450p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega649" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega649" >&5 $as_echo_n "checking if ${CC} has support for atmega649... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega649=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega649" = "xyes"; then HAS_atmega649_TRUE= HAS_atmega649_FALSE='#' else HAS_atmega649_TRUE='#' HAS_atmega649_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega649a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega649a" >&5 $as_echo_n "checking if ${CC} has support for atmega649a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega649a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega649a" = "xyes"; then HAS_atmega649a_TRUE= HAS_atmega649a_FALSE='#' else HAS_atmega649a_TRUE='#' HAS_atmega649a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega649p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega649p" >&5 $as_echo_n "checking if ${CC} has support for atmega649p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega649p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega649p" = "xyes"; then HAS_atmega649p_TRUE= HAS_atmega649p_FALSE='#' else HAS_atmega649p_TRUE='#' HAS_atmega649p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega6490" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6490" >&5 $as_echo_n "checking if ${CC} has support for atmega6490... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega6490=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega6490" = "xyes"; then HAS_atmega6490_TRUE= HAS_atmega6490_FALSE='#' else HAS_atmega6490_TRUE='#' HAS_atmega6490_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega6490a" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6490a" >&5 $as_echo_n "checking if ${CC} has support for atmega6490a... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega6490a=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega6490a" = "xyes"; then HAS_atmega6490a_TRUE= HAS_atmega6490a_FALSE='#' else HAS_atmega6490a_TRUE='#' HAS_atmega6490a_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega6490p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6490p" >&5 $as_echo_n "checking if ${CC} has support for atmega6490p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega6490p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega6490p" = "xyes"; then HAS_atmega6490p_TRUE= HAS_atmega6490p_FALSE='#' else HAS_atmega6490p_TRUE='#' HAS_atmega6490p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega64c1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64c1" >&5 $as_echo_n "checking if ${CC} has support for atmega64c1... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega64c1=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega64c1" = "xyes"; then HAS_atmega64c1_TRUE= HAS_atmega64c1_FALSE='#' else HAS_atmega64c1_TRUE='#' HAS_atmega64c1_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega64hve" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64hve" >&5 $as_echo_n "checking if ${CC} has support for atmega64hve... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega64hve=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega64hve" = "xyes"; then HAS_atmega64hve_TRUE= HAS_atmega64hve_FALSE='#' else HAS_atmega64hve_TRUE='#' HAS_atmega64hve_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega64m1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64m1" >&5 $as_echo_n "checking if ${CC} has support for atmega64m1... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega64m1=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega64m1" = "xyes"; then HAS_atmega64m1_TRUE= HAS_atmega64m1_FALSE='#' else HAS_atmega64m1_TRUE='#' HAS_atmega64m1_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega128rfa1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega128rfa1" >&5 $as_echo_n "checking if ${CC} has support for atmega128rfa1... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega128rfa1=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega128rfa1" = "xyes"; then HAS_atmega128rfa1_TRUE= HAS_atmega128rfa1_FALSE='#' else HAS_atmega128rfa1_TRUE='#' HAS_atmega128rfa1_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=m3000" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for m3000" >&5 $as_echo_n "checking if ${CC} has support for m3000... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_m3000=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_m3000" = "xyes"; then HAS_m3000_TRUE= HAS_m3000_FALSE='#' else HAS_m3000_TRUE='#' HAS_m3000_FALSE= fi #avr51 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avr51" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr51" >&5 $as_echo_n "checking if ${CC} has support for avr51... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avr51=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avr51" = "xyes"; then HAS_avr51_TRUE= HAS_avr51_FALSE='#' else HAS_avr51_TRUE='#' HAS_avr51_FALSE= fi if true; then HAS_atmega128_TRUE= HAS_atmega128_FALSE='#' else HAS_atmega128_TRUE='#' HAS_atmega128_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega1280" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1280" >&5 $as_echo_n "checking if ${CC} has support for atmega1280... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega1280=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega1280" = "xyes"; then HAS_atmega1280_TRUE= HAS_atmega1280_FALSE='#' else HAS_atmega1280_TRUE='#' HAS_atmega1280_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega1281" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1281" >&5 $as_echo_n "checking if ${CC} has support for atmega1281... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega1281=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega1281" = "xyes"; then HAS_atmega1281_TRUE= HAS_atmega1281_FALSE='#' else HAS_atmega1281_TRUE='#' HAS_atmega1281_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega1284p" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1284p" >&5 $as_echo_n "checking if ${CC} has support for atmega1284p... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega1284p=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega1284p" = "xyes"; then HAS_atmega1284p_TRUE= HAS_atmega1284p_FALSE='#' else HAS_atmega1284p_TRUE='#' HAS_atmega1284p_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90can128" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90can128" >&5 $as_echo_n "checking if ${CC} has support for at90can128... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90can128=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90can128" = "xyes"; then HAS_at90can128_TRUE= HAS_at90can128_FALSE='#' else HAS_at90can128_TRUE='#' HAS_at90can128_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90usb1286" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb1286" >&5 $as_echo_n "checking if ${CC} has support for at90usb1286... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90usb1286=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90usb1286" = "xyes"; then HAS_at90usb1286_TRUE= HAS_at90usb1286_FALSE='#' else HAS_at90usb1286_TRUE='#' HAS_at90usb1286_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=at90usb1287" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb1287" >&5 $as_echo_n "checking if ${CC} has support for at90usb1287... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_at90usb1287=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_at90usb1287" = "xyes"; then HAS_at90usb1287_TRUE= HAS_at90usb1287_FALSE='#' else HAS_at90usb1287_TRUE='#' HAS_at90usb1287_FALSE= fi # avr6 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avr6" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr6" >&5 $as_echo_n "checking if ${CC} has support for avr6... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avr6=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avr6" = "xyes"; then HAS_avr6_TRUE= HAS_avr6_FALSE='#' else HAS_avr6_TRUE='#' HAS_avr6_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega2560" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega2560" >&5 $as_echo_n "checking if ${CC} has support for atmega2560... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega2560=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega2560" = "xyes"; then HAS_atmega2560_TRUE= HAS_atmega2560_FALSE='#' else HAS_atmega2560_TRUE='#' HAS_atmega2560_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atmega2561" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega2561" >&5 $as_echo_n "checking if ${CC} has support for atmega2561... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atmega2561=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atmega2561" = "xyes"; then HAS_atmega2561_TRUE= HAS_atmega2561_FALSE='#' else HAS_atmega2561_TRUE='#' HAS_atmega2561_FALSE= fi # avrxmega2 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avrxmega2" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega2" >&5 $as_echo_n "checking if ${CC} has support for avrxmega2... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avrxmega2=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avrxmega2" = "xyes"; then HAS_avrxmega2_TRUE= HAS_avrxmega2_FALSE='#' else HAS_avrxmega2_TRUE='#' HAS_avrxmega2_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega16a4" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16a4" >&5 $as_echo_n "checking if ${CC} has support for atxmega16a4... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega16a4=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega16a4" = "xyes"; then HAS_atxmega16a4_TRUE= HAS_atxmega16a4_FALSE='#' else HAS_atxmega16a4_TRUE='#' HAS_atxmega16a4_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega16d4" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16d4" >&5 $as_echo_n "checking if ${CC} has support for atxmega16d4... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega16d4=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega16d4" = "xyes"; then HAS_atxmega16d4_TRUE= HAS_atxmega16d4_FALSE='#' else HAS_atxmega16d4_TRUE='#' HAS_atxmega16d4_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega32a4" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32a4" >&5 $as_echo_n "checking if ${CC} has support for atxmega32a4... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega32a4=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega32a4" = "xyes"; then HAS_atxmega32a4_TRUE= HAS_atxmega32a4_FALSE='#' else HAS_atxmega32a4_TRUE='#' HAS_atxmega32a4_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega32d4" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32d4" >&5 $as_echo_n "checking if ${CC} has support for atxmega32d4... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega32d4=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega32d4" = "xyes"; then HAS_atxmega32d4_TRUE= HAS_atxmega32d4_FALSE='#' else HAS_atxmega32d4_TRUE='#' HAS_atxmega32d4_FALSE= fi # avrxmega4 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avrxmega4" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega4" >&5 $as_echo_n "checking if ${CC} has support for avrxmega4... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avrxmega4=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avrxmega4" = "xyes"; then HAS_avrxmega4_TRUE= HAS_avrxmega4_FALSE='#' else HAS_avrxmega4_TRUE='#' HAS_avrxmega4_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega64a3" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a3" >&5 $as_echo_n "checking if ${CC} has support for atxmega64a3... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega64a3=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega64a3" = "xyes"; then HAS_atxmega64a3_TRUE= HAS_atxmega64a3_FALSE='#' else HAS_atxmega64a3_TRUE='#' HAS_atxmega64a3_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega64d3" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64d3" >&5 $as_echo_n "checking if ${CC} has support for atxmega64d3... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega64d3=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega64d3" = "xyes"; then HAS_atxmega64d3_TRUE= HAS_atxmega64d3_FALSE='#' else HAS_atxmega64d3_TRUE='#' HAS_atxmega64d3_FALSE= fi # avrxmega5 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avrxmega5" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega5" >&5 $as_echo_n "checking if ${CC} has support for avrxmega5... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avrxmega5=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avrxmega5" = "xyes"; then HAS_avrxmega5_TRUE= HAS_avrxmega5_FALSE='#' else HAS_avrxmega5_TRUE='#' HAS_avrxmega5_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega64a1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a1" >&5 $as_echo_n "checking if ${CC} has support for atxmega64a1... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega64a1=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega64a1" = "xyes"; then HAS_atxmega64a1_TRUE= HAS_atxmega64a1_FALSE='#' else HAS_atxmega64a1_TRUE='#' HAS_atxmega64a1_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega64a1u" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a1u" >&5 $as_echo_n "checking if ${CC} has support for atxmega64a1u... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega64a1u=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega64a1u" = "xyes"; then HAS_atxmega64a1u_TRUE= HAS_atxmega64a1u_FALSE='#' else HAS_atxmega64a1u_TRUE='#' HAS_atxmega64a1u_FALSE= fi # avrxmega6 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avrxmega6" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega6" >&5 $as_echo_n "checking if ${CC} has support for avrxmega6... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avrxmega6=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avrxmega6" = "xyes"; then HAS_avrxmega6_TRUE= HAS_avrxmega6_FALSE='#' else HAS_avrxmega6_TRUE='#' HAS_avrxmega6_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega128a3" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a3" >&5 $as_echo_n "checking if ${CC} has support for atxmega128a3... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega128a3=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega128a3" = "xyes"; then HAS_atxmega128a3_TRUE= HAS_atxmega128a3_FALSE='#' else HAS_atxmega128a3_TRUE='#' HAS_atxmega128a3_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega128d3" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128d3" >&5 $as_echo_n "checking if ${CC} has support for atxmega128d3... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega128d3=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega128d3" = "xyes"; then HAS_atxmega128d3_TRUE= HAS_atxmega128d3_FALSE='#' else HAS_atxmega128d3_TRUE='#' HAS_atxmega128d3_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega192a3" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192a3" >&5 $as_echo_n "checking if ${CC} has support for atxmega192a3... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega192a3=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega192a3" = "xyes"; then HAS_atxmega192a3_TRUE= HAS_atxmega192a3_FALSE='#' else HAS_atxmega192a3_TRUE='#' HAS_atxmega192a3_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega192d3" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192d3" >&5 $as_echo_n "checking if ${CC} has support for atxmega192d3... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega192d3=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega192d3" = "xyes"; then HAS_atxmega192d3_TRUE= HAS_atxmega192d3_FALSE='#' else HAS_atxmega192d3_TRUE='#' HAS_atxmega192d3_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega256a3" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3" >&5 $as_echo_n "checking if ${CC} has support for atxmega256a3... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega256a3=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega256a3" = "xyes"; then HAS_atxmega256a3_TRUE= HAS_atxmega256a3_FALSE='#' else HAS_atxmega256a3_TRUE='#' HAS_atxmega256a3_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega256a3b" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3b" >&5 $as_echo_n "checking if ${CC} has support for atxmega256a3b... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega256a3b=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega256a3b" = "xyes"; then HAS_atxmega256a3b_TRUE= HAS_atxmega256a3b_FALSE='#' else HAS_atxmega256a3b_TRUE='#' HAS_atxmega256a3b_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega256d3" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256d3" >&5 $as_echo_n "checking if ${CC} has support for atxmega256d3... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega256d3=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega256d3" = "xyes"; then HAS_atxmega256d3_TRUE= HAS_atxmega256d3_FALSE='#' else HAS_atxmega256d3_TRUE='#' HAS_atxmega256d3_FALSE= fi # avrxmega7 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avrxmega7" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega7" >&5 $as_echo_n "checking if ${CC} has support for avrxmega7... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avrxmega7=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avrxmega7" = "xyes"; then HAS_avrxmega7_TRUE= HAS_avrxmega7_FALSE='#' else HAS_avrxmega7_TRUE='#' HAS_avrxmega7_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega128a1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a1" >&5 $as_echo_n "checking if ${CC} has support for atxmega128a1... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega128a1=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega128a1" = "xyes"; then HAS_atxmega128a1_TRUE= HAS_atxmega128a1_FALSE='#' else HAS_atxmega128a1_TRUE='#' HAS_atxmega128a1_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=atxmega128a1u" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a1u" >&5 $as_echo_n "checking if ${CC} has support for atxmega128a1u... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_atxmega128a1u=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_atxmega128a1u" = "xyes"; then HAS_atxmega128a1u_TRUE= HAS_atxmega128a1u_FALSE='#' else HAS_atxmega128a1u_TRUE='#' HAS_atxmega128a1u_FALSE= fi # avrtiny10 old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=avrtiny10" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrtiny10" >&5 $as_echo_n "checking if ${CC} has support for avrtiny10... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_avrtiny10=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_avrtiny10" = "xyes"; then HAS_avrtiny10_TRUE= HAS_avrtiny10_FALSE='#' else HAS_avrtiny10_TRUE='#' HAS_avrtiny10_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny4" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny4" >&5 $as_echo_n "checking if ${CC} has support for attiny4... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny4=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny4" = "xyes"; then HAS_attiny4_TRUE= HAS_attiny4_FALSE='#' else HAS_attiny4_TRUE='#' HAS_attiny4_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny5" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny5" >&5 $as_echo_n "checking if ${CC} has support for attiny5... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny5=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny5" = "xyes"; then HAS_attiny5_TRUE= HAS_attiny5_FALSE='#' else HAS_attiny5_TRUE='#' HAS_attiny5_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny9" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny9" >&5 $as_echo_n "checking if ${CC} has support for attiny9... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny9=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny9" = "xyes"; then HAS_attiny9_TRUE= HAS_attiny9_FALSE='#' else HAS_attiny9_TRUE='#' HAS_attiny9_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny10" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny10" >&5 $as_echo_n "checking if ${CC} has support for attiny10... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny10=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny10" = "xyes"; then HAS_attiny10_TRUE= HAS_attiny10_FALSE='#' else HAS_attiny10_TRUE='#' HAS_attiny10_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny20" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny20" >&5 $as_echo_n "checking if ${CC} has support for attiny20... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny20=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny20" = "xyes"; then HAS_attiny20_TRUE= HAS_attiny20_FALSE='#' else HAS_attiny20_TRUE='#' HAS_attiny20_FALSE= fi old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=attiny40" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny40" >&5 $as_echo_n "checking if ${CC} has support for attiny40... " >&6; } cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ _ACEOF if ac_fn_c_try_compile "$LINENO"; then : has_dev_support=yes else has_dev_support=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test "x$has_dev_support" = "xyes" then HAS_attiny40=yes fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 $as_echo "$has_dev_support" >&6; } CC=${old_CC} CFLAGS=${old_CFLAGS} if test "x$HAS_attiny40" = "xyes"; then HAS_attiny40_TRUE= HAS_attiny40_FALSE='#' else HAS_attiny40_TRUE='#' HAS_attiny40_FALSE= fi # Generate all files from *.in sources. ac_config_files="$ac_config_files Makefile avr-libc.spec avr/Makefile avr/lib/Makefile common/Makefile crt1/Makefile doc/Makefile doc/api/Makefile doc/examples/Makefile include/Makefile include/avr/Makefile include/avr/builtins.h include/compat/Makefile include/util/Makefile include/util/delay.h libc/Makefile libc/misc/Makefile libc/pmstring/Makefile libc/stdio/Makefile libc/stdlib/Makefile libc/string/Makefile libm/Makefile libm/fplib/Makefile scripts/Makefile devtools/Makefile" #avr1 and avr2 ac_config_files="$ac_config_files avr/lib/avr2/Makefile avr/lib/avr2/at90s1200/Makefile avr/lib/avr2/at90s2313/Makefile avr/lib/avr2/at90s2323/Makefile avr/lib/avr2/at90s2333/Makefile avr/lib/avr2/at90s2343/Makefile avr/lib/avr2/at90s4414/Makefile avr/lib/avr2/at90s4433/Makefile avr/lib/avr2/at90s4434/Makefile avr/lib/avr2/at90s8515/Makefile avr/lib/avr2/at90c8534/Makefile avr/lib/avr2/at90s8535/Makefile avr/lib/avr2/attiny11/Makefile avr/lib/avr2/attiny12/Makefile avr/lib/avr2/attiny13/Makefile avr/lib/avr2/attiny15/Makefile avr/lib/avr2/attiny22/Makefile avr/lib/avr2/attiny24/Makefile avr/lib/avr2/attiny25/Makefile avr/lib/avr2/attiny26/Makefile avr/lib/avr2/attiny261/Makefile avr/lib/avr2/attiny28/Makefile avr/lib/avr2/attiny44/Makefile avr/lib/avr2/attiny45/Makefile avr/lib/avr2/attiny461/Makefile avr/lib/avr2/attiny84/Makefile avr/lib/avr2/attiny85/Makefile avr/lib/avr2/attiny861/Makefile avr/lib/avr2/attiny2313/Makefile avr/lib/avr2/at86rf401/Makefile" #avr25 ac_config_files="$ac_config_files avr/lib/avr25/Makefile avr/lib/avr25/at86rf401/Makefile avr/lib/avr25/ata6289/Makefile avr/lib/avr25/attiny13/Makefile avr/lib/avr25/attiny13a/Makefile avr/lib/avr25/attiny2313/Makefile avr/lib/avr25/attiny2313a/Makefile avr/lib/avr25/attiny24/Makefile avr/lib/avr25/attiny24a/Makefile avr/lib/avr25/attiny25/Makefile avr/lib/avr25/attiny261/Makefile avr/lib/avr25/attiny261a/Makefile avr/lib/avr25/attiny4313/Makefile avr/lib/avr25/attiny43u/Makefile avr/lib/avr25/attiny44/Makefile avr/lib/avr25/attiny44a/Makefile avr/lib/avr25/attiny45/Makefile avr/lib/avr25/attiny461/Makefile avr/lib/avr25/attiny461a/Makefile avr/lib/avr25/attiny48/Makefile avr/lib/avr25/attiny84/Makefile avr/lib/avr25/attiny84a/Makefile avr/lib/avr25/attiny85/Makefile avr/lib/avr25/attiny861/Makefile avr/lib/avr25/attiny861a/Makefile avr/lib/avr25/attiny87/Makefile avr/lib/avr25/attiny88/Makefile" #avr3 ac_config_files="$ac_config_files avr/lib/avr3/Makefile avr/lib/avr3/atmega103/Makefile avr/lib/avr3/at43usb320/Makefile avr/lib/avr3/at43usb355/Makefile avr/lib/avr3/at76c711/Makefile avr/lib/avr3/at90usb82/Makefile avr/lib/avr3/at90usb162/Makefile" #avr31 ac_config_files="$ac_config_files avr/lib/avr31/Makefile avr/lib/avr31/atmega103/Makefile avr/lib/avr31/at43usb320/Makefile" #avr35 ac_config_files="$ac_config_files avr/lib/avr35/Makefile avr/lib/avr35/at90usb82/Makefile avr/lib/avr35/at90usb162/Makefile avr/lib/avr35/atmega8u2/Makefile avr/lib/avr35/atmega16u2/Makefile avr/lib/avr35/atmega32u2/Makefile avr/lib/avr35/attiny167/Makefile" #avr4 ac_config_files="$ac_config_files avr/lib/avr4/Makefile avr/lib/avr4/atmega48/Makefile avr/lib/avr4/atmega48a/Makefile avr/lib/avr4/atmega48p/Makefile avr/lib/avr4/atmega8/Makefile avr/lib/avr4/atmega88/Makefile avr/lib/avr4/atmega88a/Makefile avr/lib/avr4/atmega88p/Makefile avr/lib/avr4/atmega88pa/Makefile avr/lib/avr4/atmega8515/Makefile avr/lib/avr4/atmega8535/Makefile avr/lib/avr4/atmega8hva/Makefile avr/lib/avr4/at90pwm1/Makefile avr/lib/avr4/at90pwm2/Makefile avr/lib/avr4/at90pwm2b/Makefile avr/lib/avr4/at90pwm3/Makefile avr/lib/avr4/at90pwm3b/Makefile avr/lib/avr4/at90pwm81/Makefile" #avr5 ac_config_files="$ac_config_files avr/lib/avr5/Makefile avr/lib/avr5/at90can32/Makefile avr/lib/avr5/at90can64/Makefile avr/lib/avr5/at90can128/Makefile avr/lib/avr5/at90pwm216/Makefile avr/lib/avr5/at90pwm316/Makefile avr/lib/avr5/at90scr100/Makefile avr/lib/avr5/at90usb646/Makefile avr/lib/avr5/at90usb647/Makefile avr/lib/avr5/at90usb1286/Makefile avr/lib/avr5/at90usb1287/Makefile avr/lib/avr5/at94k/Makefile avr/lib/avr5/atmega16/Makefile avr/lib/avr5/atmega16a/Makefile avr/lib/avr5/atmega161/Makefile avr/lib/avr5/atmega162/Makefile avr/lib/avr5/atmega163/Makefile avr/lib/avr5/atmega164a/Makefile avr/lib/avr5/atmega164p/Makefile avr/lib/avr5/atmega165/Makefile avr/lib/avr5/atmega165a/Makefile avr/lib/avr5/atmega165p/Makefile avr/lib/avr5/atmega168/Makefile avr/lib/avr5/atmega168a/Makefile avr/lib/avr5/atmega168p/Makefile avr/lib/avr5/atmega169/Makefile avr/lib/avr5/atmega169a/Makefile avr/lib/avr5/atmega169p/Makefile avr/lib/avr5/atmega169pa/Makefile avr/lib/avr5/atmega16hva/Makefile avr/lib/avr5/atmega16hva2/Makefile avr/lib/avr5/atmega16hvb/Makefile avr/lib/avr5/atmega16hvbrevb/Makefile avr/lib/avr5/atmega16m1/Makefile avr/lib/avr5/atmega16u4/Makefile avr/lib/avr5/atmega32/Makefile avr/lib/avr5/atmega323/Makefile avr/lib/avr5/atmega324a/Makefile avr/lib/avr5/atmega324p/Makefile avr/lib/avr5/atmega324pa/Makefile avr/lib/avr5/atmega325/Makefile avr/lib/avr5/atmega325a/Makefile avr/lib/avr5/atmega325p/Makefile avr/lib/avr5/atmega3250/Makefile avr/lib/avr5/atmega3250a/Makefile avr/lib/avr5/atmega3250p/Makefile avr/lib/avr5/atmega328/Makefile avr/lib/avr5/atmega328p/Makefile avr/lib/avr5/atmega329/Makefile avr/lib/avr5/atmega329a/Makefile avr/lib/avr5/atmega329p/Makefile avr/lib/avr5/atmega329pa/Makefile avr/lib/avr5/atmega3290/Makefile avr/lib/avr5/atmega3290a/Makefile avr/lib/avr5/atmega3290p/Makefile avr/lib/avr5/atmega32c1/Makefile avr/lib/avr5/atmega32hvb/Makefile avr/lib/avr5/atmega32hvbrevb/Makefile avr/lib/avr5/atmega32m1/Makefile avr/lib/avr5/atmega32u4/Makefile avr/lib/avr5/atmega32u6/Makefile avr/lib/avr5/atmega406/Makefile avr/lib/avr5/atmega64/Makefile avr/lib/avr5/atmega640/Makefile avr/lib/avr5/atmega644/Makefile avr/lib/avr5/atmega644a/Makefile avr/lib/avr5/atmega644p/Makefile avr/lib/avr5/atmega644pa/Makefile avr/lib/avr5/atmega645/Makefile avr/lib/avr5/atmega645a/Makefile avr/lib/avr5/atmega645p/Makefile avr/lib/avr5/atmega6450/Makefile avr/lib/avr5/atmega6450a/Makefile avr/lib/avr5/atmega6450p/Makefile avr/lib/avr5/atmega649/Makefile avr/lib/avr5/atmega649a/Makefile avr/lib/avr5/atmega649p/Makefile avr/lib/avr5/atmega6490/Makefile avr/lib/avr5/atmega6490a/Makefile avr/lib/avr5/atmega6490p/Makefile avr/lib/avr5/atmega64c1/Makefile avr/lib/avr5/atmega64hve/Makefile avr/lib/avr5/atmega64m1/Makefile avr/lib/avr5/atmega128/Makefile avr/lib/avr5/atmega1280/Makefile avr/lib/avr5/atmega1281/Makefile avr/lib/avr5/atmega1284p/Makefile avr/lib/avr5/atmega128rfa1/Makefile avr/lib/avr5/m3000/Makefile" #avr51 ac_config_files="$ac_config_files avr/lib/avr51/Makefile avr/lib/avr51/atmega128/Makefile avr/lib/avr51/atmega1280/Makefile avr/lib/avr51/atmega1281/Makefile avr/lib/avr51/atmega1284p/Makefile avr/lib/avr51/atmega128rfa1/Makefile avr/lib/avr51/at90can128/Makefile avr/lib/avr51/at90usb1286/Makefile avr/lib/avr51/at90usb1287/Makefile" #avr6 ac_config_files="$ac_config_files avr/lib/avr6/Makefile avr/lib/avr6/atmega2560/Makefile avr/lib/avr6/atmega2561/Makefile" # avrxmega2 ac_config_files="$ac_config_files avr/lib/avrxmega2/Makefile avr/lib/avrxmega2/atxmega16a4/Makefile avr/lib/avrxmega2/atxmega16d4/Makefile avr/lib/avrxmega2/atxmega32a4/Makefile avr/lib/avrxmega2/atxmega32d4/Makefile" # avrxmega4 ac_config_files="$ac_config_files avr/lib/avrxmega4/Makefile avr/lib/avrxmega4/atxmega64a3/Makefile avr/lib/avrxmega4/atxmega64d3/Makefile" # avrxmega5 ac_config_files="$ac_config_files avr/lib/avrxmega5/Makefile avr/lib/avrxmega5/atxmega64a1/Makefile avr/lib/avrxmega5/atxmega64a1u/Makefile" # avrxmega6 ac_config_files="$ac_config_files avr/lib/avrxmega6/Makefile avr/lib/avrxmega6/atxmega128a3/Makefile avr/lib/avrxmega6/atxmega128d3/Makefile avr/lib/avrxmega6/atxmega192a3/Makefile avr/lib/avrxmega6/atxmega192d3/Makefile avr/lib/avrxmega6/atxmega256a3/Makefile avr/lib/avrxmega6/atxmega256a3b/Makefile avr/lib/avrxmega6/atxmega256d3/Makefile" # avrxmega7 ac_config_files="$ac_config_files avr/lib/avrxmega7/Makefile avr/lib/avrxmega7/atxmega128a1/Makefile avr/lib/avrxmega7/atxmega128a1u/Makefile" # avrtiny10 ac_config_files="$ac_config_files avr/lib/avrtiny10/Makefile avr/lib/avrtiny10/attiny4/Makefile avr/lib/avrtiny10/attiny5/Makefile avr/lib/avrtiny10/attiny9/Makefile avr/lib/avrtiny10/attiny10/Makefile avr/lib/avrtiny10/attiny20/Makefile avr/lib/avrtiny10/attiny40/Makefile" cat >confcache <<\_ACEOF # This file is a shell script that caches the results of configure # tests run on this system so they can be shared between configure # scripts and configure runs, see configure's option --config-cache. # It is not useful on other systems. If it contains results you don't # want to keep, you may remove or edit it. # # config.status only pays attention to the cache file if you give it # the --recheck option to rerun configure. # # `ac_cv_env_foo' variables (set or unset) will be overridden when # loading this file, other *unset* `ac_cv_foo' will be assigned the # following values. _ACEOF # The following way of writing the cache mishandles newlines in values, # but we know of no workaround that is simple, portable, and efficient. # So, we kill variables containing newlines. # Ultrix sh set writes to stderr and can't be redirected directly, # and sets the high bit in the cache file unless we assign to the vars. ( for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do eval ac_val=\$$ac_var case $ac_val in #( *${as_nl}*) case $ac_var in #( *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 $as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; esac case $ac_var in #( _ | IFS | as_nl) ;; #( BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( *) { eval $ac_var=; unset $ac_var;} ;; esac ;; esac done (set) 2>&1 | case $as_nl`(ac_space=' '; set) 2>&1` in #( *${as_nl}ac_space=\ *) # `set' does not quote correctly, so add quotes: double-quote # substitution turns \\\\ into \\, and sed turns \\ into \. sed -n \ "s/'/'\\\\''/g; s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" ;; #( *) # `set' quotes correctly as required by POSIX, so do not add quotes. sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" ;; esac | sort ) | sed ' /^ac_cv_env_/b end t clear :clear s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ t end s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ :end' >>confcache if diff "$cache_file" confcache >/dev/null 2>&1; then :; else if test -w "$cache_file"; then if test "x$cache_file" != "x/dev/null"; then { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 $as_echo "$as_me: updating cache $cache_file" >&6;} if test ! -f "$cache_file" || test -h "$cache_file"; then cat confcache >"$cache_file" else case $cache_file in #( */* | ?:*) mv -f confcache "$cache_file"$$ && mv -f "$cache_file"$$ "$cache_file" ;; #( *) mv -f confcache "$cache_file" ;; esac fi fi else { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 $as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} fi fi rm -f confcache test "x$prefix" = xNONE && prefix=$ac_default_prefix # Let make expand exec_prefix. test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' DEFS=-DHAVE_CONFIG_H ac_libobjs= ac_ltlibobjs= U= for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue # 1. Remove the extension, and $U if already installed. ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' ac_i=`$as_echo "$ac_i" | sed "$ac_script"` # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR # will be set to the directory where LIBOBJS objects are built. as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' done LIBOBJS=$ac_libobjs LTLIBOBJS=$ac_ltlibobjs if test -n "$EXEEXT"; then am__EXEEXT_TRUE= am__EXEEXT_FALSE='#' else am__EXEEXT_TRUE='#' am__EXEEXT_FALSE= fi if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then as_fn_error $? "conditional \"AMDEP\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then as_fn_error $? "conditional \"am__fastdepCC\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${am__fastdepCCAS_TRUE}" && test -z "${am__fastdepCCAS_FALSE}"; then as_fn_error $? "conditional \"am__fastdepCCAS\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr1_TRUE}" && test -z "${HAS_avr1_FALSE}"; then as_fn_error $? "conditional \"HAS_avr1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s1200_TRUE}" && test -z "${HAS_at90s1200_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s1200\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny11_TRUE}" && test -z "${HAS_attiny11_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny11\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny12_TRUE}" && test -z "${HAS_attiny12_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny12\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny15_TRUE}" && test -z "${HAS_attiny15_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny15\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny28_TRUE}" && test -z "${HAS_attiny28_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny28\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr2_TRUE}" && test -z "${HAS_avr2_FALSE}"; then as_fn_error $? "conditional \"HAS_avr2\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s2313_TRUE}" && test -z "${HAS_at90s2313_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s2313\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s2323_TRUE}" && test -z "${HAS_at90s2323_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s2323\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s2333_TRUE}" && test -z "${HAS_at90s2333_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s2333\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s2343_TRUE}" && test -z "${HAS_at90s2343_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s2343\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s4414_TRUE}" && test -z "${HAS_at90s4414_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s4414\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s4433_TRUE}" && test -z "${HAS_at90s4433_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s4433\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s4434_TRUE}" && test -z "${HAS_at90s4434_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s4434\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s8515_TRUE}" && test -z "${HAS_at90s8515_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s8515\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90c8534_TRUE}" && test -z "${HAS_at90c8534_FALSE}"; then as_fn_error $? "conditional \"HAS_at90c8534\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90s8535_TRUE}" && test -z "${HAS_at90s8535_FALSE}"; then as_fn_error $? "conditional \"HAS_at90s8535\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny22_TRUE}" && test -z "${HAS_attiny22_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny22\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny26_TRUE}" && test -z "${HAS_attiny26_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny26\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr25_TRUE}" && test -z "${HAS_avr25_FALSE}"; then as_fn_error $? "conditional \"HAS_avr25\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_ata6289_TRUE}" && test -z "${HAS_ata6289_FALSE}"; then as_fn_error $? "conditional \"HAS_ata6289\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny13_TRUE}" && test -z "${HAS_attiny13_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny13\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny13a_TRUE}" && test -z "${HAS_attiny13a_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny13a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny2313_TRUE}" && test -z "${HAS_attiny2313_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny2313\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny2313a_TRUE}" && test -z "${HAS_attiny2313a_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny2313a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny24_TRUE}" && test -z "${HAS_attiny24_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny24\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny24a_TRUE}" && test -z "${HAS_attiny24a_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny24a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny25_TRUE}" && test -z "${HAS_attiny25_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny25\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny261_TRUE}" && test -z "${HAS_attiny261_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny261\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny261a_TRUE}" && test -z "${HAS_attiny261a_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny261a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny43u_TRUE}" && test -z "${HAS_attiny43u_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny43u\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny4313_TRUE}" && test -z "${HAS_attiny4313_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny4313\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny44_TRUE}" && test -z "${HAS_attiny44_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny44\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny44a_TRUE}" && test -z "${HAS_attiny44a_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny44a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny45_TRUE}" && test -z "${HAS_attiny45_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny45\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny461_TRUE}" && test -z "${HAS_attiny461_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny461\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny461a_TRUE}" && test -z "${HAS_attiny461a_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny461a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny48_TRUE}" && test -z "${HAS_attiny48_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny48\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny84_TRUE}" && test -z "${HAS_attiny84_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny84\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny84a_TRUE}" && test -z "${HAS_attiny84a_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny84a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny85_TRUE}" && test -z "${HAS_attiny85_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny85\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny861_TRUE}" && test -z "${HAS_attiny861_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny861\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny861a_TRUE}" && test -z "${HAS_attiny861a_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny861a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny87_TRUE}" && test -z "${HAS_attiny87_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny87\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny88_TRUE}" && test -z "${HAS_attiny88_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny88\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at86rf401_TRUE}" && test -z "${HAS_at86rf401_FALSE}"; then as_fn_error $? "conditional \"HAS_at86rf401\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr3_TRUE}" && test -z "${HAS_avr3_FALSE}"; then as_fn_error $? "conditional \"HAS_avr3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at43usb320_TRUE}" && test -z "${HAS_at43usb320_FALSE}"; then as_fn_error $? "conditional \"HAS_at43usb320\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at43usb355_TRUE}" && test -z "${HAS_at43usb355_FALSE}"; then as_fn_error $? "conditional \"HAS_at43usb355\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at76c711_TRUE}" && test -z "${HAS_at76c711_FALSE}"; then as_fn_error $? "conditional \"HAS_at76c711\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr31_TRUE}" && test -z "${HAS_avr31_FALSE}"; then as_fn_error $? "conditional \"HAS_avr31\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega103_TRUE}" && test -z "${HAS_atmega103_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega103\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr35_TRUE}" && test -z "${HAS_avr35_FALSE}"; then as_fn_error $? "conditional \"HAS_avr35\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90usb82_TRUE}" && test -z "${HAS_at90usb82_FALSE}"; then as_fn_error $? "conditional \"HAS_at90usb82\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90usb162_TRUE}" && test -z "${HAS_at90usb162_FALSE}"; then as_fn_error $? "conditional \"HAS_at90usb162\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega8u2_TRUE}" && test -z "${HAS_atmega8u2_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega8u2\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega16u2_TRUE}" && test -z "${HAS_atmega16u2_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega16u2\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega32u2_TRUE}" && test -z "${HAS_atmega32u2_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega32u2\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny167_TRUE}" && test -z "${HAS_attiny167_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny167\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr4_TRUE}" && test -z "${HAS_avr4_FALSE}"; then as_fn_error $? "conditional \"HAS_avr4\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega8_TRUE}" && test -z "${HAS_atmega8_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega8\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega8515_TRUE}" && test -z "${HAS_atmega8515_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega8515\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega8535_TRUE}" && test -z "${HAS_atmega8535_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega8535\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega48_TRUE}" && test -z "${HAS_atmega48_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega48\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega48a_TRUE}" && test -z "${HAS_atmega48a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega48a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega48p_TRUE}" && test -z "${HAS_atmega48p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega48p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega88_TRUE}" && test -z "${HAS_atmega88_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega88\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega88a_TRUE}" && test -z "${HAS_atmega88a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega88a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega88p_TRUE}" && test -z "${HAS_atmega88p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega88p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega88pa_TRUE}" && test -z "${HAS_atmega88pa_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega88pa\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega8hva_TRUE}" && test -z "${HAS_atmega8hva_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega8hva\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90pwm1_TRUE}" && test -z "${HAS_at90pwm1_FALSE}"; then as_fn_error $? "conditional \"HAS_at90pwm1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90pwm2_TRUE}" && test -z "${HAS_at90pwm2_FALSE}"; then as_fn_error $? "conditional \"HAS_at90pwm2\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90pwm2b_TRUE}" && test -z "${HAS_at90pwm2b_FALSE}"; then as_fn_error $? "conditional \"HAS_at90pwm2b\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90pwm3_TRUE}" && test -z "${HAS_at90pwm3_FALSE}"; then as_fn_error $? "conditional \"HAS_at90pwm3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90pwm3b_TRUE}" && test -z "${HAS_at90pwm3b_FALSE}"; then as_fn_error $? "conditional \"HAS_at90pwm3b\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90pwm81_TRUE}" && test -z "${HAS_at90pwm81_FALSE}"; then as_fn_error $? "conditional \"HAS_at90pwm81\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr5_TRUE}" && test -z "${HAS_avr5_FALSE}"; then as_fn_error $? "conditional \"HAS_avr5\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90can32_TRUE}" && test -z "${HAS_at90can32_FALSE}"; then as_fn_error $? "conditional \"HAS_at90can32\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90can64_TRUE}" && test -z "${HAS_at90can64_FALSE}"; then as_fn_error $? "conditional \"HAS_at90can64\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90scr100_TRUE}" && test -z "${HAS_at90scr100_FALSE}"; then as_fn_error $? "conditional \"HAS_at90scr100\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90usb646_TRUE}" && test -z "${HAS_at90usb646_FALSE}"; then as_fn_error $? "conditional \"HAS_at90usb646\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90usb647_TRUE}" && test -z "${HAS_at90usb647_FALSE}"; then as_fn_error $? "conditional \"HAS_at90usb647\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90pwm316_TRUE}" && test -z "${HAS_at90pwm316_FALSE}"; then as_fn_error $? "conditional \"HAS_at90pwm316\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90pwm216_TRUE}" && test -z "${HAS_at90pwm216_FALSE}"; then as_fn_error $? "conditional \"HAS_at90pwm216\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at94k_TRUE}" && test -z "${HAS_at94k_FALSE}"; then as_fn_error $? "conditional \"HAS_at94k\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega16_TRUE}" && test -z "${HAS_atmega16_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega16\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega16a_TRUE}" && test -z "${HAS_atmega16a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega16a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega161_TRUE}" && test -z "${HAS_atmega161_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega161\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega162_TRUE}" && test -z "${HAS_atmega162_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega162\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega163_TRUE}" && test -z "${HAS_atmega163_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega163\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega164a_TRUE}" && test -z "${HAS_atmega164a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega164a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega164p_TRUE}" && test -z "${HAS_atmega164p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega164p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega165_TRUE}" && test -z "${HAS_atmega165_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega165\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega165a_TRUE}" && test -z "${HAS_atmega165a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega165a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega165p_TRUE}" && test -z "${HAS_atmega165p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega165p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega168_TRUE}" && test -z "${HAS_atmega168_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega168\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega168a_TRUE}" && test -z "${HAS_atmega168a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega168a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega168p_TRUE}" && test -z "${HAS_atmega168p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega168p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega169_TRUE}" && test -z "${HAS_atmega169_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega169\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega169a_TRUE}" && test -z "${HAS_atmega169a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega169a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega169p_TRUE}" && test -z "${HAS_atmega169p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega169p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega169pa_TRUE}" && test -z "${HAS_atmega169pa_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega169pa\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega16hva_TRUE}" && test -z "${HAS_atmega16hva_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega16hva\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega16hva2_TRUE}" && test -z "${HAS_atmega16hva2_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega16hva2\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega16hvb_TRUE}" && test -z "${HAS_atmega16hvb_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega16hvb\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega16hvbrevb_TRUE}" && test -z "${HAS_atmega16hvbrevb_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega16hvbrevb\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega16m1_TRUE}" && test -z "${HAS_atmega16m1_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega16m1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega16u4_TRUE}" && test -z "${HAS_atmega16u4_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega16u4\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega32_TRUE}" && test -z "${HAS_atmega32_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega32\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega323_TRUE}" && test -z "${HAS_atmega323_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega323\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega324a_TRUE}" && test -z "${HAS_atmega324a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega324a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega324p_TRUE}" && test -z "${HAS_atmega324p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega324p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega324pa_TRUE}" && test -z "${HAS_atmega324pa_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega324pa\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega325_TRUE}" && test -z "${HAS_atmega325_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega325\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega325a_TRUE}" && test -z "${HAS_atmega325a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega325a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega325p_TRUE}" && test -z "${HAS_atmega325p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega325p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega3250_TRUE}" && test -z "${HAS_atmega3250_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega3250\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega3250a_TRUE}" && test -z "${HAS_atmega3250a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega3250a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega3250p_TRUE}" && test -z "${HAS_atmega3250p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega3250p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega328_TRUE}" && test -z "${HAS_atmega328_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega328\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega328p_TRUE}" && test -z "${HAS_atmega328p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega328p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega329_TRUE}" && test -z "${HAS_atmega329_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega329\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega329a_TRUE}" && test -z "${HAS_atmega329a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega329a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega329p_TRUE}" && test -z "${HAS_atmega329p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega329p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega329pa_TRUE}" && test -z "${HAS_atmega329pa_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega329pa\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega3290_TRUE}" && test -z "${HAS_atmega3290_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega3290\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega3290a_TRUE}" && test -z "${HAS_atmega3290a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega3290a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega3290p_TRUE}" && test -z "${HAS_atmega3290p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega3290p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega32c1_TRUE}" && test -z "${HAS_atmega32c1_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega32c1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega32hvb_TRUE}" && test -z "${HAS_atmega32hvb_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega32hvb\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega32hvbrevb_TRUE}" && test -z "${HAS_atmega32hvbrevb_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega32hvbrevb\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega32m1_TRUE}" && test -z "${HAS_atmega32m1_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega32m1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega32u4_TRUE}" && test -z "${HAS_atmega32u4_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega32u4\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega32u6_TRUE}" && test -z "${HAS_atmega32u6_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega32u6\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega406_TRUE}" && test -z "${HAS_atmega406_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega406\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega64_TRUE}" && test -z "${HAS_atmega64_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega64\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega640_TRUE}" && test -z "${HAS_atmega640_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega640\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega644_TRUE}" && test -z "${HAS_atmega644_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega644\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega644a_TRUE}" && test -z "${HAS_atmega644a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega644a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega644p_TRUE}" && test -z "${HAS_atmega644p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega644p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega644pa_TRUE}" && test -z "${HAS_atmega644pa_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega644pa\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega645_TRUE}" && test -z "${HAS_atmega645_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega645\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega645a_TRUE}" && test -z "${HAS_atmega645a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega645a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega645p_TRUE}" && test -z "${HAS_atmega645p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega645p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega6450_TRUE}" && test -z "${HAS_atmega6450_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega6450\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega6450a_TRUE}" && test -z "${HAS_atmega6450a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega6450a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega6450p_TRUE}" && test -z "${HAS_atmega6450p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega6450p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega649_TRUE}" && test -z "${HAS_atmega649_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega649\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega649a_TRUE}" && test -z "${HAS_atmega649a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega649a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega649p_TRUE}" && test -z "${HAS_atmega649p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega649p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega6490_TRUE}" && test -z "${HAS_atmega6490_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega6490\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega6490a_TRUE}" && test -z "${HAS_atmega6490a_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega6490a\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega6490p_TRUE}" && test -z "${HAS_atmega6490p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega6490p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega64c1_TRUE}" && test -z "${HAS_atmega64c1_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega64c1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega64hve_TRUE}" && test -z "${HAS_atmega64hve_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega64hve\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega64m1_TRUE}" && test -z "${HAS_atmega64m1_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega64m1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega128rfa1_TRUE}" && test -z "${HAS_atmega128rfa1_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega128rfa1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_m3000_TRUE}" && test -z "${HAS_m3000_FALSE}"; then as_fn_error $? "conditional \"HAS_m3000\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr51_TRUE}" && test -z "${HAS_avr51_FALSE}"; then as_fn_error $? "conditional \"HAS_avr51\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega128_TRUE}" && test -z "${HAS_atmega128_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega128\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega1280_TRUE}" && test -z "${HAS_atmega1280_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega1280\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega1281_TRUE}" && test -z "${HAS_atmega1281_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega1281\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega1284p_TRUE}" && test -z "${HAS_atmega1284p_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega1284p\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90can128_TRUE}" && test -z "${HAS_at90can128_FALSE}"; then as_fn_error $? "conditional \"HAS_at90can128\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90usb1286_TRUE}" && test -z "${HAS_at90usb1286_FALSE}"; then as_fn_error $? "conditional \"HAS_at90usb1286\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_at90usb1287_TRUE}" && test -z "${HAS_at90usb1287_FALSE}"; then as_fn_error $? "conditional \"HAS_at90usb1287\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avr6_TRUE}" && test -z "${HAS_avr6_FALSE}"; then as_fn_error $? "conditional \"HAS_avr6\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega2560_TRUE}" && test -z "${HAS_atmega2560_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega2560\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atmega2561_TRUE}" && test -z "${HAS_atmega2561_FALSE}"; then as_fn_error $? "conditional \"HAS_atmega2561\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avrxmega2_TRUE}" && test -z "${HAS_avrxmega2_FALSE}"; then as_fn_error $? "conditional \"HAS_avrxmega2\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega16a4_TRUE}" && test -z "${HAS_atxmega16a4_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega16a4\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega16d4_TRUE}" && test -z "${HAS_atxmega16d4_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega16d4\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega32a4_TRUE}" && test -z "${HAS_atxmega32a4_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega32a4\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega32d4_TRUE}" && test -z "${HAS_atxmega32d4_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega32d4\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avrxmega4_TRUE}" && test -z "${HAS_avrxmega4_FALSE}"; then as_fn_error $? "conditional \"HAS_avrxmega4\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega64a3_TRUE}" && test -z "${HAS_atxmega64a3_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega64a3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega64d3_TRUE}" && test -z "${HAS_atxmega64d3_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega64d3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avrxmega5_TRUE}" && test -z "${HAS_avrxmega5_FALSE}"; then as_fn_error $? "conditional \"HAS_avrxmega5\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega64a1_TRUE}" && test -z "${HAS_atxmega64a1_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega64a1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega64a1u_TRUE}" && test -z "${HAS_atxmega64a1u_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega64a1u\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avrxmega6_TRUE}" && test -z "${HAS_avrxmega6_FALSE}"; then as_fn_error $? "conditional \"HAS_avrxmega6\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega128a3_TRUE}" && test -z "${HAS_atxmega128a3_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega128a3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega128d3_TRUE}" && test -z "${HAS_atxmega128d3_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega128d3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega192a3_TRUE}" && test -z "${HAS_atxmega192a3_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega192a3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega192d3_TRUE}" && test -z "${HAS_atxmega192d3_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega192d3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega256a3_TRUE}" && test -z "${HAS_atxmega256a3_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega256a3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega256a3b_TRUE}" && test -z "${HAS_atxmega256a3b_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega256a3b\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega256d3_TRUE}" && test -z "${HAS_atxmega256d3_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega256d3\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avrxmega7_TRUE}" && test -z "${HAS_avrxmega7_FALSE}"; then as_fn_error $? "conditional \"HAS_avrxmega7\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega128a1_TRUE}" && test -z "${HAS_atxmega128a1_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega128a1\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_atxmega128a1u_TRUE}" && test -z "${HAS_atxmega128a1u_FALSE}"; then as_fn_error $? "conditional \"HAS_atxmega128a1u\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_avrtiny10_TRUE}" && test -z "${HAS_avrtiny10_FALSE}"; then as_fn_error $? "conditional \"HAS_avrtiny10\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny4_TRUE}" && test -z "${HAS_attiny4_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny4\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny5_TRUE}" && test -z "${HAS_attiny5_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny5\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny9_TRUE}" && test -z "${HAS_attiny9_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny9\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny10_TRUE}" && test -z "${HAS_attiny10_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny10\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny20_TRUE}" && test -z "${HAS_attiny20_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny20\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${HAS_attiny40_TRUE}" && test -z "${HAS_attiny40_FALSE}"; then as_fn_error $? "conditional \"HAS_attiny40\" was never defined. Usually this means the macro was only invoked conditionally." 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"avr/lib/avr25/attiny2313a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny2313a/Makefile" ;; "avr/lib/avr25/attiny24/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny24/Makefile" ;; "avr/lib/avr25/attiny24a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny24a/Makefile" ;; "avr/lib/avr25/attiny25/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny25/Makefile" ;; "avr/lib/avr25/attiny261/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny261/Makefile" ;; "avr/lib/avr25/attiny261a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny261a/Makefile" ;; "avr/lib/avr25/attiny4313/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny4313/Makefile" ;; "avr/lib/avr25/attiny43u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny43u/Makefile" ;; "avr/lib/avr25/attiny44/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny44/Makefile" ;; "avr/lib/avr25/attiny44a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny44a/Makefile" ;; "avr/lib/avr25/attiny45/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny45/Makefile" ;; "avr/lib/avr25/attiny461/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny461/Makefile" ;; "avr/lib/avr25/attiny461a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny461a/Makefile" ;; "avr/lib/avr25/attiny48/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny48/Makefile" ;; "avr/lib/avr25/attiny84/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny84/Makefile" ;; "avr/lib/avr25/attiny84a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny84a/Makefile" ;; "avr/lib/avr25/attiny85/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny85/Makefile" ;; "avr/lib/avr25/attiny861/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny861/Makefile" ;; "avr/lib/avr25/attiny861a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny861a/Makefile" ;; "avr/lib/avr25/attiny87/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny87/Makefile" ;; "avr/lib/avr25/attiny88/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny88/Makefile" ;; "avr/lib/avr3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/Makefile" ;; "avr/lib/avr3/atmega103/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/atmega103/Makefile" ;; "avr/lib/avr3/at43usb320/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/at43usb320/Makefile" ;; "avr/lib/avr3/at43usb355/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/at43usb355/Makefile" ;; "avr/lib/avr3/at76c711/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/at76c711/Makefile" ;; "avr/lib/avr3/at90usb82/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/at90usb82/Makefile" ;; "avr/lib/avr3/at90usb162/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/at90usb162/Makefile" ;; "avr/lib/avr31/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr31/Makefile" ;; "avr/lib/avr31/atmega103/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr31/atmega103/Makefile" ;; "avr/lib/avr31/at43usb320/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr31/at43usb320/Makefile" ;; "avr/lib/avr35/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/Makefile" ;; "avr/lib/avr35/at90usb82/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/at90usb82/Makefile" ;; "avr/lib/avr35/at90usb162/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/at90usb162/Makefile" ;; "avr/lib/avr35/atmega8u2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/atmega8u2/Makefile" ;; "avr/lib/avr35/atmega16u2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/atmega16u2/Makefile" ;; "avr/lib/avr35/atmega32u2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/atmega32u2/Makefile" ;; "avr/lib/avr35/attiny167/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/attiny167/Makefile" ;; "avr/lib/avr4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/Makefile" ;; "avr/lib/avr4/atmega48/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48/Makefile" ;; "avr/lib/avr4/atmega48a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48a/Makefile" ;; "avr/lib/avr4/atmega48p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48p/Makefile" ;; "avr/lib/avr4/atmega8/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8/Makefile" ;; "avr/lib/avr4/atmega88/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88/Makefile" ;; "avr/lib/avr4/atmega88a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88a/Makefile" ;; "avr/lib/avr4/atmega88p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88p/Makefile" ;; "avr/lib/avr4/atmega88pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88pa/Makefile" ;; "avr/lib/avr4/atmega8515/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8515/Makefile" ;; "avr/lib/avr4/atmega8535/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8535/Makefile" ;; "avr/lib/avr4/atmega8hva/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8hva/Makefile" ;; "avr/lib/avr4/at90pwm1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm1/Makefile" ;; "avr/lib/avr4/at90pwm2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm2/Makefile" ;; "avr/lib/avr4/at90pwm2b/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm2b/Makefile" ;; "avr/lib/avr4/at90pwm3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm3/Makefile" ;; "avr/lib/avr4/at90pwm3b/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm3b/Makefile" ;; "avr/lib/avr4/at90pwm81/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm81/Makefile" ;; "avr/lib/avr5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/Makefile" ;; "avr/lib/avr5/at90can32/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90can32/Makefile" ;; "avr/lib/avr5/at90can64/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90can64/Makefile" ;; "avr/lib/avr5/at90can128/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90can128/Makefile" ;; "avr/lib/avr5/at90pwm216/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90pwm216/Makefile" ;; "avr/lib/avr5/at90pwm316/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90pwm316/Makefile" ;; "avr/lib/avr5/at90scr100/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90scr100/Makefile" ;; "avr/lib/avr5/at90usb646/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90usb646/Makefile" ;; "avr/lib/avr5/at90usb647/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90usb647/Makefile" ;; "avr/lib/avr5/at90usb1286/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90usb1286/Makefile" ;; "avr/lib/avr5/at90usb1287/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90usb1287/Makefile" ;; "avr/lib/avr5/at94k/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at94k/Makefile" ;; "avr/lib/avr5/atmega16/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16/Makefile" ;; "avr/lib/avr5/atmega16a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16a/Makefile" ;; "avr/lib/avr5/atmega161/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega161/Makefile" ;; "avr/lib/avr5/atmega162/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega162/Makefile" ;; "avr/lib/avr5/atmega163/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega163/Makefile" ;; "avr/lib/avr5/atmega164a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega164a/Makefile" ;; "avr/lib/avr5/atmega164p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega164p/Makefile" ;; "avr/lib/avr5/atmega165/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165/Makefile" ;; "avr/lib/avr5/atmega165a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165a/Makefile" ;; "avr/lib/avr5/atmega165p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165p/Makefile" ;; "avr/lib/avr5/atmega168/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168/Makefile" ;; "avr/lib/avr5/atmega168a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168a/Makefile" ;; "avr/lib/avr5/atmega168p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168p/Makefile" ;; "avr/lib/avr5/atmega169/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169/Makefile" ;; "avr/lib/avr5/atmega169a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169a/Makefile" ;; "avr/lib/avr5/atmega169p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169p/Makefile" ;; "avr/lib/avr5/atmega169pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169pa/Makefile" ;; "avr/lib/avr5/atmega16hva/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hva/Makefile" ;; "avr/lib/avr5/atmega16hva2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hva2/Makefile" ;; "avr/lib/avr5/atmega16hvb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hvb/Makefile" ;; "avr/lib/avr5/atmega16hvbrevb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hvbrevb/Makefile" ;; "avr/lib/avr5/atmega16m1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16m1/Makefile" ;; "avr/lib/avr5/atmega16u4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16u4/Makefile" ;; "avr/lib/avr5/atmega32/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32/Makefile" ;; "avr/lib/avr5/atmega323/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega323/Makefile" ;; "avr/lib/avr5/atmega324a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega324a/Makefile" ;; "avr/lib/avr5/atmega324p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega324p/Makefile" ;; "avr/lib/avr5/atmega324pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega324pa/Makefile" ;; "avr/lib/avr5/atmega325/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325/Makefile" ;; "avr/lib/avr5/atmega325a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325a/Makefile" ;; "avr/lib/avr5/atmega325p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325p/Makefile" ;; "avr/lib/avr5/atmega3250/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250/Makefile" ;; "avr/lib/avr5/atmega3250a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250a/Makefile" ;; "avr/lib/avr5/atmega3250p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250p/Makefile" ;; "avr/lib/avr5/atmega328/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega328/Makefile" ;; "avr/lib/avr5/atmega328p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega328p/Makefile" ;; "avr/lib/avr5/atmega329/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329/Makefile" ;; "avr/lib/avr5/atmega329a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329a/Makefile" ;; "avr/lib/avr5/atmega329p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329p/Makefile" ;; "avr/lib/avr5/atmega329pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329pa/Makefile" ;; "avr/lib/avr5/atmega3290/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290/Makefile" ;; "avr/lib/avr5/atmega3290a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290a/Makefile" ;; "avr/lib/avr5/atmega3290p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290p/Makefile" ;; "avr/lib/avr5/atmega32c1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32c1/Makefile" ;; "avr/lib/avr5/atmega32hvb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32hvb/Makefile" ;; "avr/lib/avr5/atmega32hvbrevb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32hvbrevb/Makefile" ;; "avr/lib/avr5/atmega32m1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32m1/Makefile" ;; "avr/lib/avr5/atmega32u4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32u4/Makefile" ;; "avr/lib/avr5/atmega32u6/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32u6/Makefile" ;; "avr/lib/avr5/atmega406/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega406/Makefile" ;; "avr/lib/avr5/atmega64/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64/Makefile" ;; "avr/lib/avr5/atmega640/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega640/Makefile" ;; "avr/lib/avr5/atmega644/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644/Makefile" ;; "avr/lib/avr5/atmega644a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644a/Makefile" ;; "avr/lib/avr5/atmega644p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644p/Makefile" ;; "avr/lib/avr5/atmega644pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644pa/Makefile" ;; "avr/lib/avr5/atmega645/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega645/Makefile" ;; "avr/lib/avr5/atmega645a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega645a/Makefile" ;; "avr/lib/avr5/atmega645p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega645p/Makefile" ;; "avr/lib/avr5/atmega6450/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6450/Makefile" ;; "avr/lib/avr5/atmega6450a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6450a/Makefile" ;; "avr/lib/avr5/atmega6450p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6450p/Makefile" ;; "avr/lib/avr5/atmega649/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega649/Makefile" ;; "avr/lib/avr5/atmega649a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega649a/Makefile" ;; "avr/lib/avr5/atmega649p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega649p/Makefile" ;; "avr/lib/avr5/atmega6490/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6490/Makefile" ;; "avr/lib/avr5/atmega6490a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6490a/Makefile" ;; "avr/lib/avr5/atmega6490p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6490p/Makefile" ;; "avr/lib/avr5/atmega64c1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64c1/Makefile" ;; "avr/lib/avr5/atmega64hve/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64hve/Makefile" ;; "avr/lib/avr5/atmega64m1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64m1/Makefile" ;; "avr/lib/avr5/atmega128/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega128/Makefile" ;; "avr/lib/avr5/atmega1280/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega1280/Makefile" ;; "avr/lib/avr5/atmega1281/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega1281/Makefile" ;; "avr/lib/avr5/atmega1284p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega1284p/Makefile" ;; "avr/lib/avr5/atmega128rfa1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega128rfa1/Makefile" ;; "avr/lib/avr5/m3000/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/m3000/Makefile" ;; "avr/lib/avr51/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/Makefile" ;; "avr/lib/avr51/atmega128/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128/Makefile" ;; "avr/lib/avr51/atmega1280/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1280/Makefile" ;; "avr/lib/avr51/atmega1281/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1281/Makefile" ;; "avr/lib/avr51/atmega1284p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1284p/Makefile" ;; "avr/lib/avr51/atmega128rfa1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128rfa1/Makefile" ;; "avr/lib/avr51/at90can128/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/at90can128/Makefile" ;; "avr/lib/avr51/at90usb1286/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/at90usb1286/Makefile" ;; "avr/lib/avr51/at90usb1287/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/at90usb1287/Makefile" ;; "avr/lib/avr6/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/Makefile" ;; "avr/lib/avr6/atmega2560/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega2560/Makefile" ;; "avr/lib/avr6/atmega2561/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega2561/Makefile" ;; "avr/lib/avrxmega2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/Makefile" ;; "avr/lib/avrxmega2/atxmega16a4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16a4/Makefile" ;; "avr/lib/avrxmega2/atxmega16d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16d4/Makefile" ;; "avr/lib/avrxmega2/atxmega32a4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32a4/Makefile" ;; "avr/lib/avrxmega2/atxmega32d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32d4/Makefile" ;; "avr/lib/avrxmega4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/Makefile" ;; "avr/lib/avrxmega4/atxmega64a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64a3/Makefile" ;; "avr/lib/avrxmega4/atxmega64d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64d3/Makefile" ;; "avr/lib/avrxmega5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega5/Makefile" ;; "avr/lib/avrxmega5/atxmega64a1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega5/atxmega64a1/Makefile" ;; "avr/lib/avrxmega5/atxmega64a1u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega5/atxmega64a1u/Makefile" ;; "avr/lib/avrxmega6/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/Makefile" ;; "avr/lib/avrxmega6/atxmega128a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128a3/Makefile" ;; "avr/lib/avrxmega6/atxmega128d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128d3/Makefile" ;; "avr/lib/avrxmega6/atxmega192a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192a3/Makefile" ;; "avr/lib/avrxmega6/atxmega192d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192d3/Makefile" ;; "avr/lib/avrxmega6/atxmega256a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3/Makefile" ;; "avr/lib/avrxmega6/atxmega256a3b/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3b/Makefile" ;; "avr/lib/avrxmega6/atxmega256d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256d3/Makefile" ;; "avr/lib/avrxmega7/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/Makefile" ;; "avr/lib/avrxmega7/atxmega128a1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/atxmega128a1/Makefile" ;; "avr/lib/avrxmega7/atxmega128a1u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/atxmega128a1u/Makefile" ;; "avr/lib/avrtiny10/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny10/Makefile" ;; "avr/lib/avrtiny10/attiny4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny10/attiny4/Makefile" ;; "avr/lib/avrtiny10/attiny5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny10/attiny5/Makefile" ;; "avr/lib/avrtiny10/attiny9/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny10/attiny9/Makefile" ;; "avr/lib/avrtiny10/attiny10/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny10/attiny10/Makefile" ;; "avr/lib/avrtiny10/attiny20/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny10/attiny20/Makefile" ;; "avr/lib/avrtiny10/attiny40/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny10/attiny40/Makefile" ;; *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;; esac done # If the user did not use the arguments to specify the items to instantiate, # then the envvar interface is used. Set only those that are not. # We use the long form for the default assignment because of an extremely # bizarre bug on SunOS 4.1.3. if $ac_need_defaults; then test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands fi # Have a temporary directory for convenience. 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When coming back to configure, we # need to make the FD available again. if test "$no_create" != yes; then ac_cs_success=: ac_config_status_args= test "$silent" = yes && ac_config_status_args="$ac_config_status_args --quiet" exec 5>/dev/null $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false exec 5>>config.log # Use ||, not &&, to avoid exiting from the if with $? = 1, which # would make configure fail if this is the last instruction. $ac_cs_success || as_fn_exit 1 fi if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} fi avr-libc-1.8.0.orig/NEWS0000644000000000000000000012655711732702554011571 0ustar *** Changes in avr-libc-1.8.0: * Bugs fixed: [#17815] Configure does not honor --mandir option [#23234] Alternate interrupt macro [#24861] Interrupt documentation contains extra include [#32103] Support for Target-Triplets [#32419] Incorrect EEPROM size in header for ATxmega192A3 [#32650] Missing include in util/delay.h [#32675] power_all_enable/disable does not affect timer1 on ATmega164P [#32698] power.h has additional endif that will break the build [#32773] stdiodemo source code is broken [#32988] Internal compiler error: build_unary_op [#33130] twitest.c source code is broken [#33230] Sleep modes have incorrect names for ATtiny261/461/861 [#33238] Wrong _VECTORS_SIZE for mega8U2 et al [#33858] in avr/power.h, clock_prescale_set() not defined for mega328 [#33920] ICR1 incorrectly defined for tiny167 [#34047] missing math.h include in delay.h [#34514] misspelled in math.h [#35020] stdint.h: signed types need explicit "signed" [#35093] strlcat_P fails for some destinations [no-id] New names for CLKSTA/CLKSEL0/1 for AT90USB82/162 system when power_all_disable() is used [no-id] util/delay.h would not compile with -ffreestanding * New devices supported: * Contributed Patches: [#7531] Bad name of bit in TCCR0A : WGM0 instead of CTC0 for ATtinyX61 [#7362] iom16a.h: USART vectors inconsistently named for ATmega16A [#7226] ATMEGA8U2 Patches * Other changes: - The old prog_* typedefs are now deprecated, and are only included if requested by the user. This request is expressed by declaring the macro __PROG_TYPES_COMPAT__, either by a #define directive before including , or by a -D compiler option. - Optimized strlen_P, thanks to Jan Waclawek. Rename strlen_P to be __strlen_P and add new strlen_P inline function in header file that checks if value is a constant and known at compile time. If not, then the new inline function calls __strlen_P as normal. *** Changes in avr-libc-1.7.1: * Bugs fixed: [Atmel: #11793] XMEGA A devices: 4096-cycle DAC refresh interval setting has wrong name [Atmel: #12314] Hi-Res(CTRLA) and AWex (FDEMASK) [Atmel: #12536] Remove CALCTRL in xmega header files. [no-id] Fix wrong vector table size for ATmega168A devices. [#29235] power.h - warning: comma at end of enumerator list [#30783] Missing prototype in power.h [#31270] Stale link to Philips (now NXP) I2C specification/users manual * New devices supported: ATTiny84a ATMega16HVB RevB ATMega32HVB RevB * Contributed Patches: * Other changes: *** Changes in avr-libc-1.7.0: * Bugs fixed: [Atmel: #7159] the memory location of tccr0b is mixed with tccr0a for tiny48/88 [no-id] Fix CLKPCE bit value to be 7. [no-id] inlining failed in call to '_delay_ms': function body not available [no-id] malloc() could allocate memory beyond the limits of heap [no-id] xmega header file updates. [no-id] Enable ATmega128RFA1 in [no-id] longjmp() writes to EIND register, it is forbidden by AVR-GCC's API [no-id] Define _VECTORS_SIZE in iom3000.h [no-id] Redefine __tmp_reg__ and __zer_reg__ for AVR TINY. [AVR Tools: #9724] Error in ATtiny13A include file, PRR register [sourceforge.net: #1836849] Multiplication does not work for AT90USB162 [sourceforge.net: #1883630] ATmegaXX4 - USART0 and USART1 additional bits aliases [sourceforge.net: #1910885] Typo in io90pwm3b.h [sourceforge.net: #1913681] Missing INT3 define in io90pwm3b.h [sourceforge.net: #1957780] New 'FUSES-support' gives error in c++ files [sourceforge.net: #1969436] Wrong flash size for ATmega32U4 [sourceforge.net: #2010688] ATtiny48 SPSR register bits [sourceforge.net: #2012448] ATmega6450 USART Interrupts [sourceforge.net: #2016128] Incorrect ATMega32[c1|m1] Header Entries [sourceforge.net: #2018957] Wrong SPM_PAGESIZE for mega1284P [sourceforge.net: #2033993] User manual: data symbol spec incorrect [sourceforge.net: #2305703] iom162.h ASSR bitdef, typo? [sourceforge.net: #2411516] Error/Bug in the iotn88.h file [sourceforge.net: #2420567] ATmega329P missing in sleep.h [sourceforge.net: #2693898] ATmega32U6 missing in power.h [sourceforge.net: #2738926] avr/eeprom.h EEGET and EEPUT [sourceforge.net: #2812125] ATmega16U4 missing in power.h [sourceforge.net: #2913419] Misspelled Structure Element - xmega [#3485] Using float arithmetic without linking with -lm result in incorrect code [#19079] sscanf %s eats 1 char too much [#19494] sfr_defs.h documentation: Remove references to deprecated macros. [#21410] Incorrect use of 16-bit eeprom addresses in devices with 8-Bit address registers [#21621] Allow autoconf 2.61 [#21622] Support building in a subdirectory [#21623] boot.h: Use the "z" register constraint [#21869] Multiple defines in iotn2313.h [#21872] __floatunsisf/undisf incorrectly named [#21905] scanf: float conversion ignores the suppression symbol [#21906] scanf: float conversion, wrong width count in case of sign or exponent [#21931] Wrong fuses defined for the ATMEGA88/168 [#21935] Typo in avr-ar example avr-as should be avr-ar [#21995] pgm_read_xxxx() does not use enhanced LPM instruction [#21958] UBRR0/UBRR1 SFR is redefined for ATmegaXX8p and atmega1284p devices [#21962] PSYNC1_0 a PSYNC1_1 bits not defined for AT90PWM3B and AT90PWM316 devices [#21986] Typo in iotn13.h [#22016] Typo in iotn2313.h: SIG_OUTPUT_COPMARE0A [#22119] Misleading statement in FAQ [#22153] setjmp.o is wrong in libc.a (1.6.1) for avr's with SPH [#22240] Add EEPROM Page Size to header files [#22276] wdt_reset fails with devices with large WDTCSR addresses [#22377] Wrong XRAMEND for some recent ioXXX.h header files. [#22387] Missing EIMSK and __EEPROM_REG_LOCATIONS__ in iom168p.h [#22390] Unclear note about function pointers [#22447] Summary of iom?8p.h header updates needed [#22493] Typo in iom1284p.h. [#22540] Adding signature bytes to header files [#22548] Missing IVCE and IVSEL in iom328p.h [#22568] Missing EEPROM_REG_LOCATIONS in iom328p.h [#22572] Documentation FAQ example proposal [#22642] AT90USB162 and AT90USB82 not supported in [#22643] math.h c99 incompability [#22666] io90pwm3b.h errors [#22785] ATMega644P Support Missing from avr/include/avr/sleep.h [#22828] eeprom_write_block(): incompatibility in args order [#22834] ATmega164P/324P/644P/1284P lack BODS/BODSE bits in MCUCR [#22870] Error in wdt.h and ATmega164P [#22877] Fuse information wrong for xmega devices. [#22878] eeprom_*_word/dword/block cause hang in ATmega256x [#23004] Watchdog enable docu only generated for Xmega series [#23032] Define PORTxn, PINxn, DDxn bit names in iomxx4.h. [#23166] atmega328p does not have SPMEN [#23261] AT90USB162 and AT90USB82 missing power_all_[enable,disable]() in power.h [#23409] Provide an implementation for strtok() [#23546] FAQ documentation symbol seems wrong [#23554] Wrong bit values in iom32u4.h [#23677] Request for cbrt() and strdup to be added to libc [#23703] eeprom write functions optimisation [#23774] Using some defines from avr/fuse.h produces warning [#23850] ATMega8 does not have MCUSR defined [#23871] clock_prescale_set() not available for ATmega32U4 [#23959] Small typo in deprecated documentation [#23969] eeprom_read_byte() throws interrupt EE_READY although EERIE is cleared, controller resets [#24207] Example in inttypes.h is wrong [#24446] _attribute_ should be __attribute__ (with double underscores) [#24762] 1.6.3 wdt.h compile-time bug [#24890] Small error in libm source fp_rempio2.S [#25048] eeprom.h will not compile as c++ code. [#25120] pgm_read_*_far() functions cause incorrect usage of the Z pointer for RAM access in ATxmega series [#25131] Incorrect definition of default lfuse bits for ATTiny2313 [#25261] TWIHSR spelling deviates from XML file in AVR Studio 4.15 [#25535] Nonexistent bit definitions in iotn88.h/iotn48.h AREFD REFS1 RWWSB SM2 [#25645] xmega header files broken #defines [#25723] Realloc corrupts free list when growing into the next free item [#25846] include/avr/power.h:628:1: error: missing binary operator before token "defined" [#25925] cannot be included on Xmega devices [#25929] boot.h Fuse read not compatible with Tiny48/88. [#25930] New IO-Headerfiles missing PXn Portpindefinitions [#26188] Wrong or missing definition of SIGNATURE_X in iom644.h and others [#26284] boot_lock_fuse_bits_get does not compile under gcc 4.3.X [#26308] WDE defined as WDE3 in io90pwm3b.h and io90pwm2b.h [#26767] XMEGA GPIO register name discrepancy [#26809] Some common math constants missing in math.h [#26840] Missing #define in iom32m1.h [#26876] include io.h into fuse.h [#27201] _WORDREGISTER in xmega headers does not work in C99 mode [#27235] malloc: Several things go wrong [#27242] realloc: serious error when size shrinks [#27243] malloc: small error in comment [#27367] RAMSTART missing in elder device header files [#27434] Arguments of macros must be protected in parentheses [#28575] Minor bug in iousb162.h - missing FUSE_ prefixes [#28688] using_tools.dox fails to build due to extra underscore [#28756] Bug in AVR libc 1.6.7 (power.h for 8-bit AVR) [#28812] iotn48.h TWS# bits off by one [#28584] iocanxx.h Add word definitions to iocanxx.h [#28627] power.h ATMEGA32U2 clock_prescale_set() not available [#28901] Xmega header files with missing definitions for GPIO_t and CPU_t [#28574] Xmega D ADC struct missing registers [#28582] XMEGA A3B, RTC32 not properly supported [#28921] pointer to function > 128k flash [#29502] literal error in iox128a1.h [#29653] PUD bit missing for at90usb82 [#29950] ATtiny167 SPM_PAGESIZE Discrepancy [#30018] Errors in include files [#30085] memcpy_P on XMega does not clr NVM.CMD before copy [#30104] power.h - Missing "power_usart1_/enable/disable()" functions for ATmega644 [#30148] XMEGA register discrepancy [#30600] Missing processor spec - wdt.h include file [#30597] Missing definition for ATmega16/32/64m1/c1 [#30475] SPM_PAGESIZE is incorrect in io90pwm3b.h and io90pwm2b.h [#30552] Missing definition ADCW [#30569] ATmega16U4/32U4 wrong bit definition [#30669] Improve comment in stdiodemo [#30735] bug in example twitest [#31086] ATTINY88 RAMEND value not set to correct value in iotn88.h [#30363] _delay_xx() functions in are broken [#31990] PRPSC0 used in power.h for AT90PWM81 instead of PRPSCR [#31873] power_aes_enable/disable() are commented in power.h for xmega devices * Other changes: - Added 'avr35' architecture. Now 'MOVW' and 'LPM Rx, Z[+]' instructions supported for AT90USB82 and AT90USB162 devices. GCC 4.3 or above is necessary to use this. - Function vfscanf() is rewriten. The float point version is optimized considerably: the expense of a stack was cut by half, and the size of function has decreased approximately on 1KB. Opportunities of standard and minimal versions are expanded, and their size has remained at a former level. Briefly: . Restrictions of a float point format are eliminated. . Conversion '%[' is present in standart version now. . The minimal version differs from standard only absence of '%[' conv. . The 'hh' type qualifier is added ('char *', C99). . The maximal field width is increased up to 255 (65535 in float version). . All known bugs are fixed. New vfscanf() concedes old in: . The size of the minimal and standard versions has increased for old branches of compiler (less 4.1) and ancient chips (without MOVW). . The maximum quantity of conversions now is limited (255). - EEPROM functions are rewriten. Now they are pure asm functions. The reading of long word or block is speed up. New functions for 32-bit words and floats are added. The group of 'update' (burn only different bytes) functions is added. A set of Avr-libc bugs are fixed. - Added support for XMEGA architectures. - The Postscript documentation build has been removed in favour of building only the PDF (and HTML and man page) versions. PDF offers the same printing quality as postscript at a smaller file size. This also works around a bug in doxygen 1.5.7 where it appears to be no longer possible to set GENERATE_HTML = NO. - A sleeping BOD API was added to . This allows you to disable the Brown Out Detector (BOD) before going to sleep, thereby reducing power even further. - The note about signbit() implementation is removed from documenatation. The reason is that the GCC can replace it with inline code and the nonzero value is unpredictable in such case. - Signature API added in . - All functions are now placed in the .text.avr-libc section, and the floating point functions are placed in the .text.avr-libc.fplib section. This allows the user the ability to relocate all avr-libc routines to a different address using a custom linker script. - The port/pin assignments of the HD44780 LCD controller in the stdiodemo example can now be distributed across more than a single AVR port. The only remaining requirement is that all data bits are assigned to a single port in ascending order. - Added support for avrtiny10 architecture, to support the ATtiny10 Family. - Added new headerfile: ; currently contains _NOP() and _MemoryBarrier(). - The twidemo can now optionally address 24C32 and larger EEPROMs that require 16-bit word addressing. - Add a "memory barrier" to the cli() and sei() macros. * New devices supported: + ATxmega64D3 + ATxmega128D3 + ATxmega256D3 + ATxmega192A3 + ATxmega128A1 + ATxmega64A1 + ATmega32M1 + ATmega32C1 + ATmega32U4 + ATtiny167 + ATtiny13A + ATmega32U6 + AT90SCR100 + ATtiny87 + ATxmega32A4 + ATmega16M1 + ATmega64C1 + ATmega64M1 + ATA6289 + AT90PWM81 + ATmega128RFA1 + ATxmega32D4 + ATxmega16A4 + ATxmega16D4 + ATmega16U4 + ATmega8U2 + ATmega16U2 + ATmega32U2 + ATxmega192D3 + ATtiny2313A + ATtiny4313 + ATtiny24A + ATtiny44A + ATtiny261A + ATtiny461A + ATtiny861A + ATmega644PA + ATmega88PA + ATmega16A + ATmega64HVE + ATmega169PA + ATmega649P + ATmega324PA + ATmega16HVA2 + ATmega16HVB + ATmega48A + ATmega88A + ATmega168A + ATmega328 + ATmega164A + ATmega324A + ATmega644A + ATmega165A + ATmega169A + ATmega645A + ATmega6450A + ATmega649A + ATmega6490A + ATmega6490P + ATmega645P + ATmega6450P + ATmega329PA + ATxmega128A1U + ATxmega64A1U + ATtiny4 + ATtiny5 + ATtiny9 + ATtiny10 + ATtiny20 + ATtiny40 + ATtiny84A + ATmega325A + ATmega3250A + ATmega329A + ATmega3290A + M3000 * Optimized functions: eeprom_read_block eeprom_read_dword eeprom_read_word eeprom_write_block eeprom_write_dword eeprom_write_word strtod setjmp sqrt (and callers: acos, asin and hypot) sin, cos, tan: minor in space strlcat, strlcat_P strlcpy, strlcpy_P strtok, strtok_r * Contributed Patches: [#6194] Twitest updated to handle larger EEPROM devices [#6352] Far pointer library [#6500] Reentrant code faq [#6517] Pgmspace with float support [#6555] malloc improvement [#6649] sqrt.S in libm changes [#6690] Shorten calculation of dallas 1-wire crc [#6718] Optimize the EEPROM functions [#6720] FAQ update. Add EEPROM section, baud rate section. Correct spelling. [#6791] Minor fixes to stdio.h documentation [#6878] eewr_byte.S update for patch #6718 [#6891] Add XMega software reset to the FAQ section on software reset [#6895] Improved malloc behaviour when expanding used area [#6897] Allow to be used with assembler source * New functions: cbrt eeprom_read_dword eeprom_read_float eeprom_update_block eeprom_update_byte eeprom_update_dword eeprom_update_float eeprom_update_word eeprom_write_dword eeprom_write_float memccpy_P strdup strtok strtok_P strtok_rP strlen_PF strnlen_PF memcpy_PF strcpy_PF strncpy_PF strcat_PF strlcat_PF strncat_PF strcmp_PF strncmp_PF strcasecmp_PF strncasecmp_PF strstr_PF strlcpy_PF memcmp_PF *** Changes in avr-libc-1.6.0: * Main changes from avr-libc 1.4 to 1.6: + The fplib/math library is completely rewritten. Now features of the IEEE 754 standard are supported all: negative zero, subnormals, Infs and NaNs. It concerns both to base operations (arithmetic, comparison...), and to all functions. Speed of performance is increased, sometimes considerably. A number of mistakes (not reflected in the Bugs) which led severe losses of accuracy for some arguments is corrected. A number of new functions is added. It is necessary to note, that the new library concedes old under the charge of flash memory a little. Incompatibilities: - Conversion from float to long (make similar to GCC/x86): in case if overflow was or if input is NaN return 0x80000000 for signed result and return 0 for unsigned result. Negative input (not too big in absolute value) is permissible for cast to unsigned long, for example: (unsigned long)(-1.0) returns ULONG_MAX. - The signbit() function: return 1 as nonzero value (make similar to builtin GCC). - Make frexp() similar to GCC/x86 in case of nonfinite arg: write 0 by exponent pointer. Early Avr-libc's frexp() skips exponent storing in this case. Make the NULL a legal address to skip a storing. + Functions of numbers to ascii conversion are completely rewritten: dtostre(), dtostrf() and printf() family. They more do not use float point operations. Speed of int/float to ascii has increased in some times. For printf() the stack usage is reduced. + Test suite is added to the Avr-libc project. + A few new util's headers: util/atomic.h, util/setbaud.h . * Bugs fixed: [no-id] iscntrl() return true for some values from 0x80 to 0xff. [no-id] Fix the examples installation for non-doc builds. [no-id] Fix the spelling of the OCR1A/B registers in ATtinyX4 devices. [no-id] LED1/2 don't work in the largedemo on an ATmega16. [no-id] Not defined SPM_PAGESIZE for ATtinyX4/X5/X61 and ATtiny2313 devices. [no-id] Typo in iomxx0_1.h: PRUSART3. [no-id] Make include/avr/sfr_defs.h -Wundef safe. [no-id] Make include/avr/eeprom.h -Wundef safe. [no-id] Fix the timing of the HD44780 driver in the stdiodemo. [no-id] Fix the sleep mode definitions for the ATtiny2313. [no-id] Exclude 64-bit types for -mint8. [no-id] Make documentation build work with doxygen 1.5.x [#1929] -Inf not detected [#11511] NaN not generated correctly by division library [#11820] dtostre: wrong output with percision =3 [#13330] NaN is recognized not always [#15161] util/delay.h misses inline keyword (regression) [#15193] incorrect definition of IVSEL bit in MCUCR register [#15266] Function ldexp incorrectly processes overflow and underflow cases. [#15494] Compile warning and errors if compiler flag -Wundef flag specified [#15512] Bootloader macros not interrupt safe. [#15519] AT90CAN* processors incorrectly identified as "AT90S family" [#15522] Typo in iotn2313.h vector table [#15559] Wrong macro for boot_page_write(address) and ATmega128 [#15574] unneeded compatibility break [#15595] GPIOR0 misspelled for ATtiny25/45/85 [#15732] interrupt.h: ISR() incompatibility with gcc 3.4.5 [#15890] missing /devtools/gen-avr-lib-tree.sh [#16039] Names in Pxy (i.e. PA0) style of ports pins for some devices are not defined. [#16125] HD44780 data bit assignment restrictive [#16260] _crc16_update lacks C equivalent [#16411] Add the 'used' attribute to all interrupt service routine macros. [#16434] EMPTY_INTERRUPT has no misspelled vector checking [#16441] eeprom.h should use __asm__ [#16868] depricated.h: outp() arguments order misprint [#17068] wdt.h file: __AVR_ATmeg324P__ spelling mistake [#17470] Add API for CLKPR register. [#17551] Update documentation to point to issues with gcc4.1 [#17591] /avr-libc/libm/fplib/fp_split.S error return will fail for 3-Byte PC devices [#17608] Add ISR_ALIAS() to avr/interrupt.h [#18115] online documentation typo/bug avr/boot.h [#18373] Bugs in Inline ASM documentacion [#18385] SPM_PAGESIZE wrong value for ATmega164p and ATmega324p [#18509] strtod.S crashes due to stack problem with atmega 2560 [#18662] rand() keeps returning the same value if seeded with 0 [#18686] AT90USB**** devices are absent in interrupt-verctor-names table [#18688] vfscanf and vfprintf don't use malloc [#18726] the dtostrf function description is missing in AVR-Libc's webpage [#18903] ATmega644 register definitions for SPI and PRR (datasheet vs. iom*.h) [#18915] PWM1X Bit missing for ATtiny261/461/861 [#18964] USART definitions *wrong* in iocanxx.h [#18994] minor optimization possible to stdlib functions isspace(), isprint(), and islower() [#19009] Make issue a warning when optimizations are turned off [#19050] gcrt1.S should call main rather than jumping to it [#19060] PCMSKx registers transposed in header for attinyX61 [#19445] _malloc_heap_end does not follow _heap_end on m2561 [#19495] documentation: fix inclusion of cli and sei macros [#19496] Add documentation: how to build toolchain for Windows. [#19650] avr-libc: wrong named bit in SFR of AT90PWMx [#19666] AT90PWMx: Another patch for the include file (missing SFR) [#19669] Need function to read signature row [#19686] alloc declaration missing [#19841] Error building 1.4 HEAD: undefined reference to 'exit' [#20248] FAQ#3: clarify which registers are safe to be used [#20276] power.h missing ATmega644Ppower_XXX_[en/dis]able() macros [#20435] Bit name definitions for AT90PWM3 [#20530] Bug in sample code for early wdt disable [#20650] Missing description of AVR specific C-preprocessor macros [#20682] Bad bit name in avr/io2313.h - Sugestion [#20843] Mega 2561 library [#21174] assembly error with targets at90s1200, attiny11, attiny12, and attiny28 [#21183] Fix Program Space example code. [#21204] iotnx61.h PRR bits incorrect [#21228] Missing 3rd clause in BSD license in documentation pages [#21299] Duplicate register address in iotn48.h. [#21411] Typographical error in 'iotn13.h' [#21432] Incorrect timer interrupt handler names for ATtiny45 [#21434] Bit name definitions for AT90CANxxx [#21444] Undocument -minit-stack [#21484] Documentation build for avr/version.h does not susbstitute autoconf macros [#21749] AT90PWM316: _VECTORS_SIZE should be 128 [#21691] iomx8.h-> IVSEL and IVCE should not be available for ATmega48 [#21743] AT90PWM316 missing PSOC1 bit definitions [#21626] Incorrect Bit Definition for ADC14 and ADC15 Digital Input Disable [#21521] incorrect bit definitions in iotnx61.h [#21840] RAMEND wrong for ATmega48P/88P/168P * Other changes: - New Power Management API in . This provides C language macros to manipulate the Power Reduction Register(s) and the System Clock Prescaler register across multiple processors. [patch #4611] sleep.h sleep_mode() not interrupt safe - The simple demo has been modernized a bit. Documentation now generally refers to the ATmega8 rather than the AT90S2313, and the #ifdef spaghetti has been moved out into iocompat.h. - A new demo project ("largedemo") has been added. It extends the simple demo by adding some controls, and thereby touches a good number of avr-libc concepts. It has originally been written for the ATmega16, but can also be run on an ATmega8 or a member of the ATmegaX8 family, as well as on an ATtiny2313. - Another demo project ("stdiodemo") has been added. It demonstrates the setup of the standard IO facilities using a practical small application. - The demo projects now install their source code as part of the documentation tree. - The simple demo has been ported to ATmega8515, ATmega8535, ATmega164P, ATmega165, ATmega169, ATmega324P, ATmega325, ATmega3250, ATmega329, ATmega3290, ATmega640, ATmega644, ATmega644P, ATmega645, ATmega6450, ATmega649, ATmega6490, ATmega1280, ATmega1281, ATtiny2313, ATtiny24, ATtiny25, ATtiny26, ATtiny261, ATtiny44, ATtiny45, ATtiny461, ATtiny84, ATtiny85, ATtiny861. - More overhaul of the demo documentation, don't use the "squid" cable for the largedemo as it is not part of the STK500. - Integrate a copy of the license file into the documentation. - Include an alphabetical index of all globals (functions, macros, types, variables) into the documentation. - Added 'avr25' architecture. Now 'MOVW' and 'LPM Rx, Z[+]' instructions supported for AT86RF401, ATtiny13, ATtiny2313, ATtiny24, ATtiny25, ATtiny261, ATtiny44, ATtiny45, ATtiny461, ATtiny84, ATtiny85 and ATtiny861 devices. GCC 4.2 or above is necessary to use this. - Add the benchmark page. [patch #5756] New atomic.h header file (added as ) [patch #5343] Add a util/setbaud.h "helper" file [patch #6236] Improving _delay_us and _delay_ms [patch #5644] New interrupt.h header file * New devices supported: + ATtiny24 + ATtiny261 + ATtiny44 + ATtiny461 + ATtiny84 + ATtiny861 + ATmega406 + ATmega169 Rev. F + AT90USB82 + AT90USB162 + AT90USB646 + AT90USB647 + AT90USB1286 + AT90USB1287 + ATmega48P + ATmega88P + ATmega164P (renamed from ATmega164) + ATmega168P + ATmega324P (renamed from ATmega324) + ATmega328P + ATmega644P + ATmega1284P + ATmega165P + ATmega169P + ATmega2560 [patch #4461] + ATmega2561 [patch #4461] + ATmega325P + ATmega3250P + ATmega329P + ATmega3290P + AT90PWM1 + ATmega8HVA + ATmega16HVA + ATmega32HVB + AT90PWM216 + AT90PWM316 + ATtiny43U + ATtiny48 + ATtiny88 + AT90PWM2B + AT90PWM3B * New functions: strstr_P (Contributed by Werner Boellmann) round lround lrint * Optimized functions: dtostre *** Changes in avr-libc-1.4.0: * Major API changes: - The INTERRUPT() macro has been deprecated, and it will be removed in a future version. Use __attribute__((interrupt)) explicitly if this functionality is really needed. - A new ISR() macro has been added, and is now the preferred for to introduce an interrupt service routine. It is equivalent to the old SIGNAL() macro, which might become deprecated in a future version. - A new header file, has been established. Its purpose is to collect deprecated items from older versions of the library, starting out with the enable_external_int(), timer_enable_int(), and INTERRUPT() macros/functions, as well as the old obsoleted inp/outp/sbi/cbi macros. - A new include file subdirectory named "util/" has been created. The files , , , and have been moved into the new util/ subdirectory. - A new set of interrupt vector names has been added, closely matching the names given in the datasheet, and more compatible to other compilers available for the AVR platform. The table of interrupt vector names in the documentation is now automatically generated, and explicitly mentions the MCU type for each vector name. - The standard IO facilities API has been enhanced . The backend functions put and get that are passed to fdevopen() during the setup of a stream now take the stream itself as an additional argument. By defining the macro __STDIO_FDEVOPEN_COMPAT_12 before including , an fdevopen() function prototype will be declared that is backwards-compatible with avr-libc version 1.2 and before. . It is possible to tie user data to a stream using fdev_set_udata(), and to retrieve them using fdev_get_udata(). Together with the additional argument to the backend functions, these functions can now e.g. keep track of internal user state, or distinguish two different devices using the same backend function. . The get backend function can now return _FDEV_EOF to indicate an end-of-file condition, in addition to _FDEV_ERR for an error condition. This will affect the internal state that can be queried using the standard feof() and ferror() functions. . A new macro fdev_setup_stream() is provided to setup a user-supplied stream without the need to call fdevopen(), and thus without requiring malloc(). A similar macro FDEV_SETUP_STREAM() exists that can be used to initialized a FILE object. The floating-point implementations of vfscanf() and vfprintf() now allocate their conversion buffer on the stack, so they do not need malloc() anymore either. - An API has been added to track the library version number. See the documentation of the new header file . * Bugs fixed: [#3573] Make local symbols in .S files truely local [#12324] overview: boot_page_write_safe, etc. [#12333] Standard requires libstdc to define vprintf and vscanf [#12495] about Busy-wait delay loops(document) [#12496] about set_sleep_mode() and tiny26/tiny2313 [#12735] No support for AT94K devices in sleep.h [#12739] Gcc assumes that target libc provides ffs function [#12775] Possible Bug in sscanf on string end [#13340] Math lib documentation/lib mismatch [#13557] small typo in avr-libc-user-manual-1.2.3 [#14224] _delay_ms() not inlining if called more than once in a unit [#14241] 'eeprom_is_ready' is not compiled with ATmega48 [#14262] avr-libc documentation error about .init sections [#14266] use __extension__ in avr-libc header files [#14327] wdt_disable() missing a cli [#14378] EEPROM library d'not support at86rf401 device [#14380] configure/make work only in source directory [#14433] Improve documentation of [#14486] some macros from boot.h doesn't compile correctly [#14503] strnlen_P is wrong with classic AVRs [#14798] several IO registers definition issue in header files [#14852] fp pow function broken for negative x * Other changes: [patch #3592] speedup tanh function in libm [patch #3750] Allow passing user data to stdio fdevopen() get and put methods. (This is part of the API changes mentioned above.) [patch #3780] header [patch #3781] add dummy fflush() to [patch #3782] modernize [patch #3912] Fix ctype.S linker error due to asm branches out of range [patch #3925] Dallas iButton 8-bit CRC [patch #4087] C99 conformal headers stdint.h and inttypes.h [patch #4505] Unified interrupt vector names in header files [patch #4557] Adds to the fplib usage of MUL instruction in group avr4; avr5 devices [patch #4608] rpm spec file update [patch #4622] unify doc file location in rpms - Update the build system to recent versions of autoconf/automake; the old "doconf" and "domake" scripts are gone now, "reconf" has been renamed to "bootstrap". - Update the documentation system to doxygen >= 1.4.1. - Major overhaul of the documentation, new layout of the HTML pages, several clarifications and additions. - Add support for the following new devices (depending on the ability of the compiler/binutils to handle them): . AT90CAN32/64 . AT90PWM2(B)/3(B) . ATmega329/3290/649/6490 . ATtiny25/45/85 . ATmega164/324/644 . ATmega640/1280/1281 - The library is now compiled with -Os for avr3 and avr5 MCUs (i.e. for those with > 8 KB of ROM); used to be -O3 before. * New string functions. Contributed by Dmitry Xmelkov. ffs ffsl ffsll _FFS (macro) * Optimized functions. misc/itoa misc/ltoa misc/utoa misc/ultoa stdlib/longjmp string/memchr string/memccpy string/strchr string/strrchr string/strsep string/strstr *** Changes since avr-libc-1.2.4: * Bugs fixed: [no-id] EEPROM handling not working for AT90CAN128 ATmega48 ATmega88 ATmega165 ATmega168 ATmega169 ATmega325 ATmega3250 ATmega645 ATmega6450 [#12646] strtod returns error for valid input (patch#4137) [#13341] Remove ADHSM bit from header files. * Other improvements: [patch#4189] Document replacement for sbi/cbi instructions * boot.h: implement boot_lock_fuse_bits_get() plus macros for the respective addresses (low/high/ext fuse, lock bits) *** Changes since avr-libc-1.2.3: * Bugs fixed: [no-id] Work around a bug in gas that made the weak symbol __stack fixed inside gcrt1.S (since the assembler already inserted its value). [no-id] Modify the doxygen build system to cope with artefacts from recent versions of doxygen and (pdfelatex-based) LaTeX. [#12033] macros.inc need to be protected from multiple inclusion. [#12040] overview: sbi in FAQ [#12134] ADC register name definitions [#12422] Add new bit definitions for LCDCCR register in iom169.h. [#12448] Fix bit definition for SJW0 in iocan128.h [#12785] Fix documenation for log10() function in math.h. [#12955] Signal name misprints: SIG_COMPERATOR in iom169.h, SIG_EPROM_READY in iotn26.h [#12993] Signal "__EICR" redefined warning ATmega8 [#13290] avr/io.h EEAR def is flawed for the Mega48 [#13327] Fix bit definition for UCSZ02 in iom325.h, iom3250.h, iom645.h, iom6450.h [#13678] The _wdt_write(value) macro in wdt.h doesn't work with the ATmega325.(also with ATmega3250, ATmega645, ATmega6450, ATmega165). * demo.c extended for ATmega16 *** Changes since avr-libc-1.2.2: * Bugs fixed: [#11987] sscanf parsing problem : leading zero ignored in %u *** Changes since avr-libc-1.2.1: * Bugs fixed: [#11805] Fix call to __fp_cosinus in sin(). [#11817] Replace SYSCLK with F_CPU in twitest example. [#11868] realloc doesn't work correctly on block at end of freelist when growing [#11898] Change optimisation level for building printf libraries to -Os. *** Changes since avr-libc-1.2.0: * Bugs fixed: [no-id] Prefix all internal global symbols in libm with __fp_ so they do not collide with the application namespace. [#4101] setjmp/longjmp destroy changes in global registers. [#11479] Add missing pin definitions for iotn16.h. [#11486] Put the port bit defintions back in for mega16. [#11494] strtol() return wrong value in the underflow case [#11505] Remove doxygen comment about the deprecated inp/outp items. [#11510] Abstract the change enable bit in wdt.h for mega32. [#11522] Rewrite wdt_disable() to match datasheet algorithm. [#11684] realloc overwrites first to bytes of memory block when shrinking [patch #3618] Optimization strtol(), a little (related to bug #11494). [#11732] Update doc/examples/progmem.c to use the latest API. * Extend stdio and pmstring APIs: Implement patch #3516: printf: Handling of argument strings from program memory The %S format can now be used to print strings that are located in program-space memory (aka. ROM). As a prerequisite for this, the function strnlen_P() has been added which is similar to strnlen() except that it takes a pointer to a program-space string. *** Changes in avr-libc-1.2: * Bugs fixed: [no-id] Fix TICIE1 value in usb header files. [no-id] Fix bug introduced in fix for bug #7802 (missing parens). [no-id] Move ATtiny2313 and ATtiny13 from avr4 to avr2 (by now). [#2143] malloc() routines chunk smaller than requested [#5454] Inline functions results in undefined reference when optimize level 0 is used. [#5799] error(?) in iom162.h [#2233] Documentation issues with inline asm [#6352] Sleep mode for ATmega162, ATmega161, and ATmega8515 [#7469] "Problem" by using the library function "boot_lock_bits_set" [#7556] printf and friends improperly handle non-null terminated strings when a %s argument has a precision. [#7802] vfscanf problem with unsigned long (patch #2554) [#7989] dtostrf() destroys string pointer registers? [#8119] _wdt_write macro in wdt.h doesn't work with ATmega169 [#8391] Fuse mask in boot.h wrong? NOTE: boot_lock_bits_set() was broken. Please see the new documentation for examples of how the new version works. [#8452] some SFR and bit names in iom169.h are incorrect NOTE: Where possible, the old names are retained to avoid breaking existing code, but the OCR1A and OCR1B names where just plain wrong so they have been changed and the incorrect names (OCRA1 and OCRB1) are undefined. [#8649] sfr_defs.h: missed _SFR_BYTE() in bit_is_set/clear [#9345] Zero-Padding on vfprintf [#10150] Update release versions compatible with avr-libc and instructions. [#10489] Sleep mode for atmega48/88/168 family [#10733] Fix bit identifer ADFR to ADATE in mega64. [#10828] Fix licenses on files to have same BSD license. [#11242] Add the EEARH register definition for the mega48. [#11275] fdevopen() should document its use of malloc() [#11315] Add USART* signal names to match datasheet for mega32 and mega16. [#11405] Add USART* signal names to match datasheet for mega128. [#11418] Add PRR register and bit definitions for mega169. [#11425] sleep.h missing semicolon * Remove deprecated items: + obsolete headers from the base include directory (moved to the avr/ subdirectory long ago) + deprecated macros and functions from . (eeprom_rb, eeprom_rw, eeprom_wb), . (cbi, sbi, inb, outb, inw, outw, inp, outp, BV), . (PRG_RDB). + . removed completely. * Moved header files: + moved to + moved to * New devices supported: + ATmega165 + ATmega325 + ATmega3250 + ATmega645 + ATmega6450 + ATmega48 + ATmega88 + ATmega168 + ATtiny13 + ATtiny2313 + AT90CAN128 * Pin names for ports are now consistent for all devices. * dtostrf() now uses movw where possible * realloc() has been implemented. * Extend pgmspace API. The pgmspace API has had the following macros added to allow accessing of unsigned 32-bit values: pgm_read_dword_near pgm_read_dword_far pgm_read_dword * Change boot API. The boot API internals have changed such that it is not compatible with the 1.0.x API. These macros have been changed so that they no longer wait for SPM and EEPROM operations to complete. It turns out that doing those checks all the time is not needed and tends to bloat the code. Removing the checks allows you to write more compact code (see the example in avr/boot.h). boot_page_fill boot_page_erase boot_page_write boot_rww_enable boot_lock_bits_set If you want the old behaviour (1.0.x compatible), use these new macros: boot_page_fill_safe boot_page_erase_safe boot_page_write_safe boot_rww_enable_safe boot_lock_bits_set_safe * Extend eeprom API. New macro: eeprom_busy_wait * Extend crc16 API. New functions: _crc_xmodem_update _crc_ccitt_update * Extend stdio API. New functions: vfprintf_P vfscanf_P vsprintf vsprintf_P vsnprintf vsnprintf_P * Extend malloc API. Implement realloc(). * Extend delay API (). Implement inline functions for specifying delays in microseconds, or milliseconds directly (based on the macro F_CPU specifying the CPU clock frequency). * Documentation changes: + Use newer Doxygen. + Many fixes and added documentation. + Unix-style man pages are generated now when doc generation has been enabled in ./configure * Optimize slightly strtol and strtoul functions. * Unified copyright. All of the avr-libc files are now distributed under a single license. All of the authors of the files agreed to this step. The new license is a 3-clause simplified ``BSD-style'' license which is believed to be fully compatible with the GPL on one hand, yet imposes as minimal restrictions as possible for any kind of commercial use in applications based on avr-libc. To build the documentation, doxygen-1.3.4 or newer is strongly recommended. *** Changes in avr-libc-1.0: * Move source to cvs repositiory at http://savannah.gnu.org/projects/avr-libc Anonymous cvs access to the source is now available. There is also a mailing list set up for discussion of development of avr-libc. * License changes. All the files in the project now are covered by a modified BSD license. This allows royalty free use of the library in commerical products. All of the public domain files in the project have been switched to the new license and copyright given to the contributors of the files. There were some files taken from GNU GPL'd projects which were removed from avr-libc to simplify the licensing. The removed files only supplied alternate implementations, so nothing was lost by their removal. * Requires latest binutils and gcc Marek did some fairly major work with binutils and gcc to make adding support for new devices easier. His changes in those tools required changes to avr-libc which make it incompatible with older versions of binutils and gcc. Gcc versions >= 3.3 and binutils versions >= 2.13 are required. * New malloc implementation. Joerg Wunsch has supplied an improved malloc implementation which is less prone to fragmentation. * Documentation! Joerg Wunsch and Ted Roth and have been working on using the doxygen program to embed documentation comments into source code. Additionally, Harald Kipp's inline asm cookbook and Rich Neswold's Avr Tools document have been merged into the user manual. The goal is to have a single place for all the documentation a user would need to get started developing for AVR microcontrollers using the GNU development tool chain. The latest documentation is available online at http://www.freesoftware.fsf.org/avr-libc/ * I/O registers accessible directly in C expressions You can now do this in your code: PORTA |= 0x02; See the "Special Function Registers" documentation for details. This method is preferred over the use of the deprecated inp(), inb(), inw(), outp(), outb() and outw() functions. * New devices supported mega128 mega169 mega16 mega32 mega64 [untested] mega8515 [untested] mega8535 [untested] tiny26 76c711 43usb320 43usb355 86rf401 * Improved trigonometrical functions: Reiner Patommel provided complete rewrites for asin(), atan() and atan2() that feature a better (for some argument ranges even much better) accuracy than the previous versions. Note that since acos() uses asin(), it also benefits from this. * Incompatibilities with previous version. The arguments for outb()/outw() have been reversed. (value,port) -> (port,value) * New pgmspace.h API. Changed function names and added new functions to read the Program Space FLASH. Added new functions to read 16-bit (word) values. The new API should also clear up problems with reading data from devices with > 64K of FLASH. The API now includes: pgm_read_byte (maps to the *_near function below) pgm_read_word (maps to the *_near function below) pgm_read_byte_near pgm_read_word_near pgm_read_byte_far pgm_read_word_far * New bootloader support API. #include This provides bootloader support functions to those processors that have builtin bootloader support. * inb / outb / inw / outw / cbi / sbi macros are deprecated. * New string functions and optimized string functions. strlcpy (optimized) strlcat (optimized) strsep (new) strtok_r (new) strlcat_P (new) strlcpy_P (new) strncat_P (new) Contributed by Reiner Patommel with some work on strlcpy, strlcat by Eric Weddington. * New eeprom functions by Artur Lipowski eeprom_write_word eeprom_write_block *** Changes up to avr-libc-20020203: See the ChangeLog file up to 2002-02-03 for details. avr-libc-1.8.0.orig/AUTHORS0000644000000000000000000000123411732702554012122 0ustar Project Administrators ---------------------- Marek Michalkiewicz Joerg Wunsch Project Administrator alumni ---------------------------- Theodore A. Roth Authors (in Last Name alphabetical order) ----------------------------------------- Pieter Conradie Ruud v Gessel Keith Gudger Bjoern Haase Steinar Haugen Peter Jansen Reinhard Jessich Artur Lipowski Marek Michalkiewicz Colin O'Flynn Bob Paddock Andrey Pashchenko Reiner Patommel Alexander Popov Michael Rickman Theodore A. Roth Juergen Schilling Philip Soeberg Anatoly Sokolov Nils Kristian Strom Michael Stumpf Helmut Wallner Eric B. Weddington Joerg Wunsch Dmitry Xmelkov University of California, Berkeley avr-libc-1.8.0.orig/devtools/0000755000000000000000000000000011732702554012711 5ustar avr-libc-1.8.0.orig/devtools/cr_check.py0000755000000000000000000000667611732702554015046 0ustar #! /usr/bin/env python # # Copyright (c) 2004 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: cr_check.py 605 2004-11-02 16:01:29Z troth $ # # # Use this script from the toplevel of the avr-libc tree to find files with # bogus carriage returns. # import os.path, fnmatch def listFiles (root='.', match=['*'], ignore=[], recurse=1, return_folders=0): class Bunch: def __init__ (self, **kw): self.__dict__.update (kw) arg = Bunch (recurse=recurse, match_list=match, ignore_list=ignore, return_folders=return_folders, results=[]) def visit (arg, dirname, files): # Append to arg.results all relevant files (and perhaps folders) for name in files: fullname = os.path.normpath (os.path.join (dirname, name)) if arg.return_folders or os.path.isfile (fullname): for match in arg.match_list: if fnmatch.fnmatch (name, match): add = 1 for ignore in arg.ignore_list: if fnmatch.fnmatch (name, ignore): add = 0 if add: arg.results.append (fullname) break # Block recursion if recursion was disallowed if not arg.recurse: files[:]=[] os.path.walk (root, visit, arg) return arg.results def cr_check (file): ln = 1 f = open (file).readlines () for l in f: if '\r' in l: print '%s:%d: Found CR.' % (file, ln) ln += 1 def check_cvs_dir (entry): f = open (entry).readlines () base_dir = os.path.dirname (os.path.dirname (entry)) for l in f: if l[0] == 'D': continue else: file = l.split ('/')[1] if base_dir: file = base_dir+'/'+file cr_check (file) if __name__ == '__main__': for file in listFiles (match=['*Entries*']): check_cvs_dir (file) avr-libc-1.8.0.orig/devtools/Makefile.in0000644000000000000000000002602411732702554014762 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2006, Anatoly Sokolov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 2166 2010-06-13 13:14:47Z joerg_wunsch $ # VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ subdir = devtools DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = SOURCES = DIST_SOURCES = DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = @ACLOCAL@ AMTAR = @AMTAR@ AR = @AR@ AS = @AS@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AVR_LIBC_MAJOR = @AVR_LIBC_MAJOR@ AVR_LIBC_MINOR = @AVR_LIBC_MINOR@ AVR_LIBC_RELDATE = @AVR_LIBC_RELDATE@ AVR_LIBC_REVISION = @AVR_LIBC_REVISION@ AVR_LIBC_USER_MANUAL = @AVR_LIBC_USER_MANUAL@ AVR_LIBC_VERSION = @AVR_LIBC_VERSION@ AVR_LIBC_VERSION_NUMERIC = @AVR_LIBC_VERSION_NUMERIC@ AWK = @AWK@ CC = @CC@ CCAS = @CCAS@ CCASDEPMODE = @CCASDEPMODE@ CCASFLAGS = @CCASFLAGS@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ CPPFLAGS = @CPPFLAGS@ CYGPATH_W = @CYGPATH_W@ DEFS = @DEFS@ DEPDIR = @DEPDIR@ DOCSDIR = @DOCSDIR@ DOC_INST_DIR = @DOC_INST_DIR@ ECHO_C = @ECHO_C@ ECHO_N = @ECHO_N@ ECHO_T = @ECHO_T@ EXEEXT = @EXEEXT@ FNO_JUMP_TABLES = @FNO_JUMP_TABLES@ HAS_DELAY_CYCLES = @HAS_DELAY_CYCLES@ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_DOX_HTML = @INSTALL_DOX_HTML@ INSTALL_DOX_MAN = @INSTALL_DOX_MAN@ INSTALL_DOX_PDF = @INSTALL_DOX_PDF@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_SCRIPT = @INSTALL_SCRIPT@ INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ LDFLAGS = @LDFLAGS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAKEINFO = @MAKEINFO@ MKDIR_P = @MKDIR_P@ OBJEXT = @OBJEXT@ PACKAGE = @PACKAGE@ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ PACKAGE_NAME = @PACKAGE_NAME@ PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_URL = @PACKAGE_URL@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ PNGTOPNM = @PNGTOPNM@ PNMTOPNG = @PNMTOPNG@ RANLIB = @RANLIB@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ TARGET_DOX_HTML = @TARGET_DOX_HTML@ TARGET_DOX_PDF = @TARGET_DOX_PDF@ VERSION = @VERSION@ abs_builddir = @abs_builddir@ abs_srcdir = @abs_srcdir@ abs_top_builddir = @abs_top_builddir@ abs_top_srcdir = @abs_top_srcdir@ ac_ct_CC = @ac_ct_CC@ am__include = @am__include@ am__leading_dot = @am__leading_dot@ am__quote = @am__quote@ am__tar = @am__tar@ am__untar = @am__untar@ bindir = @bindir@ build = @build@ build_alias = @build_alias@ build_cpu = @build_cpu@ build_os = @build_os@ build_vendor = @build_vendor@ builddir = @builddir@ datadir = @datadir@ datarootdir = @datarootdir@ docdir = @docdir@ dvidir = @dvidir@ exec_prefix = @exec_prefix@ host = @host@ host_alias = @host_alias@ host_cpu = @host_cpu@ host_os = @host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ EXTRA_DIST = \ Architecture.am \ Avr.am \ Device.am \ Lib.am \ cr_check.py \ gen-avr-lib-tree.sh \ make-binary-dist.sh all: all-am .SUFFIXES: $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(am__configure_deps) @for dep in $?; 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IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: make-binary-dist.sh 897 2005-10-17 19:43:21Z joerg_wunsch $ # # Build a binary distribution archive. # # Assumes a bootstrapped source tree to be present in ${topdir}. #set -x # Optional argument to script $1: top-level source directory to # compile from. builddir=$(pwd) topdir=${1:-.} topdir=$( (cd $topdir && pwd) ) # If ${MAKE} is not set, and a gmake program is available, use gmake # (GNU make). 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IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # SUBDIRS = lib avr-libc-1.8.0.orig/devtools/Device.am0000644000000000000000000000502611732702554014432 0ustar # Copyright (c) 2004, Theodore A. Roth # Copyright (c) 2005, 2008 Anatoly Sokolov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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We will look for the # the AUTHORS file in the current dir and the parent. After that, we complain # and fatal error out. # Define the special flags for special sub-targets. CFLAGS_SPACE="-mcall-prologues -Os" CFLAGS_BIG_MEMORY='-Os $(FNO_JUMP_TABLES)' CFLAGS_SPEED="-Os" ASFLAGS_SPEED="-DOPTIMIZE_SPEED" AVR12_DEV_INFO="\ at90s1200:crts1200.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny11:crttn11.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny12:crttn12.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny13:crttn13.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny15:crttn15.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny2313:crttn2313.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny28:crttn28.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90s2313:crts2313.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90s2323:crts2323.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90s2333:crts2333.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90s2343:crts2343.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90s4433:crts4433.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90s4414:crts4414.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90s4434:crts4434.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90s8515:crts8515.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90s8535:crts8535.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90c8534:crtc8534.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny22:crttn22.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny26:crttn26.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at86rf401:crt86401.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny25:crttn25.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny45:crttn45.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny85:crttn85.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny24:crttn24.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny44:crttn44.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny84:crttn84.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny261:crttn261.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny461:crttn461.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny861:crttn861.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " AVR25_DEV_INFO="\ at86rf401:crt86401.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ ata6289:crta6289.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny13:crttn13.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny13a:crttn13a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny2313:crttn2313.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny2313a:crttn2313a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny24:crttn24.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny24a:crttn24a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny25:crttn25.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny261:crttn261.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny261a:crttn261a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny4313:crttn4313.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny43u:crttn43u.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny44:crttn44.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny44a:crttn44a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny45:crttn45.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny461:crttn461.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny461a:crttn461a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny48:crttn48.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny84:crttn84.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny84a:crttn84a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny85:crttn85.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny861:crttn861.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny861a:crttn861a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny87:crttn87.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny88:crttn88.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " AVR3_DEV_INFO="\ atmega103:crtm103.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at43usb320:crt43320.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at43usb355:crt43355.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at76c711:crt76711.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90usb82:crtusb82.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90usb162:crtusb162.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " AVR31_DEV_INFO="\ atmega103:crtm103.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at43usb320:crt43320.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " AVR35_DEV_INFO="\ at90usb82:crtusb82.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90usb162:crtusb162.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega8u2:crtm8u2.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16u2:crtm16u2.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32u2:crtm32u2.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny167:crttn167.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " AVR4_DEV_INFO="\ atmega48:crtm48.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega48a:crtm48a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega48p:crtm48p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega8:crtm8.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega88:crtm88.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega88a:crtm88a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega88p:crtm88p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega88pa:crtm88pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega8515:crtm8515.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega8535:crtm8535.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega8hva:crtm8hva.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm1:crt90pwm1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm2:crt90pwm2.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm2b:crt90pwm2b.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm3:crt90pwm3.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm3b:crt90pwm3b.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm81:crt90pwm81.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " AVR5_DEV_INFO="\ at90can32:crtcan32.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90can64:crtcan64.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90can128:crtcan128.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm216:crt90pwm216.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm316:crt90pwm316.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90scr100:crt90scr100.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90usb646:crtusb646.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90usb647:crtusb647.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90usb1286:crtusb1286.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90usb1287:crtusb1287.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at94k:crtat94k.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16:crtm16.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16a:crtm16a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega161:crtm161.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega162:crtm162.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega163:crtm163.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega164a:crtm164a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega164p:crtm164p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega165:crtm165.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega165a:crtm165a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega165p:crtm165p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega168:crtm168.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega168a:crtm168a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega168p:crtm168p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega169:crtm169.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega169a:crtm169a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega169p:crtm169p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega169pa:crtm169pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16hva:crtm16hva.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16hva2:crtm16hva2.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16hvb:crtm16hvb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16hvbrevb:crtm16hvbrevb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16m1:crtm16m1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16u4:crtm16u4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32:crtm32.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega323:crtm323.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega324a:crtm324a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega324p:crtm324p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega324pa:crtm324pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega325:crtm325.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega325a:crtm325a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega325p:crtm325p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega3250:crtm3250.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega3250a:crtm3250a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega3250p:crtm3250p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega328:crtm328.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega328p:crtm328p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega329:crtm329.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega329a:crtm329a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega329p:crtm329p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega329pa:crtm329pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega3290:crtm3290.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega3290a:crtm3290a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega3290p:crtm3290p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32c1:crtm32c1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32hvb:crtm32hvb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32hvbrevb:crtm32hvbrevb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32m1:crtm32m1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32u4:crtm32u4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32u6:crtm32u6.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega406:crtm406.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega64:crtm64.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega640:crtm640.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega644:crtm644.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega644a:crtm644a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega644p:crtm644p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega644pa:crtm644pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega645:crtm645.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega645a:crtm645a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega645p:crtm645p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega6450:crtm6450.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega6450a:crtm6450a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega6450p:crtm6450p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega649:crtm649.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega649a:crtm649a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega649p:crtm649p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega6490:crtm6490.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega6490a:crtm6490a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega6490p:crtm6490p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega64c1:crtm64c1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega64hve:crtm64hve.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega64m1:crtm64m1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega128:crtm128.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega1280:crtm1280.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega1281:crtm1281.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega1284p:crtm1284p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega128rfa1:crtm128rfa1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ m3000:crtm3000.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " AVR51_DEV_INFO="\ atmega128:crtm128.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atmega1280:crtm1280.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atmega1281:crtm1281.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atmega1284p:crtm1284p.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atmega128rfa1:crtm128rfa1.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ at90can128:crtcan128.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ at90usb1286:crtusb1286.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ at90usb1287:crtusb1287.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS}\ " AVR6_DEV_INFO="\ atmega2560:crtm2560.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atmega2561:crtm2561.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS}\ " AVRXMEGA2_DEV_INFO="\ atxmega16a4:crtx16a4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atxmega16d4:crtx16d4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atxmega32a4:crtx32a4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atxmega32d4:crtx32d4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " AVRXMEGA4_DEV_INFO="\ atxmega64a3:crtx64a3.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atxmega64d3:crtx64d3.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS}\ " AVRXMEGA5_DEV_INFO="\ atxmega64a1:crtx64a1.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atxmega64a1u:crtx64a1u.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS}\ " AVRXMEGA6_DEV_INFO="\ atxmega128a3:crtx128a3.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atxmega128d3:crtx128d3.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atxmega192a3:crtx192a3.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atxmega192d3:crtx192d3.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atxmega256a3:crtx256a3.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atxmega256a3b:crtx256a3b.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atxmega256d3:crtx256d3.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS}\ " AVRXMEGA7_DEV_INFO="\ atxmega128a1:crtx128a1.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ atxmega128a1u:crtx128a1u.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS}\ " AVRTINY10_DEV_INFO="\ attiny4:crttn4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny5:crttn5.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny9:crttn9.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny10:crttn10.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny20:crttn20.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny40:crttn40.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " LIB_DEFS="-D__COMPILING_AVR_LIBC__" AVR_ARH_INFO="\ avr2:AVR12_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ avr25:AVR25_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ avr3:AVR3_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ avr31:AVR31_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ avr35:AVR35_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ avr4:AVR4_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ avr5:AVR5_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ avr51:AVR51_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ avr6:AVR6_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ avrxmega2:AVRXMEGA2_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ avrxmega4:AVRXMEGA4_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ avrxmega5:AVRXMEGA5_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ avrxmega6:AVRXMEGA6_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ avrxmega7:AVRXMEGA7_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ avrtiny10:AVRTINY10_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " echo "Generating source directories:" top_dir="UNKNOWN" if test -e AUTHORS then top_dir="$PWD" else cd .. if test -e AUTHORS then top_dir="$PWD" fi fi if test $top_dir = "UNKNOWN" then echo "Can't determine the top level source dir. Aborting." exit 1 fi test -d avr || mkdir avr test -d avr/lib || mkdir avr/lib cd avr/lib || exit 1 IFS=';' ARH_SUBDIRS="" for ath_lib in $AVR_ARH_INFO do arh=$(echo $ath_lib | cut -d ':' -f 1) dev_info=$(echo $ath_lib | cut -d ':' -f 2) lib_defs=$(echo $ath_lib | cut -d ':' -f 3) lib_cflags=$(echo $ath_lib | cut -d ':' -f 4) lib_asflags=$(echo $ath_lib | cut -d ':' -f 5) install_dir=$arh if [ $arh = avr2 ] then install_dir="" fi echo " avr/lib/$arh/" test -d $arh || mkdir $arh cd $arh || exit 1 DEV_SUBDIRS="" eval DEV_INFO=\"\$\{$dev_info\}\" for dev_crt in $DEV_INFO do dev=$(echo $dev_crt | cut -d ':' -f 1) crt=$(echo $dev_crt | cut -d ':' -f 2) crt_defs=$(echo $dev_crt | cut -d ':' -f 3) crt_cflags=$(echo $dev_crt | cut -d ':' -f 4) crt_asflags=$(echo $dev_crt | cut -d ':' -f 5) echo " avr/lib/$arh/$dev" test -d $dev || mkdir $dev cat $top_dir/devtools/Device.am > $dev/Makefile.am sed -e "s/<>/$dev/g" \ -e "s/<>/$crt/g" \ -e "s/<>/$crt_defs/g" \ -e "s/<>/$crt_cflags/g" \ -e "s/<>/$crt_asflags/g" \ -e "s/<>/$install_dir/g" $dev/Makefile.am \ > $dev/tempfile && mv -f $dev/tempfile $dev/Makefile.am DEV_SUBDIRS="$DEV_SUBDIRS $dev" done cat $top_dir/devtools/Architecture.am > Makefile.am sed -e "s/<>/$DEV_SUBDIRS/g" \ -e "s/<>/$arh/g" \ -e "s/<>/$lib_defs/g" \ -e "s/<>/$lib_cflags/g" \ -e "s/<>/$lib_asflags/g" \ -e "s/<>/$install_dir/g" Makefile.am \ > tempfile && mv -f tempfile Makefile.am # Find the first and the last lines of <> block. n1=`grep '^if[[:blank:]]+HAS_<>' -En Makefile.am \ | cut -d ':' -f 1` n2=`grep '^endif[[:blank:]]+#[[:blank:]]*<>' -En Makefile.am \ | cut -d ':' -f 1` # Before the <> block. head -n $(($n1 - 1)) Makefile.am > tempfile # Duplicate the <> block and substitute. for dev_crt in $DEV_INFO ; do dev=`echo $dev_crt | cut -d ':' -f 1` tail -n +$n1 Makefile.am \ | head -n $(($n2 - $n1 + 1)) \ | sed -e "s/<>/$dev/g" >> tempfile done # After the <> block. tail -n +$(($n2 + 1)) Makefile.am >> tempfile # Result. mv -f tempfile Makefile.am ARH_SUBDIRS="$ARH_SUBDIRS $arh" cd .. done cat $top_dir/devtools/Lib.am > Makefile.am sed -e "s/<>/$ARH_SUBDIRS/g" Makefile.am \ > tempfile && mv -f tempfile Makefile.am cd .. cat $top_dir/devtools/Avr.am > Makefile.am avr-libc-1.8.0.orig/devtools/Makefile.am0000644000000000000000000000333011732702554014744 0ustar # Copyright (c) 2006, Anatoly Sokolov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 2166 2010-06-13 13:14:47Z joerg_wunsch $ # EXTRA_DIST = \ Architecture.am \ Avr.am \ Device.am \ Lib.am \ cr_check.py \ gen-avr-lib-tree.sh \ make-binary-dist.sh avr-libc-1.8.0.orig/devtools/Architecture.am0000644000000000000000000000671311732702554015661 0ustar # Copyright (c) 2004, Theodore A. Roth # Copyright (c) 2005, 2008, 2009 Anatoly Sokolov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # SUBDIRS = <> AVR_TARGET = <> AVR_TARGET_DEFS = <> AVR_TARGET_CFLAGS = <> AVR_TARGET_ASFLAGS = <> AVR_INSTALL_DIR = <> VPATH = $(top_srcdir)/libc/stdlib:$(top_srcdir)/libc/pmstring:$(top_srcdir)/libc/string:$(top_srcdir)/libc/misc:$(top_srcdir)/libc/stdio:$(top_srcdir)/libm/fplib if HAS_<> AVRLIB_DEVLIST = if HAS_<> AVRLIB_DEVLIST += <> endif # <> AM_CPPFLAGS = -I$(top_srcdir)/common -I$(top_srcdir)/include -I$(top_builddir)/include AVRLIB_CFLAGS = -g -Wall -W -Wstrict-prototypes -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_CFLAGS) AVRLIB_ASFLAGS = -x assembler-with-cpp -Wa,-gstabs -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_ASFLAGS) AM_CFLAGS = $(AVRLIB_CFLAGS) AM_CCASFLAGS = $(AM_CPPFLAGS) $(AVRLIB_ASFLAGS) __install_dir = $(prefix)/avr/lib/$(AVR_INSTALL_DIR) avrdir = $(__install_dir) avrlibdir = $(__install_dir) avr_LIBRARIES = \ libc.a \ libprintf_min.a \ libprintf_flt.a \ libscanf_min.a \ libscanf_flt.a \ libm.a include $(top_srcdir)/libc/stdlib/Rules.am include $(top_srcdir)/libc/pmstring/Rules.am include $(top_srcdir)/libc/string/Rules.am include $(top_srcdir)/libc/misc/Rules.am include $(top_srcdir)/libc/stdio/Rules.am include $(top_srcdir)/libm/fplib/Rules.am nodist_libc_a_SOURCES = \ $(stdlib_a_c_sources) \ $(stdlib_a_asm_sources) \ $(pmstring_a_c_sources) \ $(pmstring_a_asm_sources) \ $(string_a_c_sources) \ $(string_a_asm_sources) \ $(misc_a_c_sources) \ $(misc_a_asm_sources) \ $(stdio_a_c_sources) \ $(stdio_a_asm_sources) \ $(libm_a_c_sources) \ $(libm_a_asm_sources) nodist_libm_a_SOURCES = \ $(libm_a_c_sources) \ $(libm_a_asm_sources) libc_a_LIBADD = \ $(stdio_a_libadd) \ $(misc_a_libadd) libc_a_DEPENDENCIES = \ $(stdio_a_libadd) \ $(misc_a_libadd) else echo all distdir install installdirs clean distclean uninstall check: endifavr-libc-1.8.0.orig/config.sub0000555000000000000000000007315311732702554013044 0ustar #! /bin/sh # Configuration validation subroutine script. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, # 2000, 2001, 2002, 2003 Free Software Foundation, Inc. timestamp='2003-07-04' # This file is (in principle) common to ALL GNU software. # The presence of a machine in this file suggests that SOME GNU software # can handle that machine. It does not imply ALL GNU software can. # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, # Boston, MA 02111-1307, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. # # Configuration subroutine to validate and canonicalize a configuration type. # Supply the specified configuration type as an argument. # If it is invalid, we print an error message on stderr and exit with code 1. # Otherwise, we print the canonical config type on stdout and succeed. # This file is supposed to be the same for all GNU packages # and recognize all the CPU types, system types and aliases # that are meaningful with *any* GNU software. # Each package is responsible for reporting which valid configurations # it does not support. The user should be able to distinguish # a failure to support a valid configuration from a meaningless # configuration. # The goal of this file is to map all the various variations of a given # machine specification into a single specification in the form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM # or in some cases, the newer four-part form: # CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM # It is wrong to echo any other type of specification. me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] CPU-MFR-OPSYS $0 [OPTION] ALIAS Canonicalize a configuration name. Operation modes: -h, --help print this help, then exit -t, --time-stamp print date of last modification, then exit -v, --version print version number, then exit Report bugs and patches to ." version="\ GNU config.sub ($timestamp) Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit 0 ;; --version | -v ) echo "$version" ; exit 0 ;; --help | --h* | -h ) echo "$usage"; exit 0 ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" exit 1 ;; *local*) # First pass through any local machine types. echo $1 exit 0;; * ) break ;; esac done case $# in 0) echo "$me: missing argument$help" >&2 exit 1;; 1) ;; *) echo "$me: too many arguments$help" >&2 exit 1;; esac # Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). # Here we must recognize all the valid KERNEL-OS combinations. maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` case $maybe_os in nto-qnx* | linux-gnu* | kfreebsd*-gnu* | netbsd*-gnu* | storm-chaos* | os2-emx* | rtmk-nova*) os=-$maybe_os basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` ;; *) basic_machine=`echo $1 | sed 's/-[^-]*$//'` if [ $basic_machine != $1 ] then os=`echo $1 | sed 's/.*-/-/'` else os=; fi ;; esac ### Let's recognize common machines as not being operating systems so ### that things like config.sub decstation-3100 work. We also ### recognize some manufacturers as not being operating systems, so we ### can provide default operating systems below. case $os in -sun*os*) # Prevent following clause from handling this invalid input. ;; -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ -apple | -axis) os= basic_machine=$1 ;; -sim | -cisco | -oki | -wec | -winbond) os= basic_machine=$1 ;; -scout) ;; -wrs) os=-vxworks basic_machine=$1 ;; -chorusos*) os=-chorusos basic_machine=$1 ;; -chorusrdb) os=-chorusrdb basic_machine=$1 ;; -hiux*) os=-hiuxwe2 ;; -sco5) os=-sco3.2v5 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco4) os=-sco3.2v4 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco3.2.[4-9]*) os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco3.2v[4-9]*) # Don't forget version if it is 3.2v4 or newer. basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco*) os=-sco3.2v2 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -udk*) basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -isc) os=-isc2.2 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -clix*) basic_machine=clipper-intergraph ;; -isc*) basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -lynx*) os=-lynxos ;; -ptx*) basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` ;; -windowsnt*) os=`echo $os | sed -e 's/windowsnt/winnt/'` ;; -psos*) os=-psos ;; -mint | -mint[0-9]*) basic_machine=m68k-atari os=-mint ;; esac # Decode aliases for certain CPU-COMPANY combinations. case $basic_machine in # Recognize the basic CPU types without company name. # Some are omitted here because they have special meanings below. 1750a | 580 \ | a29k \ | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr \ | c4x | clipper \ | d10v | d30v | dlx | dsp16xx \ | fr30 | frv \ | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | i370 | i860 | i960 | ia64 \ | ip2k \ | m32r | m68000 | m68k | m88k | mcore \ | mips | mipsbe | mipseb | mipsel | mipsle \ | mips16 \ | mips64 | mips64el \ | mips64vr | mips64vrel \ | mips64orion | mips64orionel \ | mips64vr4100 | mips64vr4100el \ | mips64vr4300 | mips64vr4300el \ | mips64vr5000 | mips64vr5000el \ | mipsisa32 | mipsisa32el \ | mipsisa32r2 | mipsisa32r2el \ | mipsisa64 | mipsisa64el \ | mipsisa64sb1 | mipsisa64sb1el \ | mipsisa64sr71k | mipsisa64sr71kel \ | mipstx39 | mipstx39el \ | mn10200 | mn10300 \ | msp430 \ | ns16k | ns32k \ | openrisc | or32 \ | pdp10 | pdp11 | pj | pjl \ | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ | pyramid \ | sh | sh[1234] | sh[23]e | sh[34]eb | shbe | shle | sh[1234]le | sh3ele \ | sh64 | sh64le \ | sparc | sparc64 | sparc86x | sparclet | sparclite | sparcv9 | sparcv9b \ | strongarm \ | tahoe | thumb | tic4x | tic80 | tron \ | v850 | v850e \ | we32k \ | x86 | xscale | xstormy16 | xtensa \ | z8k) basic_machine=$basic_machine-unknown ;; m6811 | m68hc11 | m6812 | m68hc12) # Motorola 68HC11/12. basic_machine=$basic_machine-unknown os=-none ;; m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) ;; # We use `pc' rather than `unknown' # because (1) that's what they normally are, and # (2) the word "unknown" tends to confuse beginning users. i*86 | x86_64) basic_machine=$basic_machine-pc ;; # Object if more than one company name word. *-*-*) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; # Recognize the basic CPU types with company name. 580-* \ | a29k-* \ | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ | alphapca5[67]-* | alpha64pca5[67]-* | amd64-* | arc-* \ | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ | avr-* \ | bs2000-* \ | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ | clipper-* | cydra-* \ | d10v-* | d30v-* | dlx-* \ | elxsi-* \ | f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \ | h8300-* | h8500-* \ | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ | i*86-* | i860-* | i960-* | ia64-* \ | ip2k-* \ | m32r-* \ | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ | m88110-* | m88k-* | mcore-* \ | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ | mips16-* \ | mips64-* | mips64el-* \ | mips64vr-* | mips64vrel-* \ | mips64orion-* | mips64orionel-* \ | mips64vr4100-* | mips64vr4100el-* \ | mips64vr4300-* | mips64vr4300el-* \ | mips64vr5000-* | mips64vr5000el-* \ | mipsisa32-* | mipsisa32el-* \ | mipsisa32r2-* | mipsisa32r2el-* \ | mipsisa64-* | mipsisa64el-* \ | mipsisa64sb1-* | mipsisa64sb1el-* \ | mipsisa64sr71k-* | mipsisa64sr71kel-* \ | mipstx39-* | mipstx39el-* \ | msp430-* \ | none-* | np1-* | nv1-* | ns16k-* | ns32k-* \ | orion-* \ | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ | pyramid-* \ | romp-* | rs6000-* \ | sh-* | sh[1234]-* | sh[23]e-* | sh[34]eb-* | shbe-* \ | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ | sparc-* | sparc64-* | sparc86x-* | sparclet-* | sparclite-* \ | sparcv9-* | sparcv9b-* | strongarm-* | sv1-* | sx?-* \ | tahoe-* | thumb-* \ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ | tron-* \ | v850-* | v850e-* | vax-* \ | we32k-* \ | x86-* | x86_64-* | xps100-* | xscale-* | xstormy16-* \ | xtensa-* \ | ymp-* \ | z8k-*) ;; # Recognize the various machine names and aliases which stand # for a CPU type and a company and sometimes even an OS. 386bsd) basic_machine=i386-unknown os=-bsd ;; 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) basic_machine=m68000-att ;; 3b*) basic_machine=we32k-att ;; a29khif) basic_machine=a29k-amd os=-udi ;; adobe68k) basic_machine=m68010-adobe os=-scout ;; alliant | fx80) basic_machine=fx80-alliant ;; altos | altos3068) basic_machine=m68k-altos ;; am29k) basic_machine=a29k-none os=-bsd ;; amd64) basic_machine=x86_64-pc ;; amdahl) basic_machine=580-amdahl os=-sysv ;; amiga | amiga-*) basic_machine=m68k-unknown ;; amigaos | amigados) basic_machine=m68k-unknown os=-amigaos ;; amigaunix | amix) basic_machine=m68k-unknown os=-sysv4 ;; apollo68) basic_machine=m68k-apollo os=-sysv ;; apollo68bsd) basic_machine=m68k-apollo os=-bsd ;; aux) basic_machine=m68k-apple os=-aux ;; balance) basic_machine=ns32k-sequent os=-dynix ;; c90) basic_machine=c90-cray os=-unicos ;; convex-c1) basic_machine=c1-convex os=-bsd ;; convex-c2) basic_machine=c2-convex os=-bsd ;; convex-c32) basic_machine=c32-convex os=-bsd ;; convex-c34) basic_machine=c34-convex os=-bsd ;; convex-c38) basic_machine=c38-convex os=-bsd ;; cray | j90) basic_machine=j90-cray os=-unicos ;; crds | unos) basic_machine=m68k-crds ;; cris | cris-* | etrax*) basic_machine=cris-axis ;; da30 | da30-*) basic_machine=m68k-da30 ;; decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) basic_machine=mips-dec ;; decsystem10* | dec10*) basic_machine=pdp10-dec os=-tops10 ;; decsystem20* | dec20*) basic_machine=pdp10-dec os=-tops20 ;; delta | 3300 | motorola-3300 | motorola-delta \ | 3300-motorola | delta-motorola) basic_machine=m68k-motorola ;; delta88) basic_machine=m88k-motorola os=-sysv3 ;; dpx20 | dpx20-*) basic_machine=rs6000-bull os=-bosx ;; dpx2* | dpx2*-bull) basic_machine=m68k-bull os=-sysv3 ;; ebmon29k) basic_machine=a29k-amd os=-ebmon ;; elxsi) basic_machine=elxsi-elxsi os=-bsd ;; encore | umax | mmax) basic_machine=ns32k-encore ;; es1800 | OSE68k | ose68k | ose | OSE) basic_machine=m68k-ericsson os=-ose ;; fx2800) basic_machine=i860-alliant ;; genix) basic_machine=ns32k-ns ;; gmicro) basic_machine=tron-gmicro os=-sysv ;; go32) basic_machine=i386-pc os=-go32 ;; h3050r* | hiux*) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; h8300hms) basic_machine=h8300-hitachi os=-hms ;; h8300xray) basic_machine=h8300-hitachi os=-xray ;; h8500hms) basic_machine=h8500-hitachi os=-hms ;; harris) basic_machine=m88k-harris os=-sysv3 ;; hp300-*) basic_machine=m68k-hp ;; hp300bsd) basic_machine=m68k-hp os=-bsd ;; hp300hpux) basic_machine=m68k-hp os=-hpux ;; hp3k9[0-9][0-9] | hp9[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k2[0-9][0-9] | hp9k31[0-9]) basic_machine=m68000-hp ;; hp9k3[2-9][0-9]) basic_machine=m68k-hp ;; hp9k6[0-9][0-9] | hp6[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k7[0-79][0-9] | hp7[0-79][0-9]) basic_machine=hppa1.1-hp ;; hp9k78[0-9] | hp78[0-9]) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[0-9][13679] | hp8[0-9][13679]) basic_machine=hppa1.1-hp ;; hp9k8[0-9][0-9] | hp8[0-9][0-9]) basic_machine=hppa1.0-hp ;; hppa-next) os=-nextstep3 ;; hppaosf) basic_machine=hppa1.1-hp os=-osf ;; hppro) basic_machine=hppa1.1-hp os=-proelf ;; i370-ibm* | ibm*) basic_machine=i370-ibm ;; # I'm not sure what "Sysv32" means. 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nv1) basic_machine=nv1-cray os=-unicosmp ;; nsr-tandem) basic_machine=nsr-tandem ;; op50n-* | op60c-*) basic_machine=hppa1.1-oki os=-proelf ;; or32 | or32-*) basic_machine=or32-unknown os=-coff ;; OSE68000 | ose68000) basic_machine=m68000-ericsson os=-ose ;; os68k) basic_machine=m68k-none os=-os68k ;; pa-hitachi) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; paragon) basic_machine=i860-intel os=-osf ;; pbd) basic_machine=sparc-tti ;; pbb) basic_machine=m68k-tti ;; pc532 | pc532-*) basic_machine=ns32k-pc532 ;; pentium | p5 | k5 | k6 | nexgen | viac3) basic_machine=i586-pc ;; pentiumpro | p6 | 6x86 | athlon | athlon_*) basic_machine=i686-pc ;; pentiumii | pentium2 | pentiumiii | pentium3) basic_machine=i686-pc ;; pentium4) basic_machine=i786-pc ;; pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumpro-* | p6-* | 6x86-* | athlon-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentium4-*) basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pn) basic_machine=pn-gould ;; power) basic_machine=power-ibm ;; ppc) basic_machine=powerpc-unknown ;; ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppcle | powerpclittle | ppc-le | powerpc-little) basic_machine=powerpcle-unknown ;; ppcle-* | powerpclittle-*) basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64) basic_machine=powerpc64-unknown ;; ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64le | powerpc64little | ppc64-le | powerpc64-little) basic_machine=powerpc64le-unknown ;; ppc64le-* | powerpc64little-*) basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ps2) basic_machine=i386-ibm ;; pw32) basic_machine=i586-unknown os=-pw32 ;; rom68k) basic_machine=m68k-rom68k os=-coff ;; rm[46]00) basic_machine=mips-siemens ;; rtpc | rtpc-*) basic_machine=romp-ibm ;; s390 | s390-*) basic_machine=s390-ibm ;; s390x | s390x-*) basic_machine=s390x-ibm ;; sa29200) basic_machine=a29k-amd os=-udi ;; sb1) basic_machine=mipsisa64sb1-unknown ;; sb1el) basic_machine=mipsisa64sb1el-unknown ;; sei) basic_machine=mips-sei os=-seiux ;; sequent) basic_machine=i386-sequent ;; sh) basic_machine=sh-hitachi os=-hms ;; sh64) basic_machine=sh64-unknown ;; sparclite-wrs | simso-wrs) basic_machine=sparclite-wrs os=-vxworks ;; sps7) basic_machine=m68k-bull os=-sysv2 ;; spur) basic_machine=spur-unknown ;; st2000) basic_machine=m68k-tandem ;; stratus) basic_machine=i860-stratus os=-sysv4 ;; sun2) basic_machine=m68000-sun ;; sun2os3) basic_machine=m68000-sun os=-sunos3 ;; sun2os4) basic_machine=m68000-sun os=-sunos4 ;; sun3os3) basic_machine=m68k-sun os=-sunos3 ;; sun3os4) basic_machine=m68k-sun os=-sunos4 ;; sun4os3) basic_machine=sparc-sun os=-sunos3 ;; sun4os4) basic_machine=sparc-sun os=-sunos4 ;; sun4sol2) basic_machine=sparc-sun os=-solaris2 ;; sun3 | sun3-*) basic_machine=m68k-sun ;; sun4) basic_machine=sparc-sun ;; sun386 | sun386i | roadrunner) basic_machine=i386-sun ;; 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xps | xps100) basic_machine=xps100-honeywell ;; ymp) basic_machine=ymp-cray os=-unicos ;; z8k-*-coff) basic_machine=z8k-unknown os=-sim ;; none) basic_machine=none-none os=-none ;; # Here we handle the default manufacturer of certain CPU types. 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See the # GNU General Public License for more details. # You should have received a copy of the GNU General Public License # along with this program. If not, see . # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Originally written by Alexandre Oliva . case $1 in '') echo "$0: No command. Try \`$0 --help' for more information." 1>&2 exit 1; ;; -h | --h*) cat <<\EOF Usage: depcomp [--help] [--version] PROGRAM [ARGS] Run PROGRAMS ARGS to compile a file, generating dependencies as side-effects. Environment variables: depmode Dependency tracking mode. source Source file read by `PROGRAMS ARGS'. object Object file output by `PROGRAMS ARGS'. DEPDIR directory where to store dependencies. depfile Dependency file to output. tmpdepfile Temporary file to use when outputing dependencies. libtool Whether libtool is used (yes/no). Report bugs to . EOF exit $? ;; -v | --v*) echo "depcomp $scriptversion" exit $? ;; esac if test -z "$depmode" || test -z "$source" || test -z "$object"; then echo "depcomp: Variables source, object and depmode must be set" 1>&2 exit 1 fi # Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po. depfile=${depfile-`echo "$object" | sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`} tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`} rm -f "$tmpdepfile" # Some modes work just like other modes, but use different flags. We # parameterize here, but still list the modes in the big case below, # to make depend.m4 easier to write. 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Note that the slowdown incurred here ## affects only configure: in makefiles, %FASTDEP% shortcuts this. for arg do case $arg in -c) set fnord "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" "$arg" ;; *) set fnord "$@" "$arg" ;; esac shift # fnord shift # $arg done "$@" stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi mv "$tmpdepfile" "$depfile" ;; gcc) ## There are various ways to get dependency output from gcc. Here's ## why we pick this rather obscure method: ## - Don't want to use -MD because we'd like the dependencies to end ## up in a subdir. Having to rename by hand is ugly. ## (We might end up doing this anyway to support other compilers.) ## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like ## -MM, not -M (despite what the docs say). ## - Using -M directly means running the compiler twice (even worse ## than renaming). if test -z "$gccflag"; then gccflag=-MD, fi "$@" -Wp,"$gccflag$tmpdepfile" stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi rm -f "$depfile" echo "$object : \\" > "$depfile" alpha=ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz ## The second -e expression handles DOS-style file names with drive letters. sed -e 's/^[^:]*: / /' \ -e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile" ## This next piece of magic avoids the `deleted header file' problem. ## The problem is that when a header file which appears in a .P file ## is deleted, the dependency causes make to die (because there is ## typically no way to rebuild the header). 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You may also peek at any GNU archive site, in case some other package would contain this missing \`$1' program." exit 1 ;; esac exit 0 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-time-zone: "UTC" # time-stamp-end: "; # UTC" # End: avr-libc-1.8.0.orig/install-sh0000555000000000000000000003253711732702554013066 0ustar #!/bin/sh # install - install a program, script, or datafile scriptversion=2009-04-28.21; # UTC # This originates from X11R5 (mit/util/scripts/install.sh), which was # later released in X11R6 (xc/config/util/install.sh) with the # following copyright and license. # # Copyright (C) 1994 X Consortium # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to # deal in the Software without restriction, including without limitation the # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or # sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN # AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- # TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # Except as contained in this notice, the name of the X Consortium shall not # be used in advertising or otherwise to promote the sale, use or other deal- # ings in this Software without prior written authorization from the X Consor- # tium. # # # FSF changes to this file are in the public domain. # # Calling this script install-sh is preferred over install.sh, to prevent # `make' implicit rules from creating a file called install from it # when there is no Makefile. # # This script is compatible with the BSD install script, but was written # from scratch. nl=' ' IFS=" "" $nl" # set DOITPROG to echo to test this script # Don't use :- since 4.3BSD and earlier shells don't like it. doit=${DOITPROG-} if test -z "$doit"; then doit_exec=exec else doit_exec=$doit fi # Put in absolute file names if you don't have them in your path; # or use environment vars. chgrpprog=${CHGRPPROG-chgrp} chmodprog=${CHMODPROG-chmod} chownprog=${CHOWNPROG-chown} cmpprog=${CMPPROG-cmp} cpprog=${CPPROG-cp} mkdirprog=${MKDIRPROG-mkdir} mvprog=${MVPROG-mv} rmprog=${RMPROG-rm} stripprog=${STRIPPROG-strip} posix_glob='?' initialize_posix_glob=' test "$posix_glob" != "?" || { if (set -f) 2>/dev/null; then posix_glob= else posix_glob=: fi } ' posix_mkdir= # Desired mode of installed file. mode=0755 chgrpcmd= chmodcmd=$chmodprog chowncmd= mvcmd=$mvprog rmcmd="$rmprog -f" stripcmd= src= dst= dir_arg= dst_arg= copy_on_change=false no_target_directory= usage="\ Usage: $0 [OPTION]... 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(umask $mkdir_umask && eval "\$doit_exec \$mkdirprog $prefixes") || test -d "$dstdir" || exit 1 obsolete_mkdir_used=true fi fi fi if test -n "$dir_arg"; then { test -z "$chowncmd" || $doit $chowncmd "$dst"; } && { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } && { test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false || test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1 else # Make a couple of temp file names in the proper directory. dsttmp=$dstdir/_inst.$$_ rmtmp=$dstdir/_rm.$$_ # Trap to clean up those temp files at exit. trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 # Copy the file name to the temp name. (umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") && # and set any options; do chmod last to preserve setuid bits. # # If any of these fail, we abort the whole thing. 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In this case, the final cleanup might fail but the new # file should still install successfully. { test ! -f "$dst" || $doit $rmcmd -f "$dst" 2>/dev/null || { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && { $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; } } || { echo "$0: cannot unlink or rename $dst" >&2 (exit 1); exit 1 } } && # Now rename the file to the real destination. $doit $mvcmd "$dsttmp" "$dst" } fi || exit 1 trap '' 0 fi done # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-time-zone: "UTC" # time-stamp-end: "; # UTC" # End: avr-libc-1.8.0.orig/INSTALL0000644000000000000000000001745311732702554012115 0ustar NB: avr-libc requires a cross-compiler. The recommended way to run configure is ./configure --build=`./config.guess` --host=avr [other options] Basic Installation ================== These are generic installation instructions. The `configure' shell script attempts to guess correct values for various system-dependent variables used during compilation. It uses those values to create a `Makefile' in each directory of the package. It may also create one or more `.h' files containing system-dependent definitions. Finally, it creates a shell script `config.status' that you can run in the future to recreate the current configuration, a file `config.cache' that saves the results of its tests to speed up reconfiguring, and a file `config.log' containing compiler output (useful mainly for debugging `configure'). If you need to do unusual things to compile the package, please try to figure out how `configure' could check whether to do them, and mail diffs or instructions to the address given in the `README' so they can be considered for the next release. If at some point `config.cache' contains results you don't want to keep, you may remove or edit it. The file `configure.in' is used to create `configure' by a program called `autoconf'. You only need `configure.in' if you want to change it or regenerate `configure' using a newer version of `autoconf'. The simplest way to compile this package is: 1. `cd' to the directory containing the package's source code and type `./configure' to configure the package for your system. If you're using `csh' on an old version of System V, you might need to type `sh ./configure' instead to prevent `csh' from trying to execute `configure' itself. Running `configure' takes awhile. While running, it prints some messages telling which features it is checking for. 2. Type `make' to compile the package. 3. Optionally, type `make check' to run any self-tests that come with the package. 4. Type `make install' to install the programs and any data files and documentation. 5. You can remove the program binaries and object files from the source code directory by typing `make clean'. To also remove the files that `configure' created (so you can compile the package for a different kind of computer), type `make distclean'. There is also a `make maintainer-clean' target, but that is intended mainly for the package's developers. If you use it, you may have to get all sorts of other programs in order to regenerate files that came with the distribution. Compilers and Options ===================== Some systems require unusual options for compilation or linking that the `configure' script does not know about. You can give `configure' initial values for variables by setting them in the environment. Using a Bourne-compatible shell, you can do that on the command line like this: CC=c89 CFLAGS=-O2 LIBS=-lposix ./configure Or on systems that have the `env' program, you can do it like this: env CPPFLAGS=-I/usr/local/include LDFLAGS=-s ./configure Compiling For Multiple Architectures ==================================== You can compile the package for more than one kind of computer at the same time, by placing the object files for each architecture in their own directory. To do this, you must use a version of `make' that supports the `VPATH' variable, such as GNU `make'. `cd' to the directory where you want the object files and executables to go and run the `configure' script. `configure' automatically checks for the source code in the directory that `configure' is in and in `..'. If you have to use a `make' that does not supports the `VPATH' variable, you have to compile the package for one architecture at a time in the source code directory. After you have installed the package for one architecture, use `make distclean' before reconfiguring for another architecture. Installation Names ================== By default, `make install' will install the package's files in `/usr/local/bin', `/usr/local/man', etc. You can specify an installation prefix other than `/usr/local' by giving `configure' the option `--prefix=PATH'. You can specify separate installation prefixes for architecture-specific files and architecture-independent files. If you give `configure' the option `--exec-prefix=PATH', the package will use PATH as the prefix for installing programs and libraries. Documentation and other data files will still use the regular prefix. In addition, if you use an unusual directory layout you can give options like `--bindir=PATH' to specify different values for particular kinds of files. Run `configure --help' for a list of the directories you can set and what kinds of files go in them. If the package supports it, you can cause programs to be installed with an extra prefix or suffix on their names by giving `configure' the option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'. Optional Features ================= Some packages pay attention to `--enable-FEATURE' options to `configure', where FEATURE indicates an optional part of the package. They may also pay attention to `--with-PACKAGE' options, where PACKAGE is something like `gnu-as' or `x' (for the X Window System). The `README' should mention any `--enable-' and `--with-' options that the package recognizes. For packages that use the X Window System, `configure' can usually find the X include and library files automatically, but if it doesn't, you can use the `configure' options `--x-includes=DIR' and `--x-libraries=DIR' to specify their locations. Specifying the System Type ========================== There may be some features `configure' can not figure out automatically, but needs to determine by the type of host the package will run on. Usually `configure' can figure that out, but if it prints a message saying it can not guess the host type, give it the `--host=TYPE' option. TYPE can either be a short name for the system type, such as `sun4', or a canonical name with three fields: CPU-COMPANY-SYSTEM See the file `config.sub' for the possible values of each field. If `config.sub' isn't included in this package, then this package doesn't need to know the host type. If you are building compiler tools for cross-compiling, you can also use the `--target=TYPE' option to select the type of system they will produce code for and the `--build=TYPE' option to select the type of system on which you are compiling the package. Sharing Defaults ================ If you want to set default values for `configure' scripts to share, you can create a site shell script called `config.site' that gives default values for variables like `CC', `cache_file', and `prefix'. `configure' looks for `PREFIX/share/config.site' if it exists, then `PREFIX/etc/config.site' if it exists. Or, you can set the `CONFIG_SITE' environment variable to the location of the site script. A warning: not all `configure' scripts look for a site script. Operation Controls ================== `configure' recognizes the following options to control how it operates. `--cache-file=FILE' Use and save the results of the tests in FILE instead of `./config.cache'. Set FILE to `/dev/null' to disable caching, for debugging `configure'. `--help' Print a summary of the options to `configure', and exit. `--quiet' `--silent' `-q' Do not print messages saying which checks are being made. To suppress all normal output, redirect it to `/dev/null' (any error messages will still be shown). `--srcdir=DIR' Look for the package's source code in directory DIR. Usually `configure' can determine that directory automatically. `--version' Print the version of Autoconf used to generate the `configure' script, and exit. `configure' also accepts some other, not widely useful, options. avr-libc-1.8.0.orig/ChangeLog-20050000644000000000000000000020675311732702554013225 0ustar 2005-12-31 Joerg Wunsch Fix the examples installation for non-doc builds. * Makefile.am: always include "doc" into SUBDIRS. * configure.ac: make "api" conditional, not "doc". * doc/Makefile.am: make the "api" subdir conditional. * doc/examples/Makefile.am: correctly uninstall, as opposed to doc/api/Makefile.am doing it for us. 2005-12-29 Joerg Wunsch * doc/api/Makefile.am: Install JPEG files in docs. * doc/examples/Makefile.am: Install the demo source code as part of the documentation. * doc/examples/largedemo/largedemo.dox: Omit the verbatim source code from the docs, instead place references to the installed code. * doc/examples/stdiodemo/stdiodemo.dox: (Ditto.) * doc/examples/twitest/twitest.dox: (Ditto.) 2005-12-28 Joerg Wunsch Add an "stdio" demo, and minor review of the "large" demo. * doc/api/Makefile.am: Generalize the demo handling; run "make dox" in all demos that need it as a prerequisite to build the documentation, and run "make clean" there as well. * doc/api/doxygen.config.in: Add more example and image directories (for stdiodemo). * doc/examples/Makefile.am: Add stdiodemo files. * doc/examples/all-demos.dox: Wire the stdiodemo into the general comment about the demos. * doc/examples/largedemo/Makefile: add code to convert a JPEG image into an EPS file. * doc/examples/largedemo/largedemo.dox: Fix some minor mistakes, and add photo images of the setup. * doc/examples/largedemo/largedemo-setup.jpg: New file. * doc/examples/largedemo/largedemo-wiring.jpg: New file. * doc/examples/stdiodemo/Makefile: New file. * doc/examples/stdiodemo/defines.h: New file. * doc/examples/stdiodemo/hd44780.c: New file. * doc/examples/stdiodemo/hd44780.h: New file. * doc/examples/stdiodemo/lcd.c: New file. * doc/examples/stdiodemo/lcd.h: New file. * doc/examples/stdiodemo/stdiodemo-setup.jpg: New file. * doc/examples/stdiodemo/stdiodemo.c: New file. * doc/examples/stdiodemo/stdiodemo.dox: New file. * doc/examples/stdiodemo/uart.c: New file. * doc/examples/stdiodemo/uart.h: New file. 2005-12-27 Joerg Wunsch * configure.ac: Bump version date. 2005-12-27 Joerg Wunsch Submitted by Risto Eerola: * include/avr/sleep.h: add sleep_enable(), sleep_disable(), and sleep_cpu(). patch #4611: sleep.h sleep_mode() not interrupt safe 2005-12-25 Anatoly Sokolov * libm/fplib/Files.am: include new files. * libm/fplib/fp_m_inf.S: new file. * libm/fplib/fp_p_inf.S: new file. * libm/fplib/fplib.inc (EMAX, EMIN): Add. * libm/fplib/ldexp.S: Check underflow and overflow cases. [Fixed bug #15226] 2005-12-23 Anatoly Sokolov * libm/fplib/fp_cmp.S: Use 'rByte' instead 'retByte'. * libm/fplib/fplib.inc (retByte): Deleted. 2005-12-18 Anatoly Sokolov Submitted by Werner Boellmann: * include/avr/pgmspace.h (strstr_P): Declare. * libc/pmstring/Files.am: Include new file. * libc/pmstring/strstr_P.S: New file. Add patch #4668: progmem aware verson of strstr(). 2005-12-17 Joerg Wunsch * xml/patch-headers.py: add the ATtinyX4 family, fix the list of ATtinyX5. * doc/api/vectortable.dox: Regenerate using patch-headers.py. 2005-12-15 Anatoly Sokolov * configure.ac: add tests for the ATtiny24/44/84 support. * devtools/gen-avr-lib-tree.sh: add support for ATtiny24/44/84. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * include/avr/iotn24.h: new file. * include/avr/iotn44.h: new file. * include/avr/iotn84.h: new file. * include/avr/iotnx4.h: new file. * include/avr/Makefile.am: include new files. * doc/api/main_page.dox: Document support for ATtiny24/44/84. * doc/api/using-tools.dox: (Ditto.) 2005-12-14 Anatoly Sokolov * /include/avr/iocanxx.h (IVSE): Rename in IVSEL. [Fixed bug #15161] 2005-12-13 Joerg Wunsch Submitted by Frank Behrens: * include/util/delay.h: fix inlining of the delay functions. Fix from bug #15161: util/delay.h misses inline keyword (regression). 2005-12-11 Anatoly Sokolov * /libm/fplib/fp_powerseries.S: Use __addsf3/__mulsf3/__divsf3 instead __addsf3x/__mulsf3x/__divsf3x. * /libm/fplib/asin.S (table_asin): Change constants to ieee format. * /libm/fplib/atan.S (.Ltable_atan): (Ditto.). * /libm/fplib/exp.S (table_exp): (Ditto.). * /libm/fplib/fp_cosinus.S (table_cos): (Ditto.). * /libm/fplib/log.S (table_log): (Ditto.). * /libm/fplib/tan.S (table_tan): (Ditto.). 2005-12-06 Anatoly Sokolov * /libm/fplib/Files.am: Include new files. * /libm/fplib/divsf3.S (__fp_inverse): Move to ... * /libm/fplib/fp_inverse.S: ... new file. * /libm/fplib/mulsf3.S (square): Move to ... * /libm/fplib/square.S: ... new file. 2005-12-05 Joerg Wunsch Add a new demo project ("largedemo"). * doc/examples/largedemo/Makefile: New file. * doc/examples/largedemo/largedemo.c: New file. * doc/examples/largedemo/largedemo.dox: New file. * doc/api/doxygen.config.in: Wire the largedemo into the build. * doc/examples/Makefile.am: (Ditto.) * doc/examples/all-demos.dox: Add some blurb for largedemo. 2005-12-06 Anatoly Sokolov * libm/fplib/fp_split.S (__fp_split_a): Add new function. * libm/fplib/ceil.S: Use __fp_split_a. * libm/fplib/floor.S: (Ditto.) * libm/fplib/fp_powerseries.S: (Ditto.) * libm/fplib/frexp.S: (Ditto.) * libm/fplib/ldexp.S: (Ditto.) * libm/fplib/log.S: (Ditto.) * libm/fplib/modf.S: (Ditto.) * libm/fplib/sqrt.S: (Ditto.) 2005-12-01 Joerg Wunsch * doc/examples/demo/demo.c: Modernize the demo a bit, keep the #ifdef spaghetti out in its own include file. * doc/examples/demo/demo.dox: (Ditto.) * doc/examples/demo/demo.fig: (Ditto.) * doc/examples/demo/iocompat.h: New file. * doc/examples/Makefile.am (EXTRA_DIST): include demo/iocompat.h. 2005-11-19 Joerg Wunsch Released avr-libc-1.4.0. 2005-11-19 Joerg Wunsch Submitted by Dmitry Xmelkov: * libm/fplib/pow.S: reimplement. Fixes bug #14852: fp pow function broken for negative x 2005-11-15 Anatoly Sokolov Submitted by Peeter Vois: * libm/fplib/mulsf3x.S: use MUL instruction in group avr4, avr5 devices [patch #4557] Adds to the fplib usage of MUL instruction in group avr4; avr5 devices 2005-11-14 Joerg Wunsch * include/avr/crc16.h (_crc_ibutton_update): new function. [patch #3925]: Dallas iButton 8-bit CRC 2005-11-14 Joerg Wunsch Submitted by Galen Seitz: * avr-libc.spec.in: unify location of doc files. [patch #4622] unify doc file location in rpms 2005-11-13 Anatoly Sokolov * libm/fplib/fp_split.S: Make labels local. * libm/fplib/tanh.S: speedup tanh function. patch #3592: speedup tanh function in libm 2005-11-11 Anatoly Sokolov * common/macros.inc(X_movw): Adds the possibility to use upper case latters in register names: R0..R31. (Patch submitted by Dmitry Xmelkov.) (LOAD_X): Deleted. (LOAD_Z): Deleted. 2005-11-11 Joerg Wunsch * devtools/gen-avr-lib-tree.sh (CFLAGS_SPEED): change from -O3 to -Os. Mostly, this even yields the fastest code anyway. 2005-11-10 Anatoly Sokolov * include/math.h (exp): Rename argument. (inverse): Deleted. [Fixed bug #13340] 2005-11-11 Joerg Wunsch * doc/api/rel-method.dox: Update for new configuration method, fix some typos. * doc/api/Makefile.am: replace "signal" in the comment by "vector" to reflect our changed naming convention. 2005-11-10 Joerg Wunsch Submitted by Risto Eerola: * include/avr/io43u32x.h: Unify (old-style SIG_xxx) interrupt vector names. * include/avr/io43u35x.h: (Ditto.) * include/avr/io90pwmx.h: (Ditto.) * include/avr/iomx8.h: (Ditto.) * include/avr/iomxx4.h: (Ditto.) * include/avr/iotn11.h: (Ditto.) * include/avr/iotn12.h: (Ditto.) * include/avr/iotn15.h: (Ditto.) * include/avr/iotn2313.h: (Ditto.) * include/avr/iotn26.h: (Ditto.) * include/avr/iotnx5.h: (Ditto.) * doc/api/vectortable.dox: Regenerate, document the changes. patch #4505: Unified interrupt vector names in header files. 2005-11-10 Anatoly Sokolov * fplib/fmod.S: Make labels local, add Id line. [Fixed bug #3573] 2005-11-10 Joerg Wunsch Submitted by Galen Seitz: * avr-libc.spec.in: upgrade to current build system. [patch #4608] rpm spec file update 2005-11-10 Anatoly Sokolov * crt1/gcrt1.S: Make labels local, add Id line. 2005-11-10 Joerg Wunsch * doc/api/doxygen.config.in: set SHOW_DIRECTORIES to NO, as we don't really use that feature, and enabling it yields junk "man pages" for the directory entries. 2005-11-10 Anatoly Sokolov * libc/stdlib/ctype.S (isxdigit, ispunct, tolower, toupper): Make labels local. * libc/stdlib/setjmp.S: add Id line. (setjmp): use X_movw instead LOAD_Z. (longjmp): use X_movw instead LOAD_X, use X_movw when possible. 2005-11-10 Anatoly Sokolov * libc/stdlib/atoi.S: Make labels local, use X_movw instead LOAD_Z. * libc/stdlib/atol.S: Make labels local, add Id line, use X_movw instead LOAD_Z. 2005-11-09 Joerg Wunsch * libc/stdio/vfscanf.c: fix the return value for starred format specifiers, and return the number of assignments rather than the number of conversions. Fixes bug #14104: sscanf returns number of matches instead of number of assignments 2005-11-09 Joerg Wunsch * doc/api/Makefile.am(EXTRA_DIST): add doxygen.config.in (reported by Galen Seitz). * libc/stdio/vfscanf.c: include so strtod() is declared before using it. 2005-11-08 Anatoly Sokolov * libc/pmstring/strncat_P.S: Make labels local, add Id line, use X_movw when possible, use X_movw instead LOAD_X/LOAD_Z. * libc/pmstring/strncpy_P.S: (Ditto.) * libc/pmstring/memcpy_P.S: Make labels local, add Id line, use X_movw instead LOAD_X/LOAD_Z. * libc/pmstring/strcasecmp_P.S: (Ditto.) * libc/pmstring/strcat_P.S: (Ditto.) * libc/pmstring/strcmp_P.S: (Ditto.) * libc/pmstring/strcpy_P.S: (Ditto.) * libc/pmstring/strlcat_P.S: (Ditto.) * libc/pmstring/strlcpy_P.S: (Ditto.) * libc/pmstring/strlen_P.S: (Ditto.) * libc/pmstring/strncasecmp_P.S: (Ditto.) * libc/pmstring/strncmp_P.S: (Ditto.) * libc/pmstring/strnlen_P.S: (Ditto.) 2005-11-06 Joerg Wunsch (Patch submitted by Colin O'Flynn.) * include/avr/wdt.h: protect wdt_disable against interrupts, resolves bug #14327 overview: wdt_disable() missing a cli 2005-11-05 Joerg Wunsch * configure.ac: bump version date 2005-11-05 Joerg Wunsch * include/Makefile.am: add new subdir util/. * include/compat/deprecated.h: add inp/outp/sbi/cbi. * include/compat/ina90.h: add minimal doxygen documentation. * include/compat/twi.h: move to util/twi.h, leave stub. * include/avr/crc16.h: move to util/crc16.h, leave stub. * include/avr/delay.h: move to util/delay.h, leave stub. * include/avr/parity.h: move to util/parity.h, leave stub. * include/util/Makefile.am: (New file) * include/util/crc16.h: moved from avr/crc16.h. * include/util/delay.h: moved from avr/delay.h. * include/util/parity.h: moved from avr/parity.h. * include/util/twi.h: moved from compat/twi.h, doxygenified. * doc/examples/twitest/twitest.c: -> * doc/examples/twitest/twitest.dox: (Ditto.) * configur.ac: include include/util. 2005-11-05 Anatoly Sokolov * libc/string/strcasecmp.S: Make labels local, add Id line, use X_movw instead LOAD_X/LOAD_Z. * libc/string/strlwr.S: (Ditto.) * libc/string/strncasecmp.S: (Ditto.) * libc/string/strupr.S: (Ditto.) * libc/string/memccpy.S: Rename labels. * libc/string/memchr.S: (Ditto.) * libc/string/strstr.S: Make labels local. 2005-11-04 Joerg Wunsch * doc/api/assembler.dox: replace SIGNAL() by ISR(). * doc/api/faq.dox: (Ditto.) * doc/api/interrupts.dox: (Ditto.) * doc/examples/demo/demo.c: (Ditto.) * doc/examples/demo/demo.dox: (Ditto.) * include/avr/interrupt.h: Add ISR(), move enable_external_int() and timer_enable_int() to compat/deprecated.h, move SIGNAL() here (by now). * include/avr/signal.h: Move SIGNAL() and EMPTY_INTERRUPT() to interrupt.h, issue a #warning. * include/compat/Makefile.am: add deprecated.h. * include/compat/deprecated.h: New file. Collect deprecated items from avr/signal.h. 2005-11-04 Joerg Wunsch * doc/examples/avr-recv.c: Drop long since obsolete examples. * doc/examples/io.c: (Ditto.) * doc/examples/prg: (Ditto.) * doc/examples/printf.h: (Ditto.) * doc/examples/progmem.c: (Ditto.) * doc/examples/send_byte.s: (Ditto.) * doc/examples/signal.c: (Ditto.) 2005-11-03 Anatoly Sokolov * libc/string/strsep.S: Make labels local, add Id line, use movw when possible, use X_movw instead LOAD_X/LOAD_Z, optimize. * libc/string/strlcat.S: Make labels local, add Id line, use movw when possible, use X_movw instead LOAD_X/LOAD_Z. * libc/string/strlcpy.S: (Ditto.) * libc/string/strtok_r.S: (Ditto.) 2005-10-22 Joerg Wunsch * include/avr/io1200.h: Rework headers, replace comma by underscore if needed. * include/avr/io2313.h: (Ditto.) * include/avr/io2323.h: (Ditto.) * include/avr/io2333.h: (Ditto.) * include/avr/io2343.h: (Ditto.) * include/avr/io4414.h: (Ditto.) * include/avr/io4433.h: (Ditto.) * include/avr/io4434.h: (Ditto.) * include/avr/io8515.h: (Ditto.) * include/avr/io8535.h: (Ditto.) * include/avr/io86r401.h: (Ditto.) * include/avr/io90pwmx.h: (Ditto.) * include/avr/iom103.h: (Ditto.) * include/avr/iom128.h: (Ditto.) * include/avr/iom16.h: (Ditto.) * include/avr/iom161.h: (Ditto.) * include/avr/iom162.h: (Ditto.) * include/avr/iom163.h: (Ditto.) * include/avr/iom165.h: (Ditto.) * include/avr/iom169.h: (Ditto.) * include/avr/iom32.h: (Ditto.) * include/avr/iom323.h: (Ditto.) * include/avr/iom325.h: (Ditto.) * include/avr/iom3250.h: (Ditto.) * include/avr/iom329.h: (Ditto.) * include/avr/iom3290.h: (Ditto.) * include/avr/iom64.h: (Ditto.) * include/avr/iom645.h: (Ditto.) * include/avr/iom6450.h: (Ditto.) * include/avr/iom649.h: (Ditto.) * include/avr/iom6490.h: (Ditto.) * include/avr/iom8.h: (Ditto.) * include/avr/iom8515.h: (Ditto.) * include/avr/iom8535.h: (Ditto.) * include/avr/iomx8.h: (Ditto.) * include/avr/iomxx0_1.h: (Ditto.) * include/avr/iomxx4.h: (Ditto.) * include/avr/iotn11.h: (Ditto.) * include/avr/iotn12.h: (Ditto.) * include/avr/iotn13.h: (Ditto.) * include/avr/iotn15.h: (Ditto.) * include/avr/iotn22.h: (Ditto.) * include/avr/iotn2313.h: (Ditto.) * include/avr/iotn26.h: (Ditto.) * include/avr/iotn28.h: (Ditto.) * include/avr/iotnx5.h: (Ditto.) * xml/Atmel2libc.py: Replace comma by underscore in vector names. * xml/patch-headers.py: Refine the vector rewrite algorithm, so it now properly preserves anything between the vectors (like #ifdefs). * doc/api/vectortable.dox: Reflect header changes in documentation. 2005-10-30 Anatoly Sokolov * libc/string/memcmp.S: Make labels local, add Id line, use X_movw instead LOAD_X/LOAD_Z. * libc/string/memcpy.S: (Ditto.) * libc/string/memmove.S: (Ditto.) * libc/string/memset.S: (Ditto.) * libc/string/strcat.S: (Ditto.) * libc/string/strcmp.S: (Ditto.) * libc/string/strcpy.S: (Ditto.) * libc/string/strlen.S: (Ditto.) * libc/string/strncat.S: (Ditto.) * libc/string/strncmp.S: (Ditto.) * libc/string/strncpy.S: (Ditto.) * libc/string/strnlen.S: (Ditto.) * libc/string/strrev.S: (Ditto.) 2005-10-27 Anatoly Sokolov * devtools/gen-avr-lib-tree.sh: Set optimisation for building assembler sources files for 'avr3' and 'avr5' architectures to speed. 2005-10-26 Anatoly Sokolov * libc/string/strchr.S: Make labels local, add Id line, use movw when possible, use X_movw instead LOAD_Z. * libc/string/strrchr.S: (Ditto.) * libc/string/strstr.S: use movw when possible, use X_movw instead LOAD_X/LOAD_Z. 2005-10-25 Anatoly Sokolov * configure.ac: add tests for the AT90CAN32/64 support * devtools/gen-avr-lib-tree.sh: add support for AT90CAN32/64. * include/avr/io.h: (Ditto.) * include/avr/wdt.h: (Ditto.) * include/avr/iocan32.h: new file. * include/avr/iocan64.h: new file. * include/avr/iocan128.h: move SFR, bits and interupts definitions from here .. * include/avr/iocanxx.h: .. to here. new file. * include/avr/Makefile.am: include new files. * doc/api/main_page.dox: Document support for AT90CAN32/64. * doc/api/using-tools.dox: (Ditto.) 2005-10-24 Anatoly Sokolov * devtools/gen-avr-lib-tree.sh: Change optimisation level for building libraries for 'avr2' and 'avr4' architectures to 'CFLAGS_SPACE'. 2005-10-22 Joerg Wunsch * configure.ac: bump version. * include/avr/iomxx0_1.h: Fix some lost #ifdefs. * include/avr/iomxx4.h: Fix some lost #ifdefs. * doc/api/interrupts.dox: Document we now have two styles of interrupt vector names; omit the hardcoded table of vector names. * doc/api/vectortable.dox: New file, automatically generated by xml/patch-headers.py. * doc/api/Makefile.am: tweak for new vector table. 2005-10-22 Joerg Wunsch * include/avr/io1200.h: add new (XXX_vect) vector names. * include/avr/io2313.h: (Ditto.) * include/avr/io2323.h: (Ditto.) * include/avr/io2333.h: (Ditto.) * include/avr/io2343.h: (Ditto.) * include/avr/io4414.h: (Ditto.) * include/avr/io4433.h: (Ditto.) * include/avr/io4434.h: (Ditto.) * include/avr/io8515.h: (Ditto.) * include/avr/io8535.h: (Ditto.) * include/avr/io86r401.h: (Ditto.) * include/avr/io90pwmx.h: (Ditto.) * include/avr/iocan128.h: (Ditto.) * include/avr/iom103.h: (Ditto.) * include/avr/iom128.h: (Ditto.) * include/avr/iom16.h: (Ditto.) * include/avr/iom161.h: (Ditto.) * include/avr/iom162.h: (Ditto.) * include/avr/iom163.h: (Ditto.) * include/avr/iom165.h: (Ditto.) * include/avr/iom169.h: (Ditto.) * include/avr/iom32.h: (Ditto.) * include/avr/iom323.h: (Ditto.) * include/avr/iom325.h: (Ditto.) * include/avr/iom3250.h: (Ditto.) * include/avr/iom329.h: (Ditto.) * include/avr/iom3290.h: (Ditto.) * include/avr/iom64.h: (Ditto.) * include/avr/iom645.h: (Ditto.) * include/avr/iom6450.h: (Ditto.) * include/avr/iom649.h: (Ditto.) * include/avr/iom6490.h: (Ditto.) * include/avr/iom8.h: (Ditto.) * include/avr/iom8515.h: (Ditto.) * include/avr/iom8535.h: (Ditto.) * include/avr/iomx8.h: (Ditto.) * include/avr/iomxx0_1.h: (Ditto.) * include/avr/iomxx4.h: (Ditto.) * include/avr/iotn11.h: (Ditto.) * include/avr/iotn12.h: (Ditto.) * include/avr/iotn13.h: (Ditto.) * include/avr/iotn15.h: (Ditto.) * include/avr/iotn22.h: (Ditto.) * include/avr/iotn2313.h: (Ditto.) * include/avr/iotn26.h: (Ditto.) * include/avr/iotn28.h: (Ditto.) * include/avr/iotnx5.h: (Ditto.) 2005-10-21 Joerg Wunsch * xml/Desc-parser.py: rename to Descparser.py, as Python doesn't like dashes in file names that are to be used as a module name. * xml/Descparser.py: new (cloned) file. 2005-10-21 Joerg Wunsch * xml/Atmel2libc.py: correctly escape & in output, don't bail out if the device has holes in the vector table, map out illegal characters when constructing a vector's name, consider devices that have a bootloader but no RWW/NRWW areas, parse traditional header files for alt_names * xml/Desc-parser.py: when adding an alt_name, build a list of names, use an IO register's name as the key instead of its address, as in few cases, two registers share the same address, allow specifying a file on the command-line * xml/Device.dtd: add alt_name to the interrupt vector spec. * xml/patch-headers.py: New file. Convert XML files, and generate patched header files with mixed old and new style names. 2005-10-20 Anatoly Sokolov * libc/string/memccpy.S: Make labels local, add Id line, use movw when possible, use X_movw instead LOAD_X/LOAD_Z. * libc/string/memchr.S: (Ditto.) 2005-10-19 Anatoly Sokolov * libc/misc/itoa.S (itoa) : Use movw when possible. * libc/misc/ltoa.S (ltoa) : (Ditto.). * libc/misc/utoa.S (utoa) : (Ditto.). * libc/misc/ultoa.S (ultoa) : (Ditto.). 2005-10-18 Joerg Wunsch * include/string.h: make _FFS a plain macro that never calls ffs(); minor doc changes for _FFS * libc/string/ffs.S: refer to _FFS for compile-time constant expressions. 2005-10-18 Anatoly Sokolov * doc/api/doxygen.config.in: Use 'top_builddir' instead 'top_srcdir' in the IMAGE_PATH parameter. * doc/api/Makefile.am: Add full path for 'avrs.png-save' file. New 'sed' command for transformations 'doxygen.config.in'. 2005-10-18 Anatoly Sokolov * include/string.h (ffs): Rename 'ffs' macro to '_FFS'. Move DOXYGEN comments for 'ffs', 'ffsl' and 'ffsll' from here . * libc/string/ffs.S: .. to here, .. * libc/string/ffsl.S: .. to here and .. * libc/string/ffsll.S: .. to here. 2005-10-17 Joerg Wunsch * include/avr/io86r401.h: fix interrupt vector table. * include/avr/iomxx4.h: fix a typo and an inconsistency in in the interrupt vector definitions. * include/avr/iotn2313.h: supply traditional avr-libc-style interrupt vector names in addition to the names present in this file in avr-libc-1.2.x. 2005-10-16 Joerg Wunsch * devtools/make-binary-dist.sh: New file. 2005-10-16 Anatoly Sokolov (Contributed by Dmitry Xmelkov. ) * include/string.h (ffs, ffsl, ffsll): Add declarations. * libc/string/ffs.S: New file. * libc/string/ffsl.S: New file. * libc/string/ffcll.S: New file. * libc/string/Files.am: Include new files. [Fixed bug #12739] 2005-10-16 Anatoly Sokolov * include/avr/iom165.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, OCDR) : Change "SFR_I08()" on "_SFR_I08()". * include/avr/iom325.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, OCDR) : (Ditto.). * include/avr/iom329.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, OCDR) : (Ditto.). * include/avr/iom645.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, OCDR) : (Ditto.). * include/avr/iom649.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, OCDR) : (Ditto.). * include/avr/iom3250.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, OCDR) : (Ditto.). * include/avr/iom3290.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, OCDR) : (Ditto.). * include/avr/iom6450.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, OCDR) : (Ditto.). * include/avr/iom6490.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, OCDR) : (Ditto.). * include/avr/iomxx4.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, MONDR, OCDR) : (Ditto.). * include/avr/iomxx0_1.h (GPIOR1, GPIOR2, SPSR, SPSR, SPDR, ACSR, MONDR, OCDR) : (Ditto.). [Fixed bug #14798] 2005-10-12 Anatoly Sokolov * libc/misc/itoa.S: Make labels local, add Id line. * libc/misc/ltoa.S: (Ditto.) * libc/misc/ultoa.S: (Ditto.) * libc/misc/utoa.S: (Ditto.) 2005-10-10 Anatoly Sokolov (Idea by Dmitry K. ) * common/macros.inc (X_movw) : New version. Can use register names as arguments. 2005-10-06 Anatoly Sokolov * include/avr/boot.h (__boot_page_fill_normal, __boot_page_fill_alternate, __boot_page_erase_normal, __boot_page_erase_alternate, __boot_page_write_normal, __boot_page_write_alternate, __boot_rww_enable, __boot_rww_enable_alternate, __boot_lock_bits_set, __boot_lock_bits_set_alternate, boot_lock_fuse_bits_get): Change type of __SPM_REG operand on input, immediate. (__boot_page_fill_extended, __boot_page_erase_extended, __boot_page_write_extended) : Change type of __SPM_REG and RAMPZ operands on input, immediate. [Fixed bug #14486] 2005-09-29 Anatoly Sokolov Add support for AT90PWM2B/AT90PWM3B. * include/avr/io90pwmx.h (PCST0, PCST1, PCST2) : Add. 2005-09-29 Anatoly Sokolov * include/avr/boot.h (__boot_eeprom_spm_safe): Deleted. ( boot_page_fill_safe, boot_page_erase_safe, boot_page_write_safe, boot_rww_enable_safe, boot_lock_bits_set_safe): Changed, do not use __boot_eeprom_spm_safe macro. [Fixed bug #12324] 2005-09-26 Anatoly Sokolov (Contributed by Dmitry K. ) libc/pmstring/strnlen_P.S (strnlen_P): Move LPM_R0_ZP instruction. [Fixed bug #14503] 2005-09-25 Anatoly Sokolov * configure.ac: Use automake conditionals for enabling/disabling device support. * devtools/gen-avr-lib-tree.sh: (Ditto.) * AvrCommon.am : Delete VPATH. * AvrCommonLibC.am: (Ditto.) [ Fixed bug #14380 ] 2005-09-23 Anatoly Sokolov * include/avr/iomxx0_1.h (PCIFR): Change address from 0x1C to 0x1B 2005-09-14 Joerg Wunsch * include/stdio.h (struct __file): Add the __SMALLOC flag bit. (fdev_close): add this macro as a hook to destroy library resources when deleting fdev_setup_stream()-initialized streams. * libc/fdevopen.c: Keep track of malloc()ed streams by setting the __SMALLOC flag. * libc/fclose.c: Bail out unless __SMALLOC is set, so we don't accidentally try to free streams that have been set up by fdev_setup_stream(). 2005-09-13 Joerg Wunsch * doc/api/doxygen.config.in: use __DOXYGEN__ instead of DOXYGEN to encapsulate documentation-only code, so we are on the safe side wrt. using a reserved macro name that cannot collide with an application. * include/assert.h: (Ditto.) * include/math.h: (Ditto.) * include/setjmp.h: (Ditto.) * include/stdint.h: (Ditto.) * include/stdio.h: (Ditto.) * include/stdlib.h: (Ditto.) * include/avr/delay.h: (Ditto.) * include/avr/eeprom.h: (Ditto.) * include/avr/interrupt.h: (Ditto.) * include/avr/pgmspace.h: (Ditto.) * include/avr/sleep.h: (Ditto.) * include/avr/wdt.h: (Ditto.) * libc/misc/itoa.S: (Ditto.) * libc/misc/ltoa.S: (Ditto.) * libc/misc/mul10.S: (Ditto.) * libc/misc/mulsi10.S: (Ditto.) * libc/misc/ultoa.S: (Ditto.) * libc/misc/utoa.S: (Ditto.) * libc/pmstring/memcpy_P.S: (Ditto.) * libc/pmstring/strcasecmp_P.S: (Ditto.) * libc/pmstring/strcat_P.S: (Ditto.) * libc/pmstring/strcmp_P.S: (Ditto.) * libc/pmstring/strcpy_P.S: (Ditto.) * libc/pmstring/strlcat_P.S: (Ditto.) * libc/pmstring/strlcpy_P.S: (Ditto.) * libc/pmstring/strlen_P.S: (Ditto.) * libc/pmstring/strncasecmp_P.S: (Ditto.) * libc/pmstring/strncat_P.S: (Ditto.) * libc/pmstring/strncmp_P.S: (Ditto.) * libc/pmstring/strncpy_P.S: (Ditto.) * libc/pmstring/strnlen_P.S: (Ditto.) * libc/stdlib/atoi.S: (Ditto.) * libc/stdlib/atol.S: (Ditto.) * libc/stdlib/ctype.S: (Ditto.) * libc/stdlib/stdlib_private.h: (Ditto.) * libc/string/memccpy.S: (Ditto.) * libc/string/memchr.S: (Ditto.) * libc/string/memcmp.S: (Ditto.) * libc/string/memcpy.S: (Ditto.) * libc/string/memmove.S: (Ditto.) * libc/string/memset.S: (Ditto.) * libc/string/strcasecmp.S: (Ditto.) * libc/string/strcat.S: (Ditto.) * libc/string/strchr.S: (Ditto.) * libc/string/strcmp.S: (Ditto.) * libc/string/strcpy.S: (Ditto.) * libc/string/strlcat.S: (Ditto.) * libc/string/strlcpy.S: (Ditto.) * libc/string/strlen.S: (Ditto.) * libc/string/strlwr.S: (Ditto.) * libc/string/strncasecmp.S: (Ditto.) * libc/string/strncat.S: (Ditto.) * libc/string/strncmp.S: (Ditto.) * libc/string/strncpy.S: (Ditto.) * libc/string/strnlen.S: (Ditto.) * libc/string/strrchr.S: (Ditto.) * libc/string/strrev.S: (Ditto.) * libc/string/strsep.S: (Ditto.) * libc/string/strstr.S: (Ditto.) * libc/string/strtok_r.S: (Ditto.) * libc/string/strupr.S: (Ditto.) * libm/fplib/addsf3x.S: (Ditto.) * libm/fplib/asin.S: (Ditto.) * libm/fplib/atan2.S: (Ditto.) * libm/fplib/dtostre.S: (Ditto.) * libm/fplib/dtostrf.S: (Ditto.) * libm/fplib/exp.S: (Ditto.) * libm/fplib/floatsisf.S: (Ditto.) * libm/fplib/fmod.S: (Ditto.) * libm/fplib/fp_cosinus.S: (Ditto.) * libm/fplib/fp_merge.S: (Ditto.) * libm/fplib/fp_powerseries.S: (Ditto.) * libm/fplib/fp_split.S: (Ditto.) * libm/fplib/frexp.S: (Ditto.) * libm/fplib/ldexp.S: (Ditto.) * libm/fplib/log.S: (Ditto.) * libm/fplib/mulsf3x.S: (Ditto.) * libm/fplib/sin.S: (Ditto.) * libm/fplib/strtod.S: (Ditto.) * libm/fplib/tan.S: (Ditto.) * libm/fplib/tanh.S: (Ditto.) 2005-09-12 Joerg Wunsch * include/avr/iomxx0_1.h: change vector names to current avr-libc style. 2005-09-12 Joerg Wunsch Add a library version API, task #4597: add * configure.ac: Add all the hooks to assemble the library version number from its pieces, and substitute the result wherever it's needed. * include/avr/version.h.in: New file. * include/avr/Makefile.am: add version.h.in and the logic to create version.h out of it. * include/avr/io.h: include for backwards- compatible tests. 2005-09-09 Joerg Wunsch * include/avr/sleep.h: Fix sleep mode definitions for the AT94K devices. [Fixes bug #12735: No support for AT94K devices in sleep.h] 2005-09-09 Joerg Wunsch * include/stdio.h: Escape # to fix doxygen warning. * include/avr/delay.h: (Ditto.) * include/avr/sfr_defs.h: (Ditto.) 2005-09-08 Joerg Wunsch [bug #14266: use __extension__ in avr-libc header files] * include/avr/boot.h: Use __extension__ for brace groups that return an expression value. * include/avr/parity.h: (Ditto.) * include/avr/pgmspace.h: (Ditto.) Document exported types and defines. 2005-09-07 Anatoly Sokolov * include/avr/eeprom.h (eeprom_is_ready): Add new version for AT86RF401 [Fixed bug #14378] 2005-09-07 Joerg Wunsch * include/inttypes.h: fix a doxygen markup comment. 2005-09-07 Joerg Wunsch * include/avr/sleep.h: sleep type 2 has a few extensions (tiny2313, tiny13, tiny26), fix these; make the doxygen docs work again [bug #12496: about set_sleep_mode() and tiny26/tiny2313] 2005-09-07 Joerg Wunsch Make "make distcheck" finally work again: * Makefile.am: set DISTCHECK_CONFIGURE_FLAGS. * configure.ac (AM_INIT_AUTOMAKE): move from gzip to bzip2 distfile. * scripts/Makefile.am: add avr-man.in to EXTRA_DIST, fix location of stamp-h1 dependecny. 2005-09-07 Joerg Wunsch * include/avr/interrupt.h: Fix description of sei() [bug #13557 overview: small typo in avr-libc-user-manual-1.2.3], emit faked function prototypes for sei() and sli() within doxygen. 2005-09-07 Anatoly Sokolov * configure.ac: add tests for the ATmega640/1280/1281 support * devtools/gen-avr-lib-tree.sh: add support for ATmega640/1280/1281. * include/avr/io.h: (Ditto.) * include/avr/wdt.h: (Ditto.) * include/avr/iom640.h: new file. * include/avr/iom1280.h: new file. * include/avr/iom1281.h: new file. * include/avr/iomxx0_1.h: new file. * include/avr/Makefile.am: include new files. * crt1/gcrt1.S: add more interrupt vector names. * doc/api/main_page.dox: Document support for ATmega640/1280/1281. * doc/api/using-tools.dox: (Ditto.) 2005-09-06 Joerg Wunsch * include/avr/delay.h: improve documentation, make sure the functions will always be inlined. Fix for bugs: #12495: about Busy-wait delay loops(document) #14224: _delay_ms() not inlining if called more than once in a unit #14433: Improve documentation of 2005-09-06 Joerg Wunsch * include/avr/iomxx4.h: use avr-libc common vector names. 2005-09-06 Joerg Wunsch Fix for bug #12333: Standard requires libstdc to define vprintf and vscanf * include/stdio.h: add prototypes for vscanf() and vprintf(). * libc/stdio/vscanf.c: new file. * libc/stdio/vprintf.c: new file. * libc/stdio/Files.am: add vscanf.c and vprintf.c. 2005-09-06 Joerg Wunsch Contributed by Markus F.X.J. Oberhumer: * include/stdio.h: provide a dummy fflush(); patch #3781: add dummy fflush() to 2005-09-06 Joerg Wunsch * configure.ac: bump version. 2005-09-06 Joerg Wunsch Major API changes of the standard IO facilities. Part of these changes (passing user data to get and put) have been contributed by Ted Roth as patch #3750. * include/stdio.h: implement the new prototype for fdevopen() that allows passing user data to the backend put and get functions; retain a backwards-compatible prototype iff __STDIO_FDEVOPEN_COMPAT_12 is defined before including stdio.h; move definition of struct __file from stdio_internal.h here, so user code will be able to directly declare objects of type FILE; include the udata field in struct __file; add macros fdev_set_udata() and fdev_get_udata() to access the user data field; implement a macro-based, malloc()-free alternative API to fdevopen() consisting of the macros fdev_setup_stream() and FDEV_SETUP_STREAM() together with _FDEV_SETUP_READ, _FDEV_SETUP_WRITE, and _FDEV_SETUP_RW that can be passed to declare the open intent; add _FDEV_ERR and _FDEV_EOF to be returned by the internal get function; add inline macros shadowing the functions clearerr(), feof(), and ferror() (now that struct __file is user-visible); add documentation for all the API changes in the introduction; sub-structure the introductional doxygen comment; remove the "this is likely to be changed in future" warning. * libc/stdio/fdevopen.c (fdevopen): Update dox for new get and put argument types. Change the get() and put() function pointers so that they take the stream as an argument. Remove the definition of __iob[] to avoid the need for dragging in fdevopen() to access the standard streams. * libc/stdio/fgetc.c (fgetc): Pass stream to get() method; set __SERR or __SEOF dependent of the backend's return code. * libc/stdio/fputc.c (fputc): Pass stream to put() method. * libc/stdio/fputs.c (fputs): Ditto. * libc/stdio/fputs_p.c (fputs_P): Ditto. * libc/stdio/fwrite.c (fwrite): Ditto. * libc/stdio/puts.c (puts): Ditto. * libc/stdio/puts_p.c (puts_P): Ditto. * libc/stdio/stdio_private.h: remove struct __file from here. * libc/stdio/iob.c: New file (split off of fdevopen.c). * libc/stdio/Files.am: add iob.c. * doc/examples/twitest/twitest.c: convert to the new stdio API. * libc/stdio/clearerr.c: undef the shadow macro first. * libc/stdio/ferror.c: (Ditto.) * libc/stdio/feof.c: (Ditto.) * libc/stdio/fclose.c: change inttypes.h into stdint.h. * libc/stdio/fgets.c: don't forcibly set __SERR, getc() already handled that. * libc/stdio/gets.c: (Ditto.) * libc/stdio/vfprintf.c: Allocate the fp conversion buffer on the stack as opposed to using malloc(). * libc/stdio/vfscanf.c: (Ditto.) 2005-09-06 Joerg Wunsch * doc/api/faq.dox: Minor clarifications: make the volatile description a bit more detailed, explain that r2 through r15 are available for global register assignment, explain .initN sections better, mention that GCC no longer puts zero-init'ed .data variables into .data. * doc/api/sections.dox: move the C example from .init1 to .init3, and explain that this ensures __zero_reg__ is properly set up already. 2005-09-03 Joerg Wunsch * include/inttypes.h: C99ify, contributed by Carlos Lamas, part of patch #4087: C99 conformal headers stdint.h and inttypes.h 2005-09-03 Joerg Wunsch * doc/api/interrupts.dox: clarify the interrupt behaviour, more explanations, add sub-headlines. * include/avr/signal.h: for the deprecated INTERRUPT() macro, refer to the general description for the recommended way to get the desired behaviour. 2005-09-03 Joerg Wunsch * include/avr/signal.h: deprecate INTERRUPT(). * doc/api/interrupts.dox: remove all vestiges of INTERRUPT(). 2005-09-02 Joerg Wunsch * include/stdint.h: C99ify, contributed by Carlos Lamas, part of patch #4087: C99 conformal headers stdint.h and inttypes.h 2005-09-01 Joerg Wunsch * doc/api/main_page.dox: mention that recent devices' support requires respective support of the toolchain at compile-time. 2005-09-01 Joerg Wunsch Contributed by Markus F.X.J. Oberhumer: * include/stdint.h: use GCC attributes for exact integral types. Avoid -Wlong-long warnings by adding __extension__. Remove obsolete comments. Closes patch #3782 overview: modernize 2005-09-01 Joerg Wunsch * libc/stdlib/ctype.S: Change all branches into RJMPs to guarantee their reachability, closes patch #3912. Contributed by Stefano Rodrigo. 2005-09-01 Joerg Wunsch Implement , closes patch #3780. * include/assert.h: new file. * libc/stdlib/assert.c: new file. * include/Makefile.am: include new file(s). * libc/stdlib/Files.am: (Ditto.) 2005-09-01 Joerg Wunsch * include/avr/iom329.h: add bits for EECR. * include/avr/iom3290.h: (Ditto.) * include/avr/iom649.h: (Ditto.) * include/avr/iom6490.h: (Ditto.) 2005-08-31 Joerg Wunsch * doc/api/sections.dox: catch up with .init4 reality (fix for bug #14262) * include/avr/iomxx4.h: define the EECR bits. * include/avr/eeprom.h: use either EEWE or EEPE in eeprom_is_ready(); fix for bug #14241 2005-08-29 Joerg Wunsch * include/avr/wdt.h: Document the watchdog remaining active after a watchdog reset, and how to turn it off. 2005-08-29 Joerg Wunsch Add support for ATmega164/324/644, contributed by Anatoly Sokolov. * configure.ac: add tests for the ATmega164/324/644 support. * devtools/gen-avr-lib-tree.sh: add support for ATmega164/324/644. * include/avr/io.h: (Ditto.) * include/avr/wdt.h: (Ditto.) * include/avr/iom164.h: new file. * include/avr/iom324.h: new file. * include/avr/iom644.h: new file. * include/avr/iomxx4.h: new file. * include/avr/Makefile.am: include new files. * doc/api/main_page.dox: Document support for ATmega164/324/644. * doc/api/using-tools.dox: (Ditto.) 2005-08-28 Joerg Wunsch Add support for ATtiny25/45/85, contributed by Anatoly Sokolov. * configure.ac: add tests for the ATtiny25/45/85 support. * devtools/gen-avr-lib-tree.sh: add support for ATtiny25/45/85. * include/avr/io.h: (Ditto.) * include/avr/wdt.h: (Ditto.) * include/avr/io.h: (Ditto.) * include/avr/iotn25.h: new file. * include/avr/iotn45.h: new file. * include/avr/iotn85.h: new file. * include/avr/iotnx5.h: new file. * include/avr/Makefile.am: include new files. * doc/api/main_page.dox: Document support for ATtiny25/45/85. * doc/api/using-tools.dox: (Ditto.) 2005-08-18 Joerg Wunsch Submitted by Kai Klenovsek: * doc/api/tools-install.dox: enable DWARF-2 support for GCC. 2005-08-17 Joerg Wunsch * include/avr/io90pwmx.h: remove PORTxy definitions that are duplicated from avr/portpins.h. * libc/stdio/sscanf.c: fix warnings. * libc/stdio/sscanf_p.c: (Ditto.) * libc/stdlib/malloc.c: (Ditto.) * doc/api/Makefile.am: fix standalone build of demo app. 2005-08-16 Joerg Wunsch Add support for ATmega329/3290/649/6490, contributed by Anatoly Sokolov. * configure.ac: add new devices. * devtools/gen-avr-lib-tree.sh: (Ditto.) * include/avr/Makefile.am: add iom329.h/iom3290.h/iom649.h/iom6490.h. * include/avr/io.h: add new devices * include/avr/iom329.h: new file. * include/avr/iom3290.h: new file. * include/avr/iom649.h: new file. * include/avr/iom6490.h: new file. * include/avr/wdt.h: (Ditto.) * doc/api/main_page.dox: document new devices. * doc/api/using-tools.dox: (Ditto.) 2005-08-16 Joerg Wunsch Add support for AT90PWM2/3, contribute by Andrey Pashchenko. * AUTHORS: add Andrey Pashchenko. * configure.ac: add AC_NO_EXECUTABLES to avoid chicken-and-egg situation when configuring without any existing avr-libc; add more quotes (but it still complains), add tests for AT90PWM2/3. * devtools/gen-avr-lib-tree.sh: add AT90PWM2/3. * include/avr/Makefile.am: include io90pwmx.h. * include/avr/io90pwmx.h: new file. * include/avr/io.h: add AT90PWM2/3. * include/avr/wdt.h: (Ditto.) * doc/api/main_page.dox: document the addition of AT90PWM2/3. * doc/api/using-tools.dox: (Ditto.) 2005-08-15 Joerg Wunsch * doc/api/tools-install.dox (avr-libc): fix a missing "tar" command. 2005-08-14 Joerg Wunsch * avr-libc.spec.in: bump required tool versions. * doc/api/Makefile.am: Fix finding demo.fig, add avrs.png. * doc/api/avrs.png-save: New file. * doc/api/doxygen.config.in: Revamp the layout of the HTML pages. * doc/api/dox.css: (Ditto.) * doc/api/dox_html_header: (Ditto.) * doc/api/main_page.dox: Add explanations about the intented standard conformance, as well as about the (non-)reentrancy of our library functions. Other minor corrections. * doc/examples/demo/demo.dox: Reality-check: the AT90S2313 is obsolete, explain usage of ATtiny2313/ATmega8/48/88/168. * doc/api/interrupts.dox: Add name of header file in titles. * doc/api/sfr.dox: (Ditto.) * include/ctype.h: (Ditto.) * include/errno.h: (Ditto.) * include/inttypes.h: (Ditto.) * include/math.h: (Ditto.) * include/setjmp.h: (Ditto.) * include/stdint.h: (Ditto.) * include/stdio.h: (Ditto.) * include/stdlib.h: (Ditto.) * include/string.h: (Ditto.) * include/avr/boot.h: (Ditto.) * include/avr/crc16.h: (Ditto.) * include/avr/delay.h: (Ditto.) * include/avr/eeprom.h: (Ditto.) * include/avr/io.h: (Ditto.) * include/avr/parity.h: (Ditto.) * include/avr/pgmspace.h: (Ditto.) * include/avr/sleep.h: (Ditto.) * include/avr/wdt.h: (Ditto.) * doc/api/assembler.dox: Fix \ref to omit header file names. * doc/api/faq.dox: (Ditto.) 2005-08-13 Joerg Wunsch * doc/api/Makefile.am: add the generation of the demo project back; its output is used as part of the documentation. 2005-08-13 Joerg Wunsch * scripts/Makefile.am: Depend our manually derived targets from $(top_srcdir)/stamp-h1 so they will get reevaluated after re-running configure. * doc/api/Makefile.am: (Ditto) * doc/api/doxygen.config.in: Upgrade for doxygen 1.4.1. * README: Upgrade required version of tools (GCC, doxygen) * configure.ac: (Ditto.) 2005-08-13 Joerg Wunsch * configure.ac: Re-enable building of docs. * doc/api/Makefile.am: manually derive doxygen.config from doxygen.config.in as this is no longer automagic; do no longer try to build the demos as port of the documentation. 2005-08-11 Joerg Wunsch Merge the "autoconf" branch back to HEAD, so we can use current versions of autoconf and automake. Thanks to Ted Roth and Anatoly Sokolov for their nice work on that branch. All copyright notices from the branch files have been brought into the standard form. Changes compared to the "autoconf" branch: * configure.ac (AC_INIT): bump version to 1.3.0.20050810 * configure.ac (AC_CONFIG_SRCDIR): use doc/examples/demo/demo.c as reference file * configure.ac: use $host_alias and $build_alias instead of the deprecated $host and $build, hint about using config.guess for --build, add checks and conditional rules for attiny13, attiny2313, atmega48, atmega88, atmega165, atmega168, atmega325, atmega3250, atmega645, atmega6450, at90can128; remove warning about being work in progress. * AvrCommonLibC.am (libc_a_LIBADD libc_a_DEPENDENCIES): add misc_a_libadd (for the EEPROM libraries) * include/compat/.cvsignore: New file * scripts/.cvsignore: (Ditto.) * include/compat/Makefile.am: (Ditto.) * scripts/Makefile.am: (Ditto.) * Makefile.am (EXTRA_DIST): add ChangeLog-2004 * Makefile.am (SUBDIRS DIST_SUBDIRS): add "scripts" * doc/Makefile.am (EXTRA_DIST): remove avr-libc-reference.html * doc/api/Makefile.am (install-data-local): add INSTALL_DOX_MAN * doc/examples/Makefile.am (EXTRA_DIST): add all-demos.dox, remove the obsolete demos doc/examples/*.[cs] * include/avr/Makefile.am (avr_HEADERS): remove ina90.h and twi.h, add iom165.h, iom325.h, iom3250.h, iom645.h, iom6450.h * include/Makefile.am (avr_HEADERS): add stdint.h * include/Makefile.am (SUBDIRS): add compat * libc/misc/Files.am (misc_a_asm_sources): remove EEPROM files * libc/misc/Files.am (eeprom_asm_sources): add EEPROM files * libc/misc/Rules.am: add logic to build two different sets of EEPROM functions (suffix 1C1D1E and suffix 1F2021) * libc/pmstring/Files.am (pmstring_a_asm_sources): add strnlen_P.S * libc/stdio/Rules.am (PRINTF_CFLAGS): change from -O1 to -Os * libc/stdlib/Files.am (stdlib_a_c_sources): add realloc.c, stdlib_private.h * INSTALL, doc/INSTALL, doc/api/tools-install.dox: remove all references to the old scripts (reconf, doconf, domake), update build instructions. Here are the original ChangeLog entries from the branch (in reverse chronological order): * devtools/gen-avr-lib-tree.sh: use the Posix-portable printf instead of the GNU-only echo -n -e command. * bootstrap: logic in bootstrap to detect auto* versions is changed. * devtools/gen-avr-lib-tree.sh (AVR12_DEV_INFO, AVR3_DEV_INFO, AVR4_DEV_INFO, AVR5_DEV_INFO, AVR_ARH_INFO) : Remove semicolon after last record. * AvrCommon.am: change to compile per-architecture libs * AvrCommonLibC.am: (Ditto.) * configure.ac: (Ditto.) * devtools/gen-avr-lib-tree.sh: (Ditto.) * bootstrap: Update to work with automake 1.9 and autoconf 2.59 * include/avr/io.h: Do not generate an error if the device type is not defined and if defined __COMPILING_AVR_LIBC__. * common/macros.inc: multiple-include protect. * AvrCommonLibC.am (nodist_libc_a_SOURCES): Add libm.a sources to libc.a so that float point libs are available even if the end user forgets to use the -lm to link to the math lib. * AvrCommonLibC.am (nodist_libc_a_SOURCES): Revert addition of libm.a C and asm sources. I forget this change was in my tree when I made the previous change to this file. Will reapply it separately. * .cvsignore: Update to reflect current reality. * common/.cvsignore: New file. * doc/examples/.cvsignore: New file. * include/.cvsignore: New file. * include/avr/.cvsignore: New file. * libc/stdio/.cvsignore: New file. * configure.ac (AC_INIT): Bump version. * AvrCommonLibC.am (nodist_libc_a_SOURCES): Add stubs to trivialize adding C source files to currently asm only lib source dirs. * libc/misc/Files.am (misc_a_c_sources): Define. * libc/pmstring/Files.am (pmstring_a_c_sources): Define. * libc/string/Files.am (string_a_c_sources): Define. * libm/fplib/Files.am (libm_a_c_sources): Define. * devtools/gen-avr-lib-tree.sh: Set CFLAGS for all devices. Stub out DEV_DEFS and DEV_ASFLAGS. Remove un-needed CONF_FRAG. * configure.ac (AC_INIT): Bump version. * devtools/gen-avr-lib-tree.sh: Improve portability by eliminating the use of '<<-EOF' and 'mkdir -p'. Move all the generated copyright headers into a tmp file so only one copy will need to be maintained. * configure.ac (AC_INIT): Bump version. * devtools/gen-avr-lib-tree.sh: Use /bin/sh instead of /bin/bash in the she-bang. * AvrCommon.am (AVRLIB_CFLAGS): Add -mmcu option. * AvrCommonLibC.am (avr_LIBRARIES): Don't build the intermediate libraries, just build libc.a directly. * configure.ac (CFLAGS): Set to nothing to override any that the env sets and to suppress the default "-g -O2". Don't set the AVR_CRT_* variables since they are no longer used. * include/avr/io.h: Generate an error if the device type is not defined. * libc/misc/Rules.am: Remove unneeded rules and variables. * libc/pmstring/Rules.am: Ditto. * libc/stdio/Rules.am: Ditto. * libc/stdlib/Rules.am: Ditto. * libc/string/Rules.am: Ditto. * libm/fplib/Rules.am: Ditto. * libc/stdlib/Files.am: Add ctype source files. * libc/stdlib/cty_isfalse.S: New file. * libc/stdlib/isalnum.S: New file. * libc/stdlib/isalpha.S: New file. * libc/stdlib/isascii.S: New file. * libc/stdlib/isblank.S: New file. * libc/stdlib/iscntrl.S: New file. * libc/stdlib/isdigit.S: New file. * libc/stdlib/isprint.S: New file. * libc/stdlib/ispunct.S: New file. * libc/stdlib/isspace.S: New file. * libc/stdlib/isxdigit.S: New file. * libc/stdlib/toascii.S: New file. * libc/stdlib/tolower.S: New file. * libc/stdlib/toupper.S: New file. * AvrCommon.am (VPATH): Add fplib to search path. * AvrCommonLibC.am: Enable building of libm. * configure.ac: Set DOCSDIR so it gets substituted in Makefile.am files. * libm/Makefile.am: Rewrite. * libm/fplib/Files.am: New file. * libm/fplib/Makefile.am: Rewrite. * libm/fplib/Rules.am: New file. * libm/fplib/fplib.inc: Don't redefine __OPTIMIZE__. Gcc-3.4 seems to define it. * libm/fplib/strtod.S: Don't read in SPH if it's not defined for the target device. * configure.ac (AC_INIT): Bump version. * AvrCommonLibC.am: Enable building of libc/ files. * common/Makefile.am: New file. * libc/misc/Files.am: New file. * libc/misc/Makefile.am: Rewrite. * libc/misc/Rules.am: New file. * libc/misc/eeprom.S: Conditional compile only if E2END > 0. * libc/pmstring/Rules.am: New file. * libc/stdio/Files.am: New file. * libc/stdio/Makefile.am: Rewrite. * libc/stdio/Rules.am: New file. * libc/string/Files.am: New file. * libc/string/Makefile.am: Rewrite. * libc/string/Rules.am: New file. * AvrCommon.am: Split C library macros off into AvrCommonLibC.am. * AvrCommonLibC.am: New file. * devtools/gen-avr-lib-tree.sh: Don't include AvrCommonLibC.am for targets that don't support C programming. * libc/Makefile.am: Rewrite. * libc/pmstring/Files.am: New file. * libc/pmstring/Makefile.am: Rewrite. * libc/pmstring/Rules.am: New file. * libc/stdlib/Files.am: New file. * libc/stdlib/Makefile.am: Rewrite. * libc/stdlib/Rules.am: New file. * AvrCommon.am (__install_dir): Use prefix instead of exec_prefix. * crt1/Makefile.am: Complete rewrite. Not much is needed anymore. * include/Makefile.am: Replace EXTRA_DIST with avr_HEADERS so that the headers are installed. * include/avr/Makefile.am: Ditto. * AvrCommon.am: New file. * configure.ac: Add tool check for AS. Move new devices to separate AC_CONFIG_FILES section. * devtools/gen-avr-lib-tree.sh: Look for AvrCommon.am at top level only instead of in avr/lib/. Split out new devices to avoid compile failures with older tool chain. * Makefile.am: Scrap old version and rewrite. * bootstrap: Add temp hook to run gen-avr-lib-tree.sh. * configure.ac: Bump version. Check for avr cross-compiler. Add AC_CONFIG_FILES section for target device dirs in avr/lib/. * devtools/gen-avr-lib-tree.sh: New file. * include/Makefile.am: Add SUBDIRS. * bootstrap: Remove left-over autom4te.cache directory. * configure.ac: New file. * libc/stdlib/Makefile.am (libc_ctype_asm_objs): Fix a comment typo. * Makefile.am (EXTRA_DIST): Remove references to deleted files. Add bootstrap. * bootstrap: New file. * include/Makefile.am: New file. * include/avr/Makefile.am: New file. * config-ml.in: Remove file for autoconf/automake rewrite. * config.sub: Ditto. * configure.in: Ditto. * doconf: Ditto. * dodist: Ditto. * domake: Ditto. * reconf: Ditto. 2005-08-05 Anatoly Sokolov * libc/stdio/fgetc.c (fgetc) : Prevent movement of the pointer over the end of a string. [Fixed bug #12775] 2005-08-03 Joerg Wunsch * INSTALL: emphasize that users ought to use ./doconf. 2005-07-31 Joerg Wunsch (Contributed by Chris Candreva ) * doc/api/sfr.dox: document replacements for sbi/cbi. (Contributed by Bjarne Laursen ) * libm/fplib/strtod.S: fix endptr bug (bug#12646, patch#4137). 2005-07-31 Bjoern Haase * include/avr/eeprom.h: re-write of all functions and documentation update. EEMEM, add. * include/avr/iocan128.h: __EEPROM_REG_LOCATIONS__ define * include/avr/iom165.h, include/avr/iom169.h: Ditto. * include/avr/iom325.h, include/avr/iom3250.h: Ditto. * include/avr/iom645.h, include/avr/iom6450.h: Ditto. * include/avr/iomx8.h: Ditto. * libc/misc/Makefile.am: lib_a_asm_sources modify, eeprom_asm_sources add, lib_a_LIBADD add, lib_a_DEPENDENCIES add rule "%.1C1D1E.o: %.S" add, rule "%.1F2021.o: %.S" add * libc/misc/eeprom.S: complete re-write * AUTHORS: add Bjoern Haase * LICENSE: (Ditto.) 2005-07-29 Joerg Wunsch * include/avr/boot.h: Implement boot_lock_fuse_bits_get() plus some macros for the respective address values. 2005-07-28 Anatoly Sokolov * include/avr/iom16.h: Add comment about ADHSM bit. * include/avr/iocan128.h (ADHSM): Deleted. Add comment about ADHSM bit. * include/avr/iom128.h (ADHSM): (Ditto.) * include/avr/iom64.h (ADHSM): (Ditto.) * include/avr/iom8.h (ADHSM): (Ditto.) * include/avr/iom8535.h (ADHSM): (Ditto.) [Fixed bug #13341] 2005-07-21 Joerg Wunsch * doc/api/doxygen.config.in: Turn PDF hyperlinks off by default; the presence of this option causes the new (pdfelatex-based) LaTeX to turn from DVI to PDF generation. * doc/api/Makefile.am: Enable PDF hyperlinks for the PDF version. Modify the patchomania to properly include longtable (so it works with recent doxygen versions). 2005-07-19 Anatoly Sokolov * Add Anatoly Sokolov to the license file. 2005-07-19 Anatoly Sokolov * include/avr/wdt.h : Add support for ATmega165, ATmega325, ATmega3250, ATmega645, ATmega6450. [Fixed bug #13678] 2005-07-09 Anatoly Sokolov * include/avr/io.h [__COMPILING_AVR_LIBC__] (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io43u32x.h : Mark SFR [0x1C..0x1F] as reserved. * include/avr/io43u35x.h : (Ditto.) * include/avr/io1200.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io2313.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io2323.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io2333.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io2343.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io4414.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io4433.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io4434.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io8515.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io8534.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/io8535.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iocan128.h (EECR, EEDR, EEAR, EEARL, EEARH) : Define. * include/avr/iom8.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom16.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom32.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom64.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom103.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom128.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom161.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom162.h (EECR, EEDR, EEAR, EEARL, EEARH) : Define. * include/avr/iom163.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom165.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom169.h (EECR, EEDR, EEAR, EEARL, EEARH) : Define. * include/avr/iom323.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom325.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom645.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom3250.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom6450.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom8515.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iom8535.h (EECR, EEDR, EEAR, EEARL, EEARH, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iomx8.h (EECR, EEDR, EEAR, EEARL, EEARH) : Define. * include/avr/iotn12.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iotn13.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMPE, EEPE, EERE) : Define. * include/avr/iotn15.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iotn22.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iotn26.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMWE, EEWE, EERE) : Define. * include/avr/iotn28.h (EERIE, EEMWE, EEWE, EERE) : Delete. * include/avr/iotn2313.h (EECR, EEDR, EEAR, EEARL, EERIE, EEMPE, EEPE, EERE) : Define. [Fixed bug #13290] 2005-06-26 Joerg Wunsch * common/gasava.inc: Fix include ordering (bug #12033). * libc/stdlib/ctype.S: Ditto. * libm/fplib/acos.S: Ditto. * libm/fplib/addsf3.S: Ditto. * libm/fplib/addsf3x.S: Ditto. * libm/fplib/asin.S: Ditto. * libm/fplib/atan.S: Ditto. * libm/fplib/ceil.S: Ditto. * libm/fplib/cos.S: Ditto. * libm/fplib/cosh.S: Ditto. * libm/fplib/divsf3.S: Ditto. * libm/fplib/divsf3x.S: Ditto. * libm/fplib/dtostre.S: Ditto. * libm/fplib/exp.S: Ditto. * libm/fplib/fixsfsi.S: Ditto. * libm/fplib/floatsisf.S: Ditto. * libm/fplib/floor.S: Ditto. * libm/fplib/fmod.S: Ditto. * libm/fplib/fp_cmp.S: Ditto. * libm/fplib/fp_cosinus.S: Ditto. * libm/fplib/fp_flashconst.S: Ditto. * libm/fplib/fp_merge.S: Ditto. * libm/fplib/fp_nan.S: Ditto. * libm/fplib/fp_powerseries.S: Ditto. * libm/fplib/fp_split.S: Ditto. * libm/fplib/fp_zero.S: Ditto. * libm/fplib/fplib.inc: Ditto. * libm/fplib/frexp.S: Ditto. * libm/fplib/isinfnan.S: Ditto. * libm/fplib/ldexp.S: Ditto. * libm/fplib/log.S: Ditto. * libm/fplib/log10.S: Ditto. * libm/fplib/modf.S: Ditto. * libm/fplib/mulsf3.S: Ditto. * libm/fplib/mulsf3x.S: Ditto. * libm/fplib/negsf2.S: Ditto. * libm/fplib/pow.S: Ditto. * libm/fplib/sin.S: Ditto. * libm/fplib/sinh.S: Ditto. * libm/fplib/sqrt.S: Ditto. * libm/fplib/strtod.S: Ditto. * libm/fplib/tan.S: Ditto. * libm/fplib/tanh.S: Ditto. 2005-06-28 Anatoly Sokolov * include/avr/io2333.h [!__ASSEMBLER__] (ADC): Define. * include/avr/io43u35x.h (ADCW): Define. * include/avr/io4433.h [!__ASSEMBLER__] (ADC): Define. * include/avr/io4434.h [!__ASSEMBLER__] (ADC): Define. * include/avr/io8534.h [!__ASSEMBLER__] (ADC): Define. * include/avr/io8535.h [!__ASSEMBLER__] (ADC): Define. * include/avr/iocan128.h (ADCW): Define. * include/avr/iom103.h [!__ASSEMBLER__] (ADC): Define. * include/avr/iom16.h [!__ASSEMBLER__] (ADC): Define. (ADCW): Define. * include/avr/iom163.h [!__ASSEMBLER__] (ADC): Define. * include/avr/iom165.h [!__ASSEMBLER__] (ADC): Define. (ADCW): Define. * include/avr/iom169.h (ADCW): Define. * include/avr/iom323.h [!__ASSEMBLER__] (ADC): Define. * include/avr/iom325.h [!__ASSEMBLER__] (ADC): Define. (ADCW): Define. * include/avr/iom3250.h [!__ASSEMBLER__] (ADC): Define. (ADCW): Define. * include/avr/iom645.h [!__ASSEMBLER__] (ADC): Define. (ADCW): Define. * include/avr/iom6450.h [!__ASSEMBLER__] (ADC): Define. (ADCW): Define. * include/avr/iotn15.h [!__ASSEMBLER__] (ADC): Define. [Fixes bug #12134] 2005-06-26 Joerg Wunsch * crt1/gcrt1.S: Defer the initialization of __stack so the linker could actually update this weak symbol (works around a bug in gas). 2005-06-26 Anatoly Sokolov * include/avr/interrupt.h: Exclude redefinition __EICR. [Fixes bug #12993] * NEWS: Update bugs fixed list. Fix wrong bug number. 2005-06-25 Anatoly Sokolov * include/avr/iom169.h: Change SIG_COMPERATOR to SIG_COMPARATOR. * include/avr/iotn26.h: Change SIG_EPROM_READY to SIG_EEPROM_READY. [Fixes bug #12955] * NEWS: Update bugs fixed list. * include/avr/io.h: No undef EERIE if defined SIG_EE_READY 2005-06-24 Anatoly Sokolov * include/avr/iom325.h: Fix bit definition for UCSZ02. * include/avr/iom3250.h: ( Ditto. ) * include/avr/iom645.h: ( Ditto. ) * include/avr/iom6450.h: ( Ditto. ) [Fixes bug #13327] * NEWS: Update bugs fixed list. 2005-06-07 Eric B. Weddington * include/math.h: Fix documenation for log10() function in math.h. [Fixed bug #12785] * NEWS: Update bugs fixed list. 2005-06-07 Eric B. Weddington * include/avr/iocan128.h: Fix bit definition for SJW0. [Fixes bug #12448] * NEWS: Update bugs fixed list. 2005-06-07 Eric B. Weddington * include/avr/iom169.h: Add new bit definitions for LCDCCR register. [Fixes bug #12422] * NEWS: Update bugs fixed list. 2005-04-09 Joerg Wunsch * doc/examples/demo/demo.c: update for ATmega16. 2005-02-14 Joerg Wunsch * doc/api/faq.dox: sbi() has been removed, document standard C bit operators instead (fixes savannah bug #12040); mention that external RAM initialization as a C function would preferrably go into .init3 where __zero_reg__ has already been initialized. * doc/api/sections.dox: mention that .init2 also clears __zero_reg__, remove old outp() macro usage in example code. 2005-02-14 Joerg Wunsch * libc/stdio/vfscanf.c: fix field width accounting for leading signs and/or 0/0x prefixes. Fixes bug #11987. 2005-02-08 Eric B. Weddington * libc/stdio/Makefile.am: Change optimisation level for building printf libraries to -Os. [Fixes bug #11898] * NEWS: Update bugs fixed list. 2005-02-08 Joerg Wunsch * libc/stdlib/realloc.c: fix bug #11868. Fix submitted by Peter Fuhrmann 2005-02-07 Eric B. Weddington * doc/api/main_page.dox: Remove the untested label on devices list. 2005-02-07 Eric B. Weddington * doc/examples/twitest/twitest.c: Replace SYSCLK with F_CPU. [Fixes bug #11817] * NEWS: Update bugs fixed list. 2005-02-01 Eric B. Weddington * libm/fplib/sin.S: Fix call to __fp_cosinus. [Fixes bug #11805] * NEWS: Update bugs fixed list. 2005-01-27 Joerg Wunsch * doc/examples/Makefile.am (EXTRA_DIST): add all-demos.dox. 2005-01-25 Eric B. Weddington * doc/examples/progmem.c: Update to use the latest API. [Fixes bug #11732] * NEWS: Update bugs fixed list. 2005-01-24 Joerg Wunsch * libc/stdlib/strtol.c: Dmitry Xmelkov's fixes and speedups for strtol and strtoul (check base against legal values, correctly report ERANGE on under-/overflow, avoid costly division for common base values, parse string "0x" correctly as 0 with returning the "x" as final string); bugfix for savannah bug #11494, and savannah patch #3618. * libc/stdlib/strtoul.c: Ditto. * AUTHORS: Mention Dmitry Xmelkov for his contribution. 2005-01-24 Joerg Wunsch * doc/api/acknowledge.dox: Mention Ted Roth, fix Eric's email address. * doc/api/tools-install.dox: Remove all explicit version numbers, recommend the latest released version instead. * doc/api/faq.dox: minor cleanup to the ROM string example. 2005-01-23 Joerg Wunsch * libc/stdlib/realloc.c: Do not mess with "nx" pointers for the current entry as it is not really of struct __freelist. Fixes savannah bug #11684. 2005-01-18 Joerg Wunsch Implement savannah patch #3516: %S format for printf(). * AUTHORS: Mention Helmut Wallner for his contribution. * include/stdio.h: Document the new %S format. * include/avr/pgmspace.h: Prototype for new strnlen_P() function. * libc/pmstring/Makefile.am: Include strnlen_P.S. * libc/stdio/vfprintf.c: Add implementation for %S. 2005-01-16 Joerg Wunsch * include/setjmp.h: Document that longjmp() might destroy global register variables; see savannah bug #4101. 2005-01-13 Joerg Wunsch * include/avr/eeprom.h: Document all devices that are not supported by the library routines; add a #warning as well. 2005-01-12 Eric B. Weddington * LICENSE: Update copyright year. 2005-01-10 Eric B. Weddington * include/avr/wdt.h: Rewrite wdt_disable() to match datasheet algorithm. [Fix for bug #11522] * NEWS: Update bugs fixed list. 2005-01-09 Joerg Wunsch * libm/fplib/ldexp.S: remove jump to itself. * libm/fplib/ceil.S: translate German comments, drop IBM437 chars. 2005-01-09 Joerg Wunsch * libm/fplib/addsf3.S: Make labels local, add Id line. * libm/fplib/addsf3x.S: (Ditto.) * libm/fplib/asin.S: (Ditto.) * libm/fplib/ceil.S: (Ditto.) * libm/fplib/cos.S: (Ditto.) * libm/fplib/cosh.S: (Ditto.) * libm/fplib/divsf3.S: (Ditto.) * libm/fplib/divsf3x.S: (Ditto.) * libm/fplib/exp.S: (Ditto.) * libm/fplib/fixsfsi.S: (Ditto.) * libm/fplib/floatsisf.S: (Ditto.) * libm/fplib/floor.S: (Ditto.) * libm/fplib/fp_cmp.S: (Ditto.) * libm/fplib/fp_cosinus.S: (Ditto.) * libm/fplib/fp_flashconst.S: (Ditto.) * libm/fplib/fp_merge.S: (Ditto.) * libm/fplib/fp_nan.S: (Ditto.) * libm/fplib/fp_powerseries.S: (Ditto.) * libm/fplib/fp_split.S: (Ditto.) * libm/fplib/fp_zero.S: (Ditto.) * libm/fplib/frexp.S: (Ditto.) * libm/fplib/ldexp.S: (Ditto.) * libm/fplib/log.S: (Ditto.) * libm/fplib/log10.S: (Ditto.) * libm/fplib/modf.S: (Ditto.) * libm/fplib/mulsf3.S: (Ditto.) * libm/fplib/mulsf3x.S: (Ditto.) * libm/fplib/negsf2.S: (Ditto.) * libm/fplib/pow.S: (Ditto.) * libm/fplib/sin.S: (Ditto.) * libm/fplib/sinh.S: (Ditto.) * libm/fplib/sqrt.S: (Ditto.) * libm/fplib/strtod.S: (Ditto.) * libm/fplib/tan.S: (Ditto.) * libm/fplib/tanh.S: (Ditto.) 2005-01-07 Joerg Wunsch * libm/fplib/asin.S: prefix internal global symbols with "__fp_". * libm/fplib/atan.S: (Ditto.) * libm/fplib/cos.S: (Ditto.) * libm/fplib/cosh.S: (Ditto.) * libm/fplib/divsf3.S: (Ditto.) * libm/fplib/exp.S: (Ditto.) * libm/fplib/fp_cosinus.S: (Ditto.) * libm/fplib/fp_flashconst.S: (Ditto.) * libm/fplib/fp_powerseries.S: (Ditto.) * libm/fplib/log.S: (Ditto.) * libm/fplib/sinh.S: (Ditto.) * libm/fplib/strtod.S: (Ditto.) * libm/fplib/tan.S: (Ditto.) 2005-01-07 Eric B. Weddington * include/avr/sfr_defs.h: Remove doxygen comment about the deprecated inp/outp items. [Fix for bug #11505] * NEWS: Update bugs fixed list. 2005-01-06 Eric B. Weddington * include/avr/iom16.h: Put the port bit defintions back in for mega16. [Fix for bug #11486] * include/avr/iom16.h: Remove Windows line endings. 2005-01-06 Eric B. Weddington * include/avr/wdt.h: Abstract the change enable bit for the mega32. [Fix for bug #11510] 2005-01-03 Eric B. Weddington * include/avr/iotn26.h: Add missing pin definitions. [Fix for bug #11479] 2005-01-03 Eric B. Weddington * include/avr/iotn26.h: Get rid of Windows line endings. 2005-01-01 Joerg Wunsch * Makefile.am (install-data-local uninstall-local): Do also install .../include/compat. While being here, repair uninstalling the entire world as well. For older changes see ChangeLog-2004 avr-libc-1.8.0.orig/config.guess0000555000000000000000000012206511732702554013376 0ustar #! /bin/sh # Attempt to guess a canonical system name. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, # 2000, 2001, 2002, 2003 Free Software Foundation, Inc. timestamp='2003-07-02' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 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The machine name # can be virtually everything (everything which is not # "atarist" or "atariste" at least should have a processor # > m68000). The system name ranges from "MiNT" over "FreeMiNT" # to the lowercase version "mint" (or "freemint"). Finally # the system name "TOS" denotes a system which is actually not # MiNT. But MiNT is downward compatible to TOS, so this should # be no problem. atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) echo m68k-milan-mint${UNAME_RELEASE} exit 0 ;; hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) echo m68k-hades-mint${UNAME_RELEASE} exit 0 ;; *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) echo m68k-unknown-mint${UNAME_RELEASE} exit 0 ;; powerpc:machten:*:*) echo powerpc-apple-machten${UNAME_RELEASE} exit 0 ;; RISC*:Mach:*:*) echo mips-dec-mach_bsd4.3 exit 0 ;; RISC*:ULTRIX:*:*) echo mips-dec-ultrix${UNAME_RELEASE} exit 0 ;; VAX*:ULTRIX*:*:*) echo vax-dec-ultrix${UNAME_RELEASE} exit 0 ;; 2020:CLIX:*:* | 2430:CLIX:*:*) echo clipper-intergraph-clix${UNAME_RELEASE} exit 0 ;; mips:*:*:UMIPS | mips:*:*:RISCos) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #ifdef __cplusplus #include /* for printf() prototype */ int main (int argc, char *argv[]) { #else int main (argc, argv) int argc; char *argv[]; { #endif #if defined (host_mips) && defined (MIPSEB) #if defined (SYSTYPE_SYSV) printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_SVR4) printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); #endif #endif exit (-1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c \ && $dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \ && exit 0 echo mips-mips-riscos${UNAME_RELEASE} exit 0 ;; Motorola:PowerMAX_OS:*:*) echo powerpc-motorola-powermax exit 0 ;; Motorola:*:4.3:PL8-*) echo powerpc-harris-powermax exit 0 ;; Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) echo powerpc-harris-powermax exit 0 ;; Night_Hawk:Power_UNIX:*:*) echo powerpc-harris-powerunix exit 0 ;; m88k:CX/UX:7*:*) echo m88k-harris-cxux7 exit 0 ;; m88k:*:4*:R4*) echo m88k-motorola-sysv4 exit 0 ;; m88k:*:3*:R3*) echo m88k-motorola-sysv3 exit 0 ;; AViiON:dgux:*:*) # DG/UX returns AViiON for all architectures UNAME_PROCESSOR=`/usr/bin/uname -p` if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] then if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ [ ${TARGET_BINARY_INTERFACE}x = x ] then echo m88k-dg-dgux${UNAME_RELEASE} else echo m88k-dg-dguxbcs${UNAME_RELEASE} fi else echo i586-dg-dgux${UNAME_RELEASE} fi exit 0 ;; M88*:DolphinOS:*:*) # DolphinOS (SVR3) echo m88k-dolphin-sysv3 exit 0 ;; M88*:*:R3*:*) # Delta 88k system running SVR3 echo m88k-motorola-sysv3 exit 0 ;; XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) echo m88k-tektronix-sysv3 exit 0 ;; Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) echo m68k-tektronix-bsd exit 0 ;; *:IRIX*:*:*) echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` exit 0 ;; ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX ' i*86:AIX:*:*) echo i386-ibm-aix exit 0 ;; ia64:AIX:*:*) if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} exit 0 ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include main() { if (!__power_pc()) exit(1); puts("powerpc-ibm-aix3.2.5"); exit(0); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 echo rs6000-ibm-aix3.2.5 elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then echo rs6000-ibm-aix3.2.4 else echo rs6000-ibm-aix3.2 fi exit 0 ;; *:AIX:*:[45]) IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then IBM_ARCH=rs6000 else IBM_ARCH=powerpc fi if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${IBM_ARCH}-ibm-aix${IBM_REV} exit 0 ;; *:AIX:*:*) echo rs6000-ibm-aix exit 0 ;; ibmrt:4.4BSD:*|romp-ibm:BSD:*) echo romp-ibm-bsd4.4 exit 0 ;; ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to exit 0 ;; # report: romp-ibm BSD 4.3 *:BOSX:*:*) echo rs6000-bull-bosx exit 0 ;; DPX/2?00:B.O.S.:*:*) echo m68k-bull-sysv3 exit 0 ;; 9000/[34]??:4.3bsd:1.*:*) echo m68k-hp-bsd exit 0 ;; hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) echo m68k-hp-bsd4.4 exit 0 ;; 9000/[34678]??:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` case "${UNAME_MACHINE}" in 9000/31? ) HP_ARCH=m68000 ;; 9000/[34]?? ) HP_ARCH=m68k ;; 9000/[678][0-9][0-9]) if [ -x /usr/bin/getconf ]; then sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` case "${sc_cpu_version}" in 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 532) # CPU_PA_RISC2_0 case "${sc_kernel_bits}" in 32) HP_ARCH="hppa2.0n" ;; 64) HP_ARCH="hppa2.0w" ;; '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 esac ;; esac fi if [ "${HP_ARCH}" = "" ]; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #define _HPUX_SOURCE #include #include int main () { #if defined(_SC_KERNEL_BITS) long bits = sysconf(_SC_KERNEL_BITS); #endif long cpu = sysconf (_SC_CPU_VERSION); switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0"); break; case CPU_PA_RISC1_1: puts ("hppa1.1"); break; case CPU_PA_RISC2_0: #if defined(_SC_KERNEL_BITS) switch (bits) { case 64: puts ("hppa2.0w"); break; case 32: puts ("hppa2.0n"); break; default: puts ("hppa2.0"); break; } break; #else /* !defined(_SC_KERNEL_BITS) */ puts ("hppa2.0"); break; #endif default: puts ("hppa1.0"); break; } exit (0); } EOF (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` test -z "$HP_ARCH" && HP_ARCH=hppa fi ;; esac if [ ${HP_ARCH} = "hppa2.0w" ] then # avoid double evaluation of $set_cc_for_build test -n "$CC_FOR_BUILD" || eval $set_cc_for_build if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E -) | grep __LP64__ >/dev/null then HP_ARCH="hppa2.0w" else HP_ARCH="hppa64" fi fi echo ${HP_ARCH}-hp-hpux${HPUX_REV} exit 0 ;; ia64:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` echo ia64-hp-hpux${HPUX_REV} exit 0 ;; 3050*:HI-UX:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include int main () { long cpu = sysconf (_SC_CPU_VERSION); /* The order matters, because CPU_IS_HP_MC68K erroneously returns true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct results, however. */ if (CPU_IS_PA_RISC (cpu)) { switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; default: puts ("hppa-hitachi-hiuxwe2"); break; } } else if (CPU_IS_HP_MC68K (cpu)) puts ("m68k-hitachi-hiuxwe2"); else puts ("unknown-hitachi-hiuxwe2"); exit (0); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 echo unknown-hitachi-hiuxwe2 exit 0 ;; 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) echo hppa1.1-hp-bsd exit 0 ;; 9000/8??:4.3bsd:*:*) echo hppa1.0-hp-bsd exit 0 ;; *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) echo hppa1.0-hp-mpeix exit 0 ;; hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) echo hppa1.1-hp-osf exit 0 ;; hp8??:OSF1:*:*) echo hppa1.0-hp-osf exit 0 ;; i*86:OSF1:*:*) if [ -x /usr/sbin/sysversion ] ; then echo ${UNAME_MACHINE}-unknown-osf1mk else echo ${UNAME_MACHINE}-unknown-osf1 fi exit 0 ;; parisc*:Lites*:*:*) echo hppa1.1-hp-lites exit 0 ;; C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) echo c1-convex-bsd exit 0 ;; C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit 0 ;; C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) echo c34-convex-bsd exit 0 ;; C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) echo c38-convex-bsd exit 0 ;; C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) echo c4-convex-bsd exit 0 ;; CRAY*Y-MP:*:*:*) echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*[A-Z]90:*:*:*) echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*TS:*:*:*) echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*T3E:*:*:*) echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*SV1:*:*:*) echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; *:UNICOS/mp:*:*) echo nv1-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit 0 ;; i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} exit 0 ;; sparc*:BSD/OS:*:*) echo sparc-unknown-bsdi${UNAME_RELEASE} exit 0 ;; *:BSD/OS:*:*) echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} exit 0 ;; *:FreeBSD:*:*|*:GNU/FreeBSD:*:*) # Determine whether the default compiler uses glibc. eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include #if __GLIBC__ >= 2 LIBC=gnu #else LIBC= #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` # GNU/FreeBSD systems have a "k" prefix to indicate we are using # FreeBSD's kernel, but not the complete OS. case ${LIBC} in gnu) kernel_only='k' ;; esac echo ${UNAME_MACHINE}-unknown-${kernel_only}freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`${LIBC:+-$LIBC} exit 0 ;; i*:CYGWIN*:*) echo ${UNAME_MACHINE}-pc-cygwin exit 0 ;; i*:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 exit 0 ;; i*:PW*:*) echo ${UNAME_MACHINE}-pc-pw32 exit 0 ;; x86:Interix*:[34]*) echo i586-pc-interix${UNAME_RELEASE}|sed -e 's/\..*//' exit 0 ;; [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) echo i${UNAME_MACHINE}-pc-mks exit 0 ;; i*:Windows_NT*:* | Pentium*:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we # UNAME_MACHINE based on the output of uname instead of i386? echo i586-pc-interix exit 0 ;; i*:UWIN*:*) echo ${UNAME_MACHINE}-pc-uwin exit 0 ;; p*:CYGWIN*:*) echo powerpcle-unknown-cygwin exit 0 ;; prep*:SunOS:5.*:*) echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; *:GNU:*:*) echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` exit 0 ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix exit 0 ;; arm*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; cris:Linux:*:*) echo cris-axis-linux-gnu exit 0 ;; ia64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; m68*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; mips:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips #undef mipsel #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mipsel #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips #else CPU= #endif #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 ;; mips64:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips64 #undef mips64el #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mips64el #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips64 #else CPU= #endif #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 ;; ppc:Linux:*:*) echo powerpc-unknown-linux-gnu exit 0 ;; ppc64:Linux:*:*) echo powerpc64-unknown-linux-gnu exit 0 ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in EV5) UNAME_MACHINE=alphaev5 ;; EV56) UNAME_MACHINE=alphaev56 ;; PCA56) UNAME_MACHINE=alphapca56 ;; PCA57) UNAME_MACHINE=alphapca56 ;; EV6) UNAME_MACHINE=alphaev6 ;; EV67) UNAME_MACHINE=alphaev67 ;; EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} exit 0 ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in PA7*) echo hppa1.1-unknown-linux-gnu ;; PA8*) echo hppa2.0-unknown-linux-gnu ;; *) echo hppa-unknown-linux-gnu ;; esac exit 0 ;; parisc64:Linux:*:* | hppa64:Linux:*:*) echo hppa64-unknown-linux-gnu exit 0 ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux exit 0 ;; sh64*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; sh*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; sparc:Linux:*:* | sparc64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; x86_64:Linux:*:*) echo x86_64-unknown-linux-gnu exit 0 ;; i*86:Linux:*:*) # The BFD linker knows what the default object file format is, so # first see if it will tell us. cd to the root directory to prevent # problems with other programs or directories called `ld' in the path. # Set LC_ALL=C to ensure ld outputs messages in English. ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ | sed -ne '/supported targets:/!d s/[ ][ ]*/ /g s/.*supported targets: *// s/ .*// p'` case "$ld_supported_targets" in elf32-i386) TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" ;; a.out-i386-linux) echo "${UNAME_MACHINE}-pc-linux-gnuaout" exit 0 ;; coff-i386) echo "${UNAME_MACHINE}-pc-linux-gnucoff" exit 0 ;; "") # Either a pre-BFD a.out linker (linux-gnuoldld) or # one that does not give us useful --help. echo "${UNAME_MACHINE}-pc-linux-gnuoldld" exit 0 ;; esac # Determine whether the default compiler is a.out or elf eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include #ifdef __ELF__ # ifdef __GLIBC__ # if __GLIBC__ >= 2 LIBC=gnu # else LIBC=gnulibc1 # endif # else LIBC=gnulibc1 # endif #else #ifdef __INTEL_COMPILER LIBC=gnu #else LIBC=gnuaout #endif #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` test x"${LIBC}" != x && echo "${UNAME_MACHINE}-pc-linux-${LIBC}" && exit 0 test x"${TENTATIVE}" != x && echo "${TENTATIVE}" && exit 0 ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. # earlier versions are messed up and put the nodename in both # sysname and nodename. echo i386-sequent-sysv4 exit 0 ;; i*86:UNIX_SV:4.2MP:2.*) # Unixware is an offshoot of SVR4, but it has its own version # number series starting with 2... # I am not positive that other SVR4 systems won't match this, # I just have to hope. -- rms. # Use sysv4.2uw... so that sysv4* matches it. echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} exit 0 ;; i*86:OS/2:*:*) # If we were able to find `uname', then EMX Unix compatibility # is probably installed. echo ${UNAME_MACHINE}-pc-os2-emx exit 0 ;; i*86:XTS-300:*:STOP) echo ${UNAME_MACHINE}-unknown-stop exit 0 ;; i*86:atheos:*:*) echo ${UNAME_MACHINE}-unknown-atheos exit 0 ;; i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) echo i386-unknown-lynxos${UNAME_RELEASE} exit 0 ;; i*86:*DOS:*:*) echo ${UNAME_MACHINE}-pc-msdosdjgpp exit 0 ;; i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} else echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} fi exit 0 ;; i*86:*:5:[78]*) case `/bin/uname -X | grep "^Machine"` in *486*) UNAME_MACHINE=i486 ;; *Pentium) UNAME_MACHINE=i586 ;; *Pent*|*Celeron) UNAME_MACHINE=i686 ;; esac echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} exit 0 ;; i*86:*:3.2:*) if test -f /usr/options/cb.name; then UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ && UNAME_MACHINE=i586 (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ && UNAME_MACHINE=i686 (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ && UNAME_MACHINE=i686 echo ${UNAME_MACHINE}-pc-sco$UNAME_REL else echo ${UNAME_MACHINE}-pc-sysv32 fi exit 0 ;; pc:*:*:*) # Left here for compatibility: # uname -m prints for DJGPP always 'pc', but it prints nothing about # the processor, so we play safe by assuming i386. echo i386-pc-msdosdjgpp exit 0 ;; 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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ftoa_engine.h 1218 2007-02-18 13:18:41Z dmix $ */ #ifndef _FTOA_ENGINE_H #define _FTOA_ENGINE_H #ifndef __ASSEMBLER__ int __ftoa_engine (double val, char *buf, unsigned char prec, unsigned char maxdgs); #endif /* '__ftoa_engine' return next flags (in buf[0]): */ #define FTOA_MINUS 1 #define FTOA_ZERO 2 #define FTOA_INF 4 #define FTOA_NAN 8 #define FTOA_CARRY 16 /* Carry was to master position. */ #endif /* !_FTOA_ENGINE_H */ avr-libc-1.8.0.orig/common/gasava.inc0000644000000000000000000000345711732702554014310 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _GAS_AVA_INC #define _GAS_AVA_INC # include "ctoasm.inc" /* # define TEXT_SEG(subs, func) .section .text.##subs, "ax", @progbits ; func */ # define GLOBAL(x) _U(x): .global _U(x) # define FUNCTION(x) .func _U(x) # define ENDFUNC .endfunc #endif /* _GAS_AVA_INC */ avr-libc-1.8.0.orig/common/Makefile.in0000644000000000000000000002600011732702554014405 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2004, Theodore A. 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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SECTIONNAME_H__ #define __SECTIONNAME_H__ /* Put all avr-libc functions in a common, unique sub-section name under .text. */ #define CLIB_SECTION .text.avr-libc #define MLIB_SECTION .text.avr-libc.fplib #define STR(x) _STR(x) #define _STR(x) #x #define ATTRIBUTE_CLIB_SECTION __attribute__ ((section (STR(CLIB_SECTION)))) #define ATTRIBUTE_MLIB_SECTION __attribute__ ((section (STR(MLIB_SECTION)))) #define ASSEMBLY_CLIB_SECTION .section CLIB_SECTION, "ax", @progbits #define ASSEMBLY_MLIB_SECTION .section MLIB_SECTION, "ax", @progbits #endif avr-libc-1.8.0.orig/common/ctoasm.inc0000644000000000000000000000711311732702554014325 0ustar /* Copyright (c) 1999, Michael Stumpf All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* CtoASM.inc Specify the parameter passing from C functions Michael Stumpf, (c) 9. August 1999 */ #ifndef __CTOASM_INC #define __CTOASM_INC #define rP0 r25 /* first incoming parameter (MSB) */ #define rP1 r24 /* 2nd incoming parameter */ #define rP2 r23 /* 3rd incoming parameter */ #define rP3 r22 /* 4th incoming parameter */ #define rP4 r21 /* */ #define rP5 r20 /* */ #define rP6 r19 /* */ #define rP7 r18 /* */ #define rByte r24 /* a function returning a byte passes this as if it was an integer in R25:R24, but R25 is unused */ /* Temporary registers, usable without saving, maybe clobbered after an external function call */ #if !defined(__tmp_reg__) #if defined(__AVR_TINY__) #define __tmp_reg__ r16 #else #define __tmp_reg__ r0 #endif #endif /* The zero constant register MUST be cleared on return. */ #if !defined(__zero_reg__) #if defined(__AVR_TINY__) #define __zero_reg__ r17 #else #define __zero_reg__ r1 #endif #endif #define rTI0 r31 /* 1st temporary with immidiate */ #define rTI1 r30 /* 2nd temporary with immidiate */ #define rTI2 r27 /* 3rd temporary with immidiate */ #define rTI3 r26 /* 4th temporary with immidiate */ /* registers wich have to be saved */ #define rSI0 r17 /* first saved (pushed) register with immidiate */ #define rSI1 r16 /* 2nd push register */ #define rSI2 r29 /* 3rd saved (pushed) register */ #define rSI3 r28 /* 4th saved (pushed) register */ #define rS0 r15 /* 3rd pushed register */ #define rS1 r14 /* 4th pushed register */ #define rS2 r13 /* */ #define rS3 r12 /* */ #define rS4 r11 /* */ #define rS5 r10 /* */ #define rS6 r9 /* */ #define rS7 r8 /* */ #define rS8 r7 /* */ #define rS9 r6 /* */ #define rS10 r5 /* */ #define rS11 r4 /* */ #define rS12 r3 /* */ #define rS13 r2 /* */ #endif /* __CTOASM_INC */ avr-libc-1.8.0.orig/common/ntz.h0000644000000000000000000000447511732702554013340 0ustar /* Copyright (c) 2007, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ntz.h 1217 2007-02-18 13:18:05Z dmix $ */ #ifndef _NTZ_H #define _NTZ_H /* Number of Tail Zeros: ntz(x)= (ffs(x) ? ffs(x)-1 : 16) It works with all: cpp, gcc and gas expressions. */ #define ntz(x) \ ( (1 & (((x) & 1) == 0)) \ + (1 & (((x) & 3) == 0)) \ + (1 & (((x) & 7) == 0)) \ + (1 & (((x) & 017) == 0)) \ + (1 & (((x) & 037) == 0)) \ + (1 & (((x) & 077) == 0)) \ + (1 & (((x) & 0177) == 0)) \ + (1 & (((x) & 0377) == 0)) \ + (1 & (((x) & 0777) == 0)) \ + (1 & (((x) & 01777) == 0)) \ + (1 & (((x) & 03777) == 0)) \ + (1 & (((x) & 07777) == 0)) \ + (1 & (((x) & 017777) == 0)) \ + (1 & (((x) & 037777) == 0)) \ + (1 & (((x) & 077777) == 0)) \ + (1 & (((x) & 0177777) == 0)) ) #endif /* !_NTZ_H */ avr-libc-1.8.0.orig/common/Makefile.am0000644000000000000000000000331211732702554014375 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 2008 2009-07-01 14:14:25Z joerg_wunsch $ # EXTRA_DIST = \ ctoasm.inc \ gasava.inc \ macros.inc \ asmdef.h \ ftoa_engine.h \ ntz.h \ sectionname.h avr-libc-1.8.0.orig/common/macros.inc0000644000000000000000000002231111732702554014320 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* macros.inc - macros for use in assembler sources Contributors: Created by Marek Michalkiewicz */ #include #include "sectionname.h" /* if not defined, assume old version with underscores */ #ifndef __USER_LABEL_PREFIX__ #define __USER_LABEL_PREFIX__ _ #endif #ifndef __REGISTER_PREFIX__ #define __REGISTER_PREFIX__ #endif /* the assembler line separator (just in case it ever changes) */ #define _L $ #define CONCAT1(a, b) CONCAT2(a, b) #define CONCAT2(a, b) a ## b #define _U(x) CONCAT1(__USER_LABEL_PREFIX__, x) #define _R(x) CONCAT1(__REGISTER_PREFIX__, x) /* these should help to fix the "can't have function named r1()" bug which may require adding '%' in front of register names. */ #define r0 _R(r0) #define r1 _R(r1) #define r2 _R(r2) #define r3 _R(r3) #define r4 _R(r4) #define r5 _R(r5) #define r6 _R(r6) #define r7 _R(r7) #define r8 _R(r8) #define r9 _R(r9) #define r10 _R(r10) #define r11 _R(r11) #define r12 _R(r12) #define r13 _R(r13) #define r14 _R(r14) #define r15 _R(r15) #define r16 _R(r16) #define r17 _R(r17) #define r18 _R(r18) #define r19 _R(r19) #define r20 _R(r20) #define r21 _R(r21) #define r22 _R(r22) #define r23 _R(r23) #define r24 _R(r24) #define r25 _R(r25) #define r26 _R(r26) #define r27 _R(r27) #define r28 _R(r28) #define r29 _R(r29) #define r30 _R(r30) #define r31 _R(r31) #if !defined(__tmp_reg__) #if defined(__AVR_TINY__) #define __tmp_reg__ r16 #else #define __tmp_reg__ r0 #endif #endif #if !defined(__zero_reg__) #if defined(__AVR_TINY__) #define __zero_reg__ r17 #else #define __zero_reg__ r1 #endif #endif #if __AVR_MEGA__ #define XJMP jmp #define XCALL call #else #define XJMP rjmp #define XCALL rcall #endif /* used only by fplib/strtod.S - libgcc internal function calls */ #define PROLOGUE_SAVES(offset) XJMP (__prologue_saves__ + 2 * (offset)) #define EPILOGUE_RESTORES(offset) XJMP (__epilogue_restores__ + 2 * (offset)) #if FLASHEND > 0x10000 /* ATmega103 */ #define BIG_CODE 1 #else #define BIG_CODE 0 #endif #ifndef __AVR_HAVE_MOVW__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_MOVW__ 1 # endif #endif #ifndef __AVR_HAVE_LPMX__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_LPMX__ 1 # endif #endif #ifndef __AVR_HAVE_MUL__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_MUL__ 1 # endif #endif /* Smart version of movw: - uses "movw" if possible (supported by MCU, and both registers even) - handles overlapping register pairs correctly - no instruction generated if source and destination are the same (may expand to 0, 1 or 2 instructions). */ .macro X_movw dst src .L_movw_dst = -1 .L_movw_src = -1 .L_movw_n = 0 .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \ r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \ r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \ r30,r31 .ifc \reg,\dst .L_movw_dst = .L_movw_n .endif .ifc \reg,\src .L_movw_src = .L_movw_n .endif .L_movw_n = .L_movw_n + 1 .endr .L_movw_n = 0 .irp reg, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \ R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \ R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \ R30,R31 .ifc \reg,\dst .L_movw_dst = .L_movw_n .endif .ifc \reg,\src .L_movw_src = .L_movw_n .endif .L_movw_n = .L_movw_n + 1 .endr .if .L_movw_dst < 0 .L_movw_n = 0 .rept 32 .if \dst == .L_movw_n .L_movw_dst = .L_movw_n .endif .L_movw_n = .L_movw_n + 1 .endr .endif .if .L_movw_src < 0 .L_movw_n = 0 .rept 32 .if \src == .L_movw_n .L_movw_src = .L_movw_n .endif .L_movw_n = .L_movw_n + 1 .endr .endif .if (.L_movw_dst < 0) || (.L_movw_src < 0) .err ; Invalid 'X_movw' arg. .endif .if ((.L_movw_src) - (.L_movw_dst)) /* different registers */ .if (((.L_movw_src) | (.L_movw_dst)) & 0x01) .if (((.L_movw_src)-(.L_movw_dst)) & 0x80) /* src < dest */ mov (.L_movw_dst)+1, (.L_movw_src)+1 mov (.L_movw_dst), (.L_movw_src) .else /* src > dest */ mov (.L_movw_dst), (.L_movw_src) mov (.L_movw_dst)+1, (.L_movw_src)+1 .endif .else /* both even -> overlap not possible */ #if defined(__AVR_HAVE_MOVW__) && __AVR_HAVE_MOVW__ movw \dst, \src #else mov (.L_movw_dst), (.L_movw_src) mov (.L_movw_dst)+1, (.L_movw_src)+1 #endif .endif .endif .endm /* Macro 'X_lpm' extends enhanced lpm instruction for classic chips. Usage: X_lpm reg, dst where reg is 0..31, r0..r31 or R0..R31 dst is z, Z, z+ or Z+ It is possible to omit both arguments. Possible results for classic chips: lpm lpm / mov Rd,r0 lpm / adiw ZL,1 lpm / mov Rd,r0 / adiw ZL,1 For enhanced chips it is one instruction always. ATTENTION: unlike enhanced chips SREG (S,V,N,Z,C) flags are changed in case of 'Z+' dst. R0 is scratch. */ .macro X_lpm dst=r0, src=Z /* dst evaluation */ .L_lpm_dst = -1 .L_lpm_n = 0 .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \ r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \ r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \ r30,r31 .ifc \reg,\dst .L_lpm_dst = .L_lpm_n .endif .L_lpm_n = .L_lpm_n + 1 .endr .L_lpm_n = 0 .irp reg, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \ R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \ R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \ R30,R31 .ifc \reg,\dst .L_lpm_dst = .L_lpm_n .endif .L_lpm_n = .L_lpm_n + 1 .endr .if .L_lpm_dst < 0 .L_lpm_n = 0 .rept 32 .if \dst == .L_lpm_n .L_lpm_dst = .L_lpm_n .endif .L_lpm_n = .L_lpm_n + 1 .endr .endif .if (.L_lpm_dst < 0) .err ; Invalid dst arg of 'X_lpm' macro. .endif /* src evaluation */ .L_lpm_src = -1 .L_lpm_n = 0 .irp reg, z,Z,z+,Z+ .ifc \reg,\src .L_lpm_src = .L_lpm_n .endif .L_lpm_n = .L_lpm_n + 1 .endr .if (.L_lpm_src < 0) .err ; Invalid src arg of 'X_lpm' macro. .endif /* instruction(s) */ .if .L_lpm_src < 2 .if .L_lpm_dst == 0 lpm .else #if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ lpm .L_lpm_dst, Z #else lpm mov .L_lpm_dst, r0 #endif .endif .else .if (.L_lpm_dst >= 30) .err ; Registers 30 and 31 are inhibited as 'X_lpm *,Z+' dst. .endif #if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ lpm .L_lpm_dst, Z+ #else lpm .if .L_lpm_dst mov .L_lpm_dst, r0 .endif adiw r30, 1 #endif .endif .endm /* LPM_R0_ZPLUS_INIT is used before the loop to initialize RAMPZ for future devices with RAMPZ:Z auto-increment - [e]lpm r0, Z+. LPM_R0_ZPLUS_NEXT is used inside the loop to load a byte from the program memory at [RAMPZ:]Z to R0, and increment [RAMPZ:]Z. The argument in both macros is a register that contains the high byte (bits 23-16) of the address, bits 15-0 should be in the Z (r31:r30) register. It can be any register except for: r0, r1 (__zero_reg__ - assumed to always contain 0), r30, r31. */ .macro LPM_R0_ZPLUS_INIT hhi #if __AVR_ENHANCED__ #if BIG_CODE out AVR_RAMPZ_ADDR, \hhi #endif #endif .endm .macro LPM_R0_ZPLUS_NEXT hhi #if __AVR_ENHANCED__ #if BIG_CODE /* ELPM with RAMPZ:Z post-increment, load RAMPZ only once */ elpm r0, Z+ #else /* LPM with Z post-increment, max 64K, no RAMPZ (ATmega83/161/163/32) */ lpm r0, Z+ #endif #else #if BIG_CODE /* ELPM without post-increment, load RAMPZ each time (ATmega103) */ out AVR_RAMPZ_ADDR, \hhi elpm adiw r30,1 adc \hhi, __zero_reg__ #else /* LPM without post-increment, max 64K, no RAMPZ (AT90S*) */ lpm adiw r30,1 #endif #endif .endm avr-libc-1.8.0.orig/common/asmdef.h0000644000000000000000000001531111732702554013753 0ustar /* Copyright (c) 2007, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: asmdef.h 2191 2010-11-05 13:45:57Z arcanum $ */ #ifndef _ASMDEF_H #define _ASMDEF_H #include "sectionname.h" /* Macros in this header use local symbols with `.L__' prefix. */ #ifndef __AVR_HAVE_MOVW__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_MOVW__ 1 # else # define __AVR_HAVE_MOVW__ 0 # endif #endif #ifndef __AVR_HAVE_LPMX__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_LPMX__ 1 # else # define __AVR_HAVE_LPMX__ 0 # endif #endif /* Historicaly, the _U() was intended to concatinate '_' prefix. Let us save it, as one is usefull to find externals quickly. */ #define _U(name) name #if !defined(__tmp_reg__) #if defined(__AVR_TINY__) #define __tmp_reg__ r16 #else #define __tmp_reg__ r0 #endif #endif #if !defined(__zero_reg__) #if defined(__AVR_TINY__) #define __zero_reg__ r17 #else #define __zero_reg__ r1 #endif #endif #define XL r26 #define XH r27 #define YL r28 #define YH r29 #define ZL r30 #define ZH r31 #define SPL_IO_ADDR 0x3D #define SPH_IO_ADDR 0x3E #if defined(__AVR_MEGA__) && __AVR_MEGA__ # define XJMP jmp # define XCALL call #else # define XJMP rjmp # define XCALL rcall #endif /* Macro FUNCTION is intended to start a function body without an entry. It is needed where an entry is at the middle of function. After this, you can to use an ENTRY macro below, one time or more. TODO: make a possibility to define a few of blocks FUNCTION..ENDFUNC in a one source file. */ .macro FUNCTION name .ifdef .L__function .err ; FUNCTION is defined already. .endif .L__function = 1 #ifdef FUNC_SEGNAME .section FUNC_SEGNAME, "ax", @progbits #else ASSEMBLY_CLIB_SECTION #endif .type _U(\name), "function" .ifdef .L__END .err ; .L__END is defined already. .endif .size _U(\name), .L__END - . .endm #define FUNCTION FUNCTION /* for CPP conditional expressions */ /* Macro ENTRY is intended to start a function with entry point at the head of body. It is not needed to use a FUNCTION macro in this case. It is possible to place additional ENTRY-s below. */ .macro ENTRY name .ifndef .L__function FUNCTION \name .endif .global _U(\name) _U(\name): .endm /* This macro must used at the end of function body to calculate size. */ .macro ENDFUNC .L__END: .endm /* Macro REGNO set the symbol name 'name' to integer which is a 'reg' number (0..31). If 'reg' is not a valid register, compilation error. Valid regs are: r0..r31, R0..R31 and 0..31 */ .macro REGNO name, reg \name = -1 .L__regno = 0 .irp sym, r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \ r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \ r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \ r30,r31 .ifc \sym,\reg \name = .L__regno .endif .L__regno = .L__regno + 1 .endr .L__regno = 0 .irp sym, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \ R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \ R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \ R30,R31 .ifc \sym,\reg \name = .L__regno .endif .L__regno = .L__regno + 1 .endr .if \name < 0 .L__regno = 0 .rept 32 .if \reg == .L__regno \name = .L__regno .endif .L__regno = .L__regno + 1 .endr .endif .if \name < 0 .err ; Invalid dst arg of 'X_lpm' macro. .endif .endm /* REGNO */ /* Macro 'X_movw' extends enhanced movw instruction for classic chips. */ .macro X_movw dst,src #if __AVR_HAVE_MOVW__ movw \dst,\src #else REGNO .L__movw_dst, \dst .if .L__movw_dst < 0 .exitm .endif .if .L__movw_dst % 1 .err ; Invalid dst arg in X_movw macro. .exitm .endif REGNO .L__movw_src, \src .if .L__movw_src < 0 .exitm .endif .if .L__movw_src % 1 .err ; Invalid src arg in X_movw macro. .exitm .endif mov .L__movw_dst, .L__movw_src mov .L__movw_dst + 1, .L__movw_src + 1 #endif .endm /* Macro 'X_lpm' extends enhanced lpm instruction for classic chips. Usage: X_lpm reg, dst where reg is 0..31, r0..r31 or R0..R31 dst is z, Z, z+ or Z+ It is possible to omit both arguments. Possible results for classic chips: lpm lpm / mov Rd,r0 lpm / adiw ZL,1 lpm / mov Rd,r0 / adiw ZL,1 For enhanced chips it is one instruction always. ATTENTION: unlike enhanced chips SREG (S,V,N,Z,C) flags are changed in case of 'Z+' dst. R0 is scratch. */ .macro X_lpm dst=r0, src=Z /* dst evaluation */ REGNO .L__lpm_dst, \dst .if .L__lpm_dst < 0 .exitm ; do not multiply errors .endif /* src evaluation */ .L__lpm_src = -1 .L__lpm_n = 0 .irp reg, z,Z,z+,Z+ .ifc \reg,\src .L__lpm_src = .L__lpm_n .endif .L__lpm_n = .L__lpm_n + 1 .endr .if (.L__lpm_src < 0) .err ; Invalid src arg of 'X_lpm' macro. .endif /* instruction(s) */ .if .L__lpm_src < 2 .if .L__lpm_dst == 0 lpm .else #if __AVR_HAVE_LPMX__ lpm .L__lpm_dst, Z #else lpm mov .L__lpm_dst, r0 #endif .endif .else .if (.L__lpm_dst >= 30) .err ; Registers 30 and 31 are inhibited as 'X_lpm *,Z+' dst. .endif #if __AVR_HAVE_LPMX__ lpm .L__lpm_dst, Z+ #else lpm .if .L__lpm_dst mov .L__lpm_dst, r0 .endif adiw r30, 1 #endif .endif .endm #endif /* !_ASMDEF_H */ avr-libc-1.8.0.orig/ChangeLog-20030000644000000000000000000006512111732702554013213 0ustar 2003-11-18 Theodore A. Roth * NEWS: Add note about new crc update functions. 2003-11-18 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/crc16.h (_crc16_update): Add line break to dox. (_crc_xmodem_update): Ditto. (_crc_ccitt_update): New function. [Submitted by Tomas Vanek ] 2003-11-12 Joerg Wunsch * include/stdio.h: Implement missing stdio members: vsprintf(), vsprintf_P(), vsnprintf(), vsnprintf_P() * libc/stdio/Makefile.am: ditto. * libc/stdio/vsprintf.c: New file. * libc/stdio/vsprintf_p.c: New file. * libc/stdio/vsnprintf.c: New file. * libc/stdio/vsnprintf_p.c: New file. 2003-11-11 Theodore A. Roth * avr-libc.spec.in (BuildRequires): Don't require doxygen or tetex if "--without docs" was given. 2003-11-11 Theodore A. Roth * avr-libc.spec.in: Allow disabling build of docs sub-package with "--without docs". 2003-11-11 Theodore A. Roth * include/avr/crc16.h: Use inttypes.h defined types to allow use with -mint8. * include/avr/delay.h: Ditto. [Submitted by Tomas Vanek ] 2003-11-11 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/crc16.h (_crc16_update): Add dox. (_crc_xmodem_update): New function. 2003-11-04 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * libc/pmstring/strlcat_P.S: Use correct dox group (fix for bug #6359). * libc/pmstring/strlcpy_P.S: Use correct dox group (fix for bug #6359). 2003-10-20 Theodore A. Roth * include/avr/iom128.h: * include/avr/portpins.h: Move generic PORTn, DDn and PINn defs to portpins.h. 2003-10-20 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/io.h: Include portpins.h. * include/avr/portpins.h: New file. * include/avr/ioat94k.h: Convert PORTxn to Pxn. * include/avr/iom128.h: Convert PORTxn to Pxn. * include/avr/iom162.h: Convert PORTxn to Pxn. * include/avr/iom64.h: Convert PORTxn to Pxn. * include/avr/iotn15.h: Convert PORTxn to Pxn. 2003-10-18 Theodore A. Roth [Fix for Bug #5976] * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/faq.dox: Use pgm_read_byte() instead of __lpm_inline() in the debug_P() example. * include/stdlib.h (itoa): Add note and warning about minimal buffer size to dox. (ltoa): Ditto. (utoa): Ditto. (ultoa): Ditto. 2003-10-17 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iom162.h: Change PE[01] to UPE[01]. [Bug #5799] 2003-10-16 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * NEWS: Add note about new vfprintf_P and vfscanf_P functions. * include/stdio.h: Add prototypes and dox for vfprintf_P and vfscanf_P. * libc/stdio/Makefile.am (lib_a_c_sources): Add vfprintf_p.c and vfscanf_p.c. * libc/stdio/vfprintf_p.c: New file. * libc/stdio/vfscanf_p.c: New file. 2003-10-09 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * README: Change current branch version to 1.1. * libc/string/strcat.S: Don't use backtick to quote a C char. * libc/string/strcpy.S: Don't use backtick to quote a C char. * libc/string/strlen.S: Don't use backtick to quote a C char. * libc/string/strtok_r.S: Don't use backtick to quote a C char. [Submitted by Steven Borley ] * libc/string/strsep.S: Don't use backtick to quote a C char. Add \fn for function definition dox. Exscape '\' char. * libc/string/strstr.S: Don't use backtick to quote a C char. Add \fn for function definition dox. Exscape '\' char. 2003-10-08 Theodore A. Roth * include/avr/sfr_defs.h: Use inttypes.h defined types to allow use with -mint8. [Submitted by Tomas Vanek ] 2003-09-30 Theodore A. Roth * NEWS: Add note about doxygen upgrade. * doc/TODO: Updates. 2003-09-30 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/dox.css: Add spec for TD.mdRow. * doc/api/Makefile.am: * doc/api/doxygen.config.in: Convert for using doxygen-1.3.4. * doc/api/main_page.dox: Add a space after avr-gcc-list URL. * doc/api/rel-method.dox: * doc/api/sections.dox: * doc/api/tools-install.dox: * doc/examples/demo/demo.dox: * include/setjmp.h: * include/stdio.h: * include/stdlib.h: * include/avr/interrupt.h: * include/avr/signal.h: * libc/misc/itoa.S: * libc/misc/ltoa.S: * libc/misc/mul10.S: * libc/misc/mulsi10.S: * libc/misc/ultoa.S: * libc/misc/utoa.S: * libc/pmstring/memcpy_P.S: * libc/pmstring/strcasecmp_P.S: * libc/pmstring/strcat_P.S: * libc/pmstring/strcmp_P.S: * libc/pmstring/strcpy_P.S: * libc/pmstring/strlcat_P.S: * libc/pmstring/strlcpy_P.S: * libc/pmstring/strlen_P.S: * libc/pmstring/strncasecmp_P.S: * libc/pmstring/strncat_P.S: * libc/pmstring/strncmp_P.S: * libc/pmstring/strncpy_P.S: * libc/stdio/stdio_private.h: * libc/stdlib/atoi.S: * libc/stdlib/atol.S: * libc/stdlib/ctype.S: * libc/stdlib/malloc.c: * libc/string/memccpy.S: * libc/string/memchr.S: * libc/string/memcmp.S: * libc/string/memcpy.S: * libc/string/memmove.S: * libc/string/memset.S: * libc/string/strcasecmp.S: * libc/string/strcat.S: * libc/string/strchr.S: * libc/string/strcmp.S: * libc/string/strcpy.S: * libc/string/strlcat.S: * libc/string/strlcpy.S: * libc/string/strlen.S: * libc/string/strlwr.S: * libc/string/strncasecmp.S: * libc/string/strncat.S: * libc/string/strncmp.S: * libc/string/strncpy.S: * libc/string/strnlen.S: * libc/string/strrchr.S: * libc/string/strrev.S: * libc/string/strsep.S: * libc/string/strstr.S: * libc/string/strtok_r.S: * libc/string/strupr.S: * libm/fplib/addsf3x.S: * libm/fplib/asin.S: * libm/fplib/atan2.S: * libm/fplib/dtostre.S: * libm/fplib/dtostrf.S: * libm/fplib/exp.S: * libm/fplib/floatsisf.S: * libm/fplib/fmod.S: * libm/fplib/fp_cosinus.S: * libm/fplib/fp_merge.S: * libm/fplib/fp_powerseries.S: * libm/fplib/fp_split.S: * libm/fplib/frexp.S: * libm/fplib/ldexp.S: * libm/fplib/log.S: * libm/fplib/mulsf3x.S: * libm/fplib/sin.S: * libm/fplib/strtod.S: * libm/fplib/tan.S: * libm/fplib/tanh.S: Quell doxygen warnings. 2003-09-22 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/TODO: Update to denote 1.0 release. 2003-09-22 Theodore A. Roth * doc/api/rel-method.dox (Making a release): Fix some typos. 2003-09-21 Theodore A. Roth * NEWS: Post-branch update. * avr-libc.spec.in: Update gcc requirement to >= 3.3. 2003-09-18 Eric B. Weddington * include/avr/boot.h: Make it more -mint8 compatible. 2003-09-18 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/inttypes.h: Add note about -mint8 patch for gcc to change the size of long long from 64 bits to 32 bits. * include/avr/pgmspace.h: Replace prog_int with prog_int16_t. Replace prog_long with prog_int32_t. Replace prog_long_long with prog_int64_t. Add typedefs for prog_int8_t, prog_uint8_t, prog_uint16_t, prog_uint32_t and prog_uint64_t. Only define pgm_read_byte_far or pgm_read_word_far if RAMPZ is defined and __USING_MINT8 is not defined. 2003-09-17 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/faq.dox: Grammar fixes. 2003-09-17 Theodore A. Roth * include/avr/pgmspace.h (pgm_read_byte_near): Use uint16_t instead of unsigned short to allow use with -mint8. (pgm_read_word_near): Ditto. [Submitted by Tomas Vanek ] 2003-09-11 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/sections.dox: Grammar fix. 2003-09-11 Theodore A. Roth * include/avr/ina90.h (output_block_inc): Remove unused op arg. (output_block_dec): Ditto. [Thanks to Anatoll Sokolov for catching this.] 2003-09-08 Theodore A. Roth * doc/api/inline_asm.dox: Add 'movw' to the mnemonic constraints table. [Pointed out by Bruce D. Lightner] 2003-09-08 Theodore A. Roth * include/avr/boot.h: Set __SPM_REG using simpler logic. 2003-09-08 Theodore A. Roth * include/avr/boot.h: Move header protector before dox. Expose boot loader example code to doxygen. Expose todo note to doxygen. 2003-09-08 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/boot.h: Formatting cleanups - remove extra empty lines, wrap or shorten long lines. 2003-08-29 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. Remove obsolete comment about version numbering. * doc/api/Makefile.am: Combine multiple definitions of SUFFIXES var. 2003-08-26 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iom162.h (TCCR1A): Add missing bit values. 2003-08-15 Theodore A. Roth * Cut 1.0 branch. Branch tag is avr-libc-1_0-branch. 2003-08-15 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Set version to 0.99.90.20030815. * NEWS: Prepare for branch. * doconf: Export PATH. Try to catch CC=gcc in env to avoid configure failure. * doc/api/rel-method.dox: Update branch/release instructions. * doc/api/tools-install.dox: Add warning about having CC=gcc causing configure to fail. 2003-08-15 Theodore A. Roth * doc/api/rel-method.dox: Add note about updating NEWS file. * doc/api/tools-install.dox: Update program versions. Update avarice install notes. * include/avr/pgmspace.h: Add @{ @} around PRG_RDB to quell doxygen warning. Move note about constant tables in lower 64k were doxygen will see it. Move pgm_read_byte_far() and pgm_read_word_far() comments to be directly before macro definitions. 2003-08-15 Theodore A. Roth * include/avr/pgmspace.h: Remove extraneous empty lines. 2003-08-14 Theodore A. Roth * doc/api/rel-method.dox: Fix typo. 2003-08-14 Theodore A. Roth * README: Discuss required versions of gcc and binutils. * doc/api/Makefile.am (EXTRA_DIST): Add rel-method.dox. (IMAGE_SRC): Add releases.fig. * doc/api/main_page.dox: Grammar fix. * doc/api/rel-method.dox: New file. * doc/api/releases.fig: New file. 2003-08-11 Eric B. Weddington * include/avr/boot.h: Fix bug with not using generic SPM Control Register. 2003-08-11 Theodore A. Roth * devtools/cr_check.py: New file. 2003-08-11 Theodore A. Roth * include/string.h: Remove extra carriage returns. * include/avr/interrupt.h: Remove extra carriage returns. * include/avr/pgmspace.h: Remove extra carriage returns. * include/avr/sfr_defs.h: Remove extra carriage returns. * libc/misc/ee_wblk.S: Remove extra carriage returns. * libc/misc/ee_ww.S: Remove extra carriage returns. 2003-08-06 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/inline_asm.dox: Fix broken link to ethernut site. 2003-07-21 Eric B. Weddington * include/avr/boot.h: Make common bit definitions to handle the mega323. 2003-07-17 Eric B. Weddington New functions eeprom_write_word and eeprom_write_block from Artur Lipowski * libc/misc/eeprom.S: New functions, add const to parameters of read functions. * libc/misc/eeprom_ww.S: New file. * libc/misc/eeprom_wblk.S: New file. * include/avr/eeprom.h: New functions. * libc/misc/Makefile.am: Add new modules. * NEWS: Note about new functions. 2003-07-10 Eric B. Weddington * include/avr/boot.h: Fix doxygen. 2003-06-20 Eric B. Weddington * include/string.h: Add declarations of new functions from Reiner. * include/avr/pgmspace.h: ditto. 2003-06-20 Eric B. Weddington * libc/misc/itoa.S: Fix for bug #4010 from Reiner Patommel. * libc/misc/ltoa.S: ditto * libc/misc/ultoa.S: ditto * libc/misc/utoa.S: ditto * include/stdlib.h: Update doxygen for these functions. 2003-06-20 Eric B. Weddington * libc/stdlib/atoi.S: Fix bug with extra text. 2003-06-19 Eric B. Weddington New string functions from Reiner Patommel. * libc/string/strlcat.S: Add file. * libc/string/strlcpy.S: Add file. * libc/string/strsep.S: Add file. * libc/string/strtok_r.S: Add file. * libc/string/Makefile.am: Modify for new functions. * libc/pmstring/strlcat_P.S: Add file. * libc/pmstring/strlcpy_P.S: Add file. * libc/pmstring/strncat_P.S: Add file. * libc/pmstring/Makefile.am: Modify for new functions. * doc/TODO: Remove item about optimize strlcpy, strlcat. * NEWS: Note about new functions. 2003-06-18 Eric B. Weddington * libc/stdlib/atol.S: Fix for Bug #3576, by Reiner Patommel. 2003-06-18 Eric B. Weddington * libc/stdlib/atoi.S: Fix for Bug #3575, by Reiner Patommel. 2003-06-17 Eric B. Weddington * include/avr/interrupt.h: Fix for bug #3508. 2003-06-17 Eric B. Weddington * include/avr/pgmspace.h: Revert volatile on macros, fix macros to specify which registers are used. 2003-06-13 Joerg Wunsch * libc/stdlib/strtoul.c: fix broken unsigned handling. 2003-06-13 Eric B. Weddington * include/avr/iom169.h: Add missing EECR bit defines. 2003-06-10 Eric B. Weddington * include/avr/sfr_defs.h: Add more comments on the return value of the bit_is_set and bit_is_clear macros. [Bug #3839] 2003-06-10 Eric B. Weddington * include/avr/sfr_defs.h: Deprecate inb,outb,inw,outw,cbi,sbi macros. Remove usage of above macros. * include/avr/ina90.h: Remove usage of inb / outb macros. * include/avr/interrupt.h: ditto. * include/avr/timer.h: ditto. * NEWS: Note about deprecation of macros. 2003-06-06 Eric B. Weddington * include/avr/boot.h: Add file. Provides new bootloader support API. * NEWS: Add note about new bootloader support API. 2003-06-05 Eric B. Weddington * include/avr/pgmspace.h: Add __volatile__ to asm macros to fix optimizer blunders; use inttypes.h; formatting. 2003-06-03 Theodore A. Roth * include/avr/signal.h: Remove carriage returns. 2003-05-19 Eric B. Weddington * NEWS: Add note about new pgmspace.h API. 2003-05-19 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * NEWS: Update gcc and binutils version requirements. Add note about direct sfr access being preferred over in/out macros. 2003-05-14 Eric B. Weddington * include/avr/pgmspace.h: New API. 2003-05-14 Eric B. Weddington * include/avr/iotn26.h: Update interrupt vector names to match the datasheet. [Contributed by Artur Lipowski ] 2003-05-12 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. 2003-05-09 Eric B. Weddington * crt1/gcrt1.S: Change .data initialization under BIG_CODE to properly use elpm for the ATmega103. [Contributed by Geoffrey Wossum ] 2003-05-08 Eric B. Weddington * doc/TODO: Update, add items. 2003-05-08 Eric B. Weddington * include/avr/signal.h: Add EMPTY_INTERRUPT macro. [Contributed by Artur Lipowski ] 2003-05-05 Eric B. Weddington * include/avr/io86r401.h: Update to match datasheet. 2003-04-22 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. 2003-04-22 Joerg Wunsch * include/stdlib.h: strtod() is now tested. 2003-04-17 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * avr-libc.spec.in: Rpm in RedHat-9 is stripping avr binaries when it has no business doing so. Disable the install post scriptlet to stop this behaviour. 2003-04-14 Theodore A. Roth * include/avr/ioat94k.h: Add comment to signal defs noting official ATMEL names. [Contributed by Thibaud Gaillard ] 2003-04-14 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/ioat94k.h: Add missing register bit definitions. [Contributed by Thibaud Gaillard ] 2003-04-12 Marek Michalkiewicz * common/macros.inc: Check __AVR_MEGA__, not FLASHEND [Bug #3184]. * configure.in (AM_INIT_AUTOMAKE): Bump version. 2003-04-08 Theodore A. Roth * include/avr/iotn26.h: Add bit defines for USISR and USICR registers. [Contributed by Artur Lipowski ] 2003-04-07 Theodore A. Roth * include/avr/sleep.h: Add adc mode to sleep type 2 [Bug #3088]. 2003-04-07 Joerg Wunsch * doc/api/faq.dox: add entry about RAM/variable overlap detection. 2003-04-03 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iotn26.h: Add missing port and bit definitions [Bug #3081] [Contributed by Artur Lipowski ] 2003-03-30 Joerg Wunsch * doc/api/assembler.dox: more explanation about intr. vectors. 2003-03-24 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. 2003-03-17 Theodore A. Roth * include/avr/interrupt.h (enable_external_int): There are now 3 different registers used by various AVR devices to enable external interrupts: EIMSK, GIMSK, and GICR. If one of those is not defined, generate a compile time error. 2003-03-17 Theodore A. Roth * include/avr/pgmspace.h: Document PRG_RDB [Bug #2839]. Change strncat to strncat_P [Bug #2838]. 2003-03-17 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/stdio.h, libc/stdio/fdevopen.c: Move dox comment for fdevopen() from stdio.h to fdevopen.c to work around a broken html link due to a bug in doxygen. [Bug #2845] 2003-03-03 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. 2003-02-28 Marek Michalkiewicz * NEWS, doc/api/main_page.dox: Note AT43USB320 support. * configure.in (AM_INIT_AUTOMAKE): Bump version. * configure.in, include/avr/io.h: Add support for AT43USB320. * include/avr/io43u32x.h: New file, thanks to Keith Gudger. * include/avr/io43u35x.h: Remove defines for the non-existent UART and analog comparator. Remove IAR compatibility defines. (RAMEND, XRAMEND, FLASHEND): Update to match the datasheet. 2003-02-28 Joerg Wunsch * doc/api/faq.dox: add entry about integer promotion with bitwise operators. 2003-02-27 Theodore A. Roth * NEWS: * doc/api/main_page.dox: Note support for new devices (AT43USB355, AT76C711, AT86RF401). 2003-02-27 Marek Michalkiewicz * configure.in (AM_INIT_AUTOMAKE): Bump version. * configure.in, crt1/Makefile.am, include/avr/io.h: Add support for AT43USB355, AT76C711, AT86RF401. * include/avr/io43u35x.h: New file, thanks to Keith Gudger. * include/avr/io86r401.h: New file, thanks to Colin O'Flynn. 2003-02-27 Theodore A. Roth * doc/api/acknowledge.dox: * doc/api/tools-install.dox: * doc/api/using-avrprog.dox: Update avrdude information. 2003-02-26 Theodore A. Roth * doc/api/acknowledge.dox: Add Rich Neswold. 2003-02-25 Theodore A. Roth * include/avr/iom169.h: Update some comments only. 2003-02-25 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/faq.dox: Minor clarification. 2003-02-23 Joerg Wunsch * libc/stdlib/atoi.S: fix bug #2481. * libc/stdlib/atol.S: Ditto. 2003-02-22 Joerg Wunsch * doc/api/faq.dox: eplain PSTR() to move strings out to flash. 2003-02-21 Joerg Wunsch * include/avr/io2333.h: the datasheet says OCR1_A_. 2003-02-17 Marek Michalkiewicz * include/avr/iom8.h, include/avr/iom8535.h, include/avr/iom32.h, include/avr/iom64.h, include/avr/iom128.h, include/avr/iom169.h: Protect the ADC definition with #ifndef __ASSEMBLER__ . 2003-02-10 Joerg Wunsch * doc/TODO: update. 2003-02-08 Marek Michalkiewicz * include/avr/ioat94k.h: Fix external/FPGA interrupts. (Thanks to Nishiyama Naoki for catching this.) 2003-02-06 Joerg Wunsch * include/avr/io.h: Document SPM_PAGESIZE. * doc/api/using-tools.dox: Add a few more gcc options. 2003-02-06 Joerg Wunsch * include/avr/io.h: Document SPM_PAGESIZE. 2003-02-06 Joerg Wunsch * include/avr/iom128.h: Add SPM_PAGESIZE. * include/avr/iom16.h: Add SPM_PAGESIZE. * include/avr/iom161.h: Add SPM_PAGESIZE. * include/avr/iom162.h: Add SPM_PAGESIZE. * include/avr/iom163.h: Add SPM_PAGESIZE. * include/avr/iom169.h: Add SPM_PAGESIZE. * include/avr/iom32.h: Add SPM_PAGESIZE. * include/avr/iom323.h: Add SPM_PAGESIZE. * include/avr/iom64.h: Add SPM_PAGESIZE. * include/avr/iom8.h: Add SPM_PAGESIZE. * include/avr/iom8515.h: Add SPM_PAGESIZE. * include/avr/iom8535.h: Add SPM_PAGESIZE. 2003-02-06 Joerg Wunsch * doc/api/acknowledge.dox: mention Eric Weddington. 2003-02-05 Joerg Wunsch * doc/api/main_page.dox: fix an HREF. 2003-02-04 Joerg Wunsch * doc/TODO: remove the ina.90 xref check, Eric did it. 2003-02-03 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/TODO: Wrap a line (format only). * include/stdio.h: Grammatical and readiblity cleanups. 2003-01-20 Theodore A. Roth * doc/api/Makefile.am (EXTRA_DIST): Add unjs.pl. 2003-01-20 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/TODO: Remove note about sleep.h. * include/avr/sleep.h: Make it work with any device (mostly). 2003-01-21 Joerg Wunsch * include/stdio.h: add SEEK_*. 2003-01-20 Joerg Wunsch * doc/api/unjs.pl: new file. * doc/api/Makefile.am: include fix_javascript. 2003-01-20 Joerg Wunsch * doc/api/faq.dox: updated indirect IO port access section. 2003-01-20 Joerg Wunsch * libm/fplib/Makefile.am: remove irexp.S. * libm/fplib/irexp.S: remove. 2003-01-14 Theodore A. Roth * doc/TODO: Sync http refs up with new archive. 2003-01-14 Theodore A. Roth * include/avr/iom169.h: Fix typo (TCNT9 -> TCNT0). * include/avr/iom64.h: Fix typo (For TCCR0, CS1n -> CS0n). 2003-01-14 Theodore A. Roth * ChangeLog: Moved 2002 entries to ChangeLog-2002. * configure.in (AM_INIT_AUTOMAKE): Bump version. * libm/fplib/Makefile.am (EXTRA_DIST): Remove readme.atan2. 2003-01-13 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/sleep.h: Clear MCUCR before setting the new mode. (Thanks to Volkmar Dierkes for catching this bug.) 2003-01-08 Joerg Wunsch * configure.in: add __COMPILING_AVR_LIBC__, drop use of fake -mmcu devices when assembling, use avr[2..5] instead. * include/avr/eeprom.h: mention this to be n/a for ATmega169. * include/avr/io.h: move the common register declarations here; explain the details about the inclusion of . * include/avr/io1200.h: remove common register declarations. * include/avr/io2313.h: ditto. * include/avr/io2323.h: ditto. * include/avr/io2333.h: ditto. * include/avr/io2343.h: ditto. * include/avr/io4414.h: ditto. * include/avr/io4433.h: ditto. * include/avr/io4434.h: ditto. * include/avr/io76c711.h: ditto. * include/avr/io8515.h: ditto. * include/avr/io8534.h: ditto. * include/avr/io8535.h: ditto. * include/avr/ioat94k.h: ditto. * include/avr/iom103.h: ditto. * include/avr/iom128.h: ditto. * include/avr/iom16.h: ditto. * include/avr/iom161.h: ditto. * include/avr/iom162.h: ditto. * include/avr/iom163.h: ditto. * include/avr/iom169.h: ditto. * include/avr/iom32.h: ditto. * include/avr/iom323.h: ditto. * include/avr/iom64.h: ditto. * include/avr/iom8.h: ditto. * include/avr/iom8515.h: ditto. * include/avr/iom8535.h: ditto. * include/avr/iotn11.h: ditto. * include/avr/iotn12.h: ditto. * include/avr/iotn15.h: ditto. * include/avr/iotn22.h: ditto. * include/avr/iotn26.h: ditto. * include/avr/iotn28.h: ditto. * libc/stdlib/malloc.c: drop private declaration of the SP register. 2003-01-07 Joerg Wunsch * Makefile.am: include the scanf family. * include/stdio.h: Ditto. * libc/stdio/Makefile.am: Ditto. * libc/stdio/fgetc.c: Account len, used by scanf. * libc/stdio/stdio_private.h: New defs for scanf.. * libc/stdio/ungetc.c: Account len, used by scanf. * libc/stdio/fscanf.c: New file. * libc/stdio/fscanf_p.c: New file. * libc/stdio/scanf.c: New file. * libc/stdio/scanf_p.c: New file. * libc/stdio/sscanf.c: New file. * libc/stdio/sscanf_p.c: New file. * libc/stdio/vfscanf.c: New file. 2003-01-07 Joerg Wunsch * doc/examples/demo/demo.dox: fix the command line for extracting the contents of .eeprom. 2003-01-06 Joerg Wunsch * include/avr/sfr_defs.h: make bit_is_clear() more efficient. 2003-01-05 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/sleep.h: Fix incorrect use of bit numbers. 2003-01-05 Joerg Wunsch * doc/api/faq.dox: add an entry about default fuse bits. 2003-01-04 Joerg Wunsch * libm/fplib/strtod.S: style police: tabs, comments, local labels. 2003-01-03 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * NEWS: Add note about Binutils 2.13 being usable. Remove note about mega32 being untested. 2003-01-02 Joerg Wunsch * libc/stdio/vfprintf.c: printf_flt() needs . * libc/stdio/Makefile.am: well, asm objects come from asm sources :). For older changes see ChangeLog-2002 avr-libc-1.8.0.orig/ChangeLog-20070000644000000000000000000015431511732702554013223 0ustar 2007-12-29 Dmitry Xmelkov * include/avr/pgmspace.h: Add '__' prefix with function args. 2007-12-23 Dmitry Xmelkov Fix bug #21872: __floatunsisf/undisf incorrectly named * libm/fplib/floatsisf.S: Rename __floatunssisf --> __floatunsisf * libc/stdlib/strtod.c: Ditto. Add the preprocessing to exclude manual conversion with GCC >= 4.2 * libm/fplib/floatunsdisf.S: Move to floatundisf.S . * libm/fplib/floatundisf.S: New file: __floatunsdisf --> __floatundisf * libm/fplib/Files.am: Change source file name. * tests/simulate/fplib/ulng2flt-01.c: __floatunssisf --> __floatunsisf * tests/simulate/fplib/unll2flt-01.c: __floatunsdisf --> __floatundisf * tests/simulate/regression/bug-21872-1.c: New file. * tests/simulate/regression/bug-21872-2.c: New file. * NEWS: Note about this bug. * tests/simulate/progmem.h: Simplify pgm_read_qword() evaluation. 2007-12-20 Joerg Wunsch bug #21862: File 'bench-libm.dox' does not exist in distribution * doc/api/Makefile.am (EXTRA_DIST): add doc/api/bench-libm.dox. 2007-12-20 Anatoly Sokolov * configure.ac: Add 'avr35' architecture. Move AT90USB82 and AT90USB162 devices to 'avr35' architecture. * devtools/gen-avr-lib-tree.sh (AVR_ARH_INFO): Add 'avr35' architecture. (AVR3_DEV_INFO): Add AT90USB82 and AT90USB162 devices. (AVR35_DEV_INFO): New. (AVR5_DEV_INFO): Remove AT90USB82 and AT90USB162 devices. * doc/api/using-tools.dox: Document 'avr35'. 2007-12-20 Joerg Wunsch * NEWS: avr-libc 1.6 branched * configure.ac: bump to 1.7.0-20071220 2007-12-20 Joerg Wunsch * xml/patch-headers.py: Update for new devices and header files. * xml/Atmel2libc.py: More tweaks for strange Atmel XML files. * doc/api/vectortable.dox: Regenerate from XML. 2007-12-20 Joerg Wunsch * doc/api/bench.dox: Some minor spelling and grammar fixes to Dmitry's fine benchmark page. 2007-12-20 Joerg Wunsch * doc/api/faq.dox: Resolve all doxygen warnings except the "is not documented" ones. * doc/api/library.dox: (Ditto.) * doc/api/overview.dox: (Ditto.) * doc/api/porting.dox: (Ditto.) * doc/api/tools-install.dox: (Ditto.) * doc/examples/stdiodemo/stdiodemo.dox: (Ditto.) * include/avr/fuse.h: (Ditto.) * include/avr/lock.h: (Ditto.) * include/util/atomic.h: (Ditto.) 2007-12-20 Joerg Wunsch bug #21484: Documentation build for avr/version.h does not susbstitute autoconf macros * doc/api/doxygen.config.in (INPUT): replace version.h.in by version.h so the doxygen build uses the processed file. 2007-12-19 Dmitry Xmelkov * include/stdlib.h: Add '__' prefix with function args. * include/string.h: Add '__' prefix with function args. The ffs(), ffsl(), ffsll(): cosmetic changes to improve Doxygen output. * tests/simulate/math/isinf-01.c: New file. * include/math.h: Fix a few documentation errors (inherited from 1.4). Make args names in doc adequate ones in function declaration. Use the '\a' Doxygen's command instead to '\c' anywhere. Add CLI to abort() and exit() functions, since GCC's _exit() does not disable interrupts today. * libc/stdlib/abort.S: Add CLI before jump to _exit. * libc/stdlib/exit.S: Ditto. * include/stdlib.h: Document the CLI. * tests/simulate/stdlib/abort-1.c: New file. 2007-12-18 Joerg Wunsch Undo the CLI change. This rather belongs into _exit which is supplied by libgcc.a. Reopens bug #21841: Add CLI to exit() and abort() loops * libc/stdlib/exit.S: undo rev 1.2. * include/stdlib.h (exit): undo rev 1.30. 2007-12-18 Eric B. Weddington * include/avr/iotn43u.h: Fix RAMEND. 2007-12-18 Eric B. Weddington * include/avr/iom1284p.h: Fix RAMEND. * include/avr/iom32hvb.h: Ditto. * include/avr/iotn48.h: Ditto. * include/avr/iotn88.h: Ditto. * include/avr/io90pwm2b.h: Ditto. * include/avr/io90pwm3b.h: Ditto. * include/avr/io90pwm216.h: Ditto. * include/avr/io90pwm316.h: Ditto. 2007-12-18 Joerg Wunsch bug #21841: Add CLI to exit() and abort() loops * libc/stdlib/exit.S: add a CLI before entering the loop * include/stdlib.h (exit): document the CLI. 2007-12-18 Joerg Wunsch Submitted by Bill Johnson bug #19669: Need function to read signature row * include/avr/boot.h (boot_signature_byte_get): Add new macro. 2007-12-18 Joerg Wunsch * tests/simulate/runtest.sh: replace /bin/bash by /bin/sh as the really generic name of the shell to invoke. Not every system has bash in /bin. 2007-12-18 Eric B. Weddington Fix for bug #21840. * include/avr/iom48p.h: Fix RAMEND. * include/avr/iom88p.h: Ditto. * include/avr/iom168p.h: Ditto. * include/avr/iom328p.h: Ditto. 2007-12-18 Dmitry Xmelkov * include/alloca.h: Add '__' prefix with function args. To avoid a possible conflict with user's CPP definitions. * include/math.h: Ditto. 2007-12-17 Dmitry Xmelkov Make abort() as a normal extern function (instead to inline loop). * libc/stdlib/abort.S: Rewrite. * include/stdlib.h: Declare abort() as a normal, add doc. * tests/simulate/stdlib/abort-1.c: New file. 2007-12-16 Dmitry Xmelkov * libc/stdlib/ctype.S: . isalnum(): Optimize. . isxdigit(): Correct a behaviour with nonzero high byte. . iscntrl(): Fix bug [no-id]: iscntrl() return true for some values from 0x80 to 0xff. Optimize a little. . ispunct(): Optimize. . tolower(): Return as is, if the input is not an unsigned char value. Optimize. . toupper(): Ditto. * include/ctype.h: Specify (and change) doc about the behaviour in case then the input is not an unsigned char value. * NEWS: Note about fixed bug of iscntrl(). * tests/simulate/stdlib/isalnum-1.c: New file. * tests/simulate/stdlib/isalpha-1.c: New file. * tests/simulate/stdlib/isascii-1.c: New file. * tests/simulate/stdlib/isblank-1.c: New file. * tests/simulate/stdlib/iscntrl-1.c: New file. * tests/simulate/stdlib/isdigit-1.c: New file. * tests/simulate/stdlib/isgraph-1.c: New file. * tests/simulate/stdlib/ispunct-1.c: New file. * tests/simulate/stdlib/isupper-1.c: New file. * tests/simulate/stdlib/isxdigit-1.c: New file. * tests/simulate/stdlib/tolower-1.c: New file. * tests/simulate/stdlib/toupper-1.c: New file. 2007-12-16 Dmitry Xmelkov Fix bug #18994: minor optimization possible to stdlib functions isspace(), isprint(), and islower() * libc/stdlib/ctype.S: Optimize isspace(), isprint() and islower(). * tests/simulate/stdlib/islower-1.c: New file. * tests/simulate/stdlib/isprint-1.c: New file. * tests/simulate/stdlib/isspace-1.c: New file. * NEWS: Note about this. * NEWS: Add the chapter 'Main changes from 1.4 to 1.5'. 2007-12-12 Eric B. Weddington * include/avr/io90pwm216.h: Fix fuse data. * include/avr/io90pwm316.h: Ditto. 2007-12-12 Eric B. Weddington * include/avr/iom32hvb.h: Remove unused register. * include/avr/io90pwm216.h: Fix IVT size. Fix for bug #21749. * include/avr/io90pwm316.h: Ditto. * include/avr/iomx8.h: Remove bits for mega48. Fix for bug #21691. * include/avr/io90pwm316.h: Add bit defs. Fix for bug #21743. * include/avr/iomxx0_1.h: Fix bit defs. Fix for bug #21626. * include/avr/iotnx61.h: Fix bit defs. Fix for bug #21521. 2007-12-11 Eric B. Weddington * include/avr/lock.h: Add documentation for the Lockbit API. * doc/api/doxygen.config.in: Add avr/lock.h to the doc list. * include/avr/iom8.h: Add Fuse and Lockbit data. * include/avr/iotn43u.h: Add Lockbit data. * include/avr/io90pwm216.h: Add Lockbit data. Fix fuse data. * include/avr/io90pwm316.h: Add Lockbit data. Fix fuse data. * include/avr/io90pwm2b.h: Add Lockbit data. Fix fuse data. * include/avr/io90pwm3b.h: Add Lockbit data. Fix fuse data. * include/avr/iom88.h: Add Fuse data. * include/avr/iom168.h: Add Fuse data. * include/avr/iom128.h: Formatting. * include/avr/iom16.h: Add Fuse and Lockbit data. * include/avr/iom32.h: Ditto. * include/avr/iom64.h: Ditto. * include/avr/iom325.h: Ditto. * include/avr/iom3250.h: Ditto. * include/avr/iom645.h: Ditto. * include/avr/iom6450.h: Ditto. * include/avr/iom329.h: Ditto. * include/avr/iom3290.h: Ditto. * include/avr/iom649.h: Ditto. * include/avr/iom6490.h: Ditto. * include/avr/iom640.h: Ditto. * include/avr/iom1280.h: Ditto. * include/avr/iom1281.h: Ditto. * include/avr/iom2560.h: Ditto. * include/avr/iom2561.h: Ditto. * include/avr/iousb646.h: Ditto. * include/avr/iousb647.h: Ditto. * include/avr/iousb1286.h: Ditto. * include/avr/iousb1287.h: Ditto. * include/avr/iom8515.h: Ditto. * include/avr/iom161.h: Ditto. * include/avr/iom162.h: Ditto. * include/avr/iom163.h: Ditto. * include/avr/iousb82.h: Ditto. * include/avr/iousb162.h: Ditto. * include/avr/iom165.h: Ditto. * include/avr/iom165p.h: Ditto. * include/avr/iocan32.h: Ditto. * include/avr/iocan64.h: Ditto. * include/avr/iocan128.h: Ditto. * include/avr/io90pwmx.h: Ditto. * include/avr/io90pwm1.h: Ditto. * include/avr/iom169.h: Ditto. * include/avr/iom169p.h: Ditto. * include/avr/iom323.h: Ditto. * include/avr/iom406.h: Ditto. * include/avr/iotn261.h: Ditto. * include/avr/iotn461.h: Ditto. * include/avr/iotn861.h: Ditto. * include/avr/iotn25.h: Ditto. * include/avr/iotn45.h: Ditto. * include/avr/iotn85.h: Ditto. * include/avr/iotn24.h: Ditto. * include/avr/iotn44.h: Ditto. * include/avr/iotn84.h: Ditto. * include/avr/iotn2313.h: Ditto. * include/avr/iotn13.h: Ditto. * include/avr/iotn11.h: Ditto. * include/avr/iotn12.h: Ditto. * include/avr/iom8hva.h: Ditto. * include/avr/iom16hva.h: Ditto. * include/avr/iom8535.h: Ditto. * include/avr/iom164.h: Ditto. * include/avr/iom324.h: Ditto. * include/avr/iom644.h: Ditto. * include/avr/iotn28.h: Ditto. * include/avr/iotn26.h: Ditto. * include/avr/iotn22.h: Ditto. * include/avr/iotn15.h: Ditto. 2007-12-09 Dmitry Xmelkov * libm/fplib/frexp.S: Make frexp() similar to GCC/x86 in case of nonfinite arg: write 0 by exponent pointer. Early Avr-libc's frexp() skips exponent storing in this case. Make the NULL a legal address to skip a storing. * include/math.h: Specify this in doc. * tests/simulate/math/frexp-01.c: Add new test cases. * NEWS: Note about this. 2007-12-08 Dmitry Xmelkov * doc/api/doxygen.config.in: Change MACRO_EXPANSION and EXPAND_ONLY_PREDEF variables to YES. Add __ATTR_CONST__ to PREDEFINED list. To clean documentation: remove last label from function lists. * include/math.h: Add a note about the const attribute. * doc/api/doxygen.config.in: Remove 'libm' directory from the INPUT list, as there is no any doxygen comments. To reduce the number of doxygen warnings. 2007-12-02 Dmitry Xmelkov Extend the benchmark chapter. * doc/api/bench-libc.dox: Add a bit functions. * doc/api/bench-libm.dox: New file. * doc/api/doxygen.config.in: Add new file bench-libm.dox Make signbit() similar to GCC's builtin: return 1 as nonzero value. * libm/fplib/signbit.S: Ditto. * include/math.h: signbit(): fix comment about return value. * tests/simulate/math/signbit-01.c: New file. * NEWS: Note about this change. 2007-12-01 Dmitry Xmelkov Move all CPP statements to '#ifndef __DOXYGEN__' scope to reduce the volume of garbage in documentation. IMHO, the \file doxygen directive is redundant here, as it forces an opening a new chapter with inclusion all CPP definitions. * libc/pmstring/memcpy_P.S: (Ditto.) * libc/pmstring/strcat_P.S: (Ditto.) * libc/pmstring/strcpy_P.S: (Ditto.) * libc/pmstring/strlen_P.S: (Ditto.) * libc/pmstring/strncat_P.S: (Ditto.) * libc/pmstring/strncmp_P.S: (Ditto.) * libc/pmstring/strncpy_P.S: (Ditto.) * libc/pmstring/strnlen_P.S: (Ditto.) * libc/stdlib/atoi.S: (Ditto.) * libc/stdlib/atol.S: (Ditto.) * libc/string/memccpy.S: (Ditto.) * libc/string/memchr.S: (Ditto.) * libc/string/memcmp.S: (Ditto.) * libc/string/memcpy.S: (Ditto.) * libc/string/memmove.S: (Ditto.) * libc/string/memset.S: (Ditto.) * libc/string/strcat.S: (Ditto.) * libc/string/strcpy.S: (Ditto.) * libc/string/strlen.S: (Ditto.) * libc/string/strncat.S: (Ditto.) * libc/string/strncmp.S: (Ditto.) * libc/string/strncpy.S: (Ditto.) * libc/string/strnlen.S: (Ditto.) * libc/string/strrchr.S: (Ditto.) Add new function lrint(). * libm/fplib/lrint.S: New file. * libm/fplib/Files.am: Add new source lrint.S * include/math.h: Add lrint() function definition. * tests/simulate/math/lrint-01.c: New file. * NEWS: Update new functions list. Make conversion from float to (u)long in error cases to be more similar with GCC/x86. * libm/fplib/fixunssfsi.S: New file. * libm/fplib/Files.am: Add new source fixunssfsi.S * libm/fplib/fixsfsi.S: Rewrite to use __fixunssfsi() function. * libm/fplib/lround.S: Unify result in error cases. * include/math.h: lround(): fix comment about return value. * tests/simulate/fplib/flt2long-01.c: Update overflow test cases. * tests/simulate/fplib/flt2ulng-01.c: Ditto. * tests/simulate/math/lround-01.c: Ditto. * NEWS: Note about this change. 2007-11-30 Eric B. Weddington * doc/api/doxygen.config.in: Add avr/fuse.h to the doc list. 2007-11-30 Eric B. Weddington * include/avr/fuse.h: Add documentation for Fuse API. 2007-11-28 Eric B. Weddington Add new devices: ATmega1284P, ATmega32HVB. * configure.ac: Add new devices. * devtools/gen-avr-lib-tree.sh: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/power.h: Ditto. * include/avr/wdt.h: Ditto. * NEWS: Update new devices list. * include/avr/iom1284p.h: New file. * include/avr/iom32hvb.h: New file. 2007-11-18 Dmitry Xmelkov Add the benchmark page. Now this is only a start of work. * doc/api/bench.dox: New file. * doc/api/bench-libc.dox: New file. * doc/api/Makefile.am: Add new doxygen sources. * dod/api/doxygen.config.in: Ditto. * NEWS: Note about new doc page. 2007-11-11 Dmitry Xmelkov Add new function lround(). * libm/fplib/lround.S: New file. * libm/fplib/Files.am: Add new source lround.S * include/math.h: Add lround() function definition. * tests/simulate/math/lround-01.c: New file. * NEWS: Update new functions list. 2007-11-08 Eric B. Weddingotn Add new device: ATtiny88. * configure.ac: Add new device. * devtools/gen-avr-lib-tree.sh: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/power.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/iotn88.h: New file. * NEWS: Update new devices list. * include/avr/iotn48.h: Add lockbit information. 2007-11-05 Dmitry Xmelkov Add new function round(). * libm/fplib/round.S: New file. * libm/fplib/Files.am: Add new source round.S * include/math.h: Add round() function definition. * tests/simulate/math/round-01.c: New file. * tests/simulate/math/xxx-nan.c: Add round() function to list. * include/math.h: Add the 'const' attribute to hypot() function. 2007-11-04 Dmitry Xmelkov * libc/stdlib/dtostre.c: Optimize in space: 16..22 bytes, consided the extra function strcpy_P(). 2007-11-02 Eric B. Weddington * include/avr/iom48p.h: New implementation. No common file included. Add Fuse and lockbit definitions. Fix bugs. * include/avr/iom88p.h: Ditto. * include/avr/iom168p.h: Ditto. * include/avr/iom328p.h: Ditto. * include/avr/iomx8p.h: Remove file. * include/avr/Makefile (avr_HEADERS): Remove iomx8p.h from list. 2007-10-30 Joerg Wunsch bug #21432: Incorrect timer interrupt handler names for ATtiny45 * include/avr/iotnx5.h: Add TIMER0..._vect and TIMER1..._vect names in addition to the TIM0... and TIM1... names to match the recently changed datasheet. 2007-10-30 Joerg Wunsch bug #21204: iotnx61.h PRR bits incorrect * include/avr/iotnx61.h: Use correct bit numbers for PRTIM0/PRTIM1. 2007-10-30 Joerg Wunsch bug #21444: Undocument -minit-stack * doc/api/using-tools.dox: Remove references to -minit-stack, add an explanation for how to set __stack in order to relocate the stack. 2007-10-30 Joerg Wunsch bug #20530: Bug in sample code for early wdt disable * include/avr/wdt.h: move variable mcusr_mirror into the .noinit section in example code. 2007-10-30 Joerg Wunsch bug #20248: FAQ#3: clarify which registers are safe to be used * doc/api/faq.dox: Describe that r8...r15 can only be used for register variables if they are not used for argument passing. Clarify that call-saved registers must be preserved even in case they are used for argument passing by the compiler. 2007-10-30 Joerg Wunsch bug #20650: Missing description of AVR specific C-preprocessor macros * doc/api/using-tools.dox: Document the target-specific macros __AVR, __AVR__, AVR, and __NO_INTERRUPTS__. 2007-10-30 Joerg Wunsch bug #18373: Bugs in Inline ASM documentacion * doc/api/inline_asm.dox: Inline asm documentation improvements: . mention named operands . document that read-write constraints to work . explain read-write constraints 2007-10-29 Eric B. Weddington * include/avr/power.h: Add support for ATmega48P-88P-168P-328P devices. 2007-10-29 Joerg Wunsch * include/util/atomic.h: Fix a documentation spelling error. 2007-10-29 Joerg Wunsch * configure.ac: Bump revision to 1.5.1-20071030 in order to indicate post-release 1.5.1-20071029 state. 2007-10-29 Joerg Wunsch * configure.ac: Bump revision to 1.5.1-20071029 in order to prepare for a new (unstable) release. 2007-10-29 Joerg Wunsch Submitted by Dean Camera: Patch #5644: New interrupt.h header file * include/avr/interrupt.h: Complete overhaul of the ISR() and related macros. By Joerg Wunsch: * doc/api/interrupts.dox: Update the interrupt documentation to all the new features. 2007-10-28 Joerg Wunsch Submitted by Florin-Viorel Petrov Patch #6236: Improving _delay_us and _delay_ms * include/util/delay.h: Provide fallback functionality to extend the possible argument range to _delay_us(), and _delay_ms(), respectively. 2007-10-28 Joerg Wunsch Submitted by Cliff Lawson and Carlos Lamas: Patch #5343: Add a util/setbaud.h "helper" file * include/util/setbaud.h: New file. * include/util/Makefile.am: Include setbaud.h. 2007-10-28 Joerg Wunsch Submitted by Dean Camera: Patch #5756: New atomic.h header file * include/util/atomic.h: New file. * include/util/Makefile.am: Include atomic.h. 2007-10-25 Anatoly Sokolov * include/avr/iocanxx.h (OVFG): Define. Closes bug #21434. 2007-10-25 Anatoly Sokolov * include/avr/io90pwmx.h (AMP0EN, AMP0IS, AMP0G1, AMP0G0, AMP0TS1, AMP0TS0, AMP1EN, AMP1IS, AMP1G1, AMP1G0, AMP1TS1, AMP1TS0, ADASCR): Define. Closes bug #20435. 2007-10-25 Anatoly Sokolov * include/avr/io2313.h (TICIE1): Define. Closes bug #20682. 2007-10-25 Anatoly Sokolov * include/avr/iotn13.h (EIN1D): Rename to AIN1D. Closes bug #21411. 2007-10-24 Eric B. Weddington Add Lockbits API. Set the lockbits from within the application. * include/avr/Makefile.am: Add new file to distribution. * include/avr/io.h: Include new lock.h file. * include/avr/iom128.h: Add definitions for API. * include/avr/iom48.h: Ditto. * include/avr/iom88.h: Ditto. * include/avr/iom168.h: Ditto. * include/avr/lock.h: New file. 2007-10-23 Anatoly Sokolov * configure.ac: Add new devices: ATmega48P/88P/168P/328P. * devtools/gen-avr-lib-tree.sh: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/wdt.h: Ditto. * include/avr/iom168p.h: New file. * include/avr/iom328p.h: New file. * include/avr/iom48p.h: New file. * include/avr/iom88p.h: New file. * include/avr/iomx8p.h: New file. * NEWS: Add devices to list. 2007-10-23 Joerg Wunsch Fix bug #21174: assembly error with targets at90s1200, attiny11, attiny12, and attiny28 * crt1/gcrt1.S: for assembly-only architectures, revert to the old behaviour of jumping to main() rather than calling it, and jumping to exit() afterwards. 2007-10-23 Joerg Wunsch Fix for bug #18964: USART definitions *wrong* in iocanxx.h * include/avr/iocanxx.h: Add missing SIG_USART* vector names. 2007-10-23 Joerg Wunsch Submitted by Guohui Wang : Fix for bug #20843: Mega 2561 library * crt0/gcrt0.S: initialize EIND for avr6 architectures to the same segment __vectors belongs to. 2007-10-19 Eric B. Weddington * configure.ac: Add new devices: AT90PWM2B, AT90PWM3B. * devtools/gen-avr-lib-tree.sh: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/power.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/io90pwm2b.h: New file. * include/avr/io90pwm3b.h: New file. * NEWS: Add devices to list. 2007-10-19 Eric B. Weddington Fix for Atmel bug #6346. * include/avr/iom8515.h: Add USART* interrupt vector names to correctly reflect the device XML file. 2007-10-10 Eric B. Weddington Resolve bug #21299: Duplicate register address in iotn48.h. * include/avr/iotn48.h: Fix PRR address. * NEWS: Update fixed bug list. 2007-10-08 Eric B. Weddington * include/avr/io90pwm216.h: Add fuse information. * include/avr/io90pwm316.h: Ditto. * include/avr/iotn43u.h: Ditto. 2007-10-08 Eric B. Weddington Add new device: ATtiny48. * configure.ac: Add new devices. * devtools/gen-avr-lib-tree.sh: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/power.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/iotn48.h: New file. * NEWS: Update new devices list. 2007-10-05 Joerg Wunsch Resolve bug #21228: Missing 3rd clause in BSD license in documentation pages * doc/api/main_page.dox: Add clause #3. * doc/api/using-tools.dox: Add clause #3. 2007-10-05 Joerg Wunsch Unbreak the documentation build for recent versions of doxygen. NB: the latex package "urc" must be installed in order to successfully build the documentation. * doc/api/doxygen.config.in: Update for doxygen 1.5.x. Most of the changes have been generated by running doxygen -u. In addition, the input encoding has been changed to iso-8859-1 because this matches our current documentation. * doc/api/overview.dox: Fix two illegal special characters that were not part of ISO8859-1. 2007-10-03 Eric B. Weddington Add new device: ATtiny43U. * configure.ac: Add new device. * devtools/gen-avr-lib-tree.sh: ditto. * include/avr/Makefile.am: ditto. * include/avr/io.h: ditto. * include/avr/power.h: ditto. * doc/api/using-tools.dox: ditto. * doc/api/main_page.dox: ditto. * include/avr/iotn43u.h: New file. * NEWS: Update new devices list. 2007-10-03 Eric B. Weddington * devtools/gen-avr-lib-tree.sh: Optimize for space for all devices. 2007-10-03 Eric B. Weddington The start of a Fuse API. * include/avr/fuse.h: New file. * include/avr/io.h: Add inclusion of fuse.h. * include/avr/Makefile.am: Add fuse.h to distribution list. * include/avr/iom128.h: Add fuse information to ATmega128 IO header. 2007-10-03 Eric B. Weddington * doc/api/main_page.dox: Reorganize and update device listing. Fix spelling and grammar. 2007-10-02 Eric B. Weddington * doc/api/pgmspace.dox: Fix example code. Change description to match. * NEWS: Update fixed bugs list. Fixes bug #21183. 2007-10-01 Eric B. Weddington Add new devices: AT90PWM216, AT90PWM316, with contributions from Tobias Frost . * devtools/gen-avr-lib-tree.sh: Add new devices. * configure.ac: ditto. * doc/api/using-tools.dox: ditto. * include/avr/Makefile.am: ditto. * include/avr/power.h: ditto. * include/avr/wdt.h: ditto. * include/avr/io.h: ditto. * include/avr/io90pwm216.h: New file. * include/avr/io90pwm316.h: New file. * NEWS: Update new devices list. 2007-07-30 Eric B. Weddington *include/avr/Makefile.am: Add missing common.h to install list. 2007-07-09 Eric B. Weddington * doc/api/inline_asm.dox: Document new constraints. 2007-07-06 Eric B. Weddington * doc/api/faq.dox: Add FAQ for soft reset. 2007-07-01 Dmitry Xmelkov Add new function alloca(). Fix savannah bug #19686: alloca declaration missing. * include/alloca.h: New file. * include/Makefile.am: Add alloca.h file. * doc/api/doxygen.config.in: Add alloca.h file. * tests/simulate/other: New directory. * tests/simulate/other/alloc.c: New file. * tests/simulate/runtest.sh: Add other directory to the test list. 2007-06-27 Eric B. Weddington * include/avr/power.h: Add support for ATmega644P. * NEWS: Add item to fixed bug list. Fixes bug #20276. 2007-06-08 Eric B. Weddington * include/avr/common.h: New file. * include/avr/io.h: Move definitions to common.h. Fix documentation. * common/macros.inc: Use new common register definitions. * crt1/gcrt1.S: Use new common register definitions. * include/avr/iomxx0_1.h: Define EIND as normal without conditional compilation. * libc/stdlib/stdlib_private.h: Use new common register definitions. * doc/api/doxygen.config.in: Add avr/io.h back into the documentation list. * libc/stdlib/setjmp.S: Use new common register definitions. 2007-05-29 Eric B. Weddington * Makefile.am: Add ChangeLog-2006 to distribution list. 2007-05-29 Eric B. Weddington * configure.ac: Revert patch and add devices back into avr2 group. This allows avr-libc to work with previous versions of GCC. * devtools/gen-avr-lib-tree.sh: ditto. 2007-05-22 Eric B. Weddington * devtools/gen-avr-lib-tree.sh: Replace awk with cut, which speeds up the script. Remove devices in avr2 group that have been moved to the avr25 group. * configure.ac: Remove devices in avr2 group that have been moved to the avr25 group. 2007-05-21 Eric B. Weddington * doc/api/tools-install.dox: Add documentation on how to build the toolchain under Windows. Fix for bug #19496. * doc/api/acknowledge.dox: Typo, email address, and add missing clause. * NEWS: Add to bugs fixed list. 2007-05-15 Joerg Wunsch * xml/Atmel2libc.py: Catch (and ignore) errors resulting from empty IO register declarations in the Atmel files, as e.g. for MCUCR in AT86RF401. * xml/patch-headers.py: Add all the new devices we do support now. * doc/api/vectortable.dox: Regenerate. * doc/api/Makefile.am: add vectortable.dox. * include/avr/iotnx4.h: Sigh. AVR Studio 4.13 gratuitously renamed a number of interrupt vectors for ATtinyX4 devices. Add these new declarations along with the older ones. 2007-05-14 Joerg Wunsch * configure.ac: bump version date. 2007-05-14 Joerg Wunsch * doc/api/rel-method.dox: configure.in -> configure.ac 2007-05-14 Joerg Wunsch * common/Makefile.am: Fix file locations for automake so "make distcheck" will compile again. * libc/stdio/Files.am: (Ditto.) * libc/stdlib/Files.am: (Ditto.) 2007-05-13 Joerg Wunsch Fix bug #19009: Make issue a warning when optimizations are turned off * include/util/delay.h: Split the basic delay functions off into ; issue a warning when this file is compiled without optimization. * include/util/delay_basic.h: (New file.) * include/util/Makefile.am: add delay_basic.h 2007-05-13 Anatoly Sokolov * include/avr/iousbxx6_7.h: Change PORTxy to Pxy. 2007-05-13 Anatoly Sokolov * configure.ac: Add tests for the ATmega8HVA/16HVA support. * devtools/gen-avr-lib-tree.sh: Add support for ATmega8HVA/16HVA. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * include/avr/iom8hva.h: New file. * include/avr/iom16hva.h: New file. * include/avr/iomxxhva.h: New file. * include/avr/Makefile.am: Include new files. * doc/api/main_page.dox: Document support for ATmega8HVA/16HVA. * doc/api/using-tools.dox: (Ditto.) 2007-05-12 Anatoly Sokolov * include/avr/iousbxx2.h: Change PORTxy to Pxy. 2007-05-09 Joerg Wunsch Fix bug #19445: _malloc_heap_end does not follow _heap_end on m2561 * doc/api/malloc-std.fig: Clearly distinguish library-internal variables from absolute symbols added by the linker. * doc/api/malloc-x1.fig: (Ditto.) * doc/api/malloc-x2.fig: (Ditto.) 2007-05-09 Joerg Wunsch Fix bug #19841: Error building 1.4 HEAD: undefined reference to 'exit' * doc/api/Makefile.am (DEMO_LIBS): add exit.o to the list of files to link the demo against. 2007-05-08 Joerg Wunsch Fix bug #19050: gcrt1.S should call main rather than jumping to it * crt1/gcrt1.S: call main() rather than jumping to it, and then jump to exit(). 2007-05-07 Anatoly Sokolov * configure.ac: Add 'avr25' architecture. * devtools/gen-avr-lib-tree.sh (AVR_ARH_INFO): Ditto. (AVR25_DEV_INFO): New. * doc/api/using-tools.dox: Document 'avr25'. 2007-05-06 Eric B. Weddington Fix bug #19666: * include/avr/io90pwmx.h: Add ADHSM, ADTS3 bits to the ADCSRB register. 2007-05-05 Eric B. Weddington * doc/examples/asmdemo/asmdemo.dox: Fix HTML code in source code links. 2007-05-05 Eric B. Weddington Fix bug #19495. * include/avr/interrupt.h: Fix doxygen stuff, whitespace, remove unused C++ stuff at the end. * NEWS: Update bugs fixed. 2007-05-02 Eric B. Weddington * doc/api/overview.dox: Fix typos, grammar, names. * doc/api/inline_asm.dox: Expand title name back to the original title. 2007-04-27 Anatoly Sokolov * configure.ac: Move AT90USB82 device to 'avr5' architecture. * devtools/gen-avr-lib-tree.sh: (Ditto.). * doc/api/using-tools.dox: (Ditto.). * include/avr/iousbxx2.h (_VECTORS_SIZE): Redefine for AT90USB82. 2007-04-21 Joerg Wunsch * include/avr/io90pwm3.h: Change bit 2 of PLLCSR from PCKE to PLLF. Fixes savannah bug #19650: avr-libc: wrong named bit in SFR of AT90PWMx 2007-04-05 Eric B. Weddington * doc/api/malloc.dox: Change title and reorder sentences in Introduction. 2007-03-30 Eric B. Weddington * include/avr/io2343.h: Add missing bit definitions for MCUSR. Fixes WinAVR feature request #1657218. 2007-03-30 Dmitry Xmelkov * libc/stdlib/ctype.S: Fix bug #19281: isblank('\v') return TRUE: mismatch to C99 2007-03-29 Eric B. Weddington * doc/api/doxygen.config.in (INPUT): Add new file to list. Reorder list. * doc/api/pgmspace.dox (new file): New chapter. Data in Program Space. * doc/api/library.dox (new file): New chapter. How to Create a Library. * doc/api/porting.dox: Rewrote the introduction for better flow. * doc/api/Makefile.am (EXTRA_DIST): Add new .dox file. * include/avr/pgmspace.h: Change title of documentation. * doc/api/interrupts.dox: Fix typo. Add missing 3rd clause to license. 2007-03-28 Eric B. Weddington * doc/api/doxygen.config.in (INPUT): Add new file to list. Reorder. * doc/api/overview.dox (new file): New chapter. Overview of toolchain. * doc/api/Makefile.am (EXTRA_DIST): Add the two new .dox files. 2007-03-28 Anatoly Sokolov * configure.ac: Add tests for the AT90USB82/162 support. * devtools/gen-avr-lib-tree.sh: Add support for AT90USB82/162. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * include/avr/iousb82.h: New file. * include/avr/iousb162.h: New file. * include/avr/iousbxx2.h: New file. * include/avr/Makefile.am: Include new files. * doc/api/main_page.dox: Document support for AT90USB82/162. * doc/api/using-tools.dox: (Ditto.) 2007-03-26 Eric B. Weddington * doc/api/doxygen.config.in (INPUT): Change order of documentation pages. * doc/api/dox_html_header: Change order of header links. Change Additional Documentation to User Manual. * doc/api/porting.dox (new file): New chapter. Porting from IAR to AVR GCC. Adapted, with permission, from a document written by Eivind Sivertsen. 2007-03-25 Dmitry Xmelkov * libc/stdlib/atoi.S: Exclude the '!=' operator from GAS expression to comport with the old GAS versions (less than 2.17). * libc/stdlib/atol.S: (Ditto.) * libc/string/strcasestr.S: (Ditto.) 2007-03-17 Dmitry Xmelkov Fix bug #19280: snprintf(s,0,fmt,...) write to foreign memory: s[-1] * libc/stdio/snprintf.c: Add check of 'f.size >= 0' before writing of terminating zero. Use f.len as number of output symbols. Remove include of "stdio_private.h" as noused (after moving FILE decl.). * libc/stdio/snprintf_p.c: (Ditto.) * libc/stdio/vsnprintf.c: (Ditto.) * libc/stdio/vsnprintf_p.c: (Ditto.) * tests/simulate/printf/snprintf_all-P.c: New file. * tests/simulate/printf/snprintf_all.c: New file. * tests/simulate/printf/vsnprintf_all-P.c: New file. * tests/simulate/printf/vsnprintf_all.c: New file. * tests/simulate/regression/bug-19280.c: New file. * tests/simulate/regression/bug-19281.c: New file. 2007-03-11 Dmitry Xmelkov Has partially restored former (avr-libc 1.4 and early) behaviour at mistakes in a format string. Processing will be stopped (as in last versions), but return value will be 'len', not EOF. This is more clean behavior. (In comparison, Glibc's printf() return -1 if there is nothing specificator and continue work for other mistakes.) Note, snprintf() function (all 4 variants) has an error, which activates if vfprintf() returns EOF. * libc/stdio/vfprintf.c: Return EOF only if file is not open for writing, return 'len' for all other cases. * include/stdio.h: Update doc about return value. * tests/simulate/printf/sprintf-inv.c: Update. * tests/simulate/printf/sprintf_min-inv.c: Update. 2007-03-10 Dmitry Xmelkov Rewrite the PRINTF_MIN part of vfprintf() function to reduce size and increase speed. Other parts (STD and FLT) was rewriten at begin of Feb 2007. * libc/stdio/vfprintf.c: Rewrite the PRINTF_MIN part. Make a few of small size improvements in second (PRINTF_LEVEL > PRINTF_MIN) part. * include/stdio.h: Update the DOXYGEN description of vfprintf(). * tests/simulate/printf/{sprintf_min-1.c,sprintf_min-2.c, sprintf_min-3.c,sprintf_min-4.c,sprintf_min-5.c,sprintf_min-int.c, sprintf_min-inv.c,sprintf_std-int.c,sprintf_std-inv.c}: New files. * tests/simulate/printf/sprintf_flt-big.c: Remove 'strlen_P' definition, as it is defined in progmem.h . * tests/simulate/progmem.h: Simplify the emulated function defines. * tests/simulate/runtest.sh: Add a possibility to operate a variety of printf variants: min, std, flt. Add the 'printf' directory to the default source list. 2007-03-08 Dmitry Xmelkov Add new function (and progmem variant) memmem(). * libc/string/memmem.S: New file. * libc/string/memmem_P.S: New file. * include/string.h: Add new function definition: memmem(). * include/avr/pgmspace.h: Add new function definition: memmem_P(). * libc/string/Files.am: Add new sources: memmem.S, memmem_P.S * tests/simulate/pmstring/memmem_P.c: New file. * tests/simulate/string/memmem.c: New file. * libc/pmstring/strstr_P.S: Optimize: reduce size by 1..2 words. * libc/string/strstr.S: (Ditto.) 2007-03-06 Dmitry Xmelkov Add new function (and progmem variant) strcasestr(). * libc/string/strcasestr.S: New file. * libc/string/strcasestr_P.S: New file. As it includes the strcasestr.S, this source is placed into `string' directory to avoid a cross-directory link. Doxygen result is normal. * include/string.h: Add new function definition: strcasestr(). * include/avr/pgmspace.h: Add new function definition: strcasestr_P(). * libc/string/Files.am: Add new sources: strcasestr.S, strcasestr_P.S * tests/simulate/pmstring/strcasestr_P.c: New file. * tests/simulate/string/strcasestr.c: New file. 2007-03-03 Dmitry Xmelkov * common/asmdef.h: New file. This file is intended for use in asm sources instead of 'macros.inc'. Last clings a huge chain of dependences, that very much complicates writing/debugging new functions outside of an infrastructure of library. I think, some time both of these files will exist independently. * libc/pmstring/memrchr_P.S: New file. * libc/pmstring/strchrnul_P.S: New file. * include/avr/pgmspace.h: Add new function definitions: memrchr_P(), strchrnul_P(). * libc/pmstring/Files.am: Add new sources: memrchr_P.S, strchrnul_P.S * tests/simulate/pmstring/memrchr_P.c: New file. * tests/simulate/pmstring/strchrnul_P.c: New file. * libc/string/memrchr.S: New file. * libc/string/strchrnul.S: New file. * include/string.h: Add new function definitions: memrchr(), strchrnul(). * libc/string/Files.am: Add new sources: memrchr.S, strchrnul.S * tests/simulate/string/memrchr.c: New file. * tests/simulate/string/strchrnul.c: New file. 2007-03-02 Dmitry Xmelkov * libc/pmstring/strsep_P.S: New file. * include/avr/pgmspace.h: Add new function definition: strsep_P(). * libc/pmstring/Files.am: Add new source: strsep_P.S * tests/simulate/pmstring/strsep_P.c: New file. * libc/string/strsep.S: Optimize size and speed. * tests/simulate/string/strsep.c: New file. * libc/pmstring/memcmp_P.S: Emphasize args names in DOXYGEN comment. Move all CPP operators outside from the DOXYGEN scope. * libc/pmstring/strcasecmp_P.S: (Ditto.) * libc/pmstring/strchr_P.S: (Ditto.) * libc/pmstring/strcmp_P.S: (Ditto.) * libc/pmstring/strncasecmp_P.S: (Ditto.) * libc/pmstring/strstr_P.S: (Ditto.) * libc/string/strcasecmp.S: (Ditto.) * libc/string/strchr.S: (Ditto.) * libc/string/strcmp.S: (Ditto.) * libc/string/strncasecmp.S: (Ditto.) * libc/string/strstr.S: (Ditto.) 2007-03-01 Dmitry Xmelkov Add a few new functions and progmem mirrors: * libc/pmstring/memchr_P.S: New file. * libc/pmstring/strcspn_P.S: New file. * libc/pmstring/strrchr_P.S: New file. * libc/pmstring/strspn_P.S: New file. * libc/string/strcspn.S: New file. * libc/string/strspn.S: New file. * libc/pmstring/Files.am: Add new sources: memchr_P.S, strcspn_P.S, strrchr_P.S, strspn_P.S * libc/string/Files.am: Add new sources: strcspn.S, strspn.S * include/string.h: Add new function definitions: strcspn(), strspn(). * include/avr/pgmspace.h: Add new function definitions: memchr_P(), strcspn_P(), strrchr_P(), strspn_P(). * tests/simulate/pmstring/memchr_P.c: New file. * tests/simulate/pmstring/strcspn_P.c: New file. * tests/simulate/pmstring/strrchr_P.c: New file. * tests/simulate/pmstring/strspn_P.c: New file. * tests/simulate/string/strcspn.c: New file. * tests/simulate/string/strspn.c: New file. Optimize a few of string functions: * libc/string/strlwr.S: Optimize size and speed. * libc/string/strrev.S: Optimize speed for strings 4 bytes long and more. Size is the same. * libc/string/strupr.S: Optimize size and speed. * tests/simulate/string/strlwr.c: New file. * tests/simulate/string/strrev.c: New file. * tests/simulate/string/strupr.c: New file. Add a few of tests: * tests/simulate/pmstring/strstr_P.c: New file. * tests/simulate/string/memchr.c: New file. * tests/simulate/string/strrchr.c: New file. * tests/simulate/string/strstr.c: New file. 2007-02-27 Dmitry Xmelkov Add a new (standart) function strpbrk() and a progmem variant. * libc/pmstring/strpbrk_P.S: New file. * libc/string/strpbrk.S: New file. * libc/pmstring/Files.am: Add new source file strpbrk_P.S * libc/string/Files.am: Add new source file strpbrk.S * include/string.h (strpbrk): Add new function definition. * include/avr/pgmspace.h (strpbrk_P): Add new function definition. * tests/simulate/pmstring/strpbrk_P.c: New file. * tests/simulate/string/strpbrk.c: New file. Enable use an asm variant of atol(). Correct docs. * include/stdlib.h (atol): Change the definition of function: instead to define inline code which use strtol(), now it is a normal definition of external function. Correct the DOXYGEN comment. * include/stdlib.h (atoi): Correct the DOXYGEN comment, delete a conditional define for DOXYGEN specially. * libc/stdlib/atoi.S: Correct the DOXYGEN comment. * libc/stdlib/atol.S: Correct the DOXYGEN comment. 2007-02-26 Dmitry Xmelkov * libc/pmstring/memcmp_P.S: Fix DOXYGEN comment. * libc/pmstring/strchr_P.S: (Ditto.) 2007-02-24 Dmitry Xmelkov * libc/string/strcasecmp.S: Fix bug #19134: strcasecmp(): result sign is not changed by swaping args. * libc/string/strncasecmp.S: (Ditto.) * libc/pmstring/strcasecmp_P.S: (Ditto.) * libc/pmstring/strncasecmp_P.S: (Ditto.) * libc/string/strstr.S: Fix bug #19135: strstr(): `needle' is not always founded. Optimize code. * libc/pmstring/strstr_P.S: (Ditto.) * libc/pmstring/memcmp_P.S: New file. * include/avr/pgmspace.h: Add new function memcmp_P(). * libc/pmstring/Files.am: Add new source file memcmp_P.S * libc/string/strcmp.S: Optimize by 1 word. * libc/pmstring/strcmp_P.S: Optimize by 1 word. * tests/simulate/progmem.h: Add strlen_P() and strcmp_P() emulation. * tests/simulate/pmstring/{memcmp_P.c,strcasecmp_P.c,strcmp_P.c, strncasecmp_P.c}: New files. * tests/simulate/string/{memcmp.c,strcasecmp.c,strcmp.c, strncasecmp.c}: New files. 2007-02-24 Anatoly Sokolov * include/avr/iomxx4.h (SPCR0, SPSR0, SPDR0, SPIE0, SPE0, DORD0, MSTR0, CPOL0, CPHA0, SPR01, SPR00, SPIF0, WCOL0, SPI2X0): Rename to SPCR, SPSR, SPDR, SPIE, SPE, DORD, MSTR, CPOL, CPHA, SPR1, SPR0, SPIF, WCOL, SPI2X. (PRR): Define. Closes bug #18903: ATmega644 register definitions for SPI and PRR (datasheet vs. iom*.h) 2007-02-24 Anatoly Sokolov * configure.ac: Add tests for the ATmega325P, ATmega3250P and ATmega329P support. * devtools/gen-avr-lib-tree.sh: Add support for ATmega325P, ATmega3250P and ATmega329P devices. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * include/avr/iom325.h (BODSE, BODS): Define for ATMega325P. * include/avr/iom3250.h (BODSE, BODS): Define for ATMega3250P. * include/avr/iom329.h (BODSE, BODS, LCDCCD, LCDBD, LCDMDT): Define for ATMega3290P. * doc/api/main_page.dox: Document support for ATmega325P, ATmega3250P and ATmega329P devices. * doc/api/using-tools.dox: (Ditto.) 2007-02-24 Dmitry Xmelkov * tests/simulate/regression/{bug-19134.c,bug-19135.c}: New files. 2007-02-22 Dmitry Xmelkov * libc/stdio/vfprintf.c: Specify behaviour in case of mistakes in a line of a format. * tests/simulate/printf/sprintf-inv.c: New file. * tests/simulate/string/strchr.c: New file. * tests/simulate/pmstring: New directory. * tests/simulate/pmstring/strchr_P.c: New file. * tests/simulate/progmem.h: Add PSTR() emulation. * tests/simulate/runtest.sh: Add pmstring directory into test suite. Correct the return value for internal functions. * libc/string/strchr.S: Reduce program size by 1 word. 2007-02-19 Dmitry Xmelkov * libc/stdio/vfprintf.c: Fix error in __AVR_HAVE_LPMX__ definition. A bit of small space improvements. 2007-02-18 Anatoly Sokolov * include/avr/iotnx61.h (PCMSK0): Set address to 0x23. (PCMSK1): Set address to 0x22. Fix bug #19060: PCMSKx registers transposed in header for attinyX61 2007-02-18 Dmitry Xmelkov STD and FLT vfprintf parts are fully rewriten to reduce size and increase speed. So a set of changes are maiden: * common/ntz.h: New file. * common/ftoa_engine.h: Move from libc/stdlib/. * libc/stdlib/ftoa_engine.h: Move to common/. * libc/pmstring/strchr_P.S: New file. * libc/pmstring/Files.am: Add new source file strchr_P.S * include/avr/pgmspace.h: Add new function strchr_P(). * libc/stdio/xtoa_fast.h: New file. * libc/stdio/ultoa_invert.S: New file. * libc/stdio/Files.am: Add new source file ultoa_invert.S * libc/stdio/vfprintf.c: Parts STD and FLT are fully rewriten. * tests/simulate/printf: New directory. * tests/simulate/printf/{sprintf-1,sprintf-2,sprintf-3,sprintf-4, sprintf-5,sprintf_flt-big,sprintf_flt-e01,sprintf_flt-f01, sprintf_flt-g01,sprintf_flt-g02,sprintf_flt-nan}.c: New files. 2007-02-07 Dmitry Xmelkov * tests/simulate/stdlib/{strtoul-1.c,strtoul-2.c,strtoul-3.c, strtoul.h}: New files. 2007-02-06 Dmitry Xmelkov * tests/simulate/runtest.sh: Add option to stop after error. Add string/*.c to the list. Compile(): small correction. * tests/simulate/progmem.h: Add memcpy_P emulation. * tests/simulate/stdlib/{atol-2,bsearch-1,bsearch-2,bsearch-3, dtostre-01,dtostre-02,dtostre-03,dtostre-04,dtostre-05,dtostre-06, dtostre-expm00,dtostre-minmax,dtostre-nans,dtostre-subnrm, dtostre-zero,dtostrf-01,dtostrf-big,dtostrf-minmax,dtostrf-nans, dtostrf-round,dtostrf-width,strtol-1,strtol-2,strtol-3, strtol-4}.c: New files. * tests/simulate/string: New directory. * tests/simulate/string/{ffs-1,ffsl-1,ffsll-1}.c: New files. 2007-02-05 Joerg Wunsch * doc/api/faq.dox: Add some explanation how to convert raw binary data so they can be linked into the image. 2007-02-05 Dmitry Xmelkov * libc/stdlib/atoi.S: Fix bug #18899: atoi and atol do not handle vertical tab properly. Reduce program size considarably. * libc/stdlib/atol.S: (Ditto.) * devtools/table.tar.bz2: Remove as a test directory will expanded. * tests/: New directory. 2007-02-03 Anatoly Sokolov * include/avr/iotnx61.h (WGM00, PWM1X) Define. Closes bug #18915: PWM1X Bit missing for ATtiny261/461/861 2007-01-30 Anatoly Sokolov * /doc/api/using-tools.dox: Document GCC macros. 2007-01-27 Anatoly Sokolov * include/avr/iom3290.h (BODSE, BODS, LCDCCD, LCDBD, LCDMDT): Define for ATMega3290P. * include/avr/iom3290p.h: Delete. * include/avr/Makefile.am (avr_HEADERS): Delete iom3290p.h. * include/avr/io.h: Include iom3290.h instead iom3290p.h. 2007-01-23 Joerg Wunsch * include/assert.h: Add \file doxygen directive. * include/ctype.h: (Ditto.) * include/errno.h: (Ditto.) * include/inttypes.h: (Ditto.) * include/math.h: (Ditto.) * include/setjmp.h: (Ditto.) * include/stdint.h: (Ditto.) * include/stdio.h: (Ditto.) * include/stdlib.h: (Ditto.) * include/string.h: (Ditto.) * include/avr/boot.h: (Ditto.) * include/avr/eeprom.h: (Ditto.) * include/avr/interrupt.h: (Ditto.) * include/avr/io.h: (Ditto.) * include/avr/pgmspace.h: (Ditto.) * include/avr/power.h: (Ditto.) * include/avr/sleep.h: (Ditto.) * include/avr/wdt.h: (Ditto.) * include/util/crc16.h: (Ditto.) * include/util/delay.h: (Ditto.) * include/util/parity.h: (Ditto.) * include/util/twi.h: (Ditto.) * libc/pmstring/memcpy_P.S: (Ditto.) * libc/pmstring/strcasecmp_P.S: (Ditto.) * libc/pmstring/strcat_P.S: (Ditto.) * libc/pmstring/strcmp_P.S: (Ditto.) * libc/pmstring/strcpy_P.S: (Ditto.) * libc/pmstring/strlcat_P.S: (Ditto.) * libc/pmstring/strlcpy_P.S: (Ditto.) * libc/pmstring/strlen_P.S: (Ditto.) * libc/pmstring/strncasecmp_P.S: (Ditto.) * libc/pmstring/strncat_P.S: (Ditto.) * libc/pmstring/strncmp_P.S: (Ditto.) * libc/pmstring/strncpy_P.S: (Ditto.) * libc/pmstring/strnlen_P.S: (Ditto.) * libc/pmstring/strstr_P.S: (Ditto.) * libc/stdio/fdevopen.c: (Ditto.) * libc/stdlib/atoi.S: (Ditto.) * libc/stdlib/atol.S: (Ditto.) * libc/string/ffs.S: (Ditto.) * libc/string/ffsl.S: (Ditto.) * libc/string/ffsll.S: (Ditto.) * libc/string/memccpy.S: (Ditto.) * libc/string/memchr.S: (Ditto.) * libc/string/memcmp.S: (Ditto.) * libc/string/memcpy.S: (Ditto.) * libc/string/memmove.S: (Ditto.) * libc/string/memset.S: (Ditto.) * libc/string/strcasecmp.S: (Ditto.) * libc/string/strcat.S: (Ditto.) * libc/string/strchr.S: (Ditto.) * libc/string/strcmp.S: (Ditto.) * libc/string/strcpy.S: (Ditto.) * libc/string/strlcat.S: (Ditto.) * libc/string/strlcpy.S: (Ditto.) * libc/string/strlen.S: (Ditto.) * libc/string/strlwr.S: (Ditto.) * libc/string/strncasecmp.S: (Ditto.) * libc/string/strncat.S: (Ditto.) * libc/string/strncmp.S: (Ditto.) * libc/string/strncpy.S: (Ditto.) * libc/string/strnlen.S: (Ditto.) * libc/string/strrchr.S: (Ditto.) * libc/string/strrev.S: (Ditto.) * libc/string/strsep.S: (Ditto.) * libc/string/strstr.S: (Ditto.) * libc/string/strtok_r.S: (Ditto.) * libc/string/strupr.S: (Ditto.) * doc/api/dox_html_header: Include reference to alphabetical globals list, collected from all files that have \file. * doc/api/dox.css: Update for doxygen version 1.4.7. 2007-01-23 Joerg Wunsch Various documentation fixes. * xml/patch-headers.py: Update for new devices. * doc/api/vectortable.dox: Regenerate from patch-headers.py. Closes bug #18686: AT90USB**** devices are absent in interrupt-verctor-names table * include/stdlib.h: Fix doxygen generation for dtostr*() functions. Closes bug #18726: the dtostrf function description is missing in AVR-Libc's webpage * doc/api/faq.dox: Resolve some doxygen warnings. * doc/examples/asmdemo/asmdemo.dox: (Ditto.) * doc/examples/demo/demo.dox: (Ditto.) 2007-01-23 Joerg Wunsch Cosmetic/white space change only: * include/avr/iocanxx.h: Regenerate vector table from script. * include/avr/iom406.h: (Ditto.) * include/avr/iomxx4.h: (Ditto.) * include/avr/iotn2313.h: (Ditto.) * include/avr/iousbxx6_7.h: (Ditto.) 2007-01-23 Joerg Wunsch * LICENSE: Update copyright year. * doc/api/main_page.dox: Include copyright notice into documentation. 2007-01-21 Joerg Wunsch * include/avr/iomxx4.h: Clarify a confusing comment that all the picopower devices covered by this file feature a second USART. 2007-01-19 Joerg Wunsch * doc/examples/largedemo/largedemo.c: Port the "largedemo" to the ATtiny2313. * doc/examples/largedemo/largedemo.dox: Describe the ATtiny2313 port. * doc/examples/largedemo/Makefile: Add a MCU_TARGET hint for the ATtiny2313. 2007-01-18 Anatoly Sokolov * common/macros.inc (__AVR_HAVE_MUL__): Define. * libc/misc/mul10.S (__mulhi_const_10): Use __AVR_HAVE_MUL__ instead of __AVR_ENHANCED__. 2007-01-15 Dmitry Xmelkov * devtools/table.tar.bz2: New file. This is a test tarball of float point functions, table mode test. This is a temporary variant, so it is a tarball. See 'table/tst-all.sh' for run instruction. 2007-01-14 Anatoly Sokolov * configure.ac: Add tests for the AT90PWM1 support. * devtools/gen-avr-lib-tree.sh: Add support for AT90PWM1 device. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * include/avr/io90pwm1.h: new file. * include/avr/Makefile.am: include new file. * doc/api/main_page.dox: Document support for AT90PWM1 device. * doc/api/using-tools.dox: (Ditto.) 2007-01-14 Dmitry Xmelkov * bootstrap: Version 2.60 for autoconf is added. New version of math library: * libm/fplib/{dtostre.S,dtostrf.S,fp_cosinus.S,fp_flashconst.S, fp_inverse.S,fp_m_inf.S,fp_merge.S,fp_p_inf.S,fp_powerseries.S, fp_split.S,fplib.inc,isinfnan.S,readme.dtostre,readme.fplib, readme.strtod,strtod.S}: Removed. * libm/fplib/{asmdef.h,copysign.S,fdim.S,fixsfdi.S,floatdisf.S, floatunsdisf.S,fma.S,fmax.S,fmin.S,fp32def.h,fp_arccos.S,fp_inf.S, fp_mintl.S,fp_mpack.S,fp_negdi.S,fp_norm2.S,fp_powser.S, fp_powsodd.S, fp_pscA.S,fp_pscB.S,fp_rempio2.S,fp_round.S,fp_sinus.S,fp_split3.S, fp_trunc.S,hypot.S,inverse.S,isfinite.S,isinf.S,isnan.S,ntz.h, signbit.S,trunc.S}: New files. * libm/fplib/{Files.am,acos.S,addsf3.S,addsf3x.S,asin.S,atan.S, atan2.S,ceil.S,cos.S,cosh.S,divsf3.S,divsf3x.S,exp.S,fixsfsi.S, floatsisf.S,floor.S,fmod.S,fp_cmp.S,fp_nan.S,fp_zero.S,frexp.S, ldexp.S,log.S,log10.S,modf.S,mulsf3.S,mulsf3x.S,negsf2.S,pow.S, sin.S,sinh.S,sqrt.S,square.S,tan.S,tanh.S}: Replaced. * libc/stdlib/{atof.S,dtoa_conv.h,dtoa_prf.c,dtostre.c,dtostrf.c, ftoa_engine.S,ftoa_engine.h,strtod.c}: New files. * libc/stdlib/Files.am: A set of new files added. * include/math.h: A set of new functions added. * include/stdlib.h (dtostrf): doc is corrected 2007-01-14 Joerg Wunsch Submitted by Robert Schiele: * include/stdint.h: Exclude 64-bit types when -mint8 is in effect. * include/avr/pgmspace.h: (Ditto.) 2007-01-08 Joerg Wunsch * include/avr/boot.h (boot_lock_bits_set): Fix a typo: BLB11 needs to be programmed (rather than BLB12) in order to prevent the application from overwriting the boot loader section. Closes bug #18115: online documentation typo/bug avr/boot.h 2007-01-08 Joerg Wunsch * include/stdio.h: Document that malloc() is no longer needed for floating-point conversions as it once used to be. Closes bug #18688: vfscanf and vfprintf don't use malloc 2007-01-08 Joerg Wunsch Fix broken seeding of the PRNGs when seeding with 0. This fix is courtesy Andrew Chernov from the FreeBSD project (rev. 1.21 of their random.c). * libc/stdlib/random.c (do_random): seed with another (arbitrary) value when attempting to seed with 0. * libc/stdlib/rand.c (do_rand): (Ditto.) Closes bug #18662: rand() keeps returning the same value if seeded with 0 For older changes see ChangeLog-2006 avr-libc-1.8.0.orig/README0000644000000000000000000000114111732702554011727 0ustar This is avr-libc. It is a C library implementation for use with GNU GCC and GNU binutils for development of programs for Atmel's AVR microcontrollers. The current branch (1.3), requires the following versions of gcc and binutils: Tool Minimal Version Preferred Version =========== =============== ================= binutils 2.13 Latest gcc 3.3 Latest 3.4.x For details on installing and using AVR Libc, see the users manual in the doc/api directory or online at: http://savannah.nongnu.org/projects/avr-libc/ avr-libc-1.8.0.orig/scripts/0000755000000000000000000000000011732702554012541 5ustar avr-libc-1.8.0.orig/scripts/avr-man.in0000644000000000000000000000323711732702554014437 0ustar #! /bin/sh # Copyright (c) 2004, Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. ## man(1) replacement to access the avr-libc manual pages : ${DESTDIR:-} prefix=@prefix@ datadir=@datadir@ exec man -M @DOC_INST_DIR@/man "$@" avr-libc-1.8.0.orig/scripts/Makefile.in0000644000000000000000000003352211732702554014613 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2005, Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 857 2005-09-07 20:31:27Z joerg_wunsch $ # avrdir = $(prefix)/bin avr_SCRIPTS = \ avr-man EXTRA_DIST = \ avr-man.in CLEANFILES = $(avr_SCRIPTS) do_subst = sed \ -e 's,[@]prefix[@],$(prefix),g' \ -e 's,[@]datadir[@],$(datadir),g' \ -e 's,[@]DOC_INST_DIR[@],$(DOC_INST_DIR),g' avr-man: avr-man.in $(top_builddir)/stamp-h1 $(do_subst) < $(srcdir)/avr-man.in > avr-man chmod +x avr-man avr-libc-1.8.0.orig/LICENSE0000644000000000000000000000466111732702554012066 0ustar The contents of avr-libc are licensed with a Modified BSD License. All of this is supposed to be Free Software, Open Source, DFSG-free, GPL-compatible, and OK to use in both free and proprietary applications. See the license information in the individual source files for details. Additions and corrections to this file are welcome. ******************************************************************************* Portions of avr-libc are Copyright (c) 1999-2010 Keith Gudger, Bjoern Haase, Steinar Haugen, Peter Jansen, Reinhard Jessich, Magnus Johansson, Artur Lipowski, Marek Michalkiewicz, Colin O'Flynn, Bob Paddock, Reiner Patommel, Michael Rickman, Theodore A. Roth, Juergen Schilling, Philip Soeberg, Anatoly Sokolov, Nils Kristian Strom, Michael Stumpf, Stefan Swanepoel, Eric B. Weddington, Joerg Wunsch, Dmitry Xmelkov, The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* avr-libc-1.8.0.orig/ChangeLog-20080000644000000000000000000016437511732702554013233 0ustar 2008-12-22 Eric B. Weddington * configure.ac: Add support for AT90SCR100. * devtools/gen-avr-lib-tree.sh: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * include/avr/power.h: Same. * include/avr/sleep.h: Same. * include/avr/wdt.h: Same. * include/avr/io90scr100.h: New file. * NEWS: Add news item. 2008-12-21 Eric B. Weddington * include/avr/Makefile.am: Remove builtins.h, as it is too soon to commit. 2008-12-21 Dmitry Xmelkov Make _FFS() macro usable in CPP conditional expressions. Seems, the CPP parser is wrong with a few of '?:' operations. (The CC parser is correct.) * include/string.h: Rewrite _FFS() to workaround the difference between CPP and CC parsers. Add a note about the 16 bits width of this macro. * tests/simulate/regression/20081221-ffs.c: New file. * tests/simulate/string/ffs_macro.c: New file. * tests/simulate/regression/bug-25048.cpp: Fix typo in comment. 2008-12-19 Eric B. Weddington * include/avr/wdt.h: Add support for ATmega329P * include/avr/power.h: Add support for ATmega329P and ATmega3290P. 2008-12-17 Eric B. Weddington Fix for SourceForge bug #2411516. * include/avr/iotn88.h: Fix definition of CTC0. 2008-12-16 Eric B. Weddington Fix for SourceForge bug #2420567. * include/avr/sleep.h: Add missing ATmega329P. 2008-12-16 Anatoly Sokolov * doc/api/using-tools.dox: Document the -mno-tablejump switch as deprecated. Add description for the -fno-jump-tables switch. 2008-12-13 Dmitry Xmelkov Fix for bug #25048: eeprom.h will not compile as c++ code. * include/avr/eeprom.h: Undo (partially) the rev 1.27 (before 2008-08-19), eeprom_read_byte(): cast operation of address into 16-bit integer regardless of EEPROM size. Change (this is cosmetic) the (unsigned) cast to (size_t) cast in both byte functions. * test/simulate/regression/bug-25048.cpp: New file. TODO: add to 'runtest.sh' the possibility to operate C++ files. Today this file is ignored. * NEWS: Add to fixed bug list. 2008-12-06 Dmitry Xmelkov * common/asmdef.h: Move an explanation string of '.err' pseudo operation from arg to comment, as this pseudo op does not permit any args. * libm/fplib/asmdef.h: Move an explanation string of '.err' pseudo operation from arg to comment, as this pseudo op does not permit any args. Add the standart banner about license. Add CVS ident keyword. Permit the capital 'R' in args of 'X_movw' macro. Merge the arg parse of 'X_movw' and 'X_lpm' macroses into the one REGNO macro. * libm/fplib/fp_split3.S: Fix typo in comment. 2008-12-02 Dmitry Xmelkov Minor optimization of fp_rempio2(), which is used in sin(), cos() and tan() functions. The size of libm is reduced by 11 words. Speed of sin/cos/tan is increased a little in average, besides the interval from 1 to Pi/2 radians, where the performance is worsen by 6 cycles. Thanks to Ruud v Gessel. * libm/fplib/fp_rempio2.S: Rewritten to reduce size. * libm/fplib/fp_mpack.S: Reduce size by 2 words. Add extra entry __fp_mpack_finite(). * tests/simulate/math/fp_mpack-01.c: New file. * doc/api/bench-libm.dox: Update calculation times. * NEWS: Note about sin/cos/tan optimization. 2008-11-25 Dmitry Xmelkov Optimize the sqrt() function. Thanks to Ruud v Gessel. * libm/fplib/sqrt.S: Improve to speed up (230 clocks in average) and reduce size (12 words). * tests/simulate/math/sqrt-01.c: Add a few test cases. * NEWS: Add to optimized function list and patches applied. * AUTHORS: Add Ruud v Gessel to list. * doc/api/bench-libm.dox: Update calculation times. 2008-11-24 Eric B. Weddington * configure.ac: Fix grouping of ATtiny13A. Thanks to Anatoliy Sokolov. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/iotn13a.h: Add definition of EEARL. 2008-11-23 Dmitry Xmelkov Fix for bug #24890. Thanks to Ruud v Gessel. * libm/fplib/fp_rempio2.S: Fix misprint in SPLIT_PIO2 value. Note, it was in rare cases influence the performance only. * tests/simulate/math/cos-02.c: New file. * NEWS: Add to fixed bug list. 2008-11-17 Eric B. Weddington Fix for SF bug #2305703. * include/avr/iom162.h: Add TCN2UB definition. 2008-11-06 Joerg Wunsch * configure.ac: Bump version date for the removal of the PS documentation. 2008-11-06 Joerg Wunsch * doc/api/Makefile.am: Do not build Postscript documentation anymore. The printing quality of PDF is the same as for PS, and it saves as a separate doxygen run using ugly Makefile hacks. A bug in doxygen 1.5.7 where GENERATE_HTML can no longer be turned off was the triggering event for this step which I've long since intended to do. * doc/api/doxygen.config.in: Generate PDF by default, using hyperlinks. * configure.ac: Remove all traces of the Postscript documentation build. 2008-11-06 Eric B. Weddington * doc/api/tools-install.dox: Add more instructions for installing ghostscript for Windows tools. 2008-11-06 Joerg Wunsch * doc/api/doxygen.config.in: Update to doxygen version 1.5.7, by running doxygen -u on it. 2008-11-06 Eric B. Weddington Fix for bug #24762. * include/avr/wdt.h: Fix conditional compilation. * include/avr/sleep.h: Same. 2008-11-03 Eric B. Weddington * devtools/gen-avr-lib-tree.sh: Add missing semicolons for new devices. 2008-11-02 Eric B. Weddington * include/avr/iox128a1.h: Update header file from XML part description files. * include/avr/iox64a1.h: Same. * include/avr/iox64a3.h: Same. * include/avr/iox128a3.h: Same. * include/avr/iox256a3.h: Same. * include/avr/iox256a3b.h: Same. Add support for ATxmega64A3, ATxmega128A3, ATxmega256A3, ATxmega256A3B. * configure.ac: Add support for new devices. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/power.h: Same. Also fix register names. * include/avr/wdt.h: Same. * include/avr/sleep.h: Same. 2008-10-30 Eric B. Weddington Add support for ATmega32U6. * configure.ac: Add support for ATmega32U6. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/power.h: Same. * include/avr/wdt.h: Same. * include/avr/sleep.h: Same. * include/avr/iom32u6.h: New file. 2008-10-28 Eric B. Weddington * include/avr/iox64a3.h: Update the xmega A3 header files. * include/avr/iox128a3.h: Same. * include/avr/iox256a3.h: Same. * include/avr/iox256a3b.h: Same. * include/avr/iox256a3v.h: Remove file. Device does not exist. 2008-10-21 Eric B. Weddington Patch #6517 submitted by Anton Ivanov. * include/avr/pgmspace.h: Add float support to pgmspace.h. 2008-10-21 Eric B. Weddington * xml/avrgcc-header: Change all temporary filenames to be unique to allow script to be run in parallel. Move output of blank line in log file. 2008-10-19 Eric B. Weddington * include/avr/iox128a1.h: Update header file from XML source. * include/avr/iox64a1.h: Same. * include/avr/iox64a3.h: New header file for new device. * include/avr/iox128a3.h: Same. * include/avr/iox256a3.h: Same. * include/avr/iox256a3b.h: Same. * include/avr/iox256a3v.h: Same. 2008-10-17 Eric B. Weddington Fix bug #22540. * include/avr/io90pwm316.h: Add signature information. * include/avr/io90pwm216.h: Same. * include/avr/io90pwm3b.h: Same. * include/avr/io90pwm2b.h: Same. * include/avr/iom1281.h: Same. * include/avr/iom32.h: Same. * include/avr/iom32c1.h: Same. * include/avr/iom32m1.h: Same. * include/avr/iom48p.h: Same. * include/avr/iom64.h: Same. * include/avr/iom88.h: Same. * include/avr/iom88p.h: Same. * include/avr/iom128.h: Same. * include/avr/iom161.h: Same. * include/avr/iom162.h: Same. * include/avr/iom163.h: Same. * include/avr/iom165.h: Same. * include/avr/iom165p.h: Same. * include/avr/iom168.h: Same. * include/avr/iom168p.h: Same. * include/avr/iom169.h: Same. * include/avr/iom169p.h: Same. * include/avr/iom323.h: Same. * include/avr/iom325.h: Same. * include/avr/iom328p.h: Same. * include/avr/iom329.h: Same. * include/avr/iom406.h: Same. * include/avr/iom640.h: Same. * include/avr/iom644.h: Same. * include/avr/iom645.h: Same. * include/avr/iom649.h: Same. * include/avr/iom1280.h: Same. * include/avr/iom1284p.h: Same. * include/avr/iom2560.h: Same. * include/avr/iom2561.h: Same. * include/avr/iom3250.h: Same. * include/avr/iom3290.h: Same. * include/avr/iom6450.h: Same. * include/avr/iom6490.h: Same. * include/avr/iom8515.h: Same. * include/avr/iom8535.h: Same. * include/avr/iocan32.h: Same. * include/avr/iocan64.h: Same. * include/avr/iocan128.h: Same. * include/avr/iom8.h: Same. * include/avr/iom16.h: Same. * include/avr/iom16hva.h: Same. * include/avr/iousb647.h: Same. * include/avr/iousb1286.h: Same. * include/avr/iotn11.h: Same. * include/avr/iotn12.h: Same. * include/avr/iotn13.h: Same. * include/avr/iotn15.h: Same. * include/avr/iotn22.h: Same. * include/avr/iotn24.h: Same. * include/avr/iotn25.h: Same. * include/avr/iotn26.h: Same. * include/avr/iotn28.h: Same. * include/avr/iotn43u.h: Same. * include/avr/iotn44.h: Same. * include/avr/iotn45.h: Same. * include/avr/iotn48.h: Same. * include/avr/iotn84.h: Same. * include/avr/iotn85.h: Same. * include/avr/iotn88.h: Same. * include/avr/iotn261.h: Same. * include/avr/iotn461.h: Same. * include/avr/iotn861.h: Same. * include/avr/iotn2313.h: Same. * include/avr/iousb162.h: Same. * include/avr/iousb646.h: Same. 2008-10-17 Eric B. Weddington Fix bug #24207. * include/inttypes.h: Add missing '%' characters to documentation. 2008-10-09 Eric B. Weddington * include/avr/sleep.h: Change PM_SLEEP_CTRL to SLEEP_CTRL for xmega devices. 2008-10-07 Eric B. Weddington * crt1/gcrt1.S: Clear the RAMPZ register after __do_copy_data for devices > 64K flash. 2008-10-04 Joerg Wunsch bug #24446: _attribute_ should be __attribute__ (with double underscores) * include/avr/wdt.h: Fix spelling mistake. 2008-09-30 Eric B. Weddington Fix bug #21623. * include/avr/boot.h (__boot_page_fill_normal, __boot_page_fill_alternate, __boot_page_erase_normal, __boot_page_erase_alternate, __boot_page_write_normal, __boot_page_write_alternate): Use the 'z' constraint instead of explictly r30,r31. Thanks to Shaun Jackman for initial patch. 2008-09-19 Joerg Wunsch * bootstrap: Allow for autoconf 2.62. 2008-09-16 Eric B. Weddington * doc/api/tools-install.dox: Update tools for Windows builds. 2008-09-11 Eric B. Weddington * include/avr/iox128a1.h: Re-generate file. * include/avr/iox64a1.h: Same. 2008-09-10 Eric B. Weddington * include/avr/iotn26.h: Fix LFUSE_DEFAULT setting. 2008-09-10 Eric B. Weddington * include/avr/wdt.h: Overhaul inline assembly in wdt_enable() for xmega devices. Remove indentation on another macro. 2008-09-10 Eric B. Weddington * include/avr/wdt.h: Add missing comma in inline assembly for xmega devices. 2008-09-08 Eric B. Weddington * xml/avrgcc-header: Fix xmega header file generation to include all group mask and group position definitions. Add interrupt number generation to xmega devices. Remove blank line from classic device generation. 2008-09-08 Eric B. Weddington * include/avr/iotnx61.h: Fix misspelled bit name for TCCR0B. 2008-09-07 Eric B. Weddington * xml/avrgcc-header: Add script to convert an Atmel XML device file to a header file for inclusion in avr-libc. 2008-08-22 Anatoly Sokolov * configure.ac: Add the AT43USB320 device to avr31 architecture. 2008-08-21 Eric B. Weddington Fix for SourceForge bug #2033993. * doc/api/malloc.dox: Fix linker flags in description and add a note describing why certain linker flags have to be used. 2008-08-20 Eric B. Weddington * libc/string/strtok.c: Fix cut and paste error with strtok implementation. * include/string.h: Same. 2008-08-20 Shaun Jackman Eric B. Weddington Fix for bug #21622. * devtools/Architecture.am (AM_CPPFLAGS): Add -I$(top_builddir)/include to support building in a subdirectory. * devtools/Device.am (AM_CPPFLAGS): Same. 2008-08-20 Eric B. Weddington Fix for bug #23409. * include/string.h: Add prototype of new strtok function. * libc/string/strtok_r.S: Fix doxygen description of function. * libc/string/strtok.c: New file with strtok function. * libc/string/Files.am: Add new file to list. 2008-08-20 Eric B. Weddington Contributed by Lars Jonsson Fix bug #22572. * doc/api/faq.dox: Add Makefile fragments for converting text and binary data to an object file. 2008-08-19 Eric B. Weddington Contributed by Stu Bell. Fix bug #22878. * include/avr/eeprom.h: For the ATmega256x devices, do not call any functions to implement the EEPROM routines as they have problems if they are in high memory. So for these devices we inline the functionality. 2008-08-19 Eric B. Weddington Contributed by Mark Litwack. Patch #6500 * doc/api/faq.dox: Add FAQ about reentrant code and functions in avr-libc. * api/main_page.dox: Add reference to new FAQ. 2008-08-19 Eric B. Weddington Fix for bug #23969. * include/avr/eeprom.h: Change part of the EEPROM read routine to inline assembly to avoid problems with certain AVR parts. 2008-08-13 Eric B. Weddington * include/avr/sleep.h: Add support for ATmega3290P. * include/avr/wdt.h: Same. 2008-08-13 Eric B. Weddington Fix for bug #22240. * include/avr/io.h: Add E2PAGESIZE constant to documentation. Clean up phrasing in documentation. * include/avr/io1200.h (E2PAGESIZE): Defined. * include/avr/io2313.h: Same. * include/avr/io2323.h: Same. * include/avr/io2343.h: Same. * include/avr/io4414.h: Same. * include/avr/io4433.h: Same. * include/avr/io4434.h: Same. * include/avr/io8515.h: Same. * include/avr/io8535.h: Same. * include/avr/io86r401.h: Same. * include/avr/io90pwm216.h: Same. * include/avr/io90pwm2b.h: Same. * include/avr/io90pwm316.h: Same. * include/avr/io90pwm3b.h: Same. * include/avr/io90pwmx.h: Same. * include/avr/iocan128.h: Same. * include/avr/iocan32.h: Same. * include/avr/iocan64.h: Same. * include/avr/iom103.h: Same. * include/avr/iom128.h: Same. * include/avr/iom1280.h: Same. * include/avr/iom1281.h: Same. * include/avr/iom1284p.h: Same. * include/avr/iom16.h: Same. * include/avr/iom161.h: Same. * include/avr/iom162.h: Same. * include/avr/iom163.h: Same. * include/avr/iom164.h: Same. * include/avr/iom165.h: Same. * include/avr/iom165p.h: Same. * include/avr/iom168.h: Same. * include/avr/iom168p.h: Same. * include/avr/iom169.h: Same. * include/avr/iom169p.h: Same. * include/avr/iom16hva.h: Same. * include/avr/iom2560.h: Same. * include/avr/iom2561.h: Same. * include/avr/iom32.h: Same. * include/avr/iom323.h: Same. * include/avr/iom324.h: Same. * include/avr/iom325.h: Same. * include/avr/iom3250.h: Same. * include/avr/iom328p.h: Same. * include/avr/iom329.h: Same. * include/avr/iom3290.h: Same. * include/avr/iom32c1.h: Same. * include/avr/iom32m1.h: Same. * include/avr/iom406.h: Same. * include/avr/iom48.h: Same. * include/avr/iom48p.h: Same. * include/avr/iom64.h: Same. * include/avr/iom640.h: Same. * include/avr/iom644.h: Same. * include/avr/iom645.h: Same. * include/avr/iom6450.h: Same. * include/avr/iom649.h: Same. * include/avr/iom6490.h: Same. * include/avr/iom8.h: Same. * include/avr/iom8515.h: Same. * include/avr/iom8535.h: Same. * include/avr/iom88.h: Same. * include/avr/iom88p.h: Same. * include/avr/iom8hva.h: Same. * include/avr/iotn11.h: Same. * include/avr/iotn12.h: Same. * include/avr/iotn13.h: Same. * include/avr/iotn15.h: Same. * include/avr/iotn22.h: Same. * include/avr/iotn2313.h: Same. * include/avr/iotn24.h: Same. * include/avr/iotn25.h: Same. * include/avr/iotn26.h: Same. * include/avr/iotn261.h: Same. * include/avr/iotn28.h: Same. * include/avr/iotn43u.h: Same. * include/avr/iotn44.h: Same. * include/avr/iotn45.h: Same. * include/avr/iotn461.h: Same. * include/avr/iotn48.h: Same. * include/avr/iotn84.h: Same. * include/avr/iotn85.h: Same. * include/avr/iotn861.h: Same. * include/avr/iotn88.h: Same. * include/avr/iousb1286.h: Same. * include/avr/iousb1287.h: Same. * include/avr/iousb162.h: Same. * include/avr/iousb646.h: Same. * include/avr/iousb647.h: Same. * include/avr/iousb82.h: Same. 2008-08-10 Eric B. Weddington * include/avr/iomxx4.h: Remove definitions that were causing duplicate definitions in portpins.h. 2008-08-09 Anatoly Sokolov * devtools/gen-avr-lib-tree.sh (AVR31_DEV_INFO): Add the at43usb320 device. * doc/api/using-tools.dox: Move the AT43USB320 device to avr31 architecture. 2008-08-06 Eric B. Weddington Fix for bug #23774. * include/avr/io90pwm2b.h: Add typecast to fuse definitions. * include/avr/io90pwm3b.h: Same. * include/avr/io90pwm216.h: Same. * include/avr/io90pwm316.h: Same. * include/avr/io90pwmx.h: Same. * include/avr/io90pwm1.h: Same. * include/avr/io8535.h: Same. * include/avr/io1200.h: Same. * include/avr/io2313.h: Same. * include/avr/io2323.h: Same. * include/avr/io2343.h: Same. * include/avr/io4414.h: Same. * include/avr/io443.h: Same. * include/avr/iom32m1.h: Same. * include/avr/iom32u4.h: Same. * include/avr/iom48.h: Same. * include/avr/iom48p.h: Same. * include/avr/iom64.h: Same. * include/avr/iom88.h: Same. * include/avr/iom88p.h: Same. * include/avr/iocan32.h: Same. * include/avr/iocan64.h: Same. * include/avr/iocan128.h: Same. * include/avr/iom8.h: Same. * include/avr/iom8hva.h: Same. * include/avr/iom16.h: Same. * include/avr/iom16hva.h: Same. * include/avr/iom32.h: Same. * include/avr/iom32c1.h: Same. * include/avr/iom32hvb.h: Same. * include/avr/iom164.h: Same. * include/avr/iom165.h: Same. * include/avr/iom165p.h: Same. * include/avr/iom168.h: Same. * include/avr/iom168p.h: Same. * include/avr/iom169.h: Same. * include/avr/iom169p.h: Same. * include/avr/iom103.h: Same. * include/avr/iom128.h: Same. * include/avr/iom161.h: Same. * include/avr/iom162.h: Same. * include/avr/iom163.h: Same. * include/avr/iom406.h: Same. * include/avr/iom640.h: Same. * include/avr/iom644.h: Same. * include/avr/iom645.h: Same. * include/avr/iom649.h: Same. * include/avr/iom323.h: Same. * include/avr/iom324.h: Same. * include/avr/iom325.h: Same. * include/avr/iom328.h: Same. * include/avr/iom329.h: Same. * include/avr/iom8515.h: Same. * include/avr/iom8535.h: Same. * include/avr/iom1280.h: Same. * include/avr/iom1281.h: Same. * include/avr/iom1284p.h: Same. * include/avr/iom2560.h: Same. * include/avr/iom2561.h: Same. * include/avr/iom3250.h: Same. * include/avr/iom3290.h: Same. * include/avr/iom6450.h: Same. * include/avr/iom6490.h: Same. * include/avr/iotn88.h: Same. * include/avr/iotn167.h: Same. * include/avr/iotn261.h: Same. * include/avr/iotn461.h: Same. * include/avr/iotn861.h: Same. * include/avr/iotn2313.h: Same. * include/avr/iotn11.h: Same. * include/avr/iotn12.h: Same. * include/avr/iotn13.h: Same. * include/avr/iotn13a.h: Same. * include/avr/iotn15.h: Same. * include/avr/iotn22.h: Same. * include/avr/iotn24.h: Same. * include/avr/iotn25.h: Same. * include/avr/iotn26.h: Same. * include/avr/iotn28.h: Same. * include/avr/iotn43u.h: Same. * include/avr/iotn44.h: Same. * include/avr/iotn45.h: Same. * include/avr/iotn48.h: Same. * include/avr/iotn84.h: Same. * include/avr/iotn85.h: Same. * include/avr/iox64a1.h: Same. * include/avr/iox128a1.h: Same. * include/avr/iousb82.h: Same. * include/avr/iousb162.h: Same. * include/avr/iousb646.h: Same. * include/avr/iousb647.h: Same. * include/avr/iousb1286.h: Same. * include/avr/iousb1287.h: Same. 2008-08-06 Eric B. Weddington Fix for bug #23546. * doc/api/faq.dox: Fix typos. 2008-08-01 Eric B. Weddington Add the strdup() function. Partial fix for bug #23677. * libc/string/strdup.c: New file. * libc/string/Files.am: Add new file to build list. * libc/string/Makefile (EXTRA_DIST): Add C sources. 2008-07-30 Eric B. Weddington * bootstrap: Fix ending ']'. 2008-07-30 Eric B. Weddington Fix for bug #23959. * include/compat/deprecated.h: Fix typo in documentation. 2008-07-30 Eric B. Weddington Fix for bug #21621. * bootstrap: Add ability to use autoconf 2.61 and automake 1.10.x. 2008-07-25 Eric B. Weddington * include/avr/iom1284p.h (CLKPCE): Fix bit value to be 7. 2008-07-18 Eric B. Weddington * doc/api/main_page.dox: Update copyright list. 2008-07-18 Eric B. Weddington Fix for sourceforge.net bug #1957780. * include/avr/fuse.h: Add more documentation on how to set the fuses if compiling in C++. 2008-07-18 Eric B. Weddington Fix for sourceforge.net bug #1969436. * include/avr/iom32u4.h (SPM_PAGESIZE): Fix size to be 128. 2008-07-18 Eric B. Weddington Fix for sourceforge.net bug #2012448. * include/avr/iom6450.h (USART0_RX_vect, USART0_UDRE_vect, USART_TX_vect): Add interrupt names as aliases. * include/avr/iom3250.h: Ditto. * include/avr/iom165.h (USART_RX_vect, USART_UDRE_vect, USART_TX_vect): Add interrupt names as aliases. * include/avr/iom165p.h: Ditto. 2008-07-18 Eric B. Weddington Fix for sourceforge.net bug #2010688. * include/avr/iotn48.h (WCOL, SPIF): Fix values of bit definitions for SPSR. Fix bit definitions for MCUCR, SPMCSR, PRR, PCMSK3, PCMSK1. * include/avr/iotn88.h: Add assembler guard for ADC definition. Define ADCW. 2008-07-18 Eric B. Weddington Fix for sourceforge.net bug #2016128. * include/avr/iom32m1.h (CAN_TOVF_vect): Add missing underscore in definition. * include/avr/iom32c1.h (OCR1A): Fix address to be 0x88. 2008-07-18 Eric B. Weddington * include/avr/iotn13a.h (PRR): Change address of PRR register to 0x25. 2008-07-17 Eric B. Weddington Fix for bug #23850. * include/avr/iom8.h (MCUSR): Defined as an alias for MCUCSR. 2008-07-17 Eric B. Weddington Fix for sourceforge.net bug #2018957. * include/avr/iom1284p.h (SPM_PAGESIZE): Fix value to 256. 2008-07-17 Eric B. Weddington Fix for bug #23871. * include/avr/power.h: Enable clock_prescale_set() macro for ATmega32U4 and ATmega32C1. * NEWS: Add to fixed bug list. 2008-07-14 Joerg Wunsch * doc/api/faq.dox (faq_regbind): Fix a typo. 2008-06-25 Eric B. Weddington * include/avr/iotn13a.h: Fix idempotent guard. 2008-06-25 Eric B. Weddington * configure.ac: Add support for ATtiny13A. * devtools/gen-avr-lib-tree.sh: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/power.h: Ditto. * include/avr/sleep.h: Ditto. * include/avr/iotn13a.h: Add new file. * NEWS: Add news item. 2008-06-18 Eric B. Weddington Fix for bug #23554. * include/avr/iom32u4.h: Fix bit name definitions. 2008-06-18 Eric B. Weddington Fix for bug #23261. * include/avr/power.h: Add power_all_enable() and power_all_disable for AT90USB82 and AT90USB162. 2008-06-18 Eric B. Weddington * include/avr/iom48.h: Add fuse, and signature information. * include/avr/io1200.h: Add fuse, lockbit, and signature information. * include/avr/iom103.h: Ditto. * include/avr/io8535.h: Ditto. * include/avr/io8515.h: Ditto. * include/avr/io4434.h: Ditto. * include/avr/io4433.h: Ditto. * include/avr/io4414.h: Ditto. * include/avr/io2343.h: Ditto. * include/avr/io2323.h: Ditto. * include/avr/io2313.h: Ditto. * include/avr/io86r401.h: Ditto. 2008-06-11 Eric B. Weddington * include/avr/iom32u4.h: Fix bit names for registers OCR0A and CLKPR. 2008-06-11 Eric B. Weddington * include/avr/iom32u4.h: Fix register misnaming from DDIR2 to DIDR2. 2008-05-12 Eric B. Weddington * include/avr/iox64a1.h (SPM_PAGESIZE): Change value to 512. * include/avr/iox128a1.h (SPM_PAGESIZE): Ditto. 2008-05-07 Eric B. Weddington Fix for bug #23166. * include/avr/boot.h: Define __SPM_ENABLE as SPMEN or SELFPRGEN, depending on whether device has that bit definition. Use __SPM_ENABLE in all macros. * NEWS: Add to fixed bug list. 2008-05-04 Eric B. Weddington * include/avr/iousbxx6_7.h: Conditionally define RAMPZ only if device is AT90USB1286 or AT90USB1287 (> 64K Flash). 2008-05-02 Dmitry Xmelkov * tests/simulate/runtest.sh: Add ASM files to operate. * tests/simulate/avr/sfr-1.c: New file. * tests/simulate/avr/sfr-2.c: New file. * tests/simulate/avr/sfr-3.c: New file. * tests/simulate/avr/sfrasm-1.S: New file. * tests/simulate/avr/sfrasm-2.S: New file. * tests/simulate/avr/sfrasm-3.S: New file. 2008-05-01 Eric B. Weddington * include/avr/iox128a1.h: Conditionally compile flattened register names for use in assembler only. * include/avr/iox64a1.h: Ditto. 2008-04-29 Eric B. Weddington * include/avr/fuse.h: Fix bug with #ifndef lines. 2008-04-29 Eric B. Weddington * include/avr/iox128a1.h: New definitions to match the latest rev of the chip. * include/avr/iox64a1.h: Ditto. 2008-04-29 Eric B. Weddington * include/avr/lock.h: Protect the LOCKMEM and LOCKBITS macros from being redefined. Change the documentation accordingly. * include/avr/fuse.h: Protect the FUSEMEM and FUSES macros from being redefined. Change the documentation accordingly. 2008-04-28 Eric B. Weddington * include/avr/sfr_defs.h: Define __SFR_OFFSET value depending on whether an XMEGA device is being used. Use __SFR_OFFSET in _SFR_IO8, _SFR_IO16, _SFR_IO_ADDR, _SFR_IO_REG_P macros. 2008-04-28 Eric B. Weddington Fix for bug #23004. * include/avr/wdt.h: Fix Doxygen comment. * NEWS: Add to fixed bug list. 2008-04-28 Eric B. Weddington * include/avr/iotn48.h: Fix and protect ADC definition, add ADCW definition. * include/avr/iom1284p.h: Add ADCW definition. Protect ADC definition. * include/avr/iom328p.h: Ditto. * include/avr/iom168p.h: Ditto. * include/avr/iom48p.h: Ditto. * include/avr/iom32m1.h: Ditto. * include/avr/iom32c1.h: Ditto. * include/avr/io90pwm3b.h: Ditto. * include/avr/io90pwm2b.h: Ditto. * include/avr/iotn167.h: Ditto. 2008-04-28 Eric B. Weddington * include/avr/iom32u4.h: Remove bit definitions for UBRR1L and UBRR1H, per Sylvain Guyon, Atmel. 2008-04-26 Anatoly Sokolov * AvrCommon.am: Remove. * AvrCommonLibC.am: Remove. 2008-04-24 Eric B. Weddington Fix for bug #23032. * include/avr/iomxx4.h: Add missing PORTxn bit definitions. * NEWS: Add to bug list. 2008-04-24 Eric B. Weddington * include/avr/io90pwm2b.h (FUSE_CKLDIV8): Rename to FUSE_CKDIV8. * include/avr/io90pwm3b.h: Ditto. * include/avr/iotn167.h (BIN): Fix the value of BIN to 7 for the ADCSRB register. * include/avr/iom88p.h: Add ADCW definition and guard ADC for assembler. 2008-04-10 Eric B. Weddington * include/math.h: Change functions from 'extern inline' to 'static inline'. This works around a linker problem with including this header and using -std=[gnu99,c99] (it would give 'multiple definition' errors). 2008-04-09 Dmitry Xmelkov * include/avr/eeprom.h: Restore 'extern "C"' envelope. It was lost in 2005, with Avr-libc-1.2.6. 2008-04-08 Eric B. Weddington Fix for bug #22877: * include/avr/iox128a1.h: Fix fuse information. * include/avr/iox64a1.h: Ditto. * NEWS: Add to fixed bug list. 2008-04-07 Eric B. Weddington * include/avr/iom328p.h: Fix SPM_PAGESIZE. * include/avr/iom88p.h: Ditto. * include/avr/iom48p.h: Ditto. 2008-04-07 Eric B. Weddington Fix for bug #22870. * include/avr/wdt.h: Add support for ATmega164P, ATmega324P, ATmega644P. Rearrange condition list to alphabetical order. * NEWS: Add to fixed bug list. 2008-04-05 Dmitry Xmelkov * tests/simulate/runtest.sh: Add support of .eeprom section. Add check of simulavr's runtime errors. * tests/simulate/regression/20080405-eeprom.c: New file. 2008-04-04 Eric B. Weddington Fix for bug #22834. * include/iomxx4.h: Add BOD and BODSE bit definitions. * NEWS: Add to fixed bug list. 2008-04-04 Dmitry Xmelkov Fix for bug #22828. * include/avr/eeprom.h: Restore old args order of eeprom_write_block() function: place source address to left. This revertion at Marth 2008 was an accidental error. * tests/simulate/avr/eeprom-1.c: Ditto. * tests/simulate/regression/bug-22828.c: New file. * NEWS: Add to fixed bug list. 2008-04-03 Dmitry Xmelkov * tests/simulate/regression/bug-22800.c: New file. 2008-04-01 Eric B. Weddington * include/avr/iom32u4.h: Add UEBCX 16-bit register. This is not defined as per the datasheet or XML file. However, in talking with the USB team, the contents of the registers are supposed to be read-only and static. Because of this it makes sense to add this as a convenience to the end-user as long the user realizes that the read is not done with a temporary 8-bit register. 2008-03-31 Eric B. Weddington * include/avr/iom32u4.h: Add alias register definition TC4H, per Atmel. 2008-03-30 Eric B. Weddington Fix for bug #22785. * include/avr/sleep.h: Add support for ATmega644P, ATmega1284P, ATmega32HVB, ATtiny88, ATmega48P, ATmega88P, ATmega168P, ATmega328P, AT90PWM2B, AT90PWM3B, ATtiny48, ATtiny43U, AT90PWM216, AT90PWM316. * NEWS: Add to fixed bug list. 2008-03-29 Dmitry Xmelkov * libm/fplib/frexp.S: Avoid indirect write to R0,R1 with XMEGA. * tests/simulate/runtest.sh: Remove avr-gcc path and version output (With Eric's agree). Roll too line source line. 2008-03-28 Eric B. Weddington * eeprom.h: Re-add the eeprom_busy_wait macro that was accidentally removed. 2008-03-26 Eric B. Weddington * include/avr/iox128a1.h: Fix constants, add fuse, lockbit information. * include/avr/iox64a1.h: Ditto. * include/avr/fuse.h: Add documentation about fuse default value macros. * include/avr/lock.h: Add new lockbit groups and values for XMEGA. 2008-03-25 Eric B. Weddington * configure.ac: Add support for ATtiny167. * devtools/gen-avr-lib-tree.sh: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/power.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/sleep.h: Ditto. * include/avr/iotn167.h: New file. * NEWS: Add new device to list. * doc/api/main_page.dox: Add xmega devices to documentation. * doc/api/using-tools.dox: Ditto. * include/avr/power.h: Fix macro for ATmega32M1, ATmega32C1. * include/avr/sleep.h: Reformat some #ifdefs. 2008-03-24 Eric B. Weddington * tests/simulate/runtest.sh: Moving failed testcases: Replace -T with -f, replace dot with underscore. 2008-03-24 Eric B. Weddington * tests/simulate/runtest.sh: Fix moving failed testcases. Add printing of location and version of avr-gcc used for tests. 2008-03-24 Eric B. Weddington * configure.ac: Add support for XMEGA, ATxmega128A1, ATxmega64A1. * crt1/gcrt1.S: Ditto. * devtools/gen-avr-lib-tree.sh: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/common.h: Ditto. * include/avr/io.h: Ditto. * libc/stdlib/stdlib_private.h: Ditto. * include/avr/power.h: Ditto. * include/avr/sleep.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/iox128a1.h: New file. * include/avr/iox64a1.h: New file. * NEWS: Add news. 2008-03-24 Dmitry Xmelkov Optimize setjmp() in space. Use __AVR_3_BYTE_PC__ macro. * include/setjmp.h: Reduce size of jmp_buf by 2/1 bytes. * libc/stdlib/setjmp.S: Reduce size of jmp_buf by 2/1 bytes. Rewrite the setjmp() to save flash. Use __AVR_3_BYTE_PC__ to determine the size of return address (vs EIND register presence). Add common assembler pseudos: .type, .size . * tests/simulate/regression/20080323-jmpbuf.c: New file. * tests/simulate/stdlib/setjmp-1.S: New file. * tests/simulate/stdlib/setjmp-2.S: New file. * tests/simulate/stdlib/setjmp-3.S: New file. * tests/simulate/stdlib/setjmp-4.S: New file. * tests/simulate/stdlib/setjmp-5.S: New file. * NEWS: Add setjmp() to optimize list. 2008-03-22 Eric B. Weddington * configure.ac: Add support for ATmega32U4. * devtools/gen-avr-lib-tree.sh: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/power.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/sleep.h: Reformat doxygen comment. * include/avr/iom32u4.h: New file. * NEWS: Add to new devices list. 2008-03-22 Dmitry Xmelkov Add __unordsf2() function. GCC 4.3.0 uses it. * libm/fplib/unordsf2.S: New file. * libm/fplib/fp_cmp.S: Split to 3 separate files. * libm/fplib/cmpsf2.S: New file. It was a part of 'fp_cmp.S'. * libm/fplib/gesf2.S: (Ditto.) * libm/fplib/Files.am: Add new source files. * tests/simulate/fplib/unord-01.c: New file. * tests/simulate/fplib/unord-02.c: New file. * tests/simulate/fplib/unord-03.c: New file. * tests/simulate/regression/20080322-isinf.c: New file. 2008-03-21 Eric B. Weddington * include/avr/iomxx4.h: Add missing definitions to finish SF bug #1883630. 2008-03-20 Eric B. Weddington * include/avr/wdt.h: Change back to list of devices to fix bug #22276. 2008-03-19 Eric B. Weddington Fix for bug #3485. * doc/api/faq.dox: Add entry about linking in the math library for floating point math operations. 2008-03-19 Joerg Wunsch Make the test suite print messages for an ATmega128 target. * tests/simulate/runtest.sh: Add -k option to keep the simulavr core files upon encountering an error. * tests/simulate/readcore.py: Script to interpret the simulavr coredumps: prints exit code, and message from XRAM address 0x2000 if present. * tests/simulate/math/frexp-01.c: Make PRINTFLN print the message into external RAM at address 0x2000 when compiling for an ATmega128 target. * tests/simulate/math/isinf-01.c: (Ditto.) * tests/simulate/math/lrint-01.c: (Ditto.) * tests/simulate/math/lround-01.c: (Ditto.) * tests/simulate/math/signbit-01.c: (Ditto.) * tests/simulate/pmstring/memmem_P.c: (Ditto.) * tests/simulate/pmstring/memrchr_P.c: (Ditto.) * tests/simulate/pmstring/strcasestr_P.c: (Ditto.) * tests/simulate/pmstring/strchrnul_P.c: (Ditto.) * tests/simulate/pmstring/strsep_P.c: (Ditto.) * tests/simulate/printf/snprintf_all.c: (Ditto.) * tests/simulate/printf/sprintf_min-1.c: (Ditto.) * tests/simulate/printf/sprintf_min-2.c: (Ditto.) * tests/simulate/printf/sprintf_min-3.c: (Ditto.) * tests/simulate/printf/sprintf_min-4.c: (Ditto.) * tests/simulate/printf/sprintf_min-5.c: (Ditto.) * tests/simulate/printf/sprintf_min-inv.c: (Ditto.) * tests/simulate/printf/sprintf_std-int.c: (Ditto.) * tests/simulate/printf/sprintf_std-inv.c: (Ditto.) * tests/simulate/printf/vsnprintf_all.c: (Ditto.) * tests/simulate/scanf/scanf-nul.c: (Ditto.) * tests/simulate/scanf/scanf_brk-nul.c: (Ditto.) * tests/simulate/scanf/scanf_flt-nul.c: (Ditto.) * tests/simulate/scanf/sscanf-1.c: (Ditto.) * tests/simulate/scanf/sscanf-2.c: (Ditto.) * tests/simulate/scanf/sscanf-c1.c: (Ditto.) * tests/simulate/scanf/sscanf-c2.c: (Ditto.) * tests/simulate/scanf/sscanf-d1.c: (Ditto.) * tests/simulate/scanf/sscanf-d2.c: (Ditto.) * tests/simulate/scanf/sscanf-eof.c: (Ditto.) * tests/simulate/scanf/sscanf-eon.c: (Ditto.) * tests/simulate/scanf/sscanf-h.c: (Ditto.) * tests/simulate/scanf/sscanf-hh.c: (Ditto.) * tests/simulate/scanf/sscanf-i.c: (Ditto.) * tests/simulate/scanf/sscanf-l.c: (Ditto.) * tests/simulate/scanf/sscanf-o1.c: (Ditto.) * tests/simulate/scanf/sscanf-o2.c: (Ditto.) * tests/simulate/scanf/sscanf-s1.c: (Ditto.) * tests/simulate/scanf/sscanf-s2.c: (Ditto.) * tests/simulate/scanf/sscanf-x1.c: (Ditto.) * tests/simulate/scanf/sscanf-x2.c: (Ditto.) * tests/simulate/scanf/sscanf-x3.c: (Ditto.) * tests/simulate/scanf/sscanf_brk-1.c: (Ditto.) * tests/simulate/scanf/sscanf_brk-2.c: (Ditto.) * tests/simulate/scanf/sscanf_brk-3.c: (Ditto.) * tests/simulate/scanf/sscanf_brk-4.c: (Ditto.) * tests/simulate/scanf/sscanf_flt-f1.c: (Ditto.) * tests/simulate/scanf/sscanf_flt-f2.c: (Ditto.) * tests/simulate/scanf/sscanf_flt-f3.c: (Ditto.) * tests/simulate/scanf/sscanf_flt-fnn.c: (Ditto.) * tests/simulate/scanf/sscanf_flt-fw.c: (Ditto.) * tests/simulate/stdlib/isalnum-1.c: (Ditto.) * tests/simulate/stdlib/isalpha-1.c: (Ditto.) * tests/simulate/stdlib/isascii-1.c: (Ditto.) * tests/simulate/stdlib/isblank-1.c: (Ditto.) * tests/simulate/stdlib/iscntrl-1.c: (Ditto.) * tests/simulate/stdlib/isdigit-1.c: (Ditto.) * tests/simulate/stdlib/isgraph-1.c: (Ditto.) * tests/simulate/stdlib/islower-1.c: (Ditto.) * tests/simulate/stdlib/isprint-1.c: (Ditto.) * tests/simulate/stdlib/ispunct-1.c: (Ditto.) * tests/simulate/stdlib/isspace-1.c: (Ditto.) * tests/simulate/stdlib/isupper-1.c: (Ditto.) * tests/simulate/stdlib/isxdigit-1.c: (Ditto.) * tests/simulate/stdlib/tolower-1.c: (Ditto.) * tests/simulate/stdlib/toupper-1.c: (Ditto.) * tests/simulate/string/memmem.c: (Ditto.) * tests/simulate/string/memrchr.c: (Ditto.) * tests/simulate/string/strcasestr.c: (Ditto.) * tests/simulate/string/strchrnul.c: (Ditto.) * tests/simulate/string/strsep.c: (Ditto.) 2008-03-19 Eric B. Weddington Fix for bug SF #1883630. * include/avr/iom48p.h: Add missing bit name alias definitions. * include/avr/iom88p.h: Ditto. * include/avr/iom168p.h: Ditto. * include/avr/iom328p.h: Ditto. 2008-03-19 Eric B. Weddington Fix for bugs #22666, SF #1913681, SF #1910885. * include/avr/io90pwm3b.h: Add missing definitions, fix definitions. * include/avr/io90pwm2b.h: Ditto. 2008-03-18 Dmitry Xmelkov * tests/simulate/regression/bug-22593.c: New file. 2008-03-17 Joerg Wunsch * devtools/gen-avr-lib-tree.sh: replace \\\\\n by just a space, it's causing way less troubles. 2008-03-17 Joerg Wunsch * doc/examples/demo/iocompat.h: Add support for ATmega1284P, ATmega2560, and ATmega2561. * doc/examples/demo/Makefile: (Ditto.) 2008-03-17 Joerg Wunsch * tests/simulate/runtest.sh: Turn the bash-like arithmetics into Posix ones, so it runs correctly on FreeBSD's /bin/sh. 2008-03-17 Eric B. Weddington Fix for bug #22390. * doc/api/faq.dox: Fix statement about function pointers. 2008-03-17 Eric B. Weddington Fix for bug #22119. * doc/api/faq.dox: Fix statement about returned values. 2008-03-17 Eric B. Weddington Fix for bug #19494. * doc/api/sfr.dox: Rewrite to remove deprecated code examples. 2008-03-17 Eric B. Weddington Fix for bug #22276. * include/avr/wdt.h: Check location of watchdog register and use that to determine which code sequence to define. 2008-03-17 Eric B. Weddington Fix for bugs #22447, #22387. * include/avr/iom88p.h: Fix definitions or add definitions. * include/avr/iom168p.h: Ditto. * include/avr/iom328p.h: Ditto. * include/avr/iom48p.h: Ditto. 2008-03-17 Eric B. Weddington Fix for bug #22642. * include/avr/power.h: Add support for AT90USB82 and AT90USB162. 2008-03-17 Eric B. Weddington Fix for bug #22643. * include/math.h: Rename occurrences of 'asm' needs to to '__asm__'. 2008-03-16 Eric B. Weddington Patch #6355, by Stas Sergeev * include/avr/boot.h: add __extension__ to boot.h. 2008-03-16 Eric B. Weddington Fix for bugs #22568, #22548. * include/avr/iom328p.h: Add missing definitions. * NEWS: Update fixed bug list. 2008-03-16 Dmitry Xmelkov * libc/stdlib/ftoa_engine.S: Add CPP scopes to exclude the parsing of asm by DOXYGEN. * libc/stdlib/setjmp.S: Ditto. * libc/stdlib/ultoa_invert.S: Ditto. * libc/stdlib/atof.S: Add DOXYGEN doc and exclude other asm from DOXYGEN parsing. * include/stdlib.h: Remove DOXYGEN of atof(). 2008-03-14 Eric B. Weddington * configure.ac: Add support for ATmega32C1. * devtools/gen-avr-lib-tree.sh: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * include/avr/power.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/iom32c1.h: New file. * NEWS: Add new device to list. 2008-03-12 Anatoly Sokolov * doc/TODO: Update. 2008-03-12 Anatoly Sokolov * crt1/gcrt1.S (__do_copy_data): Don't use for GCC 4.4 and up. 2008-03-11 Anatoly Sokolov * devtools/Makefile.am (EXTRA_DIST): Add 'Architecture.am', 'Avr.am', 'Device.am' and 'Lib.am'. 2008-03-10 Eric B. Weddington * configure.ac: Add support for ATmega32M1 device. * devtools/gen-avr-lib-tree.sh: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * include/avr/power.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/iom32m1.h: New file. * NEWS: Add new device to list. 2008-03-09 Anatoly Sokolov * devtools/gen-avr-lib-tree.sh: Use 'Avr.am', 'Lib.am' and 'Architecture.am' as template for 'avr/Makefile.am', 'avr/lib/Makefile.am' and 'avr/lib/Architecture/Makefile.am'. * devtools/Architecture.am: New file. * devtools/Avr.am: New file. * devtools/Lib.am: New file. 2008-03-09 Dmitry Xmelkov * include/avr/eeprom.h: eeprom_write_byte(): add EECR clearning to force erase_and_write programming mode. Document this and add note about necessarity SELFPRGEN polling. 2008-03-08 Eric B. Weddington Fix for bug #22493. * include/avr/iom1284p.h: Fix typo. 2008-03-03 Anatoly Sokolov * devtools/gen-avr-lib-tree.sh: Use devtools/Device.am as template for dev/Makefile.am. * devtools/Device.am: New file. 2008-03-02 Dmitry Xmelkov * include/avr/eeprom.h: Change cast operation to avoid warning with '-Wsystem-headers' option. * tests/simulate/avr/eeprom-1.c: Add comment about avr-gcc 4.2.2 bug. Note, avr-gcc 4.2.3 is correct. * tests/simulate/regression/bug-31644.c: New file. 2008-03-01 Dmitry Xmelkov New variant of EEPROM functions: inline byte procedures and library multibyte envelopes. * include/avr/eeprom.h: Rewrite on the base of project by Eric B. Weddington. * libc/misc/eeprom.S: Remove file. * libc/misc/ee_rb.S: Remove file. * libc/misc/ee_rblk.S: Remove file. * libc/misc/ee_rw.S: Remove file. * libc/misc/ee_wb.S: Remove file. * libc/misc/ee_wblk.S: Remove file. * libc/misc/ee_ww.S: Remove file. * libc/misc/eerd_block.c: New file. * libc/misc/eerd_dword.c: New file. * libc/misc/eerd_word.c: New file. * libc/misc/eewr_block.c: New file. * libc/misc/eewr_dword.c: New file. * libc/misc/eewr_word.c: New file. * libc/misc/Files.am: Remove old sources, add new. * libc/misc/Makefile.am: Include $(misc_a_c_sources) to EXTRA_DIST. * libc/misc/Rules.am: Remove rules to build chip-specific objects. * tests/simulate/avr: New directory (for AVR-specific functions). * tests/simulate/avr/eeprom-1.c: New file. * tests/simulate/runtest.sh: Add 'avr/*.c' to default test list. Add $MCU_LIST_FULL for AVR-specific testing. * NEWS: Notes about EEPROM changes and fixed bug. 2008-02-24 Dmitry Xmelkov * doc/api/bench.dox: Change remark about GCC versions: replace scanf() example to dtostre(). * doc/api/bench-libc.dox: Update the results. Give two sizes: with and without prologue/epilogue modules. Add sscanf() with '%[' conversion. 2008-02-23 Dmitry Xmelkov Optimize tests in space to satisfy the space-worse 4.2.2(3) GCC. Split in cases where optimization is not possible. * tests/simulate/scanf/sscanf-d1.c: Optimize in space. * tests/simulate/scanf/sscanf-hh.c: Ditto. * tests/simulate/scanf/sscanf-o1.c: Ditto. * tests/simulate/scanf/sscanf-s1.c: Ditto. * tests/simulate/scanf/sscanf-x1.c: Ditto. * tests/simulate/scanf/sscanf-x2.c: Ditto. * tests/simulate/scanf/sscanf_brk-1.c: Ditto. * tests/simulate/scanf/sscanf_brk-2.c: Ditto. * tests/simulate/scanf/sscanf_flt-fnn.c: Ditto. * tests/simulate/scanf/sscanf-c.c: Split to 2 tests and remove. * tests/simulate/scanf/sscanf-c1.c: New file: part of above sscanf-c.c * tests/simulate/scanf/sscanf-c2.c: New file: part of above sscanf-c.c * tests/simulate/scanf/sscanf-1.c: Move a part to new sscanf-2.c * tests/simulate/scanf/sscanf-2.c: New file. * tests/simulate/scanf/sscanf-x3.c: New file. * tests/simulate/scanf/sscanf_brk-3.c: New file. * tests/simulate/scanf/sscanf_brk-4.c: New file. 2008-02-21 Eric B. Weddington Fix for bug #22377. Wrong XRAMEND for some recent ioXXX.h header files. * include/avr/io90pwm216.h: Fix XRAMEND definition. * include/avr/io90pwm2b.h: Ditto. * include/avr/io90pwm316.h: Ditto. * include/avr/io90pwm3b.h: Ditto. * include/avr/iom1284p.h: Ditto. * include/avr/iom168p.h: Ditto. * include/avr/iom328p.h: Ditto. * include/avr/iom32hvb.h: Ditto. * include/avr/iom48p.h: Ditto. * include/avr/iom88p.h: Ditto. * include/avr/iotn48.h: Ditto. * include/avr/iotn88.h: Ditto. 2008-02-21 Dmitry Xmelkov * libc/stdlib/strtod.c: Optimize, tune for new GCC (4.1 - 4.3). Add DOXYGEN comment for strtod(). * include/stdlib.h: Remove DOXYGEN for strtod(). * NEWS: Add to optimized function list. * test/simulate/stdlib/strtod-3.c: Add a few test cases. 2008-02-18 Dmitry Xmelkov Function vfscanf() is rewriten (see NEWS for details). * libc/stdio/vfscanf.c: Rewriten. * include/stdio.h: Remove DOXYGEN for vfscanf(): it is in source now. * NEWS: Notes about vfscanf() changes and fixed bugs. * tests/simulate/runtest.sh: Add 'scanf' file name interpretation. * tests/simulate/regression/bug-19079.c: New file. * tests/simulate/regression/bug-21905-scanf_flt.c: New file. * tests/simulate/regression/bug-21906-scanf_flt.c: New file. * tests/simulate/scanf: New directory. * tests/simulate/scanf/scanf-nul.c: New file. * tests/simulate/scanf/scanf_brk-nul.c: New file. * tests/simulate/scanf/scanf_flt-nul.c: New file. * tests/simulate/scanf/sscanf-1.c: New file. * tests/simulate/scanf/sscanf_brk-1.c: New file. * tests/simulate/scanf/sscanf_brk-2.c: New file. * tests/simulate/scanf/sscanf-c.c: New file. * tests/simulate/scanf/sscanf-d1.c: New file. * tests/simulate/scanf/sscanf-d2.c: New file. * tests/simulate/scanf/sscanf-eof.c: New file. * tests/simulate/scanf/sscanf-eon.c: New file. * tests/simulate/scanf/sscanf_flt-f1.c: New file. * tests/simulate/scanf/sscanf_flt-f2.c: New file. * tests/simulate/scanf/sscanf_flt-f3.c: New file. * tests/simulate/scanf/sscanf_flt-fnn.c: New file. * tests/simulate/scanf/sscanf_flt-fw.c: New file. * tests/simulate/scanf/sscanf-h.c: New file. * tests/simulate/scanf/sscanf-hh.c: New file. * tests/simulate/scanf/sscanf-i.c: New file. * tests/simulate/scanf/sscanf-l.c: New file. * tests/simulate/scanf/sscanf-o1.c: New file. * tests/simulate/scanf/sscanf-o2.c: New file. * tests/simulate/scanf/sscanf-s1.c: New file. * tests/simulate/scanf/sscanf-s2.c: New file. * tests/simulate/scanf/sscanf-x1.c: New file. * tests/simulate/scanf/sscanf-x2.c: New file. 2008-02-12 Eric B. Weddington Fix for Atmel bug #7159. * include/avr/iotn48.h: Fix address of TCCR0A and associated bit names. 2008-02-11 Eric B. Weddington Fix for bug #22016: Typo in iotn2313.h: SIG_OUTPUT_COPMARE0A * include/avr/iotn2313.h: Fix typo in SIG_OUTPUT_COPMARE0A. 2008-01-28 Joerg Wunsch bug #22153: setjmp.o is wrong in libc.a (1.6.1) for avr's with SPH * include/avr/common.h: Enable default SPL/SPH definitions not when __COMPILING_AVR_LIBC__ is active; interestingly, the comment on the #endif had already been correct but the condition hadn't. While being here, protect default definition for EIND on avr6 architectures to just avr-libc compilations (otherwise, it's supposed to come from the real device header). 2008-01-28 Joerg Wunsch * devtools/gen-avr-lib-tree.sh (AVR31_DEV_INFO): remove trailing semicolon in last entry. It caused a blank line following a backslash in lib/avr/avr31/Makefile.am, which made automake issue a warning. 2008-01-24 Anatoly Sokolov * doc/api/using-tools.dox: Document '__AVR_HAVE_JMP_CALL__' macro. Mark '__AVR_MEGA__' and '__AVR_ENHANCED__' as obsolete. Remove '__AVR_HAVE_RAMPZ__', '__AVR_HAVE_ELPM__' and '__AVR_HAVE_ELPMX__' macros from 'avr5' architecture and add to 'avr51'. 2008-01-23 Anatoly Sokolov * configure.ac: Add 'avr31' and 'avr51' architectures. * devtools/gen-avr-lib-tree.sh (AVR_ARH_INFO): (Ditto.). (AVR31_DEV_INFO, AVR51_DEV_INFO): New. * doc/api/using-tools.dox: Document 'avr31' and 'avr51'. 2008-01-14 Eric B. Weddington * include/avr/io90pwm2b.h: Add missing EEAR word register. * include/avr/io90pwm3b.h: Ditto. 2008-01-13 Dmitry Xmelkov Fix for bug #21995: pgm_read_xxxx() does not use enhanced LPM instruction. * include/avr/common.h: Restore the __AVR_HAVE_LPMX__ (also __AVR_HAVE_MOVW__, __AVR_HAVE_MUL__) definitions (in case that they are not defined by the compiler). * tests/simulate/regression/bug-21995.c: New file. * NEWS: Add to fixed bug list. 2008-01-09 Eric B. Weddington Fix for bug #21986. * include/avr/iotn13.h: Fix bit definition. 2008-01-07 Anatoly Sokolov * doc/api/using-tools.dox: Fix GCC version for 'avr35' architecture. 2008-01-06 Eric B. Weddington * include/avr/io90pwm1.h: Fix default fuse definitions. * include/avr/io90pwm216.h: Ditto. * include/avr/io90pwm2b.h: Ditto. * include/avr/io90pwm316.h: Ditto. * include/avr/io90pwm3b.h: Ditto. * include/avr/io90pwmx.h: Ditto. * include/avr/iocan128.h: Ditto. * include/avr/iocan32.h: Ditto. * include/avr/iocan64.h: Ditto. * include/avr/iom128.h: Ditto. * include/avr/iom1280.h: Ditto. * include/avr/iom1281.h: Ditto. * include/avr/iom1284p.h: Ditto. * include/avr/iom16.h: Ditto. * include/avr/iom161.h: Ditto. * include/avr/iom162.h: Ditto. * include/avr/iom163.h: Ditto. * include/avr/iom164.h: Ditto. * include/avr/iom165.h: Ditto. * include/avr/iom165p.h: Ditto. * include/avr/iom169.h: Ditto. * include/avr/iom169p.h: Ditto. * include/avr/iom16hva.h: Ditto. * include/avr/iom2560.h: Ditto. * include/avr/iom2561.h: Ditto. * include/avr/iom32.h: Ditto. * include/avr/iom323.h: Ditto. * include/avr/iom324.h: Ditto. * include/avr/iom325.h: Ditto. * include/avr/iom3250.h: Ditto. * include/avr/iom329.h: Ditto. * include/avr/iom3290.h: Ditto. * include/avr/iom32hvb.h: Ditto. * include/avr/iom406.h: Ditto. * include/avr/iom48p.h: Ditto. * include/avr/iom64.h: Ditto. * include/avr/iom640.h: Ditto. * include/avr/iom644.h: Ditto. * include/avr/iom645.h: Ditto. * include/avr/iom6450.h: Ditto. * include/avr/iom649.h: Ditto. * include/avr/iom6490.h: Ditto. * include/avr/iom8.h: Ditto. * include/avr/iom8515.h: Ditto. * include/avr/iom8535.h: Ditto. * include/avr/iom8hva.h: Ditto. * include/avr/iotn11.h: Ditto. * include/avr/iotn12.h: Ditto. * include/avr/iotn13.h: Ditto. * include/avr/iotn15.h: Ditto. * include/avr/iotn22.h: Ditto. * include/avr/iotn2313.h: Ditto. * include/avr/iotn24.h: Ditto. * include/avr/iotn25.h: Ditto. * include/avr/iotn26.h: Ditto. * include/avr/iotn261.h: Ditto. * include/avr/iotn28.h: Ditto. * include/avr/iotn43u.h: Ditto. * include/avr/iotn44.h: Ditto. * include/avr/iotn45.h: Ditto. * include/avr/iotn461.h: Ditto. * include/avr/iotn48.h: Ditto. * include/avr/iotn84.h: Ditto. * include/avr/iotn85.h: Ditto. * include/avr/iotn861.h: Ditto. * include/avr/iotn88.h: Ditto. * include/avr/iousb1286.h: Ditto. * include/avr/iousb1287.h: Ditto. 2008-01-06 Eric B. Weddington Fix for bug #21931. * include/avr/iom88.h: Fix fuse definitions. * include/avr/iom168.h: Ditto. * include/avr/iom88p.h: Ditto. * include/avr/iom168p.h: Ditto. * include/avr/iom328p.h: Ditto. * NEWS: Add to fixed bug list. 2008-01-06 Eric B. Weddington Fix for bug #21962. * include/avr/io90pwm3b.h: Fix bit definitions. * include/avr/io90pwm316.h: Ditto. * NEWS: Add to fixed bug list. 2008-01-05 Eric B. Weddington * NEWS: Add bug #21869 to fixed list. This was fixed yesterday with the huge change to the fuse definitions. 2008-01-05 Eric B. Weddington Fix for bug #21958. * include/avr/iom48p.h: Fix duplicate definitions. * include/avr/iom88p.h: Ditto. * include/avr/iom168p.h: Ditto. * include/avr/iom328p.h: Ditto. * include/avr/iom1284p.h: Ditto. 2008-01-05 Dmitry Xmelkov Fix GCC version comparison in preprocessing: * include/compat/deprecated.h: Ditto. * include/avr/interrupt.h: Ditto. * libc/stdlib/strtod.c: Ditto. * tests/simulate/regression/bug-21872-1.c: Ditto. * tests/simulate/regression/bug-21872-2.c: Ditto. 2008-01-04 Eric B. Weddington * include/avr/fuse.h: Fix documentation with new fuse definitions. * include/avr/io90pwm1.h: Add prefix to fuse definitions. * include/avr/io90pwm216.h: Ditto. * include/avr/io90pwm2b.h: Ditto. * include/avr/io90pwm316.h: Ditto. * include/avr/io90pwm3b.h: Ditto. * include/avr/io90pwmx.h: Ditto. * include/avr/iocan128.h: Ditto. * include/avr/iocan32.h: Ditto. * include/avr/iocan64.h: Ditto. * include/avr/iom128.h: Ditto. * include/avr/iom1280.h: Ditto. * include/avr/iom1281.h: Ditto. * include/avr/iom1284p.h: Ditto. * include/avr/iom16.h: Ditto. * include/avr/iom161.h: Ditto. * include/avr/iom162.h: Ditto. * include/avr/iom163.h: Ditto. * include/avr/iom164.h: Ditto. * include/avr/iom165.h: Ditto. * include/avr/iom165p.h: Ditto. * include/avr/iom168.h: Ditto. * include/avr/iom168p.h: Ditto. * include/avr/iom169.h: Ditto. * include/avr/iom169p.h: Ditto. * include/avr/iom16hva.h: Ditto. * include/avr/iom2560.h: Ditto. * include/avr/iom2561.h: Ditto. * include/avr/iom32.h: Ditto. * include/avr/iom323.h: Ditto. * include/avr/iom324.h: Ditto. * include/avr/iom325.h: Ditto. * include/avr/iom3250.h: Ditto. * include/avr/iom328p.h: Ditto. * include/avr/iom329.h: Ditto. * include/avr/iom3290.h: Ditto. * include/avr/iom32hvb.h: Ditto. * include/avr/iom406.h: Ditto. * include/avr/iom48p.h: Ditto. * include/avr/iom64.h: Ditto. * include/avr/iom640.h: Ditto. * include/avr/iom644.h: Ditto. * include/avr/iom645.h: Ditto. * include/avr/iom6450.h: Ditto. * include/avr/iom649.h: Ditto. * include/avr/iom6490.h: Ditto. * include/avr/iom8.h: Ditto. * include/avr/iom8515.h: Ditto. * include/avr/iom8535.h: Ditto. * include/avr/iom88.h: Ditto. * include/avr/iom88p.h: Ditto. * include/avr/iom8hva.h: Ditto. * include/avr/iotn11.h: Ditto. * include/avr/iotn12.h: Ditto. * include/avr/iotn13.h: Ditto. * include/avr/iotn15.h: Ditto. * include/avr/iotn22.h: Ditto. * include/avr/iotn2313.h: Ditto. * include/avr/iotn24.h: Ditto. * include/avr/iotn25.h: Ditto. * include/avr/iotn26.h: Ditto. * include/avr/iotn261.h: Ditto. * include/avr/iotn28.h: Ditto. * include/avr/iotn43u.h: Ditto. * include/avr/iotn44.h: Ditto. * include/avr/iotn45.h: Ditto. * include/avr/iotn461.h: Ditto. * include/avr/iotn48.h: Ditto. * include/avr/iotn84.h: Ditto. * include/avr/iotn85.h: Ditto. * include/avr/iotn861.h: Ditto. * include/avr/iotn88.h: Ditto. * include/avr/iousb1286.h: Ditto. * include/avr/iousb1287.h: Ditto. * include/avr/iousb162.h: Ditto. * include/avr/iousb646.h: Ditto. * include/avr/iousb647.h: Ditto. * include/avr/iousb82.h: Ditto. 2008-01-03 Eric B. Weddington * ChangeLog: Rotate ChangeLog. * ChangeLog-2007: New file. * Makefile.am: Add ChangeLog-2007 to distribution list. 2008-01-03 Eric B. Weddington Fix bug #21935. * doc/api/library.dox: Fix typo. For older changes see ChangeLog-2007 avr-libc-1.8.0.orig/ChangeLog-20090000644000000000000000000012746311732702554013231 0ustar 2009-12-29 Eric B. Weddington Fix for WinAVR bug #2913419. * include/avr/iox128a1.h: Replace DACACAINCAL with DACAGAINCAL. * include/avr/iox128a3.h: Same. * include/avr/iox128d3.h: Same. * include/avr/iox16a4.h: Same. * include/avr/iox16d4.h: Same. * include/avr/iox192a3.h: Same. * include/avr/iox256a3.h: Same. * include/avr/iox256a3b.h: Same. * include/avr/iox32a4.h: Same. * include/avr/iox32d4.h: Same. * include/avr/iox64a1.h: Same. * include/avr/iox64a3.h: Same. * include/avr/iox64d3.h: Same. * NEWS: Add to fixed bug list. 2009-12-20 Eric B. Weddington * include/avr/io.h: Fix check for ATmega164A definition. 2009-12-20 Dmitry Xmelkov * include/avr/sleep.h: Fix error in preprocessor expression (||). 2009-12-14 Eric B. Weddington * configure.ac: Fix missing line for atmega168a device support. 2009-12-14 Eric B. Weddington * include/avr/iom16hva2.h: New file. * include/avr/iom16hvb.h: Same. * include/avr/iom169pa.h: Same. * include/avr/iom649p.h: Same. * include/avr/iom64hve.h: Same. 2009-12-03 Eric B. Weddington Add support for new devices: ATmega16HVA2, ATmega16HVB, ATmega48A, ATmega88A, ATmega168A, ATmega328, ATmega164A, ATmega324A, ATmega644A, ATmega165A, ATmega169A, ATmega645A, ATmega6450A, ATmega649A, ATmega6490A, ATmega6490P, ATmega645P, ATmega6450P, ATmega329PA. * configure.ac: Add support for new devices. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/power.h: Same. * include/avr/wdt.h: Same. * include/avr/sleep.h: Same. * include/avr/eeprom.h: Same. * NEWS: Add news item. 2009-11-29 Dmitry Xmelkov Fix some tests to run with host computer. * tests/simulate/progmem.h: Add pgm_read_float() definition. * tests/simulate/math/cos-02.c: Use pgm_read_float() for float value. * tests/simulate/stdlib/strtod-1.c: (Ditto.) * tests/simulate/stdlib/strtod-2.c: (Ditto.) * tests/simulate/other/malloc-01.c: Add conditionals for AVR specific constructions. * tests/simulate/other/realloc-01.c: Add conditionals for AVR specific constructions. Fix CVS ident keyword. * tests/simulate/printf/snprintf_all.c: Exclude snprintf_P() usage if __AVR__ is't defined. Add float aliases for math functions. * include/math.h: Define a set of float function names. Simplify DOXYGEN comments by expanding {ingroup math} region. * libm/fplib/modf.S: Add modff() entry. * tests/simulate/math/all-float.c: New file. 2009-11-18 Eric B. Weddington * include/avr/iotn261a.h: New file. * include/avr/iotn461a.h: Same. * include/avr/iotn861a.h: Same. * include/avr/iom324pa.h: Same. * include/avr/iotn10.h: Same. * include/avr/iotn4.h: Same. * include/avr/iotn5.h: Same. * include/avr/iotn9.h: Same. 2009-11-15 Dmitry Xmelkov Add new function memccpy_P(). * libc/string/memccpy.S: Add code for PROGMEM version. * libc/pmstring/memccpy_P.S: New file. * libc/pmstring/Files.am: Add memccpy_P.S to file list. * include/avr/pgmspace.h: Add memccpy_P(). * tests/simulate/string/memccpy.c: New file. * tests/simulate/pmstring/memccpy_P.c: New file. * NEWS: Add memccpy_P to new funcions list. 2009-11-14 Eric B. Weddington Add support for these devices: ATtiny2313A, ATtiny4313, ATtiny24A, ATtiny44A, ATmega644PA, ATmega88PA, ATmega16A, ATtiny261A, ATtiny861A, ATtiny461A, ATmega64HVE, ATmega169PA, ATmega649P, ATmega324PA. * configure.ac: Add support for new devices. Reorganize AM_CONDITIONAL and AC_CONFIG_FILES lists. * devtools/gen-avr-lib-tree.sh: Same. Reorganize AVR5_DEV_INFO list. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. Reorganize table. * include/avr/power.h: Same. * include/avr/wdt.h: Same. * include/avr/sleep.h: Same. * include/avr/eeprom.h: Same. * NEWS: Add news items for new devices. 2009-11-08 Dmitry Xmelkov Add new functions: strtok_P() and strtok_rP(). * include/avr/pgmspace.h: Add strtok_P(), strtok_rP(). * libc/pmstring/strtok_P.c: New file. * libc/pmstring/strtok_rP.S: New file. * libc/pmstring/Files.am: Add new sources. * libc/pmstring/Makefile.am: Extend EXTRA_DIST list. * tests/simulate/pmstring/strtok_P.c: New file. * NEWS: Add strtok_P, strtok_rP to new function list. * doc/api/doxygen.config.in: Add ATTRIBUTE_CLIB_SECTION to list of predefined macroses. 2009-11-01 Eric B. Weddington * include/avr/iom16a.h: New file. * include/avr/iom88pa.h: Same. * include/avr/iom644pa.h: Same. * include/avr/iotn24a.h: Same. * include/avr/iotn44a.h: Same. * include/avr/iotn2313a.h: Same. * include/avr/iotn4313.h: Same. 2009-11-01 Dmitry Xmelkov * libc/string/strtok_r.S: Rewrite to optimize and remove surplus stack usage. * tests/simulate/strtok.c: New file. * NEWS: Add to optimized functions list. 2009-10-25 Dmitry Xmelkov * libc/string/strlcat.S: Rewrite to reduce size (considerably) and speed up. * libc/pmstring/strlcat_P.S: Ditto. * tests/simulate/string/strlcat.c: New file. * tests/simulate/pmstring/strlcat_P.c: New file. * NEWS: Add to optimized functions list. 2009-10-23 Eric B. Weddington * include/avr/iox256d3.h: Update header file. 2009-10-18 Dmitry Xmelkov * libc/string/strlcpy.S: Optimize: remove surplus size testing, reorder code. * libc/pmstring/strlcpy_P.S: Ditto. * tests/simulate/string/strlcpy.c: New file. * tests/simulate/pmstring/strlcpy_P.c: New file. * NEWS: Add to optimized functions list. 2009-10-11 Dmitry Xmelkov * include/avr/sleep.h: Add 'do ... while (0)' for '{}' block macros. * include/avr/power.h: Ditto. 2009-09-14 Eric B. Weddington Fix for bug #27434. * include/avr/boot.h: Add parentheses around vars in inline assembly macros. (boot_signature_byte_get) Reformat white space, remove unneeded temporary variable. 2009-09-10 Dmitry Xmelkov Apply the patch #6878: eewr_byte.S update for patch #6718 Thanks to Bob Paddock and Simone Zamboni for the patch. * libc/misc/eewr_byte.S: Fix the XMEGA part of code. * NEWS: Add item about patch contributed. 2009-08-17 Anitha Boyapati * include/avr/iox128a1.h: Add '__extension__' to generation of _WORDREGISTER and _DWORDREGISTER macros. Fix for bug #27201 * include/avr/iox128a3.h: Same. * include/avr/iox128d3.h: Same. * include/avr/iox16a4.h: Same. * include/avr/iox16d4.h: Same. * include/avr/iox192a3.h: Same. * include/avr/iox256a3.h: Same. * include/avr/iox256a3b.h: Same. * include/avr/iox32a4.h: Same. * include/avr/iox32d4.h: Same. * include/avr/iox64a1.h: Same. * include/avr/iox64a3.h: Same. 2009-08-15 Anitha Boyapati Fix for WinAVR bug #2812125. * include/avr/power.h: Define clock prescale register for ATmega16U4. 2009-08-07 Eric B. Weddington * xml/avrgcc-header: Add '__extension__' to generation of _WORDREGISTER and _DWORDREGISTER macros in XMEGA header files. This is a partial fix for bug #27201. 2009-08-06 Eric B. Weddington Fix for bug #26840. Thanks to Anitha Boyapati for the patch. * include/avr/iom16m1.h: Add DAOE bit name. * include/avr/iom32c1.h: Same. * include/avr/iom32m1.h: Same. * include/avr/iom64c1.h: Same. * include/avr/iom64m1.h: Same. 2009-08-04 Eric B. Weddington * configure.ac: Add support for ATxmega192D3. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/power.h: Same. * include/avr/wdt.h: Same. * include/avr/sleep.h: Same. * include/avr/eeprom.h: Same. * NEWS: Add news item for new device. 2009-08-02 Eric B. Weddington * include/avr/iox192d3.h: New file. 2009-07-30 Eric B. Weddington * configure.ac: Add support for ATmega8U2, ATmega16U2, and ATmega32U2. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/Makefile.am: Same. Also reorder files in avr_HEADERS. * include/avr/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/power.h: Same. Also fix macro name. * include/avr/wdt.h: Same. * include/avr/sleep.h: Same. * include/avr/eeprom.h: Same. * NEWS: Add news item for new devices. 2009-07-17 Eric B. Weddington * include/avr/iom8u2.h: New file. * include/avr/iom16u2.h: New file. * include/avr/iom32u2.h: New file. 2009-07-15 Joerg Wunsch * doc/api/rel-method.dox: Remember to update the Savannah bug tracker version numbers when releasing. 2009-07-14 Eric B. Weddington Fix for bug #26876. * include/avr/fuse.h: Add check for , so fuse.h isn't included directly. 2009-07-01 Joerg Wunsch * include/avr/iom128rfa1.h: Fix the structured IO register access. 2009-06-28 Dmitry Xmelkov Fix for bug #26809: Some common math constants missing in math.h * include/math.h: Add a set of common math constans. * NEWS: Add item to fixed bug list. 2009-06-27 Dmitry Xmelkov * libc/misc/eerd_block.S: Add 'eepr_hi' definition to fix the XMEGA variant. 2009-06-25 Joerg Wunsch Allow the HD44780 connection in stdiodemo to be spread across more than a single port. * doc/examples/stdiodemo/defines.h: Pin assignments now contain both, a port name as well as a pin number. * doc/examples/stdiodemo/hd44780.c: Implement the new macros to access the port pins. * doc/examples/stdiodemo/hd44780.h: Mention the newly added function hd44780_powerdown() that prepares the port pins to safely power down the HD44780 (externally). * doc/examples/stdiodemo/stdiodemo.dox: Adapt to the changes implemented. 2009-06-25 Joerg Wunsch * devtools/gen-avr-lib-tree.sh: replace Linux options to head(1) and tail(1) by their Posix counterparts for portability. 2009-06-11 Joerg Wunsch * include/avr/iom128rfa1.h: Update. 2009-06-06 Dmitry Xmelkov * include/avr/eeprom.h: Add __EEPUT() and __EEGET() macroses. (They were losted in patch #6718). * NEWS: Add items about bugs fixed. 2009-06-06 Dmitry Xmelkov Apply the patch #6718: Optimize the EEPROM functions. * devtools/Architecture.am: Add AVRLIB_DEVLIST. * devtools/gen-avr-lib-tree.sh: Add a code to replace the <> template into real device names. * include/avr/eeprom.h: Rewrite all function definitions. Add a set of 'update' functions. Add a set of float arg functions. Add a documentation. * libc/misc/eerd_block.c: Remove. * libc/misc/eerd_dword.c: Remove. * libc/misc/eerd_word.c: Remove. * libc/misc/eewr_block.c: Remove. * libc/misc/eewr_dword.c: Remove. * libc/misc/eewr_word.c: Remove. * libc/misc/eedef.h: New file. * libc/misc/eerd_block.S: New file. * libc/misc/eerd_byte.S: New file. * libc/misc/eerd_dword.S: New file. * libc/misc/eerd_word.S: New file. * libc/misc/eeupd_block.S: New file. * libc/misc/eeupd_byte.S: New file. * libc/misc/eeupd_dword.S: New file. * libc/misc/eeupd_word.S: New file. * libc/misc/eewr_block.S: New file. * libc/misc/eewr_byte.S: New file. * libc/misc/eewr_dword.S: New file. * libc/misc/eewr_word.S: New file. * libc/misc/readme_eeprom.txt: New file. * libc/misc/Files.am: Remove EEPROM C sources. Add EEPROM asm sources. Add new files to EXTRA list. * libc/misc/Makefile.am: Add 'eeprom_asm_sources'. * libc/misc/Rules.am: Add code to generate rules for all devices from AVRLIB_DEVLIST (EEPROM objects). * tests/simulate/avr/eeprom-1.c: Rewrite a part of code to avoid the Simulavr bug in case of small SRAM chips. Fix a typo in memory checking. * tests/simulate/avr/eeprom-2.c: New file. * tests/simulate/avr/eeprom-3.c: New file. * NEWS: Rewrite a topic about the EEPROM improvement. Add the optimized functions list. Add the new functions list. Add the note of patch applied. 2009-05-24 Dmitry Xmelkov Fix for bug #23677: new function cbrt() is added. * libm/fplib/cbrt.S: New file. * libm/fplib/Files.am: Add 'cbrt.S' source. * include/math.h: Add cbrt(). * tests/simulate/math/cbrt-01.c: New file. * tests/simulate/math/cbrt-02.c: New file. * tests/simulate/math/cbrt-03.c: New file. * tests/simulate/math/cbrt-500.c: New file. * tests/simulate/math/xxx-nan.c: Add cbrt(). * doc/api/bench-libm.dox: Add cbrt(). * NEWS: Add item to fixed bug list and new function cbrt(). 2009-05-20 Joerg Wunsch * include/avr/iom128rfa1.h: Fix some typos, mainly in comments. 2009-05-16 Dmitry Xmelkov * libc/stdlib/setjmp.S: Remove the EIJMP instruction usage, as the EIND changing is forbidden by AVR-GCC's API. * NEWS: add item to fixed bug list (no-id). 2009-04-28 Eric B. Weddington Fix for bug AVR Tools #9724. * include/avr/iotn13a.h: Remove PRSPI. Change value of PRTIM0. * include/avr/power.h: Add macros for ATtiny13A. * NEWS: Add item to fixed bug list. 2009-04-25 Eric B. Weddington Fix for bug #25929. Thanks to Bob Paddock for a patch. * include/avr/boot.h (__BOOT_LOCK_BITS_SET): Provide alternate definition if RFLB is defined instead of BLBSET. NEWS: Add item to fixed bug list. 2009-04-25 Eric B. Weddington Fix for bug #26284. Thanks to Brad Schick for the patch. * include/avr/boot.h (boot_lock_fuse_bits_get): Remove explicit load of Z, use 'z' constraint instead. Remove unneeded clobbers. NEW: Add item to fixed bug list. 2009-04-25 Eric B. Weddington Fix for bug #26188. * include/avr/io.h: Include separate header file for ATmega644P. * include/avr/Makefile.am (avr_HEADERS): Add new file. * include/avr/iom644p.h: New file, forked from iom644.h. (SIGNATURE_2): Fix signature byte definition. * include/avr/iom164.h: Add signature bytes for ATmega164P. * include/avr/iom324.h: Add signature bytes for ATmega324P. * NEWS: Add item to fixed bug list. 2009-04-25 Eric B. Weddington Fix for bug #26308. * include/avr/io90pwm2b.h: Replace WDE3 with WDE. * include/avr/io90pwm3b.h: Same. * NEWS: Add item to fixed bug list. 2009-04-25 Eric B. Weddington * devtools/gen-avr-lib-tree.sh: Use generic variable for turning off jump tables optimization. Turn off this optimization for more devices and architectures. 2009-04-20 Eric B. Weddington * configure.ac: Add support for ATxmega64D3. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/power.h: Same. * include/avr/sleep.h: Same. * include/avr/wdt.h: Same. * include/avr/iox64d3.h: New file. * NEWS: Add news item. 2009-04-19 Eric B. Weddington * devtools/gen-avr-lib-tree.sh: Use -fno-jump-tables to compile libraries for large memory devices. 2009-04-09 Eric B. Weddington * configure.ac: Add support for ATxmega128D3 and ATxmega256D3. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/power.h: Same. * include/avr/sleep.h: Same. * include/avr/wdt.h: Same. * include/avr/iox128d3.h: New file. * include/avr/iox256d3.h: New file. * NEWS: Add news items. 2009-04-09 Eric B. Weddington Fix for SF bug #2738926. * include/avr/eeprom.h: Add __EEGET, __EEPUT for IAR compatibility. * NEWS: Add item to fixed bug list. 2009-04-01 Eric B. Weddington * xml/avrgcc-header: Add generation of hardware pin definitions for non-xmega devices. 2009-04-01 Eric B. Weddington Put all functions in .text.avr-libc section, floating point math routines in .text.avr-libc.fplib section. * common/sectionname.h: New file. * common/asmdef.h: Fix spelling in comments. Change default linker section. * common/gasava.inc: Comment out macro that is no longer being used. * common/macros.inc: Add include file. * devtools/gen-avr-lib-tree.sh: Remove use of -mcall-prologues on 2 xmega devices. * libc/misc/eerd_block.c: Change linker section. * libc/misc/eerd_dword.c: Same. * libc/misc/eerd_word.c: Same. * libc/misc/eewr_block.c: Same. * libc/misc/eewr_dword.c: Same. * libc/misc/eewr_word.c: Same. * libc/misc/itoa.S: Same. * libc/misc/ltoa.S: Same. * libc/misc/mul10.S: Same. * libc/misc/mulsi10.S: Same. * libc/misc/ultoa.S: Same. * libc/misc/utoa.S: Same. * libc/pmstring/memchr_P.S: Same. * libc/pmstring/memcmp_P.S: Same. * libc/pmstring/memcpy_P.S: Same. * libc/pmstring/strcasecmp_P.S: Same. * libc/pmstring/strcat_P.S: Same. * libc/pmstring/strchr_P.S: Same. * libc/pmstring/strcmp_P.S: Same. * libc/pmstring/strcpy_P.S: Same. * libc/pmstring/strcspn_P.S: Same. * libc/pmstring/strlcat_P.S: Same. * libc/pmstring/strlcpy_P.S: Same. * libc/pmstring/strlen_P.S: Same. * libc/pmstring/strncasecmp_P.S: Same. * libc/pmstring/strncat_P.S: Same. * libc/pmstring/strncmp_P.S: Same. * libc/pmstring/strncpy_P.S: Same. * libc/pmstring/strnlen_P.S: Same. * libc/pmstring/strpbrk_P.S: Same. * libc/pmstring/strrchr_P.S: Same. * libc/pmstring/strsep_P.S: Same. * libc/pmstring/strspn_P.S: Same. * libc/pmstring/strstr_P.S: Same. * libc/stdio/clearerr.c: Same. * libc/stdio/fclose.c: Same. * libc/stdio/fdevopen.c: Same. * libc/stdio/feof.c: Same. * libc/stdio/ferror.c: Same. * libc/stdio/fgetc.c: Same. * libc/stdio/fgets.c: Same. * libc/stdio/fprintf.c: Same. * libc/stdio/fprintf_p.c: Same. * libc/stdio/fputc.c: Same. * libc/stdio/fputs.c: Same. * libc/stdio/fputs_p.c: Same. * libc/stdio/fread.c: Same. * libc/stdio/fscanf.c: Same. * libc/stdio/fscanf_p.c: Same. * libc/stdio/fwrite.c: Same. * libc/stdio/getc.S: Same. * libc/stdio/getchar.c: Same. * libc/stdio/gets.c: Same. * libc/stdio/printf.c: Same. * libc/stdio/printf_p.c: Same. * libc/stdio/putc.S: Same. * libc/stdio/putchar.c: Same. * libc/stdio/puts.c: Same. * libc/stdio/puts_p.c: Same. * libc/stdio/scanf.c: Same. * libc/stdio/scanf_p.c: Same. * libc/stdio/snprintf.c: Same. * libc/stdio/snprintf_p.c: Same. * libc/stdio/sprintf.c: Same. * libc/stdio/sprintf_p.c: Same. * libc/stdio/sscanf.c: Same. * libc/stdio/sscanf_p.c: Same. * libc/stdio/ultoa_invert.S: Same. * libc/stdio/ungetc.c: Same. * libc/stdio/vfprintf.c: Same. * libc/stdio/vfprintf_p.c: Same. * libc/stdio/vfscanf.c: Same. * libc/stdio/vfscanf_p.c: Same. * libc/stdio/vprintf.c: Same. * libc/stdio/vscanf.c: Same. * libc/stdio/vsnprintf.c: Same. * libc/stdio/vsnprintf_p.c: Same. * libc/stdio/vsprintf.c: Same. * libc/stdio/vsprintf_p.c: Same. * libc/stdlib/abort.S: Same. * libc/stdlib/abort.c: Same. * libc/stdlib/abs.c: Same. * libc/stdlib/assert.c: Same. And use standard function declaration. * libc/stdlib/atof.S: Same. * libc/stdlib/atoi.S: Same. * libc/stdlib/atoi.c: Same. * libc/stdlib/atol.S: Same. * libc/stdlib/atol.c: Same. * libc/stdlib/bsearch.c: Same. And use standard function declaration. * libc/stdlib/calloc.c: Same. * libc/stdlib/ctype.S: Same. * libc/stdlib/div.S: Same. * libc/stdlib/dtoa_prf.c: Same. * libc/stdlib/dtostre.c: Same. * libc/stdlib/dtostrf.c: Same. * libc/stdlib/exit.S: Same. * libc/stdlib/ftoa_engine.S: Same. * libc/stdlib/labs.c: Same. * libc/stdlib/ldiv.S: Same. * libc/stdlib/malloc.c: Same. * libc/stdlib/qsort.c: Same. And use standard function declaration. * libc/stdlib/rand.c: Same. * libc/stdlib/random.c: Same. * libc/stdlib/realloc.c: Same. * libc/stdlib/setjmp.S: Same. * libc/stdlib/strtod.c: Same. * libc/stdlib/strtol.c: Same. And use standard function declaration. * libc/stdlib/strtoul.c: Same. And use standard function declaration. * libc/string/ffs.S: Same. * libc/string/ffsl.S: Same. * libc/string/ffsll.S: Same. * libc/string/memccpy.S: Same. * libc/string/memchr.S: Same. * libc/string/memcmp.S: Same. * libc/string/memcpy.S: Same. * libc/string/memmem_P.S: Same. And add missing copyright and license, with permission from Dmitry Xmelkov. * libc/string/memmove.S: Same. * libc/string/memset.S: Same. * libc/string/strcasecmp.S: Same. * libc/string/strcasestr_P.S: Same. And add missing copyright and license, with permission from Dmitry Xmelkov. * libc/string/strcat.S: Same. * libc/string/strchr.S: Same. * libc/string/strcmp.S: Same. * libc/string/strcpy.S: Same. * libc/string/strcspn.S: Same. * libc/string/strdup.c: Same. * libc/string/strlcat.S: Same. * libc/string/strlcat.c: Same. And remove dead code. * libc/string/strlcpy.S: Same. * libc/string/strlcpy.c: Same. And remove dead code. * libc/string/strlen.S: Same. * libc/string/strlwr.S: Same. * libc/string/strncasecmp.S: Same. * libc/string/strncat.S: Same. * libc/string/strncmp.S: Same. * libc/string/strncpy.S: Same. * libc/string/strnlen.S: Same. * libc/string/strpbrk.S: Same. * libc/string/strrchr.S: Same. * libc/string/strrev.S: Same. * libc/string/strsep.S: Same. * libc/string/strspn.S: Same. * libc/string/strstr.S: Same. * libc/string/strtok.c: Same. * libc/string/strtok_r.S: Same. * libc/string/strupr.S: Same. * libm/fplib/fp32def.h: Same. * NEWS: Add item. 2009-03-27 Eric B. Weddington * include/avr/iotn48.h: Fix comment. 2009-03-23 Joerg Wunsch * include/avr/power.h: Fully enable the ATmega128RFA1 within this file. 2009-03-20 Eric B. Weddington * include/avr/iox32d4.h: Add missing typedefs on fuse definitions. * include/avr/iox64a1.h: Same. * include/avr/iox64a3.h: Same. * include/avr/iox128a1.h: Same. * include/avr/iox128a3.h: Same. * include/avr/iox256a3.h: Same. * include/avr/iox256a3b.h: Same. * include/avr/iox16a4.h: Same. * include/avr/iox16d4.h: Same. * include/avr/iox32a4.h: Same. 2009-03-19 Eric B. Weddington * configure.ac: Add support for ATxmega192A3. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * include/avr/using-tools.dox: Same. * include/avr/power.h: Same. * include/avr/wdt.h: Same. * include/avr/sleep.h: Same. * NEWS: Add news item about new device. * include/avr/iox192a3.h: New file. * xml/avrgcc-header: Add typecasts to fuse data information for xmega devices. 2009-03-19 Eric B. Weddington * include/avr/signature.h: New file. * include/avr/Makefile.am: Add signature.h. * doc/api/doxygen.config.in: Add signature.h. * NEWS: Add news item. 2009-03-19 Eric B. Weddington Fix for bug #25930. Thanks to Simon Küppers for the patch. * include/avr/portpins.h: Add short pin definitions if missing. 2009-03-19 Joerg Wunsch * tests/simulate/runtest.sh: (cosmetics) Replace <<8 by *256 to unconfuse Emacs' syntax highlighting. 2009-03-19 Eric B. Weddington Fix for SF bug #2693898. * include/avr/power.h: Add ATmega32U6 for clock_prescale* API. * NEWS: Add item to fixed bugs list. 2009-03-13 Eric B. Weddington Fix bug #25846. * include/avr/power.h: Add missing ||. * NEWS: Update for new version release. Add fixed bug item. 2009-03-08 Eric B. Weddington * include/avr/iox128a1.h: Regenerate from latest XML device file. * include/avr/iox128a3.h: Same. * include/avr/iox16a4.h: Same. * include/avr/iox256a3.h: Same. * include/avr/iox256a3b.h: Same. * include/avr/iox32a4.h: Same. * include/avr/iox64a1.h: Same. * include/avr/iox64a3.h: Same. 2009-03-07 Dmitry Xmelkov * tests/simulate/progmem.h: Add copyright notice. * tests/simulate/avr/{eeprom-1.c, sfr-1.c, sfr-2.c, sfr-3.c, sfrasm-1.S, sfrasm-2.S, sfrasm-3.S}: Add copyright notice. * tests/simulate/fplib/{add-01.c, add-02.c, add-03.c, add-500.c, add-inf.c, add-nan.c, cmp-01.c, cmp-02.c, cmp-03.c, div-01.c, div-02.c, div-03.c, div-500.c, div-inf.c, div-nan.c, flt2llng-01.c, flt2long-01.c, flt2ulng-01.c, flt2unll-01.c, llng2flt-01.c, llng2flt-500.c, mul-01.c, mul-02.c, mul-03.c, mul-500.c, mul-inf.c, mul-nan.c, neg-01.c, ulng2flt-01.c, unll2flt-01.c, unord-01.c, unord-02.c, unord-03.c}: Add copyright notice. * tests/simulate/math/{acos-01.c, acos-500.c, asin-01.c, asin-500.c, atan-01.c, atan-500.c, atan2-01.c, atan2-500.c, ceil-01.c, copysign-01.c, cos-01.c, cos-02.c, cos-500.c, cosh-01.c, cosh-02.c, cosh-500.c, exp-01.c, exp-500.c, fdim-01.c, fdim-500.c, floor-01.c, fma-01.c, fmax-01.c, fmax-500.c, fmin-01.c, fmin-500.c, fmod-01.c, fmod-500.c, fmod-nan.c, fp_mpack-01.c, frexp-01.c, hypot-01.c, hypot-500.c, isfinite-01.c, isinf-01.c, isnan-01.c, ldexp-01.c, ldexp-nan.c, log-01.c, log-02.c, log-500.c, log-nan.c, log10-01.c, lrint-01.c, lround-01.c, modf-01.c, modf-nan.c, modf-np.c, pow-01.c, pow-02.c, pow-500.c, pow-nan.c, round-01.c, signbit-01.c, sin-01.c, sin-500.c, sinh-01.c, sinh-02.c, sinh-500.c, sqrt-01.c, sqrt-500.c, tan-01.c, tan-500.c, tanh-01.c, tanh-02.c, tanh-500.c, trunc-01.c, xxx-inf.c, xxx-nan.c}: Add copyright notice. * tests/simulate/other/alloca.c: Add copyright notice. * tests/simulate/pmstring/{memchr_P.c, memcmp_P.c, memmem_P.c, memrchr_P.c, strcasecmp_P.c, strcasestr_P.c, strchr_P.c, strchrnul_P.c, strcmp_P.c, strcspn_P.c, strncasecmp_P.c, strpbrk_P.c, strrchr_P.c, strsep_P.c, strspn_P.c, strstr_P.c}: Add copyright notice. * tests/simulate/printf/{snprintf_all-P.c, snprintf_all.c, sprintf-1.c, sprintf-2.c, sprintf-3.c, sprintf-4.c, sprintf-5.c, sprintf-inv.c, sprintf_flt-big.c, sprintf_flt-e01.c, sprintf_flt-f01.c, sprintf_flt-g01.c, sprintf_flt-g02.c, sprintf_flt-nan.c, sprintf_min-1.c, sprintf_min-2.c, sprintf_min-3.c, sprintf_min-4.c, sprintf_min-5.c, sprintf_min-int.c, sprintf_min-inv.c, sprintf_std-int.c, sprintf_std-inv.c, vsnprintf_all-P.c, vsnprintf_all.c}: Add copyright notice. * tests/simulate/regression/{20080322-isinf.c, 20080323-jmpbuf.c, 20080405-eeprom.c, 20081221-ffs.c, bug-01929.c, bug-11511.c, bug-11820.c, bug-13330.c, bug-18899.c, bug-19079.c, bug-19134.c, bug-19135.c, bug-19280.c, bug-19281.c, bug-21872-1.c, bug-21872-2.c, bug-21905-scanf_flt.c, bug-21906-scanf_flt.c, bug-21955.c, bug-22593.c, bug-22800.c, bug-22828.c, bug-25048.cpp, bug-31644.c}: Add copyright notice. * tests/simulate/scanf/{scanf-nul.c, scanf_brk-nul.c, scanf_flt-nul.c, sscanf-1.c, sscanf-2.c, sscanf-c1.c, sscanf-c2.c, sscanf-d1.c, sscanf-d2.c, sscanf-eof.c, sscanf-eon.c, sscanf-h.c, sscanf-hh.c, sscanf-i.c, sscanf-l.c, sscanf-o1.c, sscanf-o2.c, sscanf-s1.c, sscanf-s2.c, sscanf-x1.c, sscanf-x2.c, sscanf-x3.c, sscanf_brk-1.c, sscanf_brk-2.c, sscanf_brk-3.c, sscanf_brk-4.c, sscanf_flt-f1.c, sscanf_flt-f2.c, sscanf_flt-f3.c, sscanf_flt-fnn.c, sscanf_flt-fw.c}: Add copyright notice. * tests/simulate/stdlib/{abort-1.c, atoi-1.c, atol-1.c, atol-2.c, bsearch-1.c, bsearch-2.c, bsearch-3.c, dtostre-01.c, dtostre-02.c, dtostre-03.c, dtostre-04.c, dtostre-05.c, dtostre-06.c, dtostre-expm00.c, dtostre-minmax.c, dtostre-nans.c, dtostre-subnrm.c, dtostre-zero.c, dtostre.h, dtostrf-01.c, dtostrf-big.c, dtostrf-minmax.c, dtostrf-nans.c, dtostrf-round.c, dtostrf-width.c, dtostrf.h, exit-1.c, isalnum-1.c, isalpha-1.c, isascii-1.c, isblank-1.c, iscntrl-1.c, isdigit-1.c, isgraph-1.c, islower-1.c, isprint-1.c, ispunct-1.c, isspace-1.c, isupper-1.c, isxdigit-1.c, setjmp-1.c, setjmp-2.c, setjmp-3.c, setjmp-4.c, setjmp-5.c, strtod-1.c, strtod-2.c, strtod-3.c, strtol-1.c, strtol-2.c, strtol-3.c, strtol-4.c, strtol.h, strtoul-1.c, strtoul-2.c, strtoul-3.c, strtoul.h, tolower-1.c, toupper-1.c}: Add copyright notice. * tests/simulate/string/{ffs-1.c, ffs_macro.c, ffsl-1.c, ffsll-1.c, memchr.c, memcmp.c, memmem.c, memrchr.c, strcasecmp.c, strcasestr.c, strchr.c, strchrnul.c, strcmp.c, strcspn.c, strlwr.c, strncasecmp.c, strpbrk.c, strrchr.c, strrev.c, strsep.c, strspn.c, strstr.c, strupr.c}: Add copyright notice. 2009-03-05 Dmitry Xmelkov * include/math.h: signbit(): remove note about implementation. isinf(), modf(): add precaution about GCC inline realization. * NEWS: add note about signbit() function. 2009-03-04 Joerg Wunsch * libc/stdlib/malloc.c: Fix a bug found by the testsuite script other/malloc-01.c: when being close to the top of heap, make sure the pointers don't wrap before calculating the available space. 2009-03-04 Eric B. Weddington * include/avr/io90scr100.h: Yet another update. 2009-03-04 Eric B. Weddington * include/avr/io90scr100.h: Updated header file based on new XML device file. 2009-03-04 Joerg Wunsch Submitted by Lou Amadio: bug #25723: Realloc corrupts free list when growing into the next free item * libc/stdlib/realloc.c: Fix calculation of freelist. * tests/simulate/regression/bug-25723.c: Testscript to demonstrate the bug as well as its fix. 2009-03-03 Joerg Wunsch * tests/simulate/other/realloc-01.c: Basic realloc() test script. Currently exhibits a failure when simulating on the AT90S8515, which is actually due to a real bug (most likely #25723). 2009-03-03 Joerg Wunsch * tests/simulate/runtest.sh: Add -g to CFLAGS, to help debugging any ELF files that experience issues in the simulation. 2009-03-03 Joerg Wunsch * tests/simulate/other/malloc-01.c: Basic malloc() test script. Currently exhibits a failure when simulating on the AT90S8515, which is actually due to a real bug (possibly same as bug #22567, and maybe #25723). 2009-03-02 Eric B. Weddington * crt1/gcrt1.S (__init): Clear RAMPD, RAMPX, RAMPY, RAMPZ registers conditional on __AVR_HAVE_RAMPD__. * include/avr/common.h (AVR_RAMPD_REG, AVR_RAMPD_ADDR, AVR_RAMPX_REG, AVR_RAMPX_ADDR, AVR_RAMPY_REG, AVR_RAMPY_ADDR): Add definitions. 2009-03-02 Eric B. Weddington * crt1/gcrt1.S (__do_copy_data): Make clearing of RAMPZ at end conditional on __AVR_HAVE_RAMPD__ (currently avrxmega3, avrxmega5, and avrxmega7 architectures). These architectures can access > 64K RAM, hence RAMPZ is required to be cleared. 2009-03-01 Eric B. Weddington Fix for bug #25120. * include/avr/pgmspace.h (__ELPM_xmega__, __ELPM_word_xmega__, __ELPM_dword_xmega__, __ELPM_float_xmega__): Add new macros. (__ELPM, __ELPM_word, __ELPM_dword, __ELPM_float): Add new conditional definitions based on __AVR_HAVE_RAMPD__ (i.e. avrxmega3, avrxmega5, and avrxmega7 architectures). * NEWS: Add item to fixed bug list. 2009-03-01 Dmitry Xmelkov * libc/stdlib/setjmp.S: longjmp(): optimize stack pointer writing in case of XMEGA devices. 2009-02-25 Joerg Wunsch * include/util/delay.h (_delay_us): Swap _delay_us() and _delay_ms() so when _delay_us() wants to fall back to _delay_ms(), the function call can actually be inlined by the compiler. 2009-02-19 Joerg Wunsch * include/avr/iom128rfa1.h: Fix some C syntax errors that have sneaked in during the last update. 2009-02-19 Eric B. Weddington * configure.ac: Add support for ATmega16U4. * devtools/gen-avr-lib-tree.sh: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/power.h: Same. * include/avr/wdt.h: Same. * include/avr/sleep.h: Same. * include/avr/iom16u4.h: New file. * NEWS: Add item. 2009-02-19 Eric B. Weddington * include/avr/sleep.h: Add sleeping BOD API. * NEWS: Add news item. 2009-02-19 Eric B. Weddington Fix bug #25645. * include/avr/iox256a3b.h: Change PR register to PRGEN because this conflicts with a #defined symbol. * include/avr/iox256a3.h: Same. * include/avr/iox128a3.h: Same. * include/avr/iox128a1.h: Same. * include/avr/iox64a3.h: Same. * include/avr/iox64a1.h: Same. * NEWS: Add item to fixed bug list. 2009-02-19 Joerg Wunsch Contributed by Bob Paddock: (part of) patch #6720: FAQ update. Add EEPROM section, baud rate section. Correct spelling. * doc/api/faq.dox: Spelling fixes, remove trailing white space. 2009-02-19 Joerg Wunsch Contributed by Bob Paddock: (part of) patch #6720: FAQ update. Add EEPROM section, baud rate section. Correct spelling. * doc/api/faq.dox (faq_eeprom_corruption, faq_wrong_baud_rate): new entries. 2009-02-18 Joerg Wunsch * include/avr/power.h: Add ATmega128RFA1. * include/avr/sleep.h: (Ditto.) 2009-02-16 Eric B. Weddington Fix repository breakage. Thanks to Anatoly. * configure.ac: Test for xmega2 architecture. Fix architecture type. * devtools/gen-avr-lib-tree.sh: Add missing semicolons. 2009-02-13 Eric B. Weddington Fix bug #25261. * include/avr/iotn48.h: Add register TWHSR. Deprecate register TWIHSR. * NEWS: Add item to fixed bug list. 2009-02-13 Eric B. Weddington Fix bug #25535. * include/avr/iotn88.h: Remove AREFD, REFS1 bit definitions. * include/avr/iotn48.h: Same. * NEWS: Add item. 2009-02-13 Eric B. Weddington * include/avr/sleep.h: Add support for ATxmega32D4, ATxmega16A4, ATxmega16D4. 2009-02-13 Eric B. Weddington * configure.ac: Add support for ATxmega32D4, ATxmega16A4, ATxmega16D4. * devtools/gen-avr-lib-tree.sh: Same. * include/Makefile.am: Same. * include/io.h: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/power.h: Same. * include/avr/wdt.h: Same. * NEWS: Same. * devtools/gen-avr-lib-tree.sh (CFLAGS_SPACE_NO_CALL): Add. Optimize for space but without -mcall-prologues flag. (AVR6_DEV_INFO) Use CFLAGS_SPACE_NO_CALL. (AVRXMEGA6_DEV_INFO) Use CFLAGS_SPACE_NO_CALL on devices with 256K+ flash. 2009-02-12 Joerg Wunsch * include/avr/iom128rfa1.h: Fix some buglets noticed by Eric: - the __NOSTRUCT__ logic was broken - _VECTORS_SIZE was off by one vector - the *_vect_num definitions were missing 2009-02-11 Eric B. Weddington Partial fix for bug #25535. * include/avr/iotn88.h: Remove SM2 bit definition. * include/avr/iotn48.h: Same. 2009-02-11 Joerg Wunsch * doc/api/assembler.dox: Add missing 3rd copyright clause. * doc/api/malloc.dox: (Ditto.) * doc/api/faq.dox: (Ditto.) 2009-02-11 Eric B. Weddington Fix bug #25131. * include/avr/iotn2313.h: Fix LFUSE_DEFAULT definition. 2009-02-11 Eric B. Weddington Make definition of XRAMEND more consistent across all I/O header files. * include/avr/io.h: Add missing word in documentation on XRAMEND. * include/avr/iousb82.h: Change XRAMEND definition from a constant to RAMEND. * include/avr/iousb162.h: Same. * include/avr/iotn84.h: Same. * include/avr/iotn85.h: Same. * include/avr/iotn861.h: Same. * include/avr/iotn44.h: Same. * include/avr/iotn45.h: Same. * include/avr/iotn461.h: Same. * include/avr/iotn22.h: Same. * include/avr/iotn2313.h: Same. * include/avr/iotn24.h: Same. * include/avr/iotn25.h: Same. * include/avr/iotn26.h: Same. * include/avr/iotn261.h: Same. * include/avr/iotn13.h: Same. * include/avr/iom8hva.h: Same. * include/avr/iom88.h: Same. * include/avr/iom8535.h: Same. * include/avr/iom8.h: Same. * include/avr/iom6490.h: Same. * include/avr/iom649.h: Same. * include/avr/iom6450.h: Same. * include/avr/iom645.h: Same. * include/avr/iom644.h: Same. * include/avr/iom48.h: Same. * include/avr/iom406.h: Same. * include/avr/iotn43u.h: Same. * include/avr/iom3290.h: Same. * include/avr/iom329.h: Same. * include/avr/iom325.h: Same. * include/avr/iom3250.h: Same. * include/avr/iom32.h: Same. * include/avr/iom323.h: Same. * include/avr/iom324.h: Same. * include/avr/iom16hva.h: Same. * include/avr/iom169.h: Same. * include/avr/iom169p.h: Same. * include/avr/iom168.h: Same. * include/avr/iom165.h: Same. * include/avr/iom165p.h: Same. * include/avr/iom164.h: Same. * include/avr/iom163.h: Same. * include/avr/iom16.h: Same. * include/avr/io90pwmx.h: Same. * include/avr/io90pwm1.h: Same. * include/avr/io86r401.h: Same. * include/avr/io8535.h: Same. * include/avr/io8534.h: Same. * include/avr/io76c711.h: Same. * include/avr/io4434.h: Same. * include/avr/io4433.h: Same. * include/avr/io43u35x.h: Same. * include/avr/io43u32x.h: Same. * include/avr/io2343.h: Same. * include/avr/io2333.h: Same. * include/avr/io2323.h: Same. * include/avr/io2313.h: Same. * include/avr/iotn88.h: Change XRAMEND definition to just RAMEND. * include/avr/iotn48.h: Same. * include/avr/iotn167.h: Same. * include/avr/iotn13a.h: Same. * include/avr/iom88p.h: Same. * include/avr/iom48p.h: Same. * include/avr/iom32hvb.h: Same. * include/avr/iom328p.h: Same. * include/avr/iom168p.h: Same. * include/avr/iom1284p.h: Same. * include/avr/ioa6289.h: Same. * include/avr/io90scr100.h: Same. * include/avr/io90pwm3b.h: Same. * include/avr/io90pwm316.h: Same. * include/avr/io90pwm2b.h: Same. * include/avr/io90pwm216.h: Same. * include/avr/iom32u6.h: Fix XRAMEND definition to be XRAMSIZE - 1. * include/avr/iom32u4.h: Same. 2009-02-08 Anatoly Sokolov * configure.ac: (FNO_JUMP_TABLES, CHECK_MNO_TABLEJUMP, CHECK_FNO_JUMP_TABLES): Add. * libc\stdio\Rules.am (PRINTF_CFLAGS): Use FNO_JUMP_TABLES. 2009-02-07 Anatoly Sokolov * include/avr/iotnx4.h: Add RSIG bit definition. * include/avr/iotnx5.h: Same. 2009-02-06 Eric B. Weddington * include/avr/iotnx4.h: Add BODS and BODSE bit definitions. * include/avr/iotnx5.h: Same. * include/avr/iomxx4.h: Define BODS and BODSE only if not ATmega644. 2009-02-06 Eric B. Weddington * include/avr/iom1284p.h: Fix OCROA_0..OCROA_7 to OCR0A_0..OCR0A_7. * include/avr/iom328p.h: Same. * include/avr/iom168p.h: Same. * include/avr/iom88p.h: Same. * include/avr/iom48p.h: Same. * include/avr/iotn48.h: Same. * include/avr/iom32u6.h: Same. * include/avr/io90scr100.h: Same. * include/avr/iom128rfa1.h: Same. 2009-02-06 Eric B. Weddington * include/avr/sleep.h: Add support for AT90PWM81. 2009-02-06 Eric B. Weddington * xml/avrgcc-header: Add Id line. Always add *PAGE_SIZE constant definitions for xmega devices. Fix definition of XRAMEND constant for classic AVR devices. * include/avr/iox128a1.h: Add *PAGE_SIZE constants. * include/avr/iox16a4.h: Same. * include/avr/iox16d4.h: Same. * include/avr/iox32a4.h: Same. * include/avr/iox32d4.h: Same. * include/avr/iox64a1.h: Same. * include/avr/iox64a3.h: Same. * include/avr/iox128a3.h: Same. * include/avr/iox256a3.h: Same. * include/avr/iox256a3b.h: Same. 2009-02-06 Joerg Wunsch * configure.ac: Bump version date to 20090205 2009-02-06 Joerg Wunsch * configure.ac: Add the ATmega128RFA1 device. * devtools/gen-avr-lib-tree.sh: (Ditto.) * include/avr/Makefile.am: (Ditto.) * include/avr/io.h: (Ditto.) * include/avr/wdt.h: (Ditto.) * include/avr/iom128rfa1.h: (Ditto.) 2009-02-04 Eric B. Weddington * bootstrap: Remove autoconf and automake version checks. * configure.ac (AC_INIT): Make this call be first in script according to docs. (AC_PREREQ): Change minimum autoconf version to 2.59. (AM_INIT_AUTOMAKE) Check for minimum automake version of 1.8 2009-02-01 Eric B. Weddington * configure.ac: Add support for AT90PWM81. * devtools/gen-avr-lib-tree.sh: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * include/avr/power.h: Same. * include/avr/wdt.h: Same. * NEWS: Add news items. 2009-02-01 Eric B. Weddington * include/avr/iox32d4.h: New file. * include/avr/iox16a4.h: New file. * include/avr/iox16d4.h: New file. 2009-02-01 Eric B. Weddington * include/avr/io90pwm81.h: New file. 2009-01-29 Eric B. Weddington * configure.ac: Add support for ATA6289. * devtools/gen-avr-lib-tree.sh: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * include/avr/sleep.h: Same. * include/avr/wdt.h: Same. * include/avr/ioa6289.h: New file. * NEWS: Add news item. 2009-01-26 Eric B. Weddington * configure.ac: Add support for ATmega64M1, ATmega64C1, ATmega16M1. * devtools/gen-avr-lib-tree.sh: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * include/avr/power.h: Same. * include/avr/sleep.h: Same. * include/avr/wdt.h: Same. * NEWS: Add news items. 2009-01-26 Eric B. Weddington * include/avr/io90pwm2b.h: Bit definitions OCR0_0..OCR0_7 were duplicated. Change to OCR0A_0..OCR0A_0 and OCR0B_0..OCR0B_7. Add old definitions back in for backwards compatibility. * include/avr/io90pwm3b.h: Same. 2009-01-26 Eric B. Weddington * include/avr/iom64m1.h: New file. * include/avr/iom64c1.h: New file. * include/avr/iom16m1.h: New file. 2009-01-26 Eric B. Weddington * include/avr/iom32m1.h: File has been regenerated from updated XML file. SPM_PAGESIZE fix, new bit definitions, new 16-bit combined registers, 22 renamed definitions, remove DAOE bitfield, fix bit definitions, new register PCICR, renamed EEPROM bit definitions, miscellaneous whitespace changes. * include/avr/iom32c1.h: File has been regenerated from updated XML file. Fix line endings to be Unix line endings, SPM_PAGESIZE fix, fix bit definitions, remove DAOE bitfield, new register PCICR, renamed EEPROM bit definitions, miscellaneous whitespace changes. * include/avr/iox32a4.h: File has been regenerated from updated XML file. PR.PR register renamed to PR.PRGEN. Fix missing AES definitions for PRGEN register. 2009-01-24 Eric B. Weddington * configure.ac: Add support for ATxmega32A4. * devtools/gen-avr-lib-tree.sh: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * include/avr/power.h: Same. * include/avr/sleep.h: Same. * include/avr/wdt.h: Same. * NEWS: Add news item. 2009-01-23 Eric B. Weddington * include/avr/iox32a4.h: New file. 2009-01-23 Eric B. Weddington * Makefile.am (EXTRA_DIST): Add ChangeLog-2008. 2009-01-22 Eric B. Weddington * configure.ac: Add support for ATtiny87. * devtools/gen-avr-lib-tree.sh: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/Makefile.am: Same. * include/avr/io.h: Same. * include/avr/power.h: Same. * include/avr/sleep.h: Same. * include/avr/wdt.h: Same. * include/avr/iotn87.h: New file. * NEWS: Add news item. For older changes see ChangeLog-2008 avr-libc-1.8.0.orig/avr-libc.spec0000644000000000000000000001427511732702554013436 0ustar ## -*- mode: rpm-spec; -*- ## ## ## Copyright (c) 2004 Theodore A. Roth ## All rights reserved. ## ## Redistribution and use in source and binary forms, with or without ## modification, are permitted provided that the following conditions are met: ## ## * Redistributions of source code must retain the above copyright ## notice, this list of conditions and the following disclaimer. ## ## * Redistributions in binary form must reproduce the above copyright ## notice, this list of conditions and the following disclaimer in ## the documentation and/or other materials provided with the ## distribution. ## ## * Neither the name of the copyright holders nor the names of ## contributors may be used to endorse or promote products derived ## from this software without specific prior written permission. ## ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ## POSSIBILITY OF SUCH DAMAGE. ## ## $Id: avr-libc.spec.in 1037 2006-01-06 22:31:33Z joerg_wunsch $ ## ## avr-libc.spec. Generated from avr-libc.spec.in by configure. ## %define libc_version 1.8.0 # We don't want rpm stripping any files %define __spec_install_post %{nil} # Don't build the debuginfo rpm %define debug_package %{nil} %define _with_docs 1 %{?_without_docs: %define _with_docs 0} Summary: AVR libc. Name: avr-libc Version: %{libc_version} Release: 1 License: BSD Group: Avr/Development/Tools URL: http://savannah.gnu.org/projects/avr-libc Source0: http://savannah.gnu.org/download/avr-libc/avr-libc-%{version}.tar.bz2 Buildroot: /var/tmp/avr-libc-%{version}-root BuildRequires: gzip avr-gcc >= 3.4.3 %if %{_with_docs} BuildRequires: doxygen >= 1.4.1 tetex transfig %endif Requires: avr-gcc >= 3.4.3 %define ourdocdir %{_defaultdocdir}/%{name} %description Avr-libc is a C library for developing applications for Atmel AVR microcontrollers. %if %{_with_docs} ## The avr-libc-docs subpackage %package docs Summary: Documentation for avr-libc. Group: Avr/Documentation %description docs Documentation for avr-libc in html, postscript and pdf formats. %endif %prep %setup -q %build ./configure \ %if %{_with_docs} --enable-doc --disable-versioned-doc \ %endif --host=avr --build=$(./config.guess) \ --prefix=%{_prefix} --mandir=%{_mandir} --infodir=%{_infodir} make %install rm -rf ${RPM_BUILD_ROOT} mkdir -p ${RPM_BUILD_ROOT}%{_prefix} make prefix=$RPM_BUILD_ROOT%{_prefix} mandir=$RPM_BUILD_ROOT%{_mandir} \ infodir=$RPM_BUILD_ROOT%{_infodir} install # Move/copy files to appropriate directory to workaround the fact that the doc # directive will delete files that are already installed. %if ! %{_with_docs} mkdir -p $RPM_BUILD_ROOT%{ourdocdir} %endif cp AUTHORS ChangeLog* INSTALL LICENSE NEWS README $RPM_BUILD_ROOT%{ourdocdir} %if %{_with_docs} gzip -9 ${RPM_BUILD_ROOT}%{ourdocdir}/man/man3/*.3 %else ## Don't need man script if we aren't installing man pages. rm ${RPM_BUILD_ROOT}%{_bindir}/avr-man %endif %clean rm -rf ${RPM_BUILD_ROOT} %files %defattr(-,root,root) %docdir %{ourdocdir} %{ourdocdir}/AUTHORS %{ourdocdir}/ChangeLog* %{ourdocdir}/INSTALL %{ourdocdir}/LICENSE %{ourdocdir}/NEWS %{ourdocdir}/README %{ourdocdir}/examples %dir %{_prefix}/avr %dir %{_prefix}/avr/lib %dir %{_prefix}/avr/lib/avr3 %dir %{_prefix}/avr/lib/avr4 %dir %{_prefix}/avr/lib/avr5 %dir %{_prefix}/avr/include %dir %{_prefix}/avr/include/avr %dir %{_prefix}/avr/include/compat %dir %{_prefix}/avr/include/util %{_prefix}/avr/lib/lib* %{_prefix}/avr/lib/crt* %{_prefix}/avr/lib/avr3/lib* %{_prefix}/avr/lib/avr3/crt* %{_prefix}/avr/lib/avr4/lib* %{_prefix}/avr/lib/avr4/crt* %{_prefix}/avr/lib/avr5/lib* %{_prefix}/avr/lib/avr5/crt* %{_prefix}/avr/include/*.h %{_prefix}/avr/include/avr/*.h %{_prefix}/avr/include/compat/*.h %{_prefix}/avr/include/util/*.h ## TRoth/20021013: Argh! Why does the fscking %doc directive remove the doc ## dir? That's absolutely stupid. We install things there _assuming_ they ## will stay there. Rpm should _not_ removing things we've installed, but alas ## it does. Be sure to watch the output when you are building the packages. %if %{_with_docs} %files docs %defattr(-,root,root) %{_bindir}/avr-man %doc %{ourdocdir}/avr-libc-user-manual %doc %{ourdocdir}/avr-libc-user-manual.ps %doc %{ourdocdir}/avr-libc-user-manual.pdf %doc %{ourdocdir}/man %endif %changelog * Fri Jan 6 2006 Galen Seitz - Dealt with moved examples directory. * Tue Nov 10 2005 Galen Seitz - Updated to work with latest tools and build procedure. * Tue Oct 21 2003 Theodore Roth - Allow disabling build of docs sub-package with "--without docs". * Thu Apr 17 2003 Theodore Roth - Don't build debuginfo package. - Don't run post install since it strips binaries. * Mon Nov 11 2002 Theodore Roth - Add --enable-doc to configure command. * Sun Oct 13 2002 Theodore Roth - Drop avr-gcc requirement to >= 3.2.75 to allow building snapshot packages. - Add docs sub-package for user manual. * Mon Aug 12 2002 Joerg Wunsch - Require avr-gcc >= 3.3. * Mon Jul 08 2002 Theodore Roth - Integrate spec file into build system. * Fri May 03 2002 Theodore Roth - Added patch to fix timer.h for mega128. * Mon Apr 29 2002 Theodore Roth - Added patch to fix headers. - Fix strncasecmp_P macro in pgmspace.h. * Wed Mar 27 2002 Theodore Roth - Updated avr-gcc dependency to 3.0.4-2. - Fixed up %files section to work with rh-7.1. * Mon Mar 17 2002 Theodore Roth - Initial spec file. avr-libc-1.8.0.orig/configure.ac0000644000000000000000000011273011732702554013344 0ustar # -*- Autoconf -*- # # Copyright (c) 2004, Theodore A. Roth # Copyright (c) 2005,2006,2007,2009 Anatoly Sokolov # Copyright (c) 2005,2008 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: configure.ac 2272 2011-12-29 08:49:21Z joerg_wunsch $ # # Process this file with autoconf to produce a configure script. # dnl library versioning -- modify these on releases dnl macro name value description m4_define([avr_libc_major], [1])dnl major version m4_define([avr_libc_minor], [8])dnl minor version m4_define([avr_libc_revision], [0])dnl revision (dot-dot version) m4_define([avr_libc_revision_suffix], [])dnl revision suffix (if any) m4_define([avr_libc_reldate], [20111228])dnl release date dnl end of library versioning data m4_define([avr_libc_version], avr_libc_major.avr_libc_minor.avr_libc_revision()avr_libc_revision_suffix)dnl m4_define([avr_libc_version_numeric], m4_eval(10000 * avr_libc_major + dnl 100 * avr_libc_minor + dnl avr_libc_revision))dnl AC_INIT(avr-libc, avr_libc_version, avr-libc-dev@nongnu.org) AC_PREREQ(2.59) AC_REVISION($Revision: 2272 $) AC_CONFIG_SRCDIR([doc/examples/demo/demo.c]) AC_CONFIG_HEADER([config.h]) dnl substitute M4 macros into shell variables AVR_LIBC_MAJOR=avr_libc_major AVR_LIBC_MINOR=avr_libc_minor AVR_LIBC_REVISION=avr_libc_revision AVR_LIBC_RELDATE=avr_libc_reldate AVR_LIBC_VERSION=avr_libc_version AVR_LIBC_VERSION_NUMERIC=avr_libc_version_numeric dnl ...and trigger Makefile.in substitutions AC_SUBST(AVR_LIBC_MAJOR) AC_SUBST(AVR_LIBC_MINOR) AC_SUBST(AVR_LIBC_REVISION) AC_SUBST(AVR_LIBC_RELDATE) AC_SUBST(AVR_LIBC_VERSION) AC_SUBST(AVR_LIBC_VERSION_NUMERIC) AC_CANONICAL_BUILD AC_CANONICAL_HOST # See if the user specified '--build=`../config.guess` --host=avr' when # running ../configure. AC_MSG_CHECKING([if configuring for cross compile]) if test "x${build_alias}" = "x${host_alias}"; then if test "x${build_alias}" = "x" ; then build_alias='`./config.guess`' fi AC_MSG_RESULT(no) AC_MSG_WARN() AC_MSG_WARN(AVR-LIBC must be built using an avr cross-compiler.) AC_MSG_WARN(Try configuring with:) AC_MSG_WARN("$0 --build=$build_alias --host=avr") AC_MSG_WARN() AC_MSG_ERROR(aborting configure) else AC_MSG_RESULT([yes]) fi AC_MSG_CHECKING([if target host is avr]) case "$host" in avr* ) AC_MSG_RESULT([yes]) ;; * ) AC_MSG_RESULT(no) AC_MSG_WARN() AC_MSG_WARN(Avr-libc must be built using an avr cross-compiler.) AC_MSG_WARN(Try configuring with:) AC_MSG_WARN("$0 --build=$build --host=avr") AC_MSG_WARN() AC_MSG_ERROR(aborting configure) ;; esac ## TODO: Write a check for GNU Make dnl The default check whether the C compiler can create an executable dnl is inappropriate for us as it requires an existing library. AC_NO_EXECUTABLES dnl Minimum version of Automake is 1.8. dnl We don't want the gzip distribution tarball anymore. AM_INIT_AUTOMAKE([1.8 dist-bzip2 no-dist-gzip]) # We don't want touse the cflags from the environment since we need control # of this when we're building the libs. CFLAGS="" dnl This fix is from Newlib in config/override.m4. dnl Fix 2.64 cross compile detection for AVR by not trying to compile fopen. m4_if(m4_defn([m4_PACKAGE_VERSION]), [2.64], [m4_foreach([_GCC_LANG], [C, C++, Fortran, Fortran 77], [m4_define([_AC_LANG_IO_PROGRAM(]_GCC_LANG[)], m4_defn([AC_LANG_PROGRAM(]_GCC_LANG[)]))])]) # Checks for programs. AC_PROG_CC AC_CHECK_TOOL(AS, as, as) AM_PROG_AS AC_PROG_RANLIB AC_CHECK_TOOL(AR, ar, ar) # Make sure that we found the right avr cross-compiler. case "${CC}" in *avr*gcc*) ;; *) AC_MSG_ERROR(Wrong C compiler found; check the PATH!) ;; esac case "${AS}" in *avr*as*) ;; *) AC_MSG_ERROR(Wrong assembler found; check the PATH!) ;; esac case "${AR}" in *avr*ar*) ;; *) AC_MSG_ERROR(Wrong archiver found; check the PATH!) ;; esac case "${RANLIB}" in *avr*ranlib*) ;; *) AC_MSG_ERROR(Wrong ranlib found; check the PATH!) ;; esac AC_PROG_INSTALL AC_PROG_LN_S AC_PROG_MAKE_SET dnl TODO: Check for various tools used to build the documentation. If anything dnl is missing, don't build the docs by default. dnl Disable building of dox by default since it they may not build properly on dnl all systems. This isn't optimal, but how do we work around the user not dnl having fig2dev and still build all the formats? AC_ARG_ENABLE(doc, [ --enable-doc build all doc formats (disabled is default)], [case "${enableval}" in yes) enable_doc=yes ;; no) enable_doc=no ;; *) AC_MSG_ERROR(bad value ${enableval} for global doc option) ;; esac], [enable_doc=no])dnl dnl Various documentation options. By default, we enable all of them, dnl i. e. HTML, Postscript, PDF, and Unix-style man pages. AC_ARG_ENABLE(html-doc, [ --enable-html-doc build HTML documentation (default)], [case "${enableval}" in yes) html_doc=yes ;; no) html_doc=no ;; *) AC_MSG_ERROR(bad value ${enableval} for html-doc option) ;; esac], [html_doc=yes])dnl AC_ARG_ENABLE(pdf-doc, [ --enable-pdf-doc build PDF documentation (default)], [case "${enableval}" in yes) pdf_doc=yes ;; no) pdf_doc=no ;; *) AC_MSG_ERROR(bad value ${enableval} for pdf-doc option) ;; esac], [pdf_doc=yes])dnl dnl Man pages are currently not tunable; they'll be built whenever dnl the HTML documentation is built. However, it can be configured dnl whether the result is about to be installed or not. AC_ARG_ENABLE(man-doc, [ --enable-man-doc build Unix-style manual pages (default)], [case "${enableval}" in yes) man_doc=yes ;; no) man_doc=no ;; *) AC_MSG_ERROR(bad value ${enableval} for man-doc option) ;; esac], [man_doc=yes])dnl AC_ARG_ENABLE(versioned-doc, [ --enable-versioned-doc install docs in directory with version name (default)], [case "${enableval}" in yes) versioned_doc=yes ;; no) versioned_doc=no ;; *) AC_MSG_ERROR(bad value ${enableval} for versioned-doc option) ;; esac], [versioned_doc=yes])dnl dnl troth/2002-07-12: The CHECK_DOXYGEN macro should be moved to a config dnl dir. I put it here until I figure out how to integrate the config dir. dnl dnl @synopsis CHECK_DOXYGEN dnl dnl This macro checks if doxygen is installed on the build system dnl dnl @version Id: check_doxygen.m4,v 1.2 2002/02/10 23:22:40 troth Exp dnl @author Theodore A. Roth dnl AC_DEFUN([CHECK_DOXYGEN],[dnl dnl AC_MSG_CHECKING([for doxygen]) dox_ver=`doxygen --version 2>/dev/null` if test "x$dox_ver" = "x"; then AC_MSG_RESULT(no) else # FIXME: should also check for dox_ver >= 1.4.1 AC_MSG_RESULT(yes) if test "$pdf_doc" = "yes"; then AC_MSG_NOTICE([Enabling PDF docs]) TARGET_DOX_PDF=dox-pdf INSTALL_DOX_PDF=install-dox-pdf fi if test "$html_doc" = "yes"; then AC_MSG_NOTICE([Enabling HTML docs]) TARGET_DOX_HTML=dox-html INSTALL_DOX_HTML=install-dox-html fi dnl The creation of man pages is a side-effect of the HTML dnl generation, so a different target is only needed for installation. if test "$man_doc" = "yes"; then AC_MSG_NOTICE([Enabling man pages]) TARGET_DOX_HTML=dox-html INSTALL_DOX_MAN=install-dox-man fi fi dnl AC_SUBST(TARGET_DOX_PDF) AC_SUBST(TARGET_DOX_HTML) AC_SUBST(INSTALL_DOX_PDF) AC_SUBST(INSTALL_DOX_HTML) AC_SUBST(INSTALL_DOX_MAN) ])dnl CHECK_DOXYGEN dnl dnl @synopsis CHECK_PNG_UTILS dnl dnl This macro checks if pngtopnm and pnmtopng are installed. If they are not dnl installed we just fake it with "cat". dnl dnl We use these in the dox to insert transparency into the png images as such: dnl dnl $ pngtopnm foo.png > tmp.pnm dnl $ pnmtopng -transparent white tmp.pnm > foo.png dnl dnl @version dnl @author Theodore A. Roth and Eric B. Weddington dnl AC_DEFUN([CHECK_PNG_UTILS],[dnl dnl AC_MSG_CHECKING([for pngtopnm]) has_pngtopnm=`pngtopnm --version 2>&1 | grep -c -i Version` if test "$has_pngtopnm" = "1"; then AC_MSG_RESULT(yes) PNGTOPNM="pngtopnm" else AC_MSG_RESULT(no) PNGTOPNM="cat" fi dnl AC_MSG_CHECKING([for pnmtopng]) has_pnmtopng=`pnmtopng --version 2>&1 | grep -c -i Version` if test "$has_pnmtopng" = "1"; then AC_MSG_RESULT(yes) PNMTOPNG="pnmtopng" else AC_MSG_RESULT(no) PNMTOPNG="cat" PNGTOPNM="cat" fi AC_SUBST(PNGTOPNM) AC_SUBST(PNMTOPNG) ])dnl CHECK_PNG_UTILS if test "$versioned_doc" = "yes"; then DOC_INST_DIR='${DESTDIR}${datadir}/doc/avr-libc-$(VERSION)' AVR_LIBC_USER_MANUAL="avr-libc-user-manual-${VERSION}" else DOC_INST_DIR='${DESTDIR}${datadir}/doc/avr-libc' AVR_LIBC_USER_MANUAL="avr-libc-user-manual" fi dnl We only want to build the docs if the user has passed dnl "--enable-doc" to configure. if test "$enable_doc" = "yes"; then DOCSDIR='api' else DOCSDIR='' fi AC_SUBST(DOCSDIR) AC_SUBST(AVR_LIBC_USER_MANUAL) AC_SUBST(DOC_INST_DIR) FNO_JUMP_TABLES="" AC_SUBST(FNO_JUMP_TABLES) HAS_DELAY_CYCLES=0 AC_SUBST(HAS_DELAY_CYCLES) AC_DEFUN( CHECK_MNO_TABLEJUMP, [ old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mno-tablejump" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` AC_MSG_CHECKING(whether ${CC} supports -mno-tablejump) AC_COMPILE_IFELSE( [AC_LANG_SOURCE([],[])], [has_mno_tablejump=yes], [has_mno_tablejump=no] ) if test "x$has_mno_tablejump" = "xyes" then FNO_JUMP_TABLES="-mno-tablejump" fi AC_MSG_RESULT($has_mno_tablejump) CC=${old_CC} CFLAGS=${old_CFLAGS} ] ) AC_DEFUN( CHECK_FNO_JUMP_TABLES, [ old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-fno-jump-tables" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` AC_MSG_CHECKING(whether ${CC} supports -fno-jump-tables) AC_COMPILE_IFELSE( [AC_LANG_SOURCE([],[])], [has_fno_jump_tables=yes], [has_fno_jump_tables=no] ) if test "x$has_fno_jump_tables" = "xyes" then FNO_JUMP_TABLES="-fno-jump-tables" fi AC_MSG_RESULT($has_fno_jump_tables) CC=${old_CC} CFLAGS=${old_CFLAGS} ] ) AC_DEFUN( CHECK_BUILTIN_DELAY_CYCLES, [ CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` AC_MSG_CHECKING(whether ${CC} supports __builtin_avr_delay_cycles) echo "extern void __builtin_avr_delay_cycles(unsigned long);\ int main(void) { __builtin_avr_delay_cycles(42); return 0; }" |\ ${CC} -S -xc -o- - |\ grep __builtin_avr_delay_cycles >/dev/null if test "$?" != "0" then HAS_DELAY_CYCLES=1 has_delay_cycles="yes" else has_delay_cycles="no" fi AC_MSG_RESULT($has_delay_cycles) CC=${old_CC} ] ) CHECK_MNO_TABLEJUMP CHECK_FNO_JUMP_TABLES CHECK_BUILTIN_DELAY_CYCLES dnl Some devices are only handled by newer version of gcc. This macro lets us dnl probe to see if the installed avr-gcc supports a questionable device. AC_DEFUN( CHECK_AVR_DEVICE, [ old_CC=${CC} old_CFLAGS=${CFLAGS} CFLAGS="-mmcu=$1" CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` AC_MSG_CHECKING(if ${CC} has support for $1) AC_COMPILE_IFELSE( [AC_LANG_SOURCE([],[])], [has_dev_support=yes], [has_dev_support=no] ) if test "x$has_dev_support" = "xyes" then HAS_$1=yes fi AC_MSG_RESULT($has_dev_support) CC=${old_CC} CFLAGS=${old_CFLAGS} ] ) # avr1 AM_CONDITIONAL(HAS_avr1, true) AM_CONDITIONAL(HAS_at90s1200, true) AM_CONDITIONAL(HAS_attiny11, true) AM_CONDITIONAL(HAS_attiny12, true) AM_CONDITIONAL(HAS_attiny15, true) AM_CONDITIONAL(HAS_attiny28, true) # avr2 AM_CONDITIONAL(HAS_avr2, true) AM_CONDITIONAL(HAS_at90s2313, true) AM_CONDITIONAL(HAS_at90s2323, true) AM_CONDITIONAL(HAS_at90s2333, true) AM_CONDITIONAL(HAS_at90s2343, true) AM_CONDITIONAL(HAS_at90s4414, true) AM_CONDITIONAL(HAS_at90s4433, true) AM_CONDITIONAL(HAS_at90s4434, true) AM_CONDITIONAL(HAS_at90s8515, true) AM_CONDITIONAL(HAS_at90c8534, true) AM_CONDITIONAL(HAS_at90s8535, true) AM_CONDITIONAL(HAS_attiny22, true) AM_CONDITIONAL(HAS_attiny26, true) #avr25 CHECK_AVR_DEVICE(avr25) AM_CONDITIONAL(HAS_avr25, test "x$HAS_avr25" = "xyes") CHECK_AVR_DEVICE(ata6289) AM_CONDITIONAL(HAS_ata6289, test "x$HAS_ata6289" = "xyes") CHECK_AVR_DEVICE(attiny13) AM_CONDITIONAL(HAS_attiny13, test "x$HAS_attiny13" = "xyes") CHECK_AVR_DEVICE(attiny13a) AM_CONDITIONAL(HAS_attiny13a, test "x$HAS_attiny13a" = "xyes") CHECK_AVR_DEVICE(attiny2313) AM_CONDITIONAL(HAS_attiny2313, test "x$HAS_attiny2313" = "xyes") CHECK_AVR_DEVICE(attiny2313a) AM_CONDITIONAL(HAS_attiny2313a, test "x$HAS_attiny2313a" = "xyes") CHECK_AVR_DEVICE(attiny24) AM_CONDITIONAL(HAS_attiny24, test "x$HAS_attiny24" = "xyes") CHECK_AVR_DEVICE(attiny24a) AM_CONDITIONAL(HAS_attiny24a, test "x$HAS_attiny24a" = "xyes") CHECK_AVR_DEVICE(attiny25) AM_CONDITIONAL(HAS_attiny25, test "x$HAS_attiny25" = "xyes") CHECK_AVR_DEVICE(attiny261) AM_CONDITIONAL(HAS_attiny261, test "x$HAS_attiny261" = "xyes") CHECK_AVR_DEVICE(attiny261a) AM_CONDITIONAL(HAS_attiny261a, test "x$HAS_attiny261a" = "xyes") CHECK_AVR_DEVICE(attiny43u) AM_CONDITIONAL(HAS_attiny43u, test "x$HAS_attiny43u" = "xyes") CHECK_AVR_DEVICE(attiny4313) AM_CONDITIONAL(HAS_attiny4313, test "x$HAS_attiny4313" = "xyes") CHECK_AVR_DEVICE(attiny44) AM_CONDITIONAL(HAS_attiny44, test "x$HAS_attiny44" = "xyes") CHECK_AVR_DEVICE(attiny44a) AM_CONDITIONAL(HAS_attiny44a, test "x$HAS_attiny44a" = "xyes") CHECK_AVR_DEVICE(attiny45) AM_CONDITIONAL(HAS_attiny45, test "x$HAS_attiny45" = "xyes") CHECK_AVR_DEVICE(attiny461) AM_CONDITIONAL(HAS_attiny461, test "x$HAS_attiny461" = "xyes") CHECK_AVR_DEVICE(attiny461a) AM_CONDITIONAL(HAS_attiny461a, test "x$HAS_attiny461a" = "xyes") CHECK_AVR_DEVICE(attiny48) AM_CONDITIONAL(HAS_attiny48, test "x$HAS_attiny48" = "xyes") CHECK_AVR_DEVICE(attiny84) AM_CONDITIONAL(HAS_attiny84, test "x$HAS_attiny84" = "xyes") CHECK_AVR_DEVICE(attiny84a) AM_CONDITIONAL(HAS_attiny84a, test "x$HAS_attiny84a" = "xyes") CHECK_AVR_DEVICE(attiny85) AM_CONDITIONAL(HAS_attiny85, test "x$HAS_attiny85" = "xyes") CHECK_AVR_DEVICE(attiny861) AM_CONDITIONAL(HAS_attiny861, test "x$HAS_attiny861" = "xyes") CHECK_AVR_DEVICE(attiny861a) AM_CONDITIONAL(HAS_attiny861a, test "x$HAS_attiny861a" = "xyes") CHECK_AVR_DEVICE(attiny87) AM_CONDITIONAL(HAS_attiny87, test "x$HAS_attiny87" = "xyes") CHECK_AVR_DEVICE(attiny88) AM_CONDITIONAL(HAS_attiny88, test "x$HAS_attiny88" = "xyes") CHECK_AVR_DEVICE(at86rf401) AM_CONDITIONAL(HAS_at86rf401, test "x$HAS_at86rf401" = "xyes") # avr3 AM_CONDITIONAL(HAS_avr3, true) AM_CONDITIONAL(HAS_at43usb320, true) AM_CONDITIONAL(HAS_at43usb355, true) AM_CONDITIONAL(HAS_at76c711, true) #avr31 CHECK_AVR_DEVICE(avr31) AM_CONDITIONAL(HAS_avr31, test "x$HAS_avr31" = "xyes") AM_CONDITIONAL(HAS_atmega103, true) #avr35 CHECK_AVR_DEVICE(avr35) AM_CONDITIONAL(HAS_avr35, test "x$HAS_avr35" = "xyes") CHECK_AVR_DEVICE(at90usb82) AM_CONDITIONAL(HAS_at90usb82, test "x$HAS_at90usb82" = "xyes") CHECK_AVR_DEVICE(at90usb162) AM_CONDITIONAL(HAS_at90usb162, test "x$HAS_at90usb162" = "xyes") CHECK_AVR_DEVICE(atmega8u2) AM_CONDITIONAL(HAS_atmega8u2, test "x$HAS_atmega8u2" = "xyes") CHECK_AVR_DEVICE(atmega16u2) AM_CONDITIONAL(HAS_atmega16u2, test "x$HAS_atmega16u2" = "xyes") CHECK_AVR_DEVICE(atmega32u2) AM_CONDITIONAL(HAS_atmega32u2, test "x$HAS_atmega32u2" = "xyes") CHECK_AVR_DEVICE(attiny167) AM_CONDITIONAL(HAS_attiny167, test "x$HAS_attiny167" = "xyes") # avr4 AM_CONDITIONAL(HAS_avr4, true) AM_CONDITIONAL(HAS_atmega8, true) AM_CONDITIONAL(HAS_atmega8515, true) AM_CONDITIONAL(HAS_atmega8535, true) CHECK_AVR_DEVICE(atmega48) AM_CONDITIONAL(HAS_atmega48, test "x$HAS_atmega48" = "xyes") CHECK_AVR_DEVICE(atmega48a) AM_CONDITIONAL(HAS_atmega48a, test "x$HAS_atmega48a" = "xyes") CHECK_AVR_DEVICE(atmega48p) AM_CONDITIONAL(HAS_atmega48p, test "x$HAS_atmega48p" = "xyes") CHECK_AVR_DEVICE(atmega88) AM_CONDITIONAL(HAS_atmega88, test "x$HAS_atmega88" = "xyes") CHECK_AVR_DEVICE(atmega88a) AM_CONDITIONAL(HAS_atmega88a, test "x$HAS_atmega88a" = "xyes") CHECK_AVR_DEVICE(atmega88p) AM_CONDITIONAL(HAS_atmega88p, test "x$HAS_atmega88p" = "xyes") CHECK_AVR_DEVICE(atmega88pa) AM_CONDITIONAL(HAS_atmega88pa, test "x$HAS_atmega88pa" = "xyes") CHECK_AVR_DEVICE(atmega8hva) AM_CONDITIONAL(HAS_atmega8hva, test "x$HAS_atmega8hva" = "xyes") CHECK_AVR_DEVICE(at90pwm1) AM_CONDITIONAL(HAS_at90pwm1, test "x$HAS_at90pwm1" = "xyes") CHECK_AVR_DEVICE(at90pwm2) AM_CONDITIONAL(HAS_at90pwm2, test "x$HAS_at90pwm2" = "xyes") CHECK_AVR_DEVICE(at90pwm2b) AM_CONDITIONAL(HAS_at90pwm2b, test "x$HAS_at90pwm2b" = "xyes") CHECK_AVR_DEVICE(at90pwm3) AM_CONDITIONAL(HAS_at90pwm3, test "x$HAS_at90pwm3" = "xyes") CHECK_AVR_DEVICE(at90pwm3b) AM_CONDITIONAL(HAS_at90pwm3b, test "x$HAS_at90pwm3b" = "xyes") CHECK_AVR_DEVICE(at90pwm81) AM_CONDITIONAL(HAS_at90pwm81, test "x$HAS_at90pwm81" = "xyes") # avr5 AM_CONDITIONAL(HAS_avr5, true) CHECK_AVR_DEVICE(at90can32) AM_CONDITIONAL(HAS_at90can32, test "x$HAS_at90can32" = "xyes") CHECK_AVR_DEVICE(at90can64) AM_CONDITIONAL(HAS_at90can64, test "x$HAS_at90can64" = "xyes") CHECK_AVR_DEVICE(at90scr100) AM_CONDITIONAL(HAS_at90scr100, test "x$HAS_at90scr100" = "xyes") CHECK_AVR_DEVICE(at90usb646) AM_CONDITIONAL(HAS_at90usb646, test "x$HAS_at90usb646" = "xyes") CHECK_AVR_DEVICE(at90usb647) AM_CONDITIONAL(HAS_at90usb647, test "x$HAS_at90usb647" = "xyes") CHECK_AVR_DEVICE(at90pwm316) AM_CONDITIONAL(HAS_at90pwm316, test "x$HAS_at90pwm316" = "xyes") CHECK_AVR_DEVICE(at90pwm216) AM_CONDITIONAL(HAS_at90pwm216, test "x$HAS_at90pwm216" = "xyes") CHECK_AVR_DEVICE(at94k) AM_CONDITIONAL(HAS_at94k, test "x$HAS_at94k" = "xyes") CHECK_AVR_DEVICE(atmega16) AM_CONDITIONAL(HAS_atmega16, test "x$HAS_atmega16" = "xyes") CHECK_AVR_DEVICE(atmega16a) AM_CONDITIONAL(HAS_atmega16a, test "x$HAS_atmega16a" = "xyes") CHECK_AVR_DEVICE(atmega161) AM_CONDITIONAL(HAS_atmega161, test "x$HAS_atmega161" = "xyes") CHECK_AVR_DEVICE(atmega162) AM_CONDITIONAL(HAS_atmega162, test "x$HAS_atmega162" = "xyes") CHECK_AVR_DEVICE(atmega163) AM_CONDITIONAL(HAS_atmega163, test "x$HAS_atmega163" = "xyes") CHECK_AVR_DEVICE(atmega164a) AM_CONDITIONAL(HAS_atmega164a, test "x$HAS_atmega164a" = "xyes") CHECK_AVR_DEVICE(atmega164p) AM_CONDITIONAL(HAS_atmega164p, test "x$HAS_atmega164p" = "xyes") CHECK_AVR_DEVICE(atmega165) AM_CONDITIONAL(HAS_atmega165, test "x$HAS_atmega165" = "xyes") CHECK_AVR_DEVICE(atmega165a) AM_CONDITIONAL(HAS_atmega165a, test "x$HAS_atmega165a" = "xyes") CHECK_AVR_DEVICE(atmega165p) AM_CONDITIONAL(HAS_atmega165p, test "x$HAS_atmega165p" = "xyes") CHECK_AVR_DEVICE(atmega168) AM_CONDITIONAL(HAS_atmega168, test "x$HAS_atmega168" = "xyes") CHECK_AVR_DEVICE(atmega168a) AM_CONDITIONAL(HAS_atmega168a, test "x$HAS_atmega168a" = "xyes") CHECK_AVR_DEVICE(atmega168p) AM_CONDITIONAL(HAS_atmega168p, test "x$HAS_atmega168p" = "xyes") CHECK_AVR_DEVICE(atmega169) AM_CONDITIONAL(HAS_atmega169, test "x$HAS_atmega169" = "xyes") CHECK_AVR_DEVICE(atmega169a) AM_CONDITIONAL(HAS_atmega169a, test "x$HAS_atmega169a" = "xyes") CHECK_AVR_DEVICE(atmega169p) AM_CONDITIONAL(HAS_atmega169p, test "x$HAS_atmega169p" = "xyes") CHECK_AVR_DEVICE(atmega169pa) AM_CONDITIONAL(HAS_atmega169pa, test "x$HAS_atmega169pa" = "xyes") CHECK_AVR_DEVICE(atmega16hva) AM_CONDITIONAL(HAS_atmega16hva, test "x$HAS_atmega16hva" = "xyes") CHECK_AVR_DEVICE(atmega16hva2) AM_CONDITIONAL(HAS_atmega16hva2, test "x$HAS_atmega16hva2" = "xyes") CHECK_AVR_DEVICE(atmega16hvb) AM_CONDITIONAL(HAS_atmega16hvb, test "x$HAS_atmega16hvb" = "xyes") CHECK_AVR_DEVICE(atmega16hvbrevb) AM_CONDITIONAL(HAS_atmega16hvbrevb, test "x$HAS_atmega16hvbrevb" = "xyes") CHECK_AVR_DEVICE(atmega16m1) AM_CONDITIONAL(HAS_atmega16m1, test "x$HAS_atmega16m1" = "xyes") CHECK_AVR_DEVICE(atmega16u4) AM_CONDITIONAL(HAS_atmega16u4, test "x$HAS_atmega16u4" = "xyes") CHECK_AVR_DEVICE(atmega32) AM_CONDITIONAL(HAS_atmega32, test "x$HAS_atmega32" = "xyes") CHECK_AVR_DEVICE(atmega323) AM_CONDITIONAL(HAS_atmega323, test "x$HAS_atmega323" = "xyes") CHECK_AVR_DEVICE(atmega324a) AM_CONDITIONAL(HAS_atmega324a, test "x$HAS_atmega324a" = "xyes") CHECK_AVR_DEVICE(atmega324p) AM_CONDITIONAL(HAS_atmega324p, test "x$HAS_atmega324p" = "xyes") CHECK_AVR_DEVICE(atmega324pa) AM_CONDITIONAL(HAS_atmega324pa, test "x$HAS_atmega324pa" = "xyes") CHECK_AVR_DEVICE(atmega325) AM_CONDITIONAL(HAS_atmega325, test "x$HAS_atmega325" = "xyes") CHECK_AVR_DEVICE(atmega325a) AM_CONDITIONAL(HAS_atmega325a, test "x$HAS_atmega325a" = "xyes") CHECK_AVR_DEVICE(atmega325p) AM_CONDITIONAL(HAS_atmega325p, test "x$HAS_atmega325p" = "xyes") CHECK_AVR_DEVICE(atmega3250) AM_CONDITIONAL(HAS_atmega3250, test "x$HAS_atmega3250" = "xyes") CHECK_AVR_DEVICE(atmega3250a) AM_CONDITIONAL(HAS_atmega3250a, test "x$HAS_atmega3250a" = "xyes") CHECK_AVR_DEVICE(atmega3250p) AM_CONDITIONAL(HAS_atmega3250p, test "x$HAS_atmega3250p" = "xyes") CHECK_AVR_DEVICE(atmega328) AM_CONDITIONAL(HAS_atmega328, test "x$HAS_atmega328" = "xyes") CHECK_AVR_DEVICE(atmega328p) AM_CONDITIONAL(HAS_atmega328p, test "x$HAS_atmega328p" = "xyes") CHECK_AVR_DEVICE(atmega329) AM_CONDITIONAL(HAS_atmega329, test "x$HAS_atmega329" = "xyes") CHECK_AVR_DEVICE(atmega329a) AM_CONDITIONAL(HAS_atmega329a, test "x$HAS_atmega329a" = "xyes") CHECK_AVR_DEVICE(atmega329p) AM_CONDITIONAL(HAS_atmega329p, test "x$HAS_atmega329p" = "xyes") CHECK_AVR_DEVICE(atmega329pa) AM_CONDITIONAL(HAS_atmega329pa, test "x$HAS_atmega329pa" = "xyes") CHECK_AVR_DEVICE(atmega3290) AM_CONDITIONAL(HAS_atmega3290, test "x$HAS_atmega3290" = "xyes") CHECK_AVR_DEVICE(atmega3290a) AM_CONDITIONAL(HAS_atmega3290a, test "x$HAS_atmega3290a" = "xyes") CHECK_AVR_DEVICE(atmega3290p) AM_CONDITIONAL(HAS_atmega3290p, test "x$HAS_atmega3290p" = "xyes") CHECK_AVR_DEVICE(atmega32c1) AM_CONDITIONAL(HAS_atmega32c1, test "x$HAS_atmega32c1" = "xyes") CHECK_AVR_DEVICE(atmega32hvb) AM_CONDITIONAL(HAS_atmega32hvb, test "x$HAS_atmega32hvb" = "xyes") CHECK_AVR_DEVICE(atmega32hvbrevb) AM_CONDITIONAL(HAS_atmega32hvbrevb, test "x$HAS_atmega32hvbrevb" = "xyes") CHECK_AVR_DEVICE(atmega32m1) AM_CONDITIONAL(HAS_atmega32m1, test "x$HAS_atmega32m1" = "xyes") CHECK_AVR_DEVICE(atmega32u4) AM_CONDITIONAL(HAS_atmega32u4, test "x$HAS_atmega32u4" = "xyes") CHECK_AVR_DEVICE(atmega32u6) AM_CONDITIONAL(HAS_atmega32u6, test "x$HAS_atmega32u6" = "xyes") CHECK_AVR_DEVICE(atmega406) AM_CONDITIONAL(HAS_atmega406, test "x$HAS_atmega406" = "xyes") CHECK_AVR_DEVICE(atmega64) AM_CONDITIONAL(HAS_atmega64, test "x$HAS_atmega64" = "xyes") CHECK_AVR_DEVICE(atmega640) AM_CONDITIONAL(HAS_atmega640, test "x$HAS_atmega640" = "xyes") CHECK_AVR_DEVICE(atmega644) AM_CONDITIONAL(HAS_atmega644, test "x$HAS_atmega644" = "xyes") CHECK_AVR_DEVICE(atmega644a) AM_CONDITIONAL(HAS_atmega644a, test "x$HAS_atmega644a" = "xyes") CHECK_AVR_DEVICE(atmega644p) AM_CONDITIONAL(HAS_atmega644p, test "x$HAS_atmega644p" = "xyes") CHECK_AVR_DEVICE(atmega644pa) AM_CONDITIONAL(HAS_atmega644pa, test "x$HAS_atmega644pa" = "xyes") CHECK_AVR_DEVICE(atmega645) AM_CONDITIONAL(HAS_atmega645, test "x$HAS_atmega645" = "xyes") CHECK_AVR_DEVICE(atmega645a) AM_CONDITIONAL(HAS_atmega645a, test "x$HAS_atmega645a" = "xyes") CHECK_AVR_DEVICE(atmega645p) AM_CONDITIONAL(HAS_atmega645p, test "x$HAS_atmega645p" = "xyes") CHECK_AVR_DEVICE(atmega6450) AM_CONDITIONAL(HAS_atmega6450, test "x$HAS_atmega6450" = "xyes") CHECK_AVR_DEVICE(atmega6450a) AM_CONDITIONAL(HAS_atmega6450a, test "x$HAS_atmega6450a" = "xyes") CHECK_AVR_DEVICE(atmega6450p) AM_CONDITIONAL(HAS_atmega6450p, test "x$HAS_atmega6450p" = "xyes") CHECK_AVR_DEVICE(atmega649) AM_CONDITIONAL(HAS_atmega649, test "x$HAS_atmega649" = "xyes") CHECK_AVR_DEVICE(atmega649a) AM_CONDITIONAL(HAS_atmega649a, test "x$HAS_atmega649a" = "xyes") CHECK_AVR_DEVICE(atmega649p) AM_CONDITIONAL(HAS_atmega649p, test "x$HAS_atmega649p" = "xyes") CHECK_AVR_DEVICE(atmega6490) AM_CONDITIONAL(HAS_atmega6490, test "x$HAS_atmega6490" = "xyes") CHECK_AVR_DEVICE(atmega6490a) AM_CONDITIONAL(HAS_atmega6490a, test "x$HAS_atmega6490a" = "xyes") CHECK_AVR_DEVICE(atmega6490p) AM_CONDITIONAL(HAS_atmega6490p, test "x$HAS_atmega6490p" = "xyes") CHECK_AVR_DEVICE(atmega64c1) AM_CONDITIONAL(HAS_atmega64c1, test "x$HAS_atmega64c1" = "xyes") CHECK_AVR_DEVICE(atmega64hve) AM_CONDITIONAL(HAS_atmega64hve, test "x$HAS_atmega64hve" = "xyes") CHECK_AVR_DEVICE(atmega64m1) AM_CONDITIONAL(HAS_atmega64m1, test "x$HAS_atmega64m1" = "xyes") CHECK_AVR_DEVICE(atmega128rfa1) AM_CONDITIONAL(HAS_atmega128rfa1, test "x$HAS_atmega128rfa1" = "xyes") CHECK_AVR_DEVICE(m3000) AM_CONDITIONAL(HAS_m3000, test "x$HAS_m3000" = "xyes") #avr51 CHECK_AVR_DEVICE(avr51) AM_CONDITIONAL(HAS_avr51, test "x$HAS_avr51" = "xyes") AM_CONDITIONAL(HAS_atmega128, true) CHECK_AVR_DEVICE(atmega1280) AM_CONDITIONAL(HAS_atmega1280, test "x$HAS_atmega1280" = "xyes") CHECK_AVR_DEVICE(atmega1281) AM_CONDITIONAL(HAS_atmega1281, test "x$HAS_atmega1281" = "xyes") CHECK_AVR_DEVICE(atmega1284p) AM_CONDITIONAL(HAS_atmega1284p, test "x$HAS_atmega1284p" = "xyes") CHECK_AVR_DEVICE(at90can128) AM_CONDITIONAL(HAS_at90can128, test "x$HAS_at90can128" = "xyes") CHECK_AVR_DEVICE(at90usb1286) AM_CONDITIONAL(HAS_at90usb1286, test "x$HAS_at90usb1286" = "xyes") CHECK_AVR_DEVICE(at90usb1287) AM_CONDITIONAL(HAS_at90usb1287, test "x$HAS_at90usb1287" = "xyes") # avr6 CHECK_AVR_DEVICE(avr6) AM_CONDITIONAL(HAS_avr6, test "x$HAS_avr6" = "xyes") CHECK_AVR_DEVICE(atmega2560) AM_CONDITIONAL(HAS_atmega2560, test "x$HAS_atmega2560" = "xyes") CHECK_AVR_DEVICE(atmega2561) AM_CONDITIONAL(HAS_atmega2561, test "x$HAS_atmega2561" = "xyes") # avrxmega2 CHECK_AVR_DEVICE(avrxmega2) AM_CONDITIONAL(HAS_avrxmega2, test "x$HAS_avrxmega2" = "xyes") CHECK_AVR_DEVICE(atxmega16a4) AM_CONDITIONAL(HAS_atxmega16a4, test "x$HAS_atxmega16a4" = "xyes") CHECK_AVR_DEVICE(atxmega16d4) AM_CONDITIONAL(HAS_atxmega16d4, test "x$HAS_atxmega16d4" = "xyes") CHECK_AVR_DEVICE(atxmega32a4) AM_CONDITIONAL(HAS_atxmega32a4, test "x$HAS_atxmega32a4" = "xyes") CHECK_AVR_DEVICE(atxmega32d4) AM_CONDITIONAL(HAS_atxmega32d4, test "x$HAS_atxmega32d4" = "xyes") # avrxmega4 CHECK_AVR_DEVICE(avrxmega4) AM_CONDITIONAL(HAS_avrxmega4, test "x$HAS_avrxmega4" = "xyes") CHECK_AVR_DEVICE(atxmega64a3) AM_CONDITIONAL(HAS_atxmega64a3, test "x$HAS_atxmega64a3" = "xyes") CHECK_AVR_DEVICE(atxmega64d3) AM_CONDITIONAL(HAS_atxmega64d3, test "x$HAS_atxmega64d3" = "xyes") # avrxmega5 CHECK_AVR_DEVICE(avrxmega5) AM_CONDITIONAL(HAS_avrxmega5, test "x$HAS_avrxmega5" = "xyes") CHECK_AVR_DEVICE(atxmega64a1) AM_CONDITIONAL(HAS_atxmega64a1, test "x$HAS_atxmega64a1" = "xyes") CHECK_AVR_DEVICE(atxmega64a1u) AM_CONDITIONAL(HAS_atxmega64a1u, test "x$HAS_atxmega64a1u" = "xyes") # avrxmega6 CHECK_AVR_DEVICE(avrxmega6) AM_CONDITIONAL(HAS_avrxmega6, test "x$HAS_avrxmega6" = "xyes") CHECK_AVR_DEVICE(atxmega128a3) AM_CONDITIONAL(HAS_atxmega128a3, test "x$HAS_atxmega128a3" = "xyes") CHECK_AVR_DEVICE(atxmega128d3) AM_CONDITIONAL(HAS_atxmega128d3, test "x$HAS_atxmega128d3" = "xyes") CHECK_AVR_DEVICE(atxmega192a3) AM_CONDITIONAL(HAS_atxmega192a3, test "x$HAS_atxmega192a3" = "xyes") CHECK_AVR_DEVICE(atxmega192d3) AM_CONDITIONAL(HAS_atxmega192d3, test "x$HAS_atxmega192d3" = "xyes") CHECK_AVR_DEVICE(atxmega256a3) AM_CONDITIONAL(HAS_atxmega256a3, test "x$HAS_atxmega256a3" = "xyes") CHECK_AVR_DEVICE(atxmega256a3b) AM_CONDITIONAL(HAS_atxmega256a3b, test "x$HAS_atxmega256a3b" = "xyes") CHECK_AVR_DEVICE(atxmega256d3) AM_CONDITIONAL(HAS_atxmega256d3, test "x$HAS_atxmega256d3" = "xyes") # avrxmega7 CHECK_AVR_DEVICE(avrxmega7) AM_CONDITIONAL(HAS_avrxmega7, test "x$HAS_avrxmega7" = "xyes") CHECK_AVR_DEVICE(atxmega128a1) AM_CONDITIONAL(HAS_atxmega128a1, test "x$HAS_atxmega128a1" = "xyes") CHECK_AVR_DEVICE(atxmega128a1u) AM_CONDITIONAL(HAS_atxmega128a1u, test "x$HAS_atxmega128a1u" = "xyes") # avrtiny10 CHECK_AVR_DEVICE(avrtiny10) AM_CONDITIONAL(HAS_avrtiny10, test "x$HAS_avrtiny10" = "xyes") CHECK_AVR_DEVICE(attiny4) AM_CONDITIONAL(HAS_attiny4, test "x$HAS_attiny4" = "xyes") CHECK_AVR_DEVICE(attiny5) AM_CONDITIONAL(HAS_attiny5, test "x$HAS_attiny5" = "xyes") CHECK_AVR_DEVICE(attiny9) AM_CONDITIONAL(HAS_attiny9, test "x$HAS_attiny9" = "xyes") CHECK_AVR_DEVICE(attiny10) AM_CONDITIONAL(HAS_attiny10, test "x$HAS_attiny10" = "xyes") CHECK_AVR_DEVICE(attiny20) AM_CONDITIONAL(HAS_attiny20, test "x$HAS_attiny20" = "xyes") CHECK_AVR_DEVICE(attiny40) AM_CONDITIONAL(HAS_attiny40, test "x$HAS_attiny40" = "xyes") # Generate all files from *.in sources. AC_CONFIG_FILES([ Makefile avr-libc.spec avr/Makefile avr/lib/Makefile common/Makefile crt1/Makefile doc/Makefile doc/api/Makefile doc/examples/Makefile include/Makefile include/avr/Makefile include/avr/builtins.h include/compat/Makefile include/util/Makefile include/util/delay.h libc/Makefile libc/misc/Makefile libc/pmstring/Makefile libc/stdio/Makefile libc/stdlib/Makefile libc/string/Makefile libm/Makefile libm/fplib/Makefile scripts/Makefile devtools/Makefile ]) #avr1 and avr2 AC_CONFIG_FILES([ avr/lib/avr2/Makefile avr/lib/avr2/at90s1200/Makefile avr/lib/avr2/at90s2313/Makefile avr/lib/avr2/at90s2323/Makefile avr/lib/avr2/at90s2333/Makefile avr/lib/avr2/at90s2343/Makefile avr/lib/avr2/at90s4414/Makefile avr/lib/avr2/at90s4433/Makefile avr/lib/avr2/at90s4434/Makefile avr/lib/avr2/at90s8515/Makefile avr/lib/avr2/at90c8534/Makefile avr/lib/avr2/at90s8535/Makefile avr/lib/avr2/attiny11/Makefile avr/lib/avr2/attiny12/Makefile avr/lib/avr2/attiny13/Makefile avr/lib/avr2/attiny15/Makefile avr/lib/avr2/attiny22/Makefile avr/lib/avr2/attiny24/Makefile avr/lib/avr2/attiny25/Makefile avr/lib/avr2/attiny26/Makefile avr/lib/avr2/attiny261/Makefile avr/lib/avr2/attiny28/Makefile avr/lib/avr2/attiny44/Makefile avr/lib/avr2/attiny45/Makefile avr/lib/avr2/attiny461/Makefile avr/lib/avr2/attiny84/Makefile avr/lib/avr2/attiny85/Makefile avr/lib/avr2/attiny861/Makefile avr/lib/avr2/attiny2313/Makefile avr/lib/avr2/at86rf401/Makefile ]) #avr25 AC_CONFIG_FILES([ avr/lib/avr25/Makefile avr/lib/avr25/at86rf401/Makefile avr/lib/avr25/ata6289/Makefile avr/lib/avr25/attiny13/Makefile avr/lib/avr25/attiny13a/Makefile avr/lib/avr25/attiny2313/Makefile avr/lib/avr25/attiny2313a/Makefile avr/lib/avr25/attiny24/Makefile avr/lib/avr25/attiny24a/Makefile avr/lib/avr25/attiny25/Makefile avr/lib/avr25/attiny261/Makefile avr/lib/avr25/attiny261a/Makefile avr/lib/avr25/attiny4313/Makefile avr/lib/avr25/attiny43u/Makefile avr/lib/avr25/attiny44/Makefile avr/lib/avr25/attiny44a/Makefile avr/lib/avr25/attiny45/Makefile avr/lib/avr25/attiny461/Makefile avr/lib/avr25/attiny461a/Makefile avr/lib/avr25/attiny48/Makefile avr/lib/avr25/attiny84/Makefile avr/lib/avr25/attiny84a/Makefile avr/lib/avr25/attiny85/Makefile avr/lib/avr25/attiny861/Makefile avr/lib/avr25/attiny861a/Makefile avr/lib/avr25/attiny87/Makefile avr/lib/avr25/attiny88/Makefile ]) #avr3 AC_CONFIG_FILES([ avr/lib/avr3/Makefile avr/lib/avr3/atmega103/Makefile avr/lib/avr3/at43usb320/Makefile avr/lib/avr3/at43usb355/Makefile avr/lib/avr3/at76c711/Makefile avr/lib/avr3/at90usb82/Makefile avr/lib/avr3/at90usb162/Makefile ]) #avr31 AC_CONFIG_FILES([ avr/lib/avr31/Makefile avr/lib/avr31/atmega103/Makefile avr/lib/avr31/at43usb320/Makefile ]) #avr35 AC_CONFIG_FILES([ avr/lib/avr35/Makefile avr/lib/avr35/at90usb82/Makefile avr/lib/avr35/at90usb162/Makefile avr/lib/avr35/atmega8u2/Makefile avr/lib/avr35/atmega16u2/Makefile avr/lib/avr35/atmega32u2/Makefile avr/lib/avr35/attiny167/Makefile ]) #avr4 AC_CONFIG_FILES([ avr/lib/avr4/Makefile avr/lib/avr4/atmega48/Makefile avr/lib/avr4/atmega48a/Makefile avr/lib/avr4/atmega48p/Makefile avr/lib/avr4/atmega8/Makefile avr/lib/avr4/atmega88/Makefile avr/lib/avr4/atmega88a/Makefile avr/lib/avr4/atmega88p/Makefile avr/lib/avr4/atmega88pa/Makefile avr/lib/avr4/atmega8515/Makefile avr/lib/avr4/atmega8535/Makefile avr/lib/avr4/atmega8hva/Makefile avr/lib/avr4/at90pwm1/Makefile avr/lib/avr4/at90pwm2/Makefile avr/lib/avr4/at90pwm2b/Makefile avr/lib/avr4/at90pwm3/Makefile avr/lib/avr4/at90pwm3b/Makefile avr/lib/avr4/at90pwm81/Makefile ]) #avr5 AC_CONFIG_FILES([ avr/lib/avr5/Makefile avr/lib/avr5/at90can32/Makefile avr/lib/avr5/at90can64/Makefile avr/lib/avr5/at90can128/Makefile avr/lib/avr5/at90pwm216/Makefile avr/lib/avr5/at90pwm316/Makefile avr/lib/avr5/at90scr100/Makefile avr/lib/avr5/at90usb646/Makefile avr/lib/avr5/at90usb647/Makefile avr/lib/avr5/at90usb1286/Makefile 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avr/lib/avr5/atmega325/Makefile avr/lib/avr5/atmega325a/Makefile avr/lib/avr5/atmega325p/Makefile avr/lib/avr5/atmega3250/Makefile avr/lib/avr5/atmega3250a/Makefile avr/lib/avr5/atmega3250p/Makefile avr/lib/avr5/atmega328/Makefile avr/lib/avr5/atmega328p/Makefile avr/lib/avr5/atmega329/Makefile avr/lib/avr5/atmega329a/Makefile avr/lib/avr5/atmega329p/Makefile avr/lib/avr5/atmega329pa/Makefile avr/lib/avr5/atmega3290/Makefile avr/lib/avr5/atmega3290a/Makefile avr/lib/avr5/atmega3290p/Makefile avr/lib/avr5/atmega32c1/Makefile avr/lib/avr5/atmega32hvb/Makefile avr/lib/avr5/atmega32hvbrevb/Makefile avr/lib/avr5/atmega32m1/Makefile avr/lib/avr5/atmega32u4/Makefile avr/lib/avr5/atmega32u6/Makefile avr/lib/avr5/atmega406/Makefile avr/lib/avr5/atmega64/Makefile avr/lib/avr5/atmega640/Makefile avr/lib/avr5/atmega644/Makefile avr/lib/avr5/atmega644a/Makefile avr/lib/avr5/atmega644p/Makefile avr/lib/avr5/atmega644pa/Makefile avr/lib/avr5/atmega645/Makefile avr/lib/avr5/atmega645a/Makefile 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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: frexp.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float frexp (float A, int *pexp); The frexp() function is used to split the number A into a normalized fraction and an exponent which is stored by pexp. Return: If A is a normal float point number, the frexp() function returns the value v, such that v has a magnitude in the interval [1/2, 1) or zero, and A equals v times 2 raised to the power *pexp. If A is zero, both parts of the result are zero. If A is not a finite number, the frexp() returns A as is and stores 0 by pexp. Note: This implementation permits a zero pointer as a directive to skip a storing the exponent. */ #define pexp_lo r20 ENTRY frexp X_movw ZL, pexp_lo ; Write 0 for next cases: Zero, Inf or NaN. #if defined(__AVR_XMEGA__) && __AVR_XMEGA__ adiw ZL, 0 breq 1f #endif st Z, r1 std Z+1, r1 1: rcall _U(__fp_splitA) brcs .L_nf ; return the same value tst rA3 breq 3f subi rA3, 126 sbc rB3, rB3 sbrs rA2, 7 rcall _U(__fp_norm2) #if defined(__AVR_XMEGA__) && __AVR_XMEGA__ adiw ZL, 0 breq 2f st Z, rA3 std Z+1, rB3 2: #else ; NULL is a legal address. Instead to check Z==0, will simply ; write and restore r1. st Z, rA3 std Z+1, rB3 clr r1 ; protection to Z == 0 #endif andi rA2, 0x7f ldi rA3, 0x3f 3: bld rA3, 7 ; restore sign ret .L_nf: rjmp _U(__fp_mpack) ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp_negdi.S0000644000000000000000000000402211732702554014766 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_negdi.S 1173 2007-01-14 15:04:40Z dmix $ */ /* long long __fp_negdi (long long x) Return negative value of x. Input/output: rA3.rA2.rA1.rA0.rB3.rB2.rB1.rB0 */ #include "fp32def.h" #include "asmdef.h" ENTRY __fp_negdi com rA3 com rA2 com rA1 com rA0 com rB3 com rB2 com rB1 neg rB0 sbci rB1, -1 sbci rB2, -1 sbci rB3, -1 sbci rA0, -1 sbci rA1, -1 sbci rA2, -1 sbci rA3, -1 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/cosh.S0000644000000000000000000000455611732702554014163 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: cosh.S 1174 2007-01-14 15:13:54Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* float cosh (float x); The cosh() function returns the hyperbolic cosine of x, which is defined mathematically as (exp(x) + exp(-x)) / 2. Notes: ldexp() is called twice to avoid overflow with too big x argument. */ #define exp_lo r20 #define exp_hi r21 ENTRY cosh ; A = exp(-fabs(x))/2 negative to exclude an extra inversion ori rA3, 0x80 rcall _U(exp) ldi exp_lo, lo8(-1) ldi exp_hi, hi8(-1) rcall _U(ldexp) ; save A and calculate exp(fabs(x))/2 push rA3 push rA2 push rA1 push rA0 ldi exp_lo, lo8(2) ldi exp_hi, hi8(2) rcall _U(ldexp) rcall _U(inverse) ; exp(x)/2 + exp(-x)/2 pop rB0 pop rB1 pop rB2 pop rB3 rjmp _U(__addsf3) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fp_powser.S0000644000000000000000000000560511732702554015227 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_powser.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* flt40_t __fp_powser (float x, ZH.ZL); The __fp_powser() function calculates the polynom. Input: rA3.rA2.rA1.rA0 - an 'x' arg ZH.ZL - table address (in low 64K flash memory) Output: rA3.rA2.rA1.rA0.rAE - result (is't rounded) Table format: ; example for 3 power: C0 + x*(C1 + x*(C2 + x*C3)) ; all floats are little-endian .byte 3 ; polynom power .byte C3,C3,C3,C3 ; flt32_t C3 .byte C2,C2,C2,C2,C2 ; flt40_t C2 .byte C1,C1,C1,C1,C1 ; flt40_t C1 .byte C0,C0,C0,C0,C0 ; flt40_t C0 */ #define rC3 r17 #define rC2 r16 #define rC1 r15 #define rC0 r14 #define rcntr r13 ENTRY __fp_powser push YH push YL push rC3 push rC2 push rC1 push rC0 push rcntr X_movw rC0, rA0 X_movw rC2, rA2 set ; as flag to return rjmp .Load5 1: mov rcntr, rBE .Loop: X_movw YL, ZL rcall _U(__mulsf3x) X_movw ZL, YL clt .Load5: X_lpm rBE, Z+ X_lpm rB0, Z+ X_lpm rB1, Z+ X_lpm rB2, Z+ X_lpm rB3, Z+ brts 1b X_movw YL, ZL rcall _U(__addsf3x) X_movw ZL, YL X_movw rB0, rC0 X_movw rB2, rC2 dec rcntr brne .Loop pop rcntr pop rC0 pop rC1 pop rC2 pop rC3 pop YL pop YH ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp_powsodd.S0000644000000000000000000000440111732702554015360 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_powsodd.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* float __fp_powsodd (float A, ZH.ZL); The __fp_powsodd() function calculates a polynom with only odd powers of x. Result is rounded. Input: rA3.rA2.rA1.rA0 - an 'x' arg ZH.ZL - table address (in flash low 64K memory) Notes: * As __fp_powsodd() is one of base function, square() is't used. */ ENTRY __fp_powsodd push rA3 push rA2 push rA1 push rA0 push ZH push ZL X_movw rB0, rA0 X_movw rB2, rA2 rcall _U(__mulsf3) pop ZL pop ZH rcall _U(__fp_powser) pop rB0 pop rB1 pop rB2 pop rB3 rjmp _U(__mulsf3) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fp_mintl.S0000644000000000000000000000561311732702554015032 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_mintl.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* float __fp_mintl (); Normalize value by shifting to left (only left) and merge parts of float value. Mainly, this function is intended for integral values, as a last stage of functions floor(), floatsisf(). Its functionality is very restricted: no subnormals, no rounding, no Inf/NaN. Input: T - sign rA3 - exponent rA2.rA1.rA0 - mantissa Output: rA3.rA2.rA1.rA0 - float value Notes: * Underflow of exponent is NOT checked: result would undefined. * In zero case mantissa must be 0. * Sign bit is set in any case. -0.0 is possible. * Shifts are optimized for speed. */ ENTRY __fp_mintl tst rA2 brne .L_bm tst rA1 breq 1f ; mantissa is 0x00XXXX subi rA3, 8 or rA2, rA1 ; to obtain N flag (rA2 was 0) mov rA1, rA0 rjmp .L_a0 ; mantissa is 0x0000XX 1: tst rA0 brne 2f clr rA3 rjmp .L_sign ; low mantissa byte != 0 2: subi rA3, 16 or rA2, rA0 ; to obtain N flag (rA2 was 0) ldi rA1, 0 .L_a0: ldi rA0, 0 .L_bm: brmi .L_pack ; N flag is from rA2 ; shift to left (1..7 positions) .Loop: dec rA3 lsl rA0 rol rA1 rol rA2 brpl .Loop .L_pack: lsl rA2 lsr rA3 ror rA2 .L_sign: bld rA3, 7 ; sign ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fp_norm2.S0000644000000000000000000000345511732702554014746 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_norm2.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" ENTRY __fp_norm2 1: subi rA3, lo8(1) sbci rB3, hi8(1) lsl rA0 rol rA1 rol rA2 brpl 1b ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/asin.S0000644000000000000000000000542711732702554014157 0ustar /* Copyright (c) 2002, Reiner Patommel Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: asin.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* float asin (float A); The asin() function returns the arc sine in radians and the value is mathematically defined to be between -PI/2 and PI/2 (inclusive). */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" #define X2SMALL 0x3e78ffff #define HI40_PI_2 0x3fc90fda /* high 4 bytes of Pi/2 */ #define LO40_PI_2 0xa2 /* lowest byte of Pi/2 */ ENTRY asin ; save A sign push rA3 ; A = fabs(A) andi rA3, 0x7f ; is A too small ? ldi ZL, hhi8(X2SMALL + 1) cpi rA2, hlo8(X2SMALL + 1) cpc rA3, ZL brsh 1f ; for small x ldi ZL, lo8 (.L_table) ldi ZH, hi8 (.L_table) rcall _U(__fp_powsodd) rjmp 2f ; arcsin(x) = Pi/2 - arccos(x) 1: rcall _U(__fp_arccos) subi rA3, 0x80 ldi rBE, LO40_PI_2 ldi rB0, lo8(HI40_PI_2) ldi rB1, hi8(HI40_PI_2) ldi rB2, hlo8(HI40_PI_2) ldi rB3, hhi8(HI40_PI_2) rcall _U(__addsf3x) rcall _U(__fp_round) ; restore sign 2: pop r0 sbrc r0, 7 subi rA3, 0x80 ret ENDFUNC PGM_SECTION .L_table: .byte 3 .byte 0x6e,0xdb,0x36,0x3d ; 15/336 .byte 0x9a,0x99,0x99,0x99,0x3d ; 3/40 .byte 0xab,0xaa,0xaa,0x2a,0x3e ; 1/6 .byte 0x00,0x00,0x00,0x80,0x3f ; 1 .end #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/sin.S0000644000000000000000000000372711732702554014017 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: sin.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float sin (float A); The sin() function returns the sine of A, where A is given in radians. */ ENTRY sin push rA3 rcall _U(__fp_rempio2) pop r0 sbrc r0, 7 subi ZL, -2 rjmp _U(__fp_sinus) ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/isfinite.S0000644000000000000000000000412111732702554015025 0ustar /* Copyright (c) 2002, Joerg Wunsch Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: isfinite.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* int isfinite (float x); The isfinite() function returns a nonzero value if x is finite: not plus or minus infinity, and not NaN. */ ENTRY isfinite /* It is not needed to return 1 if number is finite. Any nonzero value is suitable. This realization returns 0xff in low byte and nonzero value (1..255) in high byte. */ lsl rA2 rol rA3 ; rA3 = exponent subi rA3, 0xff ; C = 0, if rA3 was 0xff sbc rA2, rA2 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fp_pscB.S0000644000000000000000000000402511732702554014572 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_pscB.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* __fp_pscB (float_splited_t B); Post split classification. Return: C = 1, Z = 0 for NaN C = 0, Z = 1 for Inf C = 0, Z = 0 for finite number */ ENTRY __fp_pscB clr r0 dec r0 cp r1, rB0 cpc r1, rB1 cpc r1, rB2 cpc r0, rB3 ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fmax.S0000644000000000000000000000522311732702554014152 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fmax.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float fmax (float x, float y); The fmax() function returns the greater of the two values x and y. If an argument is NaN, the other argument is returned. If both arguments are NaN, NaN is returned. */ ENTRY fmax lsl rA3 sbc rAE, rAE ; rAE = (A < 0) ? -1 : 0 lsl rB3 sbc rBE, rBE ; rBE = (B < 0) ? -1 : 0 ; isnan(A) ? ldi ZL, 0x80 ; NaN: 0x{f/7}f800001..0x{f/7}fffffff ldi ZH, 0xfe cp r1, rA0 cpc r1, rA1 cpc ZL, rA2 cpc ZH, rA3 brlo .L_retB ; A is NaN ; isnan(B) ? cp r1, rB0 cpc r1, rB1 cpc ZL, rB2 cpc ZH, rB3 brlo .L_retA ; compare signs cp rAE, rBE brlt .L_retB ; A < 0, B >= 0 brne .L_retA ; A >= 0, B < 0 ; compare absolute values cp rA0, rB0 cpc rA1, rB1 cpc rA2, rB2 cpc rA3, rB3 ; C is set, if A < B ; analize ror rBE ; V = C ^ sign brvc .L_retA .L_retB: X_movw rA0, rB0 X_movw rA2, rB2 mov rAE, rBE .L_retA: lsr rAE ror rA3 ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp_trunc.S0000644000000000000000000000551711732702554015045 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_trunc.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* __fp_trunc (float A); This is an internal functions. __fp_trunc() splits argument and truncates to zero direction. It is intended as first part of work in floor(), ceil(), trunc() functions. Return: T - sign bit C - set if A is not finite (A is splited) rA3 - exponent: 0 - A is zero 1..126 - fabs(A) < 1 127.. - fabs(A) >= 1 rA2.rA1.rA0 - mantissa (with hidden bit) rAE - flag of nonzero fraction Notes: * Return value is not a float value. Function, like __fp_mpack(), is needed to merge a float. * In case of 'fabs(A) < 1' rA2.rA1.rA0 and rAE are random. */ ENTRY __fp_trunc rcall _U(__fp_splitA) brcs 9f ; A is finite ldi rAE, 126 cp rAE, rA3 brsh 9f ; fabs (A) >= 1.0 clr rAE 3: cpi rA3, 127+23-7 brsh 5f ; shift by 1..7 positions or no shift ; quick shift by 8 cp r1, rA0 adc rAE, r1 mov rA0, rA1 mov rA1, rA2 clr rA2 subi rA3, -8 rjmp 3b ; slow shift 4: lsr rA2 ror rA1 ror rA0 adc rAE, r1 inc rA3 5: cpi rA3, 127+23 brlo 4b 9: ret ; C == 0 ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/cbrt.S0000644000000000000000000001427211732702554014155 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: cbrt.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* double cbrt (double) Cube root function. */ #define RCNT r25 #define RA0 r22 #define RA1 r23 #define RA2 r24 #define RM0 r26 #define RM1 r27 #define RM2 r28 #define RM3 r29 #define RM4 RA0 #define RM5 RA1 #define RM6 RA2 #define RY0 r30 #define RY1 r31 #define RY2 r15 #define RQ0 r16 #define RQ1 r17 #define RQ2 r18 #define RQ3 r19 #define RQ4 r8 #define RQ5 r9 #define RD0 r20 #define RD1 r21 #define RD2 r10 #define RD3 r11 #define RD4 r12 #define RD5 r13 #define RD6 r14 #define REM RD0 FUNCTION cbrt /* Division by 3. Input: rA3 - arg Output: rA3 - quotient REM - remainder RY0 - zero (was counter) Scratch: r0 */ #if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ .Ldiv3: mov REM, rA3 ; save ldi RY0, 85 inc rA3 mul rA3, RY0 mov rA3, r1 ; quotient (((rA3 + 1) * 85) / 256) ldi RY0, 3 mul RY0, rA3 ; r1 := 0, as the result is less than 256 sub REM, r0 ; remainder clr RY0 ; API ret #else .Ldiv3: sub REM, REM ; clear remainder and carry ldi RY0, 8 ; loop counter rol rA3 1: rol REM cpi REM, 3 brlo 2f subi REM, 3 2: rol rA3 dec RY0 brne 1b com rA3 ; because C flag was complemented in loop ret #endif 0: rjmp _U(__fp_mpack) ENTRY cbrt ; split and check arg. rcall _U(__fp_splitA) brcs 0b ; !isfinite(A) tst rA3 breq 0b ; return 0 with original sign ; save registers .irp .L_reg, r29,r28,r17,r16,r15,r14,r13,r12,r11,r10,r9,r8 push \.L_reg .endr /* Calculate exponent. */ subi rA3, 127 ; bias brsh 5f ; exponent was < 0 neg rA3 ; normalize, if A is subnormal tst rA2 brmi 2f 1: inc rA3 ; increment absolute value of negative exponent lsl rA0 rol rA1 rol rA2 brpl 1b ; division 2: rcall .Ldiv3 ; reverse remainder dec REM brmi 4f ; remainder was 0 brne 3f ; REM: 2 --> 1 subi REM, -2 ; REM: 1 --> 2 3: inc rA3 ; correct quotient ; restore sign of exponent 4: neg rA3 rjmp 6f ; exponent was >= 0 5: rcall .Ldiv3 ; save result exponent 6: subi rA3, lo8(-127) push rA3 ; clear clr RY1 ; RY0 == 0 after .Ldiv3 function clr RY2 X_movw RQ0, RY0 X_movw RQ2, RY0 X_movw RQ4, RY0 X_movw RM0, RY0 X_movw RM2, RY0 ; shift mantissa by 1..3 positions 7: lsl RA0 rol RA1 rol RA2 rol RM0 dec REM brpl 7b /* -------------------------------------------------------------------- Register usage: RCNT RA0..RA2 RM0..RM2 RY0 RQ0..RQ1 RD0..RD2 Free registers for temporary values: RD4..RD6 */ ldi RCNT, 8 .Loop1: ; RQ <<= 2 lsl RQ0 rol RQ1 lsl RQ0 rol RQ1 ; RY <<= 1 lsl RY0 ; RD = RY + RQ X_movw RD0, RQ0 clr RD2 add RD0, RY0 adc RD1, r1 adc RD2, r1 ; save RD X_movw RD4, RD0 mov RD6, RD2 ; RD <<= 1 lsl RD0 rol RD1 rol RD2 ; RD += RY + RQ add RD0, RD4 adc RD1, RD5 adc RD2, RD6 ; RD |= 1 ori RD0, 1 ; RM -= RD sub RM0, RD0 sbc RM1, RD1 sbc RM2, RD2 brsh 11f ; restore RM add RM0, RD0 adc RM1, RD1 adc RM2, RD2 rjmp 12f ; RQ += RY << 1 11: X_movw RD0, RY0 lsl RD0 rol RD1 add RQ0, RD0 adc RQ1, RD1 ; RQ |= 1 ori RQ0, 1 ; RY |= 1 ori RY0, 1 ; RM = (RM << 3) <-- (RA << 3) 12: ldi RD0, 3 13: lsl RA0 rol RA1 rol RA2 rol RM0 rol RM1 rol RM2 dec RD0 brne 13b ; ... while (--RCNT) dec RCNT brne .Loop1 /* -------------------------------------------------------------------- */ ldi RCNT, 16 .Loop2: ; RQ <<= 2 20: lsl RQ0 rol RQ1 rol RQ2 rol RQ3 rol RQ4 rol RQ5 com r1 brne 20b ; RY <<= 1 lsl RY0 rol RY1 rol RY2 ; RD = 0 clr r0 X_movw RD0, r0 X_movw RD2, r0 X_movw RD4, r0 clr RD6 ; RD += RQ 21: add RD0, RQ0 adc RD1, RQ1 adc RD2, RQ2 adc RD3, RQ3 adc RD4, RQ4 adc RD5, RQ5 adc RD6, r1 ; RD += RY add RD0, RY0 adc RD1, RY1 adc RD2, RY2 adc RD3, r1 adc RD4, r1 adc RD5, r1 adc RD6, r1 ; com r0 breq 22f ; RD <<= 1 lsl RD0 rol RD1 rol RD2 rol RD3 rol RD4 rol RD5 rol RD6 rjmp 21b ; RM -= RD 22: sub RM0, RD0 sbc RM1, RD1 sbc RM2, RD2 sbc RM3, RD3 sbc RM4, RD4 sbc RM5, RD5 sbc RM6, RD6 brsh 23f ; restore RM add RM0, RD0 adc RM1, RD1 adc RM2, RD2 adc RM3, RD3 adc RM4, RD4 adc RM5, RD5 adc RM6, RD6 rjmp 24f ; RQ += 2*RY 23: add RQ0, RY0 adc RQ1, RY1 adc RQ2, RY2 adc RQ3, r1 adc RQ4, r1 adc RQ5, r1 com r0 brne 23b ; RQ |= 1 ori RQ0, 1 ; RY |= 1 ori RY0, 1 ; RM <<= 3 24: ldi RD0, 3 25: lsl RM0 rol RM1 rol RM2 rol RM3 rol RM4 rol RM5 rol RM6 dec RD0 brne 25b dec RCNT breq 26f rjmp .Loop2 ; make result 26: X_movw rA0, RY0 mov rA2, RY2 pop rA3 lsl rA2 lsr rA3 ror rA2 bld rA3, 7 ; sign ; restore registers and return .irp .L_reg, r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,r28,r29 pop \.L_reg .endr ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/lround.S0000644000000000000000000000723511732702554014527 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: lround.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* long lround (double A); The lround() function rounds A to the nearest integer, but rounds halfway cases away from zero (instead of to the nearest even integer). This function is similar to round() function, but it differs in type of return value and in that an overflow is possible. Return: The rounded long integer value. If A is infinite, NaN or an overflow was, this realization returns the LONG_MIN value (0x80000000). Algorithm roughly: - split - shift mantissa according to exponent - add 0.5 to round - restore the sign Objections to saturation are listen in __fixunssfsi.S file. */ ENTRY lround rcall _U(__fp_splitA) brcs .L_err ; A is finite subi rA3, 126 ; exponent field of 0.5 brlo .L_zr ; A is too small ; fabs(A) >= 0x0.800000p+00 subi rA3, 24 brlo 2f ; shtft to right and round breq .L_sign ; no shift ; fabs(A) >= 0x0.800000p+25 cpi rA3, 8 brsh .L_err ; A is too big ; 0x0.800000p+25 <= fabs(A) <= 0x0.ffffffp+31 --> shift to left by 1..7 mov r0, rA3 ; shift counter clr rA3 ; MSB ; rA3.2.1.0 <<= r0 1: lsl rA0 rol rA1 rol rA2 rol rA3 dec r0 brne 1b rjmp .L_sign ; quick shift to right by 8 5: mov r0, rA0 ; save for possible round mov rA0, rA1 mov rA1, rA2 clr rA2 subi rA3, -8 brne 2f lsl r0 ; restore C rjmp 4f ; and round ; 0x0.800000p+00 <= fabs(A) <= 0x0.ffffffp+23 ; Shift A to right by 1 (rA3 == -1) .. 24 (rA3 == -24) positions and ; round. 2: cpi rA3, -7 brlt 5b ; shift to right by 1..7 (slow) 3: lsr rA2 ror rA1 ror rA0 ; --> C inc rA3 ; C is not changed brne 3b ; Round. Now flag C is set if fractional is >= 0.5 4: adc rA0, r1 adc rA1, r1 adc rA2, r1 ; rA2 was <= 0x7f, so rA3 will not changed ; restore the sign and return .L_sign: brtc 6f com rA3 com rA2 com rA1 neg rA0 sbci rA1, -1 sbci rA2, -1 sbci rA3, -1 6: ret .L_err: set ; force return 0x80000000 rjmp _U(__fp_szero) .L_zr: rjmp _U(__fp_zero) ; return 0x00000000 ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/inverse.S0000644000000000000000000000372211732702554014674 0ustar /* Copyright (c) 2005 Anatoly Sokolov Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: inverse.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* float inverse (float A); The inverse() function returns 1/A value. */ #define FL_1 0x3f800000 /* +1.0 */ ENTRY inverse X_movw rB0, rA0 X_movw rB2, rA2 ; B = A ldi rA0, lo8(FL_1) ldi rA1, hi8(FL_1) ldi rA2, hlo8(FL_1) ldi rA3, hhi8(FL_1) rjmp _U(__divsf3) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fixunssfsi.S0000644000000000000000000001004011732702554015411 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fixunssfsi.S 1487 2007-12-01 02:12:55Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* unsigned long __fixunssfsi (float A); The __fixunssfsi() function converts A to the integer value. No rounding, the fractional is losted. The compiler calls this function to perform a cast operation from float (i.e. double) to unsigned long. No saturation. Negative input is permissable (like GCC/x86). Besides a normal 32-bits value __fixunssfsi() returns the extra error flag in a call-scratched register. This is used when a caller is the __fixsfsi() function. Return: rA3.rA2.rA1.rA0 - 32-bits integer rAE - flag of error (NaN, overflow or A is too big for signed conversion) if (!isnan(A) && fabs(A) <= 0x0.ffffffp+31) return [A < 0 ? -(long)(-A) : (long)A, OK_FLAG] if (!isnan(A) && fabs(A) <= 0x0.ffffffp+32) return [A < 0 ? -(unsigned long)(-A) : (unsigned long)A, ERR_FLAG] if (isnan(A) || fabs(A) >= 0x0.800000p+33) return [0, ERR_FLAG] Why no saturation? - GCC on Intel's x86 does not do it - with saturation it will be more difficult to check result - if cast is to 'int' (16 bits for AVR) then saturation is unusefull - in practice saturation is needed with user's desirable limits Algorithm roughly: - split - shift mantissa according to exponent - restore the sign */ ENTRY __fixunssfsi rcall _U(__fp_splitA) brcs .L_err ; A is finite subi rA3, 127 ; exponent field of 1.0 brlo .L_zr ; fabs(A) >= 1.0 mov rAE, rA3 clr rA3 subi rAE, 23 brlo 4f ; shift to right breq .L_sign ; no shift ; fabs(A) >= 0x0.800000p+25 To reduce code size we will not check ; number of shifts. Instead we will check a MSB of result. 1: lsl rA0 rol rA1 rol rA2 rol rA3 brmi 2f ; next shift is impossible: data lost dec rAE brne 1b rjmp .L_sign 2: cpi rAE, 1 breq .L_sign ; rAE: overflow for 'signed long' usage .L_err: rcall _U(__fp_zero) ldi rAE, 1 ; error flag ret .L_zr: rjmp _U(__fp_zero) ; return 0x00000000, clear rAE ; fabs(A) <= 0x0.ffffffp+23 ; Shift A to right by 1 (rA3==-1) .. 23 (rA3==-23) positions. 3: mov rA0, rA1 mov rA1, rA2 clr rA2 subi rAE, -8 breq .L_sign 4: cpi rAE, -7 brlt 3b ; quick shift is possible 5: lsr rA2 ror rA1 ror rA0 inc rAE brne 5b ; restore the sign and return .L_sign: brtc 6f com rA3 com rA2 com rA1 neg rA0 sbci rA1, -1 sbci rA2, -1 sbci rA3, -1 6: ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fmin.S0000644000000000000000000000522211732702554014147 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fmin.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float fmin (float x, float y); The fmin() function returns the lesser of the two values x and y. If an argument is NaN, the other argument is returned. If both arguments are NaN, NaN is returned. */ ENTRY fmin lsl rA3 sbc rAE, rAE ; rAE = (A < 0) ? -1 : 0 lsl rB3 sbc rBE, rBE ; rBE = (B < 0) ? -1 : 0 ; isnan(A) ? ldi ZL, 0x80 ; NaN: 0x{f/7}f800001..0x{f/7}fffffff ldi ZH, 0xfe cp r1, rA0 cpc r1, rA1 cpc ZL, rA2 cpc ZH, rA3 brlo .L_retB ; A is NaN ; isnan(B) ? cp r1, rB0 cpc r1, rB1 cpc ZL, rB2 cpc ZH, rB3 brlo .L_retA ; compare signs cp rAE, rBE brlt .L_retA ; A < 0, B >= 0 brne .L_retB ; A >= 0, B < 0 ; compare absolute values cp rB0, rA0 cpc rB1, rA1 cpc rB2, rA2 cpc rB3, rA3 ; C is set, if B < A ; analize ror rBE ; V = C ^ sign brvc .L_retA .L_retB: X_movw rA0, rB0 X_movw rA2, rB2 mov rAE, rBE .L_retA: lsr rAE ror rA3 ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp_inf.S0000644000000000000000000000365111732702554014463 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_inf.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* __fp_inf() return Inf value. Input: T - sign of result Return: rA3.rA2.rA1.rA0 - Inf value with sign */ ENTRY __fp_inf bld rA3, 7 ; sign ori rA3, 0x7f ldi rA2, 0x80 ldi rA1, 0 ldi rA0, 0 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/pow.S0000644000000000000000000001203611732702554014024 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: pow.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float pow (float x, float y); The pow() function returns the value of x raised to the power of y. Args combinations: x y pow(x,y) -------------------------------- +0 NaN NaN exp(log(x)*y) +0 +0,-0 +1 +0 +Inf +0 exp(log(x)*y) +0 -Inf +Inf exp(log(x)*y) +0 y > 0 +0 exp(log(x)*y) +0 y < 0 +Inf exp(log(x)*y) -0 NaN NaN exp(log(x)*y) -0 +0,-0 +1 -0 1,3,5... -0 -exp(log(x)*y) -0 y > 0 +0 exp(log(x)*y) -0 -1,-3,-5... -Inf -exp(log(x)*y) -0 y < 0 +Inf exp(log(x)*y) +1 NaN +1 +1 +Inf,-Inf +1 +1 else +1 exp(log(x)*y) -1 +0,-0 +1 -1 1,3,5... -1 -1 -1,-3,-5... -1 -1 2,4,6... +1 -1 -2,-4,-6... +1 -1 else NaN exp(log(x)*y) +Inf NaN NaN exp(log(x)*y) +Inf +0,-0 +1 +Inf y > 0 +Inf exp(log(x)*y) +Inf y < 0 +0 exp(log(x)*y) -Inf NaN NaN exp(log(x)*y) -Inf +0,-0 +1 -Inf 1,3,5... -Inf -Inf y > 0 +Inf -Inf -1,-3,-5... -0 -Inf y < 0 +0 NaN +0,-0 +1 NaN else NaN exp(log(x)*y) (0,1) NaN NaN exp(log(x)*y) (0,1) +0,-0 +1 exp(log(x)*y) (0,1) +Inf +0 exp(log(x)*y) (0,1) -Inf +Inf exp(log(x)*y) (-1,0) NaN NaN (-1,0) +0,-0 +1 (-1,0) +Inf +0 (-1,0) -Inf +Inf (-1,0) nonintegral NaN x > 1 NaN NaN x > 1 +0,-0 +1 x > 1 +Inf +Inf x > 1 -Inf +0 x < -1 NaN NaN x < -1 +0,-0 +1 x < -1 +Inf +Inf x < -1 -Inf +0 x < -1 nonintegral NaN */ #define FL_1 0x3f800000 /* +1.0 */ ENTRY pow ; ZH := exponent of y X_movw ZL, rB2 lsl ZL rol ZH ; y == 0 ? adiw ZL, 0 cpc rB0, r1 cpc rB1, r1 breq .L_one ; preliminary check cp rA0, r1 cpc rA1, r1 brne 0f ; skip a bit of comparisons ; x == 1.0 ? cpi rA2, hlo8(FL_1) ldi rAE, hhi8(FL_1) cpc rA3, rAE breq .L_ret ; x == -0.0 ? set ; flag: nonintegral y is a legal value cpi rA3, 0x80 cpc rA2, r1 breq .L_int ; x == -Inf ? cpi rA2, 0x80 ldi rAE, 0xff cpc rA3, rAE breq .L_int ; x >= 0 ? 0: tst rA3 brpl .L_pow ; isinf(y) ? cpi ZH, 0xff cpc ZL, r1 cpc rB1, r1 cpc rB0, r1 breq .L_big ; isintegral(y) ? clt ; nonintegral y is not a legal value .L_int: /* Now we have: y is nonzero value ZL == (rB2 << 1) ZH == exponenta, ZH <= 254 */ sec ; hidden bit ror ZL ; This is incorrect for subnormals, no sense: ; result would NaN. ; ffs(). Next two loops are finite due to above 'sec'. X_movw XL, rB0 ; Byte search loop. 1: tst XL brne 2f mov XL, XH mov XH, ZL subi ZH, -8 brcs 1b rjmp .L_noint ; mantisa too big ; Bit search loop. 2: subi ZH, -1 brcc .L_noint ; mantisa too big lsr XL brcc 2b ; Check exponent, is y an integral value? /* Example: 1.0 == 0x3f800000: exponent: ZH := 0x7f byte search: ZH += 2*8 --> 0x8f bit search: ZH += 8 --> 0x97 */ cpi ZH, 0x97 brlo .L_noint breq 3f ; y % 2 == 1 cpi ZH, 0x97 + 24 brsh .L_noint andi rA3, 0x7f ; y is integral, y % 2 == 0 3: push rA3 rcall .L_pow pop r0 sbrc r0, 7 subi rA3, 0x80 .L_ret: ret ; y is not an integral number .L_noint: brts .L_pow .L_nan: rjmp _U(__fp_nan) .L_one: ldi rA0, lo8(FL_1) ldi rA1, hi8(FL_1) ldi rA2, hlo8(FL_1) ldi rA3, hhi8(FL_1) ret ; replace Inf --> big finite (to exclude '0 * Inf' for legal x == -1) .L_big: ldi rB2, 0x7f .L_pow: andi rA3, 0x7f push rB3 push rB2 push rB1 push rB0 rcall _U(log) pop rB0 pop rB1 pop rB2 pop rB3 rcall _U(__mulsf3) rjmp _U(exp) ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/square.S0000644000000000000000000000354711732702554014526 0ustar /* Copyright (c) 2005 Anatoly Sokolov Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: square.S 2166 2010-06-13 13:14:47Z joerg_wunsch $ */ #include "fp32def.h" #include "asmdef.h" /* float square (float A); The square() function returns square of A. */ ENTRY square X_movw rB0, rA0 X_movw rB2, rA2 ; B = A rjmp _U(__mulsf3) ; A * B ENDFUNC avr-libc-1.8.0.orig/libm/fplib/Makefile.in0000644000000000000000000003305011732702554015137 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) 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@host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ libm_a_c_sources = libm_a_asm_sources = \ acos.S \ addsf3.S \ addsf3x.S \ asin.S \ atan2.S \ atan.S \ cbrt.S \ ceil.S \ cmpsf2.S \ copysign.S \ cosh.S \ cos.S \ divsf3.S \ divsf3x.S \ exp.S \ fixsfdi.S \ fixsfsi.S \ fixunssfsi.S \ floatdisf.S \ floatsisf.S \ floatundisf.S \ fdim.S \ floor.S \ fma.S \ fmax.S \ fmin.S \ fmod.S \ fp_arccos.S \ fp_cmp.S \ fp_inf.S \ fp_mintl.S \ fp_mpack.S \ fp_nan.S \ fp_negdi.S \ fp_norm2.S \ fp_powser.S \ fp_powsodd.S \ fp_pscA.S \ fp_pscB.S \ fp_rempio2.S \ fp_round.S \ fp_sinus.S \ fp_split3.S \ fp_trunc.S \ fp_zero.S \ frexp.S \ gesf2.S \ hypot.S \ inverse.S \ isfinite.S \ isinf.S \ isnan.S \ ldexp.S \ log10.S \ log.S \ lrint.S \ lround.S \ modf.S \ mulsf3.S \ mulsf3x.S \ negsf2.S \ pow.S \ round.S \ signbit.S \ sinh.S \ sin.S \ sqrt.S \ square.S \ tanh.S \ tan.S \ trunc.S \ unordsf2.S libm_a_extra_dist = \ asmdef.h \ fp32def.h \ ntz.h EXTRA_DIST = \ $(libm_a_asm_sources) \ $(libm_a_extra_dist) all: all-am .SUFFIXES: $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libm/fplib/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign libm/fplib/Makefile'; \ $(am__cd) $(top_srcdir) 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info-am: install-data-am: install-dvi: install-dvi-am install-dvi-am: install-exec-am: install-html: install-html-am install-html-am: install-info: install-info-am install-info-am: install-man: install-pdf: install-pdf-am install-pdf-am: install-ps: install-ps-am install-ps-am: installcheck-am: maintainer-clean: maintainer-clean-am -rm -f Makefile maintainer-clean-am: distclean-am maintainer-clean-generic mostlyclean: mostlyclean-am mostlyclean-am: mostlyclean-generic pdf: pdf-am pdf-am: ps: ps-am ps-am: uninstall-am: .MAKE: install-am install-strip .PHONY: all all-am check check-am clean clean-generic distclean \ distclean-generic distdir dvi dvi-am html html-am info info-am \ install install-am install-data install-data-am install-dvi \ install-dvi-am install-exec install-exec-am install-html \ install-html-am install-info install-info-am install-man \ install-pdf install-pdf-am install-ps install-ps-am \ install-strip installcheck installcheck-am installdirs \ maintainer-clean maintainer-clean-generic mostlyclean \ mostlyclean-generic pdf pdf-am ps ps-am uninstall uninstall-am # vim: set ft=make: # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: avr-libc-1.8.0.orig/libm/fplib/acos.S0000644000000000000000000000450011732702554014141 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: acos.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* float acos (float x); The acos() function calculates the arc cosine of x; that is the value whose cosine is x. */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" #define HI40_PI 0x40490FDA /* Pi */ #define LO40_PI 0xA2 ENTRY acos ; save A sign push rA3 ; A = arccos(fabs(A)) andi rA3, 0x7f rcall _U(__fp_arccos) ; check sign pop r0 tst r0 brpl 1f ; for negative x: arccos(x) = Pi - arccos(-x) subi rA3, 0x80 ldi rBE, LO40_PI ldi rB0, lo8(HI40_PI) ldi rB1, hi8(HI40_PI) ldi rB2, hlo8(HI40_PI) ldi rB3, hhi8(HI40_PI) rcall _U(__addsf3x) ; round 1: rjmp _U(__fp_round) ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fixsfdi.S0000644000000000000000000001142311732702554014652 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fixsfdi.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* long long __fixsfdi (float x); The __fixsfdi() function converts a float argument x into signed 8-bytes value. If x is nonintegral, then it is rounded down to the nearest integer. If absolute value of x is too big (fabs(x) >= 2**63, or NaN, the value 2**63 is returned. This is similar to Gcc+Glibc in 'float --> long' conversion case. */ ENTRY __fixsfdi ldi rAE, 62 rcall .L_sf2di brcc 1f ldi rA3, 0x80 1: ret /* unsigned long long __fixunssfdi (float x); The __fixunssfdi() function converts a float argument x into unsigned 8-bytes value. If x is nonintegral, then it is rounded down to the nearest integer. If absolute value of x is too big (fabs(x) >= 2**64, or NaN, the 0 is returned. For negative x (if fabs(x) < 2**64, result is corresponded to signed conversion (with possible overflow). This is similar to Gcc+Glibc in 'float --> unsigned long' conversion case. Examples: __fixunssfdi(-1.0) --> 0xff..ffLL __fixunssfdi(0x0.ffffffp+63) --> 0x7fffff8000000000LL __fixunssfdi(-0x0.ffffffp+63) --> 0x0000008000000000LL __fixunssfdi(0x1.000002p+63) --> 0x8000010000000000LL __fixunssfdi(0x1.fffffep+63) --> 0xffffff0000000000LL __fixunssfdi(0x1.000000p+64) --> 0LL Note: Gcc+Glibc give the strange results for negative x in such convers. */ ENTRY __fixunssfdi ldi rAE, 63 /* The .L_sf2di() function converts a float value into 8-bytes integer. Input: rA3.rA2.rA1.rA0 - float input rAE - max power of input: must 62 for signed result and 63 for unsigned result Output: rA3..rA0.rB3..rB0 - long long output, 0 if overflow was flag C - set if overflow Note: C is set and 0 return in case of: - x too large: fabs(x) >= 2**(rAE+1), - x is +/- Inf - x is NaN */ .L_sf2di: ; clear LSBytes clr rB0 clr rB1 X_movw rB2, rB0 ; split rcall _U(__fp_splitA) brcs .L_ovfl ; is not finite subi rA3, 127 ; 1.0 exponent field brlo .L_zero ; too small cp rAE, rA3 brlo .L_ovfl ; fabs(A) >= 2**64 (or 2**63) ldi rAE, 63 sub rAE, rA3 /* Now rAE is, for example: 63 - exponent was 127+0, shift >>55 is needed, 0 - exponent was 127+63, shift <<8 is needed. */ clr rA3 subi rAE, 8 ; rAE= -8..+55 brpl 3f ; fabs(A) >= 1.0 * 2**56 Shift to left is needed. /* Shift to 8 is not optimized specialy as an exotic. */ 2: lsl rA0 rol rA1 rol rA2 rol rA3 inc rAE brmi 2b rjmp .L_sign ; Shift to right is needed 3: /* Now rAE: 55 - exponent was 127+0, shift >>55 is needed, 1 - exponent was 127+54, shift >>1 is needed, 0 - exponent was 127+55, no shift is needed. */ subi rAE, 8 brmi 5f ; quick shift by 8 4: mov rB0, rB1 mov rB1, rB2 mov rB2, rB3 mov rB3, rA0 mov rA0, rA1 mov rA1, rA2 clr rA2 subi rAE, 8 brpl 4b 5: subi rAE, -8 ; rAE = 0..7 breq .L_sign ; shift to 1..7 positions 6: lsr rA2 ror rA1 ror rA0 ror rB3 ror rB2 ror rB1 ror rB0 dec rAE brne 6b .L_sign: brtc 7f rcall _U(__fp_negdi) 7: clc ret .L_zero: clc .L_ovfl: ; overflow, C is set already ldi rA0, 0 ldi rA1, 0 X_movw rA2, rA0 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fp_arccos.S0000644000000000000000000000676111732702554015166 0ustar /* Copyright (c) 2002, Reiner Patommel Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_arccos.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* flt40_t __fp_arccos (float x); This is an Arccos internal function. Arg must: 0 <= x <= 1. */ #define FL_1 0x3f800000 /* +1.0 */ #define HI40_PI_2 0x3fc90fda /* high 4 bytes of Pi/2 */ #define LO40_PI_2 0xa2 /* lowest byte of Pi/2 */ #define rC0 r16 #define rC1 r17 #define rC2 YL #define rC3 YH ENTRY __fp_arccos #if defined(__AVR_HAVE_MOVW__) && __AVR_HAVE_MOVW__ ; push push rC3 push rC2 push rC1 push rC0 ; calculate: sqrt(1-A), (C0 + A*(C1 + ...)) movw rC0, rA0 movw rC2, rA2 ldi ZL, lo8(.L_table) ldi ZH, hi8(.L_table) rcall _U(__fp_powser) rcall _U(__fp_round) movw rB0, rC0 movw rB2, rC2 movw rC0, rA0 movw rC2, rA2 ldi rA0, lo8(FL_1) ldi rA1, hi8(FL_1) ldi rA2, hlo8(FL_1) ldi rA3, hhi8(FL_1) rcall _U(__subsf3) rcall _U(sqrt) movw rB0, rC0 movw rB2, rC2 ; restore and multiply pop rC0 pop rC1 pop rC2 pop rC3 rjmp _U(__mulsf3x) #else /* to __AVR_HAVE_MOVW__ */ ; save A push rA3 push rA2 push rA1 push rA0 ; calculate: C0 + A*(C1 + ...) ldi ZL, lo8(.L_table) ldi ZH, hi8(.L_table) rcall _U(__fp_powser) rcall _U(__fp_round) ; restore A pop rB0 pop rB1 pop rB2 pop rB3 ; save calculation result push rA3 push rA2 push rA1 push rA0 ; sqrt(1-A) ldi rA0, lo8(FL_1) ldi rA1, hi8(FL_1) ldi rA2, hlo8(FL_1) ldi rA3, hhi8(FL_1) rcall _U(__subsf3) rcall _U(sqrt) ; multiply pop rB0 pop rB1 pop rB2 pop rB3 rjmp _U(__mulsf3x) #endif ENDFUNC PGM_SECTION .L_table: .byte 7 .byte 0x2c,0x7a,0xa5,0xba ; -0.0012624911 .byte 0x6c,0xc5,0x90,0xda,0x3b ; 0.0066700901 .byte 0x93,0x65,0xfc,0x8b,0xbc ; -0.0170881256 .byte 0x53,0xf8,0x10,0xfd,0x3c ; 0.0308918810 .byte 0x56,0x92,0x83,0x4d,0xbd ; -0.0501743046 .byte 0x87,0x9d,0x3a,0xb6,0x3d ; 0.0889789874 .byte 0xcb,0xc9,0xbf,0x5b,0xbe ; -0.2145988016 .byte 0x73,0xda,0x0f,0xc9,0x3f ; 1.5707963050 .end avr-libc-1.8.0.orig/libm/fplib/cmpsf2.S0000644000000000000000000000445411732702554014416 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2008 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: cmpsf2.S 1652 2008-03-22 04:04:43Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* GCC expects all these functions to return -1/0/1 as for __cmpsf2 - compare with gcc/config/fp-bit.c (the only difference is with NaNs where we should always return nonzero for EQ/NE, -1 for GT/GE, 1 for LT/LE). -MM 2000-11-18 */ #define ret_lo r24 /* return value (signed byte) */ .ifnc ret_lo, rA2 ; This is used in __fp_cmp() function. .err .endif /* Return value: if (A < B) -1 elif (A == B) 0 else // A > B || isnan(A) || isnan(B) 1 */ ENTRY __cmpsf2 ENTRY __eqsf2 ENTRY __nesf2 ENTRY __ltsf2 ENTRY __lesf2 rcall _U(__fp_cmp) brcc 1f ldi ret_lo, 1 1: ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/gesf2.S0000644000000000000000000000443111732702554014225 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2008 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: gesf2.S 1652 2008-03-22 04:04:43Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* GCC expects all these functions to return -1/0/1 as for __cmpsf2 - compare with gcc/config/fp-bit.c (the only difference is with NaNs where we should always return nonzero for EQ/NE, -1 for GT/GE, 1 for LT/LE). -MM 2000-11-18 */ #define ret_lo r24 /* return value (signed byte) */ .ifnc ret_lo, rA2 ; This is used in __fp_cmp() function. .err .endif /* Return value (ret_lo): if (A > B) 1 elif (A == B) 0 else // A < B || isnan(A) || isnan(B) -1 */ ENTRY __gesf2 ENTRY __gtsf2 rcall _U(__fp_cmp) brcc 1f ldi ret_lo, -1 1: ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fp_rempio2.S0000644000000000000000000000765111732702554015270 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov Copyright (c) 2008 Ruud v Gessel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_rempio2.S 1810 2008-12-02 13:34:42Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* __fp_rempio2 (float x); The __fp_rempio2() function computes the remainder of dividing absolute value of x by Pi/2. The return value is x - n*Pi/2, where n is the quotient of abs(x)/(Pi/2), rounded towards zero to an integer. Output: rA3.rA2.rA1.rA0.rAE - flt40_t remainder ZL - low byte of n */ #define HI40_PIO2 0x3FC90FDA /* (flt40_t) Pi/2 */ #define LO40_PIO2 0xA2 FUNCTION __fp_rempio2 0: rjmp _U(__fp_nan) ENTRY __fp_rempio2 ; split and check finite rcall _U(__fp_splitA) brcs 0b ; only finite numbers are valid clt ; ignore a sign ; init division result ldi ZL, 0 ; extend A clr rAE ; check (and modify) exponent subi rA3, hhi8(HI40_PIO2 << 1) brlo 5f ; fabs(A) < 1.0 radian, C is set ; prepare loop ldi rB0, lo8(HI40_PIO2) ldi rB1, hi8(HI40_PIO2) ldi rB2, hlo8(HI40_PIO2 | 0x800000) ; + hidden bit rjmp 1f .Loop: lsl ZL lsl rAE rol rA0 rol rA1 rol rA2 brcs 2f 1: cpi rAE, lo8(LO40_PIO2) cpc rA0, rB0 cpc rA1, rB1 cpc rA2, rB2 brlo 3f 2: subi rAE, lo8(LO40_PIO2) sbc rA0, rB0 sbc rA1, rB1 sbc rA2, rB2 inc ZL 3: dec rA3 brpl .Loop ; Normalize, we know that rA2.1.0.E >= 0x0E. You can check this with ; a test program below. cpi rA2,0x80 brcc 5f 4: dec rA3 lsl rAE rol rA0 rol rA1 rol rA2 ; C := 0 brpl 4b 5: sbci rA3, hhi8((HI40_PIO2<<1) + 0x01000000) ; undo the subi 0x7f rjmp _U(__fp_mpack_finite) ENDFUNC #if 0 /* This is a test program to find the smallest value of rA2.1.0.E after division. The nonzero value gives a garanty that normalization loop is finite. */ #include #define MNT32_PIO2 0xC90FDAA2 int main () { unsigned long rA210; unsigned long rA210E; int rA3; unsigned long c; unsigned long amin = 0xffffffff; for (rA210 = 0x800000; rA210 <= 0xffffff; rA210 += 1) { rA210E = rA210 << 8; c = 0; rA3 = 127; /* this is max for finite number */ goto m; do { c = rA210E & 0x80000000; rA210E <<= 1; m: if (c || (rA210E >= MNT32_PIO2)) rA210E -= MNT32_PIO2; if (rA210E < amin) { amin = rA210E; printf ("min of rA210E: 0x%08lx\r", amin); fflush (stdout); } } while (--rA3 >= 0); } putchar ('\n'); return 0; } #endif avr-libc-1.8.0.orig/libm/fplib/hypot.S0000644000000000000000000001326411732702554014366 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: hypot.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" #include "ntz.h" /* double hypot (double x, double y); The hypot() function returns `sqrt (x*x + y*y)'. This is the length of the hypotenuse of a right triangle with sides of length x and y, or the distance of the point (x, y) from the origin. Using this function instead of the direct formula is wise, since the error is much smaller. No underflow with small x and y. No overflow if result is in range. Notes: * Combination of NaN and Inf args is valid (like Glibc). Result: Inf. */ #define EDIFF_2BIG 13 /* such exponents difference is too big */ /* Next 2 constants are without 127-displacement. */ #define EXP_2BIG 63 /* exponent is too big, scaling needed */ #define EXP_2SMALL (-63) /* exponent is too small, scaling need. */ /* Next 2 values are positive both. SCALE_BIG is increased by 1 to provide '-SCALE_SMALL & SCALE_BIG': this is used below. */ #define SCALE_BIG (126 - EXP_2BIG + 2) #define SCALE_SMALL (149 + EXP_2SMALL + 1) /* Assert: no overlap */ #if EXP_2BIG - SCALE_BIG - (EDIFF_2BIG - 1) <= EXP_2SMALL \ || EXP_2SMALL + SCALE_SMALL + (EDIFF_2BIG - 1) >= EXP_2BIG # error #endif #define exp_lo r20 /* ldexp (float x, int exp); */ #define exp_hi r21 #define rC0 r14 #define rC1 r15 #define rC2 r16 #define rC3 r17 FUNCTION hypot .L_nf: rcall _U(__fp_pscA) breq 1f ; hypot(Inf, *) --> Inf rcall _U(__fp_pscB) breq 1f ; hypot(*, Inf) --> Inf rjmp _U(__fp_nan) ; NaN and finite, or both NaN 1: rjmp _U(__fp_inf) ; T is 0 after __fp_split3() .L_retB: X_movw rA0, rB0 X_movw rA2, rB2 .L_retA: rjmp _U(__fp_mpack) ENTRY hypot ; clear signs andi rA3, 0x7f andi rB3, 0x7f ; split and check args rcall _U(__fp_split3) brcs .L_nf tst rA3 breq .L_retB tst rB3 breq .L_retA ; sort exponents clr ZH ; scale factor cp rA3, rB3 brsh 3f ; exponent A < exponent B ; is an A too small ? mov ZL, rB3 sub ZL, rA3 cpi ZL, EDIFF_2BIG brsh .L_retB ; the A is too small ; is it needed to decrease scale ? cpi rB3, 127 + EXP_2BIG brlo 2f ldi ZH, SCALE_BIG ; positive for 'sub' instruction rjmp .L_scale ; is it needed to increase scale ? 2: cpi rA3, 127 + EXP_2SMALL brsh .L_sc0 rjmp .L_right ; exponent A >= exponent B ; is B too small? 3: mov ZL, rA3 sub ZL, rB3 cpi ZL, EDIFF_2BIG brsh .L_retA ; is it needed to decrease scale ? cpi rA3, 127 + EXP_2BIG brlo 4f ldi ZH, SCALE_BIG ; positive for 'sub' instruction rjmp .L_scale ; is it needed to increase scale ? 4: cpi rB3, 127 + EXP_2SMALL brsh .L_sc0 .L_right: ; 'shift to right' entry ldi ZH, -(SCALE_SMALL) ; normalize A, if needed tst rA2 brmi 6f 5: dec rA3 lsl rA0 rol rA1 rol rA2 brpl 5b ; normalize B, if needed 6: tst rB2 brmi 8f 7: dec rB3 lsl rB0 rol rB1 rol rB2 brpl 7b 8: ; scale and save the scale factor .L_scale: sub rA3, ZH sub rB3, ZH .L_sc0: ; `scale is 0' entry push ZH ; calculate sqrt(A*A + B*B) #if defined(__AVR_HAVE_MOVW__) && __AVR_HAVE_MOVW__ push rC3 push rC2 push rC1 push rC0 movw rC0, rB0 movw rC2, rB2 clr rAE mov rBE, rAE movw rB0, rA0 movw rB2, rA2 rcall _U(__mulsf3_pse) movw rB0, rC0 movw rB2, rC2 push rAE movw rC0, rA0 movw rC2, rA2 clr rBE mov rAE, rBE movw rA0, rB0 movw rA2, rB2 rcall _U(__mulsf3_pse) pop rBE movw rB0, rC0 movw rB2, rC2 pop rC0 pop rC1 pop rC2 pop rC3 #else /* to __AVR_HAVE_MOVW__ */ push rB3 push rB2 push rB1 push rB0 clr rAE mov rBE, rAE mov rB0, rA0 mov rB1, rA1 mov rB2, rA2 mov rB3, rA3 rcall _U(__mulsf3_pse) pop rB0 pop rB1 pop rB2 pop rB3 push rA3 push rA2 push rA1 push rA0 push rAE clr rBE mov rAE, rBE mov rA0, rB0 mov rA1, rB1 mov rA2, rB2 mov rA3, rB3 rcall _U(__mulsf3_pse) pop rBE pop rB0 pop rB1 pop rB2 pop rB3 #endif /* ! __AVR_HAVE_MOVW__ */ rcall _U(__addsf3x) rcall _U(__fp_round) rcall _U(sqrt) ; restore a scale #if (-SCALE_SMALL & SCALE_BIG) == 0 # error #endif pop exp_lo sbrs exp_lo, ntz(-SCALE_SMALL & SCALE_BIG) ret ; scale == 0 clr exp_hi sbrc exp_lo, 7 com exp_hi rjmp _U(ldexp) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/tanh.S0000644000000000000000000000643611732702554014160 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: tanh.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float tanh (float x); The tanh() function returns the hyperbolic tangent of x, which is defined mathematically as sinh(x) / cosh(x). Algorithm: if (fabs(x) <= X2SMALL) return Polinom(x) else return sign(x) * (1 - exp(-2*fabs(x))) / (1 + exp(-2*fabs(x))) */ #define X2SMALL 0x3e0fffff /* < 0.140625 */ #define FL_P1 0x3f800000 /* +1.0 */ #define exp_lo r20 /* float ldexp (float, int exp); */ #define exp_hi r21 ENTRY tanh ; save sign push rA3 ; is arg too small ? andi rA3, 0x7f ldi ZH, hhi8 (X2SMALL + 1) cpi rA2, hlo8 (X2SMALL + 1) cpc rA3, ZH brsh 1f ; for small x ldi ZL, lo8(.L_table) ldi ZH, hi8(.L_table) rcall _U(__fp_powsodd) rjmp 2f ; exp(-2*fabs(x)) 1: ori rA3, 0x80 ldi exp_lo, lo8(1) ldi exp_hi, hi8(1) rcall _U(ldexp) ; possible overflow -- no matter rcall _U(exp) ; save result and calculate 1 + exp(-2*fabs(x)) push rA3 push rA2 push rA1 push rA0 ldi rB0, lo8(FL_P1) ldi rB1, hi8(FL_P1) ldi rB2, hlo8(FL_P1) ldi rB3, hhi8(FL_P1) rcall _U(__addsf3) ; save/restore and calculate 1 - exp(-2*fabs(x)) pop rB0 pop rB1 pop rB2 pop rB3 push rA3 push rA2 push rA1 push rA0 ldi rA0, lo8(FL_P1) ldi rA1, hi8(FL_P1) ldi rA2, hlo8(FL_P1) ldi rA3, hhi8(FL_P1) rcall _U(__subsf3) ; restore pop rB0 pop rB1 pop rB2 pop rB3 ; divide rcall _U(__divsf3) ; sign 2: pop r0 sbrc r0, 7 subi rA3, 0x80 ret ENDFUNC PGM_SECTION .L_table: .byte 2 .byte 0x89,0x88,0x08,0x3e ; 2/15 .byte 0xab,0xaa,0xaa,0xaa,0xbe ; -1/3 .byte 0x00,0x00,0x00,0x80,0x3f ; 1 .end #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/Files.am0000644000000000000000000000503411732702554014454 0ustar # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # libm_a_c_sources = libm_a_asm_sources = \ acos.S \ addsf3.S \ addsf3x.S \ asin.S \ atan2.S \ atan.S \ cbrt.S \ ceil.S \ cmpsf2.S \ copysign.S \ cosh.S \ cos.S \ divsf3.S \ divsf3x.S \ exp.S \ fixsfdi.S \ fixsfsi.S \ fixunssfsi.S \ floatdisf.S \ floatsisf.S \ floatundisf.S \ fdim.S \ floor.S \ fma.S \ fmax.S \ fmin.S \ fmod.S \ fp_arccos.S \ fp_cmp.S \ fp_inf.S \ fp_mintl.S \ fp_mpack.S \ fp_nan.S \ fp_negdi.S \ fp_norm2.S \ fp_powser.S \ fp_powsodd.S \ fp_pscA.S \ fp_pscB.S \ fp_rempio2.S \ fp_round.S \ fp_sinus.S \ fp_split3.S \ fp_trunc.S \ fp_zero.S \ frexp.S \ gesf2.S \ hypot.S \ inverse.S \ isfinite.S \ isinf.S \ isnan.S \ ldexp.S \ log10.S \ log.S \ lrint.S \ lround.S \ modf.S \ mulsf3.S \ mulsf3x.S \ negsf2.S \ pow.S \ round.S \ signbit.S \ sinh.S \ sin.S \ sqrt.S \ square.S \ tanh.S \ tan.S \ trunc.S \ unordsf2.S libm_a_extra_dist = \ asmdef.h \ fp32def.h \ ntz.h # vim: set ft=make: avr-libc-1.8.0.orig/libm/fplib/signbit.S0000644000000000000000000000425611732702554014663 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: signbit.S 1491 2007-12-02 02:36:57Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* int signbit (double x); The signbit() function returns a nonzero value if the value of x has its sign bit set. This is not the same as `x < 0.0', because IEEE 754 floating point allows zero to be signed. The comparison `-0.0 < 0.0' is false, but `signbit (-0.0)' will return a nonzero value. This implementation returns 1 if sign bit is set. This corresponds to builtin GCC realization. */ ENTRY signbit lsl rA3 sbc rA2, rA2 neg rA2 clr rA3 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/ceil.S0000644000000000000000000000500511732702554014131 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ceil.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* double ceil (double x); The ceil() function rounds x up to the nearest integer. Examples: ceil(1.9) --> 2.0 ceil(-1.9) --> -1.0 */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" #define FL_P1 0x3f800000 /* +1.0 */ ENTRY ceil rcall _U(__fp_trunc) brcs .L_nf ; A is finite cpi rA3, 127 brsh 2f ; fabs(A) < 1.0 cpse rA3, r1 brtc 1f rjmp _U(__fp_szero) ; ceil(-0.0) is -0.0 ; 0.0 < A < 1.0 --> +1.0 1: ldi rA0, lo8(FL_P1) ldi rA1, hi8(FL_P1) ldi rA2, hlo8(FL_P1) ldi rA3, hhi8(FL_P1) ret ; positive values are rounded into +Inf direction 2: brts 3f ; if negative cp r1, rAE ; C = 1 if fraction != 0 adc rA0, r1 adc rA1, r1 adc rA2, r1 ; rA2 was < 0x80, overflow is impossible 3: rjmp _U(__fp_mintl) .L_nf: rjmp _U(__fp_mpack) ; pass nonfinite arg as is ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/lrint.S0000644000000000000000000000770011732702554014351 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: lrint.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* long lrint (double A); The lrint() function rounds A to the nearest integer, rounding the halfway cases to the even integer direction. (That is both 1.5 and 2.5 values are rounded to 2). This function is similar to rint() function, but it differs in type of return value and in that an overflow is possible. Return: The rounded long integer value. If A is not a finite number or an overflow was, this realization returns the LONG_MIN value (0x80000000). Algorithm roughly: - split - shift mantissa according to exponent - round (if shift was to right) - restore the sign */ ENTRY lrint rcall _U(__fp_splitA) brcs .L_err ; A is finite subi rA3, 126 ; exponent field of 0.5 brlo .L_zr ; A is too small ; fabs(A) >= 0x0.800000p+00 subi rA3, 24 brlo .L_right ; shtft to right and round breq .L_sign ; no shift ; fabs(A) >= 0x0.800000p+25 cpi rA3, 8 brsh .L_err ; fabs(A) is too big ; 0x0.800000p+25 <= fabs(A) <= 0x0.ffffffp+31 --> shift to left by 1..7 mov r0, rA3 ; shift counter clr rA3 ; MSB ; rA3.2.1.0 <<= r0 1: lsl rA0 rol rA1 rol rA2 rol rA3 dec r0 brne 1b rjmp .L_sign ; 0x0.800000p+00 <= fabs(A) <= 0x0.ffffffp+23 ; Shift A to right by 1 (rA3 == -1) .. 24 (rA3 == -24) positions and ; round. .L_right: clr rAE ; accumulator for lower bits 2: cpi rA3, -7 brge 3f ; Quick shift to right by 8. The trick with rAE is needed to save info ; about the lowerest bits. This will be used to compare fraction with ; 0.5 value. cpse rAE, r1 ldi rAE, 1 or rAE, rA0 mov rA0, rA1 mov rA1, rA2 clr rA2 subi rA3, -8 brne 2b rjmp .L_round ; shift to right by 1..7 (slow) 3: lsr rA2 ror rA1 ror rA0 ror rAE brcc 4f ori rAE, 1 ; save flag that lowerst bits are not all 0 4: inc rA3 brne 3b ; round .L_round: lsl rAE brcc .L_sign ; fraction < 0.5 brne 7f ; fraction > 0.5 sbrs rA0, 0 rjmp .L_sign ; fraction == 0.5 and value is even 7: subi rA0, -1 sbci rA1, -1 sbci rA2, -1 ; rA2 was <= 0x7f, so rA3 will not changed ; restore the sign and return .L_sign: brtc 6f com rA3 com rA2 com rA1 neg rA0 sbci rA1, -1 sbci rA2, -1 sbci rA3, -1 6: ret .L_err: set ; force return 0x80000000 rjmp _U(__fp_szero) .L_zr: rjmp _U(__fp_zero) ; return 0x00000000 ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/addsf3x.S0000644000000000000000000000733511732702554014561 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: addsf3x.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* __addsf3x (float_40 A, float_40 B); Internal function to add float point numbers. Input: rA3.rA2.rA1.rA0.rAE - arg. A rB3.rB2.rB1.rB0.rBE - arg. B Output: T rA3 rA2.rA1.rA0.rAE.ZH */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" FUNCTION __addsf3x 0: rcall _U(__fp_pscA) brcs .L_nan rcall _U(__fp_pscB) brcs .L_nan brne .L_inf ; B is finite --> return A cpi rA3, 255 brne .L_infB ; A is finite --> return B brtc .L_inf ; Inf + Inf with the same sign .L_nan: rjmp _U(__fp_nan) .L_infB: brtc .L_inf com ZL .L_inf: bst ZL, 7 rjmp _U(__fp_inf) ENTRY __addsf3x mov ZL, rA3 ; save sign of A rcall _U(__fp_split3) brcs 0b ; compare A and B cp rAE, rBE cpc rA0, rB0 cpc rA1, rB1 cpc rA2, rB2 cpc rA3, rB3 brlo 2f ; fabs(A) < fabs(B) brne 4f ; fabs(A) > fabs(B) brtc .L_add rjmp _U(__fp_zero) ; A + (-A) = +0.0 ; swap A and B 2: brtc 3f com ZL ; update sign 3: mov r0, rAE mov rAE, rBE mov rBE, r0 #if defined(__AVR_HAVE_MOVW__) && __AVR_HAVE_MOVW__ movw r0, rA0 movw rA0, rB0 movw rB0, r0 movw r0, rA2 movw rA2, rB2 movw rB2, r0 clr r1 #else mov r0, rA0 mov rA0, rB0 mov rB0, r0 mov r0, rA1 mov rA1, rB1 mov rB1, r0 mov r0, rA2 mov rA2, rB2 mov rB2, r0 mov r0, rA3 mov rA3, rB3 mov rB3, r0 #endif ; 4: clr ZH sub rB3, rA3 5: breq 7f ; shift is not needed cpi rB3, -7 brsh 6f cpi rB3, -32 brlo .L_ret cp r1, rBE sbci ZH, 0 mov rBE, rB0 mov rB0, rB1 mov rB1, rB2 clr rB2 subi rB3, -8 rjmp 5b 6: lsr rB2 ror rB1 ror rB0 ror rBE sbci ZH, 0 inc rB3 brne 6b 7: ; direction ? brtc .L_add ; A -= B cp r1, ZH sbc rAE, rBE sbc rA0, rB0 sbc rA1, rB1 sbc rA2, rB2 brmi .L_ret 8: subi rA3, 1 breq 9f lsl ZH rol rAE rol rA0 rol rA1 rol rA2 brpl 8b rjmp .L_ret .L_add: add rAE, rBE adc rA0, rB0 adc rA1, rB1 adc rA2, rB2 brcc .L_ret ror rA2 ror rA1 ror rA0 ror rAE ror ZH cpi rA3, 254 brlo 9f rjmp .L_inf 9: inc rA3 .L_ret: lsl rA2 brcs 1f clr rA3 1: lsl ZL ; sign ror rA3 ror rA2 ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp_split3.S0000644000000000000000000000662611732702554015132 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_split3.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* __fp_split3 (float A, float B); It splits two float numbers. Return: rA3, rA2.rA1.rA0 - exponent and mantissa of A (see __fp_splitA) rB3, rB2.rB1.rB0 - exponent and mantissa of B (see __fp_splitA) Flags: C = 0 - both numbers are finite C = 1 - A and/or B is Inf/NaN T = sign(A) ^ sign(B) Notes: * Flag is different sense vs __fp_splitA() * All other registers are not changed. */ ENTRY __fp_split3 ; rA3[7] := sign(A) ^ sign(B) sbrc rB3, 7 subi rA3, 0x80 ; split B lsl rB2 rol rB3 ; exponent breq 4f cpi rB3, 0xff ; C = 1, if rB3 != 0xff breq 5f 1: ror rB2 ; restore rB2 and (possible) hidden bit /* __fp_splitA (float A); It splits an A float number. Return: rA3 - exponent: 0 for +0.0/-0.0 1..254 for finite number 255 for Inf/NaN rA2.rA1.rA0 - mantissa: 0 for +0.0/-0.0 0x000001..0x7fffff for subnormal (and rA3 = 1) 0x800000..0xffffff for normal (rA3 = 1..254) 0x000000 for Inf 0x000001..0x7fffff for NaN Flags: C = 0 for finite number C = 1, Z = 1 for Inf C = 1, Z = 0 for NaN T = sign Notes: * Other registers are not scratched. */ ENTRY __fp_splitA lsl rA2 2: bst rA3, 7 rol rA3 breq 6f cpi rA3, 0xff breq 7f 3: ror rA2 ret ; B is zero or subnormal 4: cp r1, rB0 cpc r1, rB1 cpc r1, rB2 ; C = 1, if B is not a zero rol rB3 ; C = 0 rjmp 1b ; B is not a finite 5: lsr rB2 rcall __fp_splitA rjmp 8f ; A is zero or subnormal 6: cp r1, rA0 cpc r1, rA1 cpc r1, rA2 rol rA3 rjmp 3b ; A is not a finite 7: lsr rA2 ; C = 0 cpc rA1, r1 cpc rA0, r1 8: sec ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp_nan.S0000644000000000000000000000345711732702554014467 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_nan.S 1174 2007-01-14 15:13:54Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* __fp_nan() return NaN value: 0xffc0XXXX */ ENTRY __fp_nan ldi rA3, 0xFF ldi rA2, 0xC0 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/log10.S0000644000000000000000000000375511732702554014151 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: log10.S 1174 2007-01-14 15:13:54Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* double log (double A); The log10() function returns the base 10 logarithm of A. */ #define INV_LN_10 0x3ede5bd9 /* 1.0/log(10.0) */ ENTRY log10 rcall _U(log) ldi rB0, lo8(INV_LN_10) ldi rB1, hi8(INV_LN_10) ldi rB2, hlo8(INV_LN_10) ldi rB3, hhi8(INV_LN_10) rjmp _U(__mulsf3) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/modf.S0000644000000000000000000000642411732702554014150 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006,2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: modf.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* double modf (double x, double *iptr); The modf() function breaks the argument x into an integral part and a fractional part, each of which has the same sign as x. The integral part is stored in iptr. This implementation skips writing by zero pointer. */ #define iptr_lo r20 ENTRY modf ENTRY modff ; save iptr X_movw ZL, iptr_lo ; XH = exponent field X_movw XL, rA2 lsl XL rol XH ; B = A X_movw rB0, rA0 X_movw rB2, rA2 ; Is there an integral part? subi XH, 127 ; exp of 1.0 brsh 1f ; fabs(x) < 1.0: *iptr = copysign(0, x), return x clr rB0 clr rB1 clr rB2 andi rB3, 0x80 rjmp .L_write ; Is there a fraction part? 1: subi XH, 23 brsh 4f ; no fraction part ; check fraction: B >>= 23 - (exp-127) mov XL, XH ; Now XH is -23..-1 clr r0 ; to control, is the fraction zero? 2: lsr rB2 ror rB1 ror rB0 adc r0, r1 inc XL brmi 2b tst r0 breq .L_nfrc ; fraction == 0 ; restore and clear fraction: B <<= 23 - (exp-127) 3: lsl rB0 rol rB1 rol rB2 inc XH brmi 3b ; write B rcall .L_write ; return nonzero fraction: A - B rjmp _U(__subsf3) ; exponent too big: compare with smallest NaN (0x7f800001) 4: cpi rA0, 1 cpc rA1, r1 ldi XL, 0x80 cpc rA2, XL sbci XH, 128 - 23 brsh .L_write ; NaN: write and return as is ; fraction == 0 .L_nfrc: X_movw rB0, rA0 X_movw rB2, rA2 ; A = 0.0 with sign clr rA0 clr rA1 clr rA2 andi rA3, 0x80 .L_write: adiw ZL, 0 ; skip writing with NULL pointer breq 1f st Z, rB0 std Z+1, rB1 std Z+2, rB2 std Z+3, rB3 1: ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/cos.S0000644000000000000000000000356611732702554014013 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: cos.S 1174 2007-01-14 15:13:54Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* float cos (float A); The cos() function returns the cosine of A, where A is given in radians. */ ENTRY cos rcall _U(__fp_rempio2) inc ZL rjmp _U(__fp_sinus) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fp_zero.S0000644000000000000000000000357211732702554014670 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_zero.S 1174 2007-01-14 15:13:54Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* __fp_zero() return 0.0 __fp_szero() return 0.0 with sign bit. */ ENTRY __fp_zero clt ENTRY __fp_szero clr rAE clr rA0 clr rA1 X_movw rA2, rA0 bld rA3, 7 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fp_cmp.S0000644000000000000000000000642011732702554014463 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006,2008 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_cmp.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* GCC expects all these functions to return -1/0/1 as for __cmpsf2 - compare with gcc/config/fp-bit.c (the only difference is with NaNs where we should always return nonzero for EQ/NE, -1 for GT/GE, 1 for LT/LE). -MM 2000-11-18 */ #define ret_lo r24 /* return value (signed byte) */ .ifnc ret_lo, rA2 ; This is used in __fp_cmp() function. .err .endif /* The base compare function. Return: if (A < B) rA2 = -1, C = 0 elif (A == B) rA2 = 0, C = 0 elif (A > B) rA2 = 1, C = 0 else // isnan(A) || isnan(B) C = 1 */ ENTRY __fp_cmp lsl rA3 sbc r0, r0 ; r0 = (A < 0) ? -1 : 0 lsl rB3 sbc rBE, rBE ; rBE = (B < 0) ? -1 : 0 ; isnan(A) ? ldi ZL, 0x80 ; NaN: 0x{f/7}f800001..0x{f/7}fffffff ldi ZH, 0xfe cp r1, rA0 cpc r1, rA1 cpc ZL, rA2 cpc ZH, rA3 brlo 9f ; branch, if C == 1 ; isnan(B) ? cp r1, rB0 cpc r1, rB1 cpc ZL, rB2 cpc ZH, rB3 brlo 9f ; branch, if C == 1 ; compare sub rA0, rB0 sbc rA1, rB1 sbc rA2, rB2 sbc rA3, rB3 ; C is set, if A < B brne 1f ; absolute values are equal, check signs eor r0, rBE breq 9f ; if branch, rA2 = 0, C = 0 ; force -0.0 == +0.0 or rB0, rB1 or rB0, rB2 or rB0, rB3 brne 2f ; evaluate sign(B) ret ; view argument signes 1: eor r0, rBE ; C is not changed brne 2f ; signs are different sbci rBE, 1 ; rBE[0] = (A < B && A > 0) ? 0 : 1 2: lsr rBE ; C = above result OR sign(B) ; build return value, C is set, if A > B ldi rA2, -1 adc rA2, r1 adc rA2, r1 ; C = 0 at any case 9: ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/sqrt.S0000644000000000000000000001251611732702554014213 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov Copyright (c) 2008 Ruud v Gessel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* double sqrt (double); Square root function. */ FUNCTION sqrt .L_nf: brne .L_pk ; NaN, return as is brtc .L_pk ; sqrt(+Inf) --> +Inf .L_nan: rjmp _U(__fp_nan) .L_pk: rjmp _U(__fp_mpack) ENTRY sqrt ; split and check arg. rcall _U(__fp_splitA) brcs .L_nf ; !isfinite(A) tst rA3 breq .L_pk ; return 0 with original sign brts .L_nan ; sqrt(negative) --> NaN ; exponent bias subi rA3, 127 sbc rB3, rB3 ; exponent high byte ; normalize, if A is subnormal sbrs rA2, 7 rcall _U(__fp_norm2) #define msk0 r0 #define msk1 r1 #define msk2 rBE clr msk0 ; msk1=R1 already 0 ldi msk2, 0x60 ; Initial rotation mask = ; 01100000.00000000.00000000 ldi rB2, 0xa0 X_movw rB0, msk0 ; Initial developing root = ; 10100000.00000000.00000000 /* TODO: Now the Avr-libs does not have an infrastructure to build and *test automaticaly* with both OPTIMIZE_SPEED definitions. So the one variant is enabled today only. */ #if 1 /* defined(OPTIMIZE_SPEED) && OPTIMIZE_SPEED */ ;** Optimized for speed (9 code words larger than size optimized, ; 67 less cycles in average) subi rA2, 0x80 lsr rB3 ror rA3 ; Divide exponent by 2, C==>exponent was odd brcc 1f ; Jump for even exponent in argument subi rA2, lo8(-0x40) ; Initial remainder for odd exponent. ; Loop for upper 23 bits .Loop: lsl rA0 rol rA1 rol rA2 ; Shift left remainder argument brcs 2f ; C --> Bit is always 1 (rA * 2 gave C) 1: cp rB0, rA0 cpc rB1, rA1 cpc rB2, rA2 ; Does test value fit? brcc 3f ; NC --> nope, bit is 0 2: sub rA0, rB0 sbc rA1, rB1 sbc rA2, rB2 ; Prepare remainder argument for next bits or rB0, msk0 or rB1, msk1 or rB2, msk2 ; Set developing bit to 1 3: lsr msk2 ror msk1 ror msk0 ; Shift right mask, C --> end loop eor rB0, msk0 eor rB1, msk1 eor rB2, msk2 ; Shift right test bit in developing root brcc .Loop ; Develop 23 bits of the sqrt ; Loop for bit 0 and rounding .Loop1: lsl rA0 rol rA1 rol rA2 ; Shift left remainder argument brcs 4f ; C--> Last bits always 1 cp rB0, rA0 cpc rB1, rA1 cpc rB2, rA2 ; Test for last bit 1 brcc 5f ; Nope, stays the same 4: sbc rA0, rB0 ; MUST BE SBC !! sbc rA1, rB1 sbc rA2, rB2 ; Prepare remainder argument for next bit add rB0, msk0 adc rB1, msk1 adc rB2, msk1 ; Add 1 to result 5: com msk2 ; ZF if second time brne .Loop1 ; 1 for last bit, 1 for rounding #else /* vs. to OPTIMIZE_SPEED */ ;** Optimized for size (9 code words smaller than speed optimized, ; 67 more cycles in average) #define tv rAE clr tv ; Test value for end of loop subi rA2, 0x40 ; Initial remainder for odd exponent lsr rB3 ror rA3 ; Divide exponent by 2, C==>exponent was odd brcs 3f ; Jump for odd exponent in argument subi rA2, 0x40 ; Initial remainder for even exponent, C=0 ; Loop for all 24 bits .Loop: brcc 2f ; NC --> nope, bit is 0 cp msk2, tv ; Only needed to get the proper rounding ; for ffffff sbc rA0, rB0 sbc rA1, rB1 sbc rA2, rB2 ; Prepare remainder argument for next bits or rB0, msk0 or rB1, msk1 or rB2, msk2 ; Set developing bit to 1 2: lsr msk2 ror msk1 ror msk0 ; Shift right mask, C --> end loop rol tv ; Bit 1 set if end of loop eor rB0, msk0 eor rB1, msk1 eor rB2, msk2 ; Shift right test bit in developing root 3: lsl rA0 rol rA1 rol rA2 ; Shift left remainder argument (C used ; at .Loop) brcs 4f cp rB0, rA0 cpc rB1, rA1 cpc rB2, rA2 4: sbrs tv, 1 rjmp .Loop ; Rounding adc rB0, msk1 adc rB1, msk1 adc rB2, msk1 ; Rounded mantissa ready (msk1=0) #endif /* !OPTIMIZE_SPEED */ X_movw rA0, rB0 mov rA2, rB2 ; Copy to rA subi rA3, lo8(-127) ; exponent bias lsl rA2 lsr rA3 ror rA2 ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/Rules.am0000644000000000000000000000323611732702554014506 0ustar # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ include $(top_srcdir)/libm/fplib/Files.am # vim: set ft=make: avr-libc-1.8.0.orig/libm/fplib/atan2.S0000644000000000000000000001042711732702554014226 0ustar /* Copyright (c) 2002, Reiner Patommel Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: atan2.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* float atan2 (float A, float B); // A is y coord, B is x coord. The atan2() function calculates the arc tangent of the two variables A and B. It is similar to calculating the arc tangent of A/B, except that the signs of both arguments are used to determine the quadrant of the result. The atan2() function returns the result in radians, which is between -PI and PI (inclusive). Note: This implementation returns +0.0 in all four cases: +0/+0, +0/-0, -0/+0 and -0/-0. Unlike x86 (GCC/Glibc). Algorithm: if (x == 0 && y == 0) // A is y, B is x return 0 if (x >= 0 && fabs(y) <= x) return atan(y/x) // -Pi/4 .. +Pi/4 if (y >= 0 && fabs(x) <= y) return Pi/2 - atan(x/y) // +Pi/4 .. +3*Pi/4 if (y <= 0 && fabs(x) <= fabs(y)) return -Pi/2 - atan(x/y) // -Pi/4 .. -3*Pi/4 if (y >= 0) return Pi + atan(y/x) // +3*Pi/4 .. Pi else return -Pi + atan(y/x) // -3*Pi/4 .. -Pi */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" #define PI 0x40490fdb /* Pi */ #define PI_2 0x3fc90fdb /* Pi/2 */ #define disp ZL /* displacement high byte */ FUNCTION atan2 .L_nf: rcall _U(__fp_pscA) brcs .L_nan ldi rA2, 0x80 ldi rA3, 0x01 ; replace finite to very small value brne 1f ldi rA3, 0xfe ; replace Inf to very big value 1: rcall _U(__fp_pscB) brcs .L_nan ldi rB2, 0x80 ldi rB3, 0x01 ; replace finite to very small value brne .L_cmp ldi rB3, 0xfe ; replace Inf to very big value rjmp .L_cmp .L_nan: rjmp _U(__fp_nan) .L_zr: rjmp _U(__fp_zero) ENTRY atan2 ; save 'y' sign mov disp, rA3 andi disp, 0x80 ; split rcall _U(__fp_split3) brcs .L_nf ; check the (0,0) case mov r0, rA3 or r0, rB3 breq .L_zr ; compare absolute values .L_cmp: cp rB0, rA0 cpc rB1, rA1 cpc rB2, rA2 cpc rB3, rA3 brlo 1f ; fabs(A) <= fabs(B), no swapping mov r0, disp ; sign(A) bld r0, 7 ; sign(A) ^ sign(B) eor disp, r0 ; sign(B) breq 2f ; displacement is not needed eor disp, r0 ; restore sign(A) ori disp, hhi8(PI) rjmp 2f ; fabs(A) > fabs(B), swap values and change the atan sign 1: ori disp, hhi8(PI_2) bld r0, 7 ; inverse division sign com r0 bst r0, 7 X_movw XL, rA0 X_movw rA0, rB0 X_movw rB0, XL X_movw XL, rA2 X_movw rA2, rB2 X_movw rB2, XL ; save displacement and calculate atan 2: push disp rcall _U(__divsf3_pse) rcall _U(__fp_round) rcall _U(atan) ; restore disp and analize pop rB3 ; hhi8() tst rB3 breq 9f ; add displacement ldi rB0, lo8(PI) ; lo8(PI) == lo8(PI_2) ldi rB1, hi8(PI) ; hi8(PI) == hi8(PI_2) ldi rB2, hlo8(PI) sbrc rB3, 0 ; hhi8(PI) == 0x40, hhi8(PI_2) == 0x3f ldi rB2, hlo8(PI_2) rjmp _U(__addsf3) 9: ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/ntz.h0000644000000000000000000000137111732702554014057 0ustar #ifndef _NTZ_H #define _NTZ_H /* Number of Tail Zeros: ntz(x)= (ffs(x) ? ffs(x)-1 : 16) It works with all: cpp, gcc and gas expressions. */ #define ntz(x) \ ( (1 & (((x) & 1) == 0)) \ + (1 & (((x) & 3) == 0)) \ + (1 & (((x) & 7) == 0)) \ + (1 & (((x) & 017) == 0)) \ + (1 & (((x) & 037) == 0)) \ + (1 & (((x) & 077) == 0)) \ + (1 & (((x) & 0177) == 0)) \ + (1 & (((x) & 0377) == 0)) \ + (1 & (((x) & 0777) == 0)) \ + (1 & (((x) & 01777) == 0)) \ + (1 & (((x) & 03777) == 0)) \ + (1 & (((x) & 07777) == 0)) \ + (1 & (((x) & 017777) == 0)) \ + (1 & (((x) & 037777) == 0)) \ + (1 & (((x) & 077777) == 0)) \ + (1 & (((x) & 0177777) == 0)) ) #endif /* !_NTZ_H */ avr-libc-1.8.0.orig/libm/fplib/fixsfsi.S0000644000000000000000000000467611732702554014705 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fixsfsi.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* long __fixsfsi (float A); The __fixsfsi() function converts A to the integer value. No rounding, the fractional is losted. The compiler calls this function to perform a cast operation from float (i.e. double) to long. No saturation. Return: The integral part of A. If A is too big (i.e. A is less then -0x0.ffffffp+31 or A is great then +0x0.ffffffp+31), this realization returns the LONG_MIN value (i.e. 0x80000000). If A is not a number, also LONG_MIN is returned. See '__fixunssfsi.S' why saturation is't used. */ ENTRY __fixsfsi rcall _U(__fixunssfsi) set cpse rAE, r1 ; error flag rjmp _U(__fp_szero) ; return 0x80000000 ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/floatundisf.S0000644000000000000000000000653011732702554015537 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: floatundisf.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* float __floatundisf (unsigned long long x) Input: rA3.rA2.rA1.rA0.rB3.rB2.rB1.rB0 - an 'x' arg Output: rA3.rA2.rA1.rA0 */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" ENTRY __floatundisf clt ; result sign ENTRY __fp_di2sf mov ZH, rA3 ldi rA3, 127 + 55 ; exponent for 00.80.00.00.00.00.00.00 tst ZH breq .L_tstA2 /* Shift to right is needed by 1..8 positions. Optimization: accumulate an info about tail into rB2. */ cp r1, rB0 cpc r1, rB1 cpc r1, rB2 sbc rB2, rB2 ; shift to right 1: inc rA3 ; exponent += 1 lsr ZH ror rA2 ror rA1 ror rA0 ror rB3 sbci rB2, 0 ; set rB2[7] if C was 1 tst ZH brne 1b rjmp .L_round ; x == 0 2: clr rA3 ret ; check: is fast shift possible? .L_tstA2: tst rA2 brne 4f ; fast shift to left 3: subi rA3, 8 brpl 2b ; 127+55 - 7*8 --> 126 or rA2, rA1 ; obtain Z flag mov rA1, rA0 mov rA0, rB3 mov rB3, rB2 mov rB2, rB1 mov rB1, rB0 ldi rB0, 0 breq 3b ; Z is result of 'or rA2,rA1' /* rA2 is not 0. It is needed shift to left by 0..7 positions. Optimization: rB2..rB0 are not shifted. Instead, save an info about tail in rB2. */ 4: cp r1, rB0 cpc r1, rB1 cpc r1, rB2 sbc rB2, rB2 tst rA2 brmi .L_round 5: dec rA3 ; exponent -= 1 lsl rB2 rol rB3 rol rA0 rol rA1 rol rA2 brpl 5b /* Round and pack. Now we have: rA3 - mantissa rA2.rA1.rA0.rB3 - fraction rB2 - is negative if tail is not equal 0 */ .L_round: tst rB3 brpl 7f lsl rB2 rol rB3 brne 6f sbrs rA0, 0 ; round to even rjmp 7f 6: subi rA0, -1 sbci rA1, -1 sbci rA2, -1 sbci rA3, -1 ; pack 7: lsl rA2 lsr rA3 ror rA2 bld rA3, 7 ; sign ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp_pscA.S0000644000000000000000000000402511732702554014571 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_pscA.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* __fp_pscA (float_splited_t A); Post split classification. Return: C = 1, Z = 0 for NaN C = 0, Z = 1 for Inf C = 0, Z = 0 for finite number */ ENTRY __fp_pscA clr r0 dec r0 cp r1, rA0 cpc r1, rA1 cpc r1, rA2 cpc r0, rA3 ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/copysign.S0000644000000000000000000000362411732702554015055 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: copysign.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* float copysign (float x, float y); The copysign() function returns x but with the sign of y. They work even if x or y are NaN or zero. */ ENTRY copysign bst rB3, 7 bld rA3, 7 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/tan.S0000644000000000000000000000702111732702554013777 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: tan.S 1174 2007-01-14 15:13:54Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* float tan (float A); The tan() function returns the tangent of A, where A is given in radians. */ /* Calculation: 0 <= x <= Pi/4 --> tan(x) fmod Pi/4 < x < Pi/2 --> 1/tan(Pi/2-x) fmod, Pi/2-x, 1/x Pi/2 <= x <= 3*Pi/4 --> -1/tan(x-Pi/2) fmod, 1/x, -x 3*Pi/4 < x < Pi --> -tan(Pi-x) fmod, Pi/2-x, -x */ #define HI40_PIO4 0x3F490FDA /* (flt40_t) Pi/4 */ #define LO40_PIO4 0xA2 /* --"-- */ #define HI40_PIO2 0x3FC90FDA /* (flt40_t) Pi/2 */ #define LO40_PIO2 0xA2 /* --"-- */ #define rsign YH ENTRY tan ; save sign push rsign mov rsign, rA3 ; fmod by Pi/2 rcall _U(__fp_rempio2) ; save perion number lsr ZL ror rsign ; is A <= Pi/4 ? #if LO40_PIO4 == 0xFF /* HI40_PIO4: increment is not needed */ # error #endif ldi rB0, lo8(HI40_PIO4) ldi rB1, hi8(HI40_PIO4) ldi rB2, hlo8(HI40_PIO4) ldi rB3, hhi8(HI40_PIO4) cpi rAE, LO40_PIO4 + 1 cpc rA0, rB0 cpc rA1, rB1 cpc rA2, rB2 cpc rA3, rB3 ror rsign ; save comparison result brmi 1f ; N == C flag after comparison ; for A > Pi/4: tan(A) == 1/tan(Pi/2 - A) #if (HI40_PIO4 ^ HI40_PIO2) & 0xFF00FFFF /* 'ldi' optimization */ # error #endif ldi rBE, LO40_PIO2 ldi rB2, hlo8(HI40_PIO2) ori rA3, 0x80 rcall _U(__addsf3x) rcall _U(__fp_round) ; calculate tan(A) for 0 <= A <= Pi/4 1: ldi ZL, lo8(.L_table) ldi ZH, hi8(.L_table) rcall _U(__fp_powsodd) ; correct result lsl rsign brvs 2f rcall _U(inverse) 2: lsl rsign brvc 3f subi rA3, 0x80 3: pop rsign ret ENDFUNC PGM_SECTION .L_table: .byte 6 .byte 0x64,0xec,0x1b,0x3c ; 0.0095168091 .byte 0x04,0xbc,0x16,0x3e,0x3b ; 0.0029005250 .byte 0xe5,0xb9,0x3c,0xc9,0x3c ; 0.0245650893 .byte 0x37,0xc2,0x9e,0x5a,0x3d ; 0.0533740603 .byte 0x66,0x04,0x98,0x08,0x3e ; 0.1333923995 .byte 0xea,0x69,0xaa,0xaa,0x3e ; 0.3333314036 .byte 0x00,0x00,0x00,0x80,0x3f ; 1.0000000000 .end avr-libc-1.8.0.orig/libm/fplib/ldexp.S0000644000000000000000000000613711732702554014340 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ldexp.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* double ldexp (double x, int exp) The ldexp() function returns the result of multiplying the floating-point number x by 2 raised to the power exp. */ #define exp_lo r20 #define exp_hi r21 FUNCTION ldexp .L_inf: rjmp _U(__fp_inf) .L_pk: rjmp _U(__fp_mpack) ENTRY ldexp rcall _U(__fp_splitA) brcs .L_pk ; as is tst rA3 breq .L_pk ; ldexp(0,*) is always 0 .ifnc rB3, exp_hi .err ; rB3 and exp_hi are different .endif add rA3, exp_lo ; rB3.rA3 := new exponent adc rB3, r1 brvs .L_inf ; overflow is possible for exp > 0 only ; check exponent for minus and zero subi rA3, lo8(1) sbci rB3, hi8(1) brlt 5f ; denormalization is needed breq .L_pack ; normalization is impossible 1: tst rA2 brmi 2f lsl rA0 rol rA1 rol rA2 subi rA3, lo8(1) sbci rB3, hi8(1) brne 1b ; C == 0, Z == 0 ; check to overflow 2: cpi rA3, 254 cpc rB3, r1 brge .L_inf .L_pack: lsl rA2 adc rA3, r1 ; restore exponent for normal numbers lsr rA3 ror rA2 bld rA3, 7 ; sign ret ; exponent <= 0 5: cpi rB3, hi8(-24) brlt .L_zero cpi rA3, lo8(-24) brlt .L_zero ; denormalize A clr rAE 6: lsr rA2 ror rA1 ror rA0 ror rAE brcc 7f ori rAE, 1 7: inc rA3 brne 6b .L_round: lsl rAE brcc .L_pack brne 4f sbrs rA0, 0 rjmp .L_pack 4: subi rA0, -1 sbci rA1, -1 sbci rA2, -1 sbci rA3, -1 rjmp .L_pack .L_zero: rjmp _U(__fp_szero) ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/mulsf3x.S0000644000000000000000000001270011732702554014616 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: mulsf3x.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" FUNCTION __mulsf3x #if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ 0: rcall _U(__fp_pscA) brcs 1f rcall _U(__fp_pscB) brcs 1f and rA3, rB3 ; one of args is 0xff breq 1f rjmp _U(__fp_inf) ; nonzero * Inf --> Inf 1: rjmp _U(__fp_nan) ; 0 * Inf --> NaN 2: clr r1 ; after 'mul rA3,rB3' rjmp _U(__fp_szero) ENTRY __mulsf3x rcall _U(__fp_split3) brcs 0b ENTRY __mulsf3_pse ; post split entry ; check zero mul rA3, rB3 ; r1 would be clean breq 2b ; rB3.rA3 := rA3 + rB3 add rA3, rB3 ldi rB3, 0 adc rB3, rB3 ; multiplication: rA2.rA1.rA0 * rB2.rB1.rB0 --> rA2.rA1.rA0.rAE.ZH.ZL ; ZH.ZL = rA0 * rB0 mul rA0, rB0 movw ZL, r0 ; rAE.ZH += rA1 * rB0 mul rA1, rB0 clr rAE add ZH, r0 adc rAE, r1 ; rBE.rAE.ZH = rAE.ZH + rA0 * rB1 mul rA0, rB1 clr rBE add ZH, r0 adc rAE, r1 adc rBE, rBE ; rA0.rBE.rAE = rBE.rAE + rA0 * rB2 mul rA0, rB2 clr rA0 add rAE, r0 adc rBE, r1 adc rA0, rA0 ; rA0.rBE.rAE += rA2 * rB0 mul rA2, rB0 clr rB0 add rAE, r0 adc rBE, r1 adc rA0, rB0 ; rA0.rBE.rAE += rA1 * rB1 mul rA1, rB1 add rAE, r0 adc rBE, r1 adc rA0, rB0 ; rB0 == 0 ; rB0.rA0.rBE = rA0.rBE + rA2 * rB1 mul rA2, rB1 add rBE, r0 adc rA0, r1 adc rB0, rB0 ; rB0 was 0 ; rB0.rA0.rBE += rA1 * rB2 mul rA1, rB2 clr rB1 add rBE, r0 adc rA0, r1 adc rB0, rB1 ; rB0.rA0 += rA2 * rB2 mul rA2, rB2 add rA0, r0 adc rB0, r1 ; move result: rA2.rA1.rA0.rAE.ZH.ZL = rB0.rA0.rBE.rAE.ZH.ZL mov rA2, rB0 mov rA1, rA0 mov rA0, rBE ; __zero_reg__ clr r1 #else /* to __AVR_ENHANCED__ */ 0: rcall _U(__fp_pscA) brcs 1f rcall _U(__fp_pscB) brcs 1f and rA3, rB3 ; one of args is 0xff breq 1f rjmp _U(__fp_inf) ; nonzero * Inf --> Inf 1: rjmp _U(__fp_nan) ; 0 * Inf --> NaN 2: rjmp _U(__fp_szero) ENTRY __mulsf3x rcall _U(__fp_split3) brcs 0b ENTRY __mulsf3_pse ; post split entry ; check zero tst rA3 breq 2b tst rB3 breq 2b ; rB3.rA3 := rA3 + rB3 add rA3, rB3 ldi rB3, 0 adc rB3, rB3 ; multiplication: rA2.rA1.rA0 * rB2.rB1.rB0 --> rA2.rA1.rA0.rAE.ZH.ZL clr rBE ; 4-d byte of rB* clr ZL clr ZH clr rAE ; r0.rAE.ZH.ZL += rA0 * rB2.rB1.rB0 clr r0 sec ; to count loops ror rA0 1: brcc 2f add ZL, rB0 adc ZH, rB1 adc rAE, rB2 adc r0, rBE 2: lsl rB0 rol rB1 rol rB2 rol rBE lsr rA0 brne 1b ; rA0.r1.r0.rAE.ZH += rA1 * rBE.rB2.rB1 ror rA1 ; C was 1 3: brcc 4f add ZH, rB1 adc rAE, rB2 adc r0, rBE adc r1, rB0 brcc 4f inc rA0 4: lsl rB1 rol rB2 rol rBE rol rB0 lsr rA1 brne 3b ; rA0.r1.r0.rAE += rA2 * rB0.rBE.rB2 ror rA2 ; C was 1 5: brcc 6f add rAE, rB2 adc r0, rBE adc r1, rB0 adc rA0, rB1 6: lsl rB2 rol rBE rol rB0 rol rB1 lsr rA2 brne 5b ; move result: rA2.rA1.rA0.rAE.ZH.ZL := rA0.r1.r0.rAE.ZH.ZL mov rA2, rA0 mov rA1, r1 mov rA0, r0 ; __zero_reg__ clr r1 #endif /* not __AVR_ENHANCED__ */ ; exponent -= 127 (Why not 126? For compare conviniency.) subi rA3, lo8(127) sbci rB3, hi8(127) brmi 13f ; denormalization is needed breq 15f ; normalization is impossible ; result exponent > min ==> normalization is possible 10: tst rA2 brmi 11f ; mantissa is normal ; mantissa <<= 1 lsl ZL rol ZH rol rAE rol rA0 rol rA1 rol rA2 ; exponent -= 1 subi rA3, lo8(1) sbci rB3, hi8(1) brne 10b ; check to overflow 11: cpi rA3, 254 cpc rB3, r1 brlo 15f rjmp _U(__fp_inf) ; check lowest value of exponent to avoid long operation 12: rjmp _U(__fp_szero) 13: cpi rB3, hi8(-24) ; here rB3 < 0 brlt 12b cpi rA3, lo8(-24) brlt 12b ; mantissa >>= -rA3 14: lsr rA2 ror rA1 ror rA0 ror rAE ror ZH ror ZL subi rA3, -1 brne 14b ; for rounding 15: or ZH, ZL ; pack lsl rA2 adc rA3, r1 ; restore exponent for normal values lsr rA3 ror rA2 bld rA3, 7 ; sign ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/floatdisf.S0000644000000000000000000000366011732702554015175 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: floatdisf.S 1173 2007-01-14 15:04:40Z dmix $ */ /* float __floatdisf (long long x) Input: rA3.rA2.rA1.rA0.rB3.rB2.rB1.rB0 - an 'x' arg Output: rA3.rA2.rA1.rA0 */ #include "fp32def.h" #include "asmdef.h" ENTRY __floatdisf bst rA3, 7 ; sign brtc 1f rcall _U(__fp_negdi) 1: rjmp _U(__fp_di2sf) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fdim.S0000644000000000000000000000522711732702554014142 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fdim.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float fdim (float x, float y); The fdim() function return max(x-y,0). If x or y or both are NaN, NaN is returned. Notes: * In case 'A == B' subtraction is called to save flash space. Contrary it is needed to check 'Inf - Inf'. And the __subsf3() is fast if both arguments are equal. */ ENTRY fdim ; sign(A) | sign(B) mov r0, rA3 or r0, rB3 brmi 2f ; A >= 0 and B >= 0 cp rA0, rB0 cpc rA1, rB1 cpc rA2, rB2 cpc rA3, rB3 brcs 3f 1: rjmp _U(__subsf3) ; A < 0 or B < 0 2: cp rB0, rA0 cpc rB1, rA1 cpc rB2, rA2 cpc rB3, rA3 brcc 1b ; before 0 return, check a NaN 3: ldi ZL, 0x80 ; hlo8(Inf) ldi ZH, 0xfe ; hhi8(Inf) after 'lsl' lsl rA3 cp r1, rA0 cpc r1, rA1 cpc ZL, rA2 cpc ZH, rA3 brlo .L_nan ; check B for NaN lsl rB3 cp r1, rB0 cpc r1, rB1 cpc ZL, rB2 cpc ZH, rB3 brlo .L_nan ; return 0 rjmp _U(__fp_zero) .L_nan: rjmp _U(__fp_nan) ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/negsf2.S0000644000000000000000000000337111732702554014405 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: negsf2.S 1174 2007-01-14 15:13:54Z dmix $ */ /* */ #include "fp32def.h" #include "asmdef.h" ENTRY __negsf2 subi rA3, 0x80 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/floatsisf.S0000644000000000000000000000540011732702554015206 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: floatsisf.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* float __floatsisf (long) float __floatunsisf (unsigned long) */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" ENTRY __floatunsisf clt rjmp 1f ENTRY __floatsisf bst rA3, 7 ; sign brtc 1f ; negate A com rA3 com rA2 com rA1 neg rA0 sbci rA1, -1 sbci rA2, -1 sbci rA3, -1 1: tst rA3 breq 4f ; shift to right mov ZH, rA3 ldi rA3, 127 + 23 ; exponent clr rAE 2: inc rA3 lsr ZH ror rA2 ror rA1 ror rA0 ror rAE cpse ZH, r1 rjmp 2b ; rounding brpl .L_pack ; flags from 'ror rAE' lsl rAE brne 3f sbrs rA0, 0 ; round to even rjmp .L_pack 3: subi rA0, -1 sbci rA1, -1 sbci rA2, -1 sbci rA3, -1 rjmp .L_pack 4: tst rA2 breq 5f ldi rA3, 127 + 23 rjmp 8f 5: tst rA1 breq 6f ldi rA3, 127 + 15 mov rA2, rA1 mov rA1, rA0 rjmp 7f 6: tst rA0 breq 9f ; 0.0 ldi rA3, 127 + 7 mov rA2, rA0 ldi rA1, 0 7: ldi rA0, 0 brmi .L_pack ; flag from 'tst rA*' ; shift to left by 1..7 positions 10: dec rA3 lsl rA0 rol rA1 rol rA2 8: brpl 10b .L_pack: lsl rA2 lsr rA3 ror rA2 bld rA3, 7 ; sign 9: ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/Makefile.am0000644000000000000000000000325711732702554015134 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # include $(top_srcdir)/libm/fplib/Files.am EXTRA_DIST = \ $(libm_a_asm_sources) \ $(libm_a_extra_dist) avr-libc-1.8.0.orig/libm/fplib/addsf3.S0000644000000000000000000000363111732702554014364 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: addsf3.S 1174 2007-01-14 15:13:54Z dmix $ */ /* float __subsf3 (float, float); float __addsf3 (float, float); */ #include "fp32def.h" #include "asmdef.h" ENTRY __subsf3 subi rB3, 0x80 ; complement sign bit of B ENTRY __addsf3 clr rAE clr rBE rcall _U(__addsf3x) rjmp _U(__fp_round) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/trunc.S0000644000000000000000000000407311732702554014354 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: trunc.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* double trunc (double x); The trunc() function rounds x to the nearest integer not larger in absolute value. Examples: trunc(1.9) --> 1.0 trunc(-1.9) --> -1.0 */ ENTRY trunc rcall _U(__fp_trunc) brcs 2f ; pass nonfinite arg as is cpi rA3, 127 brsh 1f ; fabs(A) >= 1.0 rjmp _U(__fp_szero) 1: rjmp _U(__fp_mintl) 2: rjmp _U(__fp_mpack) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/divsf3.S0000644000000000000000000000350011732702554014411 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: divsf3.S 1174 2007-01-14 15:13:54Z dmix $ */ /* float __divsf3 (float x, float y); Return x/y. */ #include "fp32def.h" #include "asmdef.h" ENTRY __divsf3 rcall _U(__divsf3x) rjmp _U(__fp_round) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/fp_sinus.S0000644000000000000000000000505711732702554015052 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_sinus.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float __fp_sinus (flt40_t A, ZL); */ #define HI40_PIO2 0x3FC90FDA /* high 4 bytes Pi/2 */ #define LO40_PIO2 0xA2 ENTRY __fp_sinus push ZL sbrs ZL, 0 rjmp 1f ldi rBE, LO40_PIO2 ldi rB0, lo8(HI40_PIO2) ldi rB1, hi8(HI40_PIO2) ldi rB2, hlo8(HI40_PIO2) ldi rB3, hhi8(HI40_PIO2 | 0x80000000) rcall _U(__addsf3x) 1: rcall _U(__fp_round) pop r0 inc r0 sbrc r0, 1 subi rA3, 0x80 ldi ZL, lo8(.L_table) ldi ZH, hi8(.L_table) rjmp _U(__fp_powsodd) ENDFUNC PGM_SECTION .L_table: .byte 5 .byte 0xa8,0x4c,0xcd,0xb2 ; -0.0000000239 .byte 0xd4,0x4e,0xb9,0x38,0x36 ; 0.0000027526 .byte 0xa9,0x02,0x0c,0x50,0xb9 ; -0.0001984090 .byte 0x91,0x86,0x88,0x08,0x3c ; 0.0083333315 .byte 0xa6,0xaa,0xaa,0x2a,0xbe ; -0.1666666664 .byte 0x00,0x00,0x00,0x80,0x3f ; 1.0000000000 .end #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/isinf.S0000644000000000000000000000421511732702554014327 0ustar /* Copyright (c) 2002, Joerg Wunsch Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: isinf.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* int isinf (double) The isinf() function returns -1 if value represents negative infinity, 1 if value represents positive infinity, and 0 otherwise. Notes: * It is implemented to save space, as there is a time effective isfinite() inline function. */ ENTRY isinf rcall _U(__fp_splitA) ldi r24, 0 ldi r25, 0 brcc 2f ; normal value brne 2f ; NaN brtc 1f ; +Inf sbiw r24, 2 1: inc r24 2: ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/exp.S0000644000000000000000000000715111732702554014015 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: exp.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float exp (float x); The exp() function returns the value of e (the base of natural logarithms) raised to the power of x. */ #define X2BIG 0x43000000 /* exp(-X2BIG) < 0x00000001 */ #define FL_1_LN2 0x3fb8aa3b /* 1 / ln(2) */ /* second arg for modf(), ldexp() functions. */ #define exp_lo r20 #define exp_hi r21 FUNCTION exp .L_nf: brne .L_nan .L_tb: brts .L_zr rjmp _U(__fp_inf) .L_zr: rjmp _U(__fp_zero) .L_nan: rjmp _U(__fp_nan) ENTRY exp ; split and analize A rcall _U(__fp_splitA) brcs .L_nf ; A is not a finite number cpi rA3, hhi8(X2BIG << 1) brsh .L_tb ; A is too big (in absolute value) ; save sign and jump to positive bld r0, 7 push r0 clt ; A = A / ln(2) ldi rB0, lo8(FL_1_LN2) ldi rB1, hi8(FL_1_LN2) ldi rB2, hlo8(FL_1_LN2 | 0x800000) ; hidden '1' ldi rB3, hhi8(FL_1_LN2 << 1) ; exponent rcall _U(__mulsf3_pse) ; split A into fraction and integral parts push r0 push r0 push r0 in exp_lo, SPL_IO_ADDR in exp_hi, SPH_IO_ADDR push r0 rcall _U(modf) ; calculate 2**(-x) for 0 <= x < 1 ldi ZL, lo8(.L_table) ldi ZH, hi8(.L_table) rcall _U(__fp_powser) ; get integral part pop exp_lo pop exp_hi pop ZL pop ZH ; cast to integer asr ZL rol ZL rol ZH breq 2f subi ZH, 0x7e ori ZL, 0x80 clr exp_lo 1: lsl ZL rol exp_lo dec ZH brne 1b ; negate and scale neg exp_lo sbc exp_hi, exp_hi 2: rcall _U(ldexp) ; inverse for positive arg. pop r0 sbrs r0, 7 rjmp _U(inverse) ret ENDFUNC PGM_SECTION .L_table: .byte 7 .byte 0x63,0x42,0x36,0xb7 ; -0.0000108635 .byte 0x9b,0xd8,0xa7,0x1a,0x39 ; 0.0001474911 .byte 0x68,0x56,0x18,0xae,0xba ; -0.0013282400 .byte 0xab,0x55,0x8c,0x1d,0x3c ; 0.0096159779 .byte 0xb7,0xcc,0x57,0x63,0xbd ; -0.0555036542 .byte 0x6d,0xed,0xfd,0x75,0x3e ; 0.2402264688 .byte 0xf6,0x17,0x72,0x31,0xbf ; -0.6931471802 .byte 0x00,0x00,0x00,0x80,0x3f ; 1.0000000000 .end #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/mulsf3.S0000644000000000000000000000340611732702554014431 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: mulsf3.S 1174 2007-01-14 15:13:54Z dmix $ */ #include "fp32def.h" #include "asmdef.h" ENTRY __mulsf3 rcall _U(__mulsf3x) rjmp _U(__fp_round) ENDFUNC avr-libc-1.8.0.orig/libm/fplib/sinh.S0000644000000000000000000000570011732702554014160 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: sinh.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float sinh (float x); The sinh() function returns the hyperbolic sine of x, which is defined mathematically as (exp(x) - exp(-x)) / 2. Notes: ldexp() is used twice to avoid overflow for big x. */ #define X2SMALL 0x3e9fffff /* < 0.3125 */ #define exp_lo r20 /* float ldexp (float, int exp); */ #define exp_hi r21 ENTRY sinh ; save sign push rA3 ; is arg too small ? andi rA3, 0x7f ldi ZH, hhi8 (X2SMALL + 1) cpi rA2, hlo8 (X2SMALL + 1) cpc rA3, ZH brsh 1f ; for small x ldi ZL, lo8(.L_table) ldi ZH, hi8(.L_table) rcall _U(__fp_powsodd) rjmp 2f ; exp(-fabs(x)) // negative to exclude an extra inversion 1: ori rA3, 0x80 rcall _U(exp) ; exp(-fabs(x)) / 2 ldi exp_lo, lo8(-1) ldi exp_hi, hi8(-1) rcall _U(ldexp) ; save push rA3 push rA2 push rA1 push rA0 ; exp(fabs(x)) / 2 ldi exp_lo, lo8(2) ldi exp_hi, hi8(2) rcall _U(ldexp) rcall _U(inverse) ; result (in absolute value) pop rB0 pop rB1 pop rB2 pop rB3 rcall _U(__subsf3) ; set sign 2: pop r0 sbrc r0, 7 ori rA3, 0x80 ret ENDFUNC PGM_SECTION .L_table: .byte 2 .byte 0x89,0x88,0x08,0x3c ; 1/120 .byte 0xab,0xaa,0xaa,0x2a,0x3e ; 1/6 .byte 0x00,0x00,0x00,0x80,0x3f ; 1 .end #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fmod.S0000644000000000000000000000652411732702554014151 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fmod.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* double fmod (double x, double y); The fmod() function computes the remainder of dividing x by y. The return value is x - n*y, where n is the quotient of x/y, rounded towards zero to an integer. */ FUNCTION fmod 0: rcall _U(__fp_pscA) brcs .L_nan ; isnan(A) breq .L_nan ; isinf(A) rcall _U(__fp_pscB) brcc 1f ; isinf(B) -- legal arg: return A .L_nan: rjmp _U(__fp_nan) .L_sz: rjmp _U(__fp_szero) ENTRY fmod ; split and check exceptions mov ZL, rA3 ; save rcall _U(__fp_split3) brcs 0b tst rB3 breq .L_nan ; B == 0 1: bst ZL, 7 ; sign(A) ; compare A & B (in absolute value) cp rA0, rB0 cpc rA1, rB1 cpc rA2, rB2 cpc rA3, rB3 brlo .L_pk ; fabs(A) < fabs(B) --> return A breq .L_sz ; fabs(A) == fabs(B) --> return sign(A)*0 ; ZH.ZL = ilogb(A), normalize A mov ZL, rA3 clr ZH tst rA2 brmi 2f 1: sbiw ZL, 1 lsl rA0 rol rA1 rol rA2 brpl 1b ; rB3.rA3 = ilogb(B), normalize B 2: mov rA3, rB3 clr rB3 tst rB2 brmi 4f 3: subi rA3, lo8(1) sbci rB3, hi8(1) lsl rB0 rol rB1 rol rB2 brpl 3b ; prepare loop 4: clr rAE ; highest A byte sub ZL, rA3 ; ZH.ZL = ilogb(A) - ilogb(B) sbc ZH, rB3 .Loop: sub rA0, rB0 sbc rA1, rB1 sbc rA2, rB2 sbc rAE, r1 breq .L_sz brpl 5f add rA0, rB0 adc rA1, rB1 adc rA2, rB2 adc rAE, r1 5: sbiw ZL, 1 brmi 6f lsl rA0 rol rA1 rol rA2 rol rAE rjmp .Loop 6: subi rA3, lo8(1) sbci rB3, hi8(1) brmi 9f breq 8f 7: tst rA2 brmi 8f lsl rA0 rol rA1 rol rA2 subi rA3, lo8(1) sbci rB3, hi8(1) brne 7b 8: inc rA3 .L_pk: rjmp _U(__fp_mpack) 9: lsr rA2 ror rA1 ror rA0 subi rA3, -1 brne 9b rjmp 8b ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/floor.S0000644000000000000000000000476311732702554014350 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: floor.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* double floor (double x); The floor() function rounds x down to the nearest integer. Examples: floor(1.9) --> 1.0 floor(-1.9) --> -2.0 */ #define FL_M1 0xbf800000 /* -1.0 */ ENTRY floor rcall _U(__fp_trunc) brcs .L_nf ; A is finite cpi rA3, 127 brsh 2f ; fabs(A) < 1.0 cpse rA3, r1 ; floor(-0.0) is -0.0 brts 1f rjmp _U(__fp_szero) ; fabs (-1.0 < A < 0.0) --> -1.0 1: ldi rA0, lo8(FL_M1) ldi rA1, hi8(FL_M1) ldi rA2, hlo8(FL_M1) ldi rA3, hhi8(FL_M1) ret ; fabs (x) >= 1.0 2: brtc 3f ; if positive cp r1, rAE ; C = 1 if fraction != 0 adc rA0, r1 adc rA1, r1 adc rA2, r1 ; rA2 was < 0x80, overflow is impossible 3: rjmp _U(__fp_mintl) .L_nf: rjmp _U(__fp_mpack) ; pass nonfinite arg as is ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp_mpack.S0000644000000000000000000000542711732702554015005 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_mpack.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float __fp_mpack (); Merge parts of float value. Input: T - sign rA3 - exponent rA2.rA1.rA0[.rAE] - mantissa Possible input combinations: exp==0 - zero or subnormal, mantissa shift to right is needed exp==1, rA2 < 0x80 - subnormal exp==1, rA2 >= 0x80 - normal exp==2..254, rA2 >= 0x80 - normal exp==255, rA2.rA1.rA0 == 0 - Infinity exp==255, rA2.rA1.rA0 != 0 - NaN The __fp_mpack_finite entry point is intended for case where it is known that the A is a finite number. */ ENTRY __fp_mpack cpi rA3, 255 breq 1f ENTRY __fp_mpack_finite subi rA3, 1 brsh 1f ror rA2 ; rA2.7 := 1 to restore zero rA3 ror rA1 ror rA0 ror rAE 1: lsl rA2 adc rA3, r1 ; switch (A) ; zero: rA3 is restored to 0 ; subnormal: rA3 is stayed (or restored to) 0 ; normal: rA3 is restored to initial ; nonfinite: rA3 is stayed 255 lsr rA3 ror rA2 bld rA3, 7 ; sign ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/round.S0000644000000000000000000000574311732702554014355 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: round.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* double round (double A); The round() function rounds A to the nearest integer, but rounds halfway cases away from zero (instead of to the nearest even integer). Overflow is impossible. Return: The rounded value. If A is an integral or infinite, A itself is returned. If A is NaN, then NaN is returned. Algorithm roughly: - split - shift right to obtain the 0.5 at the little bit - if the little bit is set, add 1 to mantissa - merge to float This is a balance between space and speed. */ ENTRY round rcall _U(__fp_splitA) brcs .L_nf ; A is finite cpi rA3, 126 ; exponent field of 0.5 brlo .L_zr ; A is too small ; fabs(A) >= 0x0.800000p+00 cpi rA3, 126+24 brsh 4f ; A is too big ; fabs(A) <= 0x0.ffffffp+23 1: cpi rA3, 126+16 brsh 3f ; shift by 0..7 positions is needed ; quick shift by 8 mov rA0, rA1 mov rA1, rA2 clr rA2 subi rA3, -8 rjmp 1b ; slow shift 2: lsr rA2 ror rA1 ror rA0 inc rA3 3: cpi rA3, 126+23 brlo 2b ; round mov rAE, rA0 andi rAE, 1 add rA0, rAE adc rA1, r1 adc rA2, r1 ; check and correct a possible overflow brcc 4f ror rA2 ror rA1 ror rA0 inc rA3 ; merge 4: rjmp _U(__fp_mintl) .L_nf: rjmp _U(__fp_mpack) ; pass nonfinite arg "as is" .L_zr: rjmp _U(__fp_szero) ; return +0.0/-0.0 ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/atan.S0000644000000000000000000000670211732702554014145 0ustar /* Copyright (c) 2002, Reiner Patommel Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: atan.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* float atan (float A); The atan() function calculates the arc tangent of A; that is the value whose tangent is A. Algorithm: if (x > 1) return Pi/2 - atan(1/x) elif (x < -1) return -Pi/2 - atan(1/x) else return x * (1 - C1 * x**2 + ... + C8 * x**16) */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" #define FL_1 0x3f800000 /* +1.0 */ #define HI40_PI_2 0x3fc90fda /* high 4 bytes of Pi/2 */ #define LO40_PI_2 0xa2 /* lowest byte of Pi/2 */ #define corr YH ENTRY atan push corr clr corr ; inverse A, if needed mov rAE, rA3 andi rAE, 0x7f ; rAE.rA2.rA1.rA0 == fabs(A) ldi rB2, hlo8(FL_1) ldi rB3, hhi8(FL_1) cp r1, rA0 cpc r1, rA1 cpc rB2, rA2 cpc rB3, rAE brsh 1f mov corr, rA3 ; rA3 != 0 rcall _U(inverse) ; calculate atan(A) for -1.0 <= A <= +1.0 1: push rA3 push rA2 push rA1 push rA0 rcall _U(square) ldi ZL, lo8(.L_table) ldi ZH, hi8(.L_table) rcall _U(__fp_powser) rcall _U(__fp_round) pop rB0 pop rB1 pop rB2 pop rB3 rcall _U(__mulsf3x) ; is correction needed ? tst corr breq 2f ; add/sub Pi/2 subi rA3, 0x80 ldi rBE, LO40_PI_2 ldi rB0, lo8(HI40_PI_2) ldi rB1, hi8(HI40_PI_2) ldi rB2, hlo8(HI40_PI_2) ldi rB3, hhi8(HI40_PI_2) andi corr, 0x80 eor rB3, corr rcall _U(__addsf3x) ; restore and round 2: pop corr rjmp _U(__fp_round) ENDFUNC PGM_SECTION .L_table: .byte 8 .byte 0x4a,0xd7,0x3b,0x3b ; 0.0028662257 .byte 0xce,0x01,0x6e,0x84,0xbc ; -0.0161657367 .byte 0xbf,0xfd,0xc1,0x2f,0x3d ; 0.0429096138 .byte 0x6c,0x74,0x31,0x9a,0xbd ; -0.0752896400 .byte 0x56,0x83,0x3d,0xda,0x3d ; 0.1065626393 .byte 0x00,0xc7,0x7f,0x11,0xbe ; -0.1420889944 .byte 0xd9,0xe4,0xbb,0x4c,0x3e ; 0.1999355085 .byte 0x91,0x6b,0xaa,0xaa,0xbe ; -0.3333314528 .byte 0x00,0x00,0x00,0x80,0x3f ; 1.0000000000 .end #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/divsf3x.S0000644000000000000000000000740511732702554014611 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: divsf3x.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* __divsf3x (float A, float B); Output: T rA3 rA2.rA1.rA0.rAE.ZH */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" FUNCTION __divsf3x 0: rcall _U(__fp_pscB) brcs .L_nan rcall _U(__fp_pscA) brcs .L_nan brne .L_zr ; finite / Inf --> 0 .L_infA: cpi rB3, 255 breq .L_nan ; Inf / Inf --> NaN .L_inf: rjmp _U(__fp_inf) 1: cpse rB3, r1 ; 0/finite --> 0, 0/0 --> NaN .L_zr: rjmp _U(__fp_szero) .L_nan: rjmp _U(__fp_nan) ENTRY __divsf3x rcall _U(__fp_split3) brcs 0b ENTRY __divsf3_pse ; post split entry tst rA3 breq 1b tst rB3 breq .L_inf ; finite / 0.0 --> Inf sub rA3, rB3 sbc rB3, rB3 /* Prepare to division: A: rAE.rA2.rA1.rA0 0x00000001..0x00FFFFFF B: rBE.rB2.rB1.rB0 0x00000002..0x01FFFFFE A < B */ clr rAE clr rBE 2: cp rA0, rB0 cpc rA1, rB1 cpc rA2, rB2 brlo 3f subi rA3, lo8(-1) sbci rB3, hi8(-1) lsl rB0 rol rB1 rol rB2 rol rBE breq 2b 3: rcall .L_div mov r0, ZL brmi 5f ; N is result of 'com ZL' from .L_div 4: ldi ZL, 0x80 rcall .L_div1 subi rA3, lo8(1) sbci rB3, hi8(1) lsr ZL rol r0 brpl 4b 5: rcall .L_div mov ZH, ZL rcall .L_div lsl rA0 rol rA1 rol rA2 rol rAE cp rB0, rA0 cpc rB1, rA1 cpc rB2, rA2 cpc rBE, rAE ldi rAE, 0x80 breq 4f sbc rAE, rAE 4: mov rA2, r0 X_movw rA0, ZL clr ZH ; exponent += 125 subi rA3, lo8(-125) sbci rB3, hi8(-125) brmi 13f ; denormalization is needed ; check to overflow 11: cpi rA3, 254 cpc rB3, r1 brlo 15f rjmp _U(__fp_inf) ; check lowest value of exponent to avoid long operation 12: rjmp _U(__fp_szero) 13: cpi rB3, hi8(-24) ; here rB3 < 0 brlt 12b cpi rA3, lo8(-24) brlt 12b ; mantissa >>= -rA3 14: lsr rA2 ror rA1 ror rA0 ror rAE ror ZH subi rA3, -1 brne 14b ; pack 15: lsl rA2 adc rA3, r1 ; restore exponent for normal values lsr rA3 ror rA2 bld rA3, 7 ret .L_div: ldi ZL, 1 .L_div1: lsl rA0 rol rA1 rol rA2 rol rAE cp rA0, rB0 cpc rA1, rB1 cpc rA2, rB2 cpc rAE, rBE brcs 2f sub rA0, rB0 sbc rA1, rB1 sbc rA2, rB2 sbc rAE, rBE 2: rol ZL brcc .L_div1 com ZL ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fma.S0000644000000000000000000000434411732702554013765 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fma.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* double fma (double A, double B, double C) The `fma' function performs floating-point multiply-add. This is the operation (A * B) + C, but the intermediate result is not rounded to the destination type. This can sometimes improve the precision of a calculation. */ #define rC0 r14 /* lower byte of arg. C */ #define rC2 r16 ENTRY fma rcall _U(__mulsf3x) X_movw rB0, rC0 X_movw rB2, rC2 clr rBE rcall _U(__addsf3x) rjmp _U(__fp_round) ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/asmdef.h0000644000000000000000000001317311732702554014506 0ustar /* Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: asmdef.h 1815 2008-12-06 03:28:42Z dmix $ */ #ifndef _ASMDEF_H #define _ASMDEF_H #ifndef __AVR_HAVE_MOVW__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_MOVW__ 1 # endif #endif #ifndef __AVR_HAVE_LPMX__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_LPMX__ 1 # endif #endif /* Historicaly, the _U() was intended to concatinate '_' prefix. Let us save it, as one is usefull to find externals quickly. */ #define _U(name) name #define XL r26 #define XH r27 #define YL r28 #define YH r29 #define ZL r30 #define ZH r31 #define SPL_IO_ADDR 0x3D #define SPH_IO_ADDR 0x3E .macro FUNCTION name .ifdef .Lfunction .err ; FUNCTION is defined already. .endif .Lfunction = 1 #ifdef FUNC_SEGNAME .section FUNC_SEGNAME, "ax", @progbits #else .text #endif .type _U(\name), "function" .ifdef .LEND .err ; .LEND is defined already. .endif .size _U(\name), .LEND - . .endm #define FUNCTION FUNCTION /* for CPP conditional expressions */ .macro ENTRY name .ifndef .Lfunction FUNCTION \name .endif .global _U(\name) _U(\name): .endm .macro ENDFUNC .LEND: .endm /* Macro REGNO set the symbol name 'name' to integer which is a 'reg' number (0..31). If 'reg' is not a valid register, compilation error. Valid regs are: r0..r31, R0..R31 and 0..31 */ .macro REGNO name, reg \name = -1 .L__regno = 0 .irp sym, r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \ r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \ r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \ r30,r31 .ifc \sym,\reg \name = .L__regno .endif .L__regno = .L__regno + 1 .endr .L__regno = 0 .irp sym, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \ R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \ R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \ R30,R31 .ifc \sym,\reg \name = .L__regno .endif .L__regno = .L__regno + 1 .endr .if \name < 0 .L__regno = 0 .rept 32 .if \reg == .L__regno \name = .L__regno .endif .L__regno = .L__regno + 1 .endr .endif .if \name < 0 .err ; Invalid dst arg of 'X_lpm' macro. .endif .endm /* REGNO */ /* Macro 'X_movw' extends enhanced movw instruction for classic chips. */ .macro X_movw dst,src #if defined(__AVR_HAVE_MOVW__) && __AVR_HAVE_MOVW__ movw \dst,\src #else REGNO .L__movw_dst, \dst .if .L__movw_dst < 0 .exitm .endif .if .L__movw_dst % 1 .err ; Invalid dst arg in X_movw macro. .exitm .endif REGNO .L__movw_src, \src .if .L__movw_src < 0 .exitm .endif .if .L__movw_src % 1 .err ; Invalid src arg in X_movw macro. .exitm .endif mov .L__movw_dst, .L__movw_src mov .L__movw_dst + 1, .L__movw_src + 1 #endif .endm /* X_movw */ /* Macro 'X_lpm' extends enhanced lpm instruction for classic chips. Usage: X_lpm reg, dst where reg is 0..31, r0..r31 or R0..R31 dst is z, Z, z+ or Z+ It is possible to omit both arguments. Possible results for classic chips: lpm lpm / mov Rd,r0 lpm / adiw ZL,1 lpm / mov Rd,r0 / adiw ZL,1 For enhanced chips it is one instruction always. ATTENTION: unlike enhanced chips SREG (S,V,N,Z,C) flags are changed in case of 'Z+' dst. R0 is scratch. */ .macro X_lpm dst=r0, src=Z /* dst evaluation */ REGNO .L__lpm_dst, \dst .if .L__lpm_dst < 0 .exitm ; do not multiply errors .endif /* src evaluation */ .L__lpm_src = -1 .L__lpm_n = 0 .irp reg, z,Z,z+,Z+ .ifc \reg,\src .L__lpm_src = .L__lpm_n .endif .L__lpm_n = .L__lpm_n + 1 .endr .if (.L__lpm_src < 0) .err ; Invalid src arg of 'X_lpm' macro. .endif /* instruction(s) */ .if .L__lpm_src < 2 .if .L__lpm_dst == 0 lpm .else #if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ lpm .L__lpm_dst, Z #else lpm mov .L__lpm_dst, r0 #endif .endif .else .if (.L__lpm_dst >= 30) .err ; Registers 30 and 31 are inhibited as 'X_lpm *,Z+' dst. .endif #if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ lpm .L__lpm_dst, Z+ #else lpm .if .L__lpm_dst mov .L__lpm_dst, r0 .endif adiw r30, 1 #endif .endif .endm /* X_lpm */ #endif /* !_ASMDEF_H */ avr-libc-1.8.0.orig/libm/fplib/isnan.S0000644000000000000000000000400611732702554014325 0ustar /* Copyright (c) 2002, Joerg Wunsch Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: isnan.S 1173 2007-01-14 15:04:40Z dmix $ */ #include "fp32def.h" #include "asmdef.h" /* int isnan (double) The isnan() function returns a non-zero value if value is "not-a-number" (NaN), and 0 otherwise. Notes: * It is implemented to save space, as there is a time effective isfinite() inline function. */ ENTRY isnan rcall _U(__fp_splitA) ldi r24, 0 ldi r25, 0 breq 1f ; Z = 1 for Normal or Inf adc r24, r24 1: ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/unordsf2.S0000644000000000000000000000367411732702554014771 0ustar /* Copyright (c) 2008 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: unordsf2.S 1652 2008-03-22 04:04:43Z dmix $ */ /* int __unordsf2 (float A, float B) This function returns a nonzero value if either argument is NaN, otherwise 0. As this function is not used often, speed is brocken to reduce size. */ #include "fp32def.h" #include "asmdef.h" ENTRY __unordsf2 rcall _U(__fp_cmp) ; return C=1, if any of args is NaN sbc r24, r24 sbc r25, r25 ret ENDFUNC avr-libc-1.8.0.orig/libm/fplib/log.S0000644000000000000000000001133611732702554014002 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: log.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* double log (double A) The log() function returns the natural logarithm of A. */ #define FL_M1 0xbf800000 /* -1.0 */ #define LN_2 0x3f317218 /* ln(2.0) = 0.69314718 */ #define rC3 YH #define rC2 YL /* adiw,sbiw are used */ #define rC1 r17 #define rC0 r16 #define rCE r15 FUNCTION log .L_nf: brts .L_nan ; branch, if -Inf rjmp _U(__fp_mpack) ; pass as is: NaN --> NaN, +Inf --> +Inf .L_nan: rjmp _U(__fp_nan) .L_min: set rjmp _U(__fp_inf) ENTRY log rcall _U(__fp_splitA) brcs .L_nf ; !isfinite(A) tst rA3 breq .L_min ; -Inf brts .L_nan ; log(negative) push rC3 push rC2 push rC1 push rC0 push rCE ; normalize (if Subnormal) mov rC2, rA3 ; place exponent to pair rC3.rC2 clr rC3 tst rA2 brmi 2f 1: sbiw rC2, 1 lsl rA0 rol rA1 rol rA2 brpl 1b 2: ; calculate log(1+x) for x: -0x0.20p+0 <= x < 0.E0p+0 /* Different tables are used: .L_tlow - for small values: -0x0.20p+0 <= x < + 0x0.18p+0 .L_thigh - for others */ ldi rB0, lo8(FL_M1) ldi rB1, hi8(FL_M1) ldi rB2, hlo8(FL_M1) ldi rB3, hhi8(FL_M1) ldi rA3, 0x3f cpi rA2, 0x98 brlo 3f cpi rA2, 0xE0 brlo 4f adiw rC2, 1 andi rA2, ~0x80 3: rcall _U(__addsf3) ldi ZL, lo8(.L_tlow) ldi ZH, hi8(.L_tlow) rjmp 5f 4: rcall _U(__addsf3) ldi ZL, lo8(.L_thigh) ldi ZH, hi8(.L_thigh) 5: rcall _U(__fp_powser) X_movw rC0, rA0 X_movw rA0, rC2 ; rA1.rA0 = exponent (possible negative) X_movw rC2, rA2 mov rCE, rAE ; calculate log() of exponent subi rA0, 127 ; 127 is exponent field of 1.0 sbc rA1, r1 asr rA1 rol rA1 ; C = rA1 sign bit sbc rA2, rA2 sbc rA3, rA3 rcall _U(__floatsisf) ldi rB0, lo8(LN_2) ldi rB1, hi8(LN_2) ldi rB2, hlo8(LN_2) ldi rB3, hhi8(LN_2) rcall _U(__mulsf3x) mov rBE, rCE X_movw rB0, rC0 X_movw rB2, rC2 pop rCE pop rC0 pop rC1 pop rC2 pop rC3 rcall _U(__addsf3x) rjmp _U(__fp_round) ENDFUNC PGM_SECTION .L_tlow: ; __fp_powser() table for small values .byte 8 .byte 0x00,0x00,0x00,0xbe ; -0.1250000000 .byte 0x92,0x24,0x49,0x12,0x3e ; 0.1428571429 .byte 0xab,0xaa,0xaa,0x2a,0xbe ; -0.1666666667 .byte 0xcd,0xcc,0xcc,0x4c,0x3e ; 0.2000000000 .byte 0x00,0x00,0x00,0x80,0xbe ; -0.2500000000 .byte 0xab,0xaa,0xaa,0xaa,0x3e ; 0.3333333333 .byte 0x00,0x00,0x00,0x00,0xbf ; -0.5000000000 .byte 0x00,0x00,0x00,0x80,0x3f ; 1.0000000000 .byte 0x00,0x00,0x00,0x00,0x00 ; 0.0000000000 .L_thigh: ; __fp_powser() table for other values .byte 8 .byte 0x41,0x78,0xd3,0xbb ; -0.0064535442 .byte 0x43,0x87,0xd1,0x13,0x3d ; 0.0360884937 .byte 0x19,0x0e,0x3c,0xc3,0xbd ; -0.0953293897 .byte 0x42,0x82,0xad,0x2b,0x3e ; 0.1676540711 .byte 0x68,0xec,0x82,0x76,0xbe ; -0.2407338084 .byte 0xd9,0x8f,0xe1,0xa9,0x3e ; 0.3317990258 .byte 0x4c,0x80,0xef,0xff,0xbe ; -0.4998741238 .byte 0x01,0xc4,0xff,0x7f,0x3f ; 0.9999964239 .byte 0x00,0x00,0x00,0x00,0x00 ; 0.0000000000 .end #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp_round.S0000644000000000000000000000451611732702554015037 0ustar /* Copyright (c) 2002 Michael Stumpf Copyright (c) 2006 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fp_round.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "fp32def.h" #include "asmdef.h" /* float __fp_round (); The __fp_round() function rounds an input number. This is an internal function intended to run after __addsf3x() and like. Input: rA3.rA2.rA1.rA0.rAE - number in the flt40_t format ZH - more lower bits are nonzero flag */ ENTRY __fp_round ; is A finite ? mov r0, rA3 inc r0 lsl r0 brne 1f tst rA2 brmi 3f ; no, A is not a finite number ; rounding 1: lsl rAE brcc 3f or rAE, ZH brne 2f sbrs rA0, 0 ; round to even rjmp 3f 2: subi rA0, -1 sbci rA1, -1 sbci rA2, -1 sbci rA3, -1 3: ret ENDFUNC #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libm/fplib/fp32def.h0000644000000000000000000000127111732702554014474 0ustar /* Interprocedure convensions. In separate file: for math library developers. */ #ifndef _FP32DEF_H #define _FP32DEF_H #include "sectionname.h" #define rB0 r18 #define rB1 r19 #define rB2 r20 #define rB3 r21 #define rA0 r22 #define rA1 r23 #define rA2 r24 #define rA3 r25 #define rBE r26 #define rAE r27 /* Put functions at this section. */ #ifdef FUNCTION # error "The FUNCTION macro must be defined after FUNC_SEGNAME" #endif #define FUNC_SEGNAME MLIB_SECTION /* Put constant tables at low addresses in program memory, so they are reachable for "lpm" without using RAMPZ on >64K devices. */ #define PGM_SECTION .section .progmem.gcc_fplib, "a", @progbits #endif /* !_FP32DEF_H */ avr-libc-1.8.0.orig/libm/Makefile.am0000644000000000000000000000315411732702554014034 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # SUBDIRS = fplib DIST_SUBDIRS = fplib avr-libc-1.8.0.orig/config.h.in0000644000000000000000000000116111732702554013074 0ustar /* config.h.in. Generated from configure.ac by autoheader. */ /* Name of package */ #undef PACKAGE /* Define to the address where bug reports for this package should be sent. */ #undef PACKAGE_BUGREPORT /* Define to the full name of this package. */ #undef PACKAGE_NAME /* Define to the full name and version of this package. */ #undef PACKAGE_STRING /* Define to the one symbol short name of this package. */ #undef PACKAGE_TARNAME /* Define to the home page for this package. */ #undef PACKAGE_URL /* Define to the version of this package. */ #undef PACKAGE_VERSION /* Version number of package */ #undef VERSION avr-libc-1.8.0.orig/libc/0000755000000000000000000000000011732702554011763 5ustar avr-libc-1.8.0.orig/libc/misc/0000755000000000000000000000000011732702554012716 5ustar avr-libc-1.8.0.orig/libc/misc/mulsi10.S0000644000000000000000000000515011732702554014335 0ustar /* Copyright (c) 2002, Reiner Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* mulsi10.S - optimized 32-bit multiply by 10 Contributors: Created by Reiner Patommel based on mul10.S by Marek Michalkiewicz */ #if !defined(__DOXYGEN__) #include "macros.inc" #define r_hi_hi r25 #define r_hi_lo r24 #define r_lo_hi r23 #define r_lo_lo r22 #define r_tmp_hi_hi r21 #define r_tmp_hi_lo r20 #define r_tmp_lo_hi r19 #define r_tmp_lo_lo r18 /* r_hi_hi:r_hi_lo:r_lo_hi:r_lo_lo *= 10 */ ASSEMBLY_CLIB_SECTION .global _U(__mulsi_const_10) _U(__mulsi_const_10): mov r_tmp_hi_hi, r_hi_hi mov r_tmp_hi_lo, r_hi_lo mov r_tmp_lo_hi, r_lo_hi mov r_tmp_lo_lo, r_lo_lo add r_lo_lo, r_lo_lo adc r_lo_hi, r_lo_hi adc r_hi_lo, r_hi_lo adc r_hi_hi, r_hi_hi ; d *= 2 add r_lo_lo, r_lo_lo adc r_lo_hi, r_lo_hi adc r_hi_lo, r_hi_lo adc r_hi_hi, r_hi_hi ; d *= 4 add r_lo_lo, r_tmp_lo_lo adc r_lo_hi, r_tmp_lo_hi adc r_hi_lo, r_tmp_hi_lo adc r_hi_hi, r_tmp_hi_hi ; d *= 5 add r_lo_lo, r_lo_lo adc r_lo_hi, r_lo_hi adc r_hi_lo, r_hi_lo adc r_hi_hi, r_hi_hi ; d *= 10 ret #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/ltoa.S0000644000000000000000000000736011732702554014007 0ustar /* Copyright (c) 2002, Reiner Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ltoa.S 1944 2009-04-01 23:12:20Z arcanum $ */ /* ltoa.S Contributors: Created by Reiner Patommel based on itoa.s by Michael Rickmann Changes: Reiner Patommel bug# 4010 #include char *ltoa(long int value, char *string, int radix); ---------------------------------------------------------------------- */ #if !defined(__DOXYGEN__) #include "macros.inc" #include "ctoasm.inc" ASSEMBLY_CLIB_SECTION .global _U(ltoa) .func _U(ltoa) /* function arguments */ #define a_val_hhi r25 #define a_val_hlo r24 #define a_val_hi r23 #define a_val_lo r22 #define a_str_hi r21 #define a_str_lo r20 #define a_radix_hi r19 #define a_radix r18 /* local variables */ #define r_radix r28 _U(ltoa): X_movw ZL, a_str_lo ; Z = &string push r28 ; save r28 push ZH ; keep &string push ZL cpi a_radix, 2 ; no radix < 2 brlt 99f ; return with \0 cpi a_radix, 37 ; no radix > 36 brge 99f ; return with \0 mov r_radix, a_radix; save radix clt ; make sure T flag is clear cpi r_radix, 10 ; decimal number? brne 1f bst a_val_hhi, 7 ; remember sign of decimal number brtc 1f ; number positive? -> convert com a_val_hhi ; make decimal number positive com a_val_hlo com a_val_hi neg a_val_lo sbci a_val_hi, lo8(-1) sbci a_val_hlo, lo8(-1) sbci a_val_hhi, lo8(-1) 1: mov r18, r_radix ; radix is divisor clr r19 ; remainder of number is dividend clr r20 clr r21 push ZH ; Z will be clobbered push ZL ; dividend in r25:r22, divisor in r21:r18 XCALL _U(__udivmodsi4); quotient in r21:r18, remainder in r25:r22 pop ZL pop ZH subi r22, 0xd0 ; + '0' cpi r22, 0x3a ; > '9' ? brlt 10f subi r22, 0xd9 ; + 'a' - 10 - '0' 10: st Z+, r22 ; write character to string in reverse order! X_movw a_val_lo, r18 ; quotient -> dividend X_movw a_val_hlo, r20 subi a_val_lo, 0 sbci a_val_hi, 0 sbci a_val_hlo, 0 sbci a_val_hhi,0 ; value == 0 ? brne 1b brtc 99f ; decimal number positive -> finish ldi r28, '-' st Z+, r28 ; write minus sign to string 99: st Z, __zero_reg__ ; terminate string pop a_val_hlo ; restore &string as return value pop a_val_hhi pop r28 ; restore r28 XJMP _U(strrev) ; reverse string .endfunc #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eerd_byte.S0000644000000000000000000000576311732702554015017 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eerd_byte.S 1979 2009-06-05 23:08:14Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* uint8_t eeprom_read_byte (uint8_t EEMEM *addr); */ #define ret_lo r24 #define ret_hi r25 ENTRY eeprom_read_byte #if __AVR_XMEGA__ /* -------------------------------------------- */ rcall eeprom_mapen ld ret_lo, Z clr ret_hi ret ENTRY eeprom_mapen ; Load base address of NVM. ldi ZL, lo8(NVM_BASE) ldi ZH, hi8(NVM_BASE) ; Wait until NVM is not busy. 1: ldd r19, Z + NVM_STATUS - NVM_BASE sbrc r19, NVM_NVMBUSY_bp rjmp 1b ; Enable EEPROM mapping into data space. ldd r19, Z + NVM_CTRLB - NVM_BASE ori r19, NVM_EEMAPEN_bm std Z + NVM_CTRLB - NVM_BASE, r19 ; Load Z with correct EEPROM address to read from data space. movw ZL, addr_lo subi ZL, lo8(-MAPPED_EEPROM_START) sbci ZH, hi8(-MAPPED_EEPROM_START) ret #else /* -------------------------------------------- */ 1: sbic _SFR_IO_ADDR (EECR), EEWE rjmp 1b # ifdef EEARH # if E2END > 0xFF out _SFR_IO_ADDR (EEARH), addr_hi # else ; This is for chips like ATmega48: the EEAR8 bit must be cleaned. out _SFR_IO_ADDR (EEARH), __zero_reg__ # endif # endif out _SFR_IO_ADDR (EEARL), addr_lo sbi _SFR_IO_ADDR (EECR), EERE clr ret_hi in ret_lo, _SFR_IO_ADDR (EEDR) ret #endif /* -------------------------------------------- */ ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eeupd_block.S0000644000000000000000000000461711732702554015326 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eeupd_block.S 1979 2009-06-05 23:08:14Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* void eeprom_update_block (const void *sram, void *eepr, size_t n) */ #define sram_lo r24 #define eepr_lo r22 ENTRY eeprom_update_block #if RAMEND > 0xFF || E2END > 0xFF X_movw XL, sram_lo add XL, n_lo adc XH, n_hi subi n_lo, lo8(1) sbci n_hi, hi8(1) #else mov XL, sram_lo add XL, n_lo subi n_lo, lo8(1) #endif brlo 3f #if E2END > 0xFF X_movw addr_lo, eepr_lo add addr_lo, n_lo adc addr_hi, n_hi #else mov addr_lo, eepr_lo add addr_lo, n_lo #endif 1: ld r18, -X XCALL eeprom_update_r18 2: subi n_lo, lo8(1) #if RAMEND > 0xFF || E2END > 0xFF sbci n_hi, hi8(1) #endif brsh 1b 3: ret ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eewr_block.S0000644000000000000000000000436111732702554015162 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eewr_block.S 1979 2009-06-05 23:08:14Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* void eeprom_write_block (const void *sram, void *eepr, size_t n) */ #define sram_lo r24 /* SRAM address */ #define eepr_lo r22 /* EEPROM address */ ENTRY eeprom_write_block #if RAMEND > 0xFF X_movw XL, sram_lo #else mov XL, sram_lo #endif #if E2END > 0xFF X_movw addr_lo, eepr_lo #else mov addr_lo, eepr_lo #endif rjmp 2f 1: ld r18, X+ XCALL eeprom_write_r18 2: subi n_lo, lo8(1) #if E2END > 0xFF sbci n_hi, hi8(1) #endif brsh 1b ret ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/mul10.S0000644000000000000000000000457411732702554014012 0ustar /* Copyright (c) 2002, 2006, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* mul10.S - optimized 16-bit multiply by 10 Contributors: Created by Marek Michalkiewicz */ #if !defined(__DOXYGEN__) #include "macros.inc" #define r_hi r25 #define r_lo r24 #define r_tmp2 r23 #define r_tmp_lo r22 #define r_tmp_hi r23 /* r_hi:r_lo *= 10 Optimized version, without calling __mulhi3 (which is slow for non-enhanced core, and not present in libgcc.a for enhanced core). */ ASSEMBLY_CLIB_SECTION .global _U(__mulhi_const_10) _U(__mulhi_const_10): #if defined(__AVR_HAVE_MUL__) ldi r_tmp2,10 mul r_hi,r_tmp2 mov r_hi,r0 mul r_lo,r_tmp2 mov r_lo,r0 add r_hi,r1 clr r1 ; __zero_reg__ #else X_movw r_tmp_lo, r_lo add r_lo,r_lo adc r_hi,r_hi add r_lo,r_lo adc r_hi,r_hi add r_lo, r_tmp_lo adc r_hi, r_tmp_hi add r_lo,r_lo adc r_hi,r_hi #endif ret #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eewr_byte.S0000644000000000000000000001156511732702554015037 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eewr_byte.S 2024 2009-09-10 01:39:42Z dmix $ */ #ifndef __DOXYGEN #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" ENTRY eeprom_write_byte mov r18, r22 ENTRY eeprom_write_r18 #if __AVR_XMEGA__ /* -------------------------------------------- */ # ifndef CCP_IOREG_gc # define CCP_IOREG_gc 0xD8 /* IO Register Protection */ # endif # ifndef NVM_CMD_READ_EEPROM_gc # define NVM_CMD_READ_EEPROM_gc 0x06 # endif # ifndef NVM_CMD_LOAD_EEPROM_BUFFER_gc # define NVM_CMD_LOAD_EEPROM_BUFFER_gc 0x33 # endif # ifndef NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc # define NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc 0x35 # endif # ifndef NVM_CMD_ERASE_EEPROM_BUFFER_gc # define NVM_CMD_ERASE_EEPROM_BUFFER_gc 0x36 # endif ; Prepare base address of NVM. ldi ZL, lo8(NVM_BASE) ldi ZH, hi8(NVM_BASE) ; Wait until NVM is not busy. 1: ldd r19, Z + NVM_STATUS - NVM_BASE sbrc r19, NVM_NVMBUSY_bp rjmp 1b ; Disable EEPROM mapping into data space. ldd r19, Z + NVM_CTRLB - NVM_BASE andi r19, ~NVM_EEMAPEN_bm std Z + NVM_CTRLB - NVM_BASE, r19 ; Check the clearance of EEPROM page buffer. ldd r19, Z + NVM_STATUS - NVM_BASE sbrs r19, NVM_EELOAD_bp rjmp 3f ; erase is not required ; Note that we have only four clock cycles to write to the CCP ; protected register NVM_CTRLA, after writing to CCP. The 'ldi' ; instruction always takes one clock to execute and 'std' instruction takes ; two clock cycles. We fall within the four cycles that the CCP leaves ; us to write the command execution start bit to the NVM_CTRLA ; register. Note that r18 must be preserved until written to NVM_DATA0 ; Issue EEPROM Buffer Erase: ldi r19, NVM_CMD_ERASE_EEPROM_BUFFER_gc std Z + NVM_CMD - NVM_BASE, r19 ldi r19, CCP_IOREG_gc out CCP, r19 ldi r19, NVM_CMDEX_bm std Z + NVM_CTRLA - NVM_BASE, r19 ; Wait until NVM is not busy. 2: ldd r19, Z + NVM_STATUS - NVM_BASE sbrc r19, NVM_NVMBUSY_bp rjmp 2b ; Issue EEPROM Buffer Load command. 3: ldi r19, NVM_CMD_LOAD_EEPROM_BUFFER_gc std Z + NVM_CMD - NVM_BASE, r19 std Z + NVM_ADDR0 - NVM_BASE, addr_lo std Z + NVM_ADDR1 - NVM_BASE, addr_hi std Z + NVM_ADDR2 - NVM_BASE, __zero_reg__ std Z + NVM_DATA0 - NVM_BASE, r18 ; Issue EEPROM Erase & Write command. ldi r18, NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc std Z + NVM_CMD - NVM_BASE, r18 ldi r18, CCP_IOREG_gc ldi r19, NVM_CMDEX_bm out CCP, r18 std Z + NVM_CTRLA - NVM_BASE, r19 ; Increment address. adiw addr_lo, 1 ret #else /* ---------------------------------------------------- */ 1: sbic _SFR_IO_ADDR (EECR), EEWE rjmp 1b # if defined (EEPM0) && defined (EEPM1) ; Set programming mode: erase and write. out _SFR_IO_ADDR (EECR), __zero_reg__ # elif defined (EEPM0) || defined (EEPM1) # error /* Unknown EECR register. */ # endif # ifdef EEARH # if E2END > 0xFF out _SFR_IO_ADDR (EEARH), addr_hi # else ; This is for chips like ATmega48: the EEAR8 bit must be cleaned. out _SFR_IO_ADDR (EEARH), __zero_reg__ # endif # endif out _SFR_IO_ADDR (EEARL), addr_lo out _SFR_IO_ADDR (EEDR), r18 in __tmp_reg__, _SFR_IO_ADDR (SREG) cli sbi _SFR_IO_ADDR (EECR), EEMWE sbi _SFR_IO_ADDR (EECR), EEWE out _SFR_IO_ADDR (SREG), __tmp_reg__ adiw addr_lo, 1 ret #endif /* ---------------------------------------------------- */ ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eerd_block.S0000644000000000000000000001012311732702554015130 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eerd_block.S 2003 2009-06-27 05:13:00Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* void eeprom_read_block (void *sram, const void *eepr, size_t n) Input: sram - SRAM address (dst) eepr - EEPROM address (src) n - number of bytes to read void eeprom_read_blraw (const void *addr, X-pointer, size_t n) This is an internal function to obtain the word/dword reading. Input: addr - EEPROM address - SRAM (or register) address n - number of bytes This function can write result into r25..r22 with ST command. It is absent in case of XMEGA chips. */ #define sram_lo r24 /* SRAM address arg of eeprom_read_block() */ #define eepr_lo r22 /* EEPROM address arg of eeprom_read_block() */ #define eepr_hi r23 ENTRY eeprom_read_block #if __AVR_XMEGA__ /* -------------------------------------------- */ ; Load base address of NVM. ldi ZL, lo8(NVM_BASE) ldi ZH, hi8(NVM_BASE) ; Wait until NVM is not busy. 1: ldd XL, Z + NVM_STATUS - NVM_BASE sbrc XL, NVM_NVMBUSY_bp rjmp 1b ; Enable EEPROM mapping into data space. ldd XL, Z + NVM_CTRLB - NVM_BASE ori XL, NVM_EEMAPEN_bm std Z + NVM_CTRLB - NVM_BASE, XL ; Correct EEPROM address to read from data space. subi eepr_lo, lo8(-MAPPED_EEPROM_START) sbci eepr_hi, hi8(-MAPPED_EEPROM_START) ; Perform reading. XJMP memcpy #elif E2END <= 0xFF /* -------------------------------------------- */ # if RAMEND <= 0xFF mov XL, sram_lo # else X_movw XL, sram_lo # endif mov addr_lo, eepr_lo ENTRY eeprom_read_blraw mov ZL, addr_lo 1: sbic _SFR_IO_ADDR (EECR), EEWE rjmp 1b # ifdef EEARH ; This is for chips like ATmega48: the EEAR8 bit must be cleaned. out _SFR_IO_ADDR (EEARH), __zero_reg__ # endif rjmp 3f 2: out _SFR_IO_ADDR (EEARL), ZL sbi _SFR_IO_ADDR (EECR), EERE inc ZL in __tmp_reg__, _SFR_IO_ADDR (EEDR) st X+, __tmp_reg__ 3: subi n_lo, lo8(1) brsh 2b ret #else /* ------------------------------------------------------------ */ ENTRY eeprom_read_block X_movw XL, sram_lo X_movw addr_lo, eepr_lo ENTRY eeprom_read_blraw X_movw ZL, addr_lo 1: sbic _SFR_IO_ADDR (EECR), EEWE rjmp 1b rjmp 3f 2: out _SFR_IO_ADDR (EEARH), ZH out _SFR_IO_ADDR (EEARL), ZL sbi _SFR_IO_ADDR (EECR), EERE adiw ZL, 1 in __tmp_reg__, _SFR_IO_ADDR (EEDR) st X+, __tmp_reg__ 3: subi n_lo, lo8(1) sbci n_hi, hi8(1) brsh 2b ret #endif /* ------------------------------------------------------------ */ ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eeupd_word.S0000644000000000000000000000374611732702554015211 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eeupd_word.S 1979 2009-06-05 23:08:14Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* void eeprom_update_word (uint16_t *addr, uint16 val); */ ENTRY eeprom_update_word adiw addr_lo, 1 mov r18, r23 ; val_hi XCALL eeprom_update_r18 XJMP eeprom_update_byte ; val_lo ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/Makefile.in0000644000000000000000000003177511732702554015000 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 1981 2009-06-05 23:13:29Z dmix $ # # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) 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pdf: pdf-am pdf-am: ps: ps-am ps-am: uninstall-am: .MAKE: install-am install-strip .PHONY: all all-am check check-am clean clean-generic distclean \ distclean-generic distdir dvi dvi-am html html-am info info-am \ install install-am install-data install-data-am install-dvi \ install-dvi-am install-exec install-exec-am install-html \ install-html-am install-info install-info-am install-man \ install-pdf install-pdf-am install-ps install-ps-am \ install-strip installcheck installcheck-am installdirs \ maintainer-clean maintainer-clean-generic mostlyclean \ mostlyclean-generic pdf pdf-am ps ps-am uninstall uninstall-am # vim: set ft=make: # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: avr-libc-1.8.0.orig/libc/misc/utoa.S0000644000000000000000000000612011732702554014011 0ustar /* Copyright (c) 2002, Reiner Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: utoa.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* utoa.S Contributors: Created by Reiner Patommel based on itoa.s by Michael Rickmann 19 June 2003 changed by Reiner Patommel bug# 4010 #include char *utoa(unsigned int value, char *string, int radix); ---------------------------------------------------------------------- */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #include "ctoasm.inc" ASSEMBLY_CLIB_SECTION .global _U(utoa) .func _U(utoa) /* arguments */ #define r_val_hi r25 #define r_val_lo r24 #define r_str_hi r23 #define r_str_lo r22 #define r_radix r20 /* local variables */ #define r_lstr_hi r19 #define r_lstr_lo r18 _U(utoa): X_movw ZL, r_str_lo ; &string X_movw r_lstr_lo, ZL ; save &string cpi r_radix, 2 ; no radix < 2 brlt 99f cpi r_radix, 37 ; no radix > 36 brge 99f 1: mov r22, r_radix ; radix clr r23 ; dividend in r25:r24, divisor in r23:r22 XCALL _U(__udivmodhi4); quotient in r23:r22, remainder in r25:r24 ; clobbered: r0, r21, r26, r27 ; call-used but preserved: r18,r19,r20,r30,r31 subi r24, 0xd0 ; + '0' cpi r24, 0x3a ; > '9' ? brlt 10f subi r24, 0xd9 ; + 'a' - 10 - '0' 10: st Z+, r24 ; write char to string in reverse order! X_movw r_val_lo,r22 ; quotient -> dividend sbiw r_val_lo,0 ; value == 0 ? brne 1b 99: st Z, __zero_reg__ ; terminate string X_movw r_val_lo, r_lstr_lo ; restore &string as return value XJMP _U(strrev) ; reverse string .endfunc #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/misc/eewr_dword.S0000644000000000000000000000413311732702554015204 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eewr_dword.S 1979 2009-06-05 23:08:14Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* void eeprom_write_dword (uint32_t *addr, uint32 val); void eeprom_write_float (float *addr, float val); */ ENTRY eeprom_write_dword ENTRY eeprom_write_float mov r18, r20 ; val_lo XCALL eeprom_write_r18 mov r18, r21 ; val_hi XCALL eeprom_write_r18 XJMP eeprom_write_word ; val_hlo, val_hhi ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/itoa.S0000644000000000000000000000705111732702554014001 0ustar /* Copyright (c) 2000, 2001, 2002, Michael Rickmann All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: itoa.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* itoa.S Copyright (C) 2000 Michael Rickmann Changes: Reiner Patommel (no stack space used anymore) Changes: Reiner Patommel bug# 4010 #include char *itoa(int value, char *string, int radix); ---------------------------------------------------------------------- */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #include "ctoasm.inc" ASSEMBLY_CLIB_SECTION .global _U(itoa) .func _U(itoa) /* arguments */ #define r_val_hi r25 #define r_val_lo r24 #define r_str_hi r23 #define r_str_lo r22 #define r_radix r20 /* local variables */ #define r_lstr_hi r19 #define r_lstr_lo r18 _U(itoa): X_movw ZL, r_str_lo ; &string X_movw r_lstr_lo, ZL ; save &string clt ; make sure T flag is clear cpi r_radix, 2 ; no radix < 2 brlt 99f ; return with \0 cpi r_radix, 37 ; no radix > 36 brge 99f ; return with \0 cpi r_radix, 10 ; decimal number ? brne 1f ; no -> convert bst r_val_hi, 7 ; for decimal numbers remember sign of value brtc 1f ; positive number -> convert com r_val_hi ; negative number -> make positive neg r_val_lo sbci r_val_hi, 0xff 1: mov r22, r_radix ; radix clr r23 ; dividend in r25:r24, divisor in r23:r22 XCALL _U(__udivmodhi4); quotient in r23:r22, remainder in r25:r24 ; clobbered: r0, r21, r26, r27 ; call-used but preserved: r18, r19, r20, r30, r31 subi r24, 0xd0 ; + '0' cpi r24, 0x3a ; > '9' ? brlt 10f subi r24, 0xd9 ; + 'a' - 10 - '0' 10: st Z+, r24 ; write char to string in reverse order X_movw r_val_lo, r22 ; quotient -> dividend sbiw r_val_lo, 0 ; value == 0 ? brne 1b brtc 99f ; T flag clear? -> positive number ldi r21, '-' st Z+, r21 ; write minus sign to string 99: st Z, __zero_reg__ ; terminate string X_movw r_val_lo, r_lstr_lo ; restore &string as return value XJMP _U(strrev) ; reverse string .endfunc #endif /* not __DOXYGEN__ */ #endif /*!defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/misc/eerd_dword.S0000644000000000000000000000434211732702554015163 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eerd_dword.S 1979 2009-06-05 23:08:14Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* uint32_t eeprom_read_dword (const uint32_t *addr); float eeprom_read_float (const float *addr); */ ENTRY eeprom_read_dword ENTRY eeprom_read_float #if __AVR_XMEGA__ XCALL eeprom_mapen ld r22, Z ldd r23, Z+1 ldd r24, Z+2 ldd r25, Z+3 ret #else ldi XL, 22 ; start address to write: r22 # if RAMEND > 0xFF ldi XH, 0 # endif ldi n_lo, lo8(4) # if E2END > 0xFF ldi n_hi, hi8(4) # endif XJMP eeprom_read_blraw #endif ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eedef.h0000644000000000000000000000601011732702554014134 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eedef.h 1983 2009-06-05 23:16:05Z dmix $ */ #ifndef _EEDEF_H_ #define _EEDEF_H_ 1 #ifndef __DOXYGEN__ /* Internal functions redefinition. */ #define eeprom_read_blraw _EEPROM_CONCAT2 (__eerd_blraw, _EEPROM_SUFFIX) #define eeprom_write_r18 _EEPROM_CONCAT2 (__eewr_r18, _EEPROM_SUFFIX) #define eeprom_update_r18 _EEPROM_CONCAT2 (__eeupd_r18, _EEPROM_SUFFIX) /* EEPROM address arg for a set of byte/word/dword functions and for the internal eeprom_read_blraw(). */ #define addr_lo r24 #define addr_hi r25 /* Number of bytes arg for all block read/write functions, include internal. */ #define n_lo r20 #define n_hi r21 #if __AVR_XMEGA__ # define NVM_BASE NVM_ADDR0 #else # if !defined (EECR) && defined (DEECR) /* AT86RF401 */ # define EECR DEECR # define EEARL DEEAR # define EEDR DEEDR # endif # if !defined (EERE) && defined (EER) /* AT86RF401 */ # define EERE EER # endif # if !defined (EEWE) && defined (EEPE) /* A part of Mega and Tiny */ # define EEWE EEPE # endif # if !defined (EEWE) && defined (EEL) /* AT86RF401 */ # define EEWE EEL # endif # if !defined (EEMWE) && defined (EEMPE) /* A part of Mega and Tiny */ # define EEMWE EEMPE # endif # if !defined (EEMWE) && defined (EEU) /* AT86RF401 */ # define EEMWE EEU # endif # if !_SFR_IO_REG_P (EECR) \ || !_SFR_IO_REG_P (EEDR) \ || !_SFR_IO_REG_P (EEARL) \ || (defined (EEARH) && !_SFR_IO_REG_P (EEARH)) # error # endif #endif /* !__AVR_XMEGA__ */ #endif /* !__DOXYGEN__ */ #endif /* !_EEDEF_H_ */ avr-libc-1.8.0.orig/libc/misc/Files.am0000644000000000000000000000371011732702554014300 0ustar # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # misc_a_c_sources = eeprom_asm_sources = \ eerd_block.S \ eerd_byte.S \ eerd_dword.S \ eerd_word.S \ eeupd_block.S \ eeupd_byte.S \ eeupd_dword.S \ eeupd_word.S \ eewr_block.S \ eewr_byte.S \ eewr_dword.S \ eewr_word.S misc_a_asm_sources = \ itoa.S \ ltoa.S \ mulsi10.S \ mul10.S \ ultoa.S \ utoa.S misc_a_extra_dist = \ eedef.h \ readme_eeprom.txt # vim: set ft=make: avr-libc-1.8.0.orig/libc/misc/Rules.am0000644000000000000000000000614011732702554014330 0ustar # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ include $(top_srcdir)/libc/misc/Files.am # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ $(addsuffix $(dev),$(eeprom_asm_basenames2))) eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) misc_a_libadd = \ $(eeprom_asm_objlist) # Example of '-mmcu' arg generation: # $@ --> eerd_byte_atmega48.o # basename --> eerd_byte_atmega48 # subst --> eerd byte atmega48 # lastword --> atmega48 # # Example of source file generation: # $@ --> eerd_byte_atmega48.o # basename --> eerd_byte_atmega48 # subst --> eerd.byte.atmega48 # basename --> eerd.byte # subst --> eerd_byte # addsuffix --> eerd_byte.S # $(eeprom_asm_objlist): $(eeprom_asm_sources) $(filter-out -mmcu=%,$(COMPILE) $(AVRLIB_ASFLAGS)) -c -o $@ \ -mmcu=$(lastword $(subst _, ,$(basename $@))) \ $( 19 June 2003 changed by Reiner Patommel bug# 4010 #include char *ultoa(unsigned long int value, char *string, int radix); ---------------------------------------------------------------------- */ #if !defined(__DOXYGEN__) #include "macros.inc" #include "ctoasm.inc" ASSEMBLY_CLIB_SECTION .global _U(ultoa) .func _U(ultoa) /* function arguments */ #define a_val_hhi r25 #define a_val_hlo r24 #define a_val_hi r23 #define a_val_lo r22 #define a_str_hi r21 #define a_str_lo r20 #define a_radix_hi r19 #define a_radix r18 /* local variables */ #define r_radix r28 _U(ultoa): X_movw ZL, a_str_lo ; Z = &string push r28 ; save r28 push ZH ; keep &string push ZL cpi a_radix, 2 ; no radix < 2 brlt 99f ; return with \0 cpi a_radix, 37 ; no radix > 36 brge 99f ; return with \0 mov r_radix, a_radix; save radix 1: mov r18, r_radix ; radix is divisor clr r19 ; remainder of number is dividend clr r20 clr r21 push ZH ; Z will be clobbered push ZL ; dividend in r25:r22, divisor in r21:r18 XCALL _U(__udivmodsi4); quotient in r21:r18, remainder in r25:r22 pop ZL pop ZH subi r22, 0xd0 ; + '0' cpi r22, 0x3a ; > '9' ? brlt 10f subi r22, 0xd9 ; + 'a' - 10 - '0' 10: st Z+, r22 ; write character to string in reverse order! X_movw a_val_lo, r18 ; quotient -> dividend X_movw a_val_hlo, r20 subi a_val_lo, 0 sbci a_val_hi, 0 sbci a_val_hlo, 0 sbci a_val_hhi,0 ; value == 0 ? brne 1b 99: st Z, __zero_reg__ ; terminate string pop a_val_hlo ; restore &string as return value pop a_val_hhi pop r28 ; restore r28 XJMP _U(strrev) ; reverse string .endfunc #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eewr_word.S0000644000000000000000000000370711732702554015046 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eewr_word.S 1979 2009-06-05 23:08:14Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* void eeprom_write_word (uint16_t *addr, uint16 val); */ ENTRY eeprom_write_word XCALL eeprom_write_byte mov r18, r23 ; val_hi XJMP eeprom_write_r18 ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eerd_word.S0000644000000000000000000000417411732702554015022 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eerd_word.S 1979 2009-06-05 23:08:14Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* uint16_t eeprom_read_word (const uint16_t *addr); */ ENTRY eeprom_read_word #if __AVR_XMEGA__ XCALL eeprom_mapen ld r24, Z ldd r25, Z+1 ret #else ldi XL, 24 ; start address to write: r24 # if RAMEND > 0xFF ldi XH, 0 # endif ldi n_lo, lo8(2) # if E2END > 0xFF ldi n_hi, hi8(2) # endif XJMP eeprom_read_blraw #endif ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/Makefile.am0000644000000000000000000000333311732702554014754 0ustar # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 1981 2009-06-05 23:13:29Z dmix $ # include $(top_srcdir)/libc/misc/Files.am EXTRA_DIST = \ $(eeprom_asm_sources) \ $(misc_a_asm_sources) \ $(misc_a_c_sources) \ $(misc_a_extra_dist) avr-libc-1.8.0.orig/libc/misc/readme_eeprom.txt0000644000000000000000000000665711732702554016301 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ # $Id: readme_eeprom.txt 1979 2009-06-05 23:08:14Z dmix $ Register usage of internally-used functions, common archs: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ eeprom_read_blraw: Input: r27,r26 - data space address (destination) r25,r24 - EEPROM address r21,r20 - number of bytes Scratch: common call-used regs. eeprom_update_r18: Input: r18 - byte to write r25,r24 - EEPROM address Output: r25,r24 - decremented EEPROM address Scratch: r0 eeprom_update_byte: Input: r22 - byte to write r25,r24 - EEPROM address Output: r25,r24 - decremented EEPROM address Scratch: r18,r0 eeprom_write_r18: Input: r18 - byte to write r25,r24 - EEPROM address Output: r25,r24 - incremented EEPROM address Scratch: r0 eeprom_write_byte: Input: r22 - byte to write r25,r24 - EEPROM address Output: r25,r24 - incremented EEPROM address Scratch: r18,r0 Register usage of internally-used functions, XMEGA arch: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ eeprom_mapen: Input: r25,r24 - EEPROM address Output: ZH,ZL - EEPROM address + 0x2000 (to use mapping) Scratch: r19 eeprom_update_r18: Input: r18 - byte to write r25,r24 - EEPROM address Output: r25,r24 - decremented EEPROM address Scratch: r31,r30,r19,r18,r0 eeprom_update_byte: Input: r22 - byte to write r25,r24 - EEPROM address Output: r25,r24 - decremented EEPROM address Scratch: r31,r30,r19,r18,r0 eeprom_write_r18: Input: r18 - byte to write r25,r24 - EEPROM address Output: r25,r24 - incremented EEPROM address Scratch: r31,r30,r19,r18 eeprom_write_byte: Input: r22 - byte to write r25,r24 - EEPROM address Output: r25,r24 - incremented EEPROM address Scratch: r31,r30,r19,r18 avr-libc-1.8.0.orig/libc/misc/eeupd_dword.S0000644000000000000000000000423511732702554015347 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eeupd_dword.S 1979 2009-06-05 23:08:14Z dmix $ */ #ifndef __DOXYGEN__ #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* void eeprom_update_dword (uint32_t *addr, uint32 val); void eeprom_update_float (float *addr, float val); */ ENTRY eeprom_update_dword ENTRY eeprom_update_float adiw addr_lo, 3 mov r18, r23 ; val_hhi XCALL eeprom_update_r18 XCALL eeprom_update_byte ; val_hlo mov r18, r21 ; val_hi XCALL eeprom_update_r18 mov r18, r20 ; val_lo XJMP eeprom_update_r18 ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/misc/eeupd_byte.S0000644000000000000000000000611711732702554015174 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: eeupd_byte.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #ifndef __DOXYGEN #include #if E2END && __AVR_ARCH__ > 1 #include #include "asmdef.h" #include "eedef.h" /* void eeprom_update_byte (unsigned char *eepr, unsigned char val) void eeprom_update_r18 (unsigned char *eepr, r18) */ ENTRY eeprom_update_byte mov r18, r22 ENTRY eeprom_update_r18 #if __AVR_XMEGA__ XCALL eeprom_mapen ld __tmp_reg__, Z cp __tmp_reg__, r18 breq 1f XCALL eeprom_write_r18 sbiw addr_lo, 1 ; restore initial value 1: sbiw addr_lo, 1 ret #else 1: sbic _SFR_IO_ADDR (EECR), EEWE rjmp 1b # ifdef EEARH # if E2END > 0xFF out _SFR_IO_ADDR (EEARH), addr_hi # else ; This is for chips like ATmega48: the EEAR8 bit must be cleaned. out _SFR_IO_ADDR (EEARH), __zero_reg__ # endif # endif out _SFR_IO_ADDR (EEARL), addr_lo sbi _SFR_IO_ADDR (EECR), EERE # if E2END > 0xFF sbiw addr_lo, 1 # else subi addr_lo, 1 # endif in __tmp_reg__, _SFR_IO_ADDR (EEDR) cp __tmp_reg__, r18 breq 2f # if defined (EEPM0) && defined (EEPM1) ; Set programming mode: erase and write. out _SFR_IO_ADDR (EECR), __zero_reg__ # elif defined (EEPM0) || defined (EEPM1) # error /* Unknown EECR register. */ # endif out _SFR_IO_ADDR (EEDR), r18 in __tmp_reg__, _SFR_IO_ADDR (SREG) cli sbi _SFR_IO_ADDR (EECR), EEMWE sbi _SFR_IO_ADDR (EECR), EEWE out _SFR_IO_ADDR (SREG), __tmp_reg__ 2: ret #endif /* !__AVR_XMEGA__ */ ENDFUNC #endif /* E2END && __AVR_ARCH__ > 1 */ #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/0000755000000000000000000000000011732702554013626 5ustar avr-libc-1.8.0.orig/libc/pmstring/memcpy_P.S0000644000000000000000000000547111732702554015532 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memcpy_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn void *memcpy_P(void *dest, PGM_VOID_P src, size_t n) The memcpy_P() function is similar to memcpy(), except the src string resides in program space. \returns The memcpy_P() function returns a pointer to dest. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 #define len_hi r21 #define len_lo r20 ASSEMBLY_CLIB_SECTION .global _U(memcpy_P) .type _U(memcpy_P), @function _U(memcpy_P): X_movw ZL, src_lo X_movw XL, dest_lo #if OPTIMIZE_SPEED ; 17 words, (14 + len * 9 - (len & 1)) cycles sbrs len_lo, 0 rjmp .L_memcpy_P_start rjmp .L_memcpy_P_odd .L_memcpy_P_loop: X_lpm r0, Z+ st X+, r0 .L_memcpy_P_odd: X_lpm r0, Z+ st X+, r0 .L_memcpy_P_start: subi len_lo, lo8(2) sbci len_hi, hi8(2) #else ; 12 words, (13 + len * 11) cycles rjmp .L_memcpy_P_start .L_memcpy_P_loop: X_lpm r0, Z+ st X+, r0 .L_memcpy_P_start: subi len_lo, lo8(1) sbci len_hi, hi8(1) #endif brcc .L_memcpy_P_loop ; return dest (unchanged) ret .L_memcpy_P_end: .size _U(memcpy_P), .L_memcpy_P_end - _U(memcpy_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strcasecmp_PF.S0000644000000000000000000000666711732702554016522 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strcasecmp_P.S which is Copyright (c) 2002, Reiner Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcasecmp_PF.S 2192 2010-11-08 13:53:24Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define s1_b1 r25 #define s1_b0 r24 #define s2_b3 r23 #define s2_b2 r22 #define s2_b1 r21 #define s2_b0 r20 #define ret_b1 r25 #define ret_b0 r24 #define tmp s2_b1 /* copied to Z pointer */ #define cht s2_b0 /** \ingroup avr_pgmspace \fn int strcasecmp_PF (const char *s1, uint_farptr_t s2) \brief Compare two strings ignoring case The strcasecmp_PF() function compares the two strings \e s1 and \e s2, ignoring the case of the characters \param s1 A pointer to the first string in SRAM \param s2 A far pointer to the second string in Flash \returns The strcasecmp_PF() function returns an integer less than, equal to, or greater than zero if \e s1 is found, respectively, to be less than, to match, or be greater than \e s2. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(strcasecmp_PF) .type _U(strcasecmp_PF), @function _U(strcasecmp_PF): X_movw ZL, s2_b0 LPM_R0_ZPLUS_INIT s2_b2 X_movw XL, s1_b0 .L_strcasecmp_PF_loop: ld ret_b0, X+ ; load *s1 LPM_R0_ZPLUS_NEXT s2_b2 ; load *s2 mov tmp, r0 ; copy of *s2 to tmp mov cht, r0 ; copy of *s2 to cht ori cht, 0x20 ; make tmp lower case cpi cht, 'a' ; test on [a .. z] brlt .L_strcasecmp_PF_tst cpi cht, 'z'+1 brge .L_strcasecmp_PF_tst ori tmp, 0x20 ; we got an aplpha in s2 ori ret_b0, 0x20 .L_strcasecmp_PF_tst: ; compare sub ret_b0, tmp brne .L_strcasecmp_PF_done tst r0 ; end of s2? brne .L_strcasecmp_PF_loop .L_strcasecmp_PF_done: ; ret_hi = SREG.C ? 0xFF : 0 sbc ret_b1, ret_b1 ret .L_strcasecmp_PF_end: .size _U(strcasecmp_PF), .L_strcasecmp_PF_end - _U(strcasecmp_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strncasecmp_P.S0000644000000000000000000000711611732702554016560 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Reiner Patommel Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncasecmp_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* strncasecmp_P.S Case insensitive compare Contributors: Created by Reiner Patommel */ /** \file */ /** \ingroup avr_pgmspace \fn int strncasecmp_P(const char *s1, PGM_P s2, size_t n) \brief Compare two strings ignoring case. The strncasecmp_P() function is similar to strcasecmp_P(), except it only compares the first \p n characters of \p s1. \param s1 A pointer to a string in the devices SRAM. \param s2 A pointer to a string in the devices Flash. \param n The maximum number of bytes to compare. \returns The strncasecmp_P() function returns an integer less than, equal to, or greater than zero if \p s1 (or the first \p n bytes thereof) is found, respectively, to be less than, to match, or be greater than \p s2. A consequence of the ordering used by strncasecmp_P() is that if \p s1 is an initial substring of \p s2, then \p s1 is considered to be "less than" \p s2. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define len_hi r21 #define len_lo r20 #define tmp r22 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strncasecmp_P) .type _U(strncasecmp_P), @function _U(strncasecmp_P): X_movw ZL, s2_lo X_movw XL, s1_lo 1: subi len_lo, lo8(1) ; if (--len == -1) return 0 sbci len_hi, hi8(1) brlo 5f ld ret_lo, X+ ; *s1++ cpi ret_lo, 'A' ; if in [A-Z] then tolower() brlt 2f cpi ret_lo, 'Z'+1 brge 2f subi ret_lo, 'A'-'a' 2: X_lpm tmp, Z+ ; *s2++ cpi tmp, 'A' ; if in [A-Z] then tolower() brlt 3f cpi tmp, 'Z'+1 brge 3f subi tmp, 'A'-'a' 3: sub ret_lo, tmp ; compare cpse tmp, __zero_reg__ ; break, if end of string breq 1b 4: sbc ret_hi, ret_hi ; sign extension ret 5: sub ret_lo, ret_lo ; length limit, return 0 rjmp 4b .size _U(strncasecmp_P), . - _U(strncasecmp_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strchr_P.S0000644000000000000000000000542511732702554015544 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strchr_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn PGM_P strchr_P(PGM_P s, int val) \brief Locate character in program space string. The strchr_P() function locates the first occurrence of \p val (converted to a char) in the string pointed to by \p s in program space. The terminating null character is considered to be part of the string. The strchr_P() function is similar to strchr() except that \p s is pointer to a string in program space. \returns The strchr_P() function returns a pointer to the matched character or \c NULL if the character is not found. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define str_hi r25 #define str_lo r24 #define val_lo r22 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strchr_P) .type _U(strchr_P), @function _U(strchr_P): X_movw ZL, str_lo 1: X_lpm r0, Z+ cp r0, val_lo breq 2f tst r0 brne 1b ; not found, return NULL pointer X_movw ret_lo, r0 ret 2: sbiw ZL, 1 ; undo post-increment X_movw ret_lo, ZL ret .size _U(strchr_P), . - _U(strchr_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strlcat_P.S0000644000000000000000000000735311732702554015715 0ustar /* AVR LIBC strlcat_P() Copyright (c) 2003, 2005, 2006, 2007 Eric B. Weddington, R. Patommel Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlcat_P.S 2262 2011-12-24 00:38:34Z dmix $ */ /** \file */ /** \ingroup avr_pgmspace \fn size_t strlcat_P (char *dst, PGM_P src, size_t siz) \brief Concatenate two strings. The strlcat_P() function is similar to strlcat(), except that the \p src string must be located in program space (flash). Appends \p src to string \p dst of size \p siz (unlike strncat(), \p siz is the full size of \p dst, not space left). At most \p siz-1 characters will be copied. Always NULL terminates (unless \p siz <= \p strlen(dst)). \returns The strlcat_P() function returns strlen(src) + MIN(siz, strlen(initial dst)). If retval >= siz, truncation occurred. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" /* size_t strlcat (char *dst, const char *src, size_t siz) { char *d = dst; const char *s = src; do { if (--siz == ~0u) goto Len; // siz <= strlen(dst) } while (*d++); d -= 1; goto m; do { if (!(*d++ = *s++)) return (d - dst - 1); // normal end m: ; } while (--siz != ~0u); *d = 0; Len: return (d - dst + strlen (s)); } */ #define dst_lo r24 #define dst_hi r25 #define src_lo r22 #define src_hi r23 #define siz_lo r20 #define siz_hi r21 #define ret_lo r24 ENTRY strlcat_P X_movw XL, dst_lo ; X = dst X_movw ZL, src_lo ; Z = src ; find end of dst: X := dst + strlen(dsr) 1: subi siz_lo, lo8(1) sbci siz_hi, hi8(1) brlo .Len ; siz <= strlen(dst) ld __tmp_reg__, X+ tst __tmp_reg__ brne 1b sbiw XL, 1 rjmp 3f ; copy loop 2: X_lpm __tmp_reg__, Z+ st X+, __tmp_reg__ tst __tmp_reg__ breq .Ldd 3: subi siz_lo, lo8(1) sbci siz_hi, hi8(1) brsh 2b st X, __zero_reg__ ; return (d - dst + strlen(s)) X_movw src_lo, ZL ; update for strlen(s) calculation .Len: X_lpm __tmp_reg__, Z+ ; find end of src tst __tmp_reg__ brne .Len sub ZL, src_lo ; Z := strlen(s) + 1 sbc ZH, src_hi add XL, ZL ; d += strlen(s) + 1 adc XH, ZH .Ldd: sec ; d -= dst + 1 sbc XL, dst_lo sbc XH, dst_hi X_movw ret_lo, XL ; return value ret ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strnlen_PF.S0000644000000000000000000000626711732702554016037 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strnlen_P.S which is Copyright (c) 2005, Helmut Wallner based on libc/pmstring/strnlen.S which is Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strnlen_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define src_b3 r25 #define src_b2 r24 #define src_b1 r23 #define src_b0 r22 #define len_b1 r21 #define len_b0 r20 /** \ingroup avr_pgmspace \fn size_t strnlen_PF(uint_farptr_t s, size_t len) \brief Determine the length of a fixed-size string The strnlen_PF() function is similar to strnlen(), except that \e s is a far pointer to a string in program space \param s A far pointer to the string in Flash \param len The maximum number of length to return \returns The strnlen_PF function returns strlen_P(\e s), if that is less than \e len, or \e len if there is no '\\0' character among the first \e len characters pointed to by \e s. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(strnlen_PF) .type _U(strnlen_PF), @function _U(strnlen_PF): LPM_R0_ZPLUS_INIT src_b2 X_movw ZL, src_b0 .L_strnlen_PF_loop: LPM_R0_ZPLUS_NEXT src_b2 subi len_b0, lo8(1) sbci len_b1, hi8(1) cpse r0, __zero_reg__ brcc .L_strnlen_PF_loop ; RAMPZ:Z points one character past the terminating NUL ; return RAMPZ:Z - 1 - src = (-1 - src) + RAMPZ:Z = ~src + RAMPZ:Z com src_b0 com src_b1 add src_b0, ZL adc src_b1, ZH X_movw src_b2, src_b0 ; size_t is 16 bits ret .L_strnlen_PF_end: .size _U(strnlen_PF), .L_strnlen_PF_end - _U(strnlen_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/memcmp_PF.S0000644000000000000000000000651111732702554015620 0ustar /* Copyright (c) 2010 Jan Waclawek based on libc/pmstring/memcmp_P.S which is Copyright (c) 2002, 2007 Marek Michalkiewicz Copyright (c) 2007 Dmitry Xmelkov and on exteded program memory routines, which are Copyright (c) 2006, Carlos Lamas All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memcmp_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn int memcmp_PF(const void *s1, uint_farptr_t s2, size_t len) \brief Compare memory areas The memcmp_PF() function compares the first \p len bytes of the memory areas \p s1 and flash \p s2. The comparision is performed using unsigned char operations. It is an equivalent of memcmp_P() function, except that it is capable working on all FLASH including the exteded area above 64kB. \returns The memcmp_PF() function returns an integer less than, equal to, or greater than zero if the first \p len bytes of \p s1 is found, respectively, to be less than, to match, or be greater than the first \p len bytes of \p s2. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_b1 r25 #define s1_b0 r24 #define s2_b3 r23 #define s2_b2 r22 #define s2_b1 r21 #define s2_b0 r20 #define len_b1 r19 #define len_b0 r18 #define ret_b1 r25 #define ret_b0 r24 /* the conditional caters for pre-1.6.8 libc and standalone use */ #ifdef ASSEMBLY_CLIB_SECTION ASSEMBLY_CLIB_SECTION #else .text #endif .global _U(memcmp_PF) .type _U(memcmp_PF), @function _U(memcmp_PF): X_movw ZL, s2_b0 LPM_R0_ZPLUS_INIT s2_b2 X_movw XL, s1_b0 rjmp 2f 1: ld ret_b0, X+ LPM_R0_ZPLUS_NEXT s2_b2 sub ret_b0, r0 brne 3f 2: subi len_b0, lo8(1) sbci len_b1, hi8(1) brsh 1b sub ret_b0, ret_b0 3: sbc ret_b1, ret_b1 ret .size _U(memcmp_PF), . - _U(memcmp_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strlen_P.S0000644000000000000000000000542711732702554015550 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlen_P.S 2223 2011-02-23 18:15:04Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn size_t strlen_P(PGM_P src) The strlen_P() function is similar to strlen(), except that src is a pointer to a string in program space. \returns The strlen() function returns the number of characters in src. \note strlen_P() is implemented as an inline function in the avr/pgmspace.h header file, which will check if the length of the string is a constant and known at compile time. If it is not known at compile time, the macro will issue a call to __strlen_P() which will then calculate the length of the string as normal. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define src_hi r25 #define src_lo r24 ; 11 words, (14 + __strlen_P(src) * 8) cycles ASSEMBLY_CLIB_SECTION .global _U(__strlen_P) .type _U(__strlen_P), @function _U(__strlen_P): X_movw ZL, src_lo .L_strlen_P_loop: X_lpm r0, Z+ tst r0 brne .L_strlen_P_loop ; return Z - 1 - src = (-1 - src) + Z = ~src + Z com src_lo com src_hi add src_lo, ZL adc src_hi, ZH ret .L_strlen_P_end: .size _U(__strlen_P), .L_strlen_P_end - _U(__strlen_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strcpy_P.S0000644000000000000000000000471011732702554015557 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcpy_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn char *strcpy_P(char *dest, PGM_P src) The strcpy_P() function is similar to strcpy() except that src is a pointer to a string in program space. \returns The strcpy_P() function returns a pointer to the destination string dest. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 ; 10 words, (17 + strlen_P(src) * 10) cycles ASSEMBLY_CLIB_SECTION .global _U(strcpy_P) .type _U(strcpy_P), @function _U(strcpy_P): X_movw ZL, src_lo X_movw XL, dest_lo .L_strcpy_P_loop: X_lpm r0, Z+ st X+, r0 tst r0 brne .L_strcpy_P_loop ; return dest (unchanged) ret .L_strcpy_P_end: .size _U(strcpy_P), .L_strcpy_P_end - _U(strcpy_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strncasecmp_PF.S0000644000000000000000000000734311732702554016670 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strncasecmp_P.S which is Copyright (c) 2002, Reiner Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncasecmp_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define s1_b1 r25 #define s1_b0 r24 #define s2_b3 r23 #define s2_b2 r22 #define s2_b1 r21 #define s2_b0 r20 #define len_b1 r19 #define len_b0 r18 #define cht s2_b1 #define tmp s2_b0 #define ret_b1 r25 #define ret_b0 r24 /** \ingroup avr_pgmspace \fn int strncasecmp_PF (const char *s1, uint_farptr_t s2, size_t n) \brief Compare two strings ignoring case The strncasecmp_PF() function is similar to strcasecmp_PF(), except it only compares the first \e n characters of \e s1 and the string in flash is addressed using a far pointer \param s1 A pointer to a string in SRAM \param s2 A far pointer to a string in Flash \param n The maximum number of bytes to compare \returns The strncasecmp_PF() function returns an integer less than, equal to, or greater than zero if \e s1 (or the first \e n bytes thereof) is found, respectively, to be less than, to match, or be greater than \e s2. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(strncasecmp_PF) .type _U(strncasecmp_PF), @function _U(strncasecmp_PF): X_movw ZL, s2_b0 LPM_R0_ZPLUS_INIT s2_b2 X_movw XL, s1_b0 .L_strncasecmp_PF_loop: subi len_b0, lo8(1) sbci len_b1, hi8(1) brcs .L_strncasecmp_PF_equal ld ret_b0, X+ ; load *s1 LPM_R0_ZPLUS_NEXT s2_b2 ; load *s2 mov tmp, r0 ; copy of *s2 to tmp mov cht, r0 ; copy of *s2 to cht ori cht, 0x20 ; make it lower case cpi cht, 'a' ; test on [a .. z] brlt .L_strncasecmp_PF_tst cpi cht, 'z'+1 brge .L_strncasecmp_PF_tst ori tmp, 0x20 ; we got an alpha in s2 ori ret_b0, 0x20 ; make *s1, *s2 lower case .L_strncasecmp_PF_tst: sub ret_b0, tmp brne .L_strncasecmp_PF_done tst r0 brne .L_strncasecmp_PF_loop .L_strncasecmp_PF_equal: sub ret_b0, ret_b0 .L_strncasecmp_PF_done: ; ret_hi = SREG.C ? 0xFF : 0 sbc ret_b1, ret_b1 ret .L_strncasecmp_PF_end: .size _U(strncasecmp_PF), .L_strncasecmp_PF_end - _U(strncasecmp_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/Makefile.in0000644000000000000000000003245211732702554015701 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 2039 2009-11-08 06:03:42Z dmix $ # # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ $(top_srcdir)/libc/pmstring/Files.am subdir = libc/pmstring ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = SOURCES = DIST_SOURCES = DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = @ACLOCAL@ AMTAR = @AMTAR@ AR = @AR@ AS = @AS@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AVR_LIBC_MAJOR = @AVR_LIBC_MAJOR@ AVR_LIBC_MINOR = @AVR_LIBC_MINOR@ AVR_LIBC_RELDATE = @AVR_LIBC_RELDATE@ AVR_LIBC_REVISION = @AVR_LIBC_REVISION@ AVR_LIBC_USER_MANUAL = @AVR_LIBC_USER_MANUAL@ AVR_LIBC_VERSION = @AVR_LIBC_VERSION@ AVR_LIBC_VERSION_NUMERIC = @AVR_LIBC_VERSION_NUMERIC@ AWK = @AWK@ CC = @CC@ CCAS = @CCAS@ CCASDEPMODE = @CCASDEPMODE@ CCASFLAGS = @CCASFLAGS@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ CPPFLAGS = @CPPFLAGS@ CYGPATH_W = @CYGPATH_W@ DEFS = @DEFS@ DEPDIR = @DEPDIR@ DOCSDIR = @DOCSDIR@ DOC_INST_DIR = @DOC_INST_DIR@ ECHO_C = @ECHO_C@ ECHO_N = @ECHO_N@ ECHO_T = @ECHO_T@ EXEEXT = @EXEEXT@ FNO_JUMP_TABLES = @FNO_JUMP_TABLES@ HAS_DELAY_CYCLES = @HAS_DELAY_CYCLES@ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_DOX_HTML = @INSTALL_DOX_HTML@ INSTALL_DOX_MAN = @INSTALL_DOX_MAN@ INSTALL_DOX_PDF = @INSTALL_DOX_PDF@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_SCRIPT = @INSTALL_SCRIPT@ INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ LDFLAGS = @LDFLAGS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAKEINFO = @MAKEINFO@ MKDIR_P = @MKDIR_P@ OBJEXT = @OBJEXT@ PACKAGE = @PACKAGE@ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ PACKAGE_NAME = @PACKAGE_NAME@ PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_URL = @PACKAGE_URL@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ PNGTOPNM = @PNGTOPNM@ PNMTOPNG = @PNMTOPNG@ RANLIB = @RANLIB@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ TARGET_DOX_HTML = @TARGET_DOX_HTML@ TARGET_DOX_PDF = @TARGET_DOX_PDF@ VERSION = @VERSION@ abs_builddir = @abs_builddir@ abs_srcdir = @abs_srcdir@ abs_top_builddir = @abs_top_builddir@ abs_top_srcdir = @abs_top_srcdir@ ac_ct_CC = @ac_ct_CC@ am__include = @am__include@ am__leading_dot = @am__leading_dot@ am__quote = @am__quote@ am__tar = @am__tar@ am__untar = @am__untar@ bindir = @bindir@ build = @build@ build_alias = @build_alias@ build_cpu = @build_cpu@ build_os = @build_os@ build_vendor = @build_vendor@ builddir = @builddir@ datadir = @datadir@ datarootdir = @datarootdir@ docdir = @docdir@ dvidir = @dvidir@ exec_prefix = @exec_prefix@ host = @host@ host_alias = @host_alias@ host_cpu = @host_cpu@ host_os = @host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ pmstring_a_c_sources = \ strtok_P.c pmstring_a_asm_sources = \ memchr_P.S \ memcmp_P.S \ memccpy_P.S \ memcpy_P.S \ memrchr_P.S \ strcasecmp_P.S \ strcat_P.S \ strchr_P.S \ strchrnul_P.S \ strcmp_P.S \ strcpy_P.S \ strcspn_P.S \ strlcat_P.S \ strlcpy_P.S \ strlen_P.S \ strncasecmp_P.S \ strncat_P.S \ strncmp_P.S \ strncpy_P.S \ strnlen_P.S \ strpbrk_P.S \ strrchr_P.S \ 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limit (for SysV at least) may be exceeded. .NOEXPORT: avr-libc-1.8.0.orig/libc/pmstring/strncmp_PF.S0000644000000000000000000000640311732702554016030 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strncmp_P.S which is Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncmp_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define s1_b1 r25 #define s1_b0 r24 #define s2_b3 r23 #define s2_b2 r22 #define s2_b1 r21 #define s2_b0 r20 #define len_b1 r19 #define len_b0 r18 #define ret_b1 r25 #define ret_b0 r24 /** \ingroup avr_pgmspace \fn int strncmp_PF (const char *s1, uint_farptr_t s2, size_t n) \brief Compare two strings with limited length The strncmp_PF() function is similar to strcmp_PF() except it only compares the first (at most) \e n characters of \e s1 and \e s2 \param s1 A pointer to the first string in SRAM \param s2 A far pointer to the second string in Flash \param n The maximum number of bytes to compare \returns The strncmp_PF() function returns an integer less than, equal to, or greater than zero if \e s1 (or the first \e n bytes thereof) is found, respectively, to be less than, to match, or be greater than \e s2. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(strncmp_PF) .type _U(strncmp_PF), @function _U(strncmp_PF): X_movw ZL, s2_b0 LPM_R0_ZPLUS_INIT s2_b2 X_movw XL, s1_b0 .L_strncmp_PF_loop: subi len_b0, lo8(1) sbci len_b1, hi8(1) brcs .L_strncmp_PF_equal ld ret_b0, X+ LPM_R0_ZPLUS_NEXT s2_b2 sub ret_b0, r0 brne .L_strncmp_PF_done tst r0 brne .L_strncmp_PF_loop .L_strncmp_PF_equal: sub ret_b0, ret_b0 .L_strncmp_PF_done: ; ret_hi = SREG.C ? 0xFF : 0 sbc ret_b1, ret_b1 ret .L_strncmp_PF_end: .size _U(strncmp_PF), .L_strncmp_PF_end - _U(strncmp_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/memcpy_PF.S0000644000000000000000000000633211732702554015635 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/memcpy_P.S which is Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memcpy_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define dest_b1 r25 #define dest_b0 r24 #define src_b3 r23 #define src_b2 r22 #define src_b1 r21 #define src_b0 r20 #define len_b1 r19 #define len_b0 r18 /** \ingroup avr_pgmspace \fn void *memcpy_PF (void *dest, uint_farptr_t src, size_t n) \brief Copy a memory block from flash to SRAM The memcpy_PF() function is similar to memcpy(), except the data is copied from the program space and is addressed using a far pointer \param dst A pointer to the destination buffer \param src A far pointer to the origin of data in flash memory \param n The number of bytes to be copied \returns The memcpy_PF() function returns a pointer to \e dst. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(memcpy_PF) .type _U(memcpy_PF), @function _U(memcpy_PF): LPM_R0_ZPLUS_INIT src_b2 X_movw ZL, src_b0 X_movw XL, dest_b0 #if OPTIMIZE_SPEED sbrs len_b0, 0 rjmp .L_memcpy_PF_start rjmp .L_memcpy_PF_odd .L_memcpy_PF_loop: LPM_R0_ZPLUS_NEXT src_b2 st X+, r0 .L_memcpy_PF_odd: LPM_R0_ZPLUS_NEXT src_b2 st X+, r0 .L_memcpy_PF_start: subi len_b0, lo8(2) sbci len_b1, hi8(2) #else rjmp .L_memcpy_PF_start .L_memcpy_PF_loop: LPM_R0_ZPLUS_NEXT src_b2 st X+, r0 .L_memcpy_PF_start: subi len_b0, lo8(1) sbci len_b1, hi8(1) #endif brcc .L_memcpy_PF_loop ; return dest (unchanged) ret .L_memcpy_PF_end: .size _U(memcpy_PF), .L_memcpy_PF_end - _U(memcpy_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/memccpy_P.S0000644000000000000000000000317511732702554015674 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memccpy_P.S 2054 2009-11-15 06:31:31Z dmix $ */ #define Lprogmem 1 #include "../string/memccpy.S" avr-libc-1.8.0.orig/libc/pmstring/strlen_PF.S0000644000000000000000000000541711732702554015655 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strlen_P.S which is Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlen_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define src_b3 r25 /* MSB, ignored */ #define src_b2 r24 #define src_b1 r23 #define src_b0 r22 /** \ingroup avr_pgmspace \fn size_t strlen_PF (uint_farptr_t s) \brief Obtain the length of a string The strlen_PF() function is similar to strlen(), except that \e s is a far pointer to a string in program space \param s A far pointer to the string in flash \returns The strlen_PF() function returns the number of characters in \e s. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(strlen_PF) .type _U(strlen_PF), @function _U(strlen_PF): LPM_R0_ZPLUS_INIT src_b2 X_movw ZL, src_b0 .L_strlen_PF_loop: LPM_R0_ZPLUS_NEXT src_b2 tst r0 brne .L_strlen_PF_loop ; return RAMPZ:Z - 1 - src = (-1 - src) + RAMPZ:Z = ~src + RAMPZ:Z com src_b0 com src_b1 add src_b0, ZL adc src_b1, ZH X_movw src_b2, src_b0 ; size_t is 16 bits ret .L_strlen_PF_end: .size _U(strlen_PF), .L_strlen_PF_end - _U(strlen_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strpbrk_P.S0000644000000000000000000000575311732702554015732 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strpbrk_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn char *strpbrk_P(const char *s, PGM_P accept) The strpbrk_P() function locates the first occurrence in the string \p s of any of the characters in the flash string \p accept. This function is similar to strpbrk() except that \p accept is a pointer to a string in program space. \return The strpbrk_P() function returns a pointer to the character in \p s that matches one of the characters in \p accept, or \c NULL if no such character is found. The terminating zero is not considered as a part of string: if one or both args are empty, the result will \c NULL. */ #if !defined(__AVR_TINY__) #ifndef __DOXYGEN__ #include "macros.inc" #define str_lo r24 #define acc_lo r22 #define ret_lo r24 #define ret_hi r25 /* This realization is compact, but is not very fast: an accept string is not cashed. */ ASSEMBLY_CLIB_SECTION .global _U(strpbrk_P) .type _U(strpbrk_P), @function _U(strpbrk_P): X_movw XL, str_lo clr ret_hi ; a trick to save 1 word ; get next symbol from s[] 1: ld ret_lo, X+ ; *s++ tst ret_lo breq 3f ; check an occurance X_movw ZL, acc_lo 2: X_lpm r0, Z+ cp r0, ret_lo cpse r0, __zero_reg__ brne 2b brne 1b ; branch if end of accept[] is reached ; OK, is found sbiw XL, 1 X_movw ret_lo, XL 3: ret .size _U(strpbrk_P), . - _U(strpbrk_P) #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/memcmp_P.S0000644000000000000000000000545411732702554015517 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memcmp_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn int memcmp_P(const void *s1, PGM_VOID_P s2, size_t len) \brief Compare memory areas The memcmp_P() function compares the first \p len bytes of the memory areas \p s1 and flash \p s2. The comparision is performed using unsigned char operations. \returns The memcmp_P() function returns an integer less than, equal to, or greater than zero if the first \p len bytes of \p s1 is found, respectively, to be less than, to match, or be greater than the first \p len bytes of \p s2. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define len_hi r21 #define len_lo r20 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(memcmp_P) .type _U(memcmp_P), @function _U(memcmp_P): X_movw ZL, s2_lo X_movw XL, s1_lo rjmp 2f 1: ld ret_lo, X+ X_lpm r0, Z+ sub ret_lo, r0 brne 3f 2: subi len_lo, lo8(1) sbci len_hi, hi8(1) brsh 1b sub ret_lo, ret_lo 3: sbc ret_hi, ret_hi ret .size _U(memcmp_P), . - _U(memcmp_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/Files.am0000644000000000000000000000441411732702554015212 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # pmstring_a_c_sources = \ strtok_P.c pmstring_a_asm_sources = \ memchr_P.S \ memcmp_P.S \ memccpy_P.S \ memcpy_P.S \ memrchr_P.S \ strcasecmp_P.S \ strcat_P.S \ strchr_P.S \ strchrnul_P.S \ strcmp_P.S \ strcpy_P.S \ strcspn_P.S \ strlcat_P.S \ strlcpy_P.S \ strlen_P.S \ strncasecmp_P.S \ strncat_P.S \ strncmp_P.S \ strncpy_P.S \ strnlen_P.S \ strpbrk_P.S \ strrchr_P.S \ strsep_P.S \ strspn_P.S \ strstr_P.S \ strtok_rP.S \ memcpy_PF.S \ strcasecmp_PF.S \ strcat_PF.S \ strcmp_PF.S \ strcpy_PF.S \ strlcat_PF.S \ strlcpy_PF.S \ strlen_PF.S \ strncasecmp_PF.S \ strncat_PF.S \ strncmp_PF.S \ strncpy_PF.S \ strnlen_PF.S \ strstr_PF.S \ memcmp_PF.S # vim: set ft=make: avr-libc-1.8.0.orig/libc/pmstring/strcat_P.S0000644000000000000000000000513211732702554015532 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Reiner Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* strcat_P.S Contributors: Created by Reiner Patommel */ /* $Id: strcat_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn char *strcat_P(char *dest, PGM_P src) The strcat_P() function is similar to strcat() except that the \e src string must be located in program space (flash). \returns The strcat() function returns a pointer to the resulting string \e dest. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 ASSEMBLY_CLIB_SECTION .global _U(strcat_P) .type _U(strcat_P), @function _U(strcat_P): X_movw ZL, src_lo X_movw XL, dest_lo .L_strcat_P_skip: ld __tmp_reg__, X+ tst __tmp_reg__ brne .L_strcat_P_skip sbiw XL, 1 ; undo post-increment .L_strcat_P_loop: X_lpm r0, Z+ st X+, r0 tst r0 brne .L_strcat_P_loop ; return dest (unchanged) ret .L_strcat_P_end: .size _U(strcat_P), .L_strcat_P_end - _U(strcat_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strlcat_PF.S0000644000000000000000000001155711732702554016024 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strlcat_P.S which is Copyright (c) 2003, Eric B. Weddington, R. Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlcat_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \ingroup avr_pgmspace \fn size_t strlcat_PF (char *dst, uint_farptr_t src, size_t n) \brief Concatenate two strings The strlcat_PF() function is similar to strlcat(), except that the \e src string must be located in program space (flash) and is addressed using a far pointer Appends src to string dst of size \e n (unlike strncat(), \e n is the full size of \e dst, not space left). At most \e n-1 characters will be copied. Always NULL terminates (unless \e n <= strlen(\e dst)) \param dst A pointer to the destination string in SRAM \param src A far pointer to the source string in Flash \param n The total number of bytes allocated to the destination string \returns The strlcat_PF() function returns strlen(\e src) + MIN(\e n, strlen(initial \e dst)). If retval >= \e n, truncation occurred. The contents of RAMPZ SFR are undefined when the funcion returns */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define dst_b1 r25 #define dst_b0 r24 #define src_b30 r23 /* ignored */ #define src_b20 r22 /* moved to src_b2 in the code */ #define src_b1 r21 #define src_b0 r20 #define siz_b1 r19 #define siz_b0 r18 #define src_b2 r28 /* must be preserved */ #define dlen_b1 src_b30 #define dlen_b0 src_b20 #define rWord_b1 r25 #define rWord_b0 r24 .text .global _U(strlcat_PF) .type _U(strlcat_PF),@function _U(strlcat_PF): push src_b2 mov src_b2, src_b20 X_movw XL, dst_b0 ; X = dst X_movw ZL, src_b0 ; Z = src LPM_R0_ZPLUS_INIT src_b2 .L_strlcat_PF_dlen: ; Find end of dst string ld r0, X+ ; get next char from dst cp siz_b0, __zero_reg__ ; and calc dlen = len of dst cpc siz_b1, __zero_reg__ ; size == 0 ? breq 1f ; --> done tst r0 ; end of dst ? breq 1f ; --> done subi siz_b0, lo8(1) sbci siz_b1, hi8(1) ; siz-- rjmp .L_strlcat_PF_dlen ; --> next char 1: sbiw XL, 1 ; undo post increment X_movw dlen_b0, XL sub dlen_b0, dst_b0 sbc dlen_b1, dst_b1 ; dlen = X - dst cp siz_b0, __zero_reg__ cpc siz_b1, __zero_reg__ ; size == 0 ? breq .L_strlcat_PF_slen ; --> done subi siz_b0, lo8(1) sbci siz_b1, hi8(1) ; siz-- .L_strlcat_PF_concat: ; Concatenate LPM_R0_ZPLUS_NEXT src_b2 ; get next char from src cp siz_b0, __zero_reg__ cpc siz_b1, __zero_reg__ ; size == 0 ? breq 1f ; --> done tst r0 ; end of src ? breq 1f ; --> done st X+, r0 ; store in dest subi siz_b0, lo8(1) sbci siz_b1, hi8(1) ; siz-- rjmp .L_strlcat_PF_concat ; --> next char 1: st X, __zero_reg__ ; *X = '\0' sbiw ZL, 1 ; undo post increment #ifdef RAMPZ in r0, _SFR_IO_ADDR(RAMPZ) sbc r0, __zero_reg__ out _SFR_IO_ADDR(RAMPZ), r0 #endif .L_strlcat_PF_slen: LPM_R0_ZPLUS_NEXT src_b2 ; get next char from src tst r0 ; end of src ? brne .L_strlcat_PF_slen ; --> next char sbiw ZL, 1 ; undo post increment #ifdef RAMPZ in r0, _SFR_IO_ADDR(RAMPZ) sbc r0, __zero_reg__ out _SFR_IO_ADDR(RAMPZ), r0 #endif X_movw rWord_b0, dlen_b0 add rWord_b0, ZL adc rWord_b1, ZH sub rWord_b0, src_b0 sbc rWord_b1, src_b1 ; return(dlen + (Z - src)) pop src_b2 ret .L_strlcat_PF_end: .size _U(strlcat_PF), .L_strlcat_PF_end - _U(strlcat_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/memrchr_P.S0000644000000000000000000000511611732702554015671 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memrchr_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn PGM_VOID_P memrchr_P(PGM_VOID_P src, int val, size_t len) The memrchr_P() function is like the memchr_P() function, except that it searches backwards from the end of the \p len bytes pointed to by \p src instead of forwards from the front. (Glibc, GNU extension.) \return The memrchr_P() function returns a pointer to the matching byte or \c NULL if the character does not occur in the given memory area. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" #define src_hi r25 #define src_lo r24 #define val r22 #define len_hi r21 #define len_lo r20 #define ret_lo r24 ENTRY memrchr_P X_movw ZL, len_lo adiw ZL, 0 breq 2f ; len is 0, return NULL add ZL, src_lo adc ZH, src_hi 1: sbiw ZL, 1 lpm cp r0, val breq 2f ; val is found subi len_lo, lo8(1) sbci len_hi, hi8(1) brne 1b X_movw ZL, len_lo ; is zero 2: X_movw ret_lo, ZL ret ENDFUNC #endif /* not __DOXYGEN__ */ #endif /*!defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strncat_P.S0000644000000000000000000000550211732702554015711 0ustar /* Copyright (c) 2003, 2005, 2006, 2007 Reiner Patommel based on strncat by Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncat_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn char *strncat_P(char *dest, PGM_P src, size_t len) \brief Concatenate two strings. The strncat_P() function is similar to strncat(), except that the \e src string must be located in program space (flash). \returns The strncat_P() function returns a pointer to the resulting string dest. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 #define len_hi r21 #define len_lo r20 ASSEMBLY_CLIB_SECTION .global _U(strncat_P) .type _U(strncat_P), @function _U(strncat_P): X_movw ZL, src_lo X_movw XL, dest_lo .L_strncat_P_skip: ld __tmp_reg__, X+ tst __tmp_reg__ brne .L_strncat_P_skip sbiw XL, 1 ; undo post-increment (point the the NUL) .L_strncat_P_loop: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcs .L_strncat_P_done X_lpm r0, Z+ tst r0 st X+, r0 brne .L_strncat_P_loop ; return dest (unchanged) ret .L_strncat_P_done: st X, __zero_reg__ ; return dest (unchanged) ret .L_strncat_P_end: .size _U(strncat_P), .L_strncat_P_end - _U(strncat_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strrchr_P.S0000644000000000000000000000505111732702554015721 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strrchr_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn PGM_P strrchr_P(PGM_P s, int val) \brief Locate character in string. The strrchr_P() function returns a pointer to the last occurrence of the character \p val in the flash string \p s. \return The strrchr_P() function returns a pointer to the matched character or \c NULL if the character is not found. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define src_hi r25 #define src_lo r24 #define val r22 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strrchr_P) .type _U(strrchr_P), @function _U(strrchr_P): X_movw ZL, src_lo ldi ret_lo, lo8(1) ; NULL + 1 ldi ret_hi, hi8(1) 1: X_lpm r0, Z+ cp r0, val brne 2f X_movw ret_lo, ZL ; remember this character was here 2: tst r0 brne 1b sbiw ret_lo, 1 ; undo post-increment ret .size _U(strrchr_P), . - _U(strrchr_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strtok_P.c0000644000000000000000000000522611732702554015604 0ustar /* Copyright (c) 2008, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strtok_P.c 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) /** \file */ #include #include "sectionname.h" /** \ingroup avr_pgmspace \brief Parses the string into tokens. strtok_P() parses the string \p s into tokens. The first call to strtok_P() should have \p s as its first argument. Subsequent calls should have the first argument set to NULL. If a token ends with a delimiter, this delimiting character is overwritten with a '\\0' and a pointer to the next character is saved for the next call to strtok_P(). The delimiter string \p delim may be different for each call. The strtok_P() function is similar to strtok() except that \p delim is pointer to a string in program space. \returns The strtok_P() function returns a pointer to the next token or NULL when no more tokens are found. \note strtok_P() is NOT reentrant. For a reentrant version of this function see strtok_rP(). */ ATTRIBUTE_CLIB_SECTION char * strtok_P (char *s, PGM_P delim) { static char *p; return strtok_rP (s, delim, &p); } #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/Rules.am0000644000000000000000000000333511732702554015243 0ustar # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ ## Process this file with automake to generate Makefile.in include $(top_srcdir)/libc/pmstring/Files.am # vim: set ft=make: avr-libc-1.8.0.orig/libc/pmstring/strncpy_P.S0000644000000000000000000000611211732702554015733 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncpy_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn char *strncpy_P(char *dest, PGM_P src, size_t n) The strncpy_P() function is similar to strcpy_P() except that not more than n bytes of src are copied. Thus, if there is no null byte among the first n bytes of src, the result will not be null-terminated. In the case where the length of src is less than that of n, the remainder of dest will be padded with nulls. \returns The strncpy_P() function returns a pointer to the destination string dest. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 #define len_hi r21 #define len_lo r20 ASSEMBLY_CLIB_SECTION .global _U(strncpy_P) .type _U(strncpy_P), @function _U(strncpy_P): X_movw ZL, src_lo X_movw XL, dest_lo .L_strncpy_P_loop: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcs .L_strncpy_P_done X_lpm r0, Z+ st X+, r0 tst r0 brne .L_strncpy_P_loop ; store null characters up to the end of dest ; as the glibc manual says: ; This behavior is rarely useful, but it is specified by the ISO C standard. rjmp .L_strncpy_P_clr_start .L_strncpy_P_clr_loop: st X+, __zero_reg__ .L_strncpy_P_clr_start: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcc .L_strncpy_P_clr_loop .L_strncpy_P_done: ; return dest (unchanged) ret .L_strncpy_P_end: .size _U(strncpy_P), .L_strncpy_P_end - _U(strncpy_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strsep_P.S0000644000000000000000000000727011732702554015557 0ustar /* Copyright (c) 2003, 2007 Reiner Patommel Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strsep_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn char *strsep_P(char **sp, PGM_P delim) \brief Parse a string into tokens. The strsep_P() function locates, in the string referenced by \p *sp, the first occurrence of any character in the string \p delim (or the terminating '\\0' character) and replaces it with a '\\0'. The location of the next character after the delimiter character (or \c NULL, if the end of the string was reached) is stored in \p *sp. An ``empty'' field, i.e. one caused by two adjacent delimiter characters, can be detected by comparing the location referenced by the pointer returned in \p *sp to '\\0'. This function is similar to strsep() except that \p delim is a pointer to a string in program space. \return The strsep_P() function returns a pointer to the original value of \p *sp. If \p *sp is initially \c NULL, strsep_P() returns \c NULL. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define strp_lo r24 #define dlm_lo r22 #define str_lo r20 #define chr r19 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strsep_P) .type _U(strsep_P),@function _U(strsep_P): ; check a NULL pointer X_movw ZL, strp_lo ld XL, Z ; str address ldd XH, Z+1 X_movw str_lo, XL ; save for return adiw XL, 0 breq 5f ; return NULL ; get a symbol from str 1: ld chr, X+ ; scan delim[] X_movw ZL, dlm_lo 2: X_lpm r0, Z+ cp r0, chr cpse r0, __zero_reg__ brne 2b ; if symbol is't match && no delim end brne 1b ; if symbol is absent in delim[] && not a zero ; chr is founded in delim[] (possible, it is a terminating zero of str) tst r0 ; the same, as chr brne 3f X_movw XL, r0 ; __zero_reg__ is r1 rjmp 4f ; OK, delimeter symbol is founded 3: st -X, __zero_reg__ ; replace by '\0' adiw XL, 1 ; address of next token ; save result to *sp and return 4: X_movw ZL, strp_lo st Z, XL std Z+1, XH 5: X_movw ret_lo, str_lo ; return original address ret .size _U(strsep_P), . - _U(strsep_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strncpy_PF.S0000644000000000000000000000703111732702554016042 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strncpy_P.S which is Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncpy_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define dest_b1 r25 #define dest_b0 r24 #define src_b3 r23 #define src_b2 r22 #define src_b1 r21 #define src_b0 r20 #define len_b1 r19 #define len_b0 r18 /** \ingroup avr_pgmspace \fn char *strncpy_PF (char *dst, uint_farptr_t src, size_t n) \brief Duplicate a string until a limited length The strncpy_PF() function is similar to strcpy_PF() except that not more than \e n bytes of \e src are copied. Thus, if there is no null byte among the first \e n bytes of \e src, the result will not be null-terminated In the case where the length of \e src is less than that of \e n, the remainder of \e dst will be padded with nulls \param dst A pointer to the destination string in SRAM \param src A far pointer to the source string in Flash \param n The maximum number of bytes to copy \returns The strncpy_PF() function returns a pointer to the destination string \e dst. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(strncpy_PF) .type _U(strncpy_PF), @function _U(strncpy_PF): X_movw ZL, src_b0 LPM_R0_ZPLUS_INIT src_b2 X_movw XL, dest_b0 .L_strncpy_PF_loop: subi len_b0, lo8(1) sbci len_b1, hi8(1) brcs .L_strncpy_PF_done LPM_R0_ZPLUS_NEXT src_b2 st X+, r0 tst r0 brne .L_strncpy_PF_loop ; store null characters up to the end of dest ; as the glibc manual says: ; This behavior is rarely useful, but it is specified by the ISO C standard. rjmp .L_strncpy_PF_clr_start .L_strncpy_PF_clr_loop: st X+, __zero_reg__ .L_strncpy_PF_clr_start: subi len_b0, lo8(1) sbci len_b1, hi8(1) brcc .L_strncpy_PF_clr_loop .L_strncpy_PF_done: ; return dest (unchanged) ret .L_strncpy_PF_end: .size _U(strncpy_PF), .L_strncpy_PF_end - _U(strncpy_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strspn_P.S0000644000000000000000000000575611732702554015577 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strspn_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn size_t strspn_P(const char *s, PGM_P accept) The strspn_P() function calculates the length of the initial segment of \p s which consists entirely of characters in \p accept. This function is similar to strspn() except that \p accept is a pointer to a string in program space. \return The strspn_P() function returns the number of characters in the initial segment of \p s which consist only of characters from \p accept. The terminating zero is not considered as a part of string. */ #if !defined(__AVR_TINY__) #ifndef __DOXYGEN__ #include "macros.inc" #define str_lo r24 #define str_hi r25 #define acc_lo r22 #define acc_hi r23 #define chs r21 /* char from s[] */ /* This realization is compact, but is not very fast: an accept string is not cashed. */ ASSEMBLY_CLIB_SECTION .global _U(strspn_P) .type _U(strspn_P), @function _U(strspn_P): X_movw XL, str_lo ; get next symbol from s[] 1: ld chs, X+ ; *s++ tst chs breq 3f ; check an occurance X_movw ZL, acc_lo 2: X_lpm r0, Z+ cp r0, chs cpse r0, __zero_reg__ brne 2b breq 1b ; branch if chs is present in accept[] ; end of scanning: chs is not found or end of s[] is reached ; Return: X - 1 - str == X + ~str 3: com str_lo com str_hi add str_lo, XL adc str_hi, XH ret .size _U(strspn_P), . - _U(strspn_P) #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/memchr_P.S0000644000000000000000000000574211732702554015514 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memchr_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn PGM_VOID_P memchr_P(PGM_VOID_P s, int val, size_t len) \brief Scan flash memory for a character. The memchr_P() function scans the first \p len bytes of the flash memory area pointed to by \p s for the character \p val. The first byte to match \p val (interpreted as an unsigned character) stops the operation. \return The memchr_P() function returns a pointer to the matching byte or \c NULL if the character does not occur in the given memory area. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define src_hi r25 #define src_lo r24 #define val r22 #define len_hi r21 #define len_lo r20 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(memchr_P) .type _U(memchr_P), @function _U(memchr_P): X_movw ZL, src_lo #if __AVR_HAVE_LPMX__ 1: subi len_lo, lo8(1) sbci len_hi, hi8(1) brlo 2f lpm r0, Z+ cp r0, val brne 1b ; OK, val is founded sbiw ZL, 1 X_movw ret_lo, ZL ret ; fault, val is't founded 2: clr ret_lo clr ret_hi ret #else rjmp 2f 1: lpm cp r0, val breq 3f adiw ZL, 1 2: subi len_lo, lo8(1) sbci len_hi, hi8(1) brsh 1b clr ZL clr ZH 3: X_movw ret_lo, ZL ; practicaly, this will be 2 movs ret #endif .size _U(memchr_P), . - _U(memchr_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strstr_PF.S0000644000000000000000000000730411732702554015704 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strstr_P.S which is Copyright (c) 2005, Werner Boellmann Copyright (c) 2002, Philip Soeberg All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strstr_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #include "macros.inc" /** \ingroup avr_pgmspace \fn char *strstr_PF (const char *s1, uint_farptr_t s2) \brief Locate a substring. The strstr_PF() function finds the first occurrence of the substring \c s2 in the string \c s1. The terminating '\\0' characters are not compared. The strstr_PF() function is similar to strstr() except that \c s2 is a far pointer to a string in program space. \returns The strstr_PF() function returns a pointer to the beginning of the substring, or NULL if the substring is not found. If \c s2 points to a string of zero length, the function returns \c s1. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #define s1_b1 r25 #define s1_b0 r24 #define s2_b3 r23 #define s2_b2 r22 #define s2_b1 r21 #define s2_b0 r20 ; first char of str1 (updated in loop) #define chr1 s2_b3 /* MSB not used */ #define ret_b1 r25 #define ret_b0 r24 .text .global _U(strstr_PF) .type _U(strstr_PF), @function _U(strstr_PF): X_movw ZL, s2_b0 LPM_R0_ZPLUS_INIT s2_b2 X_movw XL, s1_b0 LPM_R0_ZPLUS_NEXT s2_b2 tst r0 ; is str2 empty? brne .L_findstart_P ret ; return original string (req'd by standard) .L_findstart_P: X_movw ZL, s2_b0 ; reset Z pointer LPM_R0_ZPLUS_INIT s2_b2 LPM_R0_ZPLUS_NEXT s2_b2 ; fetch first char .L_findstart_loop_P: ; Find first char ld chr1, X+ tst chr1 ; Is str1 @ end? breq .L_no_match_P ; then return cp chr1, r0 ; Is chr1 == r0? X_movw ret_b0, XL ; store return value brne .L_findstart_loop_P ; If, then start checking string .L_stringloop_P: LPM_R0_ZPLUS_NEXT s2_b2 tst r0 breq .L_match_P ld chr1, X tst chr1 breq .L_no_match_P cp chr1, r0 brne .L_findstart_P adiw XL, 1 ; Increment X with one rjmp .L_stringloop_P .L_no_match_P: clr ret_b0 clr ret_b1 ret .L_match_P: sbiw ret_b0, 1 ret .L_strstr_end_P: .size _U(strstr_PF), .L_strstr_end_P - _U(strstr_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strcspn_P.S0000644000000000000000000000562211732702554015732 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcspn_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn size_t strcspn_P(const char *s, PGM_P reject) The strcspn_P() function calculates the length of the initial segment of \p s which consists entirely of characters not in \p reject. This function is similar to strcspn() except that \p reject is a pointer to a string in program space. \return The strcspn_P() function returns the number of characters in the initial segment of \p s which are not in the string \p reject. The terminating zero is not considered as a part of string. */ #if !defined(__AVR_TINY__) #ifndef __DOXYGEN__ #include "macros.inc" #define str_lo r24 #define str_hi r25 #define acc_lo r22 #define acc_hi r23 #define chs r21 /* char from s[] */ ASSEMBLY_CLIB_SECTION .global _U(strcspn_P) .type _U(strcspn_P), @function _U(strcspn_P): X_movw XL, str_lo ; get next symbol from s[] 1: ld chs, X+ ; *s++ tst chs breq 3f ; check an occurance X_movw ZL, acc_lo 2: X_lpm r0, Z+ cp r0, chs cpse r0, __zero_reg__ brne 2b brne 1b ; branch if chs is't present in reject[] ; end of scanning: chs is found or end of s[] is reached ; Return: X - 1 - str == X + ~str 3: com str_lo com str_hi add str_lo, XL adc str_hi, XH ret .size _U(strcspn_P), . - _U(strcspn_P) #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strtok_rP.S0000644000000000000000000001343511732702554015747 0ustar /* Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strtok_rP.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn char *strtok_rP (char *string, PGM_P delim, char **last) \brief Parses string into tokens. The strtok_rP() function parses \p string into tokens. The first call to strtok_rP() should have string as its first argument. Subsequent calls should have the first argument set to NULL. If a token ends with a delimiter, this delimiting character is overwritten with a '\\0' and a pointer to the next character is saved for the next call to strtok_rP(). The delimiter string \p delim may be different for each call. \p last is a user allocated char* pointer. It must be the same while parsing the same string. strtok_rP() is a reentrant version of strtok_P(). The strtok_rP() function is similar to strtok_r() except that \p delim is pointer to a string in program space. \returns The strtok_rP() function returns a pointer to the next token or NULL when no more tokens are found. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" /* char *strtok_r (char *s, const char *delim, char **last) { char *p = *last; const char *q; char c, d; if (!s) { if (!p) return s; // end of string s = p; // continue parsing } p = s; for (;;) { // skip delimeters s = p; // space optimization (vs. s = p-1) if (!(c = *p++)) { s = 0; p = 0; goto ret; } q = delim; do { if (!(d = *q++)) goto find_end; } while (d != c); } find_end: do { q = delim; do { d = *q++; if (c == d) { *--p = 0; p++; goto ret; } } while (d); } while ((c = *p++) != 0); p = 0; // stop parsing ret: *last = p; return s; } */ #define str_hi r25 #define str_lo r24 #define dlm_lo r22 #define lst_lo r20 ENTRY strtok_rP /* Two variants below are different in registers to load chars. In case of enhanced core it is convinient to use pair as zero word. In classic case it is optimal to load delimeter char (flash) to R0. */ /* -------------------------------------------------------------------- */ #if __AVR_HAVE_LPMX__ # define dlm_ch r18 /* delimeter character */ # define str_ch r0 /* string character */ X_movw ZL, lst_lo ld XL, Z+ ; X = *last ld XH, Z ; check str sbiw str_lo, 0 brne 1f sbiw XL, 0 breq .Lret ; end of string X_movw str_lo, XL ; continue parsing ; skip delimeters 1: X_movw XL, str_lo ; p = str 2: X_movw str_lo, XL ld str_ch, X+ tst str_ch brne 3f X_movw str_lo, str_ch ; rjmp .Lclr 3: X_movw ZL, dlm_lo 4: lpm dlm_ch, Z+ tst dlm_ch breq 5f ; goto find cp dlm_ch, str_ch brne 4b rjmp 2b ; skip 1 byte ; find new token end 5: X_movw ZL, dlm_lo 6: lpm dlm_ch, Z+ cp dlm_ch, str_ch ; str_ch != 0 brne 7f st -X, __zero_reg__ adiw XL, 1 rjmp .Lret 7: tst dlm_ch brne 6b ; next str byte ld str_ch, X+ tst str_ch brne 5b ; stop parsing .Lclr: X_movw XL, str_ch ; ; save last pointer .Lret: X_movw ZL, lst_lo ; *last = X st Z+, XL st Z, XH ret /* -------------------------------------------------------------------- */ #else /* !__AVR_HAVE_LPMX__ */ # define dlm_ch r0 /* delimeter character */ # define str_ch r18 /* string character */ X_movw ZL, lst_lo ld XL, Z+ ; X = *last ld XH, Z ; check str sbiw str_lo, 0 brne 1f sbiw XL, 0 breq .Lret ; end of string X_movw str_lo, XL ; continue parsing ; skip delimeters 1: X_movw XL, str_lo ; p = str 2: X_movw str_lo, XL ld str_ch, X+ tst str_ch brne 3f clr str_lo ; return value clr str_hi rjmp .Lclr 3: X_movw ZL, dlm_lo 4: lpm ; lpm r0,Z adiw ZL, 1 tst dlm_ch breq 5f ; goto find cp dlm_ch, str_ch brne 4b rjmp 2b ; skip 1 byte ; find new token end 5: X_movw ZL, dlm_lo 6: lpm ; lpm r0,Z adiw ZL, 1 cp dlm_ch, str_ch ; str_ch != 0 brne 7f st -X, __zero_reg__ adiw XL, 1 rjmp .Lret 7: tst dlm_ch brne 6b ; next str byte ld str_ch, X+ tst str_ch brne 5b ; stop parsing .Lclr: clr XL clr XH ; save last pointer .Lret: X_movw ZL, lst_lo ; *last = X st Z+, XL st Z, XH ret /* -------------------------------------------------------------------- */ #endif /* !__AVR_HAVE_LPMX__ */ ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strcpy_PF.S0000644000000000000000000000540711732702554015671 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strcpy_P.S which is Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcpy_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define dest_b1 r25 #define dest_b0 r24 #define src_b3 r23 #define src_b2 r22 #define src_b1 r21 #define src_b0 r20 /** \ingroup avr_pgmspace \fn char *strcpy_PF (char *dst, uint_farptr_t src) \brief Duplicate a string The strcpy_PF() function is similar to strcpy() except that \e src is a far pointer to a string in program space \param dst A pointer to the destination string in SRAM \param src A far pointer to the source string in Flash \returns The strcpy_PF() function returns a pointer to the destination string \e dst. The contents of RAMPZ SFR are undefined when the funcion returns */ #if !defined(__DOXYGEN__) .text .global _U(strcpy_PF) .type _U(strcpy_PF), @function _U(strcpy_PF): X_movw ZL, src_b0 LPM_R0_ZPLUS_INIT src_b2 X_movw XL, dest_b0 .L_strcpy_PF_loop: LPM_R0_ZPLUS_NEXT src_b2 st X+, r0 tst r0 brne .L_strcpy_PF_loop ; return dest (unchanged) ret .L_strcpy_PF_end: .size _U(strcpy_PF), .L_strcpy_PF_end - _U(strcpy_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strcasecmp_P.S0000644000000000000000000000644011732702554016401 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Reiner Patommel Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcasecmp_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* strcasecmp_P.S Case insensitive compare Contributors: Created by Reiner Patommel */ /** \file */ /** \ingroup avr_pgmspace \fn int strcasecmp_P(const char *s1, PGM_P s2) \brief Compare two strings ignoring case. The strcasecmp_P() function compares the two strings \p s1 and \p s2, ignoring the case of the characters. \param s1 A pointer to a string in the devices SRAM. \param s2 A pointer to a string in the devices Flash. \returns The strcasecmp_P() function returns an integer less than, equal to, or greater than zero if \p s1 is found, respectively, to be less than, to match, or be greater than \p s2. A consequence of the ordering used by strcasecmp_P() is that if \p s1 is an initial substring of \p s2, then \p s1 is considered to be "less than" \p s2. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define ret_hi r25 #define ret_lo r24 #define tmp r22 ASSEMBLY_CLIB_SECTION .global _U(strcasecmp_P) .type _U(strcasecmp_P), @function _U(strcasecmp_P): X_movw ZL, s2_lo X_movw XL, s1_lo 1: ld ret_lo, X+ ; *s1++ cpi ret_lo, 'A' ; if in [A-Z] then tolower() brlt 2f cpi ret_lo, 'Z'+1 brge 2f subi ret_lo, 'A'-'a' 2: X_lpm tmp, Z+ ; *s2++ cpi tmp, 'A' ; if in [A-Z] then tolower() brlt 3f cpi tmp, 'Z'+1 brge 3f subi tmp, 'A'-'a' 3: sub ret_lo, tmp ; compare cpse tmp, __zero_reg__ ; break, if end of string breq 1b sbc ret_hi, ret_hi ; sign extension ret .size _U(strcasecmp_P), . - _U(strcasecmp_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/Makefile.am0000644000000000000000000000326411732702554015667 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 2039 2009-11-08 06:03:42Z dmix $ # include $(top_srcdir)/libc/pmstring/Files.am EXTRA_DIST = $(pmstring_a_asm_sources) \ $(pmstring_a_c_sources) avr-libc-1.8.0.orig/libc/pmstring/strnlen_P.S0000644000000000000000000000546011732702554015723 0ustar /* Copyright (c) 2005, 2006, 2007 Helmut Wallner based on libc/string/strnlen.S which is Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strnlen_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn size_t strnlen_P(PGM_P src, size_t len) \brief Determine the length of a fixed-size string. The strnlen_P() function is similar to strnlen(), except that \c src is a pointer to a string in program space. \returns The strnlen_P function returns strlen_P(src), if that is less than \c len, or \c len if there is no '\\0' character among the first \c len characters pointed to by \c src. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define src_hi r25 #define src_lo r24 #define len_hi r23 #define len_lo r22 ASSEMBLY_CLIB_SECTION .global _U(strnlen_P) .type _U(strnlen_P), @function _U(strnlen_P): X_movw ZL, src_lo .L_strnlen_P_loop: X_lpm r0, Z+ subi len_lo, lo8(1) sbci len_hi, hi8(1) cpse r0, __zero_reg__ brcc .L_strnlen_P_loop ; Z points one character past the terminating NUL ; return Z - 1 - src = (-1 - src) + Z = ~src + Z com src_lo com src_hi add src_lo, ZL adc src_hi, ZH ret .L_strnlen_P_end: .size _U(strnlen_P), .L_strnlen_P_end - _U(strnlen_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strchrnul_P.S0000644000000000000000000000464511732702554016266 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strchrnul_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn PGM_P strchrnul_P(PGM_P s, int c) The strchrnul_P() function is like strchr_P() except that if \p c is not found in \p s, then it returns a pointer to the null byte at the end of \p s, rather than \c NULL. (Glibc, GNU extension.) \return The strchrnul_P() function returns a pointer to the matched character, or a pointer to the null byte at the end of \p s (i.e., \c s+strlen(s)) if the character is not found. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" #define src_lo r24 #define val r22 #define ret_lo r24 ENTRY strchrnul_P X_movw ZL, src_lo 1: X_lpm r0, Z+ cp r0, val cpse r0, __zero_reg__ brne 1b sbiw ZL, 1 ; undo post-increment X_movw ret_lo, ZL ret ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strcmp_PF.S0000644000000000000000000000572611732702554015661 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strcmp_P.S which is Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcmp_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define s1_b1 r25 #define s1_b0 r24 #define s2_b3 r23 #define s2_b2 r22 #define s2_b1 r21 #define s2_b0 r20 #define ret_b1 r25 #define ret_b0 r24 /** \ingroup avr_pgmspace \fn int strcmp_PF (const char *s1, uint_farptr_t s2) \brief Compares two strings The strcmp_PF() function is similar to strcmp() except that \e s2 is a far pointer to a string in program space \param s1 A pointer to the first string in SRAM \param s2 A far pointer to the second string in Flash \returns The strcmp_PF() function returns an integer less than, equal to, or greater than zero if \e s1 is found, respectively, to be less than, to match, or be greater than \e s2. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(strcmp_PF) .type _U(strcmp_PF), @function _U(strcmp_PF): X_movw ZL, s2_b0 LPM_R0_ZPLUS_INIT s2_b2 X_movw XL, s1_b0 .L_strcmp_PF_loop: ld ret_b0, X+ LPM_R0_ZPLUS_NEXT s2_b2 sub ret_b0, r0 brne .L_strcmp_PF_done tst r0 brne .L_strcmp_PF_loop .L_strcmp_PF_done: ; ret_hi = SREG.C ? 0xFF : 0 sbc ret_b1, ret_b1 ret .L_strcmp_PF_end: .size _U(strcmp_PF), .L_strcmp_PF_end - _U(strcmp_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strstr_P.S0000644000000000000000000000710411732702554015574 0ustar /* Copyright (c) 2002, Philip Soeberg Copyright (c) 2005, 2006, 2007 Werner Boellmann Copyright (c) 2007 Dmirty Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strstr_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* strstr_P.S Search string contained in a string Originally contributed by: Philip Soeberg Modified for string s2 in program space by: Werner Boellmann */ /** \file */ /** \ingroup avr_pgmspace \fn char *strstr_P(const char *s1, PGM_P s2) \brief Locate a substring. The strstr_P() function finds the first occurrence of the substring \p s2 in the string \p s1. The terminating '\\0' characters are not compared. The strstr_P() function is similar to strstr() except that \p s2 is pointer to a string in program space. \returns The strstr_P() function returns a pointer to the beginning of the substring, or NULL if the substring is not found. If \p s2 points to a string of zero length, the function returns \p s1. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define chr1 r20 #define beg2 r21 /* begin of s2: s2[0] */ #define chr2 r0 ASSEMBLY_CLIB_SECTION .global _U(strstr_P) .type _U(strstr_P), @function _U(strstr_P): X_movw ZL, s2_lo X_lpm beg2, Z+ tst beg2 ; is str2 empty? breq .L_ret ; return original string (req'd by standard) X_movw s2_lo, ZL ; save: address of second s2 byte 0: X_movw XL, s1_lo 1: ld chr1, X+ ; Find first char cp chr1, beg2 cpse chr1, __zero_reg__ brne 1b brne .L_no_match ; end of s1 X_movw s1_lo, XL ; store return value 2: X_lpm chr2, Z+ ; compare strings tst chr2 breq .L_match ; end of s2 ld chr1, X+ cp chr1, chr2 cpse chr1, __zero_reg__ ; break, if end of s1 breq 2b X_movw ZL, s2_lo ; restore s2+1 cpse chr1, __zero_reg__ rjmp 0b .L_no_match: ldi s1_lo, lo8(1) ldi s1_hi, hi8(1) .L_match: sbiw s1_lo, 1 ; restore after post-increment .L_ret: ret .size _U(strstr_P), . - _U(strstr_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strcmp_P.S0000644000000000000000000000536611732702554015553 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcmp_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn int strcmp_P(const char *s1, PGM_P s2) The strcmp_P() function is similar to strcmp() except that \p s2 is pointer to a string in program space. \returns The strcmp_P() function returns an integer less than, equal to, or greater than zero if \p s1 is found, respectively, to be less than, to match, or be greater than \p s2. A consequence of the ordering used by strcmp_P() is that if \p s1 is an initial substring of \p s2, then \p s1 is considered to be "less than" \p s2. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strcmp_P) .type _U(strcmp_P), @function _U(strcmp_P): X_movw ZL, s2_lo X_movw XL, s1_lo .L_strcmp_P_loop: ld ret_lo, X+ X_lpm r0, Z+ sub ret_lo, r0 cpse r0, __zero_reg__ breq .L_strcmp_P_loop ; ret_hi = SREG.C ? 0xFF : 0 sbc ret_hi, ret_hi ret .L_strcmp_P_end: .size _U(strcmp_P), .L_strcmp_P_end - _U(strcmp_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strncmp_P.S0000644000000000000000000000550311732702554015722 0ustar /* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncmp_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn int strncmp_P(const char *s1, PGM_P s2, size_t n) The strncmp_P() function is similar to strcmp_P() except it only compares the first (at most) n characters of s1 and s2. \returns The strncmp_P() function returns an integer less than, equal to, or greater than zero if s1 (or the first n bytes thereof) is found, respectively, to be less than, to match, or be greater than s2. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define len_hi r21 #define len_lo r20 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strncmp_P) .type _U(strncmp_P), @function _U(strncmp_P): X_movw ZL, s2_lo X_movw XL, s1_lo .L_strncmp_P_loop: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcs .L_strncmp_P_equal ld ret_lo, X+ X_lpm r0, Z+ sub ret_lo, r0 brne .L_strncmp_P_done tst r0 brne .L_strncmp_P_loop .L_strncmp_P_equal: sub ret_lo, ret_lo .L_strncmp_P_done: ; ret_hi = SREG.C ? 0xFF : 0 sbc ret_hi, ret_hi ret .L_strncmp_P_end: .size _U(strncmp_P), .L_strncmp_P_end - _U(strncmp_P) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strcat_PF.S0000644000000000000000000000566511732702554015653 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strcat_P.S which is Copyright (c) 2002, Reiner Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcat_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define dest_b1 r25 #define dest_b0 r24 #define src_b3 r23 #define src_b2 r22 #define src_b1 r21 #define src_b0 r20 /** \ingroup avr_pgmspace \fn char *strcat_PF (char *dst, uint_farptr_t src) \brief Concatenates two strings The strcat_PF() function is similar to strcat() except that the \e src string must be located in program space (flash) and is addressed using a far pointer \param dst A pointer to the destination string in SRAM \param src A far pointer to the string to be appended in Flash \returns The strcat_PF() function returns a pointer to the resulting string \e dst. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(strcat_PF) .type _U(strcat_PF), @function _U(strcat_PF): X_movw ZL, src_b0 LPM_R0_ZPLUS_INIT src_b2 X_movw XL, dest_b0 .L_strcat_PF_skip: ld __tmp_reg__, X+ tst __tmp_reg__ brne .L_strcat_PF_skip sbiw XL, 1 ; undo post-increment .L_strcat_PF_loop: LPM_R0_ZPLUS_NEXT src_b2 st X+, r0 tst r0 brne .L_strcat_PF_loop ; return dest (unchanged) ret .L_strcat_PF_end: .size _U(strcat_PF), .L_strcat_PF_end - _U(strcat_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strncat_PF.S0000644000000000000000000000633711732702554016026 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strncat_P.S which is Copyright (c) 2003, Reiner Patommel based on strncat by Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncat_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include "macros.inc" #define dest_b1 r25 #define dest_b0 r24 #define src_b3 r23 #define src_b2 r22 #define src_b1 r21 #define src_b0 r20 #define len_b1 r19 #define len_b0 r18 /** \ingroup avr_pgmspace \fn char *strncat_PF (char *dst, uint_farptr_t src, size_t n) \brief Concatenate two strings The strncat_PF() function is similar to strncat(), except that the \e src string must be located in program space (flash) and is addressed using a far pointer \param dst A pointer to the destination string in SRAM \param src A far pointer to the source string in Flash \param n The maximum number of bytes to append \returns The strncat_PF() function returns a pointer to the resulting string \e dst. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__DOXYGEN__) .text .global _U(strncat_PF) .type _U(strncat_PF), @function _U(strncat_PF): X_movw ZL, src_b0 LPM_R0_ZPLUS_INIT src_b2 X_movw XL, dest_b0 .L_strncat_PF_skip: ld r0, X+ tst r0 brne .L_strncat_PF_skip sbiw XL, 1 ; undo post-increment (point the the NUL) .L_strncat_PF_loop: subi len_b0, lo8(1) sbci len_b1, hi8(1) brcs .L_strncat_PF_done LPM_R0_ZPLUS_NEXT src_b2 tst r0 st X+, r0 brne .L_strncat_PF_loop ; return dest (unchanged) ret .L_strncat_PF_done: st X, __zero_reg__ ; return dest (unchanged) ret .L_strncat_PF_end: .size _U(strncat_PF), .L_strncat_PF_end - _U(strncat_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strlcpy_PF.S0000644000000000000000000000673011732702554016045 0ustar /* Copyright (c) 2006, Carlos Lamas based on libc/pmstring/strlcpy_P.S which is Copyright (c) 2003, Eric B. Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlcpy_PF.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \ingroup avr_pgmspace \fn size_t strlcpy_PF (char *dst, uint_farptr_t src, size_t siz) \brief Copy a string from progmem to RAM. Copy src to string dst of size siz. At most siz-1 characters will be copied. Always NULL terminates (unless siz == 0). \returns The strlcpy_PF() function returns strlen(src). If retval >= siz, truncation occurred. The contents of RAMPZ SFR are undefined when the function returns */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define dst_b1 r25 #define dst_b0 r24 #define src_b3 r23 #define src_b2 r22 #define src_b1 r21 #define src_b0 r20 #define siz_b1 r19 #define siz_b0 r18 #define rWord_b1 r25 #define rWord_b0 r24 .text .global _U(strlcpy_PF) .type _U(strlcpy_PF), @function _U(strlcpy_PF): X_movw ZL, src_b0 ; Z = src LPM_R0_ZPLUS_INIT src_b2 X_movw XL, dst_b0 ; X = dst cp siz_b0, __zero_reg__ cpc siz_b0, __zero_reg__ ; size == 0 ? breq .L_strlcpy_PF_truncated .L_strlcpy_PF_copy_loop: ; copy src to dst subi siz_b0, lo8(1) sbci siz_b1, hi8(1) ; decrement siz breq 1f ; --> siz chars copied LPM_R0_ZPLUS_NEXT src_b2 ; get next src char st X+, r0 ; copy char tst r0 ; end of src string ? breq .L_strlcpy_PF_len ; --> all src chars copied rjmp .L_strlcpy_PF_copy_loop ; next char 1: st X, __zero_reg__ ; truncate dst string .L_strlcpy_PF_truncated: ; find Z = end of src string LPM_R0_ZPLUS_NEXT src_b2 ; get next char from src tst r0 ; end of src string ? brne .L_strlcpy_PF_truncated ; next char .L_strlcpy_PF_len: ; calculate strlen(src) sub ZL, src_b0 sbc ZH, src_b1 ; Z points past \0 sbiw ZL, 1 X_movw rWord_b0, ZL ret .L_strlcpy_PF_end: .size _U(strlcpy_PF), .L_strlcpy_PF_end - _U(strlcpy_PF) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/pmstring/strlcpy_P.S0000644000000000000000000000570411732702554015737 0ustar /* AVR LIBC strlcpy_P() Copyright (c) 2003, 2005, 2006, 2007 Eric B. Weddington Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlcpy_P.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_pgmspace \fn size_t strlcpy_P (char *dst, PGM_P src, size_t siz) \brief Copy a string from progmem to RAM. Copy \p src to string \p dst of size \p siz. At most \p siz-1 characters will be copied. Always NULL terminates (unless \p siz == 0). The strlcpy_P() function is similar to strlcpy() except that the \p src is pointer to a string in memory space. \returns The strlcpy_P() function returns strlen(src). If retval >= siz, truncation occurred. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" #define dst_lo r24 #define src_hi r23 #define src_lo r22 #define siz_hi r21 #define siz_lo r20 #define rslt_lo r24 ENTRY strlcpy_P X_movw XL, dst_lo ; X = dst X_movw ZL, src_lo ; Z = src ; copy loop 1: subi siz_lo, lo8(1) sbci siz_hi, hi8(1) brcs 4f ; is possible with siz == 0 breq 3f ; --> siz chars copied X_lpm __tmp_reg__, Z+ st X+, __tmp_reg__ tst __tmp_reg__ brne 1b ; calculate result (Z - 1 - src) and return 2: sub ZL, src_lo sbc ZH, src_hi sbiw ZL, 1 X_movw rslt_lo, ZL ret ; terminate dst 3: st X, __zero_reg__ ; find src end 4: X_lpm __tmp_reg__, Z+ tst __tmp_reg__ brne 4b rjmp 2b ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/Makefile.in0000644000000000000000000004400611732702554014034 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2004, Theodore A. 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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vprintf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int vprintf(const char *fmt, va_list ap) { return vfprintf(stdout, fmt, ap); } avr-libc-1.8.0.orig/libc/stdio/vsnprintf.c0000644000000000000000000000464111732702554015307 0ustar /* Copyright (c) 2003, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vsnprintf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int vsnprintf(char *s, size_t n, const char *fmt, va_list ap) { FILE f; int i; f.flags = __SWR | __SSTR; f.buf = s; /* Restrict max output length to 32767, as snprintf() return signed int. The fputc() function uses a signed comparison between estimated len and f.size field. So we can write a negative value into f.size in the case of n was 0. Note, that f.size will be a max number of nonzero symbols. */ if ((int)n < 0) n = (unsigned)INT_MAX + 1; /* 32768 */ f.size = n - 1; /* -1,0,...32767 */ i = vfprintf(&f, fmt, ap); /* We use f.size (not 'n') as this is more effective: two 'ld' instructions vs. two 'push+pop' and 'movw'. */ if (f.size >= 0) s[f.len < f.size ? f.len : f.size] = 0; return i; } avr-libc-1.8.0.orig/libc/stdio/fprintf.c0000644000000000000000000000347011732702554014725 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fprintf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int fprintf(FILE *stream, const char *fmt, ...) { va_list ap; int i; va_start(ap, fmt); i = vfprintf(stream, fmt, ap); va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/fputs.c0000644000000000000000000000356711732702554014425 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fputs.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int fputs(const char *str, FILE *stream) { char c; int rv = 0; if ((stream->flags & __SWR) == 0) return EOF; while ((c = *str++) != '\0') if (stream->put(c, stream) != 0) rv = EOF; return rv; } avr-libc-1.8.0.orig/libc/stdio/vsprintf_p.c0000644000000000000000000000363011732702554015445 0ustar /* Copyright (c) 2003, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vsprintf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int vsprintf_P(char *s, const char *fmt, va_list ap) { FILE f; int i; f.flags = __SWR | __SSTR | __SPGM; f.buf = s; f.size = INT_MAX; i = vfprintf(&f, fmt, ap); s[f.len] = 0; return i; } avr-libc-1.8.0.orig/libc/stdio/fdevopen.c0000644000000000000000000001026311732702554015061 0ustar /* Copyright (c) 2002,2005, 2007 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fdevopen.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" #include "stdio_private.h" /** \file */ /** \ingroup avr_stdio This function is a replacement for \c fopen(). It opens a stream for a device where the actual device implementation needs to be provided by the application. If successful, a pointer to the structure for the opened stream is returned. Reasons for a possible failure currently include that neither the \c put nor the \c get argument have been provided, thus attempting to open a stream with no IO intent at all, or that insufficient dynamic memory is available to establish a new stream. If the \c put function pointer is provided, the stream is opened with write intent. The function passed as \c put shall take two arguments, the first a character to write to the device, and the second a pointer to FILE, and shall return 0 if the output was successful, and a nonzero value if the character could not be sent to the device. If the \c get function pointer is provided, the stream is opened with read intent. The function passed as \c get shall take a pointer to FILE as its single argument, and return one character from the device, passed as an \c int type. If an error occurs when trying to read from the device, it shall return \c _FDEV_ERR. If an end-of-file condition was reached while reading from the device, \c _FDEV_EOF shall be returned. If both functions are provided, the stream is opened with read and write intent. The first stream opened with read intent is assigned to \c stdin, and the first one opened with write intent is assigned to both, \c stdout and \c stderr. fdevopen() uses calloc() (und thus malloc()) in order to allocate the storage for the new stream. \note If the macro __STDIO_FDEVOPEN_COMPAT_12 is declared before including , a function prototype for fdevopen() will be chosen that is backwards compatible with avr-libc version 1.2 and before. This is solely intented for providing a simple migration path without the need to immediately change all source code. Do not use for new code. */ ATTRIBUTE_CLIB_SECTION FILE * fdevopen(int (*put)(char, FILE *), int (*get)(FILE *)) { FILE *s; if (put == 0 && get == 0) return 0; if ((s = calloc(1, sizeof(FILE))) == 0) return 0; s->flags = __SMALLOC; if (get != 0) { s->get = get; s->flags |= __SRD; if (stdin == 0) stdin = s; } if (put != 0) { s->put = put; s->flags |= __SWR; if (stdout == 0) { stdout = s; if (stderr == 0) stderr = s; } } return s; } avr-libc-1.8.0.orig/libc/stdio/fgets.c0000644000000000000000000000372511732702554014370 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fgets.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION char * fgets(char *str, int size, FILE *stream) { char *cp; int c; if ((stream->flags & __SRD) == 0 || size <= 0) return NULL; size--; for (c = 0, cp = str; c != '\n' && size > 0; size--, cp++) { if ((c = getc(stream)) == EOF) return NULL; *cp = (char)c; } *cp = '\0'; return str; } avr-libc-1.8.0.orig/libc/stdio/vscanf.c0000644000000000000000000000335611732702554014540 0ustar /* Copyright (c) 2005, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vscanf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int vscanf(const char *fmt, va_list ap) { return vfscanf(stdin, fmt, ap); } avr-libc-1.8.0.orig/libc/stdio/sscanf_p.c0000644000000000000000000000442211732702554015047 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: sscanf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int sscanf_P(const char *s, const char *fmt, ...) { va_list ap; FILE f; int i; f.flags = __SRD | __SSTR | __SPGM; /* * It is OK to discard the "const" qualifier here. f.buf is * non-const as in the generic case, this buffer is obtained * by malloc(). In the scanf case however, the buffer is * really only be read (by getc()), and as this our FILE f we * be discarded upon exiting sscanf_P(), nobody will ever get * a chance to get write access to it again. */ f.buf = (char *)s; va_start(ap, fmt); i = vfscanf(&f, fmt, ap); va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/Makefile.in0000644000000000000000000003246711732702554015166 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) 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limit (for SysV at least) may be exceeded. .NOEXPORT: avr-libc-1.8.0.orig/libc/stdio/fputc.c0000644000000000000000000000373211732702554014377 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fputc.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int fputc(int c, FILE *stream) { if ((stream->flags & __SWR) == 0) return EOF; if (stream->flags & __SSTR) { if (stream->len < stream->size) *stream->buf++ = c; stream->len++; return c; } else { if (stream->put(c, stream) == 0) { stream->len++; return c; } else return EOF; } } avr-libc-1.8.0.orig/libc/stdio/iob.c0000644000000000000000000000327311732702554014027 0ustar /* Copyright (c) 2005, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iob.c 847 2005-09-06 18:49:15Z joerg_wunsch $ */ #include #include #include "stdio_private.h" FILE *__iob[3]; /* stdin, stdout, stderr */ avr-libc-1.8.0.orig/libc/stdio/scanf.c0000644000000000000000000000344411732702554014350 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: scanf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int scanf(const char *fmt, ...) { va_list ap; int i; va_start(ap, fmt); i = vfscanf(stdin, fmt, ap); va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/fclose.c0000644000000000000000000000420411732702554014524 0ustar /* Copyright (c) 2002,2005 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fclose.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int fclose(FILE *stream) { uint8_t i; if (!(stream->flags & __SMALLOC)) /* * If the stream had not been malloc()ed, this is * not our business. */ return 0; /* * The standard streams are only aliases. So if the stream to * be closed is also refered to by a standard stream name, * mark its slot as empty. */ for (i = 0; i < 3; i++) if (__iob[i] == stream) __iob[i] = 0; free(stream); return 0; } avr-libc-1.8.0.orig/libc/stdio/putc.S0000644000000000000000000000342211732702554014205 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: putc.S 1944 2009-04-01 23:12:20Z arcanum $ */ #include "macros.inc" /* int putc(int c, FILE *stream); */ ASSEMBLY_CLIB_SECTION .global _U(putc) .type _U(putc), @function _U(putc): XJMP fputc .L_putc_end: .size _U(putc), .L_putc_end - _U(putc) avr-libc-1.8.0.orig/libc/stdio/fputs_p.c0000644000000000000000000000416711732702554014741 0ustar /* Copyright (c) 2002,2004 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fputs_p.c 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int fputs_P(const char *str, FILE *stream) { char c; int rv = 0; if ((stream->flags & __SWR) == 0) return EOF; /* * Do not use str++ in the next line. pgm_read_byte() is a * macro, so it could evaluate its argument more than once. */ while ((c = pgm_read_byte(str)) != '\0') { if (stream->put(c, stream) != 0) rv = EOF; str++; } return rv; } #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/stdio/stdio_private.h0000644000000000000000000000346711732702554016144 0ustar /* Copyright (c) 2002,2005, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: stdio_private.h 847 2005-09-06 18:49:15Z joerg_wunsch $ */ #include #include /* values for PRINTF_LEVEL */ #define PRINTF_MIN 1 #define PRINTF_STD 2 #define PRINTF_FLT 3 /* values for SCANF_LEVEL */ #define SCANF_MIN 1 #define SCANF_STD 2 #define SCANF_FLT 3 avr-libc-1.8.0.orig/libc/stdio/vsprintf.c0000644000000000000000000000361311732702554015127 0ustar /* Copyright (c) 2003, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vsprintf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int vsprintf(char *s, const char *fmt, va_list ap) { FILE f; int i; f.flags = __SWR | __SSTR; f.buf = s; f.size = INT_MAX; i = vfprintf(&f, fmt, ap); s[f.len] = 0; return i; } avr-libc-1.8.0.orig/libc/stdio/scanf_p.c0000644000000000000000000000356611732702554014674 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: scanf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int scanf_P(const char *fmt, ...) { va_list ap; int i; va_start(ap, fmt); stdin->flags |= __SPGM; i = vfscanf(stdin, fmt, ap); stdin->flags &= ~__SPGM; va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/printf_p.c0000644000000000000000000000357411732702554015103 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: printf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int printf_P(const char *fmt, ...) { va_list ap; int i; va_start(ap, fmt); stdout->flags |= __SPGM; i = vfprintf(stdout, fmt, ap); stdout->flags &= ~__SPGM; va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/ungetc.c0000644000000000000000000000413611732702554014542 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ungetc.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int ungetc(int c, FILE *stream) { /* * Streams that are not readable, or streams that already had * had an ungetc() before will cause an error. * * ungetc(EOF, ...) causes an error per definitionem. */ if ((stream->flags & __SRD) == 0 || (stream->flags & __SUNGET) != 0 || c == EOF) return EOF; stream->unget = c; stream->flags |= __SUNGET; stream->flags &= ~__SEOF; stream->len--; return stream->unget; } avr-libc-1.8.0.orig/libc/stdio/Files.am0000644000000000000000000000442011732702554014466 0ustar # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # stdio_a_c_sources = \ clearerr.c \ fclose.c \ fdevopen.c \ feof.c \ ferror.c \ fgetc.c \ fgets.c \ fprintf.c \ fprintf_p.c \ fputc.c \ fputs.c \ fputs_p.c \ fread.c \ fscanf.c \ fscanf_p.c \ fwrite.c \ getchar.c \ gets.c \ iob.c \ printf.c \ printf_p.c \ putchar.c \ puts.c \ puts_p.c \ scanf.c \ scanf_p.c \ snprintf.c \ snprintf_p.c \ sprintf.c \ sprintf_p.c \ sscanf.c \ sscanf_p.c \ vfprintf_p.c \ vfscanf_p.c \ vprintf.c \ vscanf.c \ vsnprintf.c \ vsnprintf_p.c \ vsprintf.c \ vsprintf_p.c \ ungetc.c stdio_a_asm_sources = \ getc.S \ putc.S \ ultoa_invert.S stdio_a_extra_dist = \ vfprintf.c \ vfscanf.c \ stdio_private.h \ xtoa_fast.h # vim: set ft=make: avr-libc-1.8.0.orig/libc/stdio/clearerr.c0000644000000000000000000000340611732702554015053 0ustar /* Copyright (c) 2002,2005 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: clearerr.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" #undef clearerr ATTRIBUTE_CLIB_SECTION void clearerr(FILE *stream) { stream->flags &= ~(__SERR | __SEOF); } avr-libc-1.8.0.orig/libc/stdio/fwrite.c0000644000000000000000000000373511732702554014561 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fwrite.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION size_t fwrite(const void *ptr, size_t size, size_t nmemb, FILE *stream) { size_t i, j; const uint8_t *cp; if ((stream->flags & __SWR) == 0) return 0; for (i = 0, cp = (const uint8_t *)ptr; i < nmemb; i++) for (j = 0; j < size; j++) if (stream->put(*cp++, stream) != 0) return i; return i; } avr-libc-1.8.0.orig/libc/stdio/vfscanf.c0000644000000000000000000005636311732702554014714 0ustar /* Copyright (c) 2002,2004,2005 Joerg Wunsch Copyright (c) 2008 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vfscanf.c 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include #include #include #include #include #include #include #include #include #include "sectionname.h" #include "stdio_private.h" #if !defined (SCANF_LEVEL) # ifndef SCANF_WWIDTH /* use word for width variable */ # define SCANF_WWIDTH 0 # endif # ifndef SCANF_BRACKET /* use '%[' conversion */ # define SCANF_BRACKET 0 # endif # ifndef SCANF_FLOAT /* use float point conversion */ # define SCANF_FLOAT 0 # endif #elif SCANF_LEVEL == SCANF_MIN # define SCANF_WWIDTH 0 # define SCANF_BRACKET 0 # define SCANF_FLOAT 0 #elif SCANF_LEVEL == SCANF_STD # define SCANF_WWIDTH 0 # define SCANF_BRACKET 1 # define SCANF_FLOAT 0 #elif SCANF_LEVEL == SCANF_FLT # define SCANF_WWIDTH 1 # define SCANF_BRACKET 1 # define SCANF_FLOAT 1 #else # error "Not a known scanf level." #endif #if SCANF_WWIDTH typedef unsigned int width_t; #else typedef unsigned char width_t; #endif #ifndef DISABLE_ASM # if defined(__AVR__) && __AVR__ # define DISABLE_ASM 0 # else # define DISABLE_ASM 1 # endif #endif #if SHRT_MAX != INT_MAX # error "SHRT_MAX != INT_MAX for target: not supported" #endif /* ATTENTION: check FL_CHAR first, not FL_LONG. The last is set simultaneously. */ #define FL_STAR 0x01 /* '*': skip assignment */ #define FL_WIDTH 0x02 /* width is present */ #define FL_LONG 0x04 /* 'long' type modifier */ #define FL_CHAR 0x08 /* 'char' type modifier */ #define FL_OCT 0x10 /* octal number */ #define FL_DEC 0x20 /* decimal number */ #define FL_HEX 0x40 /* hexidecimal number */ #define FL_MINUS 0x80 /* minus flag (field or value) */ #ifndef __AVR_HAVE_LPMX__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_LPMX__ 1 # endif #endif #ifndef __AVR_HAVE_MOVW__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_MOVW__ 1 # endif #endif #if DISABLE_ASM # define GETBYTE(flag, mask, pnt) ({ \ unsigned char __c; \ __c = ((flag) & (mask)) \ ? pgm_read_byte(pnt) : *pnt; \ pnt++; \ __c; \ }) #elif defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ # define GETBYTE(flag, mask, pnt) ({ \ unsigned char __c; \ asm ( \ "sbrc %2,%3 \n\t" \ "lpm %0,Z+ \n\t" \ "sbrs %2,%3 \n\t" \ "ld %0,Z+ " \ : "=r" (__c), \ "+z" (pnt) \ : "r" (flag), \ "I" (_FFS(mask) - 1) \ ); \ __c; \ }) #else # define GETBYTE(flag, mask, pnt) ({ \ unsigned char __c; \ asm ( \ "sbrc %2,%3 \n\t" \ "lpm \n\t" \ "sbrs %2,%3 \n\t" \ "ld r0,Z \n\t" \ "adiw r30,1 \n\t" \ "mov %0,r0 " \ : "=r" (__c), \ "+z" (pnt) \ : "r" (flag), \ "I" (_FFS(mask) - 1) \ : "r0" \ ); \ __c; \ }) #endif /* Add noinline attribute to avoid GCC 4.2 optimization. */ __attribute__((noinline)) ATTRIBUTE_CLIB_SECTION static void putval (void *addr, long val, unsigned char flags) { if (!(flags & FL_STAR)) { #if DISABLE_ASM if (flags & FL_CHAR) *(char *)addr = val; else if (flags & FL_LONG) *(long *)addr = val; else *(int *)addr = val; #else asm volatile ( "sbrc %[flags], %[bit_char] \n\t" "rjmp 1f \n\t" "sbrs %[flags], %[bit_long] \n\t" "rjmp 2f \n\t" "std Z+3, %D1 \n\t" "std Z+2, %C1 \n" "2: std Z+1, %B1 \n" "1: std Z+0, %A1" :: "z"(addr), "r"(val), [flags]"r"(flags), [bit_char] "M"(_FFS(FL_CHAR) - 1), [bit_long] "M"(_FFS(FL_LONG) - 1) ); #endif } } __attribute__((noinline)) ATTRIBUTE_CLIB_SECTION static unsigned long mulacc (unsigned long val, unsigned char flags, unsigned char c) { unsigned char cnt; if (flags & FL_OCT) { cnt = 3; } else if (flags & FL_HEX) { cnt = 4; } else { #if DISABLE_ASM val += (val << 2); #else asm ( # if defined(__AVR_HAVE_MOVW__) && __AVR_HAVE_MOVW__ "movw r26, %A0 \n\t" "movw r30, %C0 \n" # else "mov r26, %A0 \n\t" "mov r27, %B0 \n\t" "mov r30, %C0 \n\t" "mov r31, %D0 \n" # endif "1: lsl r26 \n\t" "rol r27 \n\t" "rol r30 \n\t" "rol r31 \n\t" "com __zero_reg__ \n\t" "brne 1b \n\t" "add %A0, r26 \n\t" "adc %B0, r27 \n\t" "adc %C0, r30 \n\t" "adc %D0, r31" : "=r"(val) : "0"(val) : "r26","r27","r30","r31" ); #endif cnt = 1; } do { val <<= 1; } while (--cnt); return val + c; } __attribute__((noinline)) ATTRIBUTE_CLIB_SECTION static unsigned char conv_int (FILE *stream, width_t width, void *addr, unsigned char flags) { unsigned long val; int i; i = getc (stream); /* after ungetc() */ switch ((unsigned char)i) { case '-': flags |= FL_MINUS; /* FALLTHROUGH */ case '+': if (!--width || (i = getc(stream)) < 0) goto err; } val = 0; flags &= ~FL_WIDTH; if (!(flags & (FL_DEC | FL_OCT)) && (unsigned char)i == '0') { if (!--width || (i = getc (stream)) < 0) goto putval; flags |= FL_WIDTH; if ((unsigned char)(i) == 'x' || (unsigned char)(i) == 'X') { flags |= FL_HEX; if (!--width || (i = getc(stream)) < 0) goto putval; } else { if (!(flags & FL_HEX)) flags |= FL_OCT; } } /* This fact is used below to parse hexidecimal digit. */ #if ('A' - '0') != (('a' - '0') & ~('A' ^ 'a')) # error #endif do { unsigned char c = i; c -= '0'; if (c > 7) { if (flags & FL_OCT) goto unget; if (c > 9) { if (!(flags & FL_HEX)) goto unget; c &= ~('A' ^ 'a'); c += '0' - 'A'; if (c > 5) { unget: ungetc (i, stream); break; } c += 10; } } val = mulacc (val, flags, c); flags |= FL_WIDTH; if (!--width) goto putval; } while ((i = getc(stream)) >= 0); if (!(flags & FL_WIDTH)) goto err; putval: if (flags & FL_MINUS) val = -val; putval (addr, val, flags); return 1; err: return 0; } #if SCANF_BRACKET __attribute__((noinline)) ATTRIBUTE_CLIB_SECTION static const char * conv_brk (FILE *stream, width_t width, char *addr, const char *fmt) { unsigned char msk[32]; unsigned char fnegate; unsigned char frange; unsigned char cabove; int i; memset (msk, 0, sizeof(msk)); fnegate = 0; frange = 0; cabove = 0; /* init to avoid compiler warning */ for (i = 0; ; i++) { unsigned char c = GETBYTE(stream->flags, __SPGM, fmt); if (c == 0) { return 0; } else if (c == '^' && !i) { fnegate = 1; continue; } else if (i > fnegate) { if (c == ']') break; if (c == '-' && !frange) { frange = 1; continue; } } if (!frange) cabove = c; for (;;) { msk[c >> 3] |= 1 << (c & 7); if (c == cabove) break; if (c < cabove) c++; else c--; } frange = 0; } if (frange) msk['-'/8] |= 1 << ('-' & 7); if (fnegate) { unsigned char *p = msk; do { unsigned char c = *p; *p++ = ~c; } while (p != msk + sizeof(msk)); } /* And now it is a flag of fault. */ fnegate = 1; /* NUL ('\0') is consided as normal character. This is match to Glibc. Note, there is no method to include NUL into symbol list. */ do { i = getc (stream); if (i < 0) break; if (!((msk[(unsigned char)i >> 3] >> (i & 7)) & 1)) { ungetc (i, stream); break; } if (addr) *addr++ = i; fnegate = 0; } while (--width); if (fnegate) { return 0; } else { if (addr) *addr = 0; return fmt; } } #endif /* SCANF_BRACKET */ #if SCANF_FLOAT /* GCC before 4.2 does not use a library function to convert an unsigned long to float. Instead it uses a signed long to float conversion function along with a large inline code to correct the result. Seems, GCC 4.3 does not use it also. */ extern double __floatunsisf (unsigned long); PROGMEM static const float pwr_p10 [6] = { 1e+1, 1e+2, 1e+4, 1e+8, 1e+16, 1e+32 }; PROGMEM static const float pwr_m10 [6] = { 1e-1, 1e-2, 1e-4, 1e-8, 1e-16, 1e-32 }; PROGMEM static const char pstr_nfinity[] = "nfinity"; PROGMEM static const char pstr_an[] = "an"; __attribute__((noinline)) ATTRIBUTE_CLIB_SECTION static unsigned char conv_flt (FILE *stream, width_t width, float *addr) { union { unsigned long u32; float flt; } x; int i; const char *p; int exp; unsigned char flag; #define FL_MINUS 0x80 /* number is negative */ #define FL_ANY 0x02 /* any digit was readed */ #define FL_OVFL 0x04 /* overflow was */ #define FL_DOT 0x08 /* decimal '.' was */ #define FL_MEXP 0x10 /* exponent 'e' is neg. */ i = getc (stream); /* after ungetc() */ flag = 0; switch ((unsigned char)i) { case '-': flag = FL_MINUS; /* FALLTHROUGH */ case '+': if (!--width || (i = getc (stream)) < 0) goto err; } switch (tolower (i)) { case 'n': p = pstr_an; goto operate_pstr; case 'i': p = pstr_nfinity; operate_pstr: { unsigned char c; while ((c = pgm_read_byte (p++)) != 0) { if (!--width || (i = getc (stream)) < 0 || ((unsigned char)tolower(i) != c && (ungetc (i, stream), 1))) { if (p == pstr_nfinity + 3) break; goto err; } } } x.flt = (p == pstr_an + 3) ? NAN : INFINITY; break; default: exp = 0; x.u32 = 0; do { unsigned char c = i - '0'; if (c <= 9) { flag |= FL_ANY; if (flag & FL_OVFL) { if (!(flag & FL_DOT)) exp += 1; } else { if (flag & FL_DOT) exp -= 1; x.u32 = mulacc (x.u32, FL_DEC, c); if (x.u32 >= (ULONG_MAX - 9) / 10) flag |= FL_OVFL; } } else if (c == (('.'-'0') & 0xff) && !(flag & FL_DOT)) { flag |= FL_DOT; } else { break; } } while (--width && (i = getc (stream)) >= 0); if (!(flag & FL_ANY)) goto err; if ((unsigned char)i == 'e' || (unsigned char)i == 'E') { int expacc; if (!--width || (i = getc (stream)) < 0) goto err; switch ((unsigned char)i) { case '-': flag |= FL_MEXP; /* FALLTHROUGH */ case '+': if (!--width) goto err; i = getc (stream); /* test EOF will below */ } if (!isdigit (i)) goto err; expacc = 0; do { expacc = mulacc (expacc, FL_DEC, i - '0'); } while (--width && isdigit (i = getc(stream))); if (flag & FL_MEXP) expacc = -expacc; exp += expacc; } if (width && i >= 0) ungetc (i, stream); x.flt = __floatunsisf (x.u32); if (exp < 0) { p = (void *)(pwr_m10 + 5); exp = -exp; } else { p = (void *)(pwr_p10 + 5); } for (width = 32; width; width >>= 1) { for (; (unsigned)exp >= width; exp -= width) { union { long lo; float fl; } y; y.lo = pgm_read_dword (p); x.flt *= y.fl; } p = (void *)p - sizeof(float); } } /* switch */ if (flag & FL_MINUS) x.flt = -x.flt; if (addr) *addr = x.flt; return 1; err: return 0; } #endif /* SCANF_FLOAT */ __attribute__((noinline)) ATTRIBUTE_CLIB_SECTION static int skip_spaces (FILE *stream) { int i; do { if ((i = getc (stream)) < 0) return i; } while (isspace (i)); ungetc (i, stream); return i; } /** Formatted input. This function is the heart of the \b scanf family of functions. Characters are read from \a stream and processed in a way described by \a fmt. Conversion results will be assigned to the parameters passed via \a ap. The format string \a fmt is scanned for conversion specifications. Anything that doesn't comprise a conversion specification is taken as text that is matched literally against the input. White space in the format string will match any white space in the data (including none), all other characters match only itself. Processing is aborted as soon as the data and format string no longer match, or there is an error or end-of-file condition on \a stream. Most conversions skip leading white space before starting the actual conversion. Conversions are introduced with the character \b %. Possible options can follow the \b %: - a \c * indicating that the conversion should be performed but the conversion result is to be discarded; no parameters will be processed from \c ap, - the character \c h indicating that the argument is a pointer to short int (rather than int), - the 2 characters \c hh indicating that the argument is a pointer to char (rather than int). - the character \c l indicating that the argument is a pointer to long int (rather than int, for integer type conversions), or a pointer to \c double (for floating point conversions), In addition, a maximal field width may be specified as a nonzero positive decimal integer, which will restrict the conversion to at most this many characters from the input stream. This field width is limited to at most 255 characters which is also the default value (except for the %c conversion that defaults to 1). The following conversion flags are supported: - \c % Matches a literal \c % character. This is not a conversion. - \c d Matches an optionally signed decimal integer; the next pointer must be a pointer to \c int. - \c i Matches an optionally signed integer; the next pointer must be a pointer to \c int. The integer is read in base 16 if it begins with \b 0x or \b 0X, in base 8 if it begins with \b 0, and in base 10 otherwise. Only characters that correspond to the base are used. - \c o Matches an octal integer; the next pointer must be a pointer to unsigned int. - \c u Matches an optionally signed decimal integer; the next pointer must be a pointer to unsigned int. - \c x Matches an optionally signed hexadecimal integer; the next pointer must be a pointer to unsigned int. - \c f Matches an optionally signed floating-point number; the next pointer must be a pointer to \c float. - e, g, F, E, G Equivalent to \c f. - \c s Matches a sequence of non-white-space characters; the next pointer must be a pointer to \c char, and the array must be large enough to accept all the sequence and the terminating \c NUL character. The input string stops at white space or at the maximum field width, whichever occurs first. - \c c Matches a sequence of width count characters (default 1); the next pointer must be a pointer to \c char, and there must be enough room for all the characters (no terminating \c NUL is added). The usual skip of leading white space is suppressed. To skip white space first, use an explicit space in the format. - \c [ Matches a nonempty sequence of characters from the specified set of accepted characters; the next pointer must be a pointer to \c char, and there must be enough room for all the characters in the string, plus a terminating \c NUL character. The usual skip of leading white space is suppressed. The string is to be made up of characters in (or not in) a particular set; the set is defined by the characters between the open bracket \c [ character and a close bracket \c ] character. The set excludes those characters if the first character after the open bracket is a circumflex \c ^. To include a close bracket in the set, make it the first character after the open bracket or the circumflex; any other position will end the set. The hyphen character \c - is also special; when placed between two other characters, it adds all intervening characters to the set. To include a hyphen, make it the last character before the final close bracket. For instance, [^]0-9-] means the set of everything except close bracket, zero through nine, and hyphen. The string ends with the appearance of a character not in the (or, with a circumflex, in) set or when the field width runs out. Note that usage of this conversion enlarges the stack expense. - \c p Matches a pointer value (as printed by %p in printf()); the next pointer must be a pointer to \c void. - \c n Nothing is expected; instead, the number of characters consumed thus far from the input is stored through the next pointer, which must be a pointer to \c int. This is not a conversion, although it can be suppressed with the \c * flag. These functions return the number of input items assigned, which can be fewer than provided for, or even zero, in the event of a matching failure. Zero indicates that, while there was input available, no conversions were assigned; typically this is due to an invalid input character, such as an alphabetic character for a %d conversion. The value \c EOF is returned if an input failure occurs before any conversion such as an end-of-file occurs. If an error or end-of-file occurs after conversion has begun, the number of conversions which were successfully completed is returned. By default, all the conversions described above are available except the floating-point conversions and the width is limited to 255 characters. The float-point conversion will be available in the extended version provided by the library \c libscanf_flt.a. Also in this case the width is not limited (exactly, it is limited to 65535 characters). To link a program against the extended version, use the following compiler flags in the link stage: \code -Wl,-u,vfscanf -lscanf_flt -lm \endcode A third version is available for environments that are tight on space. In addition to the restrictions of the standard one, this version implements no %[ specification. This version is provided in the library \c libscanf_min.a, and can be requested using the following options in the link stage: \code -Wl,-u,vfscanf -lscanf_min -lm \endcode */ ATTRIBUTE_CLIB_SECTION int vfscanf (FILE * stream, const char *fmt, va_list ap) { unsigned char nconvs; unsigned char stream_flags; unsigned char c; width_t width; void *addr; unsigned char flags; int i; nconvs = 0; stream->len = 0; /* Initialization of stream_flags at each pass simplifies the register allocation with GCC 3.3 - 4.2. Only the GCC 4.3 is good to move it to the begin. */ while ((c = GETBYTE (stream_flags = stream->flags, __SPGM, fmt)) != 0) { if (isspace (c)) { skip_spaces (stream); } else if (c != '%' || (c = GETBYTE (stream_flags, __SPGM, fmt)) == '%') { /* Ordinary character. */ if ((i = getc (stream)) < 0) goto eof; if ((unsigned char)i != c) { ungetc (i, stream); break; } } else { flags = 0; if (c == '*') { flags = FL_STAR; c = GETBYTE (stream_flags, __SPGM, fmt); } width = 0; while ((c -= '0') < 10) { flags |= FL_WIDTH; width = mulacc (width, FL_DEC, c); c = GETBYTE (stream_flags, __SPGM, fmt); } c += '0'; if (flags & FL_WIDTH) { /* C99 says that width must be greater than zero. To simplify program do treat 0 as error in format. */ if (!width) break; } else { width = ~0; } /* ATTENTION: with FL_CHAR the FL_LONG is set also. */ switch (c) { case 'h': if ((c = GETBYTE (stream_flags, __SPGM, fmt)) != 'h') break; flags |= FL_CHAR; /* FALLTHROUGH */ case 'l': flags |= FL_LONG; c = GETBYTE (stream_flags, __SPGM, fmt); } #define CNV_BASE "cdinopsuxX" #if SCANF_BRACKET # define CNV_BRACKET "[" #else # define CNV_BRACKET "" #endif #if SCANF_FLOAT # define CNV_FLOAT "efgEFG" #else # define CNV_FLOAT "" #endif #define CNV_LIST CNV_BASE CNV_BRACKET CNV_FLOAT if (!c || !strchr_P (PSTR (CNV_LIST), c)) break; addr = (flags & FL_STAR) ? 0 : va_arg (ap, void *); if (c == 'n') { putval (addr, (unsigned)(stream->len), flags); continue; } if (c == 'c') { if (!(flags & FL_WIDTH)) width = 1; do { if ((i = getc (stream)) < 0) goto eof; if (addr) *(char *)addr++ = i; } while (--width); c = 1; /* no matter with smart GCC */ #if SCANF_BRACKET } else if (c == '[') { fmt = conv_brk (stream, width, addr, fmt); c = (fmt != 0); #endif } else { if (skip_spaces (stream) < 0) goto eof; switch (c) { case 's': /* Now we have 1 nospace symbol. */ do { if ((i = getc (stream)) < 0) break; if (isspace (i)) { ungetc (i, stream); break; } if (addr) *(char *)addr++ = i; } while (--width); if (addr) *(char *)addr = 0; c = 1; /* no matter with smart GCC */ break; #if SCANF_FLOAT case 'p': case 'x': case 'X': flags |= FL_HEX; goto conv_int; case 'd': case 'u': flags |= FL_DEC; goto conv_int; case 'o': flags |= FL_OCT; /* FALLTHROUGH */ case 'i': conv_int: c = conv_int (stream, width, addr, flags); break; default: /* e,E,f,F,g,G */ c = conv_flt (stream, width, addr); #else case 'd': case 'u': flags |= FL_DEC; goto conv_int; case 'o': flags |= FL_OCT; /* FALLTHROUGH */ case 'i': goto conv_int; default: /* p,x,X */ flags |= FL_HEX; conv_int: c = conv_int (stream, width, addr, flags); #endif } } /* else */ if (!c) { if (stream->flags & (__SERR | __SEOF)) goto eof; break; } if (!(flags & FL_STAR)) nconvs += 1; } /* else */ } /* while */ return nconvs; eof: return nconvs ? nconvs : EOF; } #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/stdio/putchar.c0000644000000000000000000000331511732702554014721 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: putchar.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #undef putchar ATTRIBUTE_CLIB_SECTION int putchar(int c) { return putc(c, stdout); } avr-libc-1.8.0.orig/libc/stdio/fprintf_p.c0000644000000000000000000000361411732702554015244 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fprintf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int fprintf_P(FILE *stream, const char *fmt, ...) { va_list ap; int i; va_start(ap, fmt); stream->flags |= __SPGM; i = vfprintf(stream, fmt, ap); stream->flags &= ~__SPGM; va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/vfscanf_p.c0000644000000000000000000000355111732702554015222 0ustar /* Copyright (c) 2003, Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vfscanf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int vfscanf_P(FILE *stream, const char *fmt, va_list ap) { int i; stream->flags |= __SPGM; i = vfscanf(stream, fmt, ap); stream->flags &= ~__SPGM; return i; } avr-libc-1.8.0.orig/libc/stdio/fscanf.c0000644000000000000000000000346511732702554014521 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fscanf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int fscanf(FILE *stream, const char *fmt, ...) { va_list ap; int i; va_start(ap, fmt); i = vfscanf(stream, fmt, ap); va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/getchar.c0000644000000000000000000000331111732702554014664 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: getchar.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #undef getchar ATTRIBUTE_CLIB_SECTION int getchar(void) { return getc(stdin); } avr-libc-1.8.0.orig/libc/stdio/ultoa_invert.S0000644000000000000000000001172511732702554015752 0ustar /* Copyright (c) 2005,2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ultoa_invert.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #ifndef __DOXYGEN__ #include "macros.inc" #include "ntz.h" #include "xtoa_fast.h" /* -------------------------------------------------------------------- char * __ultoa_invert (unsigned long val, char * str, int base) This function is intended for usage as internal printf's one. It differs from others of `xtoa_fast' family: * srt[] will NOT 0 terminated. * Sequence of digits is inverted. * It returns pointer to first byte after a string. * Only `XTOA_UPPER' flag is operated. Notes: * base: check only 8 and 16, all others are treated as 10. (internal printf's function). */ /* Input */ #define v_lo r22 #define v_hi r23 #define v_hlo r24 #define v_hhi r25 #define str_lo r20 #define str_hi r21 #define base r18 #define flags r19 /* Used */ #define v_fifth r26 /* val: bits 39..32 */ #define t_lo r18 /* temporary for shifted `val' */ #define t_hi r19 #define t_hlo r20 #define t_hhi r21 #define symb r20 /* write to string */ #define cnt r27 /* shift loop counter, local arg */ /* Fixed */ #define rzero r1 ASSEMBLY_CLIB_SECTION .global __ultoa_invert .type __ultoa_invert, "function" __ultoa_invert: X_movw ZL, str_lo clr v_fifth ; needed for all (ultoa_lsr) cpi base, 8 breq .L_oct cpi base, 16 breq .L_hex ; decimal format clt ; flag of val == 0 .L_dec_loop: push v_lo ; to calculate remander ; val &= ~1 andi v_lo, ~1 ; val += 2 subi v_lo, lo8(-2) sbci v_hi, hi8(-2) sbci v_hlo, hlo8(-2) sbci v_hhi, hhi8(-2) sbci v_fifth, hhi8(-2) ; val += val/2 ldi cnt, 1 rcall .L_div_add ; val += val/16 ldi cnt, 4 rcall .L_div_add ; val += val/256 add v_lo, v_hi adc v_hi, v_hlo adc v_hlo, v_hhi adc v_hhi, v_fifth adc v_fifth, rzero ; val += val/65536 add v_lo, v_hlo adc v_hi, v_hhi adc v_hlo, v_fifth adc v_hhi, rzero adc v_fifth, rzero ; val += val >> 32 add v_lo, v_fifth adc v_hi, rzero adc v_hlo, rzero adc v_hhi, rzero adc v_fifth, rzero ; division result: val /= 16 rcall .L_lsr_4 ; v_fitth := 0 brne 1f set ; T := Z flag 1: ; rem: val_original - 10*val pop t_hi #if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ ldi t_lo, 10 mul t_lo, v_lo clr r1 #else mov r0, v_lo lsl r0 sub t_hi, r0 lsl r0 lsl r0 #endif sub t_hi, r0 ; output digit subi t_hi, lo8(-'0') st Z+, t_hi ; quotient == 0 ? brtc .L_dec_loop ; end of string .L_eos: X_movw r24, ZL ret ; octal format .L_oct: mov symb, v_lo andi symb, 7 subi symb, lo8(-'0') st Z+, symb ldi cnt, 3 rcall .L_lsr brne .L_oct rjmp .L_eos ; hex format .L_hex: mov symb, v_lo andi symb, 0x0f subi symb, lo8(-'0') cpi symb, '9' + 1 brlo 3f subi symb, lo8('9' + 1 - 'a') sbrc flags, ntz(XTOA_UPPER) - 8 subi symb, lo8('a' - 'A') 3: st Z+, symb rcall .L_lsr_4 brne .L_hex rjmp .L_eos .L_lsr_4: ldi cnt, 4 .L_lsr: lsr v_fifth ror v_hhi ror v_hlo ror v_hi ror v_lo dec cnt brne .L_lsr ; tst sbiw v_hlo, 0 ; only Z flag is needed cpc v_lo, rzero cpc v_hi, rzero ret .L_div_add: ; copy to temporary X_movw t_lo, v_lo X_movw t_hlo, v_hlo mov r0, v_fifth ; lsr temporary 7: lsr r0 ror t_hhi ror t_hlo ror t_hi ror t_lo dec cnt brne 7b ; add add v_lo, t_lo adc v_hi, t_hi adc v_hlo, t_hlo adc v_hhi, t_hhi adc v_fifth, r0 ; here r0 == 0 ret .size __ultoa_invert, . - __ultoa_invert .end #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/stdio/snprintf_p.c0000644000000000000000000000472311732702554015441 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: snprintf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int snprintf_P(char *s, size_t n, const char *fmt, ...) { va_list ap; FILE f; int i; f.flags = __SWR | __SSTR | __SPGM; f.buf = s; /* Restrict max output length to 32767, as snprintf() return signed int. The fputc() function uses a signed comparison between estimated len and f.size field. So we can write a negative value into f.size in the case of n was 0. Note, that f.size will be a max number of nonzero symbols. */ if ((int)n < 0) n = (unsigned)INT_MAX + 1; /* 32768 */ f.size = n - 1; /* -1,0,...32767 */ va_start(ap, fmt); i = vfprintf(&f, fmt, ap); va_end(ap); /* We use f.size (not 'n') as this is more effective: two 'ld' instructions vs. two 'push+pop' and 'movw'. */ if (f.size >= 0) s[f.len < f.size ? f.len : f.size] = 0; return i; } avr-libc-1.8.0.orig/libc/stdio/Rules.am0000644000000000000000000000523011732702554014516 0ustar # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # include $(top_srcdir)/libc/stdio/Files.am stdio_a_libadd = vfprintf_std.o vfscanf_std.o nodist_libprintf_min_a_SOURCES= libprintf_min_a_LIBADD = vfprintf_min.o nodist_libprintf_flt_a_SOURCES= libprintf_flt_a_LIBADD = vfprintf_flt.o nodist_libscanf_min_a_SOURCES= libscanf_min_a_LIBADD = vfscanf_min.o nodist_libscanf_flt_a_SOURCES= libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) vfprintf_min.o: vfprintf.c $(COMPILE) $(PRINTF_CFLAGS) -DPRINTF_LEVEL=PRINTF_MIN -c -o $@ $< vfprintf_std.o: vfprintf.c $(COMPILE) $(PRINTF_CFLAGS) -DPRINTF_LEVEL=PRINTF_STD -c -o $@ $< vfprintf_flt.o: vfprintf.c $(COMPILE) $(PRINTF_CFLAGS) -DPRINTF_LEVEL=PRINTF_FLT -c -o $@ $< vfscanf_min.o: vfscanf.c $(COMPILE) $(PRINTF_CFLAGS) -DSCANF_LEVEL=SCANF_MIN -c -o $@ $< vfscanf_std.o: vfscanf.c $(COMPILE) $(PRINTF_CFLAGS) -DSCANF_LEVEL=SCANF_STD -c -o $@ $< vfscanf_flt.o: vfscanf.c $(COMPILE) $(PRINTF_CFLAGS) -DSCANF_LEVEL=SCANF_FLT -c -o $@ $< # vim: set ft=make: avr-libc-1.8.0.orig/libc/stdio/fscanf_p.c0000644000000000000000000000361111732702554015031 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fscanf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int fscanf_P(FILE *stream, const char *fmt, ...) { va_list ap; int i; va_start(ap, fmt); stream->flags |= __SPGM; i = vfscanf(stream, fmt, ap); stream->flags &= ~__SPGM; va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/gets.c0000644000000000000000000000361711732702554014222 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: gets.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION char * gets(char *str) { char *cp; int c; if ((stdin->flags & __SRD) == 0) return NULL; for (c = 0, cp = str; c != '\n'; cp++) { if ((c = getchar()) == EOF) return NULL; *cp = (char)c; } *--cp = '\0'; return str; } avr-libc-1.8.0.orig/libc/stdio/vfprintf_p.c0000644000000000000000000000356011732702554015432 0ustar /* Copyright (c) 2003, Theodore A. Roth All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vfprintf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int vfprintf_P (FILE *stream, const char *fmt, va_list ap) { int i; stream->flags |= __SPGM; i = vfprintf(stream, fmt, ap); stream->flags &= ~__SPGM; return i; } avr-libc-1.8.0.orig/libc/stdio/feof.c0000644000000000000000000000336211732702554014174 0ustar /* Copyright (c) 2002,2005 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: feof.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" #undef feof ATTRIBUTE_CLIB_SECTION int feof(FILE *stream) { return stream->flags & __SEOF; } avr-libc-1.8.0.orig/libc/stdio/puts.c0000644000000000000000000000363011732702554014246 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: puts.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int puts(const char *str) { char c; int rv = 0; if ((stdout->flags & __SWR) == 0) return EOF; while ((c = *str++) != '\0') if (stdout->put(c, stdout) != 0) rv = EOF; if (stdout->put('\n', stdout) != 0) rv = EOF; return rv; } avr-libc-1.8.0.orig/libc/stdio/sprintf.c0000644000000000000000000000366011732702554014743 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: sprintf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int sprintf(char *s, const char *fmt, ...) { va_list ap; FILE f; int i; f.flags = __SWR | __SSTR; f.buf = s; f.size = INT_MAX; va_start(ap, fmt); i = vfprintf(&f, fmt, ap); va_end(ap); s[f.len] = 0; return i; } avr-libc-1.8.0.orig/libc/stdio/getc.S0000644000000000000000000000341311732702554014154 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: getc.S 1944 2009-04-01 23:12:20Z arcanum $ */ #include "macros.inc" /* int getc(FILE *stream); */ ASSEMBLY_CLIB_SECTION .global _U(getc) .type _U(getc), @function _U(getc): XJMP fgetc .L_getc_end: .size _U(getc), .L_getc_end - _U(getc) avr-libc-1.8.0.orig/libc/stdio/fread.c0000644000000000000000000000375411732702554014343 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fread.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream) { size_t i, j; uint8_t *cp; int c; if ((stream->flags & __SRD) == 0) return 0; for (i = 0, cp = (uint8_t *)ptr; i < nmemb; i++) for (j = 0; j < size; j++) { c = getc(stream); if (c == EOF) return i; *cp++ = (uint8_t)c; } return i; } avr-libc-1.8.0.orig/libc/stdio/Makefile.am0000644000000000000000000000331111732702554015137 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # include $(top_srcdir)/libc/stdio/Files.am EXTRA_DIST = \ $(stdio_a_c_sources) \ $(stdio_a_asm_sources) \ $(stdio_a_extra_dist) avr-libc-1.8.0.orig/libc/stdio/fgetc.c0000644000000000000000000000435311732702554014346 0ustar /* Copyright (c) 2002, 2005, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: fgetc.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int fgetc(FILE *stream) { int rv; if ((stream->flags & __SRD) == 0) return EOF; if ((stream->flags & __SUNGET) != 0) { stream->flags &= ~__SUNGET; stream->len++; return stream->unget; } if (stream->flags & __SSTR) { rv = *stream->buf; if (rv == '\0') { stream->flags |= __SEOF; return EOF; } else { stream->buf++; } } else { rv = stream->get(stream); if (rv < 0) { /* if != _FDEV_ERR, assume it's _FDEV_EOF */ stream->flags |= (rv == _FDEV_ERR)? __SERR: __SEOF; return EOF; } } stream->len++; return (unsigned char)rv; } avr-libc-1.8.0.orig/libc/stdio/printf.c0000644000000000000000000000345011732702554014555 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: printf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int printf(const char *fmt, ...) { va_list ap; int i; va_start(ap, fmt); i = vfprintf(stdout, fmt, ap); va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/xtoa_fast.h0000644000000000000000000000476411732702554015261 0ustar /* Copyright (c) 2005, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: xtoa_fast.h 1223 2007-02-18 13:33:09Z dmix $ */ #ifndef _XTOA_FAST_H_ #define _XTOA_FAST_H_ #ifndef __ASSEMBLER__ #include /* for 'size_t' */ char * itoa_fast (int val, char *s, int base); char * utoa_fast (unsigned val, char *s, int base); char * ltoa_fast (long val, char *s, int base); char * ultoa_fast (unsigned long val, char *s, int base); char * itoa_width (int val, char *s, int base, size_t width); char * utoa_width (unsigned val, char *s, int base, size_t width); char * ltoa_width (long val, char *s, int base, size_t width); char * ultoa_width (unsigned long val, char *s, int base, size_t width); /* Internal function for use from `printf'. */ char * __ultoa_invert (unsigned long val, char *s, int base); #endif /* ifndef __ASSEMBLER__ */ /* Next flags are to use with `base'. Unused fields are reserved. */ #define XTOA_PREFIX 0x0100 /* put prefix for octal or hex */ #define XTOA_UPPER 0x0200 /* use upper case letters */ #endif /* _XTOA_FAST_H_ */ avr-libc-1.8.0.orig/libc/stdio/ferror.c0000644000000000000000000000337011732702554014553 0ustar /* Copyright (c) 2002,2005 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ferror.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "sectionname.h" #include "stdio_private.h" #undef ferror ATTRIBUTE_CLIB_SECTION int ferror(FILE *stream) { return stream->flags & __SERR; } avr-libc-1.8.0.orig/libc/stdio/sprintf_p.c0000644000000000000000000000367511732702554015270 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: sprintf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int sprintf_P(char *s, const char *fmt, ...) { va_list ap; FILE f; int i; f.flags = __SWR | __SSTR | __SPGM; f.buf = s; f.size = INT_MAX; va_start(ap, fmt); i = vfprintf(&f, fmt, ap); va_end(ap); s[f.len] = 0; return i; } avr-libc-1.8.0.orig/libc/stdio/snprintf.c0000644000000000000000000000470611732702554015123 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: snprintf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int snprintf(char *s, size_t n, const char *fmt, ...) { va_list ap; FILE f; int i; f.flags = __SWR | __SSTR; f.buf = s; /* Restrict max output length to 32767, as snprintf() return signed int. The fputc() function uses a signed comparison between estimated len and f.size field. So we can write a negative value into f.size in the case of n was 0. Note, that f.size will be a max number of nonzero symbols. */ if ((int)n < 0) n = (unsigned)INT_MAX + 1; /* 32768 */ f.size = n - 1; /* -1,0,...32767 */ va_start(ap, fmt); i = vfprintf(&f, fmt, ap); va_end(ap); /* We use f.size (not 'n') as this is more effective: two 'ld' instructions vs. two 'push+pop' and 'movw'. */ if (f.size >= 0) s[f.len < f.size ? f.len : f.size] = 0; return i; } avr-libc-1.8.0.orig/libc/stdio/puts_p.c0000644000000000000000000000423011732702554014562 0ustar /* Copyright (c) 2002,2004 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: puts_p.c 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int puts_P(const char *str) { char c; int rv = 0; if ((stdout->flags & __SWR) == 0) return EOF; /* * Do not use str++ in the next line. pgm_read_byte() is a * macro, so it could evaluate its argument more than once. */ while ((c = pgm_read_byte(str)) != '\0') { if (stdout->put(c, stdout) != 0) rv = EOF; str++; } if (stdout->put('\n', stdout) != 0) rv = EOF; return rv; } #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/stdio/sscanf.c0000644000000000000000000000440311732702554014527 0ustar /* Copyright (c) 2002, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: sscanf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" #include "stdio_private.h" ATTRIBUTE_CLIB_SECTION int sscanf(const char *s, const char *fmt, ...) { va_list ap; FILE f; int i; f.flags = __SRD | __SSTR; /* * It is OK to discard the "const" qualifier here. f.buf is * non-const as in the generic case, this buffer is obtained * by malloc(). In the scanf case however, the buffer is * really only be read (by getc()), and as this our FILE f we * be discarded upon exiting sscanf(), nobody will ever get * a chance to get write access to it again. */ f.buf = (char *)s; va_start(ap, fmt); i = vfscanf(&f, fmt, ap); va_end(ap); return i; } avr-libc-1.8.0.orig/libc/stdio/vsnprintf_p.c0000644000000000000000000000465611732702554015634 0ustar /* Copyright (c) 2003, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: vsnprintf_p.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int vsnprintf_P(char *s, size_t n, const char *fmt, va_list ap) { FILE f; int i; f.flags = __SWR | __SSTR | __SPGM; f.buf = s; /* Restrict max output length to 32767, as snprintf() return signed int. The fputc() function uses a signed comparison between estimated len and f.size field. So we can write a negative value into f.size in the case of n was 0. Note, that f.size will be a max number of nonzero symbols. */ if ((int)n < 0) n = (unsigned)INT_MAX + 1; /* 32768 */ f.size = n - 1; /* -1,0,...32767 */ i = vfprintf(&f, fmt, ap); /* We use f.size (not 'n') as this is more effective: two 'ld' instructions vs. two 'push+pop' and 'movw'. */ if (f.size >= 0) s[f.len < f.size ? f.len : f.size] = 0; return i; } avr-libc-1.8.0.orig/libc/stdio/vfprintf.c0000644000000000000000000003707311732702554015121 0ustar /* Copyright (c) 2002, Alexander Popov (sasho@vip.bg) Copyright (c) 2002,2004,2005 Joerg Wunsch Copyright (c) 2005, Helmut Wallner Copyright (c) 2007, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* From: Id: printf_p_new.c,v 1.1.1.9 2002/10/15 20:10:28 joerg_wunsch Exp */ /* $Id: vfprintf.c 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include #include #include #include #include #include "sectionname.h" #include "stdio_private.h" #include "ftoa_engine.h" #include "ntz.h" #include "xtoa_fast.h" /* * This file can be compiled into more than one flavour. The default * is to offer the usual modifiers and integer formatting support * (level 2). Level 1 maintains a minimal version that just offers * integer formatting, but no modifier support whatsoever. Level 3 is * intented for floating point support. */ #ifndef PRINTF_LEVEL # define PRINTF_LEVEL PRINTF_STD #endif #if PRINTF_LEVEL == PRINTF_MIN || PRINTF_LEVEL == PRINTF_STD \ || PRINTF_LEVEL == PRINTF_FLT /* OK */ #else # error "Not a known printf level." #endif #ifndef __AVR_HAVE_LPMX__ # if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ # define __AVR_HAVE_LPMX__ 1 # endif #endif #if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ # define GETBYTE(flag, mask, pnt) ({ \ unsigned char __c; \ asm ( \ "sbrc %2,%3 \n\t" \ "lpm %0,Z+ \n\t" \ "sbrs %2,%3 \n\t" \ "ld %0,Z+ " \ : "=r" (__c), \ "+z" (pnt) \ : "r" (flag), \ "I" (ntz(mask)) \ ); \ __c; \ }) #elif 1 # define GETBYTE(flag, mask, pnt) ({ \ unsigned char __c; \ asm ( \ "sbrc %2,%3 \n\t" \ "lpm \n\t" \ "sbrs %2,%3 \n\t" \ "ld r0,Z \n\t" \ "adiw r30,1 \n\t" \ "mov %0,r0 " \ : "=r" (__c), \ "+z" (pnt) \ : "r" (flag), \ "I" (ntz(mask)) \ : "r0" \ ); \ __c; \ }) #else # define GETBYTE(flag, mask, pnt) ({ \ unsigned char __c; \ __c = ((flag) & (mask)) \ ? pgm_read_byte(pnt) : *pnt; \ pnt++; \ __c; \ }) #endif /* -------------------------------------------------------------------- */ #if PRINTF_LEVEL <= PRINTF_MIN #define FL_PGMSTRING 0x01 #define FL_ALTHEX 0x04 #define FL_ALT 0x10 #define FL_ALTLWR 0x20 #define FL_NEGATIVE 0x40 #define FL_LONG 0x80 ATTRIBUTE_CLIB_SECTION int vfprintf (FILE * stream, const char *fmt, va_list ap) { unsigned char c; /* holds a char from the format string */ unsigned char flags; unsigned char buf[11]; /* size for -1 in octal, without '\0' */ stream->len = 0; if ((stream->flags & __SWR) == 0) return EOF; for (;;) { for (;;) { c = GETBYTE (stream->flags, __SPGM, fmt); if (!c) goto ret; if (c == '%') { c = GETBYTE (stream->flags, __SPGM, fmt); if (c != '%') break; } putc (c, stream); } for (flags = 0; !(flags & FL_LONG); /* 'll' will detect as error */ c = GETBYTE (stream->flags, __SPGM, fmt)) { if (c && strchr_P (PSTR(" +-.0123456789h"), c)) continue; if (c == '#') { flags |= FL_ALT; continue; } if (c == 'l') { flags |= FL_LONG; continue; } break; } /* Only a format character is valid. */ if (c && strchr_P (PSTR("EFGefg"), c)) { (void) va_arg (ap, double); putc ('?', stream); continue; } { const char * pnt; switch (c) { case 'c': putc (va_arg (ap, int), stream); continue; case 'S': flags |= FL_PGMSTRING; /* FALLTHROUGH */ case 's': pnt = va_arg (ap, char *); while ( (c = GETBYTE (flags, FL_PGMSTRING, pnt)) != 0) putc (c, stream); continue; } } if (c == 'd' || c == 'i') { long x = (flags & FL_LONG) ? va_arg(ap,long) : va_arg(ap,int); flags &= ~FL_ALT; if (x < 0) { x = -x; /* `putc ('-', stream)' will considarably inlarge stack size. So flag is used. */ flags |= FL_NEGATIVE; } c = __ultoa_invert (x, (char *)buf, 10) - (char *)buf; } else { int base; switch (c) { case 'u': flags &= ~FL_ALT; base = 10; goto ultoa; case 'o': base = 8; goto ultoa; case 'p': flags |= FL_ALT; /* no break */ case 'x': flags |= (FL_ALTHEX | FL_ALTLWR); base = 16; goto ultoa; case 'X': flags |= FL_ALTHEX; base = 16 | XTOA_UPPER; ultoa: c = __ultoa_invert ((flags & FL_LONG) ? va_arg(ap, unsigned long) : va_arg(ap, unsigned int), (char *)buf, base) - (char *)buf; break; default: goto ret; } } /* Integer number output. */ if (flags & FL_NEGATIVE) putc ('-', stream); if ((flags & FL_ALT) && (buf[c-1] != '0')) { putc ('0', stream); if (flags & FL_ALTHEX) #if FL_ALTLWR != 'x' - 'X' # error #endif putc ('X' + (flags & FL_ALTLWR), stream); } do { putc (buf[--c], stream); } while (c); } /* for (;;) */ ret: return stream->len; } /* -------------------------------------------------------------------- */ #else /* i.e. PRINTF_LEVEL > PRINTF_MIN */ #define FL_ZFILL 0x01 #define FL_PLUS 0x02 #define FL_SPACE 0x04 #define FL_LPAD 0x08 #define FL_ALT 0x10 #define FL_WIDTH 0x20 #define FL_PREC 0x40 #define FL_LONG 0x80 #define FL_PGMSTRING FL_LONG #define FL_NEGATIVE FL_LONG #define FL_ALTUPP FL_PLUS #define FL_ALTHEX FL_SPACE #define FL_FLTUPP FL_ALT #define FL_FLTEXP FL_PREC #define FL_FLTFIX FL_LONG ATTRIBUTE_CLIB_SECTION int vfprintf (FILE * stream, const char *fmt, va_list ap) { unsigned char c; /* holds a char from the format string */ unsigned char flags; unsigned char width; unsigned char prec; unsigned char buf[11]; /* size for -1 in octal, without '\0' */ stream->len = 0; if ((stream->flags & __SWR) == 0) return EOF; for (;;) { for (;;) { c = GETBYTE (stream->flags, __SPGM, fmt); if (!c) goto ret; if (c == '%') { c = GETBYTE (stream->flags, __SPGM, fmt); if (c != '%') break; } putc (c, stream); } flags = 0; width = 0; prec = 0; do { if (flags < FL_WIDTH) { switch (c) { case '0': flags |= FL_ZFILL; continue; case '+': flags |= FL_PLUS; /* FALLTHROUGH */ case ' ': flags |= FL_SPACE; continue; case '-': flags |= FL_LPAD; continue; case '#': flags |= FL_ALT; continue; } } if (flags < FL_LONG) { if (c >= '0' && c <= '9') { c -= '0'; if (flags & FL_PREC) { prec = 10*prec + c; continue; } width = 10*width + c; flags |= FL_WIDTH; continue; } if (c == '.') { if (flags & FL_PREC) goto ret; flags |= FL_PREC; continue; } if (c == 'l') { flags |= FL_LONG; continue; } if (c == 'h') continue; } break; } while ( (c = GETBYTE (stream->flags, __SPGM, fmt)) != 0); /* Only a format character is valid. */ #if 'F' != 'E'+1 || 'G' != 'F'+1 || 'f' != 'e'+1 || 'g' != 'f'+1 # error #endif #if PRINTF_LEVEL >= PRINTF_FLT if (c >= 'E' && c <= 'G') { flags |= FL_FLTUPP; c += 'e' - 'E'; goto flt_oper; } else if (c >= 'e' && c <= 'g') { int exp; /* exponent of master decimal digit */ int n; unsigned char vtype; /* result of float value parse */ unsigned char sign; /* sign character (or 0) */ # define ndigs c /* only for this block, undef is below */ flags &= ~FL_FLTUPP; flt_oper: if (!(flags & FL_PREC)) prec = 6; flags &= ~(FL_FLTEXP | FL_FLTFIX); if (c == 'e') flags |= FL_FLTEXP; else if (c == 'f') flags |= FL_FLTFIX; else if (prec > 0) prec -= 1; if (flags & FL_FLTFIX) { vtype = 7; /* 'prec' arg for 'ftoa_engine' */ ndigs = prec < 60 ? prec + 1 : 60; } else { if (prec > 7) prec = 7; vtype = prec; ndigs = 0; } exp = __ftoa_engine (va_arg(ap,double), (char *)buf, vtype, ndigs); vtype = buf[0]; sign = 0; if ((vtype & FTOA_MINUS) && !(vtype & FTOA_NAN)) sign = '-'; else if (flags & FL_PLUS) sign = '+'; else if (flags & FL_SPACE) sign = ' '; if (vtype & (FTOA_NAN | FTOA_INF)) { const char *p; ndigs = sign ? 4 : 3; if (width > ndigs) { width -= ndigs; if (!(flags & FL_LPAD)) { do { putc (' ', stream); } while (--width); } } else { width = 0; } if (sign) putc (sign, stream); p = PSTR("inf"); if (vtype & FTOA_NAN) p = PSTR("nan"); # if ('I'-'i' != 'N'-'n') || ('I'-'i' != 'F'-'f') || ('I'-'i' != 'A'-'a') # error # endif while ( (ndigs = pgm_read_byte(p)) != 0) { if (flags & FL_FLTUPP) ndigs += 'I' - 'i'; putc (ndigs, stream); p++; } goto tail; } /* Output format adjustment, number of decimal digits in buf[] */ if (flags & FL_FLTFIX) { ndigs += exp; if ((vtype & FTOA_CARRY) && buf[1] == '1') ndigs -= 1; if ((signed char)ndigs < 1) ndigs = 1; else if (ndigs > 8) ndigs = 8; } else if (!(flags & FL_FLTEXP)) { /* 'g(G)' format */ if (exp <= prec && exp >= -4) flags |= FL_FLTFIX; while (prec && buf[1+prec] == '0') prec--; if (flags & FL_FLTFIX) { ndigs = prec + 1; /* number of digits in buf */ prec = prec > exp ? prec - exp : 0; /* fractional part length */ } } /* Conversion result length, width := free space length */ if (flags & FL_FLTFIX) n = (exp>0 ? exp+1 : 1); else n = 5; /* 1e+00 */ if (sign) n += 1; if (prec) n += prec + 1; width = width > n ? width - n : 0; /* Output before first digit */ if (!(flags & (FL_LPAD | FL_ZFILL))) { while (width) { putc (' ', stream); width--; } } if (sign) putc (sign, stream); if (!(flags & FL_LPAD)) { while (width) { putc ('0', stream); width--; } } if (flags & FL_FLTFIX) { /* 'f' format */ n = exp > 0 ? exp : 0; /* exponent of left digit */ do { if (n == -1) putc ('.', stream); flags = (n <= exp && n > exp - ndigs) ? buf[exp - n + 1] : '0'; if (--n < -prec) break; putc (flags, stream); } while (1); if (n == exp && (buf[1] > '5' || (buf[1] == '5' && !(vtype & FTOA_CARRY))) ) { flags = '1'; } putc (flags, stream); } else { /* 'e(E)' format */ /* mantissa */ if (buf[1] != '1') vtype &= ~FTOA_CARRY; putc (buf[1], stream); if (prec) { putc ('.', stream); sign = 2; do { putc (buf[sign++], stream); } while (--prec); } /* exponent */ putc (flags & FL_FLTUPP ? 'E' : 'e', stream); ndigs = '+'; if (exp < 0 || (exp == 0 && (vtype & FTOA_CARRY) != 0)) { exp = -exp; ndigs = '-'; } putc (ndigs, stream); for (ndigs = '0'; exp >= 10; exp -= 10) ndigs += 1; putc (ndigs, stream); putc ('0' + exp, stream); } goto tail; # undef ndigs } #else /* to: PRINTF_LEVEL >= PRINTF_FLT */ if ((c >= 'E' && c <= 'G') || (c >= 'e' && c <= 'g')) { (void) va_arg (ap, double); buf[0] = '?'; goto buf_addr; } #endif { const char * pnt; size_t size; switch (c) { case 'c': buf[0] = va_arg (ap, int); #if PRINTF_LEVEL < PRINTF_FLT buf_addr: #endif pnt = (char *)buf; size = 1; goto no_pgmstring; case 's': pnt = va_arg (ap, char *); size = strnlen (pnt, (flags & FL_PREC) ? prec : ~0); no_pgmstring: flags &= ~FL_PGMSTRING; goto str_lpad; case 'S': pnt = va_arg (ap, char *); size = strnlen_P (pnt, (flags & FL_PREC) ? prec : ~0); flags |= FL_PGMSTRING; str_lpad: if (!(flags & FL_LPAD)) { while (size < width) { putc (' ', stream); width--; } } while (size) { putc (GETBYTE (flags, FL_PGMSTRING, pnt), stream); if (width) width -= 1; size -= 1; } goto tail; } } if (c == 'd' || c == 'i') { long x = (flags & FL_LONG) ? va_arg(ap,long) : va_arg(ap,int); flags &= ~(FL_NEGATIVE | FL_ALT); if (x < 0) { x = -x; flags |= FL_NEGATIVE; } c = __ultoa_invert (x, (char *)buf, 10) - (char *)buf; } else { int base; if (c == 'u') { flags &= ~FL_ALT; base = 10; goto ultoa; } flags &= ~(FL_PLUS | FL_SPACE); switch (c) { case 'o': base = 8; goto ultoa; case 'p': flags |= FL_ALT; /* no break */ case 'x': if (flags & FL_ALT) flags |= FL_ALTHEX; base = 16; goto ultoa; case 'X': if (flags & FL_ALT) flags |= (FL_ALTHEX | FL_ALTUPP); base = 16 | XTOA_UPPER; ultoa: c = __ultoa_invert ((flags & FL_LONG) ? va_arg(ap, unsigned long) : va_arg(ap, unsigned int), (char *)buf, base) - (char *)buf; flags &= ~FL_NEGATIVE; break; default: goto ret; } } { unsigned char len; len = c; if (flags & FL_PREC) { flags &= ~FL_ZFILL; if (len < prec) { len = prec; if ((flags & FL_ALT) && !(flags & FL_ALTHEX)) flags &= ~FL_ALT; } } if (flags & FL_ALT) { if (buf[c-1] == '0') { flags &= ~(FL_ALT | FL_ALTHEX | FL_ALTUPP); } else { len += 1; if (flags & FL_ALTHEX) len += 1; } } else if (flags & (FL_NEGATIVE | FL_PLUS | FL_SPACE)) { len += 1; } if (!(flags & FL_LPAD)) { if (flags & FL_ZFILL) { prec = c; if (len < width) { prec += width - len; len = width; } } while (len < width) { putc (' ', stream); len++; } } width = (len < width) ? width - len : 0; if (flags & FL_ALT) { putc ('0', stream); if (flags & FL_ALTHEX) putc (flags & FL_ALTUPP ? 'X' : 'x', stream); } else if (flags & (FL_NEGATIVE | FL_PLUS | FL_SPACE)) { unsigned char z = ' '; if (flags & FL_PLUS) z = '+'; if (flags & FL_NEGATIVE) z = '-'; putc (z, stream); } while (prec > c) { putc ('0', stream); prec--; } do { putc (buf[--c], stream); } while (c); } tail: /* Tail is possible. */ while (width) { putc (' ', stream); width--; } } /* for (;;) */ ret: return stream->len; } #endif /* PRINTF_LEVEL > PRINTF_MIN */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/Makefile.am0000644000000000000000000000324411732702554014022 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # SUBDIRS = stdlib pmstring string misc stdio DIST_SUBDIRS = stdlib pmstring string misc stdio avr-libc-1.8.0.orig/libc/stdlib/0000755000000000000000000000000011732702554013244 5ustar avr-libc-1.8.0.orig/libc/stdlib/stdlib_private.h0000644000000000000000000000604111732702554016431 0ustar /* Copyright (c) 2004, Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: stdlib_private.h 1657 2008-03-24 17:11:08Z arcanum $ */ #include #include #include #if !defined(__DOXYGEN__) struct __freelist { size_t sz; struct __freelist *nx; }; #endif extern char *__brkval; /* first location not yet allocated */ extern struct __freelist *__flp; /* freelist pointer (head of freelist) */ extern size_t __malloc_margin; /* user-changeable before the first malloc() */ extern char *__malloc_heap_start; extern char *__malloc_heap_end; #ifndef __AVR__ /* * When compiling malloc.c/realloc.c natively on a host machine, it will * include a main() that performs a regression test. This is meant as * a debugging aid, where a normal source-level debugger will help to * verify that the various allocator structures have the desired * appearance at each stage. * * When cross-compiling with avr-gcc, it will compile into just the * library functions malloc() and free(). */ #define MALLOC_TEST #endif /* !__AVR__ */ #ifdef MALLOC_TEST extern void *mymalloc(size_t); extern void myfree(void *); extern void *myrealloc(void *, size_t); #define malloc mymalloc #define free myfree #define realloc myrealloc #define __heap_start mymem[0] #define __heap_end mymem[256] extern char mymem[]; #define STACK_POINTER() (mymem + 256) #else /* !MALLOC_TEST */ extern char __heap_start; extern char __heap_end; /* Needed for definition of AVR_STACK_POINTER_REG. */ #include #define STACK_POINTER() ((char *)AVR_STACK_POINTER_REG) #endif /* MALLOC_TEST */ avr-libc-1.8.0.orig/libc/stdlib/isalpha.S0000644000000000000000000000321011732702554015005 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: isalpha.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lisalpha 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/atoi.c0000644000000000000000000000321611732702554014346 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int atoi(const char *p) { return (int) atol(p); } avr-libc-1.8.0.orig/libc/stdlib/isdigit.S0000644000000000000000000000321011732702554015020 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: isdigit.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lisdigit 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/strtod.c0000644000000000000000000001450211732702554014731 0ustar /* Copyright (c) 2002-2005 Michael Stumpf Copyright (c) 2006,2008 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strtod.c 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #include #include #include #include #include /* INFINITY, NAN */ #include #include "sectionname.h" /* Only GCC 4.2 calls the library function to convert an unsigned long to float. Other GCC-es (including 4.3) use a signed long to float conversion along with a large inline code to correct the result. */ extern double __floatunsisf (unsigned long); PROGMEM static const float pwr_p10 [6] = { 1e+1, 1e+2, 1e+4, 1e+8, 1e+16, 1e+32 }; PROGMEM static const float pwr_m10 [6] = { 1e-1, 1e-2, 1e-4, 1e-8, 1e-16, 1e-32 }; /* PSTR() is not used to save 1 byte per string: '\0' at the tail. */ PROGMEM static const char pstr_inf[] = {'I','N','F'}; PROGMEM static const char pstr_inity[] = {'I','N','I','T','Y'}; PROGMEM static const char pstr_nan[] = {'N','A','N'}; /** The strtod() function converts the initial portion of the string pointed to by \a nptr to double representation. The expected form of the string is an optional plus ( \c '+' ) or minus sign ( \c '-' ) followed by a sequence of digits optionally containing a decimal-point character, optionally followed by an exponent. An exponent consists of an \c 'E' or \c 'e', followed by an optional plus or minus sign, followed by a sequence of digits. Leading white-space characters in the string are skipped. The strtod() function returns the converted value, if any. If \a endptr is not \c NULL, a pointer to the character after the last character used in the conversion is stored in the location referenced by \a endptr. If no conversion is performed, zero is returned and the value of \a nptr is stored in the location referenced by \a endptr. If the correct value would cause overflow, plus or minus \c INFINITY is returned (according to the sign of the value), and \c ERANGE is stored in \c errno. If the correct value would cause underflow, zero is returned and \c ERANGE is stored in \c errno. */ ATTRIBUTE_CLIB_SECTION double strtod (const char * nptr, char ** endptr) { union { unsigned long u32; float flt; } x; unsigned char c; int exp; unsigned char flag; #define FL_MINUS 0x01 /* number is negative */ #define FL_ANY 0x02 /* any digit was readed */ #define FL_OVFL 0x04 /* overflow was */ #define FL_DOT 0x08 /* decimal '.' was */ #define FL_MEXP 0x10 /* exponent 'e' is neg. */ if (endptr) *endptr = (char *)nptr; do { c = *nptr++; } while (isspace (c)); flag = 0; if (c == '-') { flag = FL_MINUS; c = *nptr++; } else if (c == '+') { c = *nptr++; } if (!strncasecmp_P (nptr - 1, pstr_inf, 3)) { nptr += 2; if (!strncasecmp_P (nptr, pstr_inity, 5)) nptr += 5; if (endptr) *endptr = (char *)nptr; return flag & FL_MINUS ? -INFINITY : +INFINITY; } /* NAN() construction is not realised. Length would be 3 characters only. */ if (!strncasecmp_P (nptr - 1, pstr_nan, 3)) { if (endptr) *endptr = (char *)nptr + 2; return NAN; } x.u32 = 0; exp = 0; while (1) { c -= '0'; if (c <= 9) { flag |= FL_ANY; if (flag & FL_OVFL) { if (!(flag & FL_DOT)) exp += 1; } else { if (flag & FL_DOT) exp -= 1; /* x.u32 = x.u32 * 10 + c */ x.u32 = (((x.u32 << 2) + x.u32) << 1) + c; if (x.u32 >= (ULONG_MAX - 9) / 10) flag |= FL_OVFL; } } else if (c == (('.'-'0') & 0xff) && !(flag & FL_DOT)) { flag |= FL_DOT; } else { break; } c = *nptr++; } if (c == (('e'-'0') & 0xff) || c == (('E'-'0') & 0xff)) { int i; c = *nptr++; i = 2; if (c == '-') { flag |= FL_MEXP; c = *nptr++; } else if (c == '+') { c = *nptr++; } else { i = 1; } c -= '0'; if (c > 9) { nptr -= i; } else { i = 0; do { if (i < 3200) i = (((i << 2) + i) << 1) + c; /* i = 10*i + c */ c = *nptr++ - '0'; } while (c <= 9); if (flag & FL_MEXP) i = -i; exp += i; } } if ((flag & FL_ANY) && endptr) *endptr = (char *)nptr - 1; x.flt = __floatunsisf (x.u32); /* manually */ if ((flag & FL_MINUS) && (flag & FL_ANY)) x.flt = -x.flt; if (x.flt != 0) { int pwr; if (exp < 0) { nptr = (void *)(pwr_m10 + 5); exp = -exp; } else { nptr = (void *)(pwr_p10 + 5); } for (pwr = 32; pwr; pwr >>= 1) { for (; exp >= pwr; exp -= pwr) { union { unsigned long u32; float flt; } y; y.u32 = pgm_read_dword ((float *)nptr); x.flt *= y.flt; } nptr -= sizeof(float); } if (!isfinite(x.flt) || x.flt == 0) errno = ERANGE; } return x.flt; } #endif avr-libc-1.8.0.orig/libc/stdlib/qsort.c0000644000000000000000000001030311732702554014555 0ustar /*- * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include #include "sectionname.h" typedef int cmp_t(const void *, const void *); static char *med3(char *, char *, char *, cmp_t *); static void swapfunc(char *, char *, int); #define min(a, b) ((a) < (b) ? (a) : (b)) /* * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function". */ #define swapcode(TYPE, parmi, parmj, n) { \ int i = (n) / sizeof (TYPE); \ register TYPE *pi = (TYPE *) (parmi); \ register TYPE *pj = (TYPE *) (parmj); \ do { \ register TYPE t = *pi; \ *pi++ = *pj; \ *pj++ = t; \ } while (--i > 0); \ } ATTRIBUTE_CLIB_SECTION static void swapfunc(char *a, char *b, int n) { swapcode(char, a, b, n) } #define swap(a, b) swapfunc(a, b, es) #define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n) ATTRIBUTE_CLIB_SECTION static char * med3(char *a, char *b, char *c, cmp_t *cmp) { return cmp(a, b) < 0 ? (cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a )) :(cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c )); } ATTRIBUTE_CLIB_SECTION void qsort(void *a, size_t n, size_t es, cmp_t *cmp) { char *pa, *pb, *pc, *pd, *pl, *pm, *pn; int d, r, swap_cnt; loop: swap_cnt = 0; if (n < 7) { for (pm = (char *)a + es; pm < (char *)a + n * es; pm += es) for (pl = pm; pl > (char *)a && cmp(pl - es, pl) > 0; pl -= es) swap(pl, pl - es); return; } pm = (char *)a + (n / 2) * es; if (n > 7) { pl = a; pn = (char *)a + (n - 1) * es; if (n > 40) { d = (n / 8) * es; pl = med3(pl, pl + d, pl + 2 * d, cmp); pm = med3(pm - d, pm, pm + d, cmp); pn = med3(pn - 2 * d, pn - d, pn, cmp); } pm = med3(pl, pm, pn, cmp); } swap(a, pm); pa = pb = (char *)a + es; pc = pd = (char *)a + (n - 1) * es; for (;;) { while (pb <= pc && (r = cmp(pb, a)) <= 0) { if (r == 0) { swap_cnt = 1; swap(pa, pb); pa += es; } pb += es; } while (pb <= pc && (r = cmp(pc, a)) >= 0) { if (r == 0) { swap_cnt = 1; swap(pc, pd); pd -= es; } pc -= es; } if (pb > pc) break; swap(pb, pc); swap_cnt = 1; pb += es; pc -= es; } if (swap_cnt == 0) { /* Switch to insertion sort */ for (pm = (char *)a + es; pm < (char *)a + n * es; pm += es) for (pl = pm; pl > (char *)a && cmp(pl - es, pl) > 0; pl -= es) swap(pl, pl - es); return; } pn = (char *)a + n * es; r = min(pa - (char *)a, pb - pa); vecswap(a, pb - r, r); r = min(pd - pc, pn - pd - es); vecswap(pb, pn - r, r); if ((r = pb - pa) > es) qsort(a, r / es, es, cmp); if ((r = pd - pc) > es) { /* Iterate rather than recurse to save stack space */ a = pn - r; n = r / es; goto loop; } /* qsort(pn - r, r / es, es, cmp);*/ } avr-libc-1.8.0.orig/libc/stdlib/ctype.S0000644000000000000000000002124611732702554014521 0ustar ;; Copyright (c) 1999, 2000, 2001, 2002, 2005 Michael Stumpf ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; $Id: ctype.S 1944 2009-04-01 23:12:20Z arcanum $ #if !defined(__DOXYGEN__) #include "gasava.inc" #include "macros.inc" ;================================================================================ ; ctype.s ; ; Character handling - ctype.h ; ; Author : Michael Stumpf (c) 1999 ; Michael.Stumpf@t-online.de ; ; Versions : V0.1.0 ; ; adapted to avr-as ; Michael Rickmann, Feb. 2000 ; **changed**: changes to code ; ; int isalnum(int c) Letter or digit equality. ; int isalpha(int c) Letter equality. ; int iscntrl(int c) Control code equality. ; int isdigit(int c) Digit equality. ; int isgraph(int c) Printable non-space character equality. ; int islower(int c) Lower case equality. ; int isprint(int c) Printable character equality. ; int ispunct(int c) Punctuation character equality. ; int isspace(int c) White-space character equality. ; ; int isupper(int c) Upper case equality. ; int isxdigit(int c) Hex digit equality. ; int tolower(int c) Converts to lower case. ; int toupper(int c) Converts to upper case. ; int isblank(int c) Blank-space character test. ; ; realized as functions, not as macro with a 256 - byte large bit-table ; ; gives a total of 182 bytes code and short function calls ; ;================================================================================ #define rHigh rP0 #define rLow rP1 #if defined (Lisascii) ASSEMBLY_CLIB_SECTION FUNCTION(isascii) GLOBAL(isascii) CPSE rHigh,__zero_reg__ RJMP _U(__ctype_isfalse) COM rLow ANDI rLow, 0x80 RET ENDFUNC #endif #if defined (Ltoascii) ASSEMBLY_CLIB_SECTION FUNCTION(toascii) GLOBAL(toascii) CLR rHigh ANDI rLow, 0x7F RET ENDFUNC #endif #if defined (Lisalnum) ASSEMBLY_CLIB_SECTION FUNCTION(isalnum) GLOBAL(isalnum) cpse rHigh, __zero_reg__ rjmp _U(__ctype_isfalse) subi rLow, '0' subi rLow, '9'-'0'+1 brlo 2f ; rLow is digit, return negative val. subi rLow, lo8(-'9'-1) ; restore rLow rjmp _U(isalpha) 2: ret ENDFUNC #endif #if defined (Lcty_isfalse) ASSEMBLY_CLIB_SECTION FUNCTION(__ctype_isfalse) GLOBAL(__ctype_isfalse) CLR rHigh CLR rLow GLOBAL(__ctype_istrue) RET ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Lisalpha) ASSEMBLY_CLIB_SECTION FUNCTION(isupper) GLOBAL(isupper) ;CPSE rHigh,__zero_reg__ ;RJMP _U(__ctype_isfalse) ; checked by _islower later on SBRC rLow,5 ; if bit 5 is set it is no upper RJMP _U(__ctype_isfalse) ; bit 5 is clear, so if isalpha is true it is an upper GLOBAL(isalpha) ORI rLow,0x20 ; make a lower out of an upper (all others are changed but do not get alpha) GLOBAL(islower) CPSE rHigh,__zero_reg__ 1: RJMP _U(__ctype_isfalse) SUBI rLow, 'a' SUBI rLow, 'z'-'a'+1 BRSH 1b RET ; TRUE: rLow is in -26..-1 ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Lisdigit) ASSEMBLY_CLIB_SECTION FUNCTION(isdigit) GLOBAL(isdigit) CPSE rHigh,__zero_reg__ 1: RJMP _U(__ctype_isfalse) SUBI rLow,'0' SUBI rLow,10 BRSH 1b RET ; rLow: -10..-1 ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Lisxdigit) ASSEMBLY_CLIB_SECTION FUNCTION(isxdigit) ; This fact is used below. .if 'a' - 'A' - 0x20 .err .endif GLOBAL(isxdigit) cpse rHigh, __zero_reg__ 1: rjmp _U(__ctype_isfalse) subi rLow, '0' subi rLow, '9'-'0'+1 brlo 2f ; decimal digit subi rLow, lo8(-'9'-1) ; restore rLow ori rLow, 'a' - 'A' ; rLow := tolower(rLow) subi rLow, 'a' subi rLow, 'f'-'a'+1 brsh 1b 2: ret ; OK: return a negative value ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Liscntrl) ASSEMBLY_CLIB_SECTION FUNCTION(iscntrl) GLOBAL(iscntrl) CPSE rHigh,__zero_reg__ 1: RJMP _U(__ctype_isfalse) CPI rLow,0x7F BREQ 2f SUBI rLow, ' ' BRSH 1b ; iscntrl('\0') --> true 2: RET ; TRUE: rLow is 0x7F or negative value ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Lisprint) ASSEMBLY_CLIB_SECTION FUNCTION(isgraph) GLOBAL(isgraph) CPI rLow,' ' BREQ 1f GLOBAL(isprint) CPSE rHigh, __zero_reg__ 1: RJMP _U(__ctype_isfalse) SUBI rLow, ' ' SUBI rLow, 0x7E - ' ' + 1 BRSH 1b RET ; TRUE: rlow is negative value ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Lisspace) ASSEMBLY_CLIB_SECTION FUNCTION(isspace) /* This fact is used below. */ .if ('\t'-9) | ('\n'-10) | ('\f'-12) | ('\r'-13) ; '\v' is 11 .err .endif GLOBAL(isspace) CPSE rHigh,__zero_reg__ 1: RJMP _U(__ctype_isfalse) CPI rLow,' ' ; blank BREQ 2f SUBI rLow, '\t' SUBI rLow, '\r'-'\t'+1 BRSH 1b 2: RET ; TRUE result: rLow is -5..-1 or ' ' ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Lispunct) ASSEMBLY_CLIB_SECTION FUNCTION(ispunct) GLOBAL(ispunct) cpse rHigh, __zero_reg__ 1: rjmp _U(__ctype_isfalse) subi rLow, ' ' + 1 subi rLow, 0x7e - ' ' brsh 1b ; if (!isgraph(c)) return 0 subi rLow, lo8(-0x7e - 1) ; restore rLow rcall _U(isalnum) tst rLow brne 1b ; if (isalnum(c)) return 0 ldi rLow, 1 ret ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Lisblank) ASSEMBLY_CLIB_SECTION FUNCTION(isblank) GLOBAL(isblank) CPSE rHigh,__zero_reg__ 1: RJMP _U(__ctype_isfalse) CPI rLow,' ' ; blank BREQ 2f CPI rLow,0x09 ;'\t' ; tab BRNE 1b 2: RET ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Ltolower) ASSEMBLY_CLIB_SECTION FUNCTION(tolower) GLOBAL(tolower) cpse rHigh, __zero_reg__ ret ; return as is subi rLow, 'A' subi rLow, 'Z'-'A'+1 brsh 1f ; return as is subi rLow, lo8('A'-'a') ; conversion 1: subi rLow, lo8(-'Z'-1) ; restore ret ENDFUNC #endif ;------------------------------------------------------------------- #if defined (Ltoupper) ASSEMBLY_CLIB_SECTION FUNCTION(toupper) GLOBAL(toupper) cpse rHigh, __zero_reg__ ret ; return as is subi rLow, 'a' subi rLow, 'z'-'a'+1 brsh 1f ; return as is subi rLow, lo8('a'-'A') ; conversion 1: subi rLow, lo8(-'z'-1) ; restore ret ENDFUNC #endif #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/stdlib/atol.S0000644000000000000000000001021611732702554014327 0ustar /* Copyright (c) 2002, 2007 Reiner Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: atol.S 1944 2009-04-01 23:12:20Z arcanum $ */ /* atol.S Contributors: Created by Reiner Patommel Modified by Reiner Patommel 8 Feb 2003, Bug #2481 Modified by Reiner Patommel 13 May 2003, (DOXYGEN) TODO: this implementation uses an inline isspace(). If Avr-libc will use locales other than C/POSIX it is needed to call an external isspace(). ATTENTION: an external __mulsi_const_10() function is used: nonstandart call conventions: some registers and bit T must be nochanged. */ /** \file */ /** \ingroup avr_stdlib \fn long atol(const char *s) \brief Convert a string to a long integer. The atol() function converts the initial portion of the string pointed to by \p s to long integer representation. In contrast to \code strtol(s, (char **)NULL, 10); \endcode this function does not detect overflow (\c errno is not changed and the result value is not predictable), uses smaller memory (flash and stack) and works more quickly. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define str_hi r25 #define str_lo r24 #define num_hi_hi r25 #define num_hi_lo r24 #define num_lo_hi r23 #define num_lo_lo r22 #define tmp r17 ASSEMBLY_CLIB_SECTION .global _U(atol) .type _U(atol), @function /* Skip leading spaces and tabs. Process optional sign. Stop conversion on detection of a non-numeric character. Return 0 if string contains no numeric characters. */ /* This fact is used below. */ .if ('\t'-9) | ('\n'-10) | ('\f'-12) | ('\r'-13) ; '\v' is 11 .err .endif _U(atol): PUSH tmp X_movw ZL, str_lo ; set pointer to string CLR num_hi_hi CLR num_hi_lo X_movw num_lo_lo, num_hi_lo ; clear number CLT ; clear sign .L_atol_loop: LD tmp, Z+ ; get (next) character CPI tmp, ' ' ; skip whitespace BREQ .L_atol_loop CPI tmp, '\t' BRLO 1f CPI tmp, '\r'+1 BRLO .L_atol_loop 1: CPI tmp, '+' ; if '+' go on BREQ .L_atol_loop2 CPI tmp, '-' ; if '-' remember sign BRNE .L_atol_digit SET ; remember number is negative RJMP .L_atol_loop2 2: XCALL __mulsi_const_10 ; r25:r24:r23:r22 *= 10 ADD num_lo_lo, tmp ; num = (num * 10) + (tmp - '0') ADC num_lo_hi, __zero_reg__ ADC num_hi_lo, __zero_reg__ ADC num_hi_hi, __zero_reg__ .L_atol_loop2: LD tmp, Z+ .L_atol_digit: SUBI tmp, '0' ; make figure a number CPI tmp, 10 BRLO 2b BRTC .L_atol_done ; positive number? -> return COM num_hi_hi COM num_hi_lo COM num_lo_hi NEG num_lo_lo SBCI num_lo_hi, 0xff SBCI num_hi_lo, 0xff SBCI num_hi_hi, 0xff ; make number negative .L_atol_done: POP tmp RET .L_atol_end: .size _U(atol), .L_atol_end - _U(atol) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/stdlib/ldiv.S0000644000000000000000000000324211732702554014327 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* ldiv() is the same as __divmodsi4() in libgcc */ #include "macros.inc" ASSEMBLY_CLIB_SECTION .global ldiv ldiv: XJMP __divmodsi4 avr-libc-1.8.0.orig/libc/stdlib/isalnum.S0000644000000000000000000000321011732702554015034 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: isalnum.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lisalnum 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/abs.c0000644000000000000000000000321011732702554014151 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int abs(int x) { return (x < 0) ? -x : x; } avr-libc-1.8.0.orig/libc/stdlib/iscntrl.S0000644000000000000000000000321011732702554015042 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: iscntrl.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Liscntrl 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/abort.S0000644000000000000000000000350011732702554014475 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: abort.S 1944 2009-04-01 23:12:20Z arcanum $ */ #ifndef __DOXYGEN__ #include "macros.inc" ASSEMBLY_CLIB_SECTION .global _U(abort) .type _U(abort), "function" _U(abort): ldi r24, lo8(1) ldi r25, hi8(1) cli XJMP _U(_exit) .size _U(abort), . - _U(abort) #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/stdlib/cty_isfalse.S0000644000000000000000000000322011732702554015672 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: cty_isfalse.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lcty_isfalse 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/rand.c0000644000000000000000000000573111732702554014342 0ustar /*- * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * Posix rand_r function added May 1999 by Wes Peters . * * $Id: rand.c 1944 2009-04-01 23:12:20Z arcanum $ */ /* * From: static char sccsid[] = "@(#)rand.c 8.1 (Berkeley) 6/14/93"; */ #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION static int do_rand(unsigned long *ctx) { #ifdef USE_WEAK_SEEDING /* * Historic implementation compatibility. * The random sequences do not vary much with the seed, * even with overflowing. */ return ((*ctx = *ctx * 1103515245L + 12345L) % ((unsigned long)RAND_MAX + 1)); #else /* !USE_WEAK_SEEDING */ /* * Compute x = (7^5 * x) mod (2^31 - 1) * wihout overflowing 31 bits: * (2^31 - 1) = 127773 * (7^5) + 2836 * From "Random number generators: good ones are hard to find", * Park and Miller, Communications of the ACM, vol. 31, no. 10, * October 1988, p. 1195. */ long hi, lo, x; x = *ctx; /* Can't be initialized with 0, so use another value. */ if (x == 0) x = 123459876L; hi = x / 127773L; lo = x % 127773L; x = 16807L * lo - 2836L * hi; if (x < 0) x += 0x7fffffffL; return ((*ctx = x) % ((unsigned long)RAND_MAX + 1)); #endif /* !USE_WEAK_SEEDING */ } ATTRIBUTE_CLIB_SECTION int rand_r(unsigned long *ctx) { return do_rand(ctx); } static unsigned long next = 1; ATTRIBUTE_CLIB_SECTION int rand(void) { return do_rand(&next); } ATTRIBUTE_CLIB_SECTION void srand(unsigned int seed) { next = seed; } avr-libc-1.8.0.orig/libc/stdlib/Makefile.in0000644000000000000000000003240511732702554015315 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) 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be exceeded. .NOEXPORT: avr-libc-1.8.0.orig/libc/stdlib/labs.c0000644000000000000000000000321311732702554014330 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION long labs(long x) { return (x < 0) ? -x : x; } avr-libc-1.8.0.orig/libc/stdlib/ftoa_engine.S0000644000000000000000000002764711732702554015666 0ustar /* Copyright (c) 2005, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ftoa_engine.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) #ifndef __DOXYGEN__ #include "macros.inc" #include "ftoa_engine.h" #if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ # define AVR_ENH_LPM 1 #else # define AVR_ENH_LPM 0 #endif /* int __ftoa_engine (double val, char *buf, unsigned char prec, unsigned char maxdgs) Input: val - value to convert buf - output buffer address prec - precision: number of decimal digits is 'prec + 1' maxdgs - (0 if unused) precision restriction for "%f" specification Output: return - decimal exponent of first digit buf[0] - flags (FTOA_***) buf[1],... - decimal digits Number of digits: maxdgs == 0 ? prec+1 : (buf[0] & FTOA_CARRY) == 0 || buf[1] != '1' ? aver(1, maxdgs+exp, prec+1) : aver(1, masdgs+exp-1, prec+1) Notes: * Output string is not 0-terminated. For possibility of user's buffer usage in any case. * If used, 'maxdgs' is a number of digits for value with zero exponent. */ /* Input */ #define maxdgs r16 #define prec r18 #define buf_lo r20 #define buf_hi r21 #define val_lo r22 #define val_hi r23 #define val_hlo r24 #define val_hhi r25 /* Float value parse */ #define flag r19 /* Multiplication of mantisses */ #define exp_sv r17 #define mlt_1 r19 /* lowest result byte */ #define mlt_2 r14 #define mlt_3 r15 #define mlt_4 r20 #define mlt_5 r21 #define mlt_6 r28 #define mlt_7 r29 /* Conversion to string */ #define pwr_2 r1 /* lowest byte of 'powr10' element */ #define pwr_3 r17 #define pwr_4 r19 #define pwr_5 r22 #define pwr_6 r25 #define pwr_7 r0 #define digit r23 #define exp10 r24 /* Fixed */ #define zero r1 ASSEMBLY_CLIB_SECTION .global __ftoa_engine .type __ftoa_engine, "function" __ftoa_engine: /* -------------------------------------------------------------------- Float value parse. */ ; limit 'prec' cpi prec, 8 brlo 1f ldi prec, 7 1: ; init. clr flag X_movw XL, buf_lo ; val_hhi := exponent, sign test and remove #if FTOA_MINUS != 1 # error FTOA_MINUS must be 1: add with carry used #endif lsl val_hhi adc flag, zero ; FTOA_MINUS sbrc val_hlo, 7 ori val_hhi, 1 ; zero test adiw val_hlo, 0 cpc val_lo, zero cpc val_hi, zero brne 3f ; return 0 ori flag, FTOA_ZERO subi prec, -2 2: st X+, flag ldi flag, '0' dec prec brne 2b ret ; r24,r25 == 0 3: ; infinity, NaN ? #if FTOA_NAN != 2 * FTOA_INF # error Must: FTOA_NAN == 2*FTOA_INF: 'rjmp' is absent #endif cpi val_hhi, 0xff brlo 6f cpi val_hlo, 0x80 cpc val_hi, zero cpc val_lo, zero breq 5f subi flag, -FTOA_INF ; FTOA_NAN 5: subi flag, -FTOA_INF 6: ; write flags byte st X+, flag ; hidden bit cpi val_hhi, 1 brlo 7f ; if subnormal value ori val_hlo, 0x80 7: adc val_hhi, zero ; pushes push r29 push r28 push r17 push r16 push r15 push r14 /* -------------------------------------------------------------------- Multiplication of mantisses (val and table). At the begin: val_hlo .. val_lo - input value mantisse val_hhi - input value exponent X - second byte address (string begin) At the end: mlt_7 .. mlt_2 - multiplication result exp10 - decimal exponent */ ; save mov exp_sv, val_hhi ; Z := & base10[exp / 8] (sizeof(base10[0]) == 5) andi val_hhi, ~7 lsr val_hhi ; (exp/8) * 4 mov ZL, val_hhi lsr val_hhi lsr val_hhi ; exp/8 add ZL, val_hhi ; (exp/8) * 5 clr ZH subi ZL, lo8(-(.L_base10)) sbci ZH, hi8(-(.L_base10)) ; highest mantissa byte (mult. shifting prepare) clr val_hhi ; result initializ. clr mlt_1 clr mlt_2 clr mlt_3 X_movw mlt_4, mlt_2 X_movw mlt_6, mlt_2 ; multiply to 1-st table byte #if AVR_ENH_LPM lpm r0, Z+ #else lpm adiw ZL, 1 #endif sec ; for loop end control ror r0 ; addition 10: brcc 11f add mlt_1, val_lo adc mlt_2, val_hi adc mlt_3, val_hlo adc mlt_4, val_hhi adc mlt_5, zero ; arg shift 11: lsl val_lo rol val_hi rol val_hlo rol val_hhi ; next bit lsr r0 brne 10b ; second table byte #if AVR_ENH_LPM lpm r0, Z+ ; C flag is stay 1 #else lpm adiw ZL, 1 sec #endif ror r0 ; addition 12: brcc 13f add mlt_2, val_hi ; val_hi is the least byte now adc mlt_3, val_hlo adc mlt_4, val_hhi adc mlt_5, val_lo adc mlt_6, zero ; arg shift 13: lsl val_hi rol val_hlo rol val_hhi rol val_lo ; next bit lsr r0 brne 12b ; 3-t table byte #if AVR_ENH_LPM lpm r0, Z+ ; C flag is stay 1 #else lpm adiw ZL, 1 sec #endif ror r0 ; addition 14: brcc 15f add mlt_3, val_hlo ; val_hlo is the least byte now adc mlt_4, val_hhi adc mlt_5, val_lo adc mlt_6, val_hi adc mlt_7, zero ; arg shift 15: lsl val_hlo rol val_hhi rol val_lo rol val_hi ; next bit lsr r0 brne 14b ; 4-t table byte #if AVR_ENH_LPM lpm r0, Z+ ; C flag is stay 1 #else lpm #endif ror r0 ; addition 16: brcc 17f add mlt_4, val_hhi ; val_hhi is the least byte now adc mlt_5, val_lo adc mlt_6, val_hi adc mlt_7, val_hlo ; arg shift 17: lsl val_hhi rol val_lo rol val_hi rol val_hlo ; next bit lsr r0 brne 16b ; decimal exponent #if AVR_ENH_LPM lpm exp10, Z #else adiw ZL, 1 lpm mov exp10, r0 #endif ; result shift: mlt_7..2 >>= (~exp & 7) com exp_sv andi exp_sv, 7 breq 19f 18: lsr mlt_7 ror mlt_6 ror mlt_5 ror mlt_4 ror mlt_3 ror mlt_2 dec exp_sv brne 18b 19: /* -------------------------------------------------------------------- Conversion to string. Registers usage: mlt_7 .. mlt_2 - new mantissa (multiplication result) pwr_7 .. pwr_2 - 'powr10' table element Z - 'powr10' table pointer X - output string pointer maxdgs - number of digits prec - number of digits stays to output exp10 - decimal exponent digit - conversion process At the end: X - end of buffer (nonfilled byte) exp10 - corrected dec. exponent mlt_7 .. mlt_2 - remainder pwr_7 .. pwr_2 - last powr10[] element Notes: * It is possible to leave out powr10'x table with subnormal value. Result: accuracy degrease on the rounding phase. No matter: high precision with subnormals is not needed. (Now 0x00000001 is converted exactly on prec = 5, i.e. 6 digits.) */ ; to find first digit ldi ZL, lo8(.L_powr10) ldi ZH, hi8(.L_powr10) set ; 'pwr10' element reading .L_digit: X_lpm pwr_2, Z+ X_lpm pwr_3, Z+ X_lpm pwr_4, Z+ X_lpm pwr_5, Z+ X_lpm pwr_6, Z+ X_lpm pwr_7, Z+ ; 'digit' init. ldi digit, '0' - 1 ; subtraction loop 20: inc digit sub mlt_2, pwr_2 sbc mlt_3, pwr_3 sbc mlt_4, pwr_4 sbc mlt_5, pwr_5 sbc mlt_6, pwr_6 sbc mlt_7, pwr_7 brsh 20b ; restore mult add mlt_2, pwr_2 adc mlt_3, pwr_3 adc mlt_4, pwr_4 adc mlt_5, pwr_5 adc mlt_6, pwr_6 adc mlt_7, pwr_7 ; analisys brtc 25f cpi digit, '0' brne 21f ; this is the first digit finded dec exp10 rjmp .L_digit ; now is the first digit 21: clt ; number of digits subi maxdgs, 1 brlo 23f ; maxdgs was 0 add maxdgs, exp10 brpl 22f clr maxdgs 22: cp maxdgs, prec brsh 23f mov prec, maxdgs 23: inc prec mov maxdgs, prec ; operate digit 25: cpi digit, '0' + 10 brlo 27f ; overflow, digit > '9' ldi digit, '9' 26: st X+, digit dec prec brne 26b rjmp .L_up ; write digit 27: st X+, digit dec prec brne .L_digit /* -------------------------------------------------------------------- Rounding. */ .L_round: ; pwr10 /= 2 lsr pwr_7 ror pwr_6 ror pwr_5 ror pwr_4 ror pwr_3 ror pwr_2 ; mult -= pwr10 (half of last 'pwr10' value) sub mlt_2, pwr_2 sbc mlt_3, pwr_3 sbc mlt_4, pwr_4 sbc mlt_5, pwr_5 sbc mlt_6, pwr_6 sbc mlt_7, pwr_7 ; rounding direction? brlo .L_rest ; round to up .L_up: inc prec ld digit, -X inc digit cpi digit, '9' + 1 brlo 31f ldi digit, '0' 31: st X, digit cpse prec, maxdgs brsh .L_up ; it was a carry to master digit ld digit, -X ; flags ori digit, FTOA_CARRY ; 'C' is not changed st X+, digit brlo .L_rest ; above comparison ; overflow inc exp10 ldi digit, '1' 32: st X+, digit ldi digit, '0' dec prec brne 32b ; restore .L_rest: clr zero pop r14 pop r15 pop r16 pop r17 pop r28 pop r29 ; return clr r25 sbrc exp10, 7 ; high byte com r25 ret .size __ftoa_engine, . - __ftoa_engine /* -------------------------------------------------------------------- Tables. '.L_powr10' is placed first -- for subnormals stability. */ .section .progmem.data,"a",@progbits .type .L_powr10, "object" .L_powr10: .byte 0, 64, 122, 16, 243, 90 ; 100000000000000 .byte 0, 160, 114, 78, 24, 9 ; 10000000000000 .byte 0, 16, 165, 212, 232, 0 ; 1000000000000 .byte 0, 232, 118, 72, 23, 0 ; 100000000000 .byte 0, 228, 11, 84, 2, 0 ; 10000000000 .byte 0, 202, 154, 59, 0, 0 ; 1000000000 .byte 0, 225, 245, 5, 0, 0 ; 100000000 .byte 128, 150, 152, 0, 0, 0 ; 10000000 .byte 64, 66, 15, 0, 0, 0 ; 1000000 .byte 160, 134, 1, 0, 0, 0 ; 100000 .byte 16, 39, 0, 0, 0, 0 ; 10000 .byte 232, 3, 0, 0, 0, 0 ; 1000 .byte 100, 0, 0, 0, 0, 0 ; 100 .byte 10, 0, 0, 0, 0, 0 ; 10 .byte 1, 0, 0, 0, 0, 0 ; 1 .size .L_powr10, . - .L_powr10 .type .L_base10, "object" .L_base10: .byte 44, 118, 216, 136, -36 ; 2295887404 .byte 103, 79, 8, 35, -33 ; 587747175 .byte 193, 223, 174, 89, -31 ; 1504632769 .byte 177, 183, 150, 229, -29 ; 3851859889 .byte 228, 83, 198, 58, -26 ; 986076132 .byte 81, 153, 118, 150, -24 ; 2524354897 .byte 230, 194, 132, 38, -21 ; 646234854 .byte 137, 140, 155, 98, -19 ; 1654361225 .byte 64, 124, 111, 252, -17 ; 4235164736 .byte 188, 156, 159, 64, -14 ; 1084202172 .byte 186, 165, 111, 165, -12 ; 2775557562 .byte 144, 5, 90, 42, -9 ; 710542736 .byte 92, 147, 107, 108, -7 ; 1818989404 .byte 103, 109, 193, 27, -4 ; 465661287 .byte 224, 228, 13, 71, -2 ; 1192092896 .byte 245, 32, 230, 181, 0 ; 3051757813 .byte 208, 237, 144, 46, 3 ; 781250000 .byte 0, 148, 53, 119, 5 ; 2000000000 .byte 0, 128, 132, 30, 8 ; 512000000 .byte 0, 0, 32, 78, 10 ; 1310720000 .byte 0, 0, 0, 200, 12 ; 3355443200 .byte 51, 51, 51, 51, 15 ; 858993459 .byte 152, 110, 18, 131, 17 ; 2199023256 .byte 65, 239, 141, 33, 20 ; 562949953 .byte 137, 59, 230, 85, 22 ; 1441151881 .byte 207, 254, 230, 219, 24 ; 3689348815 .byte 209, 132, 75, 56, 27 ; 944473297 .byte 247, 124, 29, 144, 29 ; 2417851639 .byte 164, 187, 228, 36, 32 ; 618970020 .byte 50, 132, 114, 94, 34 ; 1584563250 .byte 129, 0, 201, 241, 36 ; 4056481921 .byte 236, 161, 229, 61, 39 ; 1038459372 .size .L_base10, . - .L_base10 .end #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/stdlib/dtostre.c0000644000000000000000000000627311732702554015104 0ustar /* Copyright (c) 2005, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: dtostre.c 2241 2011-05-11 12:59:48Z joerg_wunsch $ */ #include #include #include "ftoa_engine.h" #include "sectionname.h" ATTRIBUTE_CLIB_SECTION char * dtostre (double val, char *sbeg, unsigned char prec, unsigned char flags) { __attribute__((progmem)) static const char str_nan[2][4] = {"nan", "NAN"}; __attribute__((progmem)) static const char str_inf[2][sizeof(str_nan[0])] = {"inf", "INF"}; char *d; /* dst */ const char *s; /* src */ signed char exp; unsigned char vtype; if (prec > 7) prec = 7; exp = __ftoa_engine (val, sbeg, prec, 0); d = s = sbeg; vtype = *s++; if ((vtype & FTOA_MINUS) && !(vtype & FTOA_NAN)) /* like 'Glibc' */ *d++ = '-'; else if (flags & DTOSTR_PLUS_SIGN) *d++ = '+'; else if (flags & DTOSTR_ALWAYS_SIGN) *d++ = ' '; if (vtype & FTOA_NAN) { s = str_nan[0]; goto copy; } if (vtype & FTOA_INF) { s = str_inf[0]; copy: if (flags & DTOSTR_UPPERCASE) s += sizeof(str_nan[0]); strcpy_P (d, s); goto ret; } /* mantissa */ if ( (*d++ = *s++) != '1') vtype &= ~FTOA_CARRY; /* for possible exponent "-00" */ if (prec) { unsigned char c1, c2; c1 = '.'; do { c2 = *s++; *d++ = c1; c1 = c2; } while (--prec); *d++ = c1; } /* exponent */ *d++ = (flags & DTOSTR_UPPERCASE) ? 'E' : 'e'; if (exp < 0) { *d++ = '-'; exp = -exp; } else if (exp == 0 && (vtype & FTOA_CARRY) != 0) { *d++ = '-'; } else { *d++ = '+'; } for (prec = '0'; exp >= 10; exp -= 10) prec += 1; *d++ = prec; *d++ = '0' + exp; *d = 0; ret: return sbeg; } /*** end of file ***/ avr-libc-1.8.0.orig/libc/stdlib/errno.c0000644000000000000000000000306511732702554014541 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include int errno; avr-libc-1.8.0.orig/libc/stdlib/Files.am0000644000000000000000000000432711732702554014633 0ustar # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # stdlib_a_c_sources = \ abs.c \ assert.c \ bsearch.c \ calloc.c \ errno.c \ dtoa_prf.c \ dtostre.c \ dtostrf.c \ labs.c \ malloc.c \ qsort.c \ rand.c \ random.c \ realloc.c \ strtod.c \ strtol.c \ strtoul.c \ dtoa_conv.h \ stdlib_private.h stdlib_a_asm_sources = \ abort.S \ atof.S \ atoi.S \ atol.S \ div.S \ exit.S \ ftoa_engine.S \ ldiv.S \ setjmp.S \ isascii.S \ toascii.S \ isalnum.S \ cty_isfalse.S \ isalpha.S \ isdigit.S \ isxdigit.S \ iscntrl.S \ isprint.S \ isspace.S \ isblank.S \ ispunct.S \ tolower.S \ toupper.S stdlib_a_extra_dist = \ ctype.S \ abort.c \ atoi.c \ atol.c # vim: set ft=make: avr-libc-1.8.0.orig/libc/stdlib/strtoul.c0000644000000000000000000001007011732702554015122 0ustar /* * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * Copyright (c) 2005, Dmitry Xmelkov * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $Id: strtoul.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include #include "sectionname.h" /* * Convert a string to an unsigned long integer. * * Ignores `locale' stuff. Assumes that the upper and lower case * alphabets and digits are each contiguous. */ ATTRIBUTE_CLIB_SECTION unsigned long strtoul(const char *nptr, char **endptr, register int base) { register unsigned long acc; register unsigned char c; register unsigned long cutoff; register signed char any; unsigned char flag = 0; #define FL_NEG 0x01 /* number is negative */ #define FL_0X 0x02 /* number has a 0x prefix */ if (endptr) *endptr = (char *)nptr; if (base != 0 && (base < 2 || base > 36)) return 0; /* * See strtol for comments as to the logic used. */ do { c = *nptr++; } while (isspace(c)); if (c == '-') { flag = FL_NEG; c = *nptr++; } else if (c == '+') c = *nptr++; if ((base == 0 || base == 16) && c == '0' && (*nptr == 'x' || *nptr == 'X')) { c = nptr[1]; nptr += 2; base = 16; flag |= FL_0X; } if (base == 0) base = c == '0' ? 8 : 10; /* * cutoff computation is similar to strtol(). * * Description of the overflow detection logic used. * * First, let us assume an overflow. * * Result of `acc_old * base + c' is cut to 32 bits: * acc_new <-- acc_old * base + c - 0x100000000 * * `acc_old * base' is <= 0xffffffff (cutoff control) * * then: acc_new <= 0xffffffff + c - 0x100000000 * * or: acc_new <= c - 1 * * or: acc_new < c * * Second: * if (no overflow) then acc * base + c >= c * (or: acc_new >= c) * is clear (alls are unsigned). * */ switch (base) { case 16: cutoff = ULONG_MAX / 16; break; case 10: cutoff = ULONG_MAX / 10; break; case 8: cutoff = ULONG_MAX / 8; break; default: cutoff = ULONG_MAX / base; } for (acc = 0, any = 0;; c = *nptr++) { if (c >= '0' && c <= '9') c -= '0'; else if (c >= 'A' && c <= 'Z') c -= 'A' - 10; else if (c >= 'a' && c <= 'z') c -= 'a' - 10; else break; if (c >= base) break; if (any < 0) continue; if (acc > cutoff) { any = -1; continue; } acc = acc * base + c; any = (c > acc) ? -1 : 1; } if (endptr) { if (any) *endptr = (char *)nptr - 1; else if (flag & FL_0X) *endptr = (char *)nptr - 2; } if (flag & FL_NEG) acc = -acc; if (any < 0) { acc = ULONG_MAX; errno = ERANGE; } return (acc); } avr-libc-1.8.0.orig/libc/stdlib/calloc.c0000644000000000000000000000346011732702554014650 0ustar /* Copyright (c) 2002 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: calloc.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION void * calloc(size_t nele, size_t size) { void *p; if ((p = malloc(nele * size)) == 0) return 0; memset(p, 0, nele * size); return p; } avr-libc-1.8.0.orig/libc/stdlib/atoi.S0000644000000000000000000001004311732702554014322 0ustar /* Copyright (c) 2002, 2007 Reiner Patommel All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: atoi.S 1944 2009-04-01 23:12:20Z arcanum $ */ /* Contributors: Created by Reiner Patommel Changes: Jochen Pernsteiner, Marek Michalkiewicz Changes: Reiner Patommel, 8 Feb 2003 Changes: Reiner Patommel, 13 May 2003 (DOXYGEN) TODO: this implementation uses an inline isspace(). If Avr-libc will use locales other than C/POSIX it is needed to call an external isspace(). ATTENTION: an external __mulhi_const_10() function is used: nonstandart call conventions: some registers and bit T must be nochanged. */ /** \file */ /** \ingroup avr_stdlib \fn int atoi(const char *s) \brief Convert a string to an integer. The atoi() function converts the initial portion of the string pointed to by \p s to integer representation. In contrast to \code (int)strtol(s, (char **)NULL, 10); \endcode this function does not detect overflow (\c errno is not changed and the result value is not predictable), uses smaller memory (flash and stack) and works more quickly. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define str_hi r25 #define str_lo r24 #define num_hi r25 #define num_lo r24 #define tmp r18 ASSEMBLY_CLIB_SECTION .global _U(atoi) .type _U(atoi), @function /* Skip leading spaces and tabs. Process optional sign. Stop conversion on detection of a non-numeric character. Return 0 if string contains no numeric characters. No check is performed whether the value is within the range of an 'int' i.e. 32768 becomes -32768. */ /* This fact is used below. */ .if ('\t'-9) | ('\n'-10) | ('\f'-12) | ('\r'-13) ; '\v' is 11 .err .endif _U(atoi): X_movw ZL, str_lo ; set pointer to string CLR num_lo CLR num_hi ; clear number CLT ; clear sign flag .L_atoi_loop: LD tmp, Z+ ; get (next) character CPI tmp, ' ' ; skip whitespace BREQ .L_atoi_loop CPI tmp, '\t' ; ASCII sequence is: \t,\n,\v,\f,\r BRLO 1f CPI tmp, '\r'+1 BRLO .L_atoi_loop 1: CPI tmp, '+' ; if '+' convert BREQ .L_atoi_loop2 CPI tmp, '-' ; if '-' remember sign BRNE .L_atoi_digit SET ; remember number is negative RJMP .L_atoi_loop2 2: XCALL __mulhi_const_10 ; r25:r24 *= 10 ADD num_lo, tmp ; num = (num * 10) + (tmp - '0') ADC num_hi, __zero_reg__ .L_atoi_loop2: LD tmp, Z+ .L_atoi_digit: SUBI tmp, '0' CPI tmp, 10 BRLO 2b BRTC .L_atoi_done ; positive number? -> return COM num_hi NEG num_lo SBCI num_hi, -1 ; make number negative .L_atoi_done: RET .L_atoi_end: .size _U(atoi), .L_atoi_end - _U(atoi) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/stdlib/ispunct.S0000644000000000000000000000321011732702554015051 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: ispunct.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lispunct 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/assert.c0000644000000000000000000000452411732702554014716 0ustar /*- * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* $Id: assert.c 1944 2009-04-01 23:12:20Z arcanum $ */ #if defined(LIBC_SCCS) && !defined(lint) static char sccsid[] = "@(#)assert.c 8.1 (Berkeley) 6/4/93"; #endif /* LIBC_SCCS and not lint */ /* taken from: __FBSDID("$FreeBSD: src/lib/libc/gen/assert.c,v 1.7 2002/02/01 00:57:29 obrien Exp $"); */ #include #include #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION void __assert (const char *func, const char *file, int line, const char *failedexpr) { if (func == NULL) (void)fprintf(stderr, "Assertion failed: (%s), file %s, line %d.\n", failedexpr, file, line); else (void)fprintf(stderr, "Assertion failed: (%s), function %s, file %s, line %d.\n", failedexpr, func, file, line); abort(); /* NOTREACHED */ } avr-libc-1.8.0.orig/libc/stdlib/dtoa_conv.h0000644000000000000000000000512711732702554015376 0ustar /* Copyright (c) 2005, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: dtoa_conv.h 1175 2007-01-14 15:18:18Z dmix $ */ #ifndef _DTOA_CONV_H #define _DTOA_CONV_H #include int dtoa_prf (double val, char *s, unsigned char width, unsigned char prec, unsigned char flags); int dtoa_lim (double val, char *s, unsigned char width, unsigned char prec, unsigned char flags); int dtoa_cln (double val, char *s, unsigned char ndigs, unsigned char flags); void d2stream (double val, FILE *stream, unsigned char width, unsigned char prec, unsigned char flags); #define DTOA_SPACE 0x01 /* put space for positives */ #define DTOA_PLUS 0x02 /* put '+' for positives */ #define DTOA_UPPER 0x04 /* use uppercase letters */ #define DTOA_ZFILL 0x08 /* fill zeroes */ #define DTOA_LEFT 0x10 /* adjust to left */ #define DTOA_NOFILL 0x20 /* do not fill to width */ #define DTOA_EXP 0x40 /* d2stream: 'e(E)' format */ #define DTOA_FIX 0x80 /* d2stream: 'f(F)' format */ #define DTOA_EWIDTH (-1) /* Width too small */ #define DTOA_NONFINITE (-2) /* Value is NaN or Inf */ #endif /* !_DTOA_CONV_H */ avr-libc-1.8.0.orig/libc/stdlib/Rules.am0000644000000000000000000000323711732702554014662 0ustar # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ include $(top_srcdir)/libc/stdlib/Files.am # vim: set ft=make: avr-libc-1.8.0.orig/libc/stdlib/random.c0000644000000000000000000000527211732702554014676 0ustar /*- * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * Posix rand_r function added May 1999 by Wes Peters . * * $Id: random.c 1944 2009-04-01 23:12:20Z arcanum $ */ /* * From: static char sccsid[] = "@(#)rand.c 8.1 (Berkeley) 6/14/93"; */ #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION static long do_random(unsigned long *ctx) { /* * Compute x = (7^5 * x) mod (2^31 - 1) * wihout overflowing 31 bits: * (2^31 - 1) = 127773 * (7^5) + 2836 * From "Random number generators: good ones are hard to find", * Park and Miller, Communications of the ACM, vol. 31, no. 10, * October 1988, p. 1195. */ long hi, lo, x; x = *ctx; /* Can't be initialized with 0, so use another value. */ if (x == 0) x = 123459876L; hi = x / 127773L; lo = x % 127773L; x = 16807L * lo - 2836L * hi; if (x < 0) x += 0x7fffffffL; return ((*ctx = x) % ((unsigned long)RANDOM_MAX + 1)); } ATTRIBUTE_CLIB_SECTION long random_r(unsigned long *ctx) { return do_random(ctx); } static unsigned long next = 1; ATTRIBUTE_CLIB_SECTION long random(void) { return do_random(&next); } ATTRIBUTE_CLIB_SECTION void srandom(unsigned long seed) { next = seed; } avr-libc-1.8.0.orig/libc/stdlib/isprint.S0000644000000000000000000000321011732702554015054 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: isprint.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lisprint 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/abort.c0000644000000000000000000000317311732702554014523 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION void abort(void) { for (;;); } avr-libc-1.8.0.orig/libc/stdlib/strtol.c0000644000000000000000000001151111732702554014736 0ustar /*- * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * Copyright (c) 2005, Dmitry Xmelkov * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $Id: strtol.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include #include #include "sectionname.h" /* * Convert a string to a long integer. * * Ignores `locale' stuff. Assumes that the upper and lower case * alphabets and digits are each contiguous. */ ATTRIBUTE_CLIB_SECTION long strtol(const char *nptr, char **endptr, register int base) { register unsigned long acc; register unsigned char c; register unsigned long cutoff; register signed char any; unsigned char flag = 0; #define FL_NEG 0x01 /* number is negative */ #define FL_0X 0x02 /* number has a 0x prefix */ if (endptr) *endptr = (char *)nptr; if (base != 0 && (base < 2 || base > 36)) return 0; /* * Skip white space and pick up leading +/- sign if any. * If base is 0, allow 0x for hex and 0 for octal, else * assume decimal; if base is already 16, allow 0x. */ do { c = *nptr++; } while (isspace(c)); if (c == '-') { flag = FL_NEG; c = *nptr++; } else if (c == '+') c = *nptr++; if ((base == 0 || base == 16) && c == '0' && (*nptr == 'x' || *nptr == 'X')) { c = nptr[1]; nptr += 2; base = 16; flag |= FL_0X; } if (base == 0) base = c == '0' ? 8 : 10; /* * Compute the cutoff value between legal numbers and illegal * numbers. That is the largest legal value, divided by the * base. An input number that is greater than this value, if * followed by a legal input character, is too big. One that * is equal to this value may be valid or not; the decision * about this is done as outlined below. * * Overflow detections works as follows: * * As: * acc_old <= cutoff * then: * acc_old * base <= 0x80000000 (unsigned) * then: * acc_old * base + c <= 0x80000000 + c * or: * acc_new <= 0x80000000 + 35 * * i.e. carry from MSB (by calculating acc_new) is impossible * and we can check result directly: * * if (acc_new > 0x80000000) then overflow * * Set any if any `digits' consumed; make it negative to indicate * overflow. */ #if LONG_MIN != -LONG_MAX - 1 # error "This implementation of strtol() does not work on this platform." #endif switch (base) { case 10: cutoff = ((unsigned long)LONG_MAX + 1) / 10; break; case 16: cutoff = ((unsigned long)LONG_MAX + 1) / 16; break; case 8: cutoff = ((unsigned long)LONG_MAX + 1) / 8; break; case 2: cutoff = ((unsigned long)LONG_MAX + 1) / 2; break; default: cutoff = ((unsigned long)LONG_MAX + 1) / base; } for (acc = 0, any = 0;; c = *nptr++) { if (c >= '0' && c <= '9') c -= '0'; else if (c >= 'A' && c <= 'Z') c -= 'A' - 10; else if (c >= 'a' && c <= 'z') c -= 'a' - 10; else break; if (c >= base) break; if (any < 0) continue; if (acc > cutoff) { any = -1; continue; } acc = acc * base + c; if (acc > (unsigned long)LONG_MAX + 1) any = -1; else any = 1; } if (endptr) { if (any) *endptr = (char *)nptr - 1; else if (flag & FL_0X) *endptr = (char *)nptr - 2; } if (any < 0) { acc = (flag & FL_NEG) ? LONG_MIN : LONG_MAX; errno = ERANGE; } else if (flag & FL_NEG) { acc = -acc; } else if ((signed long)acc < 0) { acc = LONG_MAX; errno = ERANGE; } return (acc); } avr-libc-1.8.0.orig/libc/stdlib/isblank.S0000644000000000000000000000321011732702554015007 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: isblank.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lisblank 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/toascii.S0000644000000000000000000000321011732702554015017 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: toascii.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Ltoascii 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/tolower.S0000644000000000000000000000321011732702554015057 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: tolower.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Ltolower 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/atof.S0000644000000000000000000000407711732702554014331 0ustar /* Copyright (c) 2002 Michael Stumpf All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: atof.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \ingroup avr_stdlib \fn double atof (const char *nptr) The atof() function converts the initial portion of the string pointed to by \a nptr to double representation. It is equivalent to calling \code strtod(nptr, (char **)0); \endcode */ #ifndef __DOXYGEN__ #include "macros.inc" ASSEMBLY_CLIB_SECTION .global atof .type atof, "function" atof: clr r22 clr r23 XJMP strtod .size atof, .-atof .end #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/stdlib/dtostrf.c0000644000000000000000000000462111732702554015100 0ustar /* Copyright (c) 2005, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: dtostrf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include "ftoa_engine.h" #include "dtoa_conv.h" #include "sectionname.h" /* ??? Is 'width' a signed value? dtostrf.S comment: If precision is < 0, the string is left adjusted with leading spaces. If precision is > 0, the string is right adjusted with trailing spaces. dtostrf.S code: 'p_width' is a register for left/right adjustment avr-libc manual: nothing about this So, for compatibilty 'width' is signed value to left/right adjust. */ ATTRIBUTE_CLIB_SECTION char * dtostrf (double val, signed char width, unsigned char prec, char *sout) { unsigned char flags; /* DTOA_UPPER: for compatibility with avr-libc <= 1.4 with NaNs */ flags = width < 0 ? DTOA_LEFT | DTOA_UPPER : DTOA_UPPER; dtoa_prf (val, sout, abs(width), prec, flags); return sout; } /*** end of file ***/ avr-libc-1.8.0.orig/libc/stdlib/exit.S0000644000000000000000000000343011732702554014341 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: exit.S 1944 2009-04-01 23:12:20Z arcanum $ */ #ifndef __DOXYGEN__ #include "macros.inc" ASSEMBLY_CLIB_SECTION .global _U(exit) .type _U(exit), "function" _U(exit): cli XJMP _U(_exit) .size _U(exit), . - _U(exit) #endif /* !__DOXYGEN__ */ avr-libc-1.8.0.orig/libc/stdlib/atol.c0000644000000000000000000000323711732702554014354 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "sectionname.h" ATTRIBUTE_CLIB_SECTION long atol(const char *p) { return strtol(p, (char **) NULL, 10); } avr-libc-1.8.0.orig/libc/stdlib/setjmp.S0000644000000000000000000001143111732702554014672 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: setjmp.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) /* setjmp.S Contributors: Created by Marek Michalkiewicz */ /* jmp_buf: offset size description 0 16 call-saved registers (r2-r17) 16 2 frame pointer (r29:r28) 18 2 stack pointer (SPH:SPL) 20 1 status register (SREG) 21 2/3 return address (PC) (2 bytes used for <=128Kw flash) 23/24 = total size All multibytes are stored as little-endian. int setjmp(jmp_buf __jmpb); void longjmp(jmp_buf __jmpb, int __val) __attribute__((noreturn)); */ #ifndef __DOXYGEN__ #include #include "macros.inc" /* ???: What was a reason to use aliases for common registers? Check the address: is it a port number (value for IN/OUT)? */ #if AVR_STACK_POINTER_LO_ADDR != 0x3D \ || AVR_STATUS_ADDR != 0x3F # error "Strange address of common registers SPL, SREG" #endif #define jmpb_hi r25 #define jmpb_lo r24 #define val_hi r23 #define val_lo r22 #define ret_lo r24 #define ret_hi r25 ASSEMBLY_CLIB_SECTION .global _U(setjmp) .type _U(setjmp), @function _U(setjmp): X_movw XL, jmpb_lo ; save call-saved registers and frame pointer .irp .L_regno, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,28,29 st X+, r\.L_regno .endr ; get return address #if defined(__AVR_3_BYTE_PC__) && __AVR_3_BYTE_PC__ pop __tmp_reg__ ; used below #endif pop ZH pop ZL ; save stack pointer (after poping) in ret_lo, AVR_STACK_POINTER_LO_ADDR st X+, ret_lo #ifdef _HAVE_AVR_STACK_POINTER_HI in ret_lo, AVR_STACK_POINTER_HI_ADDR st X+, ret_lo #else st X+, __zero_reg__ #endif ; save status register (I flag) in ret_lo, AVR_STATUS_ADDR st X+, ret_lo ; save return address st X+, ZL st X+, ZH ; return zero clr ret_lo clr ret_hi #if defined(__AVR_3_BYTE_PC__) && __AVR_3_BYTE_PC__ st X+, __tmp_reg__ rjmp .L_jmp3 #else ijmp #endif .size _U(setjmp), . - _U(setjmp) .global _U(longjmp) .type _U(longjmp), @function _U(longjmp): X_movw XL, jmpb_lo ; return value X_movw ret_lo, val_lo ; if zero, change to 1 cpi ret_lo, 1 cpc ret_hi, __zero_reg__ adc ret_lo, __zero_reg__ ; restore call-saved registers and frame pointer .irp .L_regno, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,28,29 ld r\.L_regno, X+ .endr ; restore stack pointer (SP value before the setjmp() call) and SREG ld ZL, X+ ld ZH, X+ ld __tmp_reg__, X+ #if defined (__AVR_XMEGA__) && __AVR_XMEGA__ /* A write to SPL will automatically disable interrupts for up to 4 instructions or until the next I/O memory write. */ out AVR_STATUS_ADDR, __tmp_reg__ out AVR_STACK_POINTER_LO_ADDR, ZL out AVR_STACK_POINTER_HI_ADDR, ZH #else # ifdef _HAVE_AVR_STACK_POINTER_HI /* interrupts disabled for shortest possible time (3 cycles) */ cli out AVR_STACK_POINTER_HI_ADDR, ZH # endif /* Restore status register (including the interrupt enable flag). Interrupts are re-enabled only after the next instruction. */ out AVR_STATUS_ADDR, __tmp_reg__ out AVR_STACK_POINTER_LO_ADDR, ZL #endif ; get return address and jump ld ZL, X+ ld ZH, X+ #if defined(__AVR_3_BYTE_PC__) && __AVR_3_BYTE_PC__ ld __tmp_reg__, X+ .L_jmp3: push ZL push ZH push __tmp_reg__ ret #else ijmp #endif .size _U(longjmp), . - _U(longjmp) #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/stdlib/toupper.S0000644000000000000000000000321011732702554015062 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: toupper.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Ltoupper 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/div.S0000644000000000000000000000323511732702554014155 0ustar /* Copyright (c) 2002, Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* div() is the same as __divmodhi4() in libgcc */ #include "macros.inc" ASSEMBLY_CLIB_SECTION .global div div: XJMP __divmodhi4 avr-libc-1.8.0.orig/libc/stdlib/isspace.S0000644000000000000000000000321011732702554015013 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: isspace.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lisspace 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/isxdigit.S0000644000000000000000000000321211732702554015212 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: isxdigit.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lisxdigit 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/Makefile.am0000644000000000000000000000331511732702554015302 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # include $(top_srcdir)/libc/stdlib/Files.am EXTRA_DIST = \ $(stdlib_a_c_sources) \ $(stdlib_a_asm_sources) \ $(stdlib_a_extra_dist) avr-libc-1.8.0.orig/libc/stdlib/malloc.c0000644000000000000000000002421611732702554014664 0ustar /* Copyright (c) 2002, 2004, 2010 Joerg Wunsch Copyright (c) 2010 Gerben van den Broeke All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: malloc.c 2149 2010-06-09 20:45:37Z joerg_wunsch $ */ #include #include "sectionname.h" #include "stdlib_private.h" #ifdef MALLOC_TEST char mymem[256]; #else #include #endif /* MALLOC_TEST */ /* * Exported interface: * * When extending the data segment, the allocator will not try to go * beyond the current stack limit, decreased by __malloc_margin bytes. * Thus, all possible stack frames of interrupt routines that could * interrupt the current function, plus all further nested function * calls must not require more stack space, or they'll risk to collide * with the data segment. */ /* May be changed by the user only before the first malloc() call. */ size_t __malloc_margin = 32; char *__malloc_heap_start = &__heap_start; char *__malloc_heap_end = &__heap_end; char *__brkval; struct __freelist *__flp; ATTRIBUTE_CLIB_SECTION void * malloc(size_t len) { struct __freelist *fp1, *fp2, *sfp1, *sfp2; char *cp; size_t s, avail; /* * Our minimum chunk size is the size of a pointer (plus the * size of the "sz" field, but we don't need to account for * this), otherwise we could not possibly fit a freelist entry * into the chunk later. */ if (len < sizeof(struct __freelist) - sizeof(size_t)) len = sizeof(struct __freelist) - sizeof(size_t); /* * First, walk the free list and try finding a chunk that * would match exactly. If we found one, we are done. While * walking, note down the smallest chunk we found that would * still fit the request -- we need it for step 2. * */ for (s = 0, fp1 = __flp, fp2 = 0; fp1; fp2 = fp1, fp1 = fp1->nx) { if (fp1->sz < len) continue; if (fp1->sz == len) { /* * Found it. Disconnect the chunk from the * freelist, and return it. */ if (fp2) fp2->nx = fp1->nx; else __flp = fp1->nx; return &(fp1->nx); } else { if (s == 0 || fp1->sz < s) { /* this is the smallest chunk found so far */ s = fp1->sz; sfp1 = fp1; sfp2 = fp2; } } } /* * Step 2: If we found a chunk on the freelist that would fit * (but was too large), look it up again and use it, since it * is our closest match now. Since the freelist entry needs * to be split into two entries then, watch out that the * difference between the requested size and the size of the * chunk found is large enough for another freelist entry; if * not, just enlarge the request size to what we have found, * and use the entire chunk. */ if (s) { if (s - len < sizeof(struct __freelist)) { /* Disconnect it from freelist and return it. */ if (sfp2) sfp2->nx = sfp1->nx; else __flp = sfp1->nx; return &(sfp1->nx); } /* * Split them up. Note that we leave the first part * as the new (smaller) freelist entry, and return the * upper portion to the caller. This saves us the * work to fix up the freelist chain; we just need to * fixup the size of the current entry, and note down * the size of the new chunk before returning it to * the caller. */ cp = (char *)sfp1; s -= len; cp += s; sfp2 = (struct __freelist *)cp; sfp2->sz = len; sfp1->sz = s - sizeof(size_t); return &(sfp2->nx); } /* * Step 3: If the request could not be satisfied from a * freelist entry, just prepare a new chunk. This means we * need to obtain more memory first. The largest address just * not allocated so far is remembered in the brkval variable. * Under Unix, the "break value" was the end of the data * segment as dynamically requested from the operating system. * Since we don't have an operating system, just make sure * that we don't collide with the stack. */ if (__brkval == 0) __brkval = __malloc_heap_start; cp = __malloc_heap_end; if (cp == 0) cp = STACK_POINTER() - __malloc_margin; if (cp <= __brkval) /* * Memory exhausted. */ return 0; avail = cp - __brkval; /* * Both tests below are needed to catch the case len >= 0xfffe. */ if (avail >= len && avail >= len + sizeof(size_t)) { fp1 = (struct __freelist *)__brkval; __brkval += len + sizeof(size_t); fp1->sz = len; return &(fp1->nx); } /* * Step 4: There's no help, just fail. :-/ */ return 0; } ATTRIBUTE_CLIB_SECTION void free(void *p) { struct __freelist *fp1, *fp2, *fpnew; char *cp1, *cp2, *cpnew; /* ISO C says free(NULL) must be a no-op */ if (p == 0) return; cpnew = p; cpnew -= sizeof(size_t); fpnew = (struct __freelist *)cpnew; fpnew->nx = 0; /* * Trivial case first: if there's no freelist yet, our entry * will be the only one on it. If this is the last entry, we * can reduce __brkval instead. */ if (__flp == 0) { if ((char *)p + fpnew->sz == __brkval) __brkval = cpnew; else __flp = fpnew; return; } /* * Now, find the position where our new entry belongs onto the * freelist. Try to aggregate the chunk with adjacent chunks * if possible. */ for (fp1 = __flp, fp2 = 0; fp1; fp2 = fp1, fp1 = fp1->nx) { if (fp1 < fpnew) continue; cp1 = (char *)fp1; fpnew->nx = fp1; if ((char *)&(fpnew->nx) + fpnew->sz == cp1) { /* upper chunk adjacent, assimilate it */ fpnew->sz += fp1->sz + sizeof(size_t); fpnew->nx = fp1->nx; } if (fp2 == 0) { /* new head of freelist */ __flp = fpnew; return; } break; } /* * Note that we get here either if we hit the "break" above, * or if we fell off the end of the loop. The latter means * we've got a new topmost chunk. Either way, try aggregating * with the lower chunk if possible. */ fp2->nx = fpnew; cp2 = (char *)&(fp2->nx); if (cp2 + fp2->sz == cpnew) { /* lower junk adjacent, merge */ fp2->sz += fpnew->sz + sizeof(size_t); fp2->nx = fpnew->nx; } /* * If there's a new topmost chunk, lower __brkval instead. */ for (fp1 = __flp, fp2 = 0; fp1->nx != 0; fp2 = fp1, fp1 = fp1->nx) /* advance to entry just before end of list */; cp2 = (char *)&(fp1->nx); if (cp2 + fp1->sz == __brkval) { if (fp2 == NULL) /* Freelist is empty now. */ __flp = NULL; else fp2->nx = NULL; __brkval = cp2 - sizeof(size_t); } } #ifdef MALLOC_TEST #include #include #include #include void *handles[32]; size_t sizes[32]; void * alloc(size_t s) { void *p; if ((p = malloc(s)) == 0) return 0; memset(p, 0xd0, s); return p; } void printfreelist(void) { struct __freelist *fp1; int i; if (!__flp) { printf("no free list\n"); return; } for (i = 0, fp1 = __flp; fp1; i++, fp1 = fp1->nx) { printf("entry %d @ %u: size %u, next ", i, (char *)fp1 - mymem, fp1->sz); if (fp1->nx) printf("%u\n", (char *)fp1->nx - mymem); else printf("NULL\n"); } } int compare(const void *p1, const void *p2) { return *((size_t *)p1) - *((size_t *)p2); } void printalloc(void) { int j, k; size_t i; size_t sum, sum2; void *sortedhandles[32]; struct __freelist *fp; char *cp; for (i = j = k = sum = sum2 = 0; i < sizeof handles / sizeof (void *); i++) if (sizes[i]) { j++; sum += sizes[i]; if (handles[i]) { k++; sum2 += sizes[i]; } } printf("brkval: %d, %d request%s => sum %u bytes " "(actually %d reqs => %u bytes)\n", (char *)__brkval - mymem, j, j == 1? "": "s", sum, k, sum2); memcpy(sortedhandles, handles, sizeof sortedhandles); qsort(sortedhandles, 32, sizeof(void *), compare); for (i = j = 0; i < sizeof sortedhandles / sizeof (void *); i++) if ((cp = sortedhandles[i])) { cp -= sizeof(size_t); fp = (struct __freelist *)cp; printf("block %d @ %u: %u bytes\n", j, (char *)&fp->nx - mymem, fp->sz); j++; } } int main(void) { int i, j, k, l, m, om, p, f; size_t s; srand(time(0) ^ getpid()); for (k = 0; k < 100; k++) { memset(handles, 0, sizeof handles); memset(sizes, 0, sizeof sizes); j = rand() % 16 + 15; l = rand() % 80 + 7; for (i = s = 0; i < j && s < 256; i++) { sizes[i] = rand() % l + 1; s += sizes[i]; } j = i; for (m = om = 1, p = 1, f = 0; m < 1000; m++) { for (i = s = 0; i < j; i++) if (handles[i]) s++; if (s == (unsigned)j) break; if (m / om > 10) { p <<= 1; p |= 1; } for (i = 0; i < j; i++) if (rand() & p) { if (!handles[i] && (handles[i] = alloc(sizes[i])) == 0) f++; } for (i = 0; i < j; i++) if (rand() & 1) { free(handles[i]); handles[i] = 0; } } if (f) printf("%d alloc failure%s total\n", f, f == 1? "": "s"); printf("After alloc:\n"); printalloc(); printfreelist(); for (i = 0; i < j; i++) free(handles[i]); printf("After cleanup:\n"); printfreelist(); } return 0; } #endif /* MALLOC_TEST */ avr-libc-1.8.0.orig/libc/stdlib/isascii.S0000644000000000000000000000321011732702554015010 0ustar ;; Copyright (c) 2004, Theodore A. Roth ;; All rights reserved. ;; ;; Redistribution and use in source and binary forms, with or without ;; modification, are permitted provided that the following conditions are met: ;; ;; * Redistributions of source code must retain the above copyright ;; notice, this list of conditions and the following disclaimer. ;; * Redistributions in binary form must reproduce the above copyright ;; notice, this list of conditions and the following disclaimer in ;; the documentation and/or other materials provided with the ;; distribution. ;; * Neither the name of the copyright holders nor the names of ;; contributors may be used to endorse or promote products derived ;; from this software without specific prior written permission. ;; ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ;; POSSIBILITY OF SUCH DAMAGE. ;; ;; $Id: isascii.S 802 2005-08-11 20:55:26Z joerg_wunsch $ ;; #define Lisascii 1 #include "ctype.S" avr-libc-1.8.0.orig/libc/stdlib/bsearch.c0000644000000000000000000000610411732702554015020 0ustar /* * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #if defined(LIBC_SCCS) && !defined(lint) static char sccsid[] = "@(#)bsearch.c 8.1 (Berkeley) 6/4/93"; #endif /* LIBC_SCCS and not lint */ #include #include #include "sectionname.h" /* * Perform a binary search. * * The code below is a bit sneaky. After a comparison fails, we * divide the work in half by moving either left or right. If lim * is odd, moving left simply involves halving lim: e.g., when lim * is 5 we look at item 2, so we change lim to 2 so that we will * look at items 0 & 1. If lim is even, the same applies. If lim * is odd, moving right again involes halving lim, this time moving * the base up one item past p: e.g., when lim is 5 we change base * to item 3 and make lim 2 so that we will look at items 3 and 4. * If lim is even, however, we have to shrink it by one before * halving: e.g., when lim is 4, we still looked at item 2, so we * have to make lim 3, then halve, obtaining 1, so that we will only * look at item 3. */ ATTRIBUTE_CLIB_SECTION void * bsearch(register const void *key, const void *base0, size_t nmemb, register size_t size, register int (*compar)(const void *, const void *)) { register const char *base = base0; register size_t lim; register int cmp; register const void *p; for (lim = nmemb; lim != 0; lim >>= 1) { p = base + (lim >> 1) * size; cmp = (*compar)(key, p); if (cmp == 0) return ((void *)p); if (cmp > 0) { /* key > p: move right */ base = (char *)p + size; lim--; } /* else move left */ } return (NULL); } avr-libc-1.8.0.orig/libc/stdlib/realloc.c0000644000000000000000000001065611732702554015041 0ustar /* Copyright (c) 2004, 2010 Joerg Wunsch All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: realloc.c 2127 2010-06-07 14:49:37Z joerg_wunsch $ */ #include #include #include "sectionname.h" #include "stdlib_private.h" #ifndef MALLOC_TEST #include #endif ATTRIBUTE_CLIB_SECTION void * realloc(void *ptr, size_t len) { struct __freelist *fp1, *fp2, *fp3, *ofp3; char *cp, *cp1; void *memp; size_t s, incr; /* Trivial case, required by C standard. */ if (ptr == 0) return malloc(len); cp1 = (char *)ptr; cp1 -= sizeof(size_t); fp1 = (struct __freelist *)cp1; cp = (char *)ptr + len; /* new next pointer */ if (cp < cp1) /* Pointer wrapped across top of RAM, fail. */ return 0; /* * See whether we are growing or shrinking. When shrinking, * we split off a chunk for the released portion, and call * free() on it. Therefore, we can only shrink if the new * size is at least sizeof(struct __freelist) smaller than the * previous size. */ if (len <= fp1->sz) { /* The first test catches a possible unsigned int * rollover condition. */ if (fp1->sz <= sizeof(struct __freelist) || len > fp1->sz - sizeof(struct __freelist)) return ptr; fp2 = (struct __freelist *)cp; fp2->sz = fp1->sz - len - sizeof(size_t); fp1->sz = len; free(&(fp2->nx)); return ptr; } /* * If we get here, we are growing. First, see whether there * is space in the free list on top of our current chunk. */ incr = len - fp1->sz; cp = (char *)ptr + fp1->sz; fp2 = (struct __freelist *)cp; for (s = 0, ofp3 = 0, fp3 = __flp; fp3; ofp3 = fp3, fp3 = fp3->nx) { if (fp3 == fp2 && fp3->sz + sizeof(size_t) >= incr) { /* found something that fits */ if (fp3->sz + sizeof(size_t) - incr > sizeof(struct __freelist)) { /* split off a new freelist entry */ cp = (char *)ptr + len; fp2 = (struct __freelist *)cp; fp2->nx = fp3->nx; fp2->sz = fp3->sz - incr; fp1->sz = len; } else { /* it just fits, so use it entirely */ fp1->sz += fp3->sz + sizeof(size_t); fp2 = fp3->nx; } if (ofp3) ofp3->nx = fp2; else __flp = fp2; return ptr; } /* * Find the largest chunk on the freelist while * walking it. */ if (fp3->sz > s) s = fp3->sz; } /* * If we are the topmost chunk in memory, and there was no * large enough chunk on the freelist that could be re-used * (by a call to malloc() below), quickly extend the * allocation area if possible, without need to copy the old * data. */ if (__brkval == (char *)ptr + fp1->sz && len > s) { cp1 = __malloc_heap_end; cp = (char *)ptr + len; if (cp1 == 0) cp1 = STACK_POINTER() - __malloc_margin; if (cp < cp1) { __brkval = cp; fp1->sz = len; return ptr; } /* If that failed, we are out of luck. */ return 0; } /* * Call malloc() for a new chunk, then copy over the data, and * release the old region. */ if ((memp = malloc(len)) == 0) return 0; memcpy(memp, ptr, fp1->sz); free(ptr); return memp; } avr-libc-1.8.0.orig/libc/stdlib/dtoa_prf.c0000644000000000000000000000774211732702554015220 0ustar /* Copyright (c) 2005, Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: dtoa_prf.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include "ftoa_engine.h" #include "dtoa_conv.h" #include "sectionname.h" ATTRIBUTE_CLIB_SECTION int dtoa_prf (double val, char *s, unsigned char width, unsigned char prec, unsigned char flags) { int exp; int n; unsigned char vtype; unsigned char sign; unsigned char ndigs; unsigned char buf[9]; ndigs = prec < 60 ? prec + 1 : 60; exp = __ftoa_engine (val, (char *)buf, 7, ndigs); vtype = buf[0]; sign = 0; if ((vtype & (FTOA_MINUS | FTOA_NAN)) == FTOA_MINUS) sign = '-'; else if (flags & DTOA_PLUS) sign = '+'; else if (flags & DTOA_SPACE) sign = ' '; if (vtype & FTOA_NAN) { ndigs = sign ? 4 : 3; width = (width > ndigs) ? width - ndigs : 0; if (!(flags & DTOA_LEFT)) { while (width) { *s++ = ' '; width--; } } if (sign) *s++ = sign; if (flags & DTOA_UPPER) { *s++ = 'N'; *s++ = 'A'; *s++ = 'N'; } else { *s++ = 'n'; *s++ = 'a'; *s++ = 'n'; } while (width) { *s++ = ' '; width--; } *s = 0; return DTOA_NONFINITE; } if (vtype & FTOA_INF) { ndigs = sign ? 4 : 3; width = (width > ndigs) ? width - ndigs : 0; if (!(flags & DTOA_LEFT)) { while (width) { *s++ = ' '; width--; } } if (sign) *s++ = sign; if (flags & DTOA_UPPER) { *s++ = 'I'; *s++ = 'N'; *s++ = 'F'; } else { *s++ = 'i'; *s++ = 'n'; *s++ = 'f'; } while (width) { *s++ = ' '; width--; } *s = 0; return DTOA_NONFINITE; } n = (sign ? 1 : 0) + (exp>0 ? exp+1 : 1) + (prec ? prec+1 : 0); width = width > n ? width - n : 0; if (!(flags & DTOA_LEFT) && !(flags & DTOA_ZFILL)) { while (width) { *s++ = ' '; width--; } } if (sign) *s++ = sign; if (!(flags & DTOA_LEFT)) { while (width) { *s++ = '0'; width--; } } ndigs += exp; /* exp is resticted approx. -40 .. +40 */ sign = buf[1]; if ((vtype & FTOA_CARRY) && sign == '1') ndigs -= 1; if ((signed char)ndigs < 1) ndigs = 1; else if (ndigs > 8) ndigs = 8; n = exp > 0 ? exp : 0; do { if (n == -1) *s++ = '.'; flags = (n <= exp && n > exp - ndigs) ? buf[exp - n + 1] : '0'; if (--n < -prec) break; *s++ = flags; } while (1); if ( n == exp && (sign > '5' || (sign == '5' && !(vtype & FTOA_CARRY))) ) flags = '1'; *s++ = flags; while (width) { *s++ = ' '; width--; } *s++ = 0; return 0; } /*** end of file ***/ avr-libc-1.8.0.orig/libc/string/0000755000000000000000000000000011732702554013271 5ustar avr-libc-1.8.0.orig/libc/string/strlcat.S0000644000000000000000000000712111732702554015072 0ustar /* AVR LIBC strlcat() Copyright (c) 2003, 2007 Eric B. Weddington, R. Patommel Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlcat.S 2267 2011-12-29 07:53:03Z joerg_wunsch $ */ /** \file */ /** \ingroup avr_string \fn size_t strlcat (char *dst, const char *src, size_t siz) \brief Concatenate two strings. Appends \p src to string \p dst of size \p siz (unlike strncat(), \p siz is the full size of \p dst, not space left). At most \p siz-1 characters will be copied. Always NULL terminates (unless \p siz <= \p strlen(dst)). \returns The strlcat() function returns strlen(src) + MIN(siz, strlen(initial dst)). If retval >= siz, truncation occurred. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" /* size_t strlcat (char *dst, const char *src, size_t siz) { char *d = dst; const char *s = src; do { if (--siz == ~0u) goto Len; // siz <= strlen(dst) } while (*d++); d -= 1; goto m; do { if (!(*d++ = *s++)) return (d - dst - 1); // normal end m: ; } while (--siz != ~0u); *d = 0; Len: return (d - dst + strlen (s)); } */ #define dst_lo r24 #define dst_hi r25 #define src_lo r22 #define src_hi r23 #define siz_lo r20 #define siz_hi r21 #define ret_lo r24 ENTRY strlcat X_movw XL, dst_lo ; X = dst X_movw ZL, src_lo ; Z = src ; find end of dst: X := dst + strlen(dsr) 1: subi siz_lo, lo8(1) sbci siz_hi, hi8(1) brlo .Len ; siz <= strlen(dst) ld __tmp_reg__, X+ tst __tmp_reg__ brne 1b sbiw XL, 1 rjmp 3f ; copy loop 2: ld __tmp_reg__, Z+ st X+, __tmp_reg__ tst __tmp_reg__ breq .Ldd 3: subi siz_lo, lo8(1) sbci siz_hi, hi8(1) brsh 2b st X, __zero_reg__ ; return (d - dst + strlen(s)) X_movw src_lo, ZL ; update for strlen(s) calculation .Len: ld __tmp_reg__, Z+ ; find end of src tst __tmp_reg__ brne .Len sub ZL, src_lo ; Z := strlen(s) + 1 sbc ZH, src_hi add XL, ZL ; d += strlen(s) + 1 adc XH, ZH .Ldd: sec ; d -= dst + 1 sbc XL, dst_lo sbc XH, dst_hi X_movw ret_lo, XL ; return value ret ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* not __AVR_TINY__ */ avr-libc-1.8.0.orig/libc/string/memccpy.S0000644000000000000000000000571211732702554015057 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memccpy.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn void *memccpy(void *dest, const void *src, int val, size_t len) \brief Copy memory area. The memccpy() function copies no more than \p len bytes from memory area \p src to memory area \p dest, stopping when the character \p val is found. \returns The memccpy() function returns a pointer to the next character in \p dest after \p val, or NULL if \p val was not found in the first \p len characters of \p src. */ /** \ingroup avr_pgmspace \fn void *memccpy_P (void *dest, PGM_VOID_P src, int val, size_t len) This function is similar to memccpy() except that \p src is pointer to a string in program space. */ #if !defined(__DOXYGEN__) #include "asmdef.h" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 #define val_lo r20 #define len_hi r19 #define len_lo r18 #define ret_hi r25 #define ret_lo r24 #if defined(Lprogmem) && !defined(__AVR_TINY__) # define memccpy memccpy_P # define LOAD X_lpm #else # define LOAD ld #endif ENTRY memccpy X_movw ZL, src_lo X_movw XL, dest_lo .L_memccpy_loop: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcs .L_memccpy_notfound LOAD __tmp_reg__, Z+ st X+, __tmp_reg__ cp __tmp_reg__, val_lo brne .L_memccpy_loop X_movw ret_lo, XL ret .L_memccpy_notfound: clr ret_lo clr ret_hi ret ENDFUNC #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strcspn.S0000644000000000000000000000542311732702554015115 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcspn.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn size_t strcspn(const char *s, const char *reject) The strcspn() function calculates the length of the initial segment of \p s which consists entirely of characters not in \p reject. \return The strcspn() function returns the number of characters in the initial segment of \p s which are not in the string \p reject. The terminating zero is not considered as a part of string. */ #if !defined(__AVR_TINY__) #ifndef __DOXYGEN__ #include "macros.inc" #define str_lo r24 #define str_hi r25 #define acc_lo r22 #define acc_hi r23 #define chs r21 /* char from s[] */ ASSEMBLY_CLIB_SECTION .global _U(strcspn) .type _U(strcspn), @function _U(strcspn): X_movw XL, str_lo ; get next symbol from s[] 1: ld chs, X+ ; *s++ tst chs breq 3f ; check an occurance X_movw ZL, acc_lo 2: ld r0, Z+ cp r0, chs cpse r0, __zero_reg__ brne 2b brne 1b ; branch if chs is't present in reject[] ; end of scanning: chs is found or end of s[] is reached ; Return: X - 1 - str == X + ~str 3: com str_lo com str_hi add str_lo, XL adc str_hi, XH ret .size _U(strcspn), . - _U(strcspn) #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strrev.S0000644000000000000000000000523511732702554014747 0ustar /* Copyright (c) 2002, 2007 Reiner Patommel Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strrev.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* strrev.S Reverse a string Contributors: Created by Reiner Patommel */ /** \file */ /** \ingroup avr_string \fn char *strrev(char *s) \brief Reverse a string. The strrev() function reverses the order of the string. \returns The strrev() function returns a pointer to the beginning of the reversed string. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define str_hi r25 #define str_lo r24 #define ltemp r23 #define rtemp r22 ASSEMBLY_CLIB_SECTION .global _U(strrev) .type _U(strrev), @function _U(strrev): X_movw XL, str_lo ; X is start of string X_movw ZL, str_lo ; Z becomes end of string ; find end of string 1: mov rtemp, ltemp ; to obtain right nonzero character ld ltemp, Z+ tst ltemp brne 1b sbiw ZL, 2 ; to last nonzero byte rjmp 3f ; swap bytes 2: ld ltemp, X st X+, rtemp st Z, ltemp ld rtemp, -Z 3: cp XL, ZL cpc XH, ZH brlo 2b ret .size _U(strrev), . - _U(strrev) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/ffsll.S0000644000000000000000000000507111732702554014526 0ustar /* Copyright (c) 2005, 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ffsll.S 2191 2010-11-05 13:45:57Z arcanum $ */ #if !defined(__AVR_TINY__) /** \file */ /** \ingroup avr_string \fn int ffsll (long long val); \brief Same as ffs(), for an argument of type long long. */ #ifndef __DOXYGEN__ #include "macros.inc" #define val_0 r18 #define val_8 r19 #define val_16 r20 #define val_24 r21 #define val_32 r22 #define val_40 r23 #define val_48 r24 #define val_56 r25 #define wrd_lo r30 #define wrd_hi r31 #define cntr r18 ASSEMBLY_CLIB_SECTION .global _U(ffsll) .type _U(ffsll), @function _U(ffsll): X_movw wrd_lo, val_0 ldi cntr, 1 sbiw wrd_lo, 0 brne 1f X_movw wrd_lo, val_16 subi cntr, -16 sbiw wrd_lo, 0 brne 1f X_movw wrd_lo, val_32 subi cntr, -16 sbiw wrd_lo, 0 brne 1f X_movw wrd_lo, val_48 subi cntr, -16 sbiw wrd_lo, 0 breq 9f 1: tst wrd_lo brne 3f subi cntr, -7 mov wrd_lo, wrd_hi 2: inc cntr 3: ror wrd_lo brcc 2b mov r24, cntr clr r25 9: ret .size _U(ffsll), . - _U(ffsll) .end #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strtok.c0000644000000000000000000000476611732702554015000 0ustar /* Copyright (c) 2008, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strtok.c 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strtok(char *s, const char *delim) \brief Parses the string s into tokens. strtok parses the string s into tokens. The first call to strtok should have s as its first argument. Subsequent calls should have the first argument set to NULL. If a token ends with a delimiter, this delimiting character is overwritten with a '\\0' and a pointer to the next character is saved for the next call to strtok. The delimiter string delim may be different for each call. \returns The strtok() function returns a pointer to the next token or NULL when no more tokens are found. \note strtok() is NOT reentrant. For a reentrant version of this function see \c strtok_r(). */ #include #include "sectionname.h" static char *p; ATTRIBUTE_CLIB_SECTION char * strtok(char *s, const char *delim) { return strtok_r(s, delim, &p); } avr-libc-1.8.0.orig/libc/string/memcmp.S0000644000000000000000000000620611732702554014677 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memcmp.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn int memcmp(const void *s1, const void *s2, size_t len) \brief Compare memory areas The memcmp() function compares the first len bytes of the memory areas s1 and s2. The comparision is performed using unsigned char operations. \returns The memcmp() function returns an integer less than, equal to, or greater than zero if the first len bytes of s1 is found, respectively, to be less than, to match, or be greater than the first len bytes of s2. \note Be sure to store the result in a 16 bit variable since you may get incorrect results if you use an unsigned char or char due to truncation. \warning This function is not -mint8 compatible, although if you only care about testing for equality, this function should be safe to use. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define len_hi r21 #define len_lo r20 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(memcmp) .type _U(memcmp), @function _U(memcmp): X_movw ZL, s2_lo X_movw XL, s1_lo rjmp .L_memcmp_start .L_memcmp_loop: ld ret_lo, X+ ld __tmp_reg__, Z+ sub ret_lo, __tmp_reg__ brne .L_memcmp_done .L_memcmp_start: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcc .L_memcmp_loop ; strings are equal, so clear both ret_lo and carry sub ret_lo, ret_lo .L_memcmp_done: ; ret_hi = SREG.C ? 0xFF : 0 sbc ret_hi, ret_hi ret .L_memcmp_end: .size _U(memcmp), .L_memcmp_end - _U(memcmp) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/memchr.S0000644000000000000000000000542211732702554014673 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memchr.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn void *memchr(const void *src, int val, size_t len) \brief Scan memory for a character. The memchr() function scans the first len bytes of the memory area pointed to by src for the character val. The first byte to match val (interpreted as an unsigned character) stops the operation. \returns The memchr() function returns a pointer to the matching byte or NULL if the character does not occur in the given memory area. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define src_hi r25 #define src_lo r24 ; #define val_hi r23 #define val_lo r22 #define len_hi r21 #define len_lo r20 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(memchr) .type _U(memchr), @function _U(memchr): X_movw ZL, src_lo .L_memchr_loop: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcs .L_memchr_notfound ld __tmp_reg__, Z+ cp __tmp_reg__, val_lo brne .L_memchr_loop sbiw ZL, 1 ; undo post-increment X_movw ret_lo, ZL ret .L_memchr_notfound: clr ret_lo clr ret_hi ret .L_memchr_end: .size _U(memchr), .L_memchr_end - _U(memchr) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strchrnul.S0000644000000000000000000000463211732702554015446 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strchrnul.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strchrnul(const char *s, int c) The strchrnul() function is like strchr() except that if \p c is not found in \p s, then it returns a pointer to the null byte at the end of \p s, rather than \c NULL. (Glibc, GNU extension.) \return The strchrnul() function returns a pointer to the matched character, or a pointer to the null byte at the end of \p s (i.e., \c s+strlen(s)) if the character is not found. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" #define src_lo r24 #define val r22 #define ret_lo r24 ENTRY strchrnul X_movw ZL, src_lo 1: ld r0, Z+ cp r0, val cpse r0, __zero_reg__ brne 1b sbiw ZL, 1 ; undo post-increment X_movw ret_lo, ZL ret ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/memmem_P.S0000644000000000000000000000316411732702554015155 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memmem_P.S 1944 2009-04-01 23:12:20Z arcanum $ */ #define Lprogmem 1 #include "memmem.S" avr-libc-1.8.0.orig/libc/string/strnlen.S0000644000000000000000000000542011732702554015103 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strnlen.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn size_t strnlen(const char *src, size_t len) \brief Determine the length of a fixed-size string. The strnlen function returns the number of characters in the string pointed to by src, not including the terminating '\\0' character, but at most len. In doing this, strnlen looks only at the first len characters at src and never beyond src+len. \returns The strnlen function returns strlen(src), if that is less than len, or len if there is no '\\0' character among the first len characters pointed to by src. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define src_hi r25 #define src_lo r24 #define len_hi r23 #define len_lo r22 ASSEMBLY_CLIB_SECTION .global _U(strnlen) .type _U(strnlen), @function _U(strnlen): X_movw ZL, src_lo .L_strnlen_loop: subi len_lo, lo8(1) sbci len_hi, hi8(1) ld __tmp_reg__, Z+ cpse __tmp_reg__, __zero_reg__ brcc .L_strnlen_loop ; Z points one character past the terminating NUL ; return Z - 1 - src = (-1 - src) + Z = ~src + Z com src_lo com src_hi add src_lo, ZL adc src_hi, ZH ret .L_strnlen_end: .size _U(strnlen), .L_strnlen_end - _U(strnlen) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/Makefile.in0000644000000000000000000003234011732702554015340 0ustar # Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 1727 2008-08-01 22:05:37Z arcanum $ # # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ $(top_srcdir)/libc/string/Files.am subdir = libc/string ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = SOURCES = DIST_SOURCES = DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = @ACLOCAL@ AMTAR = @AMTAR@ AR = @AR@ AS = @AS@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AVR_LIBC_MAJOR = @AVR_LIBC_MAJOR@ AVR_LIBC_MINOR = @AVR_LIBC_MINOR@ AVR_LIBC_RELDATE = @AVR_LIBC_RELDATE@ AVR_LIBC_REVISION = @AVR_LIBC_REVISION@ AVR_LIBC_USER_MANUAL = @AVR_LIBC_USER_MANUAL@ AVR_LIBC_VERSION = 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PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_URL = @PACKAGE_URL@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ PNGTOPNM = @PNGTOPNM@ PNMTOPNG = @PNMTOPNG@ RANLIB = @RANLIB@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ TARGET_DOX_HTML = @TARGET_DOX_HTML@ TARGET_DOX_PDF = @TARGET_DOX_PDF@ VERSION = @VERSION@ abs_builddir = @abs_builddir@ abs_srcdir = @abs_srcdir@ abs_top_builddir = @abs_top_builddir@ abs_top_srcdir = @abs_top_srcdir@ ac_ct_CC = @ac_ct_CC@ am__include = @am__include@ am__leading_dot = @am__leading_dot@ am__quote = @am__quote@ am__tar = @am__tar@ am__untar = @am__untar@ bindir = @bindir@ build = @build@ build_alias = @build_alias@ build_cpu = @build_cpu@ build_os = @build_os@ build_vendor = @build_vendor@ builddir = @builddir@ datadir = @datadir@ datarootdir = @datarootdir@ docdir = @docdir@ dvidir = @dvidir@ exec_prefix = @exec_prefix@ host = @host@ host_alias = @host_alias@ host_cpu = @host_cpu@ host_os = @host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ string_a_c_sources = \ strdup.c \ strtok.c string_a_asm_sources = \ ffs.S \ ffsl.S \ ffsll.S \ memccpy.S \ memchr.S \ memcmp.S \ memcpy.S \ memmem.S \ memmem_P.S \ memmove.S \ memrchr.S \ memset.S \ strcasecmp.S \ strcasestr.S \ strcasestr_P.S \ strcat.S \ strchr.S \ strchrnul.S \ strcmp.S \ strcpy.S \ strcspn.S \ strlcat.S \ strlcpy.S \ strlen.S \ strlwr.S \ strncasecmp.S \ strncat.S \ strncmp.S \ strncpy.S \ strnlen.S \ strpbrk.S \ strrchr.S \ strrev.S \ strsep.S \ strspn.S \ strstr.S \ strtok_r.S \ strupr.S string_a_extra_dist = \ strlcat.c \ strlcpy.c EXTRA_DIST = \ $(string_a_c_sources) \ $(string_a_asm_sources) \ $(string_a_extra_dist) all: all-am .SUFFIXES: $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/string/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign libc/string/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign libc/string/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status 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avr-libc-1.8.0.orig/libc/string/strstr.S0000644000000000000000000000645311732702554014766 0ustar /* Copyright (c) 2002, 2007 Philip Soeberg Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strstr.S 2191 2010-11-05 13:45:57Z arcanum $ */ /* strstr.S Search string contained in a string Contributed by: Philip Soeberg */ /** \file */ /** \ingroup avr_string \fn char *strstr(const char *s1, const char *s2) \brief Locate a substring. The strstr() function finds the first occurrence of the substring \p s2 in the string \p s1. The terminating '\\0' characters are not compared. \returns The strstr() function returns a pointer to the beginning of the substring, or \c NULL if the substring is not found. If \p s2 points to a string of zero length, the function returns \p s1. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define chr1 r20 #define beg2 r21 /* begin of s2: s2[0] */ #define chr2 r0 ASSEMBLY_CLIB_SECTION .global _U(strstr) .type _U(strstr), @function _U(strstr): X_movw ZL, s2_lo ld beg2, Z+ tst beg2 ; is str2 empty? breq .L_ret ; return original string (req'd by standard) X_movw s2_lo, ZL ; save: address of second s2 byte 0: X_movw XL, s1_lo 1: ld chr1, X+ ; Find first char cp chr1, beg2 cpse chr1, __zero_reg__ brne 1b brne .L_no_match ; end of s1 X_movw s1_lo, XL ; store return value 2: ld chr2, Z+ ; compare strings tst chr2 breq .L_match ; end of s2 ld chr1, X+ cp chr1, chr2 cpse chr1, __zero_reg__ ; break, if end of s1 breq 2b X_movw ZL, s2_lo ; restore s2+1 cpse chr1, __zero_reg__ rjmp 0b .L_no_match: ldi s1_lo, lo8(1) ldi s1_hi, hi8(1) .L_match: sbiw s1_lo, 1 ; restore after post-increment .L_ret: ret .size _U(strstr), . - _U(strstr) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strcasestr_P.S0000644000000000000000000000317611732702554016100 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcasestr_P.S 1944 2009-04-01 23:12:20Z arcanum $ */ #define Lprogmem 1 #include "strcasestr.S" avr-libc-1.8.0.orig/libc/string/strlen.S0000644000000000000000000000471211732702554014730 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlen.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn size_t strlen(const char *src) \brief Calculate the length of a string. The strlen() function calculates the length of the string src, not including the terminating '\\0' character. \returns The strlen() function returns the number of characters in src. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define src_hi r25 #define src_lo r24 ; 10 words, (14 + strlen(src) * 5) cycles ASSEMBLY_CLIB_SECTION .global _U(strlen) .type _U(strlen), @function _U(strlen): X_movw ZL, src_lo .L_strlen_loop: ld __tmp_reg__, Z+ tst __tmp_reg__ brne .L_strlen_loop ; Z points one character past the terminating NUL ; return Z - 1 - src = (-1 - src) + Z = ~src + Z com src_lo com src_hi add src_lo, ZL adc src_hi, ZH ret .L_strlen_end: .size _U(strlen), .L_strlen_end - _U(strlen) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strcmp.S0000644000000000000000000000523511732702554014732 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcmp.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn int strcmp(const char *s1, const char *s2) \brief Compare two strings. The strcmp() function compares the two strings \p s1 and \p s2. \returns The strcmp() function returns an integer less than, equal to, or greater than zero if \p s1 is found, respectively, to be less than, to match, or be greater than \p s2. A consequence of the ordering used by strcmp() is that if \p s1 is an initial substring of \p s2, then \p s1 is considered to be "less than" \p s2. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strcmp) .type _U(strcmp), @function _U(strcmp): X_movw ZL, s2_lo X_movw XL, s1_lo .L_strcmp_loop: ld ret_lo, X+ ld __tmp_reg__, Z+ sub ret_lo, __tmp_reg__ cpse __tmp_reg__, __zero_reg__ breq .L_strcmp_loop ; ret_hi = SREG.C ? 0xFF : 0 sbc ret_hi, ret_hi ret .L_strcmp_end: .size _U(strcmp), .L_strcmp_end - _U(strcmp) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strsep.S0000644000000000000000000000706311732702554014743 0ustar /* Copyright (c) 2003, 2007 Reiner Patommel Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strsep.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strsep(char **sp, const char *delim) \brief Parse a string into tokens. The strsep() function locates, in the string referenced by \p *sp, the first occurrence of any character in the string \p delim (or the terminating '\\0' character) and replaces it with a '\\0'. The location of the next character after the delimiter character (or \c NULL, if the end of the string was reached) is stored in \p *sp. An ``empty'' field, i.e. one caused by two adjacent delimiter characters, can be detected by comparing the location referenced by the pointer returned in \p *sp to '\\0'. \return The strsep() function returns a pointer to the original value of \p *sp. If \p *sp is initially \c NULL, strsep() returns \c NULL. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define strp_lo r24 #define dlm_lo r22 #define str_lo r20 #define chr r19 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strsep) .type _U(strsep),@function _U(strsep): ; check a NULL pointer X_movw ZL, strp_lo ld XL, Z ; str address ldd XH, Z+1 X_movw str_lo, XL ; save for return adiw XL, 0 breq 5f ; return NULL ; get a symbol from str 1: ld chr, X+ ; scan delim[] X_movw ZL, dlm_lo 2: ld r0, Z+ cp r0, chr cpse r0, __zero_reg__ brne 2b ; if symbol is't match && no delim end brne 1b ; if symbol is absent in delim[] && not a zero ; chr is founded in delim[] (possible, it is a terminating zero of str) tst r0 ; the same, as chr brne 3f X_movw XL, r0 ; __zero_reg__ is r1 rjmp 4f ; OK, delimeter symbol is founded 3: st -X, __zero_reg__ ; replace by '\0' adiw XL, 1 ; address of next token ; save result to *sp and return 4: X_movw ZL, strp_lo st Z, XL std Z+1, XH 5: X_movw ret_lo, str_lo ; return original address ret .size _U(strsep), . - _U(strsep) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strtok_r.S0000644000000000000000000001025111732702554015263 0ustar /* Copyright (c) 2003, 2007 Reiner Patommel Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strtok_r.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strtok_r(char *string, const char *delim, char **last) \brief Parses string into tokens. strtok_r parses string into tokens. The first call to strtok_r should have string as its first argument. Subsequent calls should have the first argument set to NULL. If a token ends with a delimiter, this delimiting character is overwritten with a '\\0' and a pointer to the next character is saved for the next call to strtok_r. The delimiter string \p delim may be different for each call. \p last is a user allocated char* pointer. It must be the same while parsing the same string. strtok_r is a reentrant version of strtok(). \returns The strtok_r() function returns a pointer to the next token or NULL when no more tokens are found. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" /* char *strtok_r (char *s, const char *delim, char **last) { char *p = *last; const char *q; char c, d; if (!s) { if (!p) return s; // end of string s = p; // continue parsing } p = s; for (;;) { // skip delimeters s = p; // space optimization (vs. s = p-1) if (!(c = *p++)) { s = 0; p = 0; goto ret; } q = delim; do { if (!(d = *q++)) goto find_end; } while (d != c); } find_end: do { q = delim; do { d = *q++; if (c == d) { *--p = 0; p++; goto ret; } } while (d); } while ((c = *p++) != 0); p = 0; // stop parsing ret: *last = p; return s; } */ #define str_lo r24 #define dlm_lo r22 #define lst_lo r20 #define dch r18 ENTRY strtok_r X_movw ZL, lst_lo ld XL, Z+ ; X = *last ld XH, Z ; check str sbiw str_lo, 0 brne 1f sbiw XL, 0 breq .Lret ; end of string X_movw str_lo, XL ; continue parsing ; skip delimeters 1: X_movw XL, str_lo ; p = str 2: X_movw str_lo, XL ld __tmp_reg__, X+ tst __tmp_reg__ brne 3f X_movw str_lo, __tmp_reg__ ; rjmp .Lclr 3: X_movw ZL, dlm_lo 4: ld dch, Z+ tst dch breq 5f ; goto find cp dch, __tmp_reg__ brne 4b rjmp 2b ; skip 1 byte ; find new token end 5: X_movw ZL, dlm_lo 6: ld dch, Z+ cp dch, __tmp_reg__ ; __tmp_reg__ != 0 brne 7f st -X, __zero_reg__ adiw XL, 1 rjmp .Lret 7: tst dch brne 6b ; next str byte ld __tmp_reg__, X+ tst __tmp_reg__ brne 5b ; stop parsing .Lclr: X_movw XL, __tmp_reg__ ; ; save last pointer .Lret: X_movw ZL, lst_lo ; *last = X st Z+, XL st Z, XH ret ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strcasecmp.S0000644000000000000000000000611511732702554015564 0ustar /* Copyright (c) 2002, 2007 Reiner Patommel Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcasecmp.S 1944 2009-04-01 23:12:20Z arcanum $ */ /* strcasecmp.S Case insensitive compare Contributors: Created by Reiner Patommel */ /** \file */ /** \ingroup avr_string \fn int strcasecmp(const char *s1, const char *s2) \brief Compare two strings ignoring case. The strcasecmp() function compares the two strings \p s1 and \p s2, ignoring the case of the characters. \returns The strcasecmp() function returns an integer less than, equal to, or greater than zero if \p s1 is found, respectively, to be less than, to match, or be greater than \p s2. A consequence of the ordering used by strcasecmp() is that if \p s1 is an initial substring of \p s2, then \p s1 is considered to be "less than" \p s2. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define ret_hi r25 #define ret_lo r24 #define tmp r22 ASSEMBLY_CLIB_SECTION .global _U(strcasecmp) .type _U(strcasecmp), @function _U(strcasecmp): X_movw ZL, s2_lo X_movw XL, s1_lo 1: ld ret_lo, X+ ; *s1++ cpi ret_lo, 'A' ; if in [A-Z] then tolower() brlt 2f cpi ret_lo, 'Z'+1 brge 2f subi ret_lo, 'A'-'a' 2: ld tmp, Z+ ; *s2++ cpi tmp, 'A' ; if in [A-Z] then tolower() brlt 3f cpi tmp, 'Z'+1 brge 3f subi tmp, 'A'-'a' 3: sub ret_lo, tmp ; compare cpse tmp, __zero_reg__ ; break, if end of string breq 1b sbc ret_hi, ret_hi ; sign extension ret .size _U(strcasecmp), . - _U(strcasecmp) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/memmove.S0000644000000000000000000000535211732702554015067 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memmove.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn void *memmove(void *dest, const void *src, size_t len) \brief Copy memory area. The memmove() function copies len bytes from memory area src to memory area dest. The memory areas may overlap. \returns The memmove() function returns a pointer to dest. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 #define len_hi r21 #define len_lo r20 .extern _U(memcpy) ASSEMBLY_CLIB_SECTION .global _U(memmove) .type _U(memmove), @function _U(memmove): ; if src < dest, we have to copy in reverse order ; otherwise memcpy will do the right thing cp src_lo, dest_lo cpc src_hi, dest_hi brcc .L_memmove_fwd X_movw ZL, src_lo X_movw XL, dest_lo add ZL, len_lo adc ZH, len_hi add XL, len_lo adc XH, len_hi rjmp .L_memmove_start .L_memmove_loop: ld __tmp_reg__, -Z st -X, __tmp_reg__ .L_memmove_start: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcc .L_memmove_loop ; return dest (unchanged) ret .L_memmove_fwd: XJMP _U(memcpy) .L_memmove_end: .size _U(memmove), .L_memmove_end - _U(memmove) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/Files.am0000644000000000000000000000426211732702554014656 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # string_a_c_sources = \ strdup.c \ strtok.c string_a_asm_sources = \ ffs.S \ ffsl.S \ ffsll.S \ memccpy.S \ memchr.S \ memcmp.S \ memcpy.S \ memmem.S \ memmem_P.S \ memmove.S \ memrchr.S \ memset.S \ strcasecmp.S \ strcasestr.S \ strcasestr_P.S \ strcat.S \ strchr.S \ strchrnul.S \ strcmp.S \ strcpy.S \ strcspn.S \ strlcat.S \ strlcpy.S \ strlen.S \ strlwr.S \ strncasecmp.S \ strncat.S \ strncmp.S \ strncpy.S \ strnlen.S \ strpbrk.S \ strrchr.S \ strrev.S \ strsep.S \ strspn.S \ strstr.S \ strtok_r.S \ strupr.S string_a_extra_dist = \ strlcat.c \ strlcpy.c # vim: set ft=make: avr-libc-1.8.0.orig/libc/string/ffs.S0000644000000000000000000000464511732702554014204 0ustar /* Copyright (c) 2005, 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ffs.S 2166 2010-06-13 13:14:47Z joerg_wunsch $ */ /** \file */ /** \ingroup avr_string \fn int ffs (int val); \brief This function finds the first (least significant) bit set in the input value. \returns The ffs() function returns the position of the first (least significant) bit set in the word val, or 0 if no bits are set. The least significant bit is position 1. \note For expressions that are constant at compile time, consider using the \ref _FFS macro instead. */ #ifndef __DOXYGEN__ #include "macros.inc" #define val_lo r24 #define val_hi r25 #define cntr r30 ASSEMBLY_CLIB_SECTION .global _U(ffs) .type _U(ffs), @function _U(ffs): ldi cntr, 1 tst val_lo brne 2f or val_lo, val_hi breq 9f ldi cntr, 8 1: inc cntr 2: ror val_lo brcc 1b mov r24, cntr clr r25 9: ret .size _U(ffs), . - _U(ffs) .end #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strdup.c0000644000000000000000000000504611732702554014763 0ustar /* Copyright (c) 2008, Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strdup.c 1944 2009-04-01 23:12:20Z arcanum $ */ #include #include #include "sectionname.h" /** \file */ /** \ingroup avr_string \fn char *strdup(const char *s1) \brief Duplicate a string. The strdup() function allocates memory and copies into it the string addressed by s1, including the terminating null character. \warning The strdup() function calls malloc() to allocate the memory for the duplicated string! The user is responsible for freeing the memory by calling free(). \returns The strdup() function returns a pointer to the resulting string dest. If malloc() cannot allocate enough storage for the string, strdup() will return NULL. \warning Be sure to check the return value of the strdup() function to make sure that the function has succeeded in allocating the memory! */ ATTRIBUTE_CLIB_SECTION char * strdup(const char *s1) { char *s2 = malloc(strlen(s1)+1); if (s2 != NULL) { strcpy(s2, s1); } return(s2); } avr-libc-1.8.0.orig/libc/string/strcat.S0000644000000000000000000000527111732702554014722 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcat.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strcat(char *dest, const char *src) \brief Concatenate two strings. The strcat() function appends the src string to the dest string overwriting the '\\0' character at the end of dest, and then adds a terminating '\\0' character. The strings may not overlap, and the dest string must have enough space for the result. \returns The strcat() function returns a pointer to the resulting string dest. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 ASSEMBLY_CLIB_SECTION .global _U(strcat) .type _U(strcat), @function _U(strcat): X_movw ZL, src_lo X_movw XL, dest_lo .L_strcat_skip: ld __tmp_reg__, X+ tst __tmp_reg__ brne .L_strcat_skip sbiw XL, 1 ; undo post-increment .L_strcat_loop: ld __tmp_reg__, Z+ st X+, __tmp_reg__ tst __tmp_reg__ brne .L_strcat_loop ; return dest (unchanged) ret .L_strcat_end: .size _U(strcat), .L_strcat_end - _U(strcat) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strcasestr.S0000644000000000000000000001047711732702554015623 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcasestr.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strcasestr(const char *s1, const char *s2) The strcasestr() function finds the first occurrence of the substring \p s2 in the string \p s1. This is like strstr(), except that it ignores case of alphabetic symbols in searching for the substring. (Glibc, GNU extension.) \return The strcasestr() function returns a pointer to the beginning of the substring, or \c NULL if the substring is not found. If \p s2 points to a string of zero length, the function returns \p s1. */ /** \ingroup avr_pgmspace \fn char *strcasestr_P(const char *s1, PGM_P s2) This funtion is similar to strcasestr() except that \p s2 is pointer to a string in program space. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define beg2 r21 /* begin of s2 (cashed): s2[0] */ #define ctmp r20 /* scratch arg of .Lcmp() */ #define csvd r0 /* second arg of .Lcmp(), nochanged */ #ifdef Lprogmem # define strcasestr strcasestr_P # define LOAD X_lpm /* may scratch r0 */ #else # define LOAD ld #endif ENTRY strcasestr X_movw ZL, s2_lo LOAD beg2, Z+ tst beg2 ; is str2 empty? breq .L_ret ; return original string (req'd by standard) X_movw s2_lo, ZL ; save: address of second s2 byte 1: X_movw XL, s1_lo mov csvd, beg2 ; Find first char 2: ld ctmp, X+ tst ctmp breq .L_nomatch ; end of s1 rcall .Lcmp brne 2b X_movw s1_lo, XL ; store return value (decrement is needed) 3: LOAD csvd, Z+ ; compare strings (csvd is r0) tst csvd breq .L_match ; end of s2 ; Z==0 ld ctmp, X+ cpse ctmp, __zero_reg__ ; now Z==0 rcall .Lcmp ; (ctmp==0 && Z==0) || - end of s1 ; (ctmp!=0 && Z==0) || - chars are not equal ; (Z==1) - chars are equal breq 3b X_movw ZL, s2_lo ; restore s2+1 ; (ctmp==0 && Z==0) || - end of s2 ; (ctmp!=0 && Z==0) - chars are not equal cpse ctmp, __zero_reg__ ; if equal, then tail(s1) is less rjmp 1b ; then strlen(s2) .L_nomatch: ldi s1_lo, lo8(1) ldi s1_hi, hi8(1) .L_match: sbiw s1_lo, 1 ; restore after post-increment .L_ret: ret /* Compare 2 bytes ignoring a case of symbols. Input: ctmp, csvd. Return: if (bytes are equal) Z==1, else (Z==0 && ctmp != 0) Scratch: ctmp only. */ .if ('a'-'A' - 0x20) | ('Z'-'A' - 25) | ('z'-'a' - 25) .err .endif .Lcmp: eor ctmp, csvd breq 1f ; OK, bytes are equal cpi ctmp, 0x20 brne 1f ; bytes are different more than alpha case ; now caseless comparison or ctmp, csvd ; ctmp = tolower(csvd) subi ctmp, -(255 - 'z') ; shift a..z to 230..255 subi ctmp, 255 - ('z' - 'a') brlo 1f ; branch, if not an alpha sez 1: ret ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/Rules.am0000644000000000000000000000323711732702554014707 0ustar # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ include $(top_srcdir)/libc/string/Files.am # vim: set ft=make: avr-libc-1.8.0.orig/libc/string/strpbrk.S0000644000000000000000000000554511732702554015115 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strpbrk.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strpbrk(const char *s, const char *accept) The strpbrk() function locates the first occurrence in the string \p s of any of the characters in the string \p accept. \return The strpbrk() function returns a pointer to the character in \p s that matches one of the characters in \p accept, or \c NULL if no such character is found. The terminating zero is not considered as a part of string: if one or both args are empty, the result will \c NULL. */ #if !defined(__AVR_TINY__) #ifndef __DOXYGEN__ #include "macros.inc" #define str_lo r24 #define acc_lo r22 #define ret_lo r24 #define ret_hi r25 /* This realization is compact, but is not very fast: an accept string is not cashed. */ ASSEMBLY_CLIB_SECTION .global _U(strpbrk) .type _U(strpbrk), @function _U(strpbrk): X_movw XL, str_lo clr ret_hi ; a trick to save 1 word ; get next symbol from s[] 1: ld ret_lo, X+ ; *s++ tst ret_lo breq 3f ; check an occurance X_movw ZL, acc_lo 2: ld r0, Z+ cp r0, ret_lo cpse r0, __zero_reg__ brne 2b brne 1b ; branch if end of accept[] is reached ; OK, is found sbiw XL, 1 X_movw ret_lo, XL 3: ret .size _U(strpbrk), . - _U(strpbrk) #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/memrchr.S0000644000000000000000000000506711732702554015062 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memrchr.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn void *memrchr(const void *src, int val, size_t len) The memrchr() function is like the memchr() function, except that it searches backwards from the end of the \p len bytes pointed to by \p src instead of forwards from the front. (Glibc, GNU extension.) \return The memrchr() function returns a pointer to the matching byte or \c NULL if the character does not occur in the given memory area. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" #define src_hi r25 #define src_lo r24 #define val r22 #define len_hi r21 #define len_lo r20 #define ret_lo r24 ENTRY memrchr X_movw ZL, len_lo adiw ZL, 0 breq 2f ; len is 0, return NULL add ZL, src_lo adc ZH, src_hi 1: ld r0, -Z cp r0, val breq 2f ; val is found subi len_lo, lo8(1) sbci len_hi, hi8(1) brne 1b X_movw ZL, len_lo ; is zero 2: X_movw ret_lo, ZL ret ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strncat.S0000644000000000000000000000540311732702554015075 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncat.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strncat(char *dest, const char *src, size_t len) \brief Concatenate two strings. The strncat() function is similar to strcat(), except that only the first n characters of src are appended to dest. \returns The strncat() function returns a pointer to the resulting string dest. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 #define len_hi r21 #define len_lo r20 ASSEMBLY_CLIB_SECTION .global _U(strncat) .type _U(strncat), @function _U(strncat): X_movw ZL, src_lo X_movw XL, dest_lo .L_strncat_skip: ld __tmp_reg__, X+ tst __tmp_reg__ brne .L_strncat_skip sbiw XL, 1 ; undo post-increment (point the the NUL) .L_strncat_loop: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcs .L_strncat_done ld __tmp_reg__, Z+ tst __tmp_reg__ st X+, __tmp_reg__ brne .L_strncat_loop ; return dest (unchanged) ret .L_strncat_done: st X, __zero_reg__ ; return dest (unchanged) ret .L_strncat_end: .size _U(strncat), .L_strncat_end - _U(strncat) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/ffsl.S0000644000000000000000000000435011732702554014351 0ustar /* Copyright (c) 2005, 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: ffsl.S 2166 2010-06-13 13:14:47Z joerg_wunsch $ */ /** \file */ /** \ingroup avr_string \fn int ffsl (long val); \brief Same as ffs(), for an argument of type long. */ #ifndef __DOXYGEN__ #include "macros.inc" #define val_lo r22 #define val_hi r23 #define val_hlo r24 #define val_hhi r25 #define cntr r30 ASSEMBLY_CLIB_SECTION .global _U(ffsl) .type _U(ffsl), @function _U(ffsl): ldi cntr, 1 tst val_lo brne 2f subi cntr, -8 or val_lo, val_hi brne 2f subi cntr, -8 or val_lo, val_hlo brne 2f subi cntr, -7 or val_lo, val_hhi breq 9f 1: inc cntr 2: ror val_lo brcc 1b mov r24, cntr clr r25 9: ret .size _U(ffsl), . - _U(ffsl) .end #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strchr.S0000644000000000000000000000530311732702554014723 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strchr.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strchr(const char *src, int val) \brief Locate character in string. The strchr() function returns a pointer to the first occurrence of the character \p val in the string \p src. Here "character" means "byte" - these functions do not work with wide or multi-byte characters. \returns The strchr() function returns a pointer to the matched character or \c NULL if the character is not found. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define src_hi r25 #define src_lo r24 ; #define val_hi r23 #define val_lo r22 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strchr) .type _U(strchr), @function _U(strchr): X_movw ZL, src_lo .L_strchr_loop: ld ret_lo, Z+ cp ret_lo, val_lo breq .L_strchr_found tst ret_lo brne .L_strchr_loop ; not found, return NULL pointer clr ret_hi ret .L_strchr_found: sbiw ZL, 1 ; undo post-increment X_movw ret_lo, ZL ret .L_strchr_end: .size _U(strchr), .L_strchr_end - _U(strchr) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strlcat.c0000644000000000000000000000527411732702554015121 0ustar /* $OpenBSD: strlcat.c,v 1.8 2001/05/13 15:40:15 deraadt Exp $ */ /* * Copyright (c) 1998 Todd C. Miller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #if defined(LIBC_SCCS) && !defined(lint) static char *rcsid = "$OpenBSD: strlcat.c,v 1.8 2001/05/13 15:40:15 deraadt Exp $"; #endif /* LIBC_SCCS and not lint */ #include #include "sectionname.h" /** \ingroup avr_string \fn size_t strlcat (char *dst, const char *src, size_t siz) \brief Concatenate two strings. Appends src to string dst of size siz (unlike strncat(), siz is the full size of dst, not space left). At most siz-1 characters will be copied. Always NULL terminates (unless siz <= strlen(dst)). \returns The strlcat() function returns strlen(src) + MIN(siz, strlen(initial dst)). If retval >= siz, truncation occurred. */ ATTRIBUTE_CLIB_SECTION size_t strlcat (char *dst, const char *src, size_t siz) { register char *d = dst; register const char *s = src; register size_t n = siz; size_t dlen; /* Find the end of dst and adjust bytes left but don't go past end */ while (n-- != 0 && *d != '\0') d++; dlen = d - dst; n = siz - dlen; if (n == 0) return(dlen + strlen(s)); while (*s != '\0') { if (n != 1) { *d++ = *s; n--; } s++; } *d = '\0'; return(dlen + (s - src)); /* count does not include NUL */ } avr-libc-1.8.0.orig/libc/string/strlwr.S0000644000000000000000000000507411732702554014760 0ustar /* Copyright (c) 2002, 2007 Reiner Patommel Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlwr.S 1944 2009-04-01 23:12:20Z arcanum $ */ /* strlwr.S convert a string to lower case Contributors: Created by Reiner Patommel */ /** \file */ /** \ingroup avr_string \fn char *strlwr(char *s) \brief Convert a string to lower case. The strlwr() function will convert a string to lower case. Only the upper case alphabetic characters [A .. Z] are converted. Non-alphabetic characters will not be changed. \returns The strlwr() function returns a pointer to the converted string. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define str_hi r25 #define str_lo r24 #define temp r22 ASSEMBLY_CLIB_SECTION .global _U(strlwr) .type _U(strlwr), @function _U(strlwr): X_movw XL, str_lo 1: ld temp, X subi temp, 'A' cpi temp, 'Z'-'A'+1 brlo 2f ; if tepm is A..Z, then temp += 'a'-'A' subi temp, 'a'-'A' ; else restore temp 2: subi temp, -'a' st X+, temp brne 1b ; Z for temp ret .size _U(strlwr), . - _U(strlwr) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/memmem.S0000644000000000000000000000731011732702554014673 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memmem.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn void *memmem(const void *s1, size_t len1, const void *s2, size_t len2) The memmem() function finds the start of the first occurrence of the substring \p s2 of length \p len2 in the memory area \p s1 of length \p len1. \return The memmem() function returns a pointer to the beginning of the substring, or \c NULL if the substring is not found. If \p len2 is zero, the function returns \p s1. */ /** \ingroup avr_pgmspace \fn void *memmem_P(const void *s1, size_t len1, PGM_VOID_P s2, size_t len2) The memmem_P() function is similar to memmem() except that \p s2 is pointer to a string in program space. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" #define s1_hi r25 #define s1_lo r24 #define len1_hi r23 #define len1_lo r22 #define s2_hi r21 #define s2_lo r20 #define len2_hi r19 #define len2_lo r18 #define beg2 r17 /* begin of s2: s2[0] */ #define c1 r16 /* char from s1[] */ #define c2 r0 /* char from s2[]: tuned for classic lpm instr. */ #ifdef Lprogmem # define memmem memmem_P # define LOAD X_lpm #else # define LOAD ld #endif ENTRY memmem cp len2_lo, __zero_reg__ cpc len2_hi, __zero_reg__ breq .L_ret ; s2[] is empty push beg2 push c1 add len2_lo, s2_lo ; len2 = &(s2[len2]) adc len2_hi, s2_hi add len1_lo, s1_lo ; len1 = &(s1[len1]) adc len1_hi, s1_hi X_movw ZL, s2_lo LOAD beg2, Z+ ; beg2 = s2[0] X_movw s2_lo, ZL ; save: address of s2[1] 1: X_movw XL, s1_lo ; goto to begin of s1[] 2: cp XL, len1_lo ; find first char that is matched cpc XH, len1_hi brsh .L_nomatch ld c1, X+ cp c1, beg2 brne 2b X_movw s1_lo, XL ; store address X_movw ZL, s2_lo 3: cp ZL, len2_lo ; compare strings cpc ZH, len2_hi brsh .L_match ; end of s2[] --> OK cp XL, len1_lo cpc XH, len1_hi brsh .L_nomatch ; s1[] tail is too short ld c1, X+ LOAD c2, Z+ cp c1, c2 breq 3b rjmp 1b ; no equal .L_nomatch: ldi s1_lo, lo8(1) ldi s1_hi, hi8(1) .L_match: sbiw s1_lo, 1 ; restore after post-increment pop c1 pop beg2 .L_ret: ret ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strlcpy.c0000644000000000000000000000510211732702554015133 0ustar /* $OpenBSD: strlcpy.c,v 1.5 2001/05/13 15:40:16 deraadt Exp $ */ /* * Copyright (c) 1998 Todd C. Miller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #if defined(LIBC_SCCS) && !defined(lint) static char *rcsid = "$OpenBSD: strlcpy.c,v 1.5 2001/05/13 15:40:16 deraadt Exp $"; #endif /* LIBC_SCCS and not lint */ #include #include "sectionname.h" /** \ingroup avr_string \fn size_t strlcpy (char *dst, const char *src, size_t siz) \brief Copy a string. Copy src to string dst of size siz. At most siz-1 characters will be copied. Always NULL terminates (unless siz == 0). \returns The strlcpy() function returns strlen(src). If retval >= siz, truncation occurred. */ ATTRIBUTE_CLIB_SECTION size_t strlcpy (char *dst, const char *src, size_t siz) { register char *d = dst; register const char *s = src; register size_t n = siz; /* Copy as many bytes as will fit */ if (n != 0 && --n != 0) { do { if ((*d++ = *s++) == 0) break; } while (--n != 0); } /* Not enough room in dst, add NUL and traverse rest of src */ if (n == 0) { if (siz != 0) *d = '\0'; /* NUL-terminate dst */ while (*s++) ; } return(s - src - 1); /* count does not include NUL */ } avr-libc-1.8.0.orig/libc/string/Makefile.am0000644000000000000000000000331411732702554015326 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 1727 2008-08-01 22:05:37Z arcanum $ # include $(top_srcdir)/libc/string/Files.am EXTRA_DIST = \ $(string_a_c_sources) \ $(string_a_asm_sources) \ $(string_a_extra_dist) avr-libc-1.8.0.orig/libc/string/strncmp.S0000644000000000000000000000545311732702554015112 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncmp.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn int strncmp(const char *s1, const char *s2, size_t len) \brief Compare two strings. The strncmp() function is similar to strcmp(), except it only compares the first (at most) n characters of s1 and s2. \returns The strncmp() function returns an integer less than, equal to, or greater than zero if s1 (or the first n bytes thereof) is found, respectively, to be less than, to match, or be greater than s2. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define len_hi r21 #define len_lo r20 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strncmp) .type _U(strncmp), @function _U(strncmp): X_movw ZL, s2_lo X_movw XL, s1_lo .L_strncmp_loop: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcs .L_strncmp_equal ld ret_lo, X+ ld __tmp_reg__, Z+ sub ret_lo, __tmp_reg__ brne .L_strncmp_done tst __tmp_reg__ brne .L_strncmp_loop .L_strncmp_equal: sub ret_lo, ret_lo ; clear ret_lo and C flag .L_strncmp_done: ; ret_hi = SREG.C ? 0xFF : 0 sbc ret_hi, ret_hi ret .L_strncmp_end: .size _U(strncmp), .L_strncmp_end - _U(strncmp) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strspn.S0000644000000000000000000000555711732702554014762 0ustar /* Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strspn.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn size_t strspn(const char *s, const char *accept) The strspn() function calculates the length of the initial segment of \p s which consists entirely of characters in \p accept. \return The strspn() function returns the number of characters in the initial segment of \p s which consist only of characters from \p accept. The terminating zero is not considered as a part of string. */ #if !defined(__AVR_TINY__) #ifndef __DOXYGEN__ #include "macros.inc" #define str_lo r24 #define str_hi r25 #define acc_lo r22 #define acc_hi r23 #define chs r21 /* char from s[] */ /* This realization is compact, but is not very fast: an accept string is not cashed. */ ASSEMBLY_CLIB_SECTION .global _U(strspn) .type _U(strspn), @function _U(strspn): X_movw XL, str_lo ; get next symbol from s[] 1: ld chs, X+ ; *s++ tst chs breq 3f ; check an occurance X_movw ZL, acc_lo 2: ld r0, Z+ cp r0, chs cpse r0, __zero_reg__ brne 2b breq 1b ; branch if chs is present in accept[] ; end of scanning: chs is not found or end of s[] is reached ; Return: X - 1 - str == X + ~str 3: com str_lo com str_hi add str_lo, XL adc str_hi, XH ret .size _U(strspn), . - _U(strspn) #endif /* !__DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strcpy.S0000644000000000000000000000545711732702554014754 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strcpy.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strcpy(char *dest, const char *src) \brief Copy a string. The strcpy() function copies the string pointed to by src (including the terminating '\\0' character) to the array pointed to by dest. The strings may not overlap, and the destination string dest must be large enough to receive the copy. \returns The strcpy() function returns a pointer to the destination string dest. \note If the destination string of a strcpy() is not large enough (that is, if the programmer was stupid/lazy, and failed to check the size before copying) then anything might happen. Overflowing fixed length strings is a favourite cracker technique. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 ; 9 words, (14 + strlen(src) * 7) cycles ASSEMBLY_CLIB_SECTION .global _U(strcpy) .type _U(strcpy), @function _U(strcpy): X_movw ZL, src_lo X_movw XL, dest_lo .L_strcpy_loop: ld __tmp_reg__, Z+ st X+, __tmp_reg__ tst __tmp_reg__ brne .L_strcpy_loop ; return dest (unchanged) ret .L_strcpy_end: .size _U(strcpy), .L_strcpy_end - _U(strcpy) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strupr.S0000644000000000000000000000522411732702554014757 0ustar /* Copyright (c) 2002, 2007 Reiner Patommel Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strupr.S 1944 2009-04-01 23:12:20Z arcanum $ */ /* strupr.S Convert a string to upper case Contributors: Created by Reiner Patommel */ /** \file */ /** \ingroup avr_string \fn char *strupr(char *s) \brief Convert a string to upper case. The strupr() function will convert a string to upper case. Only the lower case alphabetic characters [a .. z] are converted. Non-alphabetic characters will not be changed. \returns The strupr() function returns a pointer to the converted string. The pointer is the same as that passed in since the operation is perform in place. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define str_hi r25 #define str_lo r24 #define temp r22 ASSEMBLY_CLIB_SECTION .global _U(strupr) .type _U(strupr), @function _U(strupr): X_movw XL, str_lo 1: ld temp, X subi temp, 'a' cpi temp, 'z'-'a'+1 brlo 2f ; if tepm is a..z, then temp += 'A'-'a' subi temp, 'A'-'a' ; else restore temp 2: subi temp, -'A' st X+, temp brne 1b ; Z for temp ret .size _U(strupr), . - _U(strupr) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/memset.S0000644000000000000000000000533311732702554014713 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memset.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn void *memset(void *dest, int val, size_t len) \brief Fill memory with a constant byte. The memset() function fills the first len bytes of the memory area pointed to by dest with the constant byte val. \returns The memset() function returns a pointer to the memory area dest. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 ; #define val_hi r23 #define val_lo r22 #define len_hi r21 #define len_lo r20 ASSEMBLY_CLIB_SECTION .global _U(memset) .type _U(memset), @function _U(memset): X_movw XL, dest_lo #if OPTIMIZE_SPEED ; 11 words, (12 + len * 4 - (len & 1)) cycles sbrs len_lo, 0 rjmp .L_memset_start rjmp .L_memset_odd .L_memset_loop: st X+, val_lo .L_memset_odd: st X+, val_lo .L_memset_start: subi len_lo, lo8(2) sbci len_hi, hi8(2) #else ; 8 words, (11 + len * 6) cycles rjmp .L_memset_start .L_memset_loop: st X+, val_lo .L_memset_start: subi len_lo, lo8(1) sbci len_hi, hi8(1) #endif brcc .L_memset_loop ; return dest (unchanged) ret .L_memset_end: .size _U(memset), .L_memset_end - _U(memset) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strlcpy.S0000644000000000000000000000545611732702554015127 0ustar /* AVR LIBC strlcpy() Copyright (c) 2003, 2007 Eric B. Weddington, R. Patommel Copyright (c) 2009 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strlcpy.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn size_t strlcpy (char *dst, const char *src, size_t siz) \brief Copy a string. Copy \p src to string \p dst of size \p siz. At most \p siz-1 characters will be copied. Always NULL terminates (unless \p siz == 0). \returns The strlcpy() function returns strlen(src). If retval >= siz, truncation occurred. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "asmdef.h" #define dst_lo r24 #define src_hi r23 #define src_lo r22 #define siz_hi r21 #define siz_lo r20 #define rslt_lo r24 ENTRY strlcpy X_movw XL, dst_lo ; X = dst X_movw ZL, src_lo ; Z = src ; copy loop 1: subi siz_lo, lo8(1) sbci siz_hi, hi8(1) brcs 4f ; is possible with siz == 0 breq 3f ; --> siz chars copied ld __tmp_reg__, Z+ st X+, __tmp_reg__ tst __tmp_reg__ brne 1b ; calculate result (Z - 1 - src) and return 2: sub ZL, src_lo sbc ZH, src_hi sbiw ZL, 1 X_movw rslt_lo, ZL ret ; terminate dst 3: st X, __zero_reg__ ; find src end 4: ld __tmp_reg__, Z+ tst __tmp_reg__ brne 4b rjmp 2b ENDFUNC #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/libc/string/strncpy.S0000644000000000000000000000601311732702554015117 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncpy.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strncpy(char *dest, const char *src, size_t len) \brief Copy a string. The strncpy() function is similar to strcpy(), except that not more than n bytes of src are copied. Thus, if there is no null byte among the first n bytes of src, the result will not be null-terminated. In the case where the length of src is less than that of n, the remainder of dest will be padded with nulls. \returns The strncpy() function returns a pointer to the destination string dest. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 #define len_hi r21 #define len_lo r20 ASSEMBLY_CLIB_SECTION .global _U(strncpy) .type _U(strncpy), @function _U(strncpy): X_movw ZL, src_lo X_movw XL, dest_lo .L_strncpy_loop: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcs .L_strncpy_done ld __tmp_reg__, Z+ st X+, __tmp_reg__ tst __tmp_reg__ brne .L_strncpy_loop ; store null characters up to the end of dest ; as the glibc manual says: ; This behavior is rarely useful, but it is specified by the ISO C standard. rjmp .L_strncpy_clr_start .L_strncpy_clr_loop: st X+, __zero_reg__ .L_strncpy_clr_start: subi len_lo, lo8(1) sbci len_hi, hi8(1) brcc .L_strncpy_clr_loop .L_strncpy_done: ; return dest (unchanged) ret .L_strncpy_end: .size _U(strncpy), .L_strncpy_end - _U(strncpy) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strncasecmp.S0000644000000000000000000000650511732702554015745 0ustar /* Copyright (c) 2002, 2007 Reiner Patommel Copyright (c) 2007 Dmitry Xmelkov All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strncasecmp.S 1944 2009-04-01 23:12:20Z arcanum $ */ /* strncasecmp.S Case insensitive compare Contributors: Created by Reiner Patommel */ /** \file */ /** \ingroup avr_string \fn int strncasecmp(const char *s1, const char *s2, size_t len) \brief Compare two strings ignoring case. The strncasecmp() function is similar to strcasecmp(), except it only compares the first \p len characters of \p s1. \returns The strncasecmp() function returns an integer less than, equal to, or greater than zero if \p s1 (or the first \p len bytes thereof) is found, respectively, to be less than, to match, or be greater than \p s2. A consequence of the ordering used by strncasecmp() is that if \p s1 is an initial substring of \p s2, then \p s1 is considered to be "less than" \p s2. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define s1_hi r25 #define s1_lo r24 #define s2_hi r23 #define s2_lo r22 #define len_hi r21 #define len_lo r20 #define tmp r22 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strncasecmp) .type _U(strncasecmp), @function _U(strncasecmp): X_movw ZL, s2_lo X_movw XL, s1_lo 1: subi len_lo, lo8(1) ; if (--len == -1) return 0 sbci len_hi, hi8(1) brlo 5f ld ret_lo, X+ ; *s1++ cpi ret_lo, 'A' ; if in [A-Z] then tolower() brlt 2f cpi ret_lo, 'Z'+1 brge 2f subi ret_lo, 'A'-'a' 2: ld tmp, Z+ ; *s2++ cpi tmp, 'A' ; if in [A-Z] then tolower() brlt 3f cpi tmp, 'Z'+1 brge 3f subi tmp, 'A'-'a' 3: sub ret_lo, tmp ; compare cpse tmp, __zero_reg__ ; break, if end of string breq 1b 4: sbc ret_hi, ret_hi ; sign extension ret 5: sub ret_lo, ret_lo ; length limit, return 0 rjmp 4b .size _U(strncasecmp), . - _U(strncasecmp) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/memcpy.S0000644000000000000000000000553011732702554014712 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: memcpy.S 1944 2009-04-01 23:12:20Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn void *memcpy(void *dest, const void *src, size_t len) \brief Copy a memory area. The memcpy() function copies len bytes from memory area src to memory area dest. The memory areas may not overlap. Use memmove() if the memory areas do overlap. \returns The memcpy() function returns a pointer to dest. */ #if !defined(__DOXYGEN__) #include "macros.inc" #define dest_hi r25 #define dest_lo r24 #define src_hi r23 #define src_lo r22 #define len_hi r21 #define len_lo r20 ASSEMBLY_CLIB_SECTION .global _U(memcpy) .type _U(memcpy), @function _U(memcpy): X_movw ZL, src_lo X_movw XL, dest_lo #if OPTIMIZE_SPEED ; 15 words, (14 + len * 6 - (len & 1)) cycles sbrs len_lo, 0 rjmp .L_memcpy_start rjmp .L_memcpy_odd .L_memcpy_loop: ld __tmp_reg__, Z+ st X+, __tmp_reg__ .L_memcpy_odd: ld __tmp_reg__, Z+ st X+, __tmp_reg__ .L_memcpy_start: subi len_lo, lo8(2) sbci len_hi, hi8(2) #else ; 11 words, (13 + len * 8) cycles rjmp .L_memcpy_start .L_memcpy_loop: ld __tmp_reg__, Z+ st X+, __tmp_reg__ .L_memcpy_start: subi len_lo, lo8(1) sbci len_hi, hi8(1) #endif brcc .L_memcpy_loop ; return dest (unchanged) ret .L_memcpy_end: .size _U(memcpy), .L_memcpy_end - _U(memcpy) #endif /* not __DOXYGEN__ */ avr-libc-1.8.0.orig/libc/string/strrchr.S0000644000000000000000000000537611732702554015117 0ustar /* Copyright (c) 2002, 2007 Marek Michalkiewicz All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: strrchr.S 2191 2010-11-05 13:45:57Z arcanum $ */ /** \file */ /** \ingroup avr_string \fn char *strrchr(const char *src, int val) \brief Locate character in string. The strrchr() function returns a pointer to the last occurrence of the character val in the string src. Here "character" means "byte" - these functions do not work with wide or multi-byte characters. \returns The strrchr() function returns a pointer to the matched character or NULL if the character is not found. */ #if !defined(__AVR_TINY__) #if !defined(__DOXYGEN__) #include "macros.inc" #define src_hi r25 #define src_lo r24 ; #define val_hi r23 #define val_lo r22 #define ret_hi r25 #define ret_lo r24 ASSEMBLY_CLIB_SECTION .global _U(strrchr) .type _U(strrchr), @function _U(strrchr): X_movw ZL, src_lo ldi ret_lo, lo8(1) ; NULL + 1 ldi ret_hi, hi8(1) .L_strrchr_loop: ld __tmp_reg__, Z+ cp __tmp_reg__, val_lo brne .L_strrchr_noteq X_movw ret_lo, ZL ; remember this character was here .L_strrchr_noteq: tst __tmp_reg__ brne .L_strrchr_loop sbiw ret_lo, 1 ; undo post-increment ret .L_strrchr_end: .size _U(strrchr), .L_strrchr_end - _U(strrchr) #endif /* not __DOXYGEN__ */ #endif /* !defined(__AVR_TINY__) */ avr-libc-1.8.0.orig/ChangeLog-20040000644000000000000000000007664211732702554013226 0ustar 2004-12-30 Theodore A. Roth * libc/stdlib/Makefile.am (lib_a_c_sources): Add stdlib_private.h. 2004-12-31 Joerg Wunsch Last-minute cleanup for release 1.2.0: * include/compat: New directory. * include/compat/ina90.h: Moved from avr/ina90.h. * include/compat/twi.h: Moved from avr/twi.h. * include/avr/ina90.h: Removed from old location. * include/avr/twi.h: Ditto. * include/avr/parity.h: Document. * doc/avr-libc-reference.html: Remove obsolete file. * doc/Makefile.am: Note removal of avr-libc-reference.html. * doc/examples/twitest/twitest.c: twi.h is in compat/ now. * doc/examples/twitest/twitest.dox: Ditto. * doc/TODO: Delete items done. * AUTHORS: Mention Ted Roth as alumni admin. * README: Upgrade info on tool versions. * NEWS: Mention forgotten items: realloc(), Copyright unification, extended delay API, man page generation, moved header files. 2004-12-30 Eric B. Weddington Apply patch #2155: 2004-04-07 Theodore A. Roth [Contriubuted by Luca Matteini] * libc/stdlib/strtol.c: Make a couple of optimizations. * libc/stdlib/strtoul.c: Ditto. 2004-12-30 Eric B. Weddington * include/avr/iom169.h: Add PRR register and bit definitions. [Fix for bug #11418] * NEWS: Update bugs fixed list. 2004-12-30 Eric B. Weddington * include/avr/iom128.h: Add USART* signal names to match datasheet. [Fix for bug #11405] * NEWS: Update bugs fixed list. 2004-12-29 Eric B. Weddington * include/avr/sleep.h: Fix bugs #6352, #10489, #11425. * NEWS: Update bugs fixed list. 2004-12-28 Joerg Wunsch * libc/stdio/vfprintf.c: Fix zero-padding when precision is given (savannah bug #9345) 2004-12-22 Joerg Wunsch * configure.in: Mark the branch as being pre-release. 2004-12-22 Joerg Wunsch * libc/stdio/fdevopen.c: document the use of calloc() [fix for savannah bug #11275] 2004-12-22 Joerg Wunsch * NEWS: Update, merge all fixes from 1.0 branch. 2004-12-22 Joerg Wunsch * doc/api/main_page.dox: Mention all newly supported devices. * doc/api/using-tools.dox: Mention all newly supported devices. 2004-12-22 Joerg Wunsch [Contributed by Frederik Rouleau ] * configure.in: move ATtiny2313 and ATtiny13 from avr5 to avr2 (by now, until a more appropriate solution can be found). 2004-12-22 Joerg Wunsch * include/avr/delay.h: Document the requirement of F_CPU. 2004-12-21 Joerg Wunsch * include/avr/delay.h: Move _delay_ms and _delay_us to double. 2004-12-21 Eric B. Weddington * include/avr/iomx8.h: Add the EEARH register definition for the mega48. [Fix for bug #11242.] 2004-12-21 Eric B. Weddington * include/avr/iom16.h: Add USART* signal names to match datasheet. [Fix for bug #11315, mentioned in comment.] 2004-12-21 Eric B. Weddington * include/avr/iom32.h: Add USART* signal names to match datasheet. [Fix for bug #11315] 2004-12-20 Joerg Wunsch * doc/examples/demo/Makefile: Default to an ATmega8 now. 2004-12-20 Joerg Wunsch * configure.in: Enable man page building. * doc/api/Makefile.am: (ditto) * doc/api/doxygen.config.in: (ditto) * scripts: new directory * scripts/avr-man.in: Wrapper script for man(1). * scripts/Makefile.am: Link avr-man.in into the build. * Makefile.am: Include the scripts subdir. 2004-12-19 Joerg Wunsch * include/avr/delay.h: Document the inline functions; implement the macros mentioned in TODO. * doc/TODO: Delete the respective TODO item. 2004-12-15 Joerg Wunsch * libm/fplib/fp_split.S: Clear r1 (__zero_reg__) upon NaN. Fix for (serious) savannah bug #7667. 2004-12-14 Joerg Wunsch * include/stdlib.h: Cosmetical doc change (for atof()). 2004-11-24 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * configure.in: * include/avr/io.h: Add support for mega165, mega325, mega3250, mega645 and mega6450. 2004-11-18 Eric B. Weddington * include/avr/iotn26.h: Replace file. This file is replaced to conform to the license since the original author could not be contacted. The new file matches the latest data sheet from Atmel. * AUTHORS: Updated. 2004-11-18 Eric B. Weddington * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iom16.h: Replace file. This file is replaced to conform to the license since the original author could not be contacted. The new file matches the latest data sheet from Atmel. * AUTHORS: Updated. 2004-11-12 Theodore A. Roth * doc/LICENSE-Changes/PERM-Bob-Paddock: * doc/LICENSE-Changes/PERM-Colin-OFlynn: * doc/LICENSE-Changes/PERM-Joerg-Wunsch: * doc/LICENSE-Changes/PERM-Juergen-Schilling: * doc/LICENSE-Changes/PERM-Keith-Gudger: * doc/LICENSE-Changes/PERM-Marek-Michalkiewicz: * doc/LICENSE-Changes/PERM-Micheal-Stumpf: * doc/LICENSE-Changes/PERM-Nils-Kristian-Strom: * doc/LICENSE-Changes/PERM-Peter-Jansen: * doc/LICENSE-Changes/PERM-Reinhard-Jessich: * doc/LICENSE-Changes/PERM-Steinar-Haugen: * doc/LICENSE-Changes/PERM-Theodore-A-Roth: New files. These are for documenting the granting of permission for copyright and licensing changes from various contributors. The files are the email messages we received from each individual. 2004-11-10 Eric B. Weddington * configure.in (AM_INIT_AUTOMAKE): Bump version. 2004-11-10 Eric B. Weddington * libm/fplib/readme.dtostre: Change Michael Stumpf's email address. * libm/fplib/readme.strtod: Ditto. * libm/fplib/readme.fplib: Ditto. Remove license as this is a README file, not software. This matches the other readme files. * libm/fplib/acos.S: Change license with permission of Michael Stumpf. Change Michael Stumpf's email address. * libm/fplib/addsf3.S: Ditto. * libm/fplib/addsf3x.S: Ditto. * libm/fplib/ceil.S: Ditto. * libm/fplib/cos.S: Ditto. * libm/fplib/cosh.S: Ditto. * libm/fplib/divsf3.S: Ditto. * libm/fplib/divsf3x.S: Ditto. * libm/fplib/dtostre.S: Ditto. * libm/fplib/exp.S: Ditto. * libm/fplib/fixsfsi.S: Ditto. * libm/fplib/floatsisf.S: Ditto. * libm/fplib/floor.S: Ditto. * libm/fplib/fmod.S: Ditto. * libm/fplib/fp_cmp.S: Ditto. * libm/fplib/fp_cosinus.S: Ditto. * libm/fplib/fp_flashconst.S: Ditto. * libm/fplib/fp_merge.S: Ditto. * libm/fplib/fp_nan.S: Ditto. * libm/fplib/fp_powerseries.S: Ditto. * libm/fplib/fp_split.S: Ditto. * libm/fplib/fp_zero.S: Ditto. * libm/fplib/fplib.inc: Ditto. * libm/fplib/frexp.S: Ditto. * libm/fplib/ldexp.S: Ditto. * libm/fplib/log10.S: Ditto. * libm/fplib/log.S: Ditto. * libm/fplib/modf.S: Ditto. * libm/fplib/mulsf3.S: Ditto. * libm/fplib/mulsf3x.S: Ditto. * libm/fplib/negsf2.S: Ditto. * libm/fplib/pow.S: Ditto. * libm/fplib/sin.S: Ditto. * libm/fplib/sinh.S: Ditto. * libm/fplib/sqrt.S: Ditto. * libm/fplib/strtod.S: Ditto. * libm/fplib/tan.S: Ditto. * libm/fplib/tanh.S: Ditto. * LICENSE: Update. * GPL: Remove. No longer needed. 2004-11-10 Eric B. Weddington * include/avr/iom128.h: Correct license with permission from Peter Jansen. * configure.in: Correct license with permission from Reinhard Jessich. * include/math.h: Correct license with permission from Michael Stumpf. * include/ctype.h: Ditto. 2004-11-10 Theodore A. Roth * Makefile.am (install-data-local): Don't try to install version.h. My implementation of that broke the build. :-( 2004-11-09 Eric B. Weddington * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/ina90.h (_NOP): Add semicolon to statement in block to avoid parse error. [Bug #10946] (_CLI): Ditto. (_SEI): Ditto. (_WDR): Ditto. (_SLEEP): Ditto. (_OPC): Ditto. (_LPM): Ditto. (_ELPM): Ditto. (output(port, val)): Ditto. Also correct parentheses around parameters. 2004-11-08 Eric B. Weddington * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iomx8.h (WDEE): Correct bit name WDEE to WDE to match the data sheet. * include/avr/wdt.h (_wdt_write): Add ability to switch the watchdog control register being used if device is tiny2313, mega48, mega88, mega168. Add new watchdog timeout constants. [Bug #10811, Bug #10872] Select correct macro to use for at90can128. [Bug #10905] * include/avr/wdt.h: Add include of . Typecast value in _wdt_write to uint8_t to make macro -mint8 compatible. 2004-11-03 Eric B. Weddington * include/avr/iom162.h: Correct license with permission from Nils Kristian Strom. * include/avr/iom169.h: Correct license with permission from Juergen Schilling. * doconf: Add copyright notice. * dodist: Ditto. * domake: Ditto. * reconf: Ditto. 2004-11-02 Eric B. Weddington * AUTHORS: Forgot to add Alexander Popov. 2004-11-02 Eric B. Weddington * include/avr/iom32.h: Correct license with permission from Steinar Haugen. * include/avr/iom64.h: Ditto. * include/avr/iom8515.h: Ditto. * include/avr/iom8535.h: Ditto. 2004-11-02 Eric B. Weddington * include/avr/iotn2313.h: Correct license with permission from Bob Paddock. * include/avr/wdt.h: Correct license with permission from Marek Michalkiewicz. * acconfig.h: Correct license with permission from Theodore A. Roth. * include/avr/iom168.h: Ditto. * include/avr/iom48.h: Ditto. * include/avr/iom88.h: Ditto. * include/avr/iomx8.h: Ditto. * include/avr/iotn13.h: Ditto. * include/avr/portpins.h: Ditto. * include/avr/sleep.h: Ditto. * xml/Atmel2libc.py: Ditto. * xml/Desc-parser.py: Ditto. * xml/Device.dtd: Ditto. 2004-11-02 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * acconfig.h: Add modified BSD license header. * avr-libc.spec.in: Ditto. * devtools/cr_check.py: Ditto. * xml/Validate.py: Ditto. 2004-11-01 Eric B. Weddington * doc/INSTALL: Update release versions compatible with avr-libc and instructions. [Bug #10150] 2004-11-01 Eric B. Weddington * include/avr/io8515.h: Correct license with permission from Marek Michalkiewicz. * include/avr/io8534.h: Ditto. * include/avr/io8535.h: Ditto. * include/avr/ioat94k.h: Ditto. * include/avr/iom103.h: Ditto. * include/avr/iom161.h: Ditto. * include/avr/iom163.h: Ditto. * include/avr/iom323.h: Ditto. * include/avr/iom8.h: Ditto. * include/avr/iotn11.h: Ditto. * include/avr/iotn12.h: Ditto. * include/avr/iotn15.h: Ditto. * include/avr/iotn22.h: Ditto. * include/avr/iotn28.h: Ditto. * include/avr/parity.h: Ditto. 2004-11-01 Eric B. Weddington * crt1/gcrt1.S: Correct license with permission from Marek Michalkiewicz. * common/macros.inc: Ditto. * include/errno.h: Ditto. * include/setjmp.h: Ditto. * include/stdint.h: Ditto. * include/string.h: Ditto. * include/avr/crc16.h: Ditto. * include/avr/delay.h: Ditto. * include/avr/eeprom.h: Ditto. * include/avr/interrupt.h: Ditto. * include/avr/io1200.h: Ditto. * include/avr/io2313.h: Ditto. * include/avr/io2323.h: Ditto. * include/avr/io2333.h: Ditto. * include/avr/io2343.h: Ditto. * include/avr/io4414.h: Ditto. * include/avr/io4433.h: Ditto. * include/avr/io4434.h: Ditto. * include/avr/io76c711.h: Ditto. * include/avr/sfr_defs.h: Ditto. * include/avr/signal.h: Ditto. * include/avr/twi.h: Ditto. 2004-11-01 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * libm/fplib/asin.S: Put lookup table into .progmem.gcc_fplib section. [Bug #9348] * libm/fplib/atan.S: Ditto. 2004-10-30 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iocan128.h: Remove duplicate definitions of PINAn. [Bug #10837] 2004-10-29 Eric B. Weddington * include/stdlib.h: Correct license with permission from Marek Michalkiewicz and Joerg Wunsch. * include/avr/io.h: Ditto. 2004-10-29 Eric B. Weddington * include/avr/io43u32x.h: Correct license with permission from Keith Gudger. * include/avr/io43u35x.h: Ditto. * include/avr/io86r401.h: Correct license with permission from Colin O'Flynn. * include/avr/iocan128.h: Ditto. 2004-10-29 Eric B. Weddington * include/avr/iom165.h: Correct license on my files. * include/avr/iom325.h: Ditto. * include/avr/iom3250.h: Ditto. * include/avr/iom645.h: Ditto. * include/avr/iom6450.h: Ditto. 2004-10-29 Eric B. Weddington * LICENSE: Show correct license statements, with full list of authors. * AUTHORS: Update list of authors. * GPL: New file. Contains the GNU Public License referenced in the fplib license. 2004-10-29 Eric B. Weddington * include/inttypes.h: Correct license with permission from Joerg Wunsch. * include/stdio.h: Ditto. * libc/stdio/vfscanf.c: Ditto. * libc/stdlib/calloc.c: Ditto. * libc/stdlib/malloc.c: Ditto. * libc/stdlib/realloc.c: Ditto. 2004-10-28 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iotn2313.h: Remove duplicate defines for PORTxn (they are defined in portpins.h). [Bug #10812] * include/avr/iocan128.h: Rename PORTxn defines to Pxn (let portpins.h define PORTxn). 2004-10-21 Eric B. Weddington * include/avr/iom64.h: Fix bit identifer ADFR to ADATE. [Bug #10733] 2004-10-21 Joerg Wunsch * doc/api/assembler.dox: Add section about gas pseudo-ops and AVR-specific operators * doc/api/faq.dox: add xref to that section here. 2004-10-15 Eric B. Weddington * include/avr/iom165.h: New file. [Patch #3375] * include/avr/iom325.h: New file. [Patch #3381] * include/avr/iom3250.h: New file. [Patch #3379] * include/avr/iom645.h: New file. [Patch #3380] * include/avr/iom6450.h: New file. [Patch #3377] Add IO header files for new devices. 2004-09-21 Joerg Wunsch * libc/stdio/vfscanf.c: fix parsing of multiple float values; fix for bug #10068. 2004-09-20 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/crc16.h: Update copyright year. (_crc16_update): Add __volatile__ to inline asm. [Bug #10450] (_crc_xmodem_update): Ditto. (_crc_ccitt_update): Ditto. 2004-09-19 Joerg Wunsch * include/stdlib.h: enable and document atof(). Delete realloc() from the #if 0 part, it's already declared and documented anyway. 2004-09-19 Joerg Wunsch * libc/stdio/vfscanf.c: Fix a logical flaw that caused characters > 'Z' && < 'a' to be misdetected as valid hex digits. Fix for bug #10420. 2004-09-19 Theodore A. Roth * include/stdint.h (__HAS_INT32_T__): Define if gcc can supply us with a 32 bit integer. (__HAS_INT64_T__): Define if gcc can supply us with a 64 bit integer. * include/avr/pgmspace.h (prog_int32_t): Use __HAS_INT32_T__ when typedef'ing. (prog_uint32_t): Ditto. (prog_int64_t): Use __HAS_INT64_T__ when typedef'ing. (prog_uint64_t): Ditto. 2004-09-19 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * configure.in: Don't generate version.h. * reconf: Don't run autoheader. 2004-09-10 Theodore A. Roth * include/avr/iomx8.h (OCIE0B): Fix value. [Bug #10001] (OCIE0A): Ditto. (OCIE1B): Ditto. (OCIE1A): Ditto. (OCIE2B): Ditto. (OCIE2A): Ditto. 2004-09-10 Theodore A. Roth [Contributed by Rene Liebscher ] * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/pgmspace.h (PSTR): Fix to allow PSTR to work with C++. 2004-09-09 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. (CHECK_AVR_DEVICE): Don't supply main() in function block of AC_TRY_COMPILE since it is already provided. 2004-08-22 Marek Michalkiewicz * include/string.h (strsep): Remove __ATTR_PURE__, bug #10078. (strtok_r): Remove __ATTR_PURE__ too. (strncmp): Add __ATTR_PURE__. 2004-08-09 Joerg Wunsch * doc/examples/twitest/twitest.c: Make it work on 1 MHz clock. * doc/examples/twitest/twitest.dox: Renumber annotations. 2004-07-23 Joerg Wunsch * doc/api/Makefile.am: rearrange demos into their own group. * doc/examples/demo/demo.dox: (Ditto) * doc/examples/twitest/twitest.dox: (Ditto) * doc/api/doxygen.config.in: include doc/examples in INPUT. * doc/examples/all-demos.dox: [new] Summary page for the demos. 2004-07-23 Joerg Wunsch * doc/api/malloc.dox: Document realloc() internals. * include/stdlib.h: include realloc(). * libc/stdlib/Makefile.am: include realloc.c. * libc/stdlib/malloc.c: move out shared parts to stdlib_private.h. * libc/stdlib/stdlib_private.h: [new] shared file for malloc()/realloc(). * libc/stdlib/realloc.c: [new] implementation of realloc(). 2004-07-22 Joerg Wunsch * include/avr/sleep.h: protect function-like macros, fix savannah bug #9013. * include/avr/ina90.h: Ditto. 2004-07-22 Joerg Wunsch * include/stdint.h: created from old inttypes.h. * include/inttypes.h: reduced to #include . 2004-07-22 Joerg Wunsch * include/stdio.h: Doc update: binary vs. raw streams explained, fix for savannah bug #9704. 2004-07-22 Joerg Wunsch * libc/stdio/fputs_p.c: pgm_read_byte(p++) -> pgm_read_byte(p) ... p++; * libc/stdio/puts_p.c: Ditto. * libc/stdio/vfprintf.c: Ditto. * libc/stdio/vfscanf.c: Ditto. 2004-07-21 Joerg Wunsch * doc/api/faq.dox: Fix the use of progmem tables, closes savannah bug #9669. 2004-07-21 Joerg Wunsch * doc/examples/demo.c: Update for ATmega32 2004-07-21 Joerg Wunsch * libc/stdio/fputs_p.c: replace PRG_RDB by pgm_read_byte * libc/stdio/puts_p.c: Ditto. * libc/stdio/vfprintf.c: Ditto. * libc/stdio/vfscanf.c: Ditto. 2004-07-20 Joerg Wunsch * libm/fplib/strtod.S: fix parsing of a partial exponent, fix *endp return value (savanna bug #2924) 2004-07-17 Joerg Wunsch * libm/fplib/pow.S: localize labels, fix pow(N, 0). 2004-07-10 Joerg Wunsch * include/inttypes.h: avr-gcc >= 3.5 will be able to provide [u]int32_t when -mint8 is in effect. 2004-07-02 Theodore A. Roth * xml/Atmel2libc.py: Add copyright/license. Tweaks to handle inconsistencies in Atmel's files. * xml/Desc-parser.py: New file. * xml/Device.dtd: Make rww_start and rww_end optional since some devices don't have rww. * xml/Validate.py: Allow shell gobbing to work so you can validate more than one file at a time. 2004-06-30 Theodore A. Roth * xml/Atmel2libc.py: Work around bugs in Atmel's xml files. * xml/Device.dtd: Change order of nrww and rww bootloader attributes. 2004-06-30 Theodore A. Roth * xml/Atmel2libc.py: Add code to handle the boot loader information. * xml/Device.dtd: Add bootloader element. 2004-06-23 Theodore A. Roth * xml/Atmel2libc.py (gather_io_info): New function. (dump_ioregs): Implement dumping ioregisters. * xml/Device.dtd: Move ioreg elements into ioregisters element. Add access and init attributes to bit_field element. 2004-06-22 Theodore A. Roth * xml/Atmel2libc.py: Fixes to allow validation of generated file. * xml/Device.dtd: Ditto. * xml/Validate.py: New file. 2004-06-22 Theodore A. Roth * xml/Device.dtd: Fix some syntax errors. 2004-06-22 Theodore A. Roth * xml/Atmel2libc.py: Now dumps header, memory size info and interrupts data as well-formed XML. * xml/Device.dtd: Change memory info to memory sizes. 2004-06-21 Theodore A. Roth * xml/Atmel2libc.py: New file. * xml/Device.dtd: Don't force copyright/license in doc (just use a comment). Make device name an attribute of device. Add memory_info element of device. Massage the interrupt and vector elements. 2004-06-20 Theodore A. Roth * xml: New directory. * xml/Device.dtd: New file. 2004-06-04 Theodore A. Roth * Makefile.am (install-data-local): Install version.h file. * acconfig.h: New file. * config-ml.in: When adding the Multi.tem fragment to the Makefile, don't use a variable or the fragment will be added to the version.h file instead of the Makefile. * configure.in: Generate the version.h config header file. * reconf: Run autoheader. 2004-05-25 Joerg Wunsch * doc/examples/demo.c: Update for ATmega8 2004-05-21 Theodore A. Roth [Contributed by Bruce Graham ] * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iotn13.h: Add comments for register defs. Fix SPMEN bit def. 2004-05-14 Theodore A. Roth [Thanks to Bruce Graham for reporting these.] * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iocan128.h (SRW00, SRW01, SRW10, SRW11): Fix bit name. (FOC2A, COM2A1, COM2A0): Ditto. 2004-05-13 Theodore A. Roth [Thanks to Bruce Graham for reporting these.] * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iocan128.h (OCR1A, OCR1AL, OCR1AH): Fix register name. (OCR1B, OCR1BL, OCR1BH, OCR1CL, OCR1CH): Ditto. (OCR3A, OCR3AL, OCR13H, OCR3B, OCR3BL, OCR3BH): Ditto. (OCR3CL, OCR3CH): Ditto. (OCR1C, OCR3C): Fix register name and address. (CANMSG): Define. 2004-04-29 Theodore A. Roth * configure.in: Set AVR_LIBC_USER_MANUAL with version number appended only if versioned docs are requested (that's the default). 2004-04-28 Theodore A. Roth * include/avr/eeprom.h (eeprom_rb): Remove deprecated interface. (eeprom_rw): Ditto. (eeprom_wb): Ditto. (_EEPUT): Use eeprom_write_byte() directly instead of eeprom_wb(). (_EEGET): Use eeprom_read_byte() directly instead of eeprom_rb(). * include/avr/pgmspace.h (PRG_RDB): Remove deprecated interface. * include/avr/sfr_defs.h (cbi): Ditto. (sbi): Ditto. (inb): Ditto. (outb): Ditto. (inw): Ditto. (outw): Ditto. (outp): Ditto. (inp): Ditto. (BV): Ditto. 2004-04-28 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/eeprom.h: Remove deprecated file. * include/ina90.h: Ditto. * include/interrupt.h: Ditto. * include/io.h: Ditto. * include/pgmspace.h: Ditto. * include/progmem.h: Ditto. * include/sig-avr.h: Ditto. * include/twi.h: Ditto. * include/wdt.h: Ditto. 2004-04-27 Theodore A. Roth * configure.in: Fix typo when adding crtm168.o to AVR_CRT_MEGA. 2004-04-27 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iocan128.h (RAMPZ): Define. 2004-04-23 Theodore A. Roth * configure.in: * crt1/Makefile.am: * include/avr/io.h: Add support infrastructure for mega48, mega88, mega168, tiny13, tiny2313 and at90can128. 2004-04-23 Theodore A. Roth * configure.in (AVR_LIBC_USER_MANUAL): Append version number. 2004-04-23 Theodore A. Roth * include/avr/iomx8.h: Undefine EECR, EEDR, EEAR, EEARL, and EEARH before defining them to avoid conflict with predfined values in io.h. 2004-04-23 Theodore A. Roth * include/avr/iocan128.h (UDR0): Define. 2004-04-23 Theodore A. Roth * include/avr/iocan128.h: Deleted commented out #defines. Formatting cleanups. 2004-04-23 Theodore A. Roth [Contributed by Colin O'Flynn ] * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iocan128.h: New file. 2004-04-22 Joerg Wunsch * doc/examples/demo.c: Update for ATmega{64,128} 2004-04-22 Theodore A. Roth [This fixes bug #8649.] * include/avr/sfr_defs.h (bit_is_set): Wrap sfr arg with _SFR_BYTE(). (bit_is_clear): Ditto. * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/sfr_defs.h: Move _SFR_BYTE() and _SFR_WORD() #defines to be before first usage. 2004-04-20 Theodore A. Roth [Contributed by LAL@pro.onet.pl] [This closes patch #2651] * include/avr/iom169.h: Change SIG_UART0_RECV to SIG_USART_RECV. Change SIG_UART0_DATA to SIG_USART_DATA. Change SIG_UART0_TRANS to SIG_USART_TRANS. 2004-04-20 Theodore A. Roth [This change should fix bug #8391] * include/avr/boot.h (__BOOT_LOCK_BITS_MASK): Remove. (__boot_lock_bits_set): Use the compliment of lock_bits arg so the user specifies only which bits are to be set. NOTE that this changes the usage but the previous usage was confusing and not well documented. (__boot_lock_bits_set_alternate): Ditto. (boot_lock_bits_set): Improve documentation. 2004-04-16 Theodore A. Roth [Contributed by Wolfgang Haidinger ] * configure.in (AM_INIT_AUTOMAKE): Bump version. * NEWS: Add note about new pgmspaces macros. * include/avr/pgmspace.h: Extend API to allow access of 32 bit unsigned double words. 2004-04-14 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iotn13.h: New file. 2004-04-13 Theodore A. Roth * include/avr/iotn2313.h: Don't define the EERIE, EEMPE, EEPE and EERE bits since they're defined in . 2004-04-13 Joerg Wunsch [Contributed by ] * include/avr/wdt.h: Fix _wdt_write() for the ATmega169, closes bug #8119. 2004-04-13 Theodore A. Roth [Contributed by Bob Paddock ] * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iotn2313.h: New file. 2004-04-06 Joerg Wunsch * doc/api/faq.dox: Cosmetics: update (C) year, remove some vestiges of trailing whitespace. 2004-04-06 Theodore A. Roth * include/avr/iom169.h: Update copyright year. Fixes for bug #8452. (OCR1A): Fix register name. (OCR1B): Ditto. (UCSRA): Ditto. (UCSRB): Ditto. (UCSRC): Ditto. (UBRR): Ditto. (UDR): Ditto. (PG5): Remove define. (ADHSM): Ditto. (WDCE): Fix bit name. (ISC01, ISC00): Define for EICRA register. 2004-04-06 Joerg Wunsch * doc/api/faq.dox: Add items for "clock skew detected", why are interrupt bits cleared by a `1', and why are programmed fuse bits at logical 0. 2004-04-06 Theodore A. Roth * include/avr/iomx8.h (ADC): Fix to make it 16 bit. (ADCW): Ditto. 2004-04-06 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iom168.h: New file. * include/avr/iom48.h: New file. * include/avr/iom88.h: New file. * include/avr/iomx8.h: New file. 2004-04-05 Joerg Wunsch * doc/api/main_page.dox, faq.dox: Add reference to Bruce Lightner's trickery page for programming small AVRs in C. 2004-04-05 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * libc/stdio/vfscanf.c: Rename set_bit and bit_is_set to avoid name space clash. Add parentheses when checking flags to quell a compiler warning. 2004-03-22 Theodore A. Roth [Thanks to Tim Lapawa ] * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/io43u32x.h (TICIE1): Fix value. * include/avr/io43u35x.h (TICIE1): Fix value. 2004-03-08 Theodore A. Roth * ChangeLog: Move 2003 entries to ChangeLog-2003. * ChangeLog-2003: New file. * Makefile.am (EXTRA_DIST): Add ChangeLog-2003 and ChangeLog-2002. * configure.in (AM_INIT_AUTOMAKE): Bump version. 2004-03-05 Joerg Wunsch * libm/fplib/dtostrf.S: fix bug # 7989 (preserve r16/r17); use movw when possible. * include/stdlib.h: document the return values of dtostre() and dtostrf(). 2004-03-04 Joerg Wunsch * libm/fplib/dtostrf.S: make labels local. 2004-03-04 Theodore A. Roth * include/avr/boot.h: Define BLBnx bit positions. [Bug #7469] 2004-03-04 Theodore A. Roth * NEWS: Add note about boot API changes. * include/avr/boot.h: Change example to show a more efficient usage of the API. (__boot_page_fill_normal): Remove checks for spm and eeprom busy. These are redundant checks in normal usage and just bloat the bootloader. (__boot_page_fill_alternate): Ditto. (__boot_page_fill_extended): Ditto. (__boot_page_erase_normal): Ditto. (__boot_page_erase_alternate): Ditto. (__boot_page_erase_extended): Ditto. (__boot_page_write_normal): Ditto. (__boot_page_write_alternate): Ditto. (__boot_page_write_extended): Ditto. (__boot_rww_enable): Ditto. (__boot_rww_enable_alternate): Ditto. (__boot_lock_bits_set): Ditto. (__boot_lock_bits_set_alternate): Ditto. (boot_page_fill_safe): New macro. (boot_page_erase_safe): New macro. (boot_page_write_safe): New macro. (boot_rww_enable_safe): New macro. (boot_lock_bits_set_safe): New macro. 2004-02-25 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * NEWS: Add note about new eeprom macro. * include/avr/boot.h: Update copyright year. (__boot_page_fill_normal): Replace while loop with eeprom_busy_wait. (__boot_page_fill_alternate): Ditto. (__boot_page_fill_extended): Ditto. (__boot_page_erase_normal): Ditto. (__boot_page_erase_alternate): Ditto. (__boot_page_erase_extended): Ditto. (__boot_page_write_normal): Ditto. (__boot_page_write_alternate): Ditto. (__boot_page_write_extended): Ditto. (__boot_rww_enable): Ditto. (__boot_rww_enable_alternate): Ditto. (__boot_lock_bits_set): Ditto. (__boot_lock_bits_set_alternate): Ditto. * include/avr/eeprom.h: Update copyright year. (eeprom_busy_wait): New macro interface. 2004-02-22 Joerg Wunsch * doc/examples/twitest/twitest.dox: Fix more formatting bugs. 2004-02-19 Joerg Wunsch * doc/examples/twitest/twitest.dox: Fix formatting bugs. 2004-02-18 Joerg Wunsch * doc/api/inline_asm.dox: Fix use of _SFR_IO_ADDR() in inline asm. * doc/api/faq.dox: Ditto. 2004-02-15 Joerg Wunsch * libc/stdlib/malloc.c: Fix bug #2143 (malloc wrap around top of RAM) * include/avr/timer.h: The mailing list agreed to remove this file. * include/timer.h: Remove this wrapper as well. 2004-02-13 Joerg Wunsch * include/avr/interrupt.h: make timer_enable_int() static inline; fixes bug #5454. 2004-02-13 Joerg Wunsch * include/avr/crc16.h: use __inline__ instead of inline. * include/avr/delay.h: Ditto. * include/avr/interrupt.h: Ditto: * include/avr/timer.h: Ditto. 2004-02-13 Joerg Wunsch * libc/stdio/vfscanf.c: Apply patch #2554: fix %ul format. 2004-02-12 Joerg Wunsch * libc/stdio/vfprintf.c: Fix bug #7556 (%s format with precision issue) For older changes see ChangeLog-2003 avr-libc-1.8.0.orig/ChangeLog-20020000644000000000000000000012567611732702554013226 0ustar 2002-12-31 Joerg Wunsch * include/stdio.h: add fgetc(). * libc/stdio/Makefile.am: Ditto. * libc/stdio/clearerr.c: add __SEOF. * libc/stdio/feof.c: Ditto. * libc/stdio/fgetc.c: add unget functionality, fix a blatant bug that caused and char except \0 to return EOF. * libc/stdio/fgets.c: use getc() instead of stream->get(). * libc/stdio/fread.c: Ditto. * libc/stdio/stdio_private.h: add ungetc() stuff, activate __SEOF. 2002-12-28 Joerg Wunsch * doc/api/using-tools.doc: explain side-effects of -ffreestanding. * include/stdio.h: add fread() and fwrite(). * libc/stdio/Makefile.am: Ditto. * libc/stdio/fread.c: New file. * libc/stdio/fwrite.c: New file. 2002-12-26 Joerg Wunsch * include/stdio.h: include declarations for basic input functions. * libc/stdio/Makefile.am: include the new files below. * libc/stdio/stdio_private.h: activate the __SERR flag. * libc/stdio/clearerr.c: New file. * libc/stdio/feof.c: New file. * libc/stdio/ferror.c: New file. * libc/stdio/fgetc.c: New file. * libc/stdio/fgets.c: New file. * libc/stdio/getc.S: New file. * libc/stdio/getchar.c: New file. * libc/stdio/gets.c: New file. 2002-12-26 Joerg Wunsch * libc/stdio/fdevopen.c: don't clobber flags when opening a stream for reading and writing. * libc/stdio/fputc.c: check __SWR before writing. * libc/stdio/fputs.c: check __SWR before writing, call stream->put() directly. * libc/stdio/fputs_p.c: Ditto. * libc/stdio/puts.c: Ditto. * libc/stdio/puts_p.c: Ditto. 2002-12-24 Joerg Wunsch * libm/fplib/readme.atan2: remove now unrelated file. 2002-12-23 Joerg Wunsch * include/avr/iom163.h: UBRRH -> UBRRHI. 2002-12-22 Joerg Wunsch * libc/stdio/fputs.c: New file. * libc/stdio/fputs_p.c: Ditto. * libc/stdio/putc.S: Ditto. * libc/stdio/putchar.c: Ditto. * libc/stdio/puts.c: Ditto. * libc/stdio/puts_p.c: Ditto. * include/stdio.h: document fputs*(), putc*(), puts*(). * libc/stdio/Makefile.am: include new files. 2002-12-22 Joerg Wunsch * libm/fplib/atan.S: completely rewritten, much better accuracy. * libm/fplib/atan2.S: completely rewritten; both contributed by Reiner Patommel. 2002-12-22 Joerg Wunsch * libm/fplib/fplib.inc: add FPPUSH, FPPOP, FPCLR, and FPSWAP macros; contributed by Reiner Patommel. 2002-12-18 Joerg Wunsch * doc/examples/twitest/twitest.c: TWI example, new file. * doc/examples/twitest/twitest.dox: TWI example, docs. * doc/examples/twitest/Makefile: TWI example, sample makefile. * doc/api/doxygen.config.in: include twitest. * doc/examples/Makefile.am: include twitest. 2002-12-18 Joerg Wunsch * include/avr/iom163.h: add bit definitions for TWSR. * include/avr/iom323.h: ditto. 2002-12-18 Joerg Wunsch * include/avr/twi.h: add some more useful macros. 2002-12-17 Joerg Wunsch * doc/api/faq.dox: add Eric's entry about relocating code to a fixed address. 2002-12-17 Joerg Wunsch * doc/api/using-tools.dox: add an anchor used in the FAQ. 2002-12-17 Theodore A. Roth * include/inttypes.h: Added more dox, since doxygen isn't generating them by default anymore. 2002-12-17 Joerg Wunsch * include/avr/wdt.h: fix typo. 2002-12-17 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iom169.h: Revert premature patch (from Joerg's work in progress). 2002-12-16 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/faq.dox: Fix broken link where doxygen tried to xref to "main()" when it should not. 2002-12-16 Joerg Wunsch * doc/api/faq.dox: add entry about effect of -Ox. 2002-12-15 Joerg Wunsch * include/avr/wdt.h: Document, invent symbolic timeout constants. * doc/TODO: delete wdt.h. 2002-12-15 Joerg Wunsch * doc/TODO: update per mailing list discussion. 2002-12-14 Joerg Wunsch * include/avr/iom169.h: fix typo. 2002-12-13 Joerg Wunsch * doc/api/main_page.dox: fix typo, remove non-existent tiny10. 2002-12-12 Joerg Wunsch * include/math.h: document isnan() and isinf(). 2002-12-12 Joerg Wunsch * include/*: add CVS Ids (where missing). 2002-12-11 Joerg Wunsch * libc/string/strstr.S: complete fixed rewrite, thanks to Philip Soeberg. 2002-12-11 Joerg Wunsch * libm/fplib/asin.S: complete rewrite, kudos to Reiner Patommel. 2002-12-09 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. 2002-12-09 Joerg Wunsch * libm/fplib/isinfnan.S: micro-optimize. 2002-12-08 Joerg Wunsch * libm/fplib/sqrt.S: move the detection of 0 earlier [Bug #1837]. 2002-12-08 Joerg Wunsch * libc/stdio/vfprintf.c: recognize Inf and NaN. 2002-12-08 Joerg Wunsch * include/math.h: add isinf()/isnan(). * libc/fplib/Makefile.am: ditto. * libc/fplib/isinfnan.S: new file. 2002-12-06 Joerg Wunsch * include/avr/iom128.h: fix defs for CS0[012]. 2002-12-06 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/Makefile.am: Generate a time-stamp file after fixing png's and anchors to inhibit unnecessary fixes. [Bug #1808] 2002-12-03 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/main_page.dox: Remove untested note from mega32. 2002-11-27 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * configure.in: Add missing ".o" to "crtm8535". 2002-11-26 Theodore A. Roth * NEWS: Note support for new devices (mega32, mega64, mega8515, mega8535). * configure.in: Add support for new megas. * doc/TODO: Remove note about new mega header files. * doc/api/main_page.dox: Add note about new megas. 2002-11-26 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/Makefile.am: Fix bad anchors. 2002-11-26 Joerg Wunsch * doc/api/faq.dox: add section about external RAM. 2002-11-26 Joerg Wunsch * doc/api/assembler.dox: New file. * doc/api/Makefile.am: use assembler.dox. * doc/api/inline_asm.dox: refer to assembler.dox. * doc/api/interrupts.dox: Ditto. 2002-11-26 Joerg Wunsch * include/stdlib.h: fix typos. 2002-11-25 Theodore A. Roth (Thanks to Steinar Haugen for contributing the iom32.h, iom64.h, iom8515.h and iom8535.h files.) * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iom128.h: Reformat. * include/avr/iom32.h: New file. * include/avr/iom64.h: New file. * include/avr/iom8515.h: New file. * include/avr/iom8535.h: New file. 2002-11-25 Joerg Wunsch * doc/TODO: remove obsolete entries. 2002-11-25 Joerg Wunsch * include/math.h: document. 2002-11-25 Joerg Wunsch * include/ctype.h: remove a wrong comment. 2002-11-25 Joerg Wunsch * include/inttypes.h: make -mint8 aware. 2002-11-24 Joerg Wunsch * Makefile.am: enable libprintf_flt.a. * include/stdio.h: explain floating point printf(). * libc/stdio/Makefile.am: enable libprintf_flt.a. * libc/stdio/stdio_private.h: define values for PRINTF_LEVEL. * libc/stdio/vfprintf.c: implement optional floating point support. 2002-11-24 Joerg Wunsch * libc/stdlib/ctype.S: cleanup empty comments. * libc/stdlib/ctype.S: add CVS Id. * libc/stdlib/ctype.S: rename cty_is* into __ctype_is*. * libc/stdlib/ctype.S: ispunct(): encapsulate func. calls using _U(). 2002-11-19 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * configure.in: Don't recurse into doc dir while building unless "--enable-doc is passed to configure. This allows a default build to bypass building the docs, but still allows the user to cd into the doc dir and build the docs if they feel lucky. Do you feel lucky, punk? 2002-11-18 Theodore A. Roth * libc/string/memcmp.S: Add note about unsigned nature of compare. 2002-11-18 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/inline_asm.dox: Update URL for project. Remove link to Rich Neswold's document since it is now (mostly) merged in with avr-libc. * doc/api/main_page.dox: Update URL for project. Update avr-libc-dev list address. Add note about avr-gcc mailing list. 2002-11-17 Joerg Wunsch * doc/examples/demo/Makefile: Use -j .text -j .data for avr-objcopy. * doc/examples/demo/demo.dox: Ditto. 2002-11-16 Theodore A. Roth * doc/api/faq.dox: Add \code and \endcode around example. D'oh! * doc/api/using-tools.dox: Use \verbatim instead of . * include/avr/pgmspace.h: Put both #includes in a single \code statement. 2002-11-16 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/faq.dox: Fix broken subject headers (doxygen-1.2.18 doesn't like them being bold when generating ps or pdf). Change \subsection to \section since doxygen-1.2.18 handles it properly now. New FAQ entry for arrays of strings in rom. * doc/api/inline_asm.dox: Change \subsection to \section since doxygen-1.2.18 handles it properly now. * doc/api/malloc.dox: Ditto. * doc/api/sections.dox: Ditto. * doc/api/tools-install.dox: Ditto. * doc/examples/demo/demo.dox: Ditto. * doc/api/using-tools.dox: Ditto. Change

    headings to \subsection's. 2002-11-12 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/TODO: Add note about missing io*.h files. * doc/api/main_page.dox: Update notes for at94K and at76c711. * include/avr/io.h: Include existing io76c711.h file. 2002-11-12 Theodore A. Roth [thanks to Juergen Schilling ] * include/avr/iom169.h: Fix interrupt vector defs. Remove duplicate PINE defs. Add PING defs. 2002-11-12 Theodore A. Roth * avr-libc.spec.in: Add --enable-doc to configure command. 2002-11-11 Theodore A. Roth * configure.in: Add --enable-doc option and disable building of docs as the default. * doc/TODO: Remove note about sleep api. * doc/api/Makefile.am: Remove sending error to /dev/null since that confuses windows systems. 2002-11-11 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/eeprom.h (eeprom_read_byte): New function, replaces eeprom_rb. (eeprom_read_word): New function, replaces eeprom_rw. (eeprom_write_byte): New function, replaces eeprom_wb. (eeprom_read_block): Change interface to take pointer to eeprom addr. (eeprom_rb): Deprecate and make macro to eeprom_read_byte. (eeprom_rw): Deprecate and make macro to eeprom_read_word. (eeprom_rw): Deprecate and make macro to eeprom_write_byte. * libc/misc/ee_rb.S: L_eeprom_rb -> L_eeprom_read_byte. * libc/misc/ee_rw.S: L_eeprom_rw -> L_eeprom_read_word. * libc/misc/ee_wb.S: L_eeprom_wb -> L_eeprom_write_byte. * libc/misc/eeprom.S: Convert to use new interfaces. 2002-11-10 Theodore A. Roth * doc/api/Makefile.am (fix_png): Gracefully handle missing USER_MANUAL directory. Fix spelling mistake. * include/avr/iom8.h: Fix copy/paste error in TWAR reg bit defs. 2002-11-09 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * eeprom.h: Formatting and punctuation changes. 2002-11-08 Theodore A. Roth * doc/examples/demo/Makefile: Remove png transparency fix-up since it's done later anyways. 2002-11-08 Theodore A. Roth * doc/INSTALL: Add note about reconf and autoconf/automake. 2002-11-08 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iom169.h: Fix typo in UCSR0A register bit def. 2002-11-08 Joerg Wunsch * include/setjmp.h: make -mint8 proof. 2002-11-05 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * include/avr/iom8.h: Sync up with latest datasheet (2486H-AVR-09/02). 2002-11-04 Theodore A. Roth * doc/api/Makefile.am: Fix all pngs to have proper transparency. 2002-11-04 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/TODO: Updated. * include/avr/sleep.h: New file. * include/avr/sfr_defs.h: Fix spelling in dox comments. 2002-10-31 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/examples/demo/Makefile: Set eeprom base addr to 0x0. 2002-10-30 Joerg Wunsch * doc/api/malloc.dox: fix typo. 2002-10-30 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/Makefile.am: Make `make demo` less likely to fail. 2002-10-30 Theodore A. Roth * doc/api/dox.css: Change default html colors. * doc/api/dox_html_header: Don't spec body bgcolor. 2002-10-29 Joerg Wunsch * doc/api/malloc.dox: Fix the fix. 2002-10-29 Joerg Wunsch * doc/api/malloc.dox: Make the addresses used consistent. * doc/api/malloc-x*.fig: Ditto. 2002-10-28 Theodore A. Roth * doc/api/malloc-std.fig: Make figs more consistent. * doc/api/malloc-x1.fig: Make figs more consistent. * doc/api/malloc-x2.fig: Make figs more consistent. * doc/api/malloc.dox: Grammar and spelling fixups. 2002-10-28 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * configure.in: Fix typo. Update my email address. Add CHECK_PNG_UTILS. * doc/api/Makefile.am: Add png and eps files to clean list. Add transparency to png images. * doc/examples/demo/Makefile: Add transparency to png images. 2002-10-28 Theodore A. Roth * doc/api/Makefile.am: Use png instead of gif images. * doc/api/malloc.dox: Ditto. 2002-10-27 Joerg Wunsch * doc/api/malloc*.fig: Improve pictures. * doc/api/malloc.dox: fix LaTeX pic widths. 2002-10-26 Joerg Wunsch * doc/api/malloc.dox: Include some pictures. * doc/api/Makefile.am: pictures' infrastructure. * doc/api/doxygen.conf.in: pictures' infrastructure. * doc/api/malloc*.fig: picture sources. 2002-10-25 Joerg Wunsch * doc/api/malloc.dox: Explain malloc details. * include/stdlib.h: refer to malloc explanation. * doc/api/Makefile.am: include malloc.dox. * doc/api/sections.dox: refer to malloc explanation. 2002-10-22 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * avr-libc.spec.in: Require doxygen >= 1.2.16 for build. 2002-10-20 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * reconf: Make compatible with RedHat-8.0 autotools. 2002-10-19 Joerg Wunsch * include/stdlib.h: make doxygen work. 2002-10-17 Joerg Wunsch * libc/stdio/vfprintf.c: implement %p. * include/stdio.h: document %p. 2002-10-16 Joerg Wunsch * Makefile.am: add hooks for libprintf_*.a. * libc/stdio/Makefile.am: ditto. * libc/stdio/vfprintf.c: add printf levels. 2002-10-16 Joerg Wunsch * configure.in libc/Makefile.am: wire stdio into the infrastructure. * include/stdio.h: new file. * libc/stdio/Makefile.am: new file. * libc/stdio/fclose.c: new file. * libc/stdio/fdevopen.c: new file. * libc/stdio/fprintf.c: new file. * libc/stdio/fprintf_p.c: new file. * libc/stdio/fputc.c: new file. * libc/stdio/printf.c: new file. * libc/stdio/printf_p.c: new file. * libc/stdio/snprintf.c: new file. * libc/stdio/snprintf_p.c: new file. * libc/stdio/sprintf.c: new file. * libc/stdio/sprintf_p.c: new file. * libc/stdio/stdio_private.h: new file. * libc/stdio/vfprintf.c: new file. 2002-10-16 Joerg Wunsch * include/stdlib.h: fix rand() & Co. * libc/stdlib/rand.c: fix rand() & Co. * libc/stdlib/random.c: New file. 2002-10-16 Joerg Wunsch * include/avr/ina90.h include/avr/pgmspace.h: Move __LPM & Co from ina90.h to pgmspace.h 2002-10-13 Theodore A. Roth * avr-libc.spec.in: Added docs subpackage for user manual. Dropped avr-gcc version to 3.2.75 to allow snapshots. * configure.in: Bumped version and made it rpm compatible. * doc/Makefile.am (EXTRA_DIST): Removed register-usage.txt. * doc/TODO: Updated. 2002-10-12 Joerg Wunsch * libc/stdlib/calloc.c: new file. * include/stdlib.h libc/stdlib/Makefile.am: add calloc(). 2002-10-11 Theodore A. Roth * include/errno.h: Add dox. * include/stdlib.h: Add xref to errno. 2002-10-11 Theodore A. Roth * doc/api/main_page.dox: Updated. 2002-10-11 Theodore A. Roth * include/string.h: Add note about flash based strings. * include/avr/pgmspace.h: Add note about ram based strings. 2002-10-11 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/Makefile.am (DEMO_LIBS): Only grab the first lib found. 2002-10-10 Theodore A. Roth * doc/TODO: Removed ctype.h. * include/ctype.h: Add dox comments. 2002-10-10 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/acknowledge.dox: Add cross references. 2002-10-08 Joerg Wunsch * doc/api/using-tools.dox: New file. * doc/examples/demo/demo.dox: Change title. * doc/api/faq.dox: describe register usage. * doc/register-usage.txt: file gone, it's in the FAQ now. * doc/api/Makefile.am: wire the new using-tools.dox into the make infrastructure. 2002-10-07 Joerg Wunsch * doc/examples/demo/demo.fig: Introduce R2. * doc/examples/demo/demo.dox: Document R2. 2002-10-04 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Bump version. * doc/api/faq.dox: Add io port passing entry. 2002-10-03 Joerg Wunsch * doc/examples/demo/demo.dox: Fix Ted's FIXME. 2002-10-01 Theodore A. Roth * doc/TODO: Updated. * doc/api/Makefile.am: Add using-avrprog.dox. * doc/api/tools-install.dox: Add ref to using-avrprog.dox. * doc/api/using-avrprog.dox: New file. 2002-10-01 Marek Michalkiewicz * include/avr/iom163.h: Add SIG_COMPARATOR, fix SIG_2WIRE_SERIAL. * include/avr/iotn26.h: New file, from Stefan Swanepoel . * doc/api/main_page.dox: Add attiny26 as supported. * NEWS: Add tiny26 to new device list. * configure.in (AM_INIT_AUTOMAKE): Bump version. (AVR_CRT_TINY): Add crttn26.o. 2002-09-30 Theodore A. Roth * doc/api/main_page.dox: Add atmega16 as supported. 2002-09-30 Theodore A. Roth * libc/stdlib/malloc.c: Quell compiler warning. 2002-09-30 Theodore A. Roth * include/avr/io1200.h: Generate compiler warning if not included from avr/io.h. * include/avr/io2313.h: Ditto. * include/avr/io2323.h: Ditto. * include/avr/io2333.h: Ditto. * include/avr/io2343.h: Ditto. * include/avr/io4414.h: Ditto. * include/avr/io4433.h: Ditto. * include/avr/io4434.h: Ditto. * include/avr/io76c711.h: Ditto. * include/avr/io8515.h: Ditto. * include/avr/io8534.h: Ditto. * include/avr/io8535.h: Ditto. * include/avr/ioat94k.h: Ditto. * include/avr/iom103.h: Ditto. * include/avr/iom128.h: Ditto. * include/avr/iom16.h: Ditto. * include/avr/iom161.h: Ditto. * include/avr/iom162.h: Ditto. * include/avr/iom163.h: Ditto. * include/avr/iom169.h: Ditto. * include/avr/iom323.h: Ditto. * include/avr/iom8.h: Ditto. * include/avr/iotn11.h: Ditto. * include/avr/iotn12.h: Ditto. * include/avr/iotn15.h: Ditto. * include/avr/iotn22.h: Ditto. * include/avr/iotn28.h: Ditto. 2002-09-30 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * doc/Makefile.am: Move examples to SUBDIRS. * doc/api/Makefile.am: New rules for demo project. * doc/api/doxygen.config.in: Add paths to demo project. * doc/examples/Makefile.am: New file. * doc/examples/demo/Makefile: New file. * doc/examples/demo/demo.c: New file. * doc/examples/demo/demo.dox: New file. * doc/examples/demo/demo.fig: New file. 2002-09-30 Theodore A. Roth * NEWS: Add mega16 to new device list. 2002-09-29 Marek Michalkiewicz * configure.in (AVR_CRT_MEGA): Add crtm16.o. * include/avr/iom16.h: New, from Magnus Johansson . 2002-09-29 Marek Michalkiewicz * include/avr/delay.h: New. * configure.in (AM_INIT_AUTOMAKE): Update version. 2002-09-29 Reiner Patommel * libm/fplib/atan.S, libm/fplib/atan2.S: Fix swapped atan2() arguments to match C standards. 2002-09-27 Theodore A. Roth * libc/stdlib/malloc.c: Remove cast from STACK_POINTER macro. 2002-09-27 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * include/setjmp.h: Add extern "C" for C++ usage. 2002-09-25 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * doc/api/tools-install.dox: Move note about reconf and cvs up. 2002-09-17 Marek Michalkiewicz * include/avr/sfr_defs.h (_VECTOR): Move above #ifndef __ASSEMBLER__. 2002-09-11 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * doc/api/faq.dox: Cleanups and add examples. 2002-09-11 Theodore A. Roth * doc/TODO: Remove include/stdlib.h. * include/stdlib.h: Misc cleanups. 2002-09-10 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. 2002-09-09 Theodore A. Roth * libc/string/strstr.S: Fix dox (s/needle/s2/ and s/haystack/s1/). 2002-09-09 Joerg Wunsch * doc/api/faq.dox: add three subsections. 2002-09-09 Theodore A. Roth * doc/TODO: Added note about testsuite. 2002-09-09 Joerg Wunsch * include/stdlib.h: improve grouping for old doxygen versions. 2002-09-09 Joerg Wunsch * libc/stdlib/malloc.c: use _SFR_IO16() around the SP address. 2002-09-09 Joerg Wunsch * include/stdlib.h: rename DTOSTRE_* into DTOSTR_*. * libm/fplib/dtostre.S: rename DTOSTRE_* into DTOSTR_*. 2002-09-08 Joerg Wunsch * include/stdlib.h: document this file. * libm/fplib/dtostre.S: use . 2002-09-08 Joerg Wunsch * libm/fplib/dtostre.S: another leading "0" fix. 2002-09-07 Joerg Wunsch * libm/fplib/dtostre.S: don't print "." iff prec == 0. 2002-09-07 Joerg Wunsch * libm/fplib/fplib.inc: introduce FPMOV and FPLOAD. * libm/fplib/dtostre.S: use FPMOV, FPLOAD, and XCALL. 2002-09-06 Joerg Wunsch * libm/fplib/dtostre.S: fix numerous bugs and nits. 2002-09-04 Theodore A. Roth * doc/TODO: Add what needs to be doxumented still. 2002-09-04 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * doc/TODO: Add note about __ prefix of args in dox. * include/setjmp.h: Add dox comments. 2002-09-03 Joerg Wunsch * doc/api/Makefile.am: implement --enable-versioned-doc * configure.in: implement --enable-versioned-doc 2002-09-02 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * NEWS: Note mega169 as new supported device. * doc/api/main_page.dox: Add list of supported devices. 2002-08-31 Marek Michalkiewicz * configure.in (AM_INIT_AUTOMAKE): Update version. (AVR_CRT_MEGA): Add crtm169.o. * include/avr/iom169.h: New file. * include/avr/iom323.h: Fix typo (SIG_INTERRUPT3 -> 2). 2002-08-30 Theodore A. Roth * doc/api/inline_asm.dox: Remove _PC_ from dox. It doesn't seem to be available to the user. 2002-08-30 Theodore A. Roth * doc/TODO: Updated. * doc/api/faq.dox: Remove C example for .init1; refer to sections dox. * doc/api/sections.dox: Remove faq_startup ref. Add note about -Wl,-Tdata,. Add explanation of ',"ax",@progbits'. 2002-08-30 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * doc/api/Makefile.am: Add sections.dox. * doc/api/sections.dox: New file. 2002-08-29 Theodore A. Roth * doc/api/faq.dox: Move asm faq to faq dox. * doc/api/inline_asm.dox: Move asm faq to faq dox. * configure.in(AM_INIT_AUTOMAKE): Bump version. 2002-08-29 Joerg Wunsch * doc/api/faq.dox: 16-bit timer IO registers and interrupts. * doc/api/sfr.dox: xref to the FAQ. 2002-08-28 Joerg Wunsch * doc/api/faq.dox: Mention C++ support. 2002-08-28 Joerg Wunsch * libc/stdlib/malloc.c: Fix STACK_POINTER(). 2002-08-28 Theodore A. Roth * NEWS: Updated with summary of change log. 2002-08-28 Theodore A. Roth * include/avr/iom128.h: Sync up io register bit names with latest datasheet (2467E-AVR-05/02). [modification of submission by Svein E. Seldal ]. 2002-08-28 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version * doc/api/interrupts.dox: Fix typo (s/Overflow2/Overflow3/). 2002-08-27 Theodore A. Roth * doc/TODO: Updated. 2002-08-27 Theodore A. Roth * include/avr/iom128.h: Updated IO register names to match latest datasheet from Atmel. (modified submission from Svein E. Seldal ) * configure.in(AM_INIT_AUTOMAKE): Bump version. 2002-08-22 Theodore A. Roth * common/macros.inc: Use instead of . * doc/api/faq.dox: Use instead of . * include/eeprom.h: Add deprecated #warning. * include/ina90.h: Add deprecated #warning. * include/interrupt.h: Add deprecated #warning. * include/io.h: Add deprecated #warning. * include/pgmspace.h: Add deprecated #warning. * include/progmem.h: Add deprecated #warning. * include/sig-avr.h: Add deprecated #warning. * include/timer.h: Add deprecated #warning. * include/twi.h: Add deprecated #warning. * include/wdt.h: Add deprecated #warning. * include/avr/eeprom.h: Use instead of . * include/avr/ina90.h: Use instead of . * include/avr/interrupt.h: Use instead of . * include/avr/pgmspace.h: Use instead of . Same for and * include/avr/timer.h: Use instead of . * include/avr/wdt.h: Use instead of . 2002-08-23 Joerg Wunsch * include/avr/eeprom.h: document. 2002-08-23 Joerg Wunsch * doc/api/acknowledge.dox: Mention Ted's work. 2002-08-22 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. 2002-08-22 Theodore A. Roth * doc/api/sfr.dox: Reformat paragraphs that are too wide. * include/avr/sfr_defs.h: Reformat paragraphs that are too wide. Added cvs Id keyword. 2002-08-22 Theodore A. Roth * doc/api/sfr.dox: Grammar cleanups. * include/avr/sfr_defs.h: Make Marek's notes into dox. Added compiler note to _BV(). Added note about switched arg order for outb()/outw(). Documented deprecated macros. 2002-08-21 Joerg Wunsch * doc/api/Makefile.am * doc/api/sfr.dox * include/avr/io.h * include/avr/sfr_defs.h: document . 2002-08-21 Theodore A. Roth * doc/api/inline_asm.dox: Move old history into non-doxy comment. Change GCC-AVR to AVR-GCC. Add note about new location. 2002-08-21 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * doc/api/inline_asm.dox: Removed `n' and `v' constraints from table. Grammar fixes. Add link to gcc online docs. 2002-08-16 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * doc/api/Makefile.am(EXTRA_DIST): Add tools-install.dox file. * doc/api/dox_html_header: Fix title. * doc/api/tools.dox: New file. 2002-08-14 Theodore A. Roth * doc/api/inline_asm.dox: Fixed variable name in clobber section. New section C stubs added. (thanks to Harald Kipp) 2002-08-14 Theodore A. Roth * doc/api/faq.dox: Minor dox update. * doc/api/inline_asm.dox: Minor dox update. * doc/api/main_page.dox: Minor dox update. 2002-08-13 Theodore A. Roth * doc/api/doxygen.config.in: Updated to use doxygen-1.2.17. 2002-08-13 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * doc/api/acknowledge.dox: Minor updates. 2002-08-13 Theodore A. Roth * libc/string/memset.S: Fix dox comment (s/src/dest/). 2002-08-12 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. 2002-08-12 Joerg Wunsch * crt1/gcrt1.S: avr-gcc >= 3.3 is required. * avr-libc.spec.in: avr-gcc >= 3.3 is required. 2002-08-09 Joerg Wunsch * doc/api/faq.dox: add a subsection about _BV(). 2002-08-09 Joerg Wunsch * include/avr/io.h: add documentation. 2002-08-09 Joerg Wunsch * doc/api/Makefile.am: Black magic to split a long table. * doc/api/interrupts.dox: minor changes and additions. 2002-08-09 Joerg Wunsch * domake: Allow for environmental override of ${MAKE}. 2002-08-09 Joerg Wunsch * reconf: Extend the automake/autoconf checks to allow for customized executable names for the versions required. 2002-08-09 Theodore A. Roth * reconf: Check for correct versions of automake/autoconf. 2002-08-09 Theodore A. Roth * .cvsignore: New file. * crt1/.cvsignore: New file. * doc/.cvsignore: New file. * doc/api/.cvsignore: New file. * libc/.cvsignore: New file. * libc/misc/.cvsignore: New file. * libc/pmstring/.cvsignore: New file. * libc/stdlib/.cvsignore: New file. * libc/string/.cvsignore: New file. * libm/.cvsignore: New file. * libm/fplib/.cvsignore: New file. 2002-08-09 Theodore A. Roth * doc/api/Makefile.am(EXTRA_DIST): Add new dox files. * doc/api/interrupts.dox: New file. * doc/api/acknowledge.dox: New file. * include/avr/interrupt.h: Added doxy comments. * include/avr/signal.h: Updated doxy comments. 2002-08-05 Joerg Wunsch * doc/api/Makefile.am: restructure to make the docs targets depend on actual files as opposed to .phony targets. 2002-08-05 Joerg Wunsch * doc/api/faq.dox: add Q/A about early initialization. 2002-08-05 Theodore A. Roth * libc/pmstring/strcasecmp_P.S: remove redundant sentence about return value. 2002-08-05 Joerg Wunsch * doc/api/inline_asm.dox: bump nesting level by one to make TOC display look more natural in PDF. 2002-08-05 Joerg Wunsch * configure.in: Make HTML/PS/PDF generation configurable. * doc/api/Makefile.am: Make documentation generation and installation configurable, more cleanup, make PDF generation usable with doxygen 1.2.17. 2002-08-05 Theodore A. Roth * libc/string/memccpy.S: Doxy cleanups. * libc/string/memchr.S: Doxy cleanups. * libc/string/memcmp.S: Doxy cleanups. * libc/string/memcpy.S: Doxy cleanups. * libc/string/memmove.S: Doxy cleanups. * libc/string/memset.S: Doxy cleanups. * libc/string/strcasecmp.S: Doxy cleanups. * libc/string/strchr.S: Doxy cleanups. * libc/string/strcmp.S: Doxy cleanups. * libc/string/strlen.S: Doxy cleanups. * libc/string/strlwr.S: Doxy cleanups. * libc/string/strnlen.S: Doxy cleanups. * libc/string/strrchr.S: Doxy cleanups. 2002-08-05 Theodore A. Roth * libc/string/strcpy.S: Fix incorrect reference in dox to strncpy(). 2002-08-05 Theodore A. Roth * doc/api/Makefile.am(install-dox-html): Fix to install .js and .png files. 2002-08-03 Theodore A. Roth * configure.in(AM_INIT_AUTOMAKE): Bump version. * configure.in: Add AVR_LIBC_USER_MANUAL. * doc/api/Makefile.am: Use AVR_LIBC_USER_MANUAL instead of hard coded name. * doc/api/doxygen.config.in: Ditto. 2002-08-03 Theodore A. Roth * doc/api/Makefile.am: Change osavr -> avr-libc. * doc/api/doxygen.config.in: Ditto. 2002-08-03 Theodore A. Roth * doc/api/Makefile.am: Remove use of directories as targets. * doc/api/Makefile.am: Remove use of `${MAKE} -C` to improve portability. * doc/api/doxygen.config.in: Changed html and latex output dirs to avr-libc-api and latex_src respectively. 2002-08-02 Theodore A. Roth * Makefile.am: Make doc subdir conditional. * configure.in: Fix so docs are only built once. 2002-08-02 Theodore A. Roth * doc/api/Makefile.am(clean-local): Added man dir for cleanup. * doc/api/Makefile.am: Fixed circular dependancy for dox-html <-> html. 2002-07-31 Theodore A. Roth * crt1/gcrt1.S: Allow gcc versions >= 3.2. * libc/pmstring/strncpy_P.S: Fix typo is doxy comment. 2002-07-31 Joerg Wunsch * doc/api/inline_asm.dox: fix hrefs. 2002-07-29 Joerg Wunsch * doc/api/Makefile.am: Add faq.dox file. * doc/api/faq.dox: New file. 2002-07-26 Theodore A. Roth * doc/api/Makefile.am(dox-pdf): Use ${MAKE} instead of make. * doc/api/Makefile.am(dox-ps): Use ${MAKE} instead of make. 2002-07-25 Theodore A. Roth * doc/api/Makefile.am(EXTRA_DIST): Add *.dox files. * doc/api/doxygen.config.in: Config tweaks. * doc/api/main_page.dox: New file. * doc/api/inline_asm.dox: New file. (Thanks to Harald Kipp) * include/inttypes.h: Updated comments for doxygen. * include/string.h: Updated comments for doxygen. * include/avr/signal.h: Updated comments for doxygen. * libc/string/memccpy.S: Updated comments for doxygen. * libc/string/memchr.S: Updated comments for doxygen. * libc/string/memcmp.S: Updated comments for doxygen. * libc/string/memcpy.S: Updated comments for doxygen. * libc/string/memmove.S: Updated comments for doxygen. * libc/string/memset.S: Updated comments for doxygen. * libc/string/strcasecmp.S: Updated comments for doxygen. * libc/string/strcat.S: Updated comments for doxygen. * libc/string/strchr.S: Updated comments for doxygen. * libc/string/strcmp.S: Updated comments for doxygen. * libc/string/strcpy.S: Updated comments for doxygen. * libc/string/strlcat.c: Updated comments for doxygen. * libc/string/strlcpy.c: Updated comments for doxygen. * libc/string/strlen.S: Updated comments for doxygen. * libc/string/strlwr.S: Updated comments for doxygen. * libc/string/strncasecmp.S: Updated comments for doxygen. * libc/string/strncat.S: Updated comments for doxygen. * libc/string/strncmp.S: Updated comments for doxygen. * libc/string/strncpy.S: Updated comments for doxygen. * libc/string/strnlen.S: Updated comments for doxygen. * libc/string/strrchr.S: Updated comments for doxygen. * libc/string/strrev.S: Updated comments for doxygen. * libc/string/strstr.S: Updated comments for doxygen. * libc/string/strupr.S: Updated comments for doxygen. * libm/fplib/dtostrf.S: Change comment so doxygen isn't confused. * include/avr/pgmspace.h: Updated comments for doxygen. * libc/pmstring/memcpy_P.S: Updated comments for doxygen. * libc/pmstring/strcasecmp_P.S: Updated comments for doxygen. * libc/pmstring/strcat_P.S: Updated comments for doxygen. * libc/pmstring/strcmp_P.S: Updated comments for doxygen. * libc/pmstring/strcpy_P.S: Updated comments for doxygen. * libc/pmstring/strlen_P.S: Updated comments for doxygen. * libc/pmstring/strncasecmp_P.S: Updated comments for doxygen. * libc/pmstring/strncmp_P.S: Updated comments for doxygen. * libc/pmstring/strncpy_P.S: Updated comments for doxygen. 2002-07-16 Theodore A. Roth * Makefile.am: Integrate doxygen in to build system. * configure.in: Integrate doxygen in to build system. * configure.in (AM_INIT_AUTOMAKE): Updated version. * doc/Makefile.am: New file. * doc/api/Makefile.am: New file. * doc/api/dox.css: New file. * doc/api/dox_html_footer: New file. * doc/api/dox_html_header: New file. * doc/api/doxygen.config.in: New file. 2002-07-14 Marek Michalkiewicz * configure.in (AM_INIT_AUTOMAKE): Update version. (AVR_CRT_MEGA): Add crtm162.o. * include/avr/iom162.h: New file. * ChangeLog: Add 2002-06-30 entry that got lost. 2002-07-08 Theodore A. Roth * avr-libc.spec.in: Updated License and URL info. 2002-07-08 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Updated version. * configure.in (AC_OUTPUT): Intgrated rpm spec file into build. * Makefile.am: Intgrated rpm spec file into build. * avr-libc.spec.in: New file. 2002-07-05 Theodore A. Roth * configure.in (AM_INIT_AUTOMAKE): Updated version. 2002-06-30 Marek Michalkiewicz * libm/fplib/*.S: Move constant tables to the .progmem.gcc_fplib section (guaranteed below 64K even on 128K devices). * Move AVR-specific include/*.h files to include/avr/ . * include/avr/crc16.h: New file. * Fix wdt.h, should work on ATmega128 now. * LICENSE: Remove the third restriction. 2002-06-20 Marek Michalkiewicz * crt1/gcrt1.S: Check GCC version (3.2 required, 3.1 will not work). Set __heap_end to 0 so the symbol is defined for malloc(). * include/stdlib.h: Declare __malloc_margin, __malloc_heap_start and __malloc_heap_end. * include/io*.h: Rename OVR bit to DOR. * include/iom161.h: Define the same bits for both UARTs. Define SPMCR bits. 2002-06-12 Marek Michalkiewicz * crt1/gcrt1.S: Fix bug with interrupt vectors always pointing to the reset address (no __vector_* relocs) on all <=8K chips. Oops. This also restores the "handle unexpected interrupts" feature that was present in the old gcrt1.S - define a "signal" function named __vector_default to handle all interrupts not handled elsewhere. * doc/INSTALL: Update. 2002-06-01 Marek Michalkiewicz * Rewrite gcrt1.S, make use of the new ld scripts that allow inserting user code at various stages of initialization. 2002-05-31 Marek Michalkiewicz * Rewrite I/O access macros so that you can use I/O registers directly in C expressions. See for description. Many files changed, please test - I have tried to maintain some backwards compatibility, but applications (especially assembler sources) will need to be modified. Also check C code for any outb/outw macro calls as now their arguments are in the correct (port, value) order, consistent with C assignment operators. 2002-05-30 Marek Michalkiewicz * Fix multilib build failure (some *.S files) after the 20020529 GCC changes in handling of predefined __AVR_AT*__ preprocessor macros. Do not set AM_CFLAGS in Makefile.am files. Add our own rules that add AVRLIB_ASFLAGS after CFLAGS, so that our -mmcu=atmega103 comes after multilib -mmcu=avr3 (not the other way around), now that the last -mmcu=* option completely overrides any previous one. * Move gcrt1.S from libc/ into a new crt1/ directory. * Move libc/bsd/*.c to libc/stdlib/ and remove libc/bsd/ directory. * Move strlcat.c and strlcpy.c from libc/stdlib/ to libc/string/ . * Add "set -e" and do "make distcheck" in dodist script. * libc/stdlib/malloc.c: New implementation, thanks to Joerg Wunsch. 2002-05-26 Marek Michalkiewicz The patch mentioned below is now in the binutils CVS tree. * Add copyright notices to all files in preparation for moving the project to savannah.gnu.org. Thanks to Theodore A. Roth for help with this boring task... * Remove libc/gnu/ subdir and include/string-avr.h (LGPL). * Update doc/avr-libc-reference.html (string-avr.h gone). 2002-05-11 Marek Michalkiewicz WARNING: Test release - for use only with current CVS GCC and binutils with applied patch from http://www.amelek.gda.pl/avr/test/avr-binutils-patch-20020511.gz * configure.in: Default to avr target, enable ATmega128 support. * include/io-avr.h: More known devices. * include/pgmspace.h (strncasecmp_P): Add missing third argument. * include/string.h (strlcat, strlcpy): Declare. * libc/gcrt1.S (__stack): Weak, default to RAMEND from . * libc/stdlib/Makefile.am (lib_a_c_sources): Update. * libc/stdlib/strlcat.c, libc/stdlib/strlcpy.c: New. 2002-02-03 Marek Michalkiewicz * Add dtostrf(), optimize atol(), itoa(), utoa() from Reiner Patommel. * libc/stdlib/ctype.S (isalnum): Bugfix from Jens Meyer. * include/iomactos.h: change constraints, add inw/outw, clean up. * doc/avr-libc-reference.html: Update. 2002-01-15 Marek Michalkiewicz * Add ltoa() and ultoa(), thanks to Reiner Patommel. * Optimize parity_even_bit, thanks to Greg Smith. * doc/avr-libc-reference.html: Fix CR/LF newlines. Sun Jan 06 00:11:00 2002 Reinhard Jessich * configure.in: Add the "-g" option to AVRLIB_CFLAGS. * reconf: Add "set -x" to see whta is executed. * Makefile.am: Remove the comment about automake 1.4. Sat Dec 29 22:44:00 2001 Reinhard Jessich * Bugfix in configure.in: Now avr-libc can be configured, without a present avr-libc installed. Sat Dec 29 01:29:00 2001 Reinhard Jessich * libm is working with autoconf/automake, too. * Create the new distribution package avr-libc-20011229.tar.gz. Sat Dec 28 23:34:00 2001 Reinhard Jessich * libc is working with autoconf/automake. Sat Dec 22 22:12:00 2001 Reinhard Jessich * First tries to use the autoconf/automake for the building of the avr libc. see doc/CHANGES for old changes (before autoconf/automake) support. avr-libc-1.8.0.orig/ChangeLog-20060000644000000000000000000005115111732702554013214 0ustar 2006-12-31 Joerg Wunsch Fix breakage for strtod() on avr6 architectures caused by calling __prologue_saves__. Fixes bug #18509: strtod.S crashes due to stack problem with atmega 2560 * libm/fplib/strtod.S: pop and restore EIND from the stack before calling __prologue_saves__ on 3-byte PC AVR architectures. * include/avr/io.h: Provide a value for EIND when compiling the library for an avr6 architecture. * include/avr/iomxx0_1.h: Protect the EIND definition from appearing twice in while compiling the library for an avr6 architecture. 2006-12-23 Eric B. Weddington * configure.ac: Add support for ATmega3290P * devtools/gen-avr-lib-tree.sh: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/iom3290p.h (New File): Ditto. 2006-11-30 Anatoly Sokolov * include/avr/iom164.h (SPM_PAGESIZE): Set to 128. * include/avr/iom324.h (SPM_PAGESIZE): Set to 128. Closes savannah bug #18385. 2006-10-09 Eric B. Weddington Fix for bug #17470. * include/avr/power.h: Add API for CLKPR register. 2006-10-08 Joerg Wunsch Submitted by koshchi@shaw.ca: * doc/examples/stdiodemo/defines.h: Explain databits need to be in ascending order. * doc/examples/stdiodemo/hd44780.c: Take care for databits not starting at bit 0. Closes bug #16125: HD44780 data bit assignment restrictive 2006-10-08 Joerg Wunsch * include/compat/deprecated.h: Fix argument order for outp(), add inb() and outb(). Closes bug #16868: depricated.h: outp() arguments order misprint 2006-10-07 Joerg Wunsch * doc/api/tools-install.dox: Update documentation for GCC 4.x, add hint for binutils and GCC "new device" patches, add --prefix to avr-libc configure command, remove UISP, minor addition to avrdude section. Closes bug #17551: Update documentation to point to issues with gcc4.1 2006-09-29 Joerg Wunsch Submitted by Bjoern Haase: * libm/fplib/fp_split.S: Pop 3 bytes from stack on error returns rather than 2 for avr6 architectures. Closes bug #17591: /avr-libc/libm/fplib/fp_split.S error return will fail for 3-Byte PC devices 2006-09-29 Joerg Wunsch * AvrCommon.am (AVRLIB_CFLAGS): Use -gstabs rather than -g here as well, as it's already been in AVRLIB_ASFLAGS. Without that, using a compiler that defaults to DWARF-2 yielded an interesting mix of both, DWARF-2 and stabs debugging information in the library. 2006-09-27 Joerg Wunsch * include/avr/interrupt.h (ISR_ALIAS): Add ISR_ALIAS() macro. Fix doxygen style for the other ISR macros. Closes bug #17608: Add ISR_ALIAS() to avr/interrupt.h 2006-09-20 Eric B. Weddington * configure.ac (CHECK_PNG_UTILS): Fix string echo for checking pnmtopng. Fix check for pngtopnm and pnmtopng programs. Add self to authors. * doc/api/doxygen.config.in (IMAGE_PATH): Add correct directories. * doc/api/doxygen.config.in (LATEX_BATCHMODE): Change to yes so latex will run in a batch mode and not query the user if something is amiss. * doc/api/tools-install.dox: Remove doxygen warning. * doc/examples/asmdemo/asmdemo.dox: Ditto. * doc/api/Makefile.am (fix_png): Use the actual RGB numbers instead of the color name in case the rgb.txt file cannot be found. * doc/api/Makefile.am (doxygen.confg): Remove the dependency on $(top_srcdir)/stamp-h1 as there is no rule in this Makefile to build it, which causes an error. The rule is located in the top level Makefile. 2006-09-14 Eric B. Weddington * doc/api/faq.dox: Add question about why there are five different linker scripts. 2006-09-13 Eric B. Weddington Patch #4461 by Anatoly Sokolov * configure.ac: Add support for new devices: ATmega2560, ATmega2561. * devtools/gen-avr-lib-tree.sh: Ditto. * doc/api/main_page.dox: Ditto. * doc/api/using-tools.dox: Ditto. * include/avr/Makefile.am: Ditto. * include/avr/io.h: Ditto. * include/avr/wdt.h: Ditto. * include/avr/iom2560.h (New File): Ditto. * include/avr/iom2561.h (New File): Ditto. 2006-09-11 Eric B. Weddington * bootstrap: Allow automake version 1.8.x in addition to 1.9.x. automake 1.8.2 is available on MinGW/MSYS and with autoconf 2.59 successfully builds avr-libc 1.4 branch. 2006-09-01 Eric B. Weddington Fix for bug #15512. * include/avr/boot.h: Add more documentation describing that global interrupts are not disabled for these macros. * NEWS: Update fixed bug list. 2006-09-01 Eric B. Weddington Additional fix for bug #16411. * include/avr/interrupt.h: Conditionally compile 'used' and 'externally_visible' attributes on interrupt macros based on compiler version. * include/compat/deprecated: Ditto. 2006-08-30 Joerg Wunsch * include/avr/sleep.h: Fix the entry for the ATtiny2313, the revision I datasheet was indeed correct. 2006-08-29 Joerg Wunsch Add the new "asmdemo" example. It demonstrates how C and assembly source files could be used within one project. * doc/examples/asmdemo: (New directory.) * doc/examples/asmdemo/asmdemo.c: (New file.) asmdemo implementation. * doc/examples/asmdemo/isrs.S: (Ditto.) * doc/examples/asmdemo/project.h: (Ditto.) * doc/examples/asmdemo/Makefile: (Ditto.) * doc/examples/asmdemo/asmdemo.dox: (New file.) Document the asmdemo. * doc/examples/Makefile.am: Wire the asmdemo into the build and distribution process. * doc/examples/all-demos.dox: Add a paragraph about the purpose of this new demo, including a reference to it. 2006-08-28 Eric B. Weddington Additional fix for bug #16411. * include/avr/interrupt.h: Add the 'externally_visible' attribute on all interrupt service routine macros. * include/compat/deprecated.h: Add the 'externally_visible' attribute on the INTERRUPT macro. 2006-08-28 Joerg Wunsch * doc/examples/demo/Makefile: Catch binutils 2.17 flagging an error for the empty .eeprom section. * doc/examples/demo/demo.dox: Explain binutils 2.17's changed behaviour in avr-objcopy when trying to copy an empty .eeprom section. 2006-08-24 Eric B. Weddington Fix for bug #16411. * include/avr/interrupt.h: Add the 'used' attribute on all interrupt service routine macros. * include/compat/deprecated.h: Add the 'used' attribute on the INTERRUPT macro. * NEWS: Add to fixed bug list. 2006-08-10 Joerg Wunsch Fixes to the HD44780 driver; thanks to Knut Schwichtenberg for pointing this out, and helping in testing it. * doc/examples/stdiodemo/hd44780.c: Fix timing issues. The values read back from the HD44780 need to be sampled while E is asserted. * doc/examples/stdiodemo/stdiodemo.dox: Document the new approach of the E pulse generation. 2006-07-25 Eric B. Weddington * include/avr/power.h: New file. Provides a Power Management API. * include/avr/sleep.h: Fix grammar error in doxygen comment. * NEWS: New Power Management API. 2006-07-18 Joerg Wunsch * doc/api/faq.dox (faq_spman): New entry about the SP manipulation in function prologues/epilogues. 2006-07-09 Joerg Wunsch Submitted by Guohui Wang : * include/avr/wdt.h: Fix spelling error for ATmega324P. Closes bug #17068. 2006-06-24 Anatoly Sokolov * include/avr/interrupt.h (EMPTY_INTERRUPT): Add 'signal' attribute to function prototype. Closes savannah bug #16434. 2006-06-24 Anatoly Sokolov * include/avr/iousbxx6_7.h (PRST1, SOFEN): Define. 2006-06-11 Joerg Wunsch Submitted by David Bourgeois : * doc/api/faq.dox (faq_rom_array): Fix a typo. 2006-05-23 Anatoly Sokolov * include/avr/iotnx5.h (LSM): Remove comment. 2006-05-23 Anatoly Sokolov * include/avr/eeprom.h: Turn #if on __AVR_HAVE_MOVW__ macro into #if defined(). This makes it -Wundef safe. 2006-05-17 Joerg Wunsch * include/avr/sfr_defs.h: Ensure _SFR_ASM_COMPAT is defined before it is used. This makes it -Wundef safe. 2006-05-03 Anatoly Sokolov * include/avr/iocanxx.h (CANSIT): Add. 2006-04-29 Anatoly Sokolov * include/avr/sfr_defs.h (_MMIO_DWORD, _SFR_MEM32, _SFR_DWORD): Add. * include/avr/iocanxx.h (CANIDT, CANIDM): Add. 2006-04-26 Joerg Wunsch * include/avr/eeprom.h: Use __asm__ in place of asm. Closes bug #16441: eeprom.h should use __asm__. 2006-04-22 Anatoly Sokolov * configure.ac: Add tests for the ATmega165P/169P support. * devtools/gen-avr-lib-tree.sh: Add support for ATmega165P/169P. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * include/avr/iom165p.h: New file. * include/avr/iom169p.h: New file. * include/avr/Makefile.am: Include new files. * doc/api/main_page.dox: Document support for ATmega165P/169P. * doc/api/using-tools.dox: (Ditto.) 2006-04-19 Joerg Wunsch Submitted by lx_b@gmx.at: * include/avr/interrupt.h: improve C++ robustness of ISR declarations. Closes savannah bug #15732. 2006-04-19 Joerg Wunsch Submitted by Glenn Maynard : * include/util/crc16.h (_crc16_update): add equivalent C implementation as documentation. Closes savannah bug #16260. 2006-04-19 Joerg Wunsch * doc/examples/demo/iocompat.h: Rename ATmega164/324 to ATmega164P/324P, add support for ATmega644P. * doc/examples/demo/Makefile: (Ditto.) 2006-04-17 Joerg Wunsch * doc/examples/demo/iocompat.h: Add support for ATmega640/1280/1281. * doc/examples/demo/Makefile: (Ditto.) 2006-04-13 Anatoly Sokolov * include/avr/iotn2313.h(SPMEN, SELFPRGEN): Add. 2006-04-01 Anatoly Sokolov * configure.ac: Add tests for the ATmega644P support. Rename ATmega164/ATmega324 to ATmega164P/ATmega324P. * devtools/gen-avr-lib-tree.sh: Add support for ATmega644P. Rename ATmega164/ATmega324 to ATmega164P/ATmega324P. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * doc/api/main_page.dox: Document support for ATmega644P. Rename ATmega164/ATmega324 to ATmega164P/ATmega324P. * doc/api/using-tools.dox: (Ditto.) 2006-03-24 Anatoly Sokolov * Makefile.am (DIST_SUBDIRS): Add 'devtools'. * configure.ac (AC_CONFIG_FILES): Add 'devtools/Makefile'. * devtools/.cvsignore: New file. * devtools/Makefile.am; New file. [Fixed bug #16039] 2006-03-21 Anatoly Sokolov * configure.ac: add tests for the AT90USB646/647/1286/1287 support. * devtools/gen-avr-lib-tree.sh: add support for AT90USB646/647/1286/1287. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * include/avr/iousb646.h: new file. * include/avr/iousb647.h: new file. * include/avr/iousb1286.h: new file. * include/avr/iousb1287.h: new file. * include/avr/iousbxx6_7.h: new file. * include/avr/Makefile.am: include new files. * doc/api/main_page.dox: Document support for AT90USB646/647/1286/1287. * doc/api/using-tools.dox: (Ditto.) 2006-03-19 Joerg Wunsch Submitted by Jeff Dombach: * include/avr/iomxx0_1.h: Fix bit name PRUSART3. 2006-03-14 Anatoly Sokolov * include/avr/iom169.h(LCDBD, LCDCCD): Add. [Add support ATmega169 Rev. F device] 2006-03-14 Anatoly Sokolov * include/avr/iom165.h: Add 'PINxy', 'DDxy' and 'Pxy' bits. * include/avr/iom325.h: (Ditto.). * include/avr/iom3250.h: (Ditto.). * include/avr/iom329.h: (Ditto.). * include/avr/iom3290.h: (Ditto.). * include/avr/iom645.h: (Ditto.). * include/avr/iom6450.h: (Ditto.). * include/avr/iom649.h: (Ditto.). * include/avr/iom6490.h: (Ditto.). 2006-03-10 Anatoly Sokolov * include/avr/iomxx0_1.h: Rename port pins from PORTxy to Pxy. * include/avr/portpins.h: Add PORTHy, PORTJy, PORTKy and PORTHLy. [Fixed bug #16039] 2006-03-09 Joerg Wunsch * include/avr/boot.h: Do not depend on __USING_MINT8 anymore. 2006-03-07 Joerg Wunsch Notified by Peter Schrepfer: * doc/examples/demo/iocompat.h: Fix OCR1A location for ATmega16/32 (broken in rev 1.2). 2006-03-06 Anatoly Sokolov * libc/misc/mul10.S: Use X_movw. 2006-03-04 Anatoly Sokolov * libm/fplib/fplib.inc (mLPMRdZpp, LPMRdZpp): Delete. * libm/fplib/fp_flashconst.S: Use X_lpm. * libm/fplib/fp_powerseries.S: (Ditto.). 2006-03-04 Anatoly Sokolov * common/macros.inc (X_lpm): Add. (Contributed by Dmitry Xmelkov.) (LOAD_X_CONST, LPM_R0_ZP): Delete. * libc/pmstring/memcpy_P.S: Use X_lpm. * libc/pmstring/strcasecmp_P.S: (Ditto.). * libc/pmstring/strcat_P.S: (Ditto.). * libc/pmstring/strcmp_P.S: (Ditto.). * libc/pmstring/strcpy_P.S: (Ditto.). * libc/pmstring/strlcat_P.S: (Ditto.). * libc/pmstring/strlcpy_P.S: (Ditto.). * libc/pmstring/strlen_P.S: (Ditto.). * libc/pmstring/strncasecmp_P.S: (Ditto.). * libc/pmstring/strncat_P.S: (Ditto.). * libc/pmstring/strncmp_P.S: (Ditto.). * libc/pmstring/strncpy_P.S: (Ditto.). * libc/pmstring/strnlen_P.S: (Ditto.). * libc/pmstring/strstr_P.S: (Ditto.). 2006-03-02 Joerg Wunsch * include/stdio.h: Fix example source code. 2006-02-28 Anatoly Sokolov * include/avr/io.h: Define __AVR_HAVE_LPMX__. * common/macros.inc: Define __AVR_HAVE_LPMX__. (LPM_R0_ZP): Use __AVR_HAVE_LPMX__. * include/avr/pgmspace.h: Use __AVR_HAVE_LPMX__. * libm/fplib/fplib.inc(mLPMRdZpp): Use __AVR_HAVE_LPMX__. 2006-02-26 Anatoly Sokolov * include/avr/io.h: Define __AVR_HAVE_MOVW__. * common/macros.inc: Define __AVR_HAVE_MOVW__. (X_movw): Use __AVR_HAVE_MOVW__. * include/avr/eeprom.h (eeprom_write_word): Use __AVR_HAVE_MOVW__. 2006-02-07 Anatoly Sokolov * libm/fplib/dtostrf.S: Use X_movw when possible. Use RCALL instead XCALL for calling 'pow' and 'ldexp' functions. 2006-02-02 Anatoly Sokolov * include/avr/signal.h: Include file. [Fixed bug #15574] 2006-02-02 Anatoly Sokolov * include/avr/boot.h: Corrected a choice __boot_xxx macros. [Fixed bug #15559] 2006-01-31 Anatoly Sokolov * include/avr/iotnx4.h (GPIOR0): Rename from GPI0R0. * include/avr/iotnx5.h (GPIOR0): (Ditto.). * include/avr/iotnx61.h (GPIOR0): (Ditto.). [Fixed bug #15595] 2006-01-30 Anatoly Sokolov * configure.ac: add tests for the ATmega406 support. * devtools/gen-avr-lib-tree.sh: add support for ATmega406. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * include/avr/iotm406.h: new file. * include/avr/Makefile.am: include new files. * doc/api/main_page.dox: Document support for ATmega406. * doc/api/using-tools.dox: (Ditto.) * xml/patch-headers.py: add ATmega406. * doc/api/vectortable.dox: regenerate using patch-headers.py. 2006-01-29 Anatoly Sokolov * doc/api/main_page.dox: Move AT90CANxxx devices to Misc group. [Fixed bug #15519] * include/avr/iotn2313.h (SIG_OUTPUT_COMPARE0A): Rename from SIG_OUTPUT_COPMARE0A. [Fixed bug #15522] 2006-01-22 Joerg Wunsch Fix bug #15494: Compile warning and errors if compiler flag -Wundef flag specified * include/inttypes.h: turn #if on undefined macros into #ifdef. * include/stdint.h: always define __USING_MINT8 (to 0 or 1). * include/avr/boot.h: use __USING_MINT8 the new way. 2006-01-22 Anatoly Sokolov * include/avr/iotn2313.h (SPM_PAGESIZE): Add. * include/avr/iotn24.h (SPM_PAGESIZE): (Ditto.). * include/avr/iotn25.h (SPM_PAGESIZE): (Ditto.). * include/avr/iotn261.h (SPM_PAGESIZE): (Ditto.). * include/avr/iotn44.h (SPM_PAGESIZE): (Ditto.). * include/avr/iotn45.h (SPM_PAGESIZE): (Ditto.). * include/avr/iotn461.h (SPM_PAGESIZE): (Ditto.). * include/avr/iotn84.h (SPM_PAGESIZE): (Ditto.). * include/avr/iotn85.h (SPM_PAGESIZE): (Ditto.). * include/avr/iotn861.h (SPM_PAGESIZE): (Ditto.). 2006-01-09 Joerg Wunsch * Makefile.am (EXTRA_DIST): add ChangeLog-2005. 2006-01-09 Anatoly Sokolov * libm/fplib/acos.S : Use XCALL/XJMP instead RCALL/RJMP for calling __addsf3/__subsf3/__mulsf3/__divsf3 functions. * libm/fplib/cosh.S : (Ditto.). * libm/fplib/exp.S : (Ditto.). * libm/fplib/fmod.S : (Ditto.). * libm/fplib/fp_cosinus.S : (Ditto.). * libm/fplib/log.S : (Ditto.). * libm/fplib/log10.S : (Ditto.). * libm/fplib/pow.S : (Ditto.). * libm/fplib/sin.S : (Ditto.). * libm/fplib/sinh.S : (Ditto.). * libm/fplib/strtod.S : (Ditto.). * libm/fplib/tan.S : (Ditto.). * libm/fplib/tanh.S : (Ditto.). * libm/fplib/modf.S : Use XCALL/XJMP instead RCALL/RJMP __addsf3/__fixsfsi/__floatsisf functions. * libm/fplib/asin.S : Use RCALL/RJMP instead XCALL/XJMP for calling __fp_nanEDOM/__fp_powerseries functions. * libm/fplib/atan.S : Use RCALL/RJMP instead XCALL/XJMP for calling __fp_inverse/square functions. * libm/fplib/atan2.S : Use RCALL/RJMP instead XCALL/XJMP for calling __fp_nanERANGE/atan functions. 2006-01-06 Joerg Wunsch Submitted by Galen Seitz: * avr-libc.spec.in: Fixed examples installation. 2006-01-06 Joerg Wunsch * doc/examples/Makefile.am: Fix the source directory for example installation so it will work when starting from outside $(top_srcdir). This fixes "make distcheck". * include/avr/pgmspace.h: Add a warning about the _P() functions not working above 64 KB. 2006-01-06 Anatoly Sokolov * /libm/fplib/sqrt.S: Use __addsf3/__divsf3 instead __addsf3x/__divsf3x. 2006-01-06 Anatoly Sokolov (Contributed by Dmitry Xmelkov.) * libm/fplib/ldexp.S: Fix error if 'exp' argument > 32640. 2006-01-05 Joerg Wunsch * xml/patch-headers.py: add ATtinyX61, catch errors for non-existent ALT_NAME sections in interrupt vector table * doc/api/vectortable.dox: regenerate using patch-headers.py. 2006-01-05 Joerg Wunsch Extend the simple demo project to a boatload full of different AVRs: ATmega164/324/644, ATtiny261/461/861, ATmega165, ATmega169, ATmega325x/645x, ATmega329x/649x * doc/examples/demo/Makefile: Document all supported devices. * doc/examples/demo/demo.c: make variables local to ISR, use TIMER1_PWM_INIT to setup TCCR1A. * doc/examples/demo/demo.dox: Document TIMER1_PWM_INIT, swap notes 2 and 3. * doc/examples/demo/iocompat.h: Add support for all mentioned devices. 2006-01-04 Anatoly Sokolov * configure.ac: add tests for the ATtiny261/461/861 support. * devtools/gen-avr-lib-tree.sh: add support for ATtiny261/461/861. * include/avr/io.h: (Ditto.). * include/avr/wdt.h: (Ditto.). * include/avr/iotn24.h: new file. * include/avr/iotn44.h: new file. * include/avr/iotn84.h: new file. * include/avr/iotnx4.h: new file. * include/avr/Makefile.am: include new files. * doc/api/main_page.dox: Document support for ATtiny261/461/861. * doc/api/using-tools.dox: (Ditto.) 2006-01-03 Joerg Wunsch Changes to the demo projects and their documentation. Partially based on ideas submitted by Mark J Elkins. * doc/examples/Makefile.am: Include largedemo-wiring2.jpg. * doc/examples/all-demos.dox: Document the prerequisites for the demos. * doc/examples/demo/Makefile: Add dependency from iocompat.h. * doc/examples/demo/demo.c: Port the simple demo to ATmega8515, ATmega8535, ATtiny2313, ATtinyX4, ATtinyX5, and ATtiny26. * doc/examples/demo/iocompat.h: (Ditto.) * doc/examples/demo/demo.dox: Describe iocompat.h in greater detail, fix some \section statements, add section with reference to source code. * doc/examples/largedemo/Makefile: Include largedemo-wiring2.jpg. * doc/examples/largedemo/largedemo-setup.jpg: Don't use the "squid" cable as it is not part of the STK500 (but of the JTAG ICE), use jumper cables instead. * doc/examples/largedemo/largedemo-wiring.jpg: (Ditto.) * doc/examples/largedemo/largedemo.dox: (Ditto.) * doc/examples/largedemo/largedemo.c: Fix a bug that caused the PWMDDR to be clobbered for ATmega16 MCUs so LED1 and 2 did not work. * doc/examples/stdiodemo/stdiodemo.dox: Add comment about the V5 pin on the LCD. * doc/examples/largedemo/largedemo-wiring2.jpg: New file. 2006-01-03 Joerg Wunsch * include/avr/iotnx4.h: Fix the spelling of the OCR1A/B registers. For older changes see ChangeLog-2005 avr-libc-1.8.0.orig/avr-libc.spec.in0000644000000000000000000001422511732702554014036 0ustar ## -*- mode: rpm-spec; -*- ## ## ## Copyright (c) 2004 Theodore A. Roth ## All rights reserved. ## ## Redistribution and use in source and binary forms, with or without ## modification, are permitted provided that the following conditions are met: ## ## * Redistributions of source code must retain the above copyright ## notice, this list of conditions and the following disclaimer. ## ## * Redistributions in binary form must reproduce the above copyright ## notice, this list of conditions and the following disclaimer in ## the documentation and/or other materials provided with the ## distribution. ## ## * Neither the name of the copyright holders nor the names of ## contributors may be used to endorse or promote products derived ## from this software without specific prior written permission. ## ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ## POSSIBILITY OF SUCH DAMAGE. ## ## $Id: avr-libc.spec.in 1037 2006-01-06 22:31:33Z joerg_wunsch $ ## ## @configure_input@ ## %define libc_version @VERSION@ # We don't want rpm stripping any files %define __spec_install_post %{nil} # Don't build the debuginfo rpm %define debug_package %{nil} %define _with_docs 1 %{?_without_docs: %define _with_docs 0} Summary: AVR libc. Name: avr-libc Version: %{libc_version} Release: 1 License: BSD Group: Avr/Development/Tools URL: http://savannah.gnu.org/projects/avr-libc Source0: http://savannah.gnu.org/download/avr-libc/avr-libc-%{version}.tar.bz2 Buildroot: /var/tmp/avr-libc-%{version}-root BuildRequires: gzip avr-gcc >= 3.4.3 %if %{_with_docs} BuildRequires: doxygen >= 1.4.1 tetex transfig %endif Requires: avr-gcc >= 3.4.3 %define ourdocdir %{_defaultdocdir}/%{name} %description Avr-libc is a C library for developing applications for Atmel AVR microcontrollers. %if %{_with_docs} ## The avr-libc-docs subpackage %package docs Summary: Documentation for avr-libc. Group: Avr/Documentation %description docs Documentation for avr-libc in html, postscript and pdf formats. %endif %prep %setup -q %build ./configure \ %if %{_with_docs} --enable-doc --disable-versioned-doc \ %endif --host=avr --build=$(./config.guess) \ --prefix=%{_prefix} --mandir=%{_mandir} --infodir=%{_infodir} make %install rm -rf ${RPM_BUILD_ROOT} mkdir -p ${RPM_BUILD_ROOT}%{_prefix} make prefix=$RPM_BUILD_ROOT%{_prefix} mandir=$RPM_BUILD_ROOT%{_mandir} \ infodir=$RPM_BUILD_ROOT%{_infodir} install # Move/copy files to appropriate directory to workaround the fact that the doc # directive will delete files that are already installed. %if ! %{_with_docs} mkdir -p $RPM_BUILD_ROOT%{ourdocdir} %endif cp AUTHORS ChangeLog* INSTALL LICENSE NEWS README $RPM_BUILD_ROOT%{ourdocdir} %if %{_with_docs} gzip -9 ${RPM_BUILD_ROOT}%{ourdocdir}/man/man3/*.3 %else ## Don't need man script if we aren't installing man pages. rm ${RPM_BUILD_ROOT}%{_bindir}/avr-man %endif %clean rm -rf ${RPM_BUILD_ROOT} %files %defattr(-,root,root) %docdir %{ourdocdir} %{ourdocdir}/AUTHORS %{ourdocdir}/ChangeLog* %{ourdocdir}/INSTALL %{ourdocdir}/LICENSE %{ourdocdir}/NEWS %{ourdocdir}/README %{ourdocdir}/examples %dir %{_prefix}/avr %dir %{_prefix}/avr/lib %dir %{_prefix}/avr/lib/avr3 %dir %{_prefix}/avr/lib/avr4 %dir %{_prefix}/avr/lib/avr5 %dir %{_prefix}/avr/include %dir %{_prefix}/avr/include/avr %dir %{_prefix}/avr/include/compat %dir %{_prefix}/avr/include/util %{_prefix}/avr/lib/lib* %{_prefix}/avr/lib/crt* %{_prefix}/avr/lib/avr3/lib* %{_prefix}/avr/lib/avr3/crt* %{_prefix}/avr/lib/avr4/lib* %{_prefix}/avr/lib/avr4/crt* %{_prefix}/avr/lib/avr5/lib* %{_prefix}/avr/lib/avr5/crt* %{_prefix}/avr/include/*.h %{_prefix}/avr/include/avr/*.h %{_prefix}/avr/include/compat/*.h %{_prefix}/avr/include/util/*.h ## TRoth/20021013: Argh! Why does the fscking %doc directive remove the doc ## dir? That's absolutely stupid. We install things there _assuming_ they ## will stay there. Rpm should _not_ removing things we've installed, but alas ## it does. Be sure to watch the output when you are building the packages. %if %{_with_docs} %files docs %defattr(-,root,root) %{_bindir}/avr-man %doc %{ourdocdir}/avr-libc-user-manual %doc %{ourdocdir}/avr-libc-user-manual.ps %doc %{ourdocdir}/avr-libc-user-manual.pdf %doc %{ourdocdir}/man %endif %changelog * Fri Jan 6 2006 Galen Seitz - Dealt with moved examples directory. * Tue Nov 10 2005 Galen Seitz - Updated to work with latest tools and build procedure. * Tue Oct 21 2003 Theodore Roth - Allow disabling build of docs sub-package with "--without docs". * Thu Apr 17 2003 Theodore Roth - Don't build debuginfo package. - Don't run post install since it strips binaries. * Mon Nov 11 2002 Theodore Roth - Add --enable-doc to configure command. * Sun Oct 13 2002 Theodore Roth - Drop avr-gcc requirement to >= 3.2.75 to allow building snapshot packages. - Add docs sub-package for user manual. * Mon Aug 12 2002 Joerg Wunsch - Require avr-gcc >= 3.3. * Mon Jul 08 2002 Theodore Roth - Integrate spec file into build system. * Fri May 03 2002 Theodore Roth - Added patch to fix timer.h for mega128. * Mon Apr 29 2002 Theodore Roth - Added patch to fix headers. - Fix strncasecmp_P macro in pgmspace.h. * Wed Mar 27 2002 Theodore Roth - Updated avr-gcc dependency to 3.0.4-2. - Fixed up %files section to work with rh-7.1. * Mon Mar 17 2002 Theodore Roth - Initial spec file. avr-libc-1.8.0.orig/Makefile.am0000644000000000000000000000375111732702554013114 0ustar # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 2099 2010-02-11 16:26:06Z joerg_wunsch $ # EXTRA_DIST = \ LICENSE \ bootstrap \ ChangeLog \ ChangeLog-2009 \ ChangeLog-2008 \ ChangeLog-2007 \ ChangeLog-2006 \ ChangeLog-2005 \ ChangeLog-2004 \ ChangeLog-2003 \ ChangeLog-2002 DISTCHECK_CONFIGURE_FLAGS=--host=avr SUBDIRS = common include crt1 libc libm avr doc scripts DIST_SUBDIRS = common include crt1 libc libm avr doc scripts devtools dist-hook: cp avr-libc.spec $(distdir)/avr-libc.spec avr-libc-1.8.0.orig/bootstrap0000755000000000000000000000102511732702554013013 0ustar #! /bin/sh # # $Id: bootstrap 1863 2009-02-04 18:06:24Z arcanum $ # # bootstrap script to build all the *.in files and configure script. # : ${AUTOHEADER="autoheader${AC_VER}"} : ${AUTOCONF="autoconf${AC_VER}"} : ${ACLOCAL="aclocal${AM_VER}"} : ${AUTOMAKE="automake${AM_VER}"} AUTOMAKE="${AUTOMAKE} --foreign --add-missing --copy" export AUTOMAKE AUTOCONF ACLOCAL AUTOHEADER # to see what is executed set -x rm -rf avr/lib ./devtools/gen-avr-lib-tree.sh rm -rf autom4te.cache ${ACLOCAL} ${AUTOHEADER} ${AUTOCONF} ${AUTOMAKE} avr-libc-1.8.0.orig/ChangeLog0000644000000000000000000003303111732702554012624 0ustar 2011-12-29 Joerg Wunsch Released avr-libc-1.7.1. * configure.ac: Bump version. 2011-12-29 Joerg Wunsch * include/avr/pgmspace.h: Do only include the deprecated prog_* typedefs if the user requests this by defining __PROG_TYPES_COMPAT__. If they are generally defined, users are being spammed with warning messages as soon as they include the header file, regardless of whether they want to use these typedefs or not. Also, it's not good style to deprecate the old typedefs but then use them ourselves, so make PGM_P and PGM_VOID_P use the correct definitions. 2011-12-29 Joerg Wunsch * include/avr/iotnx5.h (TIMER1_OVF_vect_num): add definition, replacing the misspelled duplicate for TIMER1_OVF_vect 2011-12-29 Joerg Wunsch * libc/string/strlcat.S: add !__AVR_TINY__ protection 2011-12-28 Joerg Wunsch bug #32773: stdiodemo source code is broken * doc/examples/stdiodemo/lcd.c: pass an argument when calling hd44780_wait_ready() * doc/examples/stdiodemo/Makefile: don't attempt to build the EEPROM load files, as there are now EEPROM data 2011-12-25 Dmitry Xmelkov Fix for bug #34514: misspelled in math.h Thanks to Naotaka Fujita. * include/math.h: Fix typo in documentation. * NEWS: Add to fixed bug list. 2011-12-24 Dmitry Xmelkov Fix for bug #35093. Thanks to Eric Mertens for the patch. * libc/pmstring/strlcat_P.S: Fix X pointer decriment. * libc/string/strlcat.S: Fix X pointer decriment. * tests/regression/bug-35093.c: New file. * NEWS: Add to fixed bug list. 2011-12-09 Joerg Wunsch bug #35020: stdint.h: signed types need explicit "signed" * include/stdint.h: explicitly declare int*_t types as signed 2011-11-02 Eric B. Weddington * include/avr/iox64a1.h (enum TC_EVACT_enum): Fix typo in enum list. Compared to iox128a1.h. Thanks to Francois Costin for the fix. 2011-10-19 Joerg Wunsch * doc/api/faq.dox (faq_assign_chain): Add paragraph about avoiding IO register assignment chains. 2011-10-13 Joerg Wunsch * doc/api/faq.dox (faq_eeprom_corruption): Remove the remarks about the EEPROM being erased pagewise, as they are not true. 2011-09-26 Eric B. Weddington Partial fix for bug #33716. * include/avr/pgmspace.h: Deprecate typedefs with __progmem__ attribute. Document as such. 2011-09-26 Eric B. Weddington Fix for bug #33858. * include/avr/power.h: Add condition for _AVR_ATmega328_. * NEWS: Add to fixed bug list. 2011-09-26 Eric B. Weddington Fix for bug #33920. * include/avr/iotn167.h (ICR): Define ICR to be a word register. * NEWS: Add to fixed bug list. 2011-09-22 Joerg Wunsch * configure.ac (avr_libc_revision, avr_libc_reldate): Bump in preparation of an 1.7.2rc. * configure.ac (avr_libc_revision_suffix): New macro. 2011-09-14 Joerg Wunsch bug #34047: missing math.h include in delay.h * util/delay.h.in: include 2011-09-14 Joerg Wunsch * util/delay.h.in: Fall back to the historic algorithm when compiling within a freestanding environment. 2011-05-23 Joerg Wunsch Reported by Heike C. Zimmerer: patch #7362: iom16a.h: USART vectors inconsistently named for ATmega16A * include/avr/iom16a.h: Add backwards-compatible USART interrupt vector names. 2011-05-23 Joerg Wunsch Reported by Palauqui Georges: patch #7531: Bad name of bit in TCCR0A : WGM0 instead of CTC0 for ATtinyX61 * include/avr/iotnx61.h: Add new name CTC0 for bit 0 of TCCR0A. 2011-05-14 Joerg Wunsch Reported by Markus Lampert: * include/avr/iousbxx2.h: Add new names for CLKSTA, CLKSEL0, CLKSEL1 (old names have been without the `L'). 2011-05-12 Eric B. Weddington Patch #7226. Thanks to Avik Juneja for the patch. * include/avr/iom8u2.h: Add UPOE register definition and bits. * include/avr/power.h: Add ATmega8u2-16u2-32u2 devices in conditional. * NEWS: Add to contributed patches list. 2011-05-11 Eric B. Weddington Fix for bug #33130. Thanks to Antoine Mercier-Linteau for the patch. * doc/examples/twitest/twitest.c: Check for reception of NAK. 2011-05-11 Eric B. Weddington Fix for bug #32650. * include/util/delay.h.in: Add math.h to list of includes. * NEWS: Add to fixed bug list. 2011-05-11 Eric B. Weddington Fix for bug #32675. * include/avr/power.h: Add TIM1 to power_all_enable() and power_all_disable(). * NEWS: Add to fixed bug list. 2011-05-11 Joerg Wunsch * include/avr/pgmspace.h: Reorder so __strlen_P is declared by the time it is attempted to be used. * libc/stdlib/dtostre.c: Part #2 of fix for bug #32988: make `s' a `const char *' as it is pointing to a constant (flash) string. 2011-05-09 Eric B. Weddington Fix for bug #32988. * include/avr/pgmspace.h: Add const keyword to PSTR definition. * NEWS: Add to fixed bug list. 2011-05-09 Eric B. Weddington Fix for bug #33230. * include/avr/sleep.h: Move conditionals for devices attiny261, attiny261a, attiny461, attiny461a, attiny861, attiny861a to correct location. * NEWS: Add to fixed bug list. 2011-05-09 Eric B. Weddington Fix for bug #33238. * include/avr/iom8u2.h: Fix _VECTORS_SIZE value. * include/avr/iom16u2.h: Same. * include/avr/iom32u2.h: Same. * NEWS: Add to fixed bug list. 2011-03-17 Eric B. Weddington * include/avr/iotn11.h: Poison deprecated items. * include/avr/iotn12.h: Same. * include/avr/iotn13.h: Same. * include/avr/iotn15.h: Same. * include/avr/iotn22.h: Same. * include/avr/iotn2313.h: Same. Also: remove duplicate definitions. * include/avr/iotn26.h: Same. * include/avr/iotn28.h: Same. 2011-03-16 Eric B. Weddington * include/avr/iom3290.h: Poison deprecated items. * include/avr/iom32m1.h: Same. * include/avr/iom64.h: Same. * include/avr/iom645.h: Same. * include/avr/iom6450.h: Same. * include/avr/iom649.h: Same. * include/avr/iom8.h: Same. * include/avr/iom8515.h: Same. * include/avr/iom8535.h: Same. * include/avr/iomx8.h: Same. * include/avr/iomxx4.h: Same. * include/avr/iomxx0_1: Same. Also add missing vector number definitions. 2011-03-15 Eric B. Weddington * include/avr/iom323.h: Poison deprecated items. * include/avr/iom325.h: Same. * include/avr/iom3250.h: Same. * include/avr/iom329.h: Same. 2011-03-08 Eric B. Weddington * include/avr/iom32.h: Poison deprecated items. 2011-03-08 Anitha Boyapati Fix for bug #32698. * include/avr/power.h: Fix #endif error for Xmega A series. 2011-03-06 Eric B. Weddington * include/avr/iom163.h: Poison deprecated items. * include/avr/iom165.h: Same. * include/avr/iom165p.h: Same. * include/avr/iom169.h: Same. * include/avr/iom169p.h: Same. 2011-03-05 Eric B. Weddington * include/avr/iom162.h: Poison deprecated items. 2011-03-05 Eric B. Weddington * include/avr/iom161.h: Poison deprecated items. 2011-03-05 Eric B. Weddington * include/avr/iom16.h: Poison deprecated items. 2011-03-04 Eric B. Weddington * include/avr/iom103.h: Poison deprecated items. 2011-03-04 Eric B. Weddington * include/avr/iom128.h: Poison deprecated items. 2011-03-02 Eric B. Weddington Fix for bug #23234. * include/avr/iousbxx2.h: Add *_vect_num definitions. * include/avr/iousbxx6_7.h: Same. * include/avr/iotnx61.h: Same. * include/avr/iotn43u.h: Same. * include/avr/iotn48.h: Same. * include/avr/iotn88.h: Same. * include/avr/iotnx4.h: Same. * include/avr/iotnx5.h: Same. * include/avr/iotn28.h: Same. * include/avr/iotn26.h: Same. * include/avr/iotn11.h: Same. * include/avr/iotn12.h: Same. * include/avr/iotn13.h: Same. * include/avr/iotn15.h: Same. * include/avr/iotn167.h: Same. * include/avr/iotn22.h: Same. * include/avr/iotn2313.h: Same. * include/avr/iom103.h: Same. * include/avr/iom128.h: Same. * include/avr/iom1284.h: Same. * include/avr/iom16.h: Same. * include/avr/iom161.h: Same. * include/avr/iom162.h: Same. * include/avr/iom163.h: Same. * include/avr/iomxxhva.h: Same. * include/avr/iomxx4.h: Same. * include/avr/iomxx0_1.h: Same. * include/avr/iomx8.h: Same. * include/avr/iom88p.h: Same. * include/avr/iom8535.h: Same. * include/avr/iom8515.h: Same. * include/avr/iom165.h: Same. * include/avr/iom8.h: Same. * include/avr/iom6490.h: Same. * include/avr/iom165p.h: Same. * include/avr/iom649.h: Same. * include/avr/iom168p.h: Same. * include/avr/iom169.h: Same. * include/avr/iom169p.h: Same. * include/avr/iom32.h: Same. * include/avr/iom323.h: Same. * include/avr/iom325.h: Same. * include/avr/iom3250.h: Same. * include/avr/iom328p.h: Same. * include/avr/iom329.h: Same. * include/avr/iom3290.h: Same. * include/avr/iom32hvbrevb.h: Same. * include/avr/iom32u4.h: Same. * include/avr/iom406.h: Same. * include/avr/iom48p.h: Same. * include/avr/iom64.h: Same. * include/avr/iom645.h: Same. * include/avr/iom6450.h: Same. * include/avr/iocanxx.h: Same. * include/avr/io90pwm1.h: Same. * include/avr/io90pwm216.h: Same. * include/avr/io1200.h: Same. * include/avr/io2343.h: Same. * include/avr/io2323.h: Same. * include/avr/io86r401.h: Same. * include/avr/io2313.h: Same. * include/avr/io2333.h: Same. * include/avr/io4434.h: Same. * include/avr/io4433.h: Same. * include/avr/io4414.h: Same. * include/avr/io8535.h: Same. * include/avr/io8515.h: Same. * include/avr/io90pwmx.h: Same. * include/avr/io90pwm3b.h: Same. * include/avr/io90pwm316.h: Same. * include/avr/io90pwm2b.h: Same. * include/avr/iom16hvbrevb: Also, update copyright year, change device name (rev b version is the older version). * include/avr/iom32hvbrevb: Same. * NEWS: Add item. 2011-02-23 Eric B. Weddington Partial fix for bug #28058, comment #2. Thanks to Jan Waclawek for the code. * include/avr/pgmspace.h: Add new strlen_P inline function. * libc/pmstring/strlen_P.S: Rename function to __strlen_P. * NEWS: Add item. 2011-02-23 Eric B. Weddington Fix for bug #17815. * doc/api/Makefile.am (install-dox-man): Rewrite to fix install location to use mandir configuration option. * NEWS: Add item to fixed bugs list. 2011-02-22 Eric B. Weddington * doc/api/tools-install.dox: Partial documentation changes for building avr-libc for MinGW/Windows. 2011-02-22 Eric B. Weddington Fix for bug #24861. * include/avr/interrupt.h: Remove extra code blocks in documentation. Fix spacing. * NEWS: Add item to fixed bugs list. 2011-02-21 Eric B. Weddington Fix for bug #32103. Thanks to Thomas Rudin for fix. * configure.ac: Fix wildcards in searching for cross tools. * NEWS: Add item to fixed bugs list. 2011-02-21 Eric B. Weddington Fix for bug #32419. * include/avr/iox192a3.h (*EEPROM_SIZE): Fix values. * NEWS: Add item to fixed bugs list. 2011-02-16 Joerg Wunsch * configure.ac: Bump for post-release. 2011-02-16 Joerg Wunsch Released avr-libc-1.7.1. 2011-02-16 Anitha Boyapati * include/avr/power.h: Changes to power_all_enable()/disable() for Xmega A and D family 2011-02-14 Anitha Boyapati Thanks to Praveen Kaushik for the device support. * configure.ac: Support for ATMega16HVB RevB, ATMega32HVB RevB. * devtools/gen-avr-lib-tree.sh: Same. * doc/api/main_page.dox: Same. * doc/api/using-tools.dox: Same. * include/avr/eeprom.h: Same. * include/avr/io.h: Same. * include/avr/iom16hvb.h: Header file regenerated. * include/avr/iom16hvbrevb.h: Added newly. * include/avr/iom32hvb.h: Header file regenerated. * include/avr/iom32hvbrevb.h: Added newly. * include/avr/Makefile.am: Support for atmega16HVB RevB, ATMega32HVB RevB. * include/avr/power.h: Same. * include/avr/sleep.h: Same. * include/avr/wdt.h: Same. 2011-02-14 Anitha Boyapati Thanks to Usha Gupta for the device support. * include/avr/io.h: Support for AVR Tiny84a * include/avr/iotn84a.h: Same. * include/avr/Makefile.am: Same. 2011-02-14 Anitha Boyapati Fix for #bug31873 * include/avr/power.h: Modifications to power_aes_enable/disable() power_all_enable/disable() functions for Xmega devices. 2011-02-11 Anitha Boyapati Thanks to Praveen Kaushik for the fix for #bug31990. * include/avr/io90pwm81.h: PRPSC0 is renamed to PRPSCR in sync with device XML file. * include/avr/power.h: power_psc0_enable()/disable() have been renamed to power_pscr_enable()/disable(). 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Roth # Copyright (c) 2005, 2008, 2009 Anatoly Sokolov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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$(AVRLIB_ASFLAGS) @HAS_avrxmega7_TRUE@__install_dir = $(prefix)/avr/lib/$(AVR_INSTALL_DIR) @HAS_avrxmega7_TRUE@avrdir = $(__install_dir) @HAS_avrxmega7_TRUE@avrlibdir = $(__install_dir) @HAS_avrxmega7_TRUE@avr_LIBRARIES = \ @HAS_avrxmega7_TRUE@ libc.a \ @HAS_avrxmega7_TRUE@ libprintf_min.a \ @HAS_avrxmega7_TRUE@ libprintf_flt.a \ @HAS_avrxmega7_TRUE@ libscanf_min.a \ @HAS_avrxmega7_TRUE@ libscanf_flt.a \ @HAS_avrxmega7_TRUE@ libm.a @HAS_avrxmega7_TRUE@stdlib_a_c_sources = \ @HAS_avrxmega7_TRUE@ abs.c \ @HAS_avrxmega7_TRUE@ assert.c \ @HAS_avrxmega7_TRUE@ bsearch.c \ @HAS_avrxmega7_TRUE@ calloc.c \ @HAS_avrxmega7_TRUE@ errno.c \ @HAS_avrxmega7_TRUE@ dtoa_prf.c \ @HAS_avrxmega7_TRUE@ dtostre.c \ @HAS_avrxmega7_TRUE@ dtostrf.c \ @HAS_avrxmega7_TRUE@ labs.c \ @HAS_avrxmega7_TRUE@ malloc.c \ @HAS_avrxmega7_TRUE@ qsort.c \ @HAS_avrxmega7_TRUE@ rand.c \ @HAS_avrxmega7_TRUE@ random.c \ @HAS_avrxmega7_TRUE@ realloc.c \ @HAS_avrxmega7_TRUE@ strtod.c \ @HAS_avrxmega7_TRUE@ strtol.c \ @HAS_avrxmega7_TRUE@ strtoul.c \ @HAS_avrxmega7_TRUE@ dtoa_conv.h \ @HAS_avrxmega7_TRUE@ stdlib_private.h @HAS_avrxmega7_TRUE@stdlib_a_asm_sources = \ @HAS_avrxmega7_TRUE@ abort.S \ @HAS_avrxmega7_TRUE@ atof.S \ @HAS_avrxmega7_TRUE@ atoi.S \ @HAS_avrxmega7_TRUE@ atol.S \ @HAS_avrxmega7_TRUE@ div.S \ @HAS_avrxmega7_TRUE@ exit.S \ @HAS_avrxmega7_TRUE@ ftoa_engine.S \ @HAS_avrxmega7_TRUE@ ldiv.S \ @HAS_avrxmega7_TRUE@ setjmp.S \ @HAS_avrxmega7_TRUE@ isascii.S \ @HAS_avrxmega7_TRUE@ toascii.S \ @HAS_avrxmega7_TRUE@ isalnum.S \ @HAS_avrxmega7_TRUE@ cty_isfalse.S \ @HAS_avrxmega7_TRUE@ isalpha.S \ @HAS_avrxmega7_TRUE@ isdigit.S \ @HAS_avrxmega7_TRUE@ isxdigit.S \ @HAS_avrxmega7_TRUE@ iscntrl.S \ @HAS_avrxmega7_TRUE@ isprint.S \ @HAS_avrxmega7_TRUE@ isspace.S \ @HAS_avrxmega7_TRUE@ isblank.S \ @HAS_avrxmega7_TRUE@ ispunct.S \ @HAS_avrxmega7_TRUE@ tolower.S \ @HAS_avrxmega7_TRUE@ toupper.S @HAS_avrxmega7_TRUE@stdlib_a_extra_dist = \ @HAS_avrxmega7_TRUE@ ctype.S \ @HAS_avrxmega7_TRUE@ abort.c \ @HAS_avrxmega7_TRUE@ atoi.c \ @HAS_avrxmega7_TRUE@ atol.c @HAS_avrxmega7_TRUE@pmstring_a_c_sources = \ @HAS_avrxmega7_TRUE@ strtok_P.c @HAS_avrxmega7_TRUE@pmstring_a_asm_sources = \ @HAS_avrxmega7_TRUE@ memchr_P.S \ @HAS_avrxmega7_TRUE@ memcmp_P.S \ @HAS_avrxmega7_TRUE@ memccpy_P.S \ @HAS_avrxmega7_TRUE@ memcpy_P.S \ @HAS_avrxmega7_TRUE@ memrchr_P.S \ @HAS_avrxmega7_TRUE@ strcasecmp_P.S \ @HAS_avrxmega7_TRUE@ strcat_P.S \ @HAS_avrxmega7_TRUE@ strchr_P.S \ @HAS_avrxmega7_TRUE@ strchrnul_P.S \ @HAS_avrxmega7_TRUE@ strcmp_P.S \ @HAS_avrxmega7_TRUE@ strcpy_P.S \ @HAS_avrxmega7_TRUE@ strcspn_P.S \ @HAS_avrxmega7_TRUE@ strlcat_P.S \ @HAS_avrxmega7_TRUE@ strlcpy_P.S \ @HAS_avrxmega7_TRUE@ strlen_P.S \ @HAS_avrxmega7_TRUE@ strncasecmp_P.S \ @HAS_avrxmega7_TRUE@ strncat_P.S \ @HAS_avrxmega7_TRUE@ strncmp_P.S \ @HAS_avrxmega7_TRUE@ strncpy_P.S \ @HAS_avrxmega7_TRUE@ strnlen_P.S \ @HAS_avrxmega7_TRUE@ strpbrk_P.S \ @HAS_avrxmega7_TRUE@ strrchr_P.S \ @HAS_avrxmega7_TRUE@ strsep_P.S \ @HAS_avrxmega7_TRUE@ strspn_P.S \ @HAS_avrxmega7_TRUE@ strstr_P.S \ @HAS_avrxmega7_TRUE@ strtok_rP.S \ @HAS_avrxmega7_TRUE@ memcpy_PF.S \ @HAS_avrxmega7_TRUE@ strcasecmp_PF.S \ @HAS_avrxmega7_TRUE@ strcat_PF.S \ @HAS_avrxmega7_TRUE@ strcmp_PF.S \ @HAS_avrxmega7_TRUE@ strcpy_PF.S \ @HAS_avrxmega7_TRUE@ strlcat_PF.S \ @HAS_avrxmega7_TRUE@ strlcpy_PF.S \ @HAS_avrxmega7_TRUE@ strlen_PF.S \ @HAS_avrxmega7_TRUE@ strncasecmp_PF.S \ @HAS_avrxmega7_TRUE@ strncat_PF.S \ @HAS_avrxmega7_TRUE@ strncmp_PF.S \ @HAS_avrxmega7_TRUE@ strncpy_PF.S \ @HAS_avrxmega7_TRUE@ strnlen_PF.S \ @HAS_avrxmega7_TRUE@ strstr_PF.S \ @HAS_avrxmega7_TRUE@ memcmp_PF.S @HAS_avrxmega7_TRUE@string_a_c_sources = \ @HAS_avrxmega7_TRUE@ strdup.c \ @HAS_avrxmega7_TRUE@ strtok.c @HAS_avrxmega7_TRUE@string_a_asm_sources = \ @HAS_avrxmega7_TRUE@ ffs.S \ @HAS_avrxmega7_TRUE@ ffsl.S \ @HAS_avrxmega7_TRUE@ ffsll.S \ @HAS_avrxmega7_TRUE@ memccpy.S \ @HAS_avrxmega7_TRUE@ memchr.S \ @HAS_avrxmega7_TRUE@ memcmp.S \ @HAS_avrxmega7_TRUE@ memcpy.S \ @HAS_avrxmega7_TRUE@ memmem.S \ @HAS_avrxmega7_TRUE@ memmem_P.S \ @HAS_avrxmega7_TRUE@ memmove.S \ @HAS_avrxmega7_TRUE@ memrchr.S \ @HAS_avrxmega7_TRUE@ memset.S \ @HAS_avrxmega7_TRUE@ strcasecmp.S \ @HAS_avrxmega7_TRUE@ strcasestr.S \ @HAS_avrxmega7_TRUE@ strcasestr_P.S \ @HAS_avrxmega7_TRUE@ strcat.S \ @HAS_avrxmega7_TRUE@ strchr.S \ @HAS_avrxmega7_TRUE@ strchrnul.S \ @HAS_avrxmega7_TRUE@ strcmp.S \ @HAS_avrxmega7_TRUE@ strcpy.S \ @HAS_avrxmega7_TRUE@ strcspn.S \ @HAS_avrxmega7_TRUE@ strlcat.S \ @HAS_avrxmega7_TRUE@ strlcpy.S \ @HAS_avrxmega7_TRUE@ strlen.S \ @HAS_avrxmega7_TRUE@ strlwr.S \ @HAS_avrxmega7_TRUE@ strncasecmp.S \ @HAS_avrxmega7_TRUE@ strncat.S \ @HAS_avrxmega7_TRUE@ strncmp.S \ @HAS_avrxmega7_TRUE@ strncpy.S \ @HAS_avrxmega7_TRUE@ strnlen.S \ @HAS_avrxmega7_TRUE@ strpbrk.S \ @HAS_avrxmega7_TRUE@ strrchr.S \ @HAS_avrxmega7_TRUE@ strrev.S \ @HAS_avrxmega7_TRUE@ strsep.S \ @HAS_avrxmega7_TRUE@ strspn.S \ @HAS_avrxmega7_TRUE@ strstr.S \ @HAS_avrxmega7_TRUE@ strtok_r.S \ @HAS_avrxmega7_TRUE@ strupr.S @HAS_avrxmega7_TRUE@string_a_extra_dist = \ @HAS_avrxmega7_TRUE@ strlcat.c \ @HAS_avrxmega7_TRUE@ strlcpy.c @HAS_avrxmega7_TRUE@misc_a_c_sources = @HAS_avrxmega7_TRUE@eeprom_asm_sources = \ @HAS_avrxmega7_TRUE@ eerd_block.S \ @HAS_avrxmega7_TRUE@ eerd_byte.S \ @HAS_avrxmega7_TRUE@ eerd_dword.S \ @HAS_avrxmega7_TRUE@ eerd_word.S \ @HAS_avrxmega7_TRUE@ eeupd_block.S \ @HAS_avrxmega7_TRUE@ eeupd_byte.S \ @HAS_avrxmega7_TRUE@ eeupd_dword.S \ @HAS_avrxmega7_TRUE@ eeupd_word.S \ @HAS_avrxmega7_TRUE@ eewr_block.S \ @HAS_avrxmega7_TRUE@ eewr_byte.S \ @HAS_avrxmega7_TRUE@ eewr_dword.S \ @HAS_avrxmega7_TRUE@ eewr_word.S @HAS_avrxmega7_TRUE@misc_a_asm_sources = \ @HAS_avrxmega7_TRUE@ itoa.S \ @HAS_avrxmega7_TRUE@ ltoa.S \ @HAS_avrxmega7_TRUE@ mulsi10.S \ @HAS_avrxmega7_TRUE@ mul10.S \ @HAS_avrxmega7_TRUE@ ultoa.S \ @HAS_avrxmega7_TRUE@ utoa.S @HAS_avrxmega7_TRUE@misc_a_extra_dist = \ @HAS_avrxmega7_TRUE@ eedef.h \ @HAS_avrxmega7_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avrxmega7_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avrxmega7_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avrxmega7_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avrxmega7_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avrxmega7_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avrxmega7_TRUE@misc_a_libadd = \ @HAS_avrxmega7_TRUE@ $(eeprom_asm_objlist) @HAS_avrxmega7_TRUE@stdio_a_c_sources = \ @HAS_avrxmega7_TRUE@ clearerr.c \ @HAS_avrxmega7_TRUE@ fclose.c \ @HAS_avrxmega7_TRUE@ fdevopen.c \ @HAS_avrxmega7_TRUE@ feof.c \ @HAS_avrxmega7_TRUE@ ferror.c \ @HAS_avrxmega7_TRUE@ fgetc.c \ @HAS_avrxmega7_TRUE@ fgets.c \ @HAS_avrxmega7_TRUE@ fprintf.c \ @HAS_avrxmega7_TRUE@ fprintf_p.c \ @HAS_avrxmega7_TRUE@ fputc.c \ @HAS_avrxmega7_TRUE@ fputs.c \ @HAS_avrxmega7_TRUE@ fputs_p.c \ @HAS_avrxmega7_TRUE@ fread.c \ @HAS_avrxmega7_TRUE@ fscanf.c \ @HAS_avrxmega7_TRUE@ fscanf_p.c \ @HAS_avrxmega7_TRUE@ fwrite.c \ @HAS_avrxmega7_TRUE@ getchar.c \ @HAS_avrxmega7_TRUE@ gets.c \ @HAS_avrxmega7_TRUE@ iob.c \ @HAS_avrxmega7_TRUE@ printf.c \ @HAS_avrxmega7_TRUE@ printf_p.c \ @HAS_avrxmega7_TRUE@ putchar.c \ @HAS_avrxmega7_TRUE@ puts.c \ @HAS_avrxmega7_TRUE@ puts_p.c \ @HAS_avrxmega7_TRUE@ scanf.c \ @HAS_avrxmega7_TRUE@ scanf_p.c \ @HAS_avrxmega7_TRUE@ snprintf.c \ @HAS_avrxmega7_TRUE@ snprintf_p.c \ @HAS_avrxmega7_TRUE@ sprintf.c \ @HAS_avrxmega7_TRUE@ sprintf_p.c \ @HAS_avrxmega7_TRUE@ sscanf.c \ @HAS_avrxmega7_TRUE@ sscanf_p.c \ @HAS_avrxmega7_TRUE@ vfprintf_p.c \ @HAS_avrxmega7_TRUE@ vfscanf_p.c \ @HAS_avrxmega7_TRUE@ vprintf.c \ @HAS_avrxmega7_TRUE@ vscanf.c \ @HAS_avrxmega7_TRUE@ vsnprintf.c \ @HAS_avrxmega7_TRUE@ vsnprintf_p.c \ @HAS_avrxmega7_TRUE@ vsprintf.c \ @HAS_avrxmega7_TRUE@ vsprintf_p.c \ @HAS_avrxmega7_TRUE@ ungetc.c @HAS_avrxmega7_TRUE@stdio_a_asm_sources = \ @HAS_avrxmega7_TRUE@ getc.S \ @HAS_avrxmega7_TRUE@ putc.S \ @HAS_avrxmega7_TRUE@ ultoa_invert.S @HAS_avrxmega7_TRUE@stdio_a_extra_dist = \ @HAS_avrxmega7_TRUE@ vfprintf.c \ @HAS_avrxmega7_TRUE@ vfscanf.c \ @HAS_avrxmega7_TRUE@ stdio_private.h \ @HAS_avrxmega7_TRUE@ xtoa_fast.h @HAS_avrxmega7_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avrxmega7_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avrxmega7_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avrxmega7_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avrxmega7_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avrxmega7_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avrxmega7_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avrxmega7_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avrxmega7_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avrxmega7_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avrxmega7_TRUE@libm_a_c_sources = @HAS_avrxmega7_TRUE@libm_a_asm_sources = \ @HAS_avrxmega7_TRUE@ acos.S \ @HAS_avrxmega7_TRUE@ addsf3.S \ @HAS_avrxmega7_TRUE@ addsf3x.S \ @HAS_avrxmega7_TRUE@ asin.S \ @HAS_avrxmega7_TRUE@ atan2.S \ @HAS_avrxmega7_TRUE@ atan.S \ @HAS_avrxmega7_TRUE@ cbrt.S \ @HAS_avrxmega7_TRUE@ ceil.S \ @HAS_avrxmega7_TRUE@ cmpsf2.S \ @HAS_avrxmega7_TRUE@ copysign.S \ @HAS_avrxmega7_TRUE@ cosh.S \ @HAS_avrxmega7_TRUE@ cos.S \ @HAS_avrxmega7_TRUE@ divsf3.S \ @HAS_avrxmega7_TRUE@ divsf3x.S \ @HAS_avrxmega7_TRUE@ exp.S \ @HAS_avrxmega7_TRUE@ fixsfdi.S \ @HAS_avrxmega7_TRUE@ fixsfsi.S \ @HAS_avrxmega7_TRUE@ fixunssfsi.S \ @HAS_avrxmega7_TRUE@ floatdisf.S \ @HAS_avrxmega7_TRUE@ floatsisf.S \ @HAS_avrxmega7_TRUE@ floatundisf.S \ @HAS_avrxmega7_TRUE@ fdim.S \ @HAS_avrxmega7_TRUE@ floor.S \ @HAS_avrxmega7_TRUE@ fma.S \ @HAS_avrxmega7_TRUE@ fmax.S \ @HAS_avrxmega7_TRUE@ fmin.S \ @HAS_avrxmega7_TRUE@ fmod.S \ @HAS_avrxmega7_TRUE@ fp_arccos.S \ @HAS_avrxmega7_TRUE@ fp_cmp.S \ @HAS_avrxmega7_TRUE@ fp_inf.S \ @HAS_avrxmega7_TRUE@ fp_mintl.S \ @HAS_avrxmega7_TRUE@ fp_mpack.S \ @HAS_avrxmega7_TRUE@ fp_nan.S \ @HAS_avrxmega7_TRUE@ fp_negdi.S \ @HAS_avrxmega7_TRUE@ fp_norm2.S \ @HAS_avrxmega7_TRUE@ fp_powser.S \ @HAS_avrxmega7_TRUE@ fp_powsodd.S \ @HAS_avrxmega7_TRUE@ fp_pscA.S \ @HAS_avrxmega7_TRUE@ fp_pscB.S \ @HAS_avrxmega7_TRUE@ fp_rempio2.S \ @HAS_avrxmega7_TRUE@ fp_round.S \ @HAS_avrxmega7_TRUE@ fp_sinus.S \ @HAS_avrxmega7_TRUE@ fp_split3.S \ @HAS_avrxmega7_TRUE@ fp_trunc.S \ @HAS_avrxmega7_TRUE@ fp_zero.S \ @HAS_avrxmega7_TRUE@ frexp.S \ @HAS_avrxmega7_TRUE@ gesf2.S \ @HAS_avrxmega7_TRUE@ hypot.S \ @HAS_avrxmega7_TRUE@ inverse.S \ @HAS_avrxmega7_TRUE@ isfinite.S \ @HAS_avrxmega7_TRUE@ isinf.S \ @HAS_avrxmega7_TRUE@ isnan.S \ @HAS_avrxmega7_TRUE@ ldexp.S \ @HAS_avrxmega7_TRUE@ log10.S \ @HAS_avrxmega7_TRUE@ log.S \ @HAS_avrxmega7_TRUE@ lrint.S \ @HAS_avrxmega7_TRUE@ lround.S \ @HAS_avrxmega7_TRUE@ modf.S \ @HAS_avrxmega7_TRUE@ mulsf3.S \ @HAS_avrxmega7_TRUE@ mulsf3x.S \ @HAS_avrxmega7_TRUE@ negsf2.S \ @HAS_avrxmega7_TRUE@ pow.S \ @HAS_avrxmega7_TRUE@ round.S \ @HAS_avrxmega7_TRUE@ signbit.S \ @HAS_avrxmega7_TRUE@ sinh.S \ @HAS_avrxmega7_TRUE@ sin.S \ @HAS_avrxmega7_TRUE@ sqrt.S \ @HAS_avrxmega7_TRUE@ square.S \ @HAS_avrxmega7_TRUE@ tanh.S \ @HAS_avrxmega7_TRUE@ tan.S \ @HAS_avrxmega7_TRUE@ trunc.S \ @HAS_avrxmega7_TRUE@ unordsf2.S @HAS_avrxmega7_TRUE@libm_a_extra_dist = \ @HAS_avrxmega7_TRUE@ asmdef.h \ @HAS_avrxmega7_TRUE@ fp32def.h \ @HAS_avrxmega7_TRUE@ ntz.h @HAS_avrxmega7_TRUE@nodist_libc_a_SOURCES = \ @HAS_avrxmega7_TRUE@ $(stdlib_a_c_sources) \ @HAS_avrxmega7_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avrxmega7_TRUE@ $(pmstring_a_c_sources) \ @HAS_avrxmega7_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avrxmega7_TRUE@ $(string_a_c_sources) \ @HAS_avrxmega7_TRUE@ $(string_a_asm_sources) \ @HAS_avrxmega7_TRUE@ $(misc_a_c_sources) \ @HAS_avrxmega7_TRUE@ $(misc_a_asm_sources) \ @HAS_avrxmega7_TRUE@ $(stdio_a_c_sources) \ @HAS_avrxmega7_TRUE@ $(stdio_a_asm_sources) \ @HAS_avrxmega7_TRUE@ $(libm_a_c_sources) \ @HAS_avrxmega7_TRUE@ $(libm_a_asm_sources) @HAS_avrxmega7_TRUE@nodist_libm_a_SOURCES = \ @HAS_avrxmega7_TRUE@ $(libm_a_c_sources) \ @HAS_avrxmega7_TRUE@ $(libm_a_asm_sources) @HAS_avrxmega7_TRUE@libc_a_LIBADD = \ @HAS_avrxmega7_TRUE@ $(stdio_a_libadd) \ @HAS_avrxmega7_TRUE@ $(misc_a_libadd) @HAS_avrxmega7_TRUE@libc_a_DEPENDENCIES = \ @HAS_avrxmega7_TRUE@ $(stdio_a_libadd) \ @HAS_avrxmega7_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am $(top_srcdir)/libc/misc/Rules.am $(top_srcdir)/libc/misc/Files.am $(top_srcdir)/libc/stdio/Rules.am $(top_srcdir)/libc/stdio/Files.am $(top_srcdir)/libm/fplib/Rules.am $(top_srcdir)/libm/fplib/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign avr/lib/avrxmega7/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign avr/lib/avrxmega7/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): install-avrLIBRARIES: $(avr_LIBRARIES) @$(NORMAL_INSTALL) test -z "$(avrdir)" || $(MKDIR_P) "$(DESTDIR)$(avrdir)" @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || list=; \ list2=; for p in $$list; do \ if test -f $$p; then \ list2="$$list2 $$p"; \ else :; fi; \ done; \ test -z "$$list2" || { \ echo " $(INSTALL_DATA) $$list2 '$(DESTDIR)$(avrdir)'"; \ $(INSTALL_DATA) $$list2 "$(DESTDIR)$(avrdir)" || exit $$?; } @$(POST_INSTALL) @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || list=; \ for p in $$list; do \ if test -f $$p; then \ $(am__strip_dir) \ echo " ( cd '$(DESTDIR)$(avrdir)' && $(RANLIB) $$f )"; \ ( cd "$(DESTDIR)$(avrdir)" && $(RANLIB) $$f ) || exit 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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AVR_LIBC_VERSION = @AVR_LIBC_VERSION@ AVR_LIBC_VERSION_NUMERIC = @AVR_LIBC_VERSION_NUMERIC@ AWK = @AWK@ CC = @CC@ CCAS = @CCAS@ CCASDEPMODE = @CCASDEPMODE@ CCASFLAGS = @CCASFLAGS@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ CPPFLAGS = @CPPFLAGS@ CYGPATH_W = @CYGPATH_W@ DEFS = @DEFS@ DEPDIR = @DEPDIR@ DOCSDIR = @DOCSDIR@ DOC_INST_DIR = @DOC_INST_DIR@ ECHO_C = @ECHO_C@ ECHO_N = @ECHO_N@ ECHO_T = @ECHO_T@ EXEEXT = @EXEEXT@ FNO_JUMP_TABLES = @FNO_JUMP_TABLES@ HAS_DELAY_CYCLES = @HAS_DELAY_CYCLES@ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_DOX_HTML = @INSTALL_DOX_HTML@ INSTALL_DOX_MAN = @INSTALL_DOX_MAN@ INSTALL_DOX_PDF = @INSTALL_DOX_PDF@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_SCRIPT = @INSTALL_SCRIPT@ INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ LDFLAGS = @LDFLAGS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAKEINFO = @MAKEINFO@ MKDIR_P = @MKDIR_P@ OBJEXT = @OBJEXT@ PACKAGE = @PACKAGE@ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ PACKAGE_NAME = @PACKAGE_NAME@ PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_URL = @PACKAGE_URL@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ PNGTOPNM = @PNGTOPNM@ PNMTOPNG = @PNMTOPNG@ RANLIB = @RANLIB@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ TARGET_DOX_HTML = @TARGET_DOX_HTML@ TARGET_DOX_PDF = @TARGET_DOX_PDF@ VERSION = @VERSION@ abs_builddir = @abs_builddir@ abs_srcdir = @abs_srcdir@ abs_top_builddir = @abs_top_builddir@ abs_top_srcdir = @abs_top_srcdir@ ac_ct_CC = @ac_ct_CC@ am__include = @am__include@ am__leading_dot = @am__leading_dot@ am__quote = @am__quote@ am__tar = @am__tar@ am__untar = @am__untar@ bindir = @bindir@ build = @build@ build_alias = @build_alias@ build_cpu = @build_cpu@ build_os = @build_os@ build_vendor = @build_vendor@ builddir = @builddir@ datadir = @datadir@ datarootdir = @datarootdir@ docdir = @docdir@ dvidir = @dvidir@ exec_prefix = @exec_prefix@ host = @host@ host_alias = @host_alias@ host_cpu = @host_cpu@ host_os = @host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ SUBDIRS = atmega103 at43usb320 at43usb355 at76c711 at90usb82 at90usb162 AVR_TARGET = avr3 AVR_TARGET_DEFS = -D__COMPILING_AVR_LIBC__ AVR_TARGET_CFLAGS = -mcall-prologues -Os AVR_TARGET_ASFLAGS = AVR_INSTALL_DIR = avr3 @HAS_avr3_TRUE@AVRLIB_DEVLIST = $(am__append_1) $(am__append_2) \ @HAS_avr3_TRUE@ $(am__append_3) $(am__append_4) $(am__append_5) \ @HAS_avr3_TRUE@ $(am__append_6) @HAS_avr3_TRUE@AM_CPPFLAGS = -I$(top_srcdir)/common -I$(top_srcdir)/include -I$(top_builddir)/include @HAS_avr3_TRUE@AVRLIB_CFLAGS = -g -Wall -W -Wstrict-prototypes -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_CFLAGS) @HAS_avr3_TRUE@AVRLIB_ASFLAGS = -x assembler-with-cpp -Wa,-gstabs -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_ASFLAGS) @HAS_avr3_TRUE@AM_CFLAGS = $(AVRLIB_CFLAGS) @HAS_avr3_TRUE@AM_CCASFLAGS = $(AM_CPPFLAGS) $(AVRLIB_ASFLAGS) @HAS_avr3_TRUE@__install_dir = $(prefix)/avr/lib/$(AVR_INSTALL_DIR) @HAS_avr3_TRUE@avrdir = $(__install_dir) @HAS_avr3_TRUE@avrlibdir = $(__install_dir) @HAS_avr3_TRUE@avr_LIBRARIES = \ @HAS_avr3_TRUE@ libc.a \ @HAS_avr3_TRUE@ libprintf_min.a \ @HAS_avr3_TRUE@ libprintf_flt.a \ @HAS_avr3_TRUE@ libscanf_min.a \ @HAS_avr3_TRUE@ libscanf_flt.a \ @HAS_avr3_TRUE@ libm.a @HAS_avr3_TRUE@stdlib_a_c_sources = \ @HAS_avr3_TRUE@ abs.c \ @HAS_avr3_TRUE@ assert.c \ @HAS_avr3_TRUE@ bsearch.c \ @HAS_avr3_TRUE@ calloc.c \ @HAS_avr3_TRUE@ errno.c \ @HAS_avr3_TRUE@ dtoa_prf.c \ @HAS_avr3_TRUE@ dtostre.c \ @HAS_avr3_TRUE@ dtostrf.c \ @HAS_avr3_TRUE@ labs.c \ @HAS_avr3_TRUE@ malloc.c \ @HAS_avr3_TRUE@ qsort.c \ @HAS_avr3_TRUE@ rand.c \ @HAS_avr3_TRUE@ random.c \ @HAS_avr3_TRUE@ realloc.c \ @HAS_avr3_TRUE@ strtod.c \ @HAS_avr3_TRUE@ strtol.c \ @HAS_avr3_TRUE@ strtoul.c \ @HAS_avr3_TRUE@ dtoa_conv.h \ @HAS_avr3_TRUE@ stdlib_private.h @HAS_avr3_TRUE@stdlib_a_asm_sources = \ @HAS_avr3_TRUE@ abort.S \ @HAS_avr3_TRUE@ atof.S \ @HAS_avr3_TRUE@ atoi.S \ @HAS_avr3_TRUE@ atol.S \ @HAS_avr3_TRUE@ div.S \ @HAS_avr3_TRUE@ exit.S \ @HAS_avr3_TRUE@ ftoa_engine.S \ @HAS_avr3_TRUE@ ldiv.S \ @HAS_avr3_TRUE@ setjmp.S \ @HAS_avr3_TRUE@ isascii.S \ @HAS_avr3_TRUE@ toascii.S \ @HAS_avr3_TRUE@ isalnum.S \ @HAS_avr3_TRUE@ cty_isfalse.S \ @HAS_avr3_TRUE@ isalpha.S \ @HAS_avr3_TRUE@ isdigit.S \ @HAS_avr3_TRUE@ isxdigit.S \ @HAS_avr3_TRUE@ iscntrl.S \ @HAS_avr3_TRUE@ isprint.S \ @HAS_avr3_TRUE@ isspace.S \ @HAS_avr3_TRUE@ isblank.S \ @HAS_avr3_TRUE@ ispunct.S \ @HAS_avr3_TRUE@ tolower.S \ @HAS_avr3_TRUE@ toupper.S @HAS_avr3_TRUE@stdlib_a_extra_dist = \ @HAS_avr3_TRUE@ ctype.S \ @HAS_avr3_TRUE@ abort.c \ @HAS_avr3_TRUE@ atoi.c \ @HAS_avr3_TRUE@ atol.c @HAS_avr3_TRUE@pmstring_a_c_sources = \ @HAS_avr3_TRUE@ strtok_P.c @HAS_avr3_TRUE@pmstring_a_asm_sources = \ @HAS_avr3_TRUE@ memchr_P.S \ @HAS_avr3_TRUE@ memcmp_P.S \ @HAS_avr3_TRUE@ memccpy_P.S \ @HAS_avr3_TRUE@ memcpy_P.S \ @HAS_avr3_TRUE@ memrchr_P.S \ @HAS_avr3_TRUE@ strcasecmp_P.S \ @HAS_avr3_TRUE@ strcat_P.S \ @HAS_avr3_TRUE@ strchr_P.S \ @HAS_avr3_TRUE@ strchrnul_P.S \ @HAS_avr3_TRUE@ strcmp_P.S \ @HAS_avr3_TRUE@ strcpy_P.S \ @HAS_avr3_TRUE@ strcspn_P.S \ @HAS_avr3_TRUE@ strlcat_P.S \ @HAS_avr3_TRUE@ strlcpy_P.S \ @HAS_avr3_TRUE@ strlen_P.S \ @HAS_avr3_TRUE@ strncasecmp_P.S \ @HAS_avr3_TRUE@ strncat_P.S \ @HAS_avr3_TRUE@ strncmp_P.S \ @HAS_avr3_TRUE@ strncpy_P.S \ @HAS_avr3_TRUE@ strnlen_P.S \ @HAS_avr3_TRUE@ strpbrk_P.S \ @HAS_avr3_TRUE@ strrchr_P.S \ @HAS_avr3_TRUE@ strsep_P.S \ @HAS_avr3_TRUE@ strspn_P.S \ @HAS_avr3_TRUE@ strstr_P.S \ @HAS_avr3_TRUE@ strtok_rP.S \ @HAS_avr3_TRUE@ memcpy_PF.S \ @HAS_avr3_TRUE@ strcasecmp_PF.S \ @HAS_avr3_TRUE@ strcat_PF.S \ @HAS_avr3_TRUE@ strcmp_PF.S \ @HAS_avr3_TRUE@ strcpy_PF.S \ @HAS_avr3_TRUE@ strlcat_PF.S \ @HAS_avr3_TRUE@ strlcpy_PF.S \ @HAS_avr3_TRUE@ strlen_PF.S \ @HAS_avr3_TRUE@ strncasecmp_PF.S \ @HAS_avr3_TRUE@ strncat_PF.S \ @HAS_avr3_TRUE@ strncmp_PF.S \ @HAS_avr3_TRUE@ strncpy_PF.S \ @HAS_avr3_TRUE@ strnlen_PF.S \ @HAS_avr3_TRUE@ strstr_PF.S \ @HAS_avr3_TRUE@ memcmp_PF.S @HAS_avr3_TRUE@string_a_c_sources = \ @HAS_avr3_TRUE@ strdup.c \ @HAS_avr3_TRUE@ strtok.c @HAS_avr3_TRUE@string_a_asm_sources = \ @HAS_avr3_TRUE@ ffs.S \ @HAS_avr3_TRUE@ ffsl.S \ @HAS_avr3_TRUE@ ffsll.S \ @HAS_avr3_TRUE@ memccpy.S \ @HAS_avr3_TRUE@ memchr.S \ @HAS_avr3_TRUE@ memcmp.S \ @HAS_avr3_TRUE@ memcpy.S \ @HAS_avr3_TRUE@ memmem.S \ @HAS_avr3_TRUE@ memmem_P.S \ @HAS_avr3_TRUE@ memmove.S \ @HAS_avr3_TRUE@ memrchr.S \ @HAS_avr3_TRUE@ memset.S \ @HAS_avr3_TRUE@ strcasecmp.S \ @HAS_avr3_TRUE@ strcasestr.S \ @HAS_avr3_TRUE@ strcasestr_P.S \ @HAS_avr3_TRUE@ strcat.S \ @HAS_avr3_TRUE@ strchr.S \ @HAS_avr3_TRUE@ strchrnul.S \ @HAS_avr3_TRUE@ strcmp.S \ @HAS_avr3_TRUE@ strcpy.S \ @HAS_avr3_TRUE@ strcspn.S \ @HAS_avr3_TRUE@ strlcat.S \ @HAS_avr3_TRUE@ strlcpy.S \ @HAS_avr3_TRUE@ strlen.S \ @HAS_avr3_TRUE@ strlwr.S \ @HAS_avr3_TRUE@ strncasecmp.S \ @HAS_avr3_TRUE@ strncat.S \ @HAS_avr3_TRUE@ strncmp.S \ @HAS_avr3_TRUE@ strncpy.S \ @HAS_avr3_TRUE@ strnlen.S \ @HAS_avr3_TRUE@ strpbrk.S \ @HAS_avr3_TRUE@ strrchr.S \ @HAS_avr3_TRUE@ strrev.S \ @HAS_avr3_TRUE@ strsep.S \ @HAS_avr3_TRUE@ strspn.S \ @HAS_avr3_TRUE@ strstr.S \ @HAS_avr3_TRUE@ strtok_r.S \ @HAS_avr3_TRUE@ strupr.S @HAS_avr3_TRUE@string_a_extra_dist = \ @HAS_avr3_TRUE@ strlcat.c \ @HAS_avr3_TRUE@ strlcpy.c @HAS_avr3_TRUE@misc_a_c_sources = @HAS_avr3_TRUE@eeprom_asm_sources = \ @HAS_avr3_TRUE@ eerd_block.S \ @HAS_avr3_TRUE@ eerd_byte.S \ @HAS_avr3_TRUE@ eerd_dword.S \ @HAS_avr3_TRUE@ eerd_word.S \ @HAS_avr3_TRUE@ eeupd_block.S \ @HAS_avr3_TRUE@ eeupd_byte.S \ @HAS_avr3_TRUE@ eeupd_dword.S \ @HAS_avr3_TRUE@ eeupd_word.S \ @HAS_avr3_TRUE@ eewr_block.S \ @HAS_avr3_TRUE@ eewr_byte.S \ @HAS_avr3_TRUE@ eewr_dword.S \ @HAS_avr3_TRUE@ eewr_word.S @HAS_avr3_TRUE@misc_a_asm_sources = \ @HAS_avr3_TRUE@ itoa.S \ @HAS_avr3_TRUE@ ltoa.S \ @HAS_avr3_TRUE@ mulsi10.S \ @HAS_avr3_TRUE@ mul10.S \ @HAS_avr3_TRUE@ ultoa.S \ @HAS_avr3_TRUE@ utoa.S @HAS_avr3_TRUE@misc_a_extra_dist = \ @HAS_avr3_TRUE@ eedef.h \ @HAS_avr3_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avr3_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avr3_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avr3_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avr3_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avr3_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avr3_TRUE@misc_a_libadd = \ @HAS_avr3_TRUE@ $(eeprom_asm_objlist) @HAS_avr3_TRUE@stdio_a_c_sources = \ @HAS_avr3_TRUE@ clearerr.c \ @HAS_avr3_TRUE@ fclose.c \ @HAS_avr3_TRUE@ fdevopen.c \ @HAS_avr3_TRUE@ feof.c \ @HAS_avr3_TRUE@ ferror.c \ @HAS_avr3_TRUE@ fgetc.c \ @HAS_avr3_TRUE@ fgets.c \ @HAS_avr3_TRUE@ fprintf.c \ @HAS_avr3_TRUE@ fprintf_p.c \ @HAS_avr3_TRUE@ fputc.c \ @HAS_avr3_TRUE@ fputs.c \ @HAS_avr3_TRUE@ fputs_p.c \ @HAS_avr3_TRUE@ fread.c \ @HAS_avr3_TRUE@ fscanf.c \ @HAS_avr3_TRUE@ fscanf_p.c \ @HAS_avr3_TRUE@ fwrite.c \ @HAS_avr3_TRUE@ getchar.c \ @HAS_avr3_TRUE@ gets.c \ @HAS_avr3_TRUE@ iob.c \ @HAS_avr3_TRUE@ printf.c \ @HAS_avr3_TRUE@ printf_p.c \ @HAS_avr3_TRUE@ putchar.c \ @HAS_avr3_TRUE@ puts.c \ @HAS_avr3_TRUE@ puts_p.c \ @HAS_avr3_TRUE@ scanf.c \ @HAS_avr3_TRUE@ scanf_p.c \ @HAS_avr3_TRUE@ snprintf.c \ @HAS_avr3_TRUE@ snprintf_p.c \ @HAS_avr3_TRUE@ sprintf.c \ @HAS_avr3_TRUE@ sprintf_p.c \ @HAS_avr3_TRUE@ sscanf.c \ @HAS_avr3_TRUE@ sscanf_p.c \ @HAS_avr3_TRUE@ vfprintf_p.c \ @HAS_avr3_TRUE@ vfscanf_p.c \ @HAS_avr3_TRUE@ vprintf.c \ @HAS_avr3_TRUE@ vscanf.c \ @HAS_avr3_TRUE@ vsnprintf.c \ @HAS_avr3_TRUE@ vsnprintf_p.c \ @HAS_avr3_TRUE@ vsprintf.c \ @HAS_avr3_TRUE@ vsprintf_p.c \ @HAS_avr3_TRUE@ ungetc.c @HAS_avr3_TRUE@stdio_a_asm_sources = \ @HAS_avr3_TRUE@ getc.S \ @HAS_avr3_TRUE@ putc.S \ @HAS_avr3_TRUE@ ultoa_invert.S @HAS_avr3_TRUE@stdio_a_extra_dist = \ @HAS_avr3_TRUE@ vfprintf.c \ @HAS_avr3_TRUE@ vfscanf.c \ @HAS_avr3_TRUE@ stdio_private.h \ @HAS_avr3_TRUE@ xtoa_fast.h @HAS_avr3_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avr3_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avr3_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avr3_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avr3_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avr3_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avr3_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avr3_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avr3_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avr3_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avr3_TRUE@libm_a_c_sources = @HAS_avr3_TRUE@libm_a_asm_sources = \ @HAS_avr3_TRUE@ acos.S \ @HAS_avr3_TRUE@ addsf3.S \ @HAS_avr3_TRUE@ addsf3x.S \ @HAS_avr3_TRUE@ asin.S \ @HAS_avr3_TRUE@ atan2.S \ @HAS_avr3_TRUE@ atan.S \ @HAS_avr3_TRUE@ cbrt.S \ @HAS_avr3_TRUE@ ceil.S \ @HAS_avr3_TRUE@ cmpsf2.S \ @HAS_avr3_TRUE@ copysign.S \ @HAS_avr3_TRUE@ cosh.S \ @HAS_avr3_TRUE@ cos.S \ @HAS_avr3_TRUE@ divsf3.S \ @HAS_avr3_TRUE@ divsf3x.S \ @HAS_avr3_TRUE@ exp.S \ @HAS_avr3_TRUE@ fixsfdi.S \ @HAS_avr3_TRUE@ fixsfsi.S \ @HAS_avr3_TRUE@ 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from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # Copyright (c) 2005, 2008 Anatoly Sokolov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # Copyright (c) 2005, 2008 Anatoly Sokolov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # Copyright (c) 2005, 2008, 2009 Anatoly Sokolov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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@HAS_avr2_TRUE@ strtok_r.S \ @HAS_avr2_TRUE@ strupr.S @HAS_avr2_TRUE@string_a_extra_dist = \ @HAS_avr2_TRUE@ strlcat.c \ @HAS_avr2_TRUE@ strlcpy.c @HAS_avr2_TRUE@misc_a_c_sources = @HAS_avr2_TRUE@eeprom_asm_sources = \ @HAS_avr2_TRUE@ eerd_block.S \ @HAS_avr2_TRUE@ eerd_byte.S \ @HAS_avr2_TRUE@ eerd_dword.S \ @HAS_avr2_TRUE@ eerd_word.S \ @HAS_avr2_TRUE@ eeupd_block.S \ @HAS_avr2_TRUE@ eeupd_byte.S \ @HAS_avr2_TRUE@ eeupd_dword.S \ @HAS_avr2_TRUE@ eeupd_word.S \ @HAS_avr2_TRUE@ eewr_block.S \ @HAS_avr2_TRUE@ eewr_byte.S \ @HAS_avr2_TRUE@ eewr_dword.S \ @HAS_avr2_TRUE@ eewr_word.S @HAS_avr2_TRUE@misc_a_asm_sources = \ @HAS_avr2_TRUE@ itoa.S \ @HAS_avr2_TRUE@ ltoa.S \ @HAS_avr2_TRUE@ mulsi10.S \ @HAS_avr2_TRUE@ mul10.S \ @HAS_avr2_TRUE@ ultoa.S \ @HAS_avr2_TRUE@ utoa.S @HAS_avr2_TRUE@misc_a_extra_dist = \ @HAS_avr2_TRUE@ eedef.h \ @HAS_avr2_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avr2_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avr2_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avr2_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avr2_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avr2_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avr2_TRUE@misc_a_libadd = \ @HAS_avr2_TRUE@ $(eeprom_asm_objlist) @HAS_avr2_TRUE@stdio_a_c_sources = \ @HAS_avr2_TRUE@ clearerr.c \ @HAS_avr2_TRUE@ fclose.c \ @HAS_avr2_TRUE@ fdevopen.c \ @HAS_avr2_TRUE@ feof.c \ @HAS_avr2_TRUE@ ferror.c \ @HAS_avr2_TRUE@ fgetc.c \ @HAS_avr2_TRUE@ fgets.c \ @HAS_avr2_TRUE@ fprintf.c \ @HAS_avr2_TRUE@ fprintf_p.c \ @HAS_avr2_TRUE@ fputc.c \ @HAS_avr2_TRUE@ fputs.c \ @HAS_avr2_TRUE@ fputs_p.c \ @HAS_avr2_TRUE@ fread.c \ @HAS_avr2_TRUE@ fscanf.c \ @HAS_avr2_TRUE@ fscanf_p.c \ @HAS_avr2_TRUE@ fwrite.c \ @HAS_avr2_TRUE@ getchar.c \ @HAS_avr2_TRUE@ gets.c \ @HAS_avr2_TRUE@ iob.c \ @HAS_avr2_TRUE@ printf.c \ @HAS_avr2_TRUE@ printf_p.c \ @HAS_avr2_TRUE@ putchar.c \ @HAS_avr2_TRUE@ puts.c \ @HAS_avr2_TRUE@ puts_p.c \ @HAS_avr2_TRUE@ scanf.c \ @HAS_avr2_TRUE@ scanf_p.c \ @HAS_avr2_TRUE@ snprintf.c \ @HAS_avr2_TRUE@ snprintf_p.c \ @HAS_avr2_TRUE@ sprintf.c \ @HAS_avr2_TRUE@ sprintf_p.c \ @HAS_avr2_TRUE@ sscanf.c \ @HAS_avr2_TRUE@ sscanf_p.c \ @HAS_avr2_TRUE@ vfprintf_p.c \ @HAS_avr2_TRUE@ vfscanf_p.c \ @HAS_avr2_TRUE@ vprintf.c \ @HAS_avr2_TRUE@ vscanf.c \ @HAS_avr2_TRUE@ vsnprintf.c \ @HAS_avr2_TRUE@ vsnprintf_p.c \ @HAS_avr2_TRUE@ vsprintf.c \ @HAS_avr2_TRUE@ vsprintf_p.c \ @HAS_avr2_TRUE@ ungetc.c @HAS_avr2_TRUE@stdio_a_asm_sources = \ @HAS_avr2_TRUE@ getc.S \ @HAS_avr2_TRUE@ putc.S \ @HAS_avr2_TRUE@ ultoa_invert.S @HAS_avr2_TRUE@stdio_a_extra_dist = \ @HAS_avr2_TRUE@ vfprintf.c \ @HAS_avr2_TRUE@ vfscanf.c \ @HAS_avr2_TRUE@ stdio_private.h \ @HAS_avr2_TRUE@ xtoa_fast.h @HAS_avr2_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avr2_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avr2_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avr2_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avr2_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avr2_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avr2_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avr2_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avr2_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avr2_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avr2_TRUE@libm_a_c_sources = @HAS_avr2_TRUE@libm_a_asm_sources = \ @HAS_avr2_TRUE@ acos.S \ @HAS_avr2_TRUE@ addsf3.S \ @HAS_avr2_TRUE@ addsf3x.S \ @HAS_avr2_TRUE@ asin.S \ @HAS_avr2_TRUE@ atan2.S \ @HAS_avr2_TRUE@ atan.S \ @HAS_avr2_TRUE@ cbrt.S \ @HAS_avr2_TRUE@ ceil.S \ @HAS_avr2_TRUE@ cmpsf2.S \ @HAS_avr2_TRUE@ copysign.S \ @HAS_avr2_TRUE@ cosh.S \ @HAS_avr2_TRUE@ cos.S \ @HAS_avr2_TRUE@ divsf3.S \ @HAS_avr2_TRUE@ divsf3x.S \ @HAS_avr2_TRUE@ exp.S \ @HAS_avr2_TRUE@ fixsfdi.S \ @HAS_avr2_TRUE@ fixsfsi.S \ @HAS_avr2_TRUE@ fixunssfsi.S \ @HAS_avr2_TRUE@ floatdisf.S \ @HAS_avr2_TRUE@ floatsisf.S \ @HAS_avr2_TRUE@ floatundisf.S \ @HAS_avr2_TRUE@ fdim.S \ @HAS_avr2_TRUE@ floor.S \ @HAS_avr2_TRUE@ fma.S \ @HAS_avr2_TRUE@ fmax.S \ @HAS_avr2_TRUE@ fmin.S \ @HAS_avr2_TRUE@ fmod.S \ @HAS_avr2_TRUE@ fp_arccos.S \ @HAS_avr2_TRUE@ fp_cmp.S \ @HAS_avr2_TRUE@ fp_inf.S \ @HAS_avr2_TRUE@ fp_mintl.S \ @HAS_avr2_TRUE@ fp_mpack.S \ @HAS_avr2_TRUE@ fp_nan.S \ @HAS_avr2_TRUE@ fp_negdi.S \ @HAS_avr2_TRUE@ fp_norm2.S \ @HAS_avr2_TRUE@ fp_powser.S \ @HAS_avr2_TRUE@ fp_powsodd.S \ @HAS_avr2_TRUE@ fp_pscA.S \ @HAS_avr2_TRUE@ fp_pscB.S \ @HAS_avr2_TRUE@ fp_rempio2.S \ @HAS_avr2_TRUE@ fp_round.S \ @HAS_avr2_TRUE@ fp_sinus.S \ @HAS_avr2_TRUE@ fp_split3.S \ @HAS_avr2_TRUE@ fp_trunc.S \ @HAS_avr2_TRUE@ fp_zero.S \ @HAS_avr2_TRUE@ frexp.S \ @HAS_avr2_TRUE@ gesf2.S \ @HAS_avr2_TRUE@ hypot.S \ @HAS_avr2_TRUE@ inverse.S \ @HAS_avr2_TRUE@ isfinite.S \ @HAS_avr2_TRUE@ isinf.S \ @HAS_avr2_TRUE@ isnan.S \ @HAS_avr2_TRUE@ ldexp.S \ @HAS_avr2_TRUE@ log10.S \ @HAS_avr2_TRUE@ log.S \ @HAS_avr2_TRUE@ lrint.S \ @HAS_avr2_TRUE@ lround.S \ @HAS_avr2_TRUE@ modf.S \ @HAS_avr2_TRUE@ mulsf3.S \ @HAS_avr2_TRUE@ mulsf3x.S \ @HAS_avr2_TRUE@ negsf2.S \ @HAS_avr2_TRUE@ pow.S \ @HAS_avr2_TRUE@ round.S \ @HAS_avr2_TRUE@ signbit.S \ @HAS_avr2_TRUE@ sinh.S \ @HAS_avr2_TRUE@ sin.S \ @HAS_avr2_TRUE@ sqrt.S \ @HAS_avr2_TRUE@ square.S \ @HAS_avr2_TRUE@ tanh.S \ @HAS_avr2_TRUE@ tan.S \ @HAS_avr2_TRUE@ trunc.S \ @HAS_avr2_TRUE@ unordsf2.S @HAS_avr2_TRUE@libm_a_extra_dist = \ @HAS_avr2_TRUE@ asmdef.h \ @HAS_avr2_TRUE@ fp32def.h \ @HAS_avr2_TRUE@ ntz.h @HAS_avr2_TRUE@nodist_libc_a_SOURCES = \ @HAS_avr2_TRUE@ $(stdlib_a_c_sources) \ @HAS_avr2_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avr2_TRUE@ $(pmstring_a_c_sources) \ @HAS_avr2_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avr2_TRUE@ $(string_a_c_sources) \ @HAS_avr2_TRUE@ $(string_a_asm_sources) \ @HAS_avr2_TRUE@ $(misc_a_c_sources) \ @HAS_avr2_TRUE@ $(misc_a_asm_sources) \ @HAS_avr2_TRUE@ $(stdio_a_c_sources) \ @HAS_avr2_TRUE@ $(stdio_a_asm_sources) \ @HAS_avr2_TRUE@ $(libm_a_c_sources) \ @HAS_avr2_TRUE@ $(libm_a_asm_sources) @HAS_avr2_TRUE@nodist_libm_a_SOURCES = \ @HAS_avr2_TRUE@ $(libm_a_c_sources) \ @HAS_avr2_TRUE@ $(libm_a_asm_sources) @HAS_avr2_TRUE@libc_a_LIBADD = \ @HAS_avr2_TRUE@ $(stdio_a_libadd) \ @HAS_avr2_TRUE@ $(misc_a_libadd) @HAS_avr2_TRUE@libc_a_DEPENDENCIES = \ @HAS_avr2_TRUE@ $(stdio_a_libadd) \ @HAS_avr2_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am $(top_srcdir)/libc/misc/Rules.am $(top_srcdir)/libc/misc/Files.am $(top_srcdir)/libc/stdio/Rules.am $(top_srcdir)/libc/stdio/Files.am $(top_srcdir)/libm/fplib/Rules.am $(top_srcdir)/libm/fplib/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign avr/lib/avr2/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign avr/lib/avr2/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; 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conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : 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$(AVRLIB_ASFLAGS) @HAS_avrxmega4_TRUE@__install_dir = $(prefix)/avr/lib/$(AVR_INSTALL_DIR) @HAS_avrxmega4_TRUE@avrdir = $(__install_dir) @HAS_avrxmega4_TRUE@avrlibdir = $(__install_dir) @HAS_avrxmega4_TRUE@avr_LIBRARIES = \ @HAS_avrxmega4_TRUE@ libc.a \ @HAS_avrxmega4_TRUE@ libprintf_min.a \ @HAS_avrxmega4_TRUE@ libprintf_flt.a \ @HAS_avrxmega4_TRUE@ libscanf_min.a \ @HAS_avrxmega4_TRUE@ libscanf_flt.a \ @HAS_avrxmega4_TRUE@ libm.a @HAS_avrxmega4_TRUE@stdlib_a_c_sources = \ @HAS_avrxmega4_TRUE@ abs.c \ @HAS_avrxmega4_TRUE@ assert.c \ @HAS_avrxmega4_TRUE@ bsearch.c \ @HAS_avrxmega4_TRUE@ calloc.c \ @HAS_avrxmega4_TRUE@ errno.c \ @HAS_avrxmega4_TRUE@ dtoa_prf.c \ @HAS_avrxmega4_TRUE@ dtostre.c \ @HAS_avrxmega4_TRUE@ dtostrf.c \ @HAS_avrxmega4_TRUE@ labs.c \ @HAS_avrxmega4_TRUE@ malloc.c \ @HAS_avrxmega4_TRUE@ qsort.c \ @HAS_avrxmega4_TRUE@ rand.c \ @HAS_avrxmega4_TRUE@ random.c \ @HAS_avrxmega4_TRUE@ realloc.c \ @HAS_avrxmega4_TRUE@ strtod.c \ @HAS_avrxmega4_TRUE@ strtol.c \ @HAS_avrxmega4_TRUE@ strtoul.c \ @HAS_avrxmega4_TRUE@ dtoa_conv.h \ @HAS_avrxmega4_TRUE@ stdlib_private.h @HAS_avrxmega4_TRUE@stdlib_a_asm_sources = \ @HAS_avrxmega4_TRUE@ abort.S \ @HAS_avrxmega4_TRUE@ atof.S \ @HAS_avrxmega4_TRUE@ atoi.S \ @HAS_avrxmega4_TRUE@ atol.S \ @HAS_avrxmega4_TRUE@ div.S \ @HAS_avrxmega4_TRUE@ exit.S \ @HAS_avrxmega4_TRUE@ ftoa_engine.S \ @HAS_avrxmega4_TRUE@ ldiv.S \ @HAS_avrxmega4_TRUE@ setjmp.S \ @HAS_avrxmega4_TRUE@ isascii.S \ @HAS_avrxmega4_TRUE@ toascii.S \ @HAS_avrxmega4_TRUE@ isalnum.S \ @HAS_avrxmega4_TRUE@ cty_isfalse.S \ @HAS_avrxmega4_TRUE@ isalpha.S \ @HAS_avrxmega4_TRUE@ isdigit.S \ @HAS_avrxmega4_TRUE@ isxdigit.S \ @HAS_avrxmega4_TRUE@ iscntrl.S \ @HAS_avrxmega4_TRUE@ isprint.S \ @HAS_avrxmega4_TRUE@ isspace.S \ @HAS_avrxmega4_TRUE@ isblank.S \ @HAS_avrxmega4_TRUE@ ispunct.S \ @HAS_avrxmega4_TRUE@ tolower.S \ @HAS_avrxmega4_TRUE@ toupper.S @HAS_avrxmega4_TRUE@stdlib_a_extra_dist = \ @HAS_avrxmega4_TRUE@ ctype.S \ @HAS_avrxmega4_TRUE@ abort.c \ @HAS_avrxmega4_TRUE@ atoi.c \ @HAS_avrxmega4_TRUE@ atol.c @HAS_avrxmega4_TRUE@pmstring_a_c_sources = \ @HAS_avrxmega4_TRUE@ strtok_P.c @HAS_avrxmega4_TRUE@pmstring_a_asm_sources = \ @HAS_avrxmega4_TRUE@ memchr_P.S \ @HAS_avrxmega4_TRUE@ memcmp_P.S \ @HAS_avrxmega4_TRUE@ memccpy_P.S \ @HAS_avrxmega4_TRUE@ memcpy_P.S \ @HAS_avrxmega4_TRUE@ memrchr_P.S \ @HAS_avrxmega4_TRUE@ strcasecmp_P.S \ @HAS_avrxmega4_TRUE@ strcat_P.S \ @HAS_avrxmega4_TRUE@ strchr_P.S \ @HAS_avrxmega4_TRUE@ strchrnul_P.S \ @HAS_avrxmega4_TRUE@ strcmp_P.S \ @HAS_avrxmega4_TRUE@ strcpy_P.S \ @HAS_avrxmega4_TRUE@ strcspn_P.S \ @HAS_avrxmega4_TRUE@ strlcat_P.S \ @HAS_avrxmega4_TRUE@ strlcpy_P.S \ @HAS_avrxmega4_TRUE@ strlen_P.S \ @HAS_avrxmega4_TRUE@ strncasecmp_P.S \ @HAS_avrxmega4_TRUE@ strncat_P.S \ @HAS_avrxmega4_TRUE@ strncmp_P.S \ @HAS_avrxmega4_TRUE@ strncpy_P.S \ @HAS_avrxmega4_TRUE@ strnlen_P.S \ @HAS_avrxmega4_TRUE@ strpbrk_P.S \ @HAS_avrxmega4_TRUE@ strrchr_P.S \ @HAS_avrxmega4_TRUE@ strsep_P.S \ @HAS_avrxmega4_TRUE@ strspn_P.S \ @HAS_avrxmega4_TRUE@ strstr_P.S \ @HAS_avrxmega4_TRUE@ strtok_rP.S \ @HAS_avrxmega4_TRUE@ memcpy_PF.S \ @HAS_avrxmega4_TRUE@ strcasecmp_PF.S \ @HAS_avrxmega4_TRUE@ strcat_PF.S \ @HAS_avrxmega4_TRUE@ strcmp_PF.S \ @HAS_avrxmega4_TRUE@ strcpy_PF.S \ @HAS_avrxmega4_TRUE@ strlcat_PF.S \ @HAS_avrxmega4_TRUE@ strlcpy_PF.S \ @HAS_avrxmega4_TRUE@ strlen_PF.S \ @HAS_avrxmega4_TRUE@ strncasecmp_PF.S \ @HAS_avrxmega4_TRUE@ strncat_PF.S \ @HAS_avrxmega4_TRUE@ strncmp_PF.S \ @HAS_avrxmega4_TRUE@ strncpy_PF.S \ @HAS_avrxmega4_TRUE@ strnlen_PF.S \ @HAS_avrxmega4_TRUE@ strstr_PF.S \ @HAS_avrxmega4_TRUE@ memcmp_PF.S @HAS_avrxmega4_TRUE@string_a_c_sources = \ @HAS_avrxmega4_TRUE@ strdup.c \ @HAS_avrxmega4_TRUE@ strtok.c @HAS_avrxmega4_TRUE@string_a_asm_sources = \ @HAS_avrxmega4_TRUE@ ffs.S \ @HAS_avrxmega4_TRUE@ ffsl.S \ @HAS_avrxmega4_TRUE@ ffsll.S \ @HAS_avrxmega4_TRUE@ memccpy.S \ @HAS_avrxmega4_TRUE@ memchr.S \ @HAS_avrxmega4_TRUE@ memcmp.S \ @HAS_avrxmega4_TRUE@ memcpy.S \ @HAS_avrxmega4_TRUE@ memmem.S \ @HAS_avrxmega4_TRUE@ memmem_P.S \ @HAS_avrxmega4_TRUE@ memmove.S \ @HAS_avrxmega4_TRUE@ memrchr.S \ @HAS_avrxmega4_TRUE@ memset.S \ @HAS_avrxmega4_TRUE@ strcasecmp.S \ @HAS_avrxmega4_TRUE@ strcasestr.S \ @HAS_avrxmega4_TRUE@ strcasestr_P.S \ @HAS_avrxmega4_TRUE@ strcat.S \ @HAS_avrxmega4_TRUE@ strchr.S \ @HAS_avrxmega4_TRUE@ strchrnul.S \ @HAS_avrxmega4_TRUE@ strcmp.S \ @HAS_avrxmega4_TRUE@ strcpy.S \ @HAS_avrxmega4_TRUE@ strcspn.S \ @HAS_avrxmega4_TRUE@ strlcat.S \ @HAS_avrxmega4_TRUE@ strlcpy.S \ @HAS_avrxmega4_TRUE@ strlen.S \ @HAS_avrxmega4_TRUE@ strlwr.S \ @HAS_avrxmega4_TRUE@ strncasecmp.S \ @HAS_avrxmega4_TRUE@ strncat.S \ @HAS_avrxmega4_TRUE@ strncmp.S \ @HAS_avrxmega4_TRUE@ strncpy.S \ @HAS_avrxmega4_TRUE@ strnlen.S \ @HAS_avrxmega4_TRUE@ strpbrk.S \ @HAS_avrxmega4_TRUE@ strrchr.S \ @HAS_avrxmega4_TRUE@ strrev.S \ @HAS_avrxmega4_TRUE@ strsep.S \ @HAS_avrxmega4_TRUE@ strspn.S \ @HAS_avrxmega4_TRUE@ strstr.S \ @HAS_avrxmega4_TRUE@ strtok_r.S \ @HAS_avrxmega4_TRUE@ strupr.S @HAS_avrxmega4_TRUE@string_a_extra_dist = \ @HAS_avrxmega4_TRUE@ strlcat.c \ @HAS_avrxmega4_TRUE@ strlcpy.c @HAS_avrxmega4_TRUE@misc_a_c_sources = @HAS_avrxmega4_TRUE@eeprom_asm_sources = \ @HAS_avrxmega4_TRUE@ eerd_block.S \ @HAS_avrxmega4_TRUE@ eerd_byte.S \ @HAS_avrxmega4_TRUE@ eerd_dword.S \ @HAS_avrxmega4_TRUE@ eerd_word.S \ @HAS_avrxmega4_TRUE@ eeupd_block.S \ @HAS_avrxmega4_TRUE@ eeupd_byte.S \ @HAS_avrxmega4_TRUE@ eeupd_dword.S \ @HAS_avrxmega4_TRUE@ eeupd_word.S \ @HAS_avrxmega4_TRUE@ eewr_block.S \ @HAS_avrxmega4_TRUE@ eewr_byte.S \ @HAS_avrxmega4_TRUE@ eewr_dword.S \ @HAS_avrxmega4_TRUE@ eewr_word.S @HAS_avrxmega4_TRUE@misc_a_asm_sources = \ @HAS_avrxmega4_TRUE@ itoa.S \ @HAS_avrxmega4_TRUE@ ltoa.S \ @HAS_avrxmega4_TRUE@ mulsi10.S \ @HAS_avrxmega4_TRUE@ mul10.S \ @HAS_avrxmega4_TRUE@ ultoa.S \ @HAS_avrxmega4_TRUE@ utoa.S @HAS_avrxmega4_TRUE@misc_a_extra_dist = \ @HAS_avrxmega4_TRUE@ eedef.h \ @HAS_avrxmega4_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avrxmega4_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avrxmega4_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avrxmega4_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avrxmega4_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avrxmega4_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avrxmega4_TRUE@misc_a_libadd = \ @HAS_avrxmega4_TRUE@ $(eeprom_asm_objlist) @HAS_avrxmega4_TRUE@stdio_a_c_sources = \ @HAS_avrxmega4_TRUE@ clearerr.c \ @HAS_avrxmega4_TRUE@ fclose.c \ @HAS_avrxmega4_TRUE@ fdevopen.c \ @HAS_avrxmega4_TRUE@ feof.c \ @HAS_avrxmega4_TRUE@ ferror.c \ @HAS_avrxmega4_TRUE@ fgetc.c \ @HAS_avrxmega4_TRUE@ fgets.c \ @HAS_avrxmega4_TRUE@ fprintf.c \ @HAS_avrxmega4_TRUE@ fprintf_p.c \ @HAS_avrxmega4_TRUE@ fputc.c \ @HAS_avrxmega4_TRUE@ fputs.c \ @HAS_avrxmega4_TRUE@ fputs_p.c \ @HAS_avrxmega4_TRUE@ fread.c \ @HAS_avrxmega4_TRUE@ fscanf.c \ @HAS_avrxmega4_TRUE@ fscanf_p.c \ @HAS_avrxmega4_TRUE@ fwrite.c \ @HAS_avrxmega4_TRUE@ getchar.c \ @HAS_avrxmega4_TRUE@ gets.c \ @HAS_avrxmega4_TRUE@ iob.c \ @HAS_avrxmega4_TRUE@ printf.c \ @HAS_avrxmega4_TRUE@ printf_p.c \ @HAS_avrxmega4_TRUE@ putchar.c \ @HAS_avrxmega4_TRUE@ puts.c \ @HAS_avrxmega4_TRUE@ puts_p.c \ @HAS_avrxmega4_TRUE@ scanf.c \ @HAS_avrxmega4_TRUE@ scanf_p.c \ @HAS_avrxmega4_TRUE@ snprintf.c \ @HAS_avrxmega4_TRUE@ snprintf_p.c \ @HAS_avrxmega4_TRUE@ sprintf.c \ @HAS_avrxmega4_TRUE@ sprintf_p.c \ @HAS_avrxmega4_TRUE@ sscanf.c \ @HAS_avrxmega4_TRUE@ sscanf_p.c \ @HAS_avrxmega4_TRUE@ vfprintf_p.c \ @HAS_avrxmega4_TRUE@ vfscanf_p.c \ @HAS_avrxmega4_TRUE@ vprintf.c \ @HAS_avrxmega4_TRUE@ vscanf.c \ @HAS_avrxmega4_TRUE@ vsnprintf.c \ @HAS_avrxmega4_TRUE@ vsnprintf_p.c \ @HAS_avrxmega4_TRUE@ vsprintf.c \ @HAS_avrxmega4_TRUE@ vsprintf_p.c \ @HAS_avrxmega4_TRUE@ ungetc.c @HAS_avrxmega4_TRUE@stdio_a_asm_sources = \ @HAS_avrxmega4_TRUE@ getc.S \ @HAS_avrxmega4_TRUE@ putc.S \ @HAS_avrxmega4_TRUE@ ultoa_invert.S @HAS_avrxmega4_TRUE@stdio_a_extra_dist = \ @HAS_avrxmega4_TRUE@ vfprintf.c \ @HAS_avrxmega4_TRUE@ vfscanf.c \ @HAS_avrxmega4_TRUE@ stdio_private.h \ @HAS_avrxmega4_TRUE@ xtoa_fast.h @HAS_avrxmega4_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avrxmega4_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avrxmega4_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avrxmega4_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avrxmega4_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avrxmega4_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avrxmega4_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avrxmega4_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avrxmega4_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avrxmega4_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avrxmega4_TRUE@libm_a_c_sources = @HAS_avrxmega4_TRUE@libm_a_asm_sources = \ @HAS_avrxmega4_TRUE@ acos.S \ @HAS_avrxmega4_TRUE@ addsf3.S \ @HAS_avrxmega4_TRUE@ addsf3x.S \ @HAS_avrxmega4_TRUE@ asin.S \ @HAS_avrxmega4_TRUE@ atan2.S \ @HAS_avrxmega4_TRUE@ atan.S \ @HAS_avrxmega4_TRUE@ cbrt.S \ @HAS_avrxmega4_TRUE@ ceil.S \ @HAS_avrxmega4_TRUE@ cmpsf2.S \ @HAS_avrxmega4_TRUE@ copysign.S \ @HAS_avrxmega4_TRUE@ cosh.S \ @HAS_avrxmega4_TRUE@ cos.S \ @HAS_avrxmega4_TRUE@ divsf3.S \ @HAS_avrxmega4_TRUE@ divsf3x.S \ @HAS_avrxmega4_TRUE@ exp.S \ @HAS_avrxmega4_TRUE@ fixsfdi.S \ @HAS_avrxmega4_TRUE@ fixsfsi.S \ @HAS_avrxmega4_TRUE@ fixunssfsi.S \ @HAS_avrxmega4_TRUE@ floatdisf.S \ @HAS_avrxmega4_TRUE@ floatsisf.S \ @HAS_avrxmega4_TRUE@ floatundisf.S \ @HAS_avrxmega4_TRUE@ fdim.S \ @HAS_avrxmega4_TRUE@ floor.S \ @HAS_avrxmega4_TRUE@ fma.S \ @HAS_avrxmega4_TRUE@ fmax.S \ @HAS_avrxmega4_TRUE@ fmin.S \ @HAS_avrxmega4_TRUE@ fmod.S \ @HAS_avrxmega4_TRUE@ fp_arccos.S \ @HAS_avrxmega4_TRUE@ fp_cmp.S \ @HAS_avrxmega4_TRUE@ fp_inf.S \ @HAS_avrxmega4_TRUE@ fp_mintl.S \ @HAS_avrxmega4_TRUE@ fp_mpack.S \ @HAS_avrxmega4_TRUE@ fp_nan.S \ @HAS_avrxmega4_TRUE@ fp_negdi.S \ @HAS_avrxmega4_TRUE@ fp_norm2.S \ @HAS_avrxmega4_TRUE@ fp_powser.S \ @HAS_avrxmega4_TRUE@ fp_powsodd.S \ @HAS_avrxmega4_TRUE@ fp_pscA.S \ @HAS_avrxmega4_TRUE@ fp_pscB.S \ @HAS_avrxmega4_TRUE@ fp_rempio2.S \ @HAS_avrxmega4_TRUE@ fp_round.S \ @HAS_avrxmega4_TRUE@ fp_sinus.S \ @HAS_avrxmega4_TRUE@ fp_split3.S \ @HAS_avrxmega4_TRUE@ fp_trunc.S \ @HAS_avrxmega4_TRUE@ fp_zero.S \ @HAS_avrxmega4_TRUE@ frexp.S \ @HAS_avrxmega4_TRUE@ gesf2.S \ @HAS_avrxmega4_TRUE@ hypot.S \ @HAS_avrxmega4_TRUE@ inverse.S \ @HAS_avrxmega4_TRUE@ isfinite.S \ @HAS_avrxmega4_TRUE@ isinf.S \ @HAS_avrxmega4_TRUE@ isnan.S \ @HAS_avrxmega4_TRUE@ ldexp.S \ @HAS_avrxmega4_TRUE@ log10.S \ @HAS_avrxmega4_TRUE@ log.S \ @HAS_avrxmega4_TRUE@ lrint.S \ @HAS_avrxmega4_TRUE@ lround.S \ @HAS_avrxmega4_TRUE@ modf.S \ @HAS_avrxmega4_TRUE@ mulsf3.S \ @HAS_avrxmega4_TRUE@ mulsf3x.S \ @HAS_avrxmega4_TRUE@ negsf2.S \ @HAS_avrxmega4_TRUE@ pow.S \ @HAS_avrxmega4_TRUE@ round.S \ @HAS_avrxmega4_TRUE@ signbit.S \ @HAS_avrxmega4_TRUE@ sinh.S \ @HAS_avrxmega4_TRUE@ sin.S \ @HAS_avrxmega4_TRUE@ sqrt.S \ @HAS_avrxmega4_TRUE@ square.S \ @HAS_avrxmega4_TRUE@ tanh.S \ @HAS_avrxmega4_TRUE@ tan.S \ @HAS_avrxmega4_TRUE@ trunc.S \ @HAS_avrxmega4_TRUE@ unordsf2.S @HAS_avrxmega4_TRUE@libm_a_extra_dist = \ @HAS_avrxmega4_TRUE@ asmdef.h \ @HAS_avrxmega4_TRUE@ fp32def.h \ @HAS_avrxmega4_TRUE@ ntz.h @HAS_avrxmega4_TRUE@nodist_libc_a_SOURCES = \ @HAS_avrxmega4_TRUE@ $(stdlib_a_c_sources) \ @HAS_avrxmega4_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avrxmega4_TRUE@ $(pmstring_a_c_sources) \ @HAS_avrxmega4_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avrxmega4_TRUE@ $(string_a_c_sources) \ @HAS_avrxmega4_TRUE@ $(string_a_asm_sources) \ @HAS_avrxmega4_TRUE@ $(misc_a_c_sources) \ @HAS_avrxmega4_TRUE@ $(misc_a_asm_sources) \ @HAS_avrxmega4_TRUE@ $(stdio_a_c_sources) \ @HAS_avrxmega4_TRUE@ $(stdio_a_asm_sources) \ @HAS_avrxmega4_TRUE@ $(libm_a_c_sources) \ @HAS_avrxmega4_TRUE@ $(libm_a_asm_sources) @HAS_avrxmega4_TRUE@nodist_libm_a_SOURCES = \ @HAS_avrxmega4_TRUE@ $(libm_a_c_sources) \ @HAS_avrxmega4_TRUE@ $(libm_a_asm_sources) @HAS_avrxmega4_TRUE@libc_a_LIBADD = \ @HAS_avrxmega4_TRUE@ $(stdio_a_libadd) \ @HAS_avrxmega4_TRUE@ $(misc_a_libadd) @HAS_avrxmega4_TRUE@libc_a_DEPENDENCIES = \ @HAS_avrxmega4_TRUE@ $(stdio_a_libadd) \ @HAS_avrxmega4_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am 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# distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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@HAS_avr4_TRUE@ eerd_byte.S \ @HAS_avr4_TRUE@ eerd_dword.S \ @HAS_avr4_TRUE@ eerd_word.S \ @HAS_avr4_TRUE@ eeupd_block.S \ @HAS_avr4_TRUE@ eeupd_byte.S \ @HAS_avr4_TRUE@ eeupd_dword.S \ @HAS_avr4_TRUE@ eeupd_word.S \ @HAS_avr4_TRUE@ eewr_block.S \ @HAS_avr4_TRUE@ eewr_byte.S \ @HAS_avr4_TRUE@ eewr_dword.S \ @HAS_avr4_TRUE@ eewr_word.S @HAS_avr4_TRUE@misc_a_asm_sources = \ @HAS_avr4_TRUE@ itoa.S \ @HAS_avr4_TRUE@ ltoa.S \ @HAS_avr4_TRUE@ mulsi10.S \ @HAS_avr4_TRUE@ mul10.S \ @HAS_avr4_TRUE@ ultoa.S \ @HAS_avr4_TRUE@ utoa.S @HAS_avr4_TRUE@misc_a_extra_dist = \ @HAS_avr4_TRUE@ eedef.h \ @HAS_avr4_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avr4_TRUE@eeprom_asm_basenames = $(basename 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distclean \ distclean-compile distclean-generic distclean-tags distdir dvi \ dvi-am html html-am info info-am install install-am \ install-avrLIBRARIES install-data install-data-am install-dvi \ install-dvi-am install-exec install-exec-am install-html \ install-html-am install-info install-info-am install-man \ install-pdf install-pdf-am install-ps install-ps-am \ install-strip installcheck installcheck-am installdirs \ installdirs-am maintainer-clean maintainer-clean-generic \ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \ ps ps-am tags tags-recursive uninstall uninstall-am \ uninstall-avrLIBRARIES # vim: set ft=make: # vim: set ft=make: # vim: set ft=make: # vim: set ft=make: # vim: set ft=make: # vim: set ft=make: # vim: set ft=make: # Example of '-mmcu' arg generation: # $@ --> eerd_byte_atmega48.o # basename --> eerd_byte_atmega48 # subst --> eerd byte atmega48 # lastword --> atmega48 # # Example of source file generation: # $@ --> eerd_byte_atmega48.o # basename --> eerd_byte_atmega48 # subst --> eerd.byte.atmega48 # basename --> eerd.byte # subst --> eerd_byte # addsuffix --> eerd_byte.S # @HAS_avr4_TRUE@$(eeprom_asm_objlist): $(eeprom_asm_sources) @HAS_avr4_TRUE@ $(filter-out -mmcu=%,$(COMPILE) $(AVRLIB_ASFLAGS)) -c -o $@ \ @HAS_avr4_TRUE@ -mmcu=$(lastword $(subst _, ,$(basename $@))) \ @HAS_avr4_TRUE@ $( # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : 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@HAS_avrxmega5_TRUE@ strspn_P.S \ @HAS_avrxmega5_TRUE@ strstr_P.S \ @HAS_avrxmega5_TRUE@ strtok_rP.S \ @HAS_avrxmega5_TRUE@ memcpy_PF.S \ @HAS_avrxmega5_TRUE@ strcasecmp_PF.S \ @HAS_avrxmega5_TRUE@ strcat_PF.S \ @HAS_avrxmega5_TRUE@ strcmp_PF.S \ @HAS_avrxmega5_TRUE@ strcpy_PF.S \ @HAS_avrxmega5_TRUE@ strlcat_PF.S \ @HAS_avrxmega5_TRUE@ strlcpy_PF.S \ @HAS_avrxmega5_TRUE@ strlen_PF.S \ @HAS_avrxmega5_TRUE@ strncasecmp_PF.S \ @HAS_avrxmega5_TRUE@ strncat_PF.S \ @HAS_avrxmega5_TRUE@ strncmp_PF.S \ @HAS_avrxmega5_TRUE@ strncpy_PF.S \ @HAS_avrxmega5_TRUE@ strnlen_PF.S \ @HAS_avrxmega5_TRUE@ strstr_PF.S \ @HAS_avrxmega5_TRUE@ memcmp_PF.S @HAS_avrxmega5_TRUE@string_a_c_sources = \ @HAS_avrxmega5_TRUE@ strdup.c \ @HAS_avrxmega5_TRUE@ strtok.c @HAS_avrxmega5_TRUE@string_a_asm_sources = \ @HAS_avrxmega5_TRUE@ ffs.S \ @HAS_avrxmega5_TRUE@ ffsl.S \ @HAS_avrxmega5_TRUE@ ffsll.S \ @HAS_avrxmega5_TRUE@ memccpy.S \ @HAS_avrxmega5_TRUE@ memchr.S \ @HAS_avrxmega5_TRUE@ memcmp.S \ @HAS_avrxmega5_TRUE@ memcpy.S \ @HAS_avrxmega5_TRUE@ memmem.S \ @HAS_avrxmega5_TRUE@ memmem_P.S \ @HAS_avrxmega5_TRUE@ memmove.S \ @HAS_avrxmega5_TRUE@ memrchr.S \ @HAS_avrxmega5_TRUE@ memset.S \ @HAS_avrxmega5_TRUE@ strcasecmp.S \ @HAS_avrxmega5_TRUE@ strcasestr.S \ @HAS_avrxmega5_TRUE@ strcasestr_P.S \ @HAS_avrxmega5_TRUE@ strcat.S \ @HAS_avrxmega5_TRUE@ strchr.S \ @HAS_avrxmega5_TRUE@ strchrnul.S \ @HAS_avrxmega5_TRUE@ strcmp.S \ @HAS_avrxmega5_TRUE@ strcpy.S \ @HAS_avrxmega5_TRUE@ strcspn.S \ @HAS_avrxmega5_TRUE@ strlcat.S \ @HAS_avrxmega5_TRUE@ strlcpy.S \ @HAS_avrxmega5_TRUE@ strlen.S \ @HAS_avrxmega5_TRUE@ strlwr.S \ @HAS_avrxmega5_TRUE@ strncasecmp.S \ @HAS_avrxmega5_TRUE@ strncat.S \ @HAS_avrxmega5_TRUE@ strncmp.S \ @HAS_avrxmega5_TRUE@ strncpy.S \ @HAS_avrxmega5_TRUE@ strnlen.S \ @HAS_avrxmega5_TRUE@ strpbrk.S \ @HAS_avrxmega5_TRUE@ strrchr.S \ @HAS_avrxmega5_TRUE@ strrev.S \ @HAS_avrxmega5_TRUE@ strsep.S \ @HAS_avrxmega5_TRUE@ strspn.S \ @HAS_avrxmega5_TRUE@ strstr.S \ @HAS_avrxmega5_TRUE@ strtok_r.S \ @HAS_avrxmega5_TRUE@ strupr.S @HAS_avrxmega5_TRUE@string_a_extra_dist = \ @HAS_avrxmega5_TRUE@ strlcat.c \ @HAS_avrxmega5_TRUE@ strlcpy.c @HAS_avrxmega5_TRUE@misc_a_c_sources = @HAS_avrxmega5_TRUE@eeprom_asm_sources = \ @HAS_avrxmega5_TRUE@ eerd_block.S \ @HAS_avrxmega5_TRUE@ eerd_byte.S \ @HAS_avrxmega5_TRUE@ eerd_dword.S \ @HAS_avrxmega5_TRUE@ eerd_word.S \ @HAS_avrxmega5_TRUE@ eeupd_block.S \ @HAS_avrxmega5_TRUE@ eeupd_byte.S \ @HAS_avrxmega5_TRUE@ eeupd_dword.S \ @HAS_avrxmega5_TRUE@ eeupd_word.S \ @HAS_avrxmega5_TRUE@ eewr_block.S \ @HAS_avrxmega5_TRUE@ eewr_byte.S \ @HAS_avrxmega5_TRUE@ eewr_dword.S \ @HAS_avrxmega5_TRUE@ eewr_word.S @HAS_avrxmega5_TRUE@misc_a_asm_sources = \ @HAS_avrxmega5_TRUE@ itoa.S \ @HAS_avrxmega5_TRUE@ ltoa.S \ @HAS_avrxmega5_TRUE@ mulsi10.S \ @HAS_avrxmega5_TRUE@ mul10.S \ @HAS_avrxmega5_TRUE@ ultoa.S \ @HAS_avrxmega5_TRUE@ utoa.S @HAS_avrxmega5_TRUE@misc_a_extra_dist = \ @HAS_avrxmega5_TRUE@ eedef.h \ @HAS_avrxmega5_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avrxmega5_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avrxmega5_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avrxmega5_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avrxmega5_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avrxmega5_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avrxmega5_TRUE@misc_a_libadd = \ @HAS_avrxmega5_TRUE@ $(eeprom_asm_objlist) @HAS_avrxmega5_TRUE@stdio_a_c_sources = \ @HAS_avrxmega5_TRUE@ clearerr.c \ @HAS_avrxmega5_TRUE@ fclose.c \ @HAS_avrxmega5_TRUE@ fdevopen.c \ @HAS_avrxmega5_TRUE@ feof.c \ @HAS_avrxmega5_TRUE@ ferror.c \ @HAS_avrxmega5_TRUE@ fgetc.c \ @HAS_avrxmega5_TRUE@ fgets.c \ @HAS_avrxmega5_TRUE@ fprintf.c \ @HAS_avrxmega5_TRUE@ fprintf_p.c \ @HAS_avrxmega5_TRUE@ fputc.c \ @HAS_avrxmega5_TRUE@ fputs.c \ @HAS_avrxmega5_TRUE@ fputs_p.c \ @HAS_avrxmega5_TRUE@ fread.c \ @HAS_avrxmega5_TRUE@ fscanf.c \ @HAS_avrxmega5_TRUE@ fscanf_p.c \ @HAS_avrxmega5_TRUE@ fwrite.c \ @HAS_avrxmega5_TRUE@ getchar.c \ @HAS_avrxmega5_TRUE@ gets.c \ @HAS_avrxmega5_TRUE@ iob.c \ @HAS_avrxmega5_TRUE@ printf.c \ @HAS_avrxmega5_TRUE@ printf_p.c \ @HAS_avrxmega5_TRUE@ putchar.c \ @HAS_avrxmega5_TRUE@ puts.c \ @HAS_avrxmega5_TRUE@ puts_p.c \ @HAS_avrxmega5_TRUE@ scanf.c \ @HAS_avrxmega5_TRUE@ scanf_p.c \ @HAS_avrxmega5_TRUE@ snprintf.c \ @HAS_avrxmega5_TRUE@ snprintf_p.c \ @HAS_avrxmega5_TRUE@ sprintf.c \ @HAS_avrxmega5_TRUE@ sprintf_p.c \ @HAS_avrxmega5_TRUE@ sscanf.c \ @HAS_avrxmega5_TRUE@ sscanf_p.c \ @HAS_avrxmega5_TRUE@ vfprintf_p.c \ @HAS_avrxmega5_TRUE@ vfscanf_p.c \ @HAS_avrxmega5_TRUE@ vprintf.c \ @HAS_avrxmega5_TRUE@ vscanf.c \ @HAS_avrxmega5_TRUE@ vsnprintf.c \ @HAS_avrxmega5_TRUE@ vsnprintf_p.c \ @HAS_avrxmega5_TRUE@ vsprintf.c \ @HAS_avrxmega5_TRUE@ vsprintf_p.c \ @HAS_avrxmega5_TRUE@ ungetc.c @HAS_avrxmega5_TRUE@stdio_a_asm_sources = \ @HAS_avrxmega5_TRUE@ getc.S \ @HAS_avrxmega5_TRUE@ putc.S \ @HAS_avrxmega5_TRUE@ ultoa_invert.S @HAS_avrxmega5_TRUE@stdio_a_extra_dist = \ @HAS_avrxmega5_TRUE@ vfprintf.c \ @HAS_avrxmega5_TRUE@ vfscanf.c \ @HAS_avrxmega5_TRUE@ stdio_private.h \ @HAS_avrxmega5_TRUE@ xtoa_fast.h @HAS_avrxmega5_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avrxmega5_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avrxmega5_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avrxmega5_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avrxmega5_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avrxmega5_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avrxmega5_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avrxmega5_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avrxmega5_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avrxmega5_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avrxmega5_TRUE@libm_a_c_sources = @HAS_avrxmega5_TRUE@libm_a_asm_sources = \ @HAS_avrxmega5_TRUE@ acos.S \ @HAS_avrxmega5_TRUE@ addsf3.S \ @HAS_avrxmega5_TRUE@ addsf3x.S \ @HAS_avrxmega5_TRUE@ asin.S \ @HAS_avrxmega5_TRUE@ atan2.S \ @HAS_avrxmega5_TRUE@ atan.S \ @HAS_avrxmega5_TRUE@ cbrt.S \ @HAS_avrxmega5_TRUE@ ceil.S \ @HAS_avrxmega5_TRUE@ cmpsf2.S \ @HAS_avrxmega5_TRUE@ copysign.S \ @HAS_avrxmega5_TRUE@ cosh.S \ @HAS_avrxmega5_TRUE@ cos.S \ @HAS_avrxmega5_TRUE@ divsf3.S \ @HAS_avrxmega5_TRUE@ divsf3x.S \ @HAS_avrxmega5_TRUE@ exp.S \ @HAS_avrxmega5_TRUE@ fixsfdi.S \ @HAS_avrxmega5_TRUE@ fixsfsi.S \ @HAS_avrxmega5_TRUE@ fixunssfsi.S \ @HAS_avrxmega5_TRUE@ floatdisf.S \ @HAS_avrxmega5_TRUE@ floatsisf.S \ @HAS_avrxmega5_TRUE@ floatundisf.S \ @HAS_avrxmega5_TRUE@ fdim.S \ @HAS_avrxmega5_TRUE@ floor.S \ @HAS_avrxmega5_TRUE@ fma.S \ @HAS_avrxmega5_TRUE@ fmax.S \ @HAS_avrxmega5_TRUE@ fmin.S \ @HAS_avrxmega5_TRUE@ fmod.S \ @HAS_avrxmega5_TRUE@ fp_arccos.S \ @HAS_avrxmega5_TRUE@ fp_cmp.S \ @HAS_avrxmega5_TRUE@ fp_inf.S \ @HAS_avrxmega5_TRUE@ fp_mintl.S \ @HAS_avrxmega5_TRUE@ fp_mpack.S \ @HAS_avrxmega5_TRUE@ fp_nan.S \ @HAS_avrxmega5_TRUE@ fp_negdi.S \ @HAS_avrxmega5_TRUE@ fp_norm2.S \ @HAS_avrxmega5_TRUE@ fp_powser.S \ @HAS_avrxmega5_TRUE@ fp_powsodd.S \ @HAS_avrxmega5_TRUE@ fp_pscA.S \ @HAS_avrxmega5_TRUE@ fp_pscB.S \ @HAS_avrxmega5_TRUE@ fp_rempio2.S \ @HAS_avrxmega5_TRUE@ fp_round.S \ @HAS_avrxmega5_TRUE@ fp_sinus.S \ @HAS_avrxmega5_TRUE@ fp_split3.S \ @HAS_avrxmega5_TRUE@ fp_trunc.S \ @HAS_avrxmega5_TRUE@ fp_zero.S \ @HAS_avrxmega5_TRUE@ frexp.S \ @HAS_avrxmega5_TRUE@ gesf2.S \ @HAS_avrxmega5_TRUE@ hypot.S \ @HAS_avrxmega5_TRUE@ inverse.S \ @HAS_avrxmega5_TRUE@ isfinite.S \ @HAS_avrxmega5_TRUE@ isinf.S \ @HAS_avrxmega5_TRUE@ isnan.S \ @HAS_avrxmega5_TRUE@ ldexp.S \ @HAS_avrxmega5_TRUE@ log10.S \ @HAS_avrxmega5_TRUE@ log.S \ @HAS_avrxmega5_TRUE@ lrint.S \ @HAS_avrxmega5_TRUE@ lround.S \ @HAS_avrxmega5_TRUE@ modf.S \ @HAS_avrxmega5_TRUE@ mulsf3.S \ @HAS_avrxmega5_TRUE@ mulsf3x.S \ @HAS_avrxmega5_TRUE@ negsf2.S \ @HAS_avrxmega5_TRUE@ pow.S \ @HAS_avrxmega5_TRUE@ round.S \ @HAS_avrxmega5_TRUE@ signbit.S \ @HAS_avrxmega5_TRUE@ sinh.S \ @HAS_avrxmega5_TRUE@ sin.S \ @HAS_avrxmega5_TRUE@ sqrt.S \ @HAS_avrxmega5_TRUE@ square.S \ @HAS_avrxmega5_TRUE@ tanh.S \ @HAS_avrxmega5_TRUE@ tan.S \ @HAS_avrxmega5_TRUE@ trunc.S \ @HAS_avrxmega5_TRUE@ unordsf2.S @HAS_avrxmega5_TRUE@libm_a_extra_dist = \ @HAS_avrxmega5_TRUE@ asmdef.h \ @HAS_avrxmega5_TRUE@ fp32def.h \ @HAS_avrxmega5_TRUE@ ntz.h @HAS_avrxmega5_TRUE@nodist_libc_a_SOURCES = \ @HAS_avrxmega5_TRUE@ $(stdlib_a_c_sources) \ @HAS_avrxmega5_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avrxmega5_TRUE@ $(pmstring_a_c_sources) \ @HAS_avrxmega5_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avrxmega5_TRUE@ $(string_a_c_sources) \ @HAS_avrxmega5_TRUE@ $(string_a_asm_sources) \ @HAS_avrxmega5_TRUE@ $(misc_a_c_sources) \ @HAS_avrxmega5_TRUE@ $(misc_a_asm_sources) \ @HAS_avrxmega5_TRUE@ $(stdio_a_c_sources) \ @HAS_avrxmega5_TRUE@ $(stdio_a_asm_sources) \ @HAS_avrxmega5_TRUE@ $(libm_a_c_sources) \ @HAS_avrxmega5_TRUE@ $(libm_a_asm_sources) @HAS_avrxmega5_TRUE@nodist_libm_a_SOURCES = \ @HAS_avrxmega5_TRUE@ $(libm_a_c_sources) \ @HAS_avrxmega5_TRUE@ $(libm_a_asm_sources) @HAS_avrxmega5_TRUE@libc_a_LIBADD = \ @HAS_avrxmega5_TRUE@ $(stdio_a_libadd) \ @HAS_avrxmega5_TRUE@ $(misc_a_libadd) @HAS_avrxmega5_TRUE@libc_a_DEPENDENCIES = \ @HAS_avrxmega5_TRUE@ $(stdio_a_libadd) \ @HAS_avrxmega5_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am $(top_srcdir)/libc/misc/Rules.am $(top_srcdir)/libc/misc/Files.am $(top_srcdir)/libc/stdio/Rules.am $(top_srcdir)/libc/stdio/Files.am $(top_srcdir)/libm/fplib/Rules.am $(top_srcdir)/libm/fplib/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign avr/lib/avrxmega5/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign avr/lib/avrxmega5/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): install-avrLIBRARIES: $(avr_LIBRARIES) @$(NORMAL_INSTALL) test -z "$(avrdir)" || $(MKDIR_P) "$(DESTDIR)$(avrdir)" @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || list=; \ list2=; for p in $$list; do \ if test -f $$p; then \ list2="$$list2 $$p"; \ else :; fi; \ done; \ test -z "$$list2" || { \ echo " $(INSTALL_DATA) $$list2 '$(DESTDIR)$(avrdir)'"; \ $(INSTALL_DATA) $$list2 "$(DESTDIR)$(avrdir)" || exit $$?; } @$(POST_INSTALL) @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || list=; \ for p in $$list; do \ if test -f $$p; then \ $(am__strip_dir) \ echo " ( cd '$(DESTDIR)$(avrdir)' && $(RANLIB) $$f )"; \ ( cd "$(DESTDIR)$(avrdir)" && $(RANLIB) $$f ) || exit $$?; \ else :; fi; \ done uninstall-avrLIBRARIES: @$(NORMAL_UNINSTALL) @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || list=; \ files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \ test -n "$$files" || exit 0; \ echo " ( cd '$(DESTDIR)$(avrdir)' && rm -f "$$files" )"; \ cd "$(DESTDIR)$(avrdir)" && rm -f $$files clean-avrLIBRARIES: -test -z "$(avr_LIBRARIES)" || rm -f $(avr_LIBRARIES) libc.a: $(libc_a_OBJECTS) $(libc_a_DEPENDENCIES) -rm -f libc.a $(libc_a_AR) libc.a $(libc_a_OBJECTS) $(libc_a_LIBADD) $(RANLIB) libc.a libm.a: $(libm_a_OBJECTS) $(libm_a_DEPENDENCIES) -rm -f libm.a $(libm_a_AR) libm.a $(libm_a_OBJECTS) $(libm_a_LIBADD) $(RANLIB) libm.a libprintf_flt.a: $(libprintf_flt_a_OBJECTS) $(libprintf_flt_a_DEPENDENCIES) -rm -f libprintf_flt.a $(libprintf_flt_a_AR) libprintf_flt.a $(libprintf_flt_a_OBJECTS) $(libprintf_flt_a_LIBADD) $(RANLIB) libprintf_flt.a libprintf_min.a: $(libprintf_min_a_OBJECTS) $(libprintf_min_a_DEPENDENCIES) -rm -f libprintf_min.a $(libprintf_min_a_AR) libprintf_min.a $(libprintf_min_a_OBJECTS) $(libprintf_min_a_LIBADD) $(RANLIB) libprintf_min.a libscanf_flt.a: $(libscanf_flt_a_OBJECTS) $(libscanf_flt_a_DEPENDENCIES) -rm -f libscanf_flt.a $(libscanf_flt_a_AR) libscanf_flt.a $(libscanf_flt_a_OBJECTS) $(libscanf_flt_a_LIBADD) $(RANLIB) libscanf_flt.a libscanf_min.a: $(libscanf_min_a_OBJECTS) $(libscanf_min_a_DEPENDENCIES) -rm -f libscanf_min.a $(libscanf_min_a_AR) libscanf_min.a $(libscanf_min_a_OBJECTS) $(libscanf_min_a_LIBADD) $(RANLIB) libscanf_min.a mostlyclean-compile: -rm -f *.$(OBJEXT) distclean-compile: -rm -f *.tab.c @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/abort.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/abs.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/acos.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/addsf3.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/addsf3x.Po@am__quote@ @AMDEP_TRUE@@am__include@ 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@am__quote@./$(DEPDIR)/cos.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cosh.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cty_isfalse.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/div.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/divsf3.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/divsf3x.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dtoa_prf.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dtostre.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dtostrf.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/errno.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/exit.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/exp.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fclose.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdevopen.Po@am__quote@ @AMDEP_TRUE@@am__include@ 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# distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : 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libscanf_flt.a \ @HAS_avr35_TRUE@ libm.a @HAS_avr35_TRUE@stdlib_a_c_sources = \ @HAS_avr35_TRUE@ abs.c \ @HAS_avr35_TRUE@ assert.c \ @HAS_avr35_TRUE@ bsearch.c \ @HAS_avr35_TRUE@ calloc.c \ @HAS_avr35_TRUE@ errno.c \ @HAS_avr35_TRUE@ dtoa_prf.c \ @HAS_avr35_TRUE@ dtostre.c \ @HAS_avr35_TRUE@ dtostrf.c \ @HAS_avr35_TRUE@ labs.c \ @HAS_avr35_TRUE@ malloc.c \ @HAS_avr35_TRUE@ qsort.c \ @HAS_avr35_TRUE@ rand.c \ @HAS_avr35_TRUE@ random.c \ @HAS_avr35_TRUE@ realloc.c \ @HAS_avr35_TRUE@ strtod.c \ @HAS_avr35_TRUE@ strtol.c \ @HAS_avr35_TRUE@ strtoul.c \ @HAS_avr35_TRUE@ dtoa_conv.h \ @HAS_avr35_TRUE@ stdlib_private.h @HAS_avr35_TRUE@stdlib_a_asm_sources = \ @HAS_avr35_TRUE@ abort.S \ @HAS_avr35_TRUE@ atof.S \ @HAS_avr35_TRUE@ atoi.S \ @HAS_avr35_TRUE@ atol.S \ @HAS_avr35_TRUE@ div.S \ @HAS_avr35_TRUE@ exit.S \ @HAS_avr35_TRUE@ ftoa_engine.S \ @HAS_avr35_TRUE@ ldiv.S \ @HAS_avr35_TRUE@ setjmp.S \ @HAS_avr35_TRUE@ isascii.S \ @HAS_avr35_TRUE@ toascii.S \ @HAS_avr35_TRUE@ isalnum.S \ @HAS_avr35_TRUE@ cty_isfalse.S \ @HAS_avr35_TRUE@ isalpha.S \ @HAS_avr35_TRUE@ isdigit.S \ @HAS_avr35_TRUE@ isxdigit.S \ @HAS_avr35_TRUE@ iscntrl.S \ @HAS_avr35_TRUE@ isprint.S \ @HAS_avr35_TRUE@ isspace.S \ @HAS_avr35_TRUE@ isblank.S \ @HAS_avr35_TRUE@ ispunct.S \ @HAS_avr35_TRUE@ tolower.S \ @HAS_avr35_TRUE@ toupper.S @HAS_avr35_TRUE@stdlib_a_extra_dist = \ @HAS_avr35_TRUE@ ctype.S \ @HAS_avr35_TRUE@ abort.c \ @HAS_avr35_TRUE@ atoi.c \ @HAS_avr35_TRUE@ atol.c @HAS_avr35_TRUE@pmstring_a_c_sources = \ @HAS_avr35_TRUE@ strtok_P.c @HAS_avr35_TRUE@pmstring_a_asm_sources = \ @HAS_avr35_TRUE@ memchr_P.S \ @HAS_avr35_TRUE@ memcmp_P.S \ @HAS_avr35_TRUE@ memccpy_P.S \ @HAS_avr35_TRUE@ memcpy_P.S \ @HAS_avr35_TRUE@ memrchr_P.S \ @HAS_avr35_TRUE@ strcasecmp_P.S \ @HAS_avr35_TRUE@ strcat_P.S \ @HAS_avr35_TRUE@ strchr_P.S \ @HAS_avr35_TRUE@ strchrnul_P.S \ @HAS_avr35_TRUE@ strcmp_P.S \ @HAS_avr35_TRUE@ strcpy_P.S \ @HAS_avr35_TRUE@ strcspn_P.S \ @HAS_avr35_TRUE@ strlcat_P.S \ @HAS_avr35_TRUE@ strlcpy_P.S \ @HAS_avr35_TRUE@ strlen_P.S \ @HAS_avr35_TRUE@ strncasecmp_P.S \ @HAS_avr35_TRUE@ strncat_P.S \ @HAS_avr35_TRUE@ strncmp_P.S \ @HAS_avr35_TRUE@ strncpy_P.S \ @HAS_avr35_TRUE@ strnlen_P.S \ @HAS_avr35_TRUE@ strpbrk_P.S \ @HAS_avr35_TRUE@ strrchr_P.S \ @HAS_avr35_TRUE@ strsep_P.S \ @HAS_avr35_TRUE@ strspn_P.S \ @HAS_avr35_TRUE@ strstr_P.S \ @HAS_avr35_TRUE@ strtok_rP.S \ @HAS_avr35_TRUE@ memcpy_PF.S \ @HAS_avr35_TRUE@ strcasecmp_PF.S \ @HAS_avr35_TRUE@ strcat_PF.S \ @HAS_avr35_TRUE@ strcmp_PF.S \ @HAS_avr35_TRUE@ strcpy_PF.S \ @HAS_avr35_TRUE@ strlcat_PF.S \ @HAS_avr35_TRUE@ strlcpy_PF.S \ @HAS_avr35_TRUE@ strlen_PF.S \ @HAS_avr35_TRUE@ strncasecmp_PF.S \ @HAS_avr35_TRUE@ strncat_PF.S \ @HAS_avr35_TRUE@ strncmp_PF.S \ @HAS_avr35_TRUE@ strncpy_PF.S \ @HAS_avr35_TRUE@ strnlen_PF.S \ @HAS_avr35_TRUE@ strstr_PF.S \ @HAS_avr35_TRUE@ memcmp_PF.S @HAS_avr35_TRUE@string_a_c_sources = \ @HAS_avr35_TRUE@ strdup.c \ @HAS_avr35_TRUE@ strtok.c @HAS_avr35_TRUE@string_a_asm_sources = \ @HAS_avr35_TRUE@ ffs.S \ @HAS_avr35_TRUE@ ffsl.S \ @HAS_avr35_TRUE@ ffsll.S \ @HAS_avr35_TRUE@ memccpy.S \ @HAS_avr35_TRUE@ memchr.S \ @HAS_avr35_TRUE@ memcmp.S \ @HAS_avr35_TRUE@ memcpy.S \ @HAS_avr35_TRUE@ memmem.S \ @HAS_avr35_TRUE@ memmem_P.S \ @HAS_avr35_TRUE@ memmove.S \ @HAS_avr35_TRUE@ memrchr.S \ @HAS_avr35_TRUE@ memset.S \ @HAS_avr35_TRUE@ strcasecmp.S \ @HAS_avr35_TRUE@ strcasestr.S \ @HAS_avr35_TRUE@ strcasestr_P.S \ @HAS_avr35_TRUE@ strcat.S \ @HAS_avr35_TRUE@ strchr.S \ @HAS_avr35_TRUE@ strchrnul.S \ @HAS_avr35_TRUE@ strcmp.S \ @HAS_avr35_TRUE@ strcpy.S \ @HAS_avr35_TRUE@ strcspn.S \ @HAS_avr35_TRUE@ strlcat.S \ @HAS_avr35_TRUE@ strlcpy.S \ @HAS_avr35_TRUE@ strlen.S \ @HAS_avr35_TRUE@ strlwr.S \ @HAS_avr35_TRUE@ strncasecmp.S \ @HAS_avr35_TRUE@ strncat.S \ @HAS_avr35_TRUE@ strncmp.S \ @HAS_avr35_TRUE@ strncpy.S \ @HAS_avr35_TRUE@ strnlen.S \ @HAS_avr35_TRUE@ strpbrk.S \ @HAS_avr35_TRUE@ strrchr.S \ @HAS_avr35_TRUE@ strrev.S \ @HAS_avr35_TRUE@ strsep.S \ @HAS_avr35_TRUE@ strspn.S \ @HAS_avr35_TRUE@ strstr.S \ @HAS_avr35_TRUE@ strtok_r.S \ @HAS_avr35_TRUE@ strupr.S @HAS_avr35_TRUE@string_a_extra_dist = \ @HAS_avr35_TRUE@ strlcat.c \ @HAS_avr35_TRUE@ strlcpy.c @HAS_avr35_TRUE@misc_a_c_sources = @HAS_avr35_TRUE@eeprom_asm_sources = \ @HAS_avr35_TRUE@ eerd_block.S \ @HAS_avr35_TRUE@ eerd_byte.S \ @HAS_avr35_TRUE@ eerd_dword.S \ @HAS_avr35_TRUE@ eerd_word.S \ @HAS_avr35_TRUE@ eeupd_block.S \ @HAS_avr35_TRUE@ eeupd_byte.S \ @HAS_avr35_TRUE@ eeupd_dword.S \ @HAS_avr35_TRUE@ eeupd_word.S \ @HAS_avr35_TRUE@ eewr_block.S \ @HAS_avr35_TRUE@ eewr_byte.S \ @HAS_avr35_TRUE@ eewr_dword.S \ @HAS_avr35_TRUE@ eewr_word.S @HAS_avr35_TRUE@misc_a_asm_sources = \ @HAS_avr35_TRUE@ itoa.S \ @HAS_avr35_TRUE@ ltoa.S \ @HAS_avr35_TRUE@ mulsi10.S \ @HAS_avr35_TRUE@ mul10.S \ @HAS_avr35_TRUE@ ultoa.S \ @HAS_avr35_TRUE@ utoa.S @HAS_avr35_TRUE@misc_a_extra_dist = \ @HAS_avr35_TRUE@ eedef.h \ @HAS_avr35_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avr35_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avr35_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avr35_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avr35_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avr35_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avr35_TRUE@misc_a_libadd = \ @HAS_avr35_TRUE@ $(eeprom_asm_objlist) @HAS_avr35_TRUE@stdio_a_c_sources = \ @HAS_avr35_TRUE@ clearerr.c \ @HAS_avr35_TRUE@ fclose.c \ @HAS_avr35_TRUE@ fdevopen.c \ @HAS_avr35_TRUE@ feof.c \ @HAS_avr35_TRUE@ ferror.c \ @HAS_avr35_TRUE@ fgetc.c \ @HAS_avr35_TRUE@ fgets.c \ @HAS_avr35_TRUE@ fprintf.c \ @HAS_avr35_TRUE@ fprintf_p.c \ @HAS_avr35_TRUE@ fputc.c \ @HAS_avr35_TRUE@ fputs.c \ @HAS_avr35_TRUE@ fputs_p.c \ @HAS_avr35_TRUE@ fread.c \ @HAS_avr35_TRUE@ fscanf.c \ @HAS_avr35_TRUE@ fscanf_p.c \ @HAS_avr35_TRUE@ fwrite.c \ @HAS_avr35_TRUE@ getchar.c \ @HAS_avr35_TRUE@ gets.c \ @HAS_avr35_TRUE@ iob.c \ @HAS_avr35_TRUE@ printf.c \ @HAS_avr35_TRUE@ printf_p.c \ @HAS_avr35_TRUE@ putchar.c \ @HAS_avr35_TRUE@ puts.c \ @HAS_avr35_TRUE@ puts_p.c \ @HAS_avr35_TRUE@ scanf.c \ @HAS_avr35_TRUE@ scanf_p.c \ @HAS_avr35_TRUE@ snprintf.c \ @HAS_avr35_TRUE@ snprintf_p.c \ @HAS_avr35_TRUE@ sprintf.c \ @HAS_avr35_TRUE@ sprintf_p.c \ @HAS_avr35_TRUE@ sscanf.c \ @HAS_avr35_TRUE@ sscanf_p.c \ @HAS_avr35_TRUE@ vfprintf_p.c \ @HAS_avr35_TRUE@ vfscanf_p.c \ @HAS_avr35_TRUE@ vprintf.c \ @HAS_avr35_TRUE@ vscanf.c \ @HAS_avr35_TRUE@ vsnprintf.c \ @HAS_avr35_TRUE@ vsnprintf_p.c \ @HAS_avr35_TRUE@ vsprintf.c \ @HAS_avr35_TRUE@ vsprintf_p.c \ @HAS_avr35_TRUE@ ungetc.c @HAS_avr35_TRUE@stdio_a_asm_sources = \ @HAS_avr35_TRUE@ getc.S \ @HAS_avr35_TRUE@ putc.S \ @HAS_avr35_TRUE@ ultoa_invert.S @HAS_avr35_TRUE@stdio_a_extra_dist = \ @HAS_avr35_TRUE@ vfprintf.c \ @HAS_avr35_TRUE@ vfscanf.c \ @HAS_avr35_TRUE@ stdio_private.h \ @HAS_avr35_TRUE@ xtoa_fast.h @HAS_avr35_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avr35_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avr35_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avr35_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avr35_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avr35_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avr35_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avr35_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avr35_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avr35_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avr35_TRUE@libm_a_c_sources = @HAS_avr35_TRUE@libm_a_asm_sources = \ @HAS_avr35_TRUE@ acos.S \ @HAS_avr35_TRUE@ addsf3.S \ @HAS_avr35_TRUE@ addsf3x.S \ @HAS_avr35_TRUE@ asin.S \ @HAS_avr35_TRUE@ atan2.S \ @HAS_avr35_TRUE@ atan.S \ @HAS_avr35_TRUE@ cbrt.S \ @HAS_avr35_TRUE@ ceil.S \ @HAS_avr35_TRUE@ cmpsf2.S \ @HAS_avr35_TRUE@ copysign.S \ @HAS_avr35_TRUE@ cosh.S \ @HAS_avr35_TRUE@ cos.S \ @HAS_avr35_TRUE@ divsf3.S \ @HAS_avr35_TRUE@ divsf3x.S \ @HAS_avr35_TRUE@ exp.S \ @HAS_avr35_TRUE@ fixsfdi.S \ @HAS_avr35_TRUE@ fixsfsi.S \ @HAS_avr35_TRUE@ fixunssfsi.S \ @HAS_avr35_TRUE@ floatdisf.S \ @HAS_avr35_TRUE@ floatsisf.S \ @HAS_avr35_TRUE@ floatundisf.S \ @HAS_avr35_TRUE@ fdim.S \ @HAS_avr35_TRUE@ floor.S \ @HAS_avr35_TRUE@ fma.S \ @HAS_avr35_TRUE@ fmax.S \ @HAS_avr35_TRUE@ fmin.S \ @HAS_avr35_TRUE@ fmod.S \ @HAS_avr35_TRUE@ fp_arccos.S \ @HAS_avr35_TRUE@ fp_cmp.S \ @HAS_avr35_TRUE@ fp_inf.S \ @HAS_avr35_TRUE@ fp_mintl.S \ @HAS_avr35_TRUE@ fp_mpack.S \ @HAS_avr35_TRUE@ fp_nan.S \ @HAS_avr35_TRUE@ fp_negdi.S \ @HAS_avr35_TRUE@ fp_norm2.S \ @HAS_avr35_TRUE@ fp_powser.S \ @HAS_avr35_TRUE@ fp_powsodd.S \ @HAS_avr35_TRUE@ fp_pscA.S \ @HAS_avr35_TRUE@ fp_pscB.S \ @HAS_avr35_TRUE@ fp_rempio2.S \ @HAS_avr35_TRUE@ fp_round.S \ @HAS_avr35_TRUE@ fp_sinus.S \ @HAS_avr35_TRUE@ fp_split3.S \ @HAS_avr35_TRUE@ fp_trunc.S \ @HAS_avr35_TRUE@ fp_zero.S \ @HAS_avr35_TRUE@ frexp.S \ @HAS_avr35_TRUE@ gesf2.S \ @HAS_avr35_TRUE@ hypot.S \ @HAS_avr35_TRUE@ inverse.S \ @HAS_avr35_TRUE@ isfinite.S \ @HAS_avr35_TRUE@ isinf.S \ @HAS_avr35_TRUE@ isnan.S \ @HAS_avr35_TRUE@ ldexp.S \ @HAS_avr35_TRUE@ log10.S \ @HAS_avr35_TRUE@ log.S \ @HAS_avr35_TRUE@ lrint.S \ @HAS_avr35_TRUE@ lround.S \ @HAS_avr35_TRUE@ modf.S \ @HAS_avr35_TRUE@ mulsf3.S \ @HAS_avr35_TRUE@ mulsf3x.S \ @HAS_avr35_TRUE@ negsf2.S \ @HAS_avr35_TRUE@ pow.S \ @HAS_avr35_TRUE@ round.S \ @HAS_avr35_TRUE@ signbit.S \ @HAS_avr35_TRUE@ sinh.S \ @HAS_avr35_TRUE@ sin.S \ @HAS_avr35_TRUE@ sqrt.S \ @HAS_avr35_TRUE@ square.S \ @HAS_avr35_TRUE@ tanh.S \ @HAS_avr35_TRUE@ tan.S \ @HAS_avr35_TRUE@ trunc.S \ @HAS_avr35_TRUE@ unordsf2.S @HAS_avr35_TRUE@libm_a_extra_dist = \ @HAS_avr35_TRUE@ asmdef.h \ @HAS_avr35_TRUE@ fp32def.h \ @HAS_avr35_TRUE@ ntz.h @HAS_avr35_TRUE@nodist_libc_a_SOURCES = \ @HAS_avr35_TRUE@ $(stdlib_a_c_sources) \ @HAS_avr35_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avr35_TRUE@ $(pmstring_a_c_sources) \ @HAS_avr35_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avr35_TRUE@ $(string_a_c_sources) \ @HAS_avr35_TRUE@ $(string_a_asm_sources) \ @HAS_avr35_TRUE@ $(misc_a_c_sources) \ @HAS_avr35_TRUE@ $(misc_a_asm_sources) \ @HAS_avr35_TRUE@ $(stdio_a_c_sources) \ @HAS_avr35_TRUE@ $(stdio_a_asm_sources) \ @HAS_avr35_TRUE@ $(libm_a_c_sources) \ @HAS_avr35_TRUE@ $(libm_a_asm_sources) @HAS_avr35_TRUE@nodist_libm_a_SOURCES = \ @HAS_avr35_TRUE@ $(libm_a_c_sources) \ @HAS_avr35_TRUE@ $(libm_a_asm_sources) @HAS_avr35_TRUE@libc_a_LIBADD = \ @HAS_avr35_TRUE@ $(stdio_a_libadd) \ @HAS_avr35_TRUE@ $(misc_a_libadd) @HAS_avr35_TRUE@libc_a_DEPENDENCIES = \ @HAS_avr35_TRUE@ $(stdio_a_libadd) \ @HAS_avr35_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am $(top_srcdir)/libc/misc/Rules.am $(top_srcdir)/libc/misc/Files.am $(top_srcdir)/libc/stdio/Rules.am $(top_srcdir)/libc/stdio/Files.am $(top_srcdir)/libm/fplib/Rules.am $(top_srcdir)/libm/fplib/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign avr/lib/avr35/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign avr/lib/avr35/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): install-avrLIBRARIES: $(avr_LIBRARIES) @$(NORMAL_INSTALL) test -z "$(avrdir)" || $(MKDIR_P) "$(DESTDIR)$(avrdir)" @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || list=; \ list2=; for p in $$list; do \ if test -f $$p; then \ list2="$$list2 $$p"; \ else :; fi; \ done; \ test -z "$$list2" || { \ echo " $(INSTALL_DATA) $$list2 '$(DESTDIR)$(avrdir)'"; \ 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conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : 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@HAS_avr5_TRUE@ strlen_P.S \ @HAS_avr5_TRUE@ strncasecmp_P.S \ @HAS_avr5_TRUE@ strncat_P.S \ @HAS_avr5_TRUE@ strncmp_P.S \ @HAS_avr5_TRUE@ strncpy_P.S \ @HAS_avr5_TRUE@ strnlen_P.S \ @HAS_avr5_TRUE@ strpbrk_P.S \ @HAS_avr5_TRUE@ strrchr_P.S \ @HAS_avr5_TRUE@ strsep_P.S \ @HAS_avr5_TRUE@ strspn_P.S \ @HAS_avr5_TRUE@ strstr_P.S \ @HAS_avr5_TRUE@ strtok_rP.S \ @HAS_avr5_TRUE@ memcpy_PF.S \ @HAS_avr5_TRUE@ strcasecmp_PF.S \ @HAS_avr5_TRUE@ strcat_PF.S \ @HAS_avr5_TRUE@ strcmp_PF.S \ @HAS_avr5_TRUE@ strcpy_PF.S \ @HAS_avr5_TRUE@ strlcat_PF.S \ @HAS_avr5_TRUE@ strlcpy_PF.S \ @HAS_avr5_TRUE@ strlen_PF.S \ @HAS_avr5_TRUE@ strncasecmp_PF.S \ @HAS_avr5_TRUE@ strncat_PF.S \ @HAS_avr5_TRUE@ strncmp_PF.S \ @HAS_avr5_TRUE@ strncpy_PF.S \ @HAS_avr5_TRUE@ strnlen_PF.S \ @HAS_avr5_TRUE@ strstr_PF.S \ @HAS_avr5_TRUE@ memcmp_PF.S @HAS_avr5_TRUE@string_a_c_sources = \ @HAS_avr5_TRUE@ strdup.c \ @HAS_avr5_TRUE@ strtok.c @HAS_avr5_TRUE@string_a_asm_sources = \ @HAS_avr5_TRUE@ ffs.S \ @HAS_avr5_TRUE@ ffsl.S \ @HAS_avr5_TRUE@ ffsll.S \ @HAS_avr5_TRUE@ memccpy.S \ @HAS_avr5_TRUE@ memchr.S \ @HAS_avr5_TRUE@ memcmp.S \ @HAS_avr5_TRUE@ memcpy.S \ @HAS_avr5_TRUE@ memmem.S \ @HAS_avr5_TRUE@ memmem_P.S \ @HAS_avr5_TRUE@ memmove.S \ @HAS_avr5_TRUE@ memrchr.S \ @HAS_avr5_TRUE@ memset.S \ @HAS_avr5_TRUE@ strcasecmp.S \ @HAS_avr5_TRUE@ strcasestr.S \ @HAS_avr5_TRUE@ strcasestr_P.S \ @HAS_avr5_TRUE@ strcat.S \ @HAS_avr5_TRUE@ strchr.S \ @HAS_avr5_TRUE@ strchrnul.S \ @HAS_avr5_TRUE@ strcmp.S \ @HAS_avr5_TRUE@ strcpy.S \ @HAS_avr5_TRUE@ strcspn.S \ @HAS_avr5_TRUE@ strlcat.S \ @HAS_avr5_TRUE@ strlcpy.S \ @HAS_avr5_TRUE@ strlen.S \ @HAS_avr5_TRUE@ strlwr.S \ @HAS_avr5_TRUE@ strncasecmp.S \ @HAS_avr5_TRUE@ strncat.S \ @HAS_avr5_TRUE@ strncmp.S \ @HAS_avr5_TRUE@ strncpy.S \ @HAS_avr5_TRUE@ strnlen.S \ @HAS_avr5_TRUE@ strpbrk.S \ @HAS_avr5_TRUE@ strrchr.S \ @HAS_avr5_TRUE@ strrev.S \ @HAS_avr5_TRUE@ strsep.S \ @HAS_avr5_TRUE@ strspn.S \ @HAS_avr5_TRUE@ strstr.S \ @HAS_avr5_TRUE@ strtok_r.S \ @HAS_avr5_TRUE@ strupr.S @HAS_avr5_TRUE@string_a_extra_dist = \ @HAS_avr5_TRUE@ strlcat.c \ @HAS_avr5_TRUE@ strlcpy.c @HAS_avr5_TRUE@misc_a_c_sources = @HAS_avr5_TRUE@eeprom_asm_sources = \ @HAS_avr5_TRUE@ eerd_block.S \ @HAS_avr5_TRUE@ eerd_byte.S \ @HAS_avr5_TRUE@ eerd_dword.S \ @HAS_avr5_TRUE@ eerd_word.S \ @HAS_avr5_TRUE@ eeupd_block.S \ @HAS_avr5_TRUE@ eeupd_byte.S \ @HAS_avr5_TRUE@ eeupd_dword.S \ @HAS_avr5_TRUE@ eeupd_word.S \ @HAS_avr5_TRUE@ eewr_block.S \ @HAS_avr5_TRUE@ eewr_byte.S \ @HAS_avr5_TRUE@ eewr_dword.S \ @HAS_avr5_TRUE@ eewr_word.S @HAS_avr5_TRUE@misc_a_asm_sources = \ @HAS_avr5_TRUE@ itoa.S \ @HAS_avr5_TRUE@ ltoa.S \ @HAS_avr5_TRUE@ mulsi10.S \ @HAS_avr5_TRUE@ mul10.S \ @HAS_avr5_TRUE@ ultoa.S \ @HAS_avr5_TRUE@ utoa.S @HAS_avr5_TRUE@misc_a_extra_dist = \ @HAS_avr5_TRUE@ eedef.h \ @HAS_avr5_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avr5_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avr5_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avr5_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avr5_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avr5_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avr5_TRUE@misc_a_libadd = \ @HAS_avr5_TRUE@ $(eeprom_asm_objlist) @HAS_avr5_TRUE@stdio_a_c_sources = \ @HAS_avr5_TRUE@ clearerr.c \ @HAS_avr5_TRUE@ fclose.c \ @HAS_avr5_TRUE@ fdevopen.c \ @HAS_avr5_TRUE@ feof.c \ @HAS_avr5_TRUE@ ferror.c \ @HAS_avr5_TRUE@ fgetc.c \ @HAS_avr5_TRUE@ fgets.c \ @HAS_avr5_TRUE@ fprintf.c \ @HAS_avr5_TRUE@ fprintf_p.c \ @HAS_avr5_TRUE@ fputc.c \ @HAS_avr5_TRUE@ fputs.c \ @HAS_avr5_TRUE@ fputs_p.c \ @HAS_avr5_TRUE@ fread.c \ @HAS_avr5_TRUE@ fscanf.c \ @HAS_avr5_TRUE@ fscanf_p.c \ @HAS_avr5_TRUE@ fwrite.c \ @HAS_avr5_TRUE@ getchar.c \ @HAS_avr5_TRUE@ gets.c \ @HAS_avr5_TRUE@ iob.c \ @HAS_avr5_TRUE@ printf.c \ @HAS_avr5_TRUE@ printf_p.c \ @HAS_avr5_TRUE@ putchar.c \ @HAS_avr5_TRUE@ puts.c \ @HAS_avr5_TRUE@ puts_p.c \ @HAS_avr5_TRUE@ scanf.c \ @HAS_avr5_TRUE@ scanf_p.c \ @HAS_avr5_TRUE@ snprintf.c \ @HAS_avr5_TRUE@ snprintf_p.c \ @HAS_avr5_TRUE@ sprintf.c \ @HAS_avr5_TRUE@ sprintf_p.c \ @HAS_avr5_TRUE@ sscanf.c \ @HAS_avr5_TRUE@ sscanf_p.c \ @HAS_avr5_TRUE@ vfprintf_p.c \ @HAS_avr5_TRUE@ vfscanf_p.c \ @HAS_avr5_TRUE@ vprintf.c \ @HAS_avr5_TRUE@ vscanf.c \ @HAS_avr5_TRUE@ vsnprintf.c \ @HAS_avr5_TRUE@ vsnprintf_p.c \ @HAS_avr5_TRUE@ vsprintf.c \ @HAS_avr5_TRUE@ vsprintf_p.c \ @HAS_avr5_TRUE@ ungetc.c @HAS_avr5_TRUE@stdio_a_asm_sources = \ @HAS_avr5_TRUE@ getc.S \ @HAS_avr5_TRUE@ putc.S \ @HAS_avr5_TRUE@ ultoa_invert.S @HAS_avr5_TRUE@stdio_a_extra_dist = \ @HAS_avr5_TRUE@ vfprintf.c \ @HAS_avr5_TRUE@ vfscanf.c \ @HAS_avr5_TRUE@ stdio_private.h \ @HAS_avr5_TRUE@ xtoa_fast.h @HAS_avr5_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avr5_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avr5_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avr5_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avr5_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avr5_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avr5_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avr5_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avr5_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avr5_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avr5_TRUE@libm_a_c_sources = @HAS_avr5_TRUE@libm_a_asm_sources = \ @HAS_avr5_TRUE@ acos.S \ @HAS_avr5_TRUE@ addsf3.S \ @HAS_avr5_TRUE@ addsf3x.S \ @HAS_avr5_TRUE@ asin.S \ @HAS_avr5_TRUE@ atan2.S \ @HAS_avr5_TRUE@ atan.S \ @HAS_avr5_TRUE@ cbrt.S \ @HAS_avr5_TRUE@ ceil.S \ @HAS_avr5_TRUE@ cmpsf2.S \ @HAS_avr5_TRUE@ copysign.S \ @HAS_avr5_TRUE@ cosh.S \ @HAS_avr5_TRUE@ cos.S \ @HAS_avr5_TRUE@ divsf3.S \ @HAS_avr5_TRUE@ divsf3x.S \ @HAS_avr5_TRUE@ exp.S \ @HAS_avr5_TRUE@ fixsfdi.S \ @HAS_avr5_TRUE@ fixsfsi.S \ @HAS_avr5_TRUE@ fixunssfsi.S \ @HAS_avr5_TRUE@ floatdisf.S \ @HAS_avr5_TRUE@ floatsisf.S \ @HAS_avr5_TRUE@ floatundisf.S \ @HAS_avr5_TRUE@ fdim.S \ @HAS_avr5_TRUE@ floor.S \ @HAS_avr5_TRUE@ fma.S \ @HAS_avr5_TRUE@ fmax.S \ @HAS_avr5_TRUE@ fmin.S \ @HAS_avr5_TRUE@ fmod.S \ @HAS_avr5_TRUE@ fp_arccos.S \ @HAS_avr5_TRUE@ fp_cmp.S \ @HAS_avr5_TRUE@ fp_inf.S \ @HAS_avr5_TRUE@ fp_mintl.S \ @HAS_avr5_TRUE@ fp_mpack.S \ @HAS_avr5_TRUE@ fp_nan.S \ @HAS_avr5_TRUE@ fp_negdi.S \ @HAS_avr5_TRUE@ fp_norm2.S \ @HAS_avr5_TRUE@ fp_powser.S \ @HAS_avr5_TRUE@ fp_powsodd.S \ @HAS_avr5_TRUE@ fp_pscA.S \ @HAS_avr5_TRUE@ fp_pscB.S \ @HAS_avr5_TRUE@ fp_rempio2.S \ @HAS_avr5_TRUE@ fp_round.S \ @HAS_avr5_TRUE@ fp_sinus.S \ @HAS_avr5_TRUE@ fp_split3.S \ @HAS_avr5_TRUE@ fp_trunc.S \ @HAS_avr5_TRUE@ fp_zero.S \ @HAS_avr5_TRUE@ frexp.S \ @HAS_avr5_TRUE@ gesf2.S \ @HAS_avr5_TRUE@ hypot.S \ @HAS_avr5_TRUE@ inverse.S \ @HAS_avr5_TRUE@ isfinite.S \ @HAS_avr5_TRUE@ isinf.S \ @HAS_avr5_TRUE@ isnan.S \ @HAS_avr5_TRUE@ ldexp.S \ @HAS_avr5_TRUE@ log10.S \ @HAS_avr5_TRUE@ log.S \ @HAS_avr5_TRUE@ lrint.S \ @HAS_avr5_TRUE@ lround.S \ @HAS_avr5_TRUE@ modf.S \ @HAS_avr5_TRUE@ mulsf3.S \ @HAS_avr5_TRUE@ mulsf3x.S \ @HAS_avr5_TRUE@ negsf2.S \ @HAS_avr5_TRUE@ pow.S \ @HAS_avr5_TRUE@ round.S \ @HAS_avr5_TRUE@ signbit.S \ @HAS_avr5_TRUE@ sinh.S \ @HAS_avr5_TRUE@ sin.S \ @HAS_avr5_TRUE@ sqrt.S \ @HAS_avr5_TRUE@ square.S \ @HAS_avr5_TRUE@ tanh.S \ @HAS_avr5_TRUE@ tan.S \ @HAS_avr5_TRUE@ trunc.S \ @HAS_avr5_TRUE@ unordsf2.S @HAS_avr5_TRUE@libm_a_extra_dist = \ @HAS_avr5_TRUE@ asmdef.h \ @HAS_avr5_TRUE@ fp32def.h \ @HAS_avr5_TRUE@ ntz.h @HAS_avr5_TRUE@nodist_libc_a_SOURCES = \ @HAS_avr5_TRUE@ $(stdlib_a_c_sources) \ @HAS_avr5_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avr5_TRUE@ $(pmstring_a_c_sources) \ @HAS_avr5_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avr5_TRUE@ $(string_a_c_sources) \ @HAS_avr5_TRUE@ $(string_a_asm_sources) \ @HAS_avr5_TRUE@ $(misc_a_c_sources) \ @HAS_avr5_TRUE@ $(misc_a_asm_sources) \ @HAS_avr5_TRUE@ $(stdio_a_c_sources) \ @HAS_avr5_TRUE@ $(stdio_a_asm_sources) \ @HAS_avr5_TRUE@ $(libm_a_c_sources) \ @HAS_avr5_TRUE@ $(libm_a_asm_sources) @HAS_avr5_TRUE@nodist_libm_a_SOURCES = \ @HAS_avr5_TRUE@ $(libm_a_c_sources) \ @HAS_avr5_TRUE@ $(libm_a_asm_sources) @HAS_avr5_TRUE@libc_a_LIBADD = \ @HAS_avr5_TRUE@ $(stdio_a_libadd) \ @HAS_avr5_TRUE@ $(misc_a_libadd) @HAS_avr5_TRUE@libc_a_DEPENDENCIES = \ @HAS_avr5_TRUE@ $(stdio_a_libadd) \ @HAS_avr5_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am $(top_srcdir)/libc/misc/Rules.am $(top_srcdir)/libc/misc/Files.am $(top_srcdir)/libc/stdio/Rules.am $(top_srcdir)/libc/stdio/Files.am $(top_srcdir)/libm/fplib/Rules.am $(top_srcdir)/libm/fplib/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign avr/lib/avr5/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign avr/lib/avr5/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): install-avrLIBRARIES: $(avr_LIBRARIES) @$(NORMAL_INSTALL) test -z "$(avrdir)" || $(MKDIR_P) "$(DESTDIR)$(avrdir)" @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || list=; \ list2=; for p in $$list; do \ if test -f $$p; then \ list2="$$list2 $$p"; \ else :; fi; \ done; \ test -z "$$list2" || { \ echo " $(INSTALL_DATA) $$list2 '$(DESTDIR)$(avrdir)'"; \ $(INSTALL_DATA) $$list2 "$(DESTDIR)$(avrdir)" || exit $$?; } @$(POST_INSTALL) @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || list=; \ for p in $$list; do \ if test -f $$p; then \ $(am__strip_dir) \ echo " ( cd '$(DESTDIR)$(avrdir)' && $(RANLIB) $$f )"; \ ( cd "$(DESTDIR)$(avrdir)" && $(RANLIB) $$f ) || exit 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Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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@infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ SUBDIRS = attiny4 attiny5 attiny9 attiny10 attiny20 attiny40 AVR_TARGET = avrtiny10 AVR_TARGET_DEFS = -D__COMPILING_AVR_LIBC__ AVR_TARGET_CFLAGS = -mcall-prologues -Os AVR_TARGET_ASFLAGS = AVR_INSTALL_DIR = avrtiny10 @HAS_avrtiny10_TRUE@AVRLIB_DEVLIST = $(am__append_1) $(am__append_2) \ @HAS_avrtiny10_TRUE@ $(am__append_3) $(am__append_4) \ @HAS_avrtiny10_TRUE@ $(am__append_5) $(am__append_6) @HAS_avrtiny10_TRUE@AM_CPPFLAGS = -I$(top_srcdir)/common -I$(top_srcdir)/include -I$(top_builddir)/include @HAS_avrtiny10_TRUE@AVRLIB_CFLAGS = -g -Wall -W -Wstrict-prototypes -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_CFLAGS) @HAS_avrtiny10_TRUE@AVRLIB_ASFLAGS = -x assembler-with-cpp -Wa,-gstabs -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_ASFLAGS) @HAS_avrtiny10_TRUE@AM_CFLAGS = $(AVRLIB_CFLAGS) @HAS_avrtiny10_TRUE@AM_CCASFLAGS = $(AM_CPPFLAGS) $(AVRLIB_ASFLAGS) @HAS_avrtiny10_TRUE@__install_dir = $(prefix)/avr/lib/$(AVR_INSTALL_DIR) @HAS_avrtiny10_TRUE@avrdir = $(__install_dir) @HAS_avrtiny10_TRUE@avrlibdir = $(__install_dir) @HAS_avrtiny10_TRUE@avr_LIBRARIES = \ @HAS_avrtiny10_TRUE@ libc.a \ @HAS_avrtiny10_TRUE@ libprintf_min.a \ @HAS_avrtiny10_TRUE@ libprintf_flt.a \ @HAS_avrtiny10_TRUE@ libscanf_min.a \ @HAS_avrtiny10_TRUE@ libscanf_flt.a \ @HAS_avrtiny10_TRUE@ libm.a @HAS_avrtiny10_TRUE@stdlib_a_c_sources = \ @HAS_avrtiny10_TRUE@ abs.c \ @HAS_avrtiny10_TRUE@ assert.c \ @HAS_avrtiny10_TRUE@ bsearch.c \ @HAS_avrtiny10_TRUE@ calloc.c \ @HAS_avrtiny10_TRUE@ errno.c \ @HAS_avrtiny10_TRUE@ dtoa_prf.c \ @HAS_avrtiny10_TRUE@ dtostre.c \ @HAS_avrtiny10_TRUE@ dtostrf.c \ @HAS_avrtiny10_TRUE@ labs.c \ @HAS_avrtiny10_TRUE@ malloc.c \ @HAS_avrtiny10_TRUE@ qsort.c \ @HAS_avrtiny10_TRUE@ rand.c \ @HAS_avrtiny10_TRUE@ random.c \ @HAS_avrtiny10_TRUE@ realloc.c \ @HAS_avrtiny10_TRUE@ strtod.c \ @HAS_avrtiny10_TRUE@ strtol.c \ @HAS_avrtiny10_TRUE@ strtoul.c \ @HAS_avrtiny10_TRUE@ dtoa_conv.h \ @HAS_avrtiny10_TRUE@ stdlib_private.h @HAS_avrtiny10_TRUE@stdlib_a_asm_sources = \ @HAS_avrtiny10_TRUE@ abort.S \ @HAS_avrtiny10_TRUE@ atof.S \ @HAS_avrtiny10_TRUE@ atoi.S \ @HAS_avrtiny10_TRUE@ atol.S \ @HAS_avrtiny10_TRUE@ div.S \ @HAS_avrtiny10_TRUE@ exit.S \ @HAS_avrtiny10_TRUE@ ftoa_engine.S \ @HAS_avrtiny10_TRUE@ ldiv.S \ @HAS_avrtiny10_TRUE@ setjmp.S \ @HAS_avrtiny10_TRUE@ isascii.S \ @HAS_avrtiny10_TRUE@ toascii.S \ @HAS_avrtiny10_TRUE@ isalnum.S \ @HAS_avrtiny10_TRUE@ cty_isfalse.S \ @HAS_avrtiny10_TRUE@ isalpha.S \ @HAS_avrtiny10_TRUE@ isdigit.S \ @HAS_avrtiny10_TRUE@ isxdigit.S \ @HAS_avrtiny10_TRUE@ iscntrl.S \ @HAS_avrtiny10_TRUE@ isprint.S \ @HAS_avrtiny10_TRUE@ isspace.S \ @HAS_avrtiny10_TRUE@ isblank.S \ @HAS_avrtiny10_TRUE@ ispunct.S \ @HAS_avrtiny10_TRUE@ tolower.S \ @HAS_avrtiny10_TRUE@ toupper.S @HAS_avrtiny10_TRUE@stdlib_a_extra_dist = \ @HAS_avrtiny10_TRUE@ ctype.S \ @HAS_avrtiny10_TRUE@ abort.c \ @HAS_avrtiny10_TRUE@ atoi.c \ @HAS_avrtiny10_TRUE@ atol.c @HAS_avrtiny10_TRUE@pmstring_a_c_sources = \ @HAS_avrtiny10_TRUE@ strtok_P.c @HAS_avrtiny10_TRUE@pmstring_a_asm_sources = \ @HAS_avrtiny10_TRUE@ memchr_P.S \ @HAS_avrtiny10_TRUE@ memcmp_P.S \ @HAS_avrtiny10_TRUE@ memccpy_P.S \ @HAS_avrtiny10_TRUE@ memcpy_P.S \ @HAS_avrtiny10_TRUE@ memrchr_P.S \ @HAS_avrtiny10_TRUE@ strcasecmp_P.S \ @HAS_avrtiny10_TRUE@ strcat_P.S \ @HAS_avrtiny10_TRUE@ strchr_P.S \ @HAS_avrtiny10_TRUE@ strchrnul_P.S \ @HAS_avrtiny10_TRUE@ strcmp_P.S \ @HAS_avrtiny10_TRUE@ strcpy_P.S \ @HAS_avrtiny10_TRUE@ strcspn_P.S \ @HAS_avrtiny10_TRUE@ strlcat_P.S \ @HAS_avrtiny10_TRUE@ strlcpy_P.S \ @HAS_avrtiny10_TRUE@ strlen_P.S \ @HAS_avrtiny10_TRUE@ strncasecmp_P.S \ @HAS_avrtiny10_TRUE@ strncat_P.S \ @HAS_avrtiny10_TRUE@ strncmp_P.S \ @HAS_avrtiny10_TRUE@ strncpy_P.S \ @HAS_avrtiny10_TRUE@ strnlen_P.S \ @HAS_avrtiny10_TRUE@ strpbrk_P.S \ @HAS_avrtiny10_TRUE@ strrchr_P.S \ @HAS_avrtiny10_TRUE@ strsep_P.S \ @HAS_avrtiny10_TRUE@ strspn_P.S \ @HAS_avrtiny10_TRUE@ strstr_P.S \ @HAS_avrtiny10_TRUE@ strtok_rP.S \ @HAS_avrtiny10_TRUE@ memcpy_PF.S \ @HAS_avrtiny10_TRUE@ strcasecmp_PF.S \ @HAS_avrtiny10_TRUE@ strcat_PF.S \ @HAS_avrtiny10_TRUE@ strcmp_PF.S \ @HAS_avrtiny10_TRUE@ strcpy_PF.S \ @HAS_avrtiny10_TRUE@ strlcat_PF.S \ @HAS_avrtiny10_TRUE@ strlcpy_PF.S \ @HAS_avrtiny10_TRUE@ strlen_PF.S \ @HAS_avrtiny10_TRUE@ strncasecmp_PF.S \ @HAS_avrtiny10_TRUE@ strncat_PF.S \ @HAS_avrtiny10_TRUE@ strncmp_PF.S \ @HAS_avrtiny10_TRUE@ strncpy_PF.S \ @HAS_avrtiny10_TRUE@ strnlen_PF.S \ @HAS_avrtiny10_TRUE@ strstr_PF.S \ @HAS_avrtiny10_TRUE@ memcmp_PF.S @HAS_avrtiny10_TRUE@string_a_c_sources = \ @HAS_avrtiny10_TRUE@ strdup.c \ @HAS_avrtiny10_TRUE@ strtok.c @HAS_avrtiny10_TRUE@string_a_asm_sources = \ @HAS_avrtiny10_TRUE@ ffs.S \ @HAS_avrtiny10_TRUE@ ffsl.S \ @HAS_avrtiny10_TRUE@ ffsll.S \ @HAS_avrtiny10_TRUE@ memccpy.S \ @HAS_avrtiny10_TRUE@ memchr.S \ @HAS_avrtiny10_TRUE@ memcmp.S \ @HAS_avrtiny10_TRUE@ memcpy.S \ @HAS_avrtiny10_TRUE@ memmem.S \ @HAS_avrtiny10_TRUE@ memmem_P.S \ @HAS_avrtiny10_TRUE@ memmove.S \ @HAS_avrtiny10_TRUE@ memrchr.S \ @HAS_avrtiny10_TRUE@ memset.S \ @HAS_avrtiny10_TRUE@ strcasecmp.S \ @HAS_avrtiny10_TRUE@ strcasestr.S \ @HAS_avrtiny10_TRUE@ strcasestr_P.S \ @HAS_avrtiny10_TRUE@ strcat.S \ @HAS_avrtiny10_TRUE@ strchr.S \ @HAS_avrtiny10_TRUE@ strchrnul.S \ @HAS_avrtiny10_TRUE@ strcmp.S \ @HAS_avrtiny10_TRUE@ strcpy.S \ @HAS_avrtiny10_TRUE@ strcspn.S \ @HAS_avrtiny10_TRUE@ strlcat.S \ @HAS_avrtiny10_TRUE@ strlcpy.S \ @HAS_avrtiny10_TRUE@ strlen.S \ @HAS_avrtiny10_TRUE@ strlwr.S \ @HAS_avrtiny10_TRUE@ strncasecmp.S \ @HAS_avrtiny10_TRUE@ strncat.S \ @HAS_avrtiny10_TRUE@ strncmp.S \ @HAS_avrtiny10_TRUE@ strncpy.S \ @HAS_avrtiny10_TRUE@ strnlen.S \ @HAS_avrtiny10_TRUE@ strpbrk.S \ @HAS_avrtiny10_TRUE@ strrchr.S \ @HAS_avrtiny10_TRUE@ strrev.S \ @HAS_avrtiny10_TRUE@ strsep.S \ @HAS_avrtiny10_TRUE@ strspn.S \ @HAS_avrtiny10_TRUE@ strstr.S \ @HAS_avrtiny10_TRUE@ strtok_r.S \ @HAS_avrtiny10_TRUE@ strupr.S @HAS_avrtiny10_TRUE@string_a_extra_dist = \ @HAS_avrtiny10_TRUE@ strlcat.c \ @HAS_avrtiny10_TRUE@ strlcpy.c @HAS_avrtiny10_TRUE@misc_a_c_sources = @HAS_avrtiny10_TRUE@eeprom_asm_sources = \ @HAS_avrtiny10_TRUE@ eerd_block.S \ @HAS_avrtiny10_TRUE@ eerd_byte.S \ @HAS_avrtiny10_TRUE@ eerd_dword.S \ @HAS_avrtiny10_TRUE@ eerd_word.S \ @HAS_avrtiny10_TRUE@ eeupd_block.S \ @HAS_avrtiny10_TRUE@ eeupd_byte.S \ @HAS_avrtiny10_TRUE@ eeupd_dword.S \ @HAS_avrtiny10_TRUE@ eeupd_word.S \ @HAS_avrtiny10_TRUE@ eewr_block.S \ @HAS_avrtiny10_TRUE@ eewr_byte.S \ @HAS_avrtiny10_TRUE@ eewr_dword.S \ @HAS_avrtiny10_TRUE@ eewr_word.S @HAS_avrtiny10_TRUE@misc_a_asm_sources = \ @HAS_avrtiny10_TRUE@ itoa.S \ @HAS_avrtiny10_TRUE@ ltoa.S \ @HAS_avrtiny10_TRUE@ mulsi10.S \ @HAS_avrtiny10_TRUE@ mul10.S \ @HAS_avrtiny10_TRUE@ ultoa.S \ @HAS_avrtiny10_TRUE@ utoa.S @HAS_avrtiny10_TRUE@misc_a_extra_dist = \ @HAS_avrtiny10_TRUE@ eedef.h \ @HAS_avrtiny10_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avrtiny10_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avrtiny10_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avrtiny10_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avrtiny10_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avrtiny10_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avrtiny10_TRUE@misc_a_libadd = \ @HAS_avrtiny10_TRUE@ $(eeprom_asm_objlist) @HAS_avrtiny10_TRUE@stdio_a_c_sources = \ @HAS_avrtiny10_TRUE@ clearerr.c \ @HAS_avrtiny10_TRUE@ fclose.c \ @HAS_avrtiny10_TRUE@ fdevopen.c \ @HAS_avrtiny10_TRUE@ feof.c \ @HAS_avrtiny10_TRUE@ ferror.c \ @HAS_avrtiny10_TRUE@ fgetc.c \ @HAS_avrtiny10_TRUE@ fgets.c \ @HAS_avrtiny10_TRUE@ fprintf.c \ @HAS_avrtiny10_TRUE@ fprintf_p.c \ @HAS_avrtiny10_TRUE@ fputc.c \ @HAS_avrtiny10_TRUE@ fputs.c \ @HAS_avrtiny10_TRUE@ fputs_p.c \ @HAS_avrtiny10_TRUE@ fread.c \ @HAS_avrtiny10_TRUE@ fscanf.c \ @HAS_avrtiny10_TRUE@ fscanf_p.c \ @HAS_avrtiny10_TRUE@ fwrite.c \ @HAS_avrtiny10_TRUE@ getchar.c \ @HAS_avrtiny10_TRUE@ gets.c \ @HAS_avrtiny10_TRUE@ iob.c \ @HAS_avrtiny10_TRUE@ printf.c \ @HAS_avrtiny10_TRUE@ printf_p.c \ @HAS_avrtiny10_TRUE@ putchar.c \ @HAS_avrtiny10_TRUE@ puts.c \ @HAS_avrtiny10_TRUE@ puts_p.c \ @HAS_avrtiny10_TRUE@ scanf.c \ @HAS_avrtiny10_TRUE@ scanf_p.c \ @HAS_avrtiny10_TRUE@ snprintf.c \ @HAS_avrtiny10_TRUE@ snprintf_p.c \ @HAS_avrtiny10_TRUE@ sprintf.c \ @HAS_avrtiny10_TRUE@ sprintf_p.c \ @HAS_avrtiny10_TRUE@ sscanf.c \ @HAS_avrtiny10_TRUE@ sscanf_p.c \ @HAS_avrtiny10_TRUE@ vfprintf_p.c \ @HAS_avrtiny10_TRUE@ vfscanf_p.c \ @HAS_avrtiny10_TRUE@ vprintf.c \ @HAS_avrtiny10_TRUE@ vscanf.c \ @HAS_avrtiny10_TRUE@ vsnprintf.c \ @HAS_avrtiny10_TRUE@ vsnprintf_p.c \ @HAS_avrtiny10_TRUE@ vsprintf.c \ @HAS_avrtiny10_TRUE@ vsprintf_p.c \ @HAS_avrtiny10_TRUE@ ungetc.c @HAS_avrtiny10_TRUE@stdio_a_asm_sources = \ @HAS_avrtiny10_TRUE@ getc.S \ @HAS_avrtiny10_TRUE@ putc.S \ @HAS_avrtiny10_TRUE@ ultoa_invert.S @HAS_avrtiny10_TRUE@stdio_a_extra_dist = \ @HAS_avrtiny10_TRUE@ vfprintf.c \ @HAS_avrtiny10_TRUE@ vfscanf.c \ @HAS_avrtiny10_TRUE@ stdio_private.h \ @HAS_avrtiny10_TRUE@ xtoa_fast.h @HAS_avrtiny10_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avrtiny10_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avrtiny10_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avrtiny10_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avrtiny10_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avrtiny10_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avrtiny10_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avrtiny10_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avrtiny10_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avrtiny10_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avrtiny10_TRUE@libm_a_c_sources = @HAS_avrtiny10_TRUE@libm_a_asm_sources = \ @HAS_avrtiny10_TRUE@ acos.S \ @HAS_avrtiny10_TRUE@ addsf3.S \ @HAS_avrtiny10_TRUE@ addsf3x.S \ @HAS_avrtiny10_TRUE@ asin.S \ @HAS_avrtiny10_TRUE@ atan2.S \ @HAS_avrtiny10_TRUE@ atan.S \ @HAS_avrtiny10_TRUE@ cbrt.S \ @HAS_avrtiny10_TRUE@ ceil.S \ @HAS_avrtiny10_TRUE@ cmpsf2.S \ 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Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ @HAS_atxmega128a3_TRUE@@HAS_avrxmega6_TRUE@am__append_1 = atxmega128a3 @HAS_atxmega128d3_TRUE@@HAS_avrxmega6_TRUE@am__append_2 = atxmega128d3 @HAS_atxmega192a3_TRUE@@HAS_avrxmega6_TRUE@am__append_3 = atxmega192a3 @HAS_atxmega192d3_TRUE@@HAS_avrxmega6_TRUE@am__append_4 = atxmega192d3 @HAS_atxmega256a3_TRUE@@HAS_avrxmega6_TRUE@am__append_5 = atxmega256a3 @HAS_atxmega256a3b_TRUE@@HAS_avrxmega6_TRUE@am__append_6 = atxmega256a3b @HAS_atxmega256d3_TRUE@@HAS_avrxmega6_TRUE@am__append_7 = atxmega256d3 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ $(top_srcdir)/libc/misc/Files.am \ $(top_srcdir)/libc/misc/Rules.am \ $(top_srcdir)/libc/pmstring/Files.am \ $(top_srcdir)/libc/pmstring/Rules.am \ $(top_srcdir)/libc/stdio/Files.am \ $(top_srcdir)/libc/stdio/Rules.am \ $(top_srcdir)/libc/stdlib/Files.am \ $(top_srcdir)/libc/stdlib/Rules.am \ $(top_srcdir)/libc/string/Files.am \ $(top_srcdir)/libc/string/Rules.am \ $(top_srcdir)/libm/fplib/Files.am \ $(top_srcdir)/libm/fplib/Rules.am subdir = avr/lib/avrxmega6 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; am__vpath_adj = case $$p in \ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ *) f=$$p;; \ esac; am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`; am__install_max = 40 am__nobase_strip_setup = \ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'` am__nobase_strip = \ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||" am__nobase_list = $(am__nobase_strip_setup); \ for p in $$list; do echo "$$p $$p"; done | \ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \ if (++n[$$2] == $(am__install_max)) \ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \ END { for (dir in files) print dir, files[dir] }' am__base_list = \ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g' am__installdirs = "$(DESTDIR)$(avrdir)" LIBRARIES = $(avr_LIBRARIES) ARFLAGS = cru libc_a_AR = $(AR) $(ARFLAGS) @HAS_avrxmega6_TRUE@am__objects_1 = abs.$(OBJEXT) assert.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ bsearch.$(OBJEXT) calloc.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ errno.$(OBJEXT) dtoa_prf.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ dtostre.$(OBJEXT) dtostrf.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ labs.$(OBJEXT) malloc.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ qsort.$(OBJEXT) rand.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ random.$(OBJEXT) realloc.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strtod.$(OBJEXT) strtol.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strtoul.$(OBJEXT) @HAS_avrxmega6_TRUE@am__objects_2 = abort.$(OBJEXT) atof.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ atoi.$(OBJEXT) atol.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ div.$(OBJEXT) exit.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ ftoa_engine.$(OBJEXT) ldiv.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ setjmp.$(OBJEXT) isascii.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ toascii.$(OBJEXT) isalnum.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ cty_isfalse.$(OBJEXT) isalpha.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ isdigit.$(OBJEXT) isxdigit.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ iscntrl.$(OBJEXT) isprint.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ isspace.$(OBJEXT) isblank.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ ispunct.$(OBJEXT) tolower.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ toupper.$(OBJEXT) @HAS_avrxmega6_TRUE@am__objects_3 = strtok_P.$(OBJEXT) @HAS_avrxmega6_TRUE@am__objects_4 = memchr_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ memcmp_P.$(OBJEXT) memccpy_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ memcpy_P.$(OBJEXT) memrchr_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strcasecmp_P.$(OBJEXT) strcat_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strchr_P.$(OBJEXT) strchrnul_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strcmp_P.$(OBJEXT) strcpy_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strcspn_P.$(OBJEXT) strlcat_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strlcpy_P.$(OBJEXT) strlen_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strncasecmp_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strncat_P.$(OBJEXT) strncmp_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strncpy_P.$(OBJEXT) strnlen_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strpbrk_P.$(OBJEXT) strrchr_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strsep_P.$(OBJEXT) strspn_P.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strstr_P.$(OBJEXT) strtok_rP.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ memcpy_PF.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strcasecmp_PF.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strcat_PF.$(OBJEXT) strcmp_PF.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strcpy_PF.$(OBJEXT) strlcat_PF.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strlcpy_PF.$(OBJEXT) strlen_PF.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strncasecmp_PF.$(OBJEXT) \ @HAS_avrxmega6_TRUE@ strncat_PF.$(OBJEXT) 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@HAS_avrxmega6_TRUE@ strncat_PF.S \ @HAS_avrxmega6_TRUE@ strncmp_PF.S \ @HAS_avrxmega6_TRUE@ strncpy_PF.S \ @HAS_avrxmega6_TRUE@ strnlen_PF.S \ @HAS_avrxmega6_TRUE@ strstr_PF.S \ @HAS_avrxmega6_TRUE@ memcmp_PF.S @HAS_avrxmega6_TRUE@string_a_c_sources = \ @HAS_avrxmega6_TRUE@ strdup.c \ @HAS_avrxmega6_TRUE@ strtok.c @HAS_avrxmega6_TRUE@string_a_asm_sources = \ @HAS_avrxmega6_TRUE@ ffs.S \ @HAS_avrxmega6_TRUE@ ffsl.S \ @HAS_avrxmega6_TRUE@ ffsll.S \ @HAS_avrxmega6_TRUE@ memccpy.S \ @HAS_avrxmega6_TRUE@ memchr.S \ @HAS_avrxmega6_TRUE@ memcmp.S \ @HAS_avrxmega6_TRUE@ memcpy.S \ @HAS_avrxmega6_TRUE@ memmem.S \ @HAS_avrxmega6_TRUE@ memmem_P.S \ @HAS_avrxmega6_TRUE@ memmove.S \ @HAS_avrxmega6_TRUE@ memrchr.S \ @HAS_avrxmega6_TRUE@ memset.S \ @HAS_avrxmega6_TRUE@ strcasecmp.S \ @HAS_avrxmega6_TRUE@ strcasestr.S \ @HAS_avrxmega6_TRUE@ strcasestr_P.S \ @HAS_avrxmega6_TRUE@ strcat.S \ @HAS_avrxmega6_TRUE@ strchr.S \ @HAS_avrxmega6_TRUE@ strchrnul.S \ @HAS_avrxmega6_TRUE@ strcmp.S \ @HAS_avrxmega6_TRUE@ strcpy.S \ @HAS_avrxmega6_TRUE@ strcspn.S \ @HAS_avrxmega6_TRUE@ strlcat.S \ @HAS_avrxmega6_TRUE@ strlcpy.S \ @HAS_avrxmega6_TRUE@ strlen.S \ @HAS_avrxmega6_TRUE@ strlwr.S \ @HAS_avrxmega6_TRUE@ strncasecmp.S \ @HAS_avrxmega6_TRUE@ strncat.S \ @HAS_avrxmega6_TRUE@ strncmp.S \ @HAS_avrxmega6_TRUE@ strncpy.S \ @HAS_avrxmega6_TRUE@ strnlen.S \ @HAS_avrxmega6_TRUE@ strpbrk.S \ @HAS_avrxmega6_TRUE@ strrchr.S \ @HAS_avrxmega6_TRUE@ strrev.S \ @HAS_avrxmega6_TRUE@ strsep.S \ @HAS_avrxmega6_TRUE@ strspn.S \ @HAS_avrxmega6_TRUE@ strstr.S \ @HAS_avrxmega6_TRUE@ strtok_r.S \ @HAS_avrxmega6_TRUE@ strupr.S @HAS_avrxmega6_TRUE@string_a_extra_dist = \ @HAS_avrxmega6_TRUE@ strlcat.c \ @HAS_avrxmega6_TRUE@ strlcpy.c @HAS_avrxmega6_TRUE@misc_a_c_sources = @HAS_avrxmega6_TRUE@eeprom_asm_sources = \ @HAS_avrxmega6_TRUE@ eerd_block.S \ @HAS_avrxmega6_TRUE@ eerd_byte.S \ @HAS_avrxmega6_TRUE@ eerd_dword.S \ @HAS_avrxmega6_TRUE@ eerd_word.S \ @HAS_avrxmega6_TRUE@ eeupd_block.S \ @HAS_avrxmega6_TRUE@ eeupd_byte.S \ @HAS_avrxmega6_TRUE@ eeupd_dword.S \ @HAS_avrxmega6_TRUE@ eeupd_word.S \ @HAS_avrxmega6_TRUE@ eewr_block.S \ @HAS_avrxmega6_TRUE@ eewr_byte.S \ @HAS_avrxmega6_TRUE@ eewr_dword.S \ @HAS_avrxmega6_TRUE@ eewr_word.S @HAS_avrxmega6_TRUE@misc_a_asm_sources = \ @HAS_avrxmega6_TRUE@ itoa.S \ @HAS_avrxmega6_TRUE@ ltoa.S \ @HAS_avrxmega6_TRUE@ mulsi10.S \ @HAS_avrxmega6_TRUE@ mul10.S \ @HAS_avrxmega6_TRUE@ ultoa.S \ @HAS_avrxmega6_TRUE@ utoa.S @HAS_avrxmega6_TRUE@misc_a_extra_dist = \ @HAS_avrxmega6_TRUE@ eedef.h \ @HAS_avrxmega6_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avrxmega6_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avrxmega6_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avrxmega6_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avrxmega6_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avrxmega6_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avrxmega6_TRUE@misc_a_libadd = \ @HAS_avrxmega6_TRUE@ $(eeprom_asm_objlist) @HAS_avrxmega6_TRUE@stdio_a_c_sources = \ @HAS_avrxmega6_TRUE@ clearerr.c \ @HAS_avrxmega6_TRUE@ fclose.c \ @HAS_avrxmega6_TRUE@ fdevopen.c \ @HAS_avrxmega6_TRUE@ feof.c \ @HAS_avrxmega6_TRUE@ ferror.c \ @HAS_avrxmega6_TRUE@ fgetc.c \ @HAS_avrxmega6_TRUE@ fgets.c \ @HAS_avrxmega6_TRUE@ fprintf.c \ @HAS_avrxmega6_TRUE@ fprintf_p.c \ @HAS_avrxmega6_TRUE@ fputc.c \ @HAS_avrxmega6_TRUE@ fputs.c \ @HAS_avrxmega6_TRUE@ fputs_p.c \ @HAS_avrxmega6_TRUE@ fread.c \ @HAS_avrxmega6_TRUE@ fscanf.c \ @HAS_avrxmega6_TRUE@ fscanf_p.c \ @HAS_avrxmega6_TRUE@ fwrite.c \ @HAS_avrxmega6_TRUE@ getchar.c \ @HAS_avrxmega6_TRUE@ gets.c \ @HAS_avrxmega6_TRUE@ iob.c \ @HAS_avrxmega6_TRUE@ printf.c \ @HAS_avrxmega6_TRUE@ printf_p.c \ @HAS_avrxmega6_TRUE@ putchar.c \ @HAS_avrxmega6_TRUE@ puts.c \ @HAS_avrxmega6_TRUE@ puts_p.c \ @HAS_avrxmega6_TRUE@ scanf.c \ @HAS_avrxmega6_TRUE@ scanf_p.c \ @HAS_avrxmega6_TRUE@ snprintf.c \ @HAS_avrxmega6_TRUE@ snprintf_p.c \ @HAS_avrxmega6_TRUE@ sprintf.c \ @HAS_avrxmega6_TRUE@ sprintf_p.c \ @HAS_avrxmega6_TRUE@ sscanf.c \ @HAS_avrxmega6_TRUE@ sscanf_p.c \ @HAS_avrxmega6_TRUE@ vfprintf_p.c \ @HAS_avrxmega6_TRUE@ vfscanf_p.c \ @HAS_avrxmega6_TRUE@ vprintf.c \ @HAS_avrxmega6_TRUE@ vscanf.c \ @HAS_avrxmega6_TRUE@ vsnprintf.c \ @HAS_avrxmega6_TRUE@ vsnprintf_p.c \ @HAS_avrxmega6_TRUE@ vsprintf.c \ @HAS_avrxmega6_TRUE@ vsprintf_p.c \ @HAS_avrxmega6_TRUE@ ungetc.c @HAS_avrxmega6_TRUE@stdio_a_asm_sources = \ @HAS_avrxmega6_TRUE@ getc.S \ @HAS_avrxmega6_TRUE@ putc.S \ @HAS_avrxmega6_TRUE@ ultoa_invert.S @HAS_avrxmega6_TRUE@stdio_a_extra_dist = \ @HAS_avrxmega6_TRUE@ vfprintf.c \ @HAS_avrxmega6_TRUE@ vfscanf.c \ @HAS_avrxmega6_TRUE@ stdio_private.h \ @HAS_avrxmega6_TRUE@ xtoa_fast.h @HAS_avrxmega6_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avrxmega6_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avrxmega6_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avrxmega6_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avrxmega6_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avrxmega6_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avrxmega6_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avrxmega6_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avrxmega6_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avrxmega6_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avrxmega6_TRUE@libm_a_c_sources = @HAS_avrxmega6_TRUE@libm_a_asm_sources = \ @HAS_avrxmega6_TRUE@ acos.S \ @HAS_avrxmega6_TRUE@ addsf3.S \ @HAS_avrxmega6_TRUE@ addsf3x.S \ @HAS_avrxmega6_TRUE@ asin.S \ @HAS_avrxmega6_TRUE@ atan2.S \ @HAS_avrxmega6_TRUE@ atan.S \ @HAS_avrxmega6_TRUE@ cbrt.S \ @HAS_avrxmega6_TRUE@ ceil.S \ @HAS_avrxmega6_TRUE@ cmpsf2.S \ @HAS_avrxmega6_TRUE@ copysign.S \ @HAS_avrxmega6_TRUE@ cosh.S \ @HAS_avrxmega6_TRUE@ cos.S \ @HAS_avrxmega6_TRUE@ divsf3.S \ @HAS_avrxmega6_TRUE@ divsf3x.S \ @HAS_avrxmega6_TRUE@ exp.S \ @HAS_avrxmega6_TRUE@ fixsfdi.S \ @HAS_avrxmega6_TRUE@ fixsfsi.S \ @HAS_avrxmega6_TRUE@ fixunssfsi.S \ @HAS_avrxmega6_TRUE@ floatdisf.S \ @HAS_avrxmega6_TRUE@ floatsisf.S \ @HAS_avrxmega6_TRUE@ floatundisf.S \ @HAS_avrxmega6_TRUE@ fdim.S \ @HAS_avrxmega6_TRUE@ floor.S \ @HAS_avrxmega6_TRUE@ fma.S \ @HAS_avrxmega6_TRUE@ fmax.S \ @HAS_avrxmega6_TRUE@ fmin.S \ @HAS_avrxmega6_TRUE@ fmod.S \ @HAS_avrxmega6_TRUE@ fp_arccos.S \ @HAS_avrxmega6_TRUE@ fp_cmp.S \ @HAS_avrxmega6_TRUE@ fp_inf.S \ @HAS_avrxmega6_TRUE@ fp_mintl.S \ @HAS_avrxmega6_TRUE@ fp_mpack.S \ @HAS_avrxmega6_TRUE@ fp_nan.S \ @HAS_avrxmega6_TRUE@ fp_negdi.S \ @HAS_avrxmega6_TRUE@ fp_norm2.S \ @HAS_avrxmega6_TRUE@ fp_powser.S \ @HAS_avrxmega6_TRUE@ fp_powsodd.S \ @HAS_avrxmega6_TRUE@ fp_pscA.S \ @HAS_avrxmega6_TRUE@ fp_pscB.S \ @HAS_avrxmega6_TRUE@ fp_rempio2.S \ @HAS_avrxmega6_TRUE@ fp_round.S \ @HAS_avrxmega6_TRUE@ fp_sinus.S \ @HAS_avrxmega6_TRUE@ fp_split3.S \ @HAS_avrxmega6_TRUE@ fp_trunc.S \ @HAS_avrxmega6_TRUE@ fp_zero.S \ @HAS_avrxmega6_TRUE@ frexp.S \ @HAS_avrxmega6_TRUE@ gesf2.S \ @HAS_avrxmega6_TRUE@ hypot.S \ @HAS_avrxmega6_TRUE@ inverse.S \ @HAS_avrxmega6_TRUE@ isfinite.S \ @HAS_avrxmega6_TRUE@ isinf.S \ @HAS_avrxmega6_TRUE@ isnan.S \ @HAS_avrxmega6_TRUE@ ldexp.S \ @HAS_avrxmega6_TRUE@ log10.S \ @HAS_avrxmega6_TRUE@ log.S \ @HAS_avrxmega6_TRUE@ lrint.S \ @HAS_avrxmega6_TRUE@ lround.S \ @HAS_avrxmega6_TRUE@ modf.S \ @HAS_avrxmega6_TRUE@ mulsf3.S \ @HAS_avrxmega6_TRUE@ mulsf3x.S \ @HAS_avrxmega6_TRUE@ negsf2.S \ @HAS_avrxmega6_TRUE@ pow.S \ @HAS_avrxmega6_TRUE@ round.S \ @HAS_avrxmega6_TRUE@ signbit.S \ @HAS_avrxmega6_TRUE@ sinh.S \ @HAS_avrxmega6_TRUE@ sin.S \ @HAS_avrxmega6_TRUE@ sqrt.S \ @HAS_avrxmega6_TRUE@ square.S \ @HAS_avrxmega6_TRUE@ tanh.S \ @HAS_avrxmega6_TRUE@ tan.S \ @HAS_avrxmega6_TRUE@ trunc.S \ @HAS_avrxmega6_TRUE@ unordsf2.S @HAS_avrxmega6_TRUE@libm_a_extra_dist = \ @HAS_avrxmega6_TRUE@ asmdef.h \ @HAS_avrxmega6_TRUE@ fp32def.h \ @HAS_avrxmega6_TRUE@ ntz.h @HAS_avrxmega6_TRUE@nodist_libc_a_SOURCES = \ @HAS_avrxmega6_TRUE@ $(stdlib_a_c_sources) \ @HAS_avrxmega6_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avrxmega6_TRUE@ $(pmstring_a_c_sources) \ @HAS_avrxmega6_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avrxmega6_TRUE@ $(string_a_c_sources) \ @HAS_avrxmega6_TRUE@ $(string_a_asm_sources) \ @HAS_avrxmega6_TRUE@ $(misc_a_c_sources) \ @HAS_avrxmega6_TRUE@ $(misc_a_asm_sources) \ @HAS_avrxmega6_TRUE@ $(stdio_a_c_sources) \ @HAS_avrxmega6_TRUE@ $(stdio_a_asm_sources) \ @HAS_avrxmega6_TRUE@ $(libm_a_c_sources) \ @HAS_avrxmega6_TRUE@ $(libm_a_asm_sources) @HAS_avrxmega6_TRUE@nodist_libm_a_SOURCES = \ @HAS_avrxmega6_TRUE@ $(libm_a_c_sources) \ @HAS_avrxmega6_TRUE@ $(libm_a_asm_sources) @HAS_avrxmega6_TRUE@libc_a_LIBADD = \ @HAS_avrxmega6_TRUE@ $(stdio_a_libadd) \ @HAS_avrxmega6_TRUE@ $(misc_a_libadd) @HAS_avrxmega6_TRUE@libc_a_DEPENDENCIES = \ @HAS_avrxmega6_TRUE@ $(stdio_a_libadd) \ @HAS_avrxmega6_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am $(top_srcdir)/libc/misc/Rules.am $(top_srcdir)/libc/misc/Files.am $(top_srcdir)/libc/stdio/Rules.am $(top_srcdir)/libc/stdio/Files.am $(top_srcdir)/libm/fplib/Rules.am $(top_srcdir)/libm/fplib/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign avr/lib/avrxmega6/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign avr/lib/avrxmega6/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): install-avrLIBRARIES: $(avr_LIBRARIES) @$(NORMAL_INSTALL) test -z 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libc.a: $(libc_a_OBJECTS) $(libc_a_DEPENDENCIES) -rm -f libc.a $(libc_a_AR) libc.a $(libc_a_OBJECTS) $(libc_a_LIBADD) $(RANLIB) libc.a libm.a: $(libm_a_OBJECTS) $(libm_a_DEPENDENCIES) -rm -f libm.a $(libm_a_AR) libm.a $(libm_a_OBJECTS) $(libm_a_LIBADD) $(RANLIB) libm.a libprintf_flt.a: $(libprintf_flt_a_OBJECTS) $(libprintf_flt_a_DEPENDENCIES) -rm -f libprintf_flt.a $(libprintf_flt_a_AR) libprintf_flt.a $(libprintf_flt_a_OBJECTS) $(libprintf_flt_a_LIBADD) $(RANLIB) libprintf_flt.a libprintf_min.a: $(libprintf_min_a_OBJECTS) $(libprintf_min_a_DEPENDENCIES) -rm -f libprintf_min.a $(libprintf_min_a_AR) libprintf_min.a $(libprintf_min_a_OBJECTS) $(libprintf_min_a_LIBADD) $(RANLIB) libprintf_min.a libscanf_flt.a: $(libscanf_flt_a_OBJECTS) $(libscanf_flt_a_DEPENDENCIES) -rm -f libscanf_flt.a $(libscanf_flt_a_AR) libscanf_flt.a $(libscanf_flt_a_OBJECTS) $(libscanf_flt_a_LIBADD) $(RANLIB) libscanf_flt.a libscanf_min.a: $(libscanf_min_a_OBJECTS) $(libscanf_min_a_DEPENDENCIES) -rm -f libscanf_min.a $(libscanf_min_a_AR) libscanf_min.a $(libscanf_min_a_OBJECTS) $(libscanf_min_a_LIBADD) $(RANLIB) libscanf_min.a mostlyclean-compile: -rm -f *.$(OBJEXT) distclean-compile: -rm -f *.tab.c @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/abort.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/abs.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/acos.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/addsf3.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/addsf3x.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/asin.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/assert.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/atan.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/atan2.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/atof.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/atoi.Po@am__quote@ @AMDEP_TRUE@@am__include@ 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@am__quote@./$(DEPDIR)/dtoa_prf.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dtostre.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dtostrf.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/errno.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/exit.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/exp.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fclose.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdevopen.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdim.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/feof.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ferror.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ffs.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ffsl.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ffsll.Po@am__quote@ @AMDEP_TRUE@@am__include@ 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BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : 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$(__install_dir) @HAS_avr51_TRUE@avrlibdir = $(__install_dir) @HAS_avr51_TRUE@avr_LIBRARIES = \ @HAS_avr51_TRUE@ libc.a \ @HAS_avr51_TRUE@ libprintf_min.a \ @HAS_avr51_TRUE@ libprintf_flt.a \ @HAS_avr51_TRUE@ libscanf_min.a \ @HAS_avr51_TRUE@ libscanf_flt.a \ @HAS_avr51_TRUE@ libm.a @HAS_avr51_TRUE@stdlib_a_c_sources = \ @HAS_avr51_TRUE@ abs.c \ @HAS_avr51_TRUE@ assert.c \ @HAS_avr51_TRUE@ bsearch.c \ @HAS_avr51_TRUE@ calloc.c \ @HAS_avr51_TRUE@ errno.c \ @HAS_avr51_TRUE@ dtoa_prf.c \ @HAS_avr51_TRUE@ dtostre.c \ @HAS_avr51_TRUE@ dtostrf.c \ @HAS_avr51_TRUE@ labs.c \ @HAS_avr51_TRUE@ malloc.c \ @HAS_avr51_TRUE@ qsort.c \ @HAS_avr51_TRUE@ rand.c \ @HAS_avr51_TRUE@ random.c \ @HAS_avr51_TRUE@ realloc.c \ @HAS_avr51_TRUE@ strtod.c \ @HAS_avr51_TRUE@ strtol.c \ @HAS_avr51_TRUE@ strtoul.c \ @HAS_avr51_TRUE@ dtoa_conv.h \ @HAS_avr51_TRUE@ stdlib_private.h @HAS_avr51_TRUE@stdlib_a_asm_sources = \ @HAS_avr51_TRUE@ abort.S \ @HAS_avr51_TRUE@ atof.S \ @HAS_avr51_TRUE@ atoi.S \ @HAS_avr51_TRUE@ atol.S \ @HAS_avr51_TRUE@ div.S \ @HAS_avr51_TRUE@ exit.S \ @HAS_avr51_TRUE@ ftoa_engine.S \ @HAS_avr51_TRUE@ ldiv.S \ @HAS_avr51_TRUE@ setjmp.S \ @HAS_avr51_TRUE@ isascii.S \ @HAS_avr51_TRUE@ toascii.S \ @HAS_avr51_TRUE@ isalnum.S \ @HAS_avr51_TRUE@ cty_isfalse.S \ @HAS_avr51_TRUE@ isalpha.S \ @HAS_avr51_TRUE@ isdigit.S \ @HAS_avr51_TRUE@ isxdigit.S \ @HAS_avr51_TRUE@ iscntrl.S \ @HAS_avr51_TRUE@ isprint.S \ @HAS_avr51_TRUE@ isspace.S \ @HAS_avr51_TRUE@ isblank.S \ @HAS_avr51_TRUE@ ispunct.S \ @HAS_avr51_TRUE@ tolower.S \ @HAS_avr51_TRUE@ toupper.S @HAS_avr51_TRUE@stdlib_a_extra_dist = \ @HAS_avr51_TRUE@ ctype.S \ @HAS_avr51_TRUE@ abort.c \ @HAS_avr51_TRUE@ atoi.c \ @HAS_avr51_TRUE@ atol.c @HAS_avr51_TRUE@pmstring_a_c_sources = \ @HAS_avr51_TRUE@ strtok_P.c @HAS_avr51_TRUE@pmstring_a_asm_sources = \ @HAS_avr51_TRUE@ memchr_P.S \ @HAS_avr51_TRUE@ memcmp_P.S \ @HAS_avr51_TRUE@ memccpy_P.S \ @HAS_avr51_TRUE@ memcpy_P.S \ @HAS_avr51_TRUE@ memrchr_P.S \ @HAS_avr51_TRUE@ strcasecmp_P.S \ @HAS_avr51_TRUE@ strcat_P.S \ @HAS_avr51_TRUE@ strchr_P.S \ @HAS_avr51_TRUE@ strchrnul_P.S \ @HAS_avr51_TRUE@ strcmp_P.S \ @HAS_avr51_TRUE@ strcpy_P.S \ @HAS_avr51_TRUE@ strcspn_P.S \ @HAS_avr51_TRUE@ strlcat_P.S \ @HAS_avr51_TRUE@ strlcpy_P.S \ @HAS_avr51_TRUE@ strlen_P.S \ @HAS_avr51_TRUE@ strncasecmp_P.S \ @HAS_avr51_TRUE@ strncat_P.S \ @HAS_avr51_TRUE@ strncmp_P.S \ @HAS_avr51_TRUE@ strncpy_P.S \ @HAS_avr51_TRUE@ strnlen_P.S \ @HAS_avr51_TRUE@ strpbrk_P.S \ @HAS_avr51_TRUE@ strrchr_P.S \ @HAS_avr51_TRUE@ strsep_P.S \ @HAS_avr51_TRUE@ strspn_P.S \ @HAS_avr51_TRUE@ strstr_P.S \ @HAS_avr51_TRUE@ strtok_rP.S \ @HAS_avr51_TRUE@ memcpy_PF.S \ @HAS_avr51_TRUE@ strcasecmp_PF.S \ @HAS_avr51_TRUE@ strcat_PF.S \ @HAS_avr51_TRUE@ strcmp_PF.S \ @HAS_avr51_TRUE@ strcpy_PF.S \ @HAS_avr51_TRUE@ strlcat_PF.S \ @HAS_avr51_TRUE@ strlcpy_PF.S \ @HAS_avr51_TRUE@ strlen_PF.S \ @HAS_avr51_TRUE@ strncasecmp_PF.S \ @HAS_avr51_TRUE@ strncat_PF.S \ @HAS_avr51_TRUE@ strncmp_PF.S \ @HAS_avr51_TRUE@ strncpy_PF.S \ @HAS_avr51_TRUE@ strnlen_PF.S \ @HAS_avr51_TRUE@ strstr_PF.S \ @HAS_avr51_TRUE@ memcmp_PF.S @HAS_avr51_TRUE@string_a_c_sources = \ @HAS_avr51_TRUE@ strdup.c \ @HAS_avr51_TRUE@ strtok.c @HAS_avr51_TRUE@string_a_asm_sources = \ @HAS_avr51_TRUE@ ffs.S \ @HAS_avr51_TRUE@ ffsl.S \ @HAS_avr51_TRUE@ ffsll.S \ @HAS_avr51_TRUE@ memccpy.S \ @HAS_avr51_TRUE@ memchr.S \ @HAS_avr51_TRUE@ memcmp.S \ @HAS_avr51_TRUE@ memcpy.S \ @HAS_avr51_TRUE@ memmem.S \ @HAS_avr51_TRUE@ memmem_P.S \ @HAS_avr51_TRUE@ memmove.S \ @HAS_avr51_TRUE@ memrchr.S \ @HAS_avr51_TRUE@ memset.S \ @HAS_avr51_TRUE@ strcasecmp.S \ @HAS_avr51_TRUE@ strcasestr.S \ @HAS_avr51_TRUE@ strcasestr_P.S \ @HAS_avr51_TRUE@ strcat.S \ @HAS_avr51_TRUE@ strchr.S \ @HAS_avr51_TRUE@ strchrnul.S \ @HAS_avr51_TRUE@ strcmp.S \ @HAS_avr51_TRUE@ strcpy.S \ @HAS_avr51_TRUE@ strcspn.S \ @HAS_avr51_TRUE@ strlcat.S \ @HAS_avr51_TRUE@ strlcpy.S \ @HAS_avr51_TRUE@ strlen.S \ @HAS_avr51_TRUE@ strlwr.S \ @HAS_avr51_TRUE@ strncasecmp.S \ @HAS_avr51_TRUE@ strncat.S \ @HAS_avr51_TRUE@ strncmp.S \ @HAS_avr51_TRUE@ strncpy.S \ @HAS_avr51_TRUE@ strnlen.S \ @HAS_avr51_TRUE@ strpbrk.S \ @HAS_avr51_TRUE@ strrchr.S \ @HAS_avr51_TRUE@ strrev.S \ @HAS_avr51_TRUE@ strsep.S \ @HAS_avr51_TRUE@ strspn.S \ @HAS_avr51_TRUE@ strstr.S \ @HAS_avr51_TRUE@ strtok_r.S \ @HAS_avr51_TRUE@ strupr.S @HAS_avr51_TRUE@string_a_extra_dist = \ @HAS_avr51_TRUE@ strlcat.c \ @HAS_avr51_TRUE@ strlcpy.c @HAS_avr51_TRUE@misc_a_c_sources = @HAS_avr51_TRUE@eeprom_asm_sources = \ @HAS_avr51_TRUE@ eerd_block.S \ @HAS_avr51_TRUE@ eerd_byte.S \ @HAS_avr51_TRUE@ eerd_dword.S \ @HAS_avr51_TRUE@ eerd_word.S \ @HAS_avr51_TRUE@ eeupd_block.S \ @HAS_avr51_TRUE@ eeupd_byte.S \ @HAS_avr51_TRUE@ eeupd_dword.S \ @HAS_avr51_TRUE@ eeupd_word.S \ @HAS_avr51_TRUE@ eewr_block.S \ @HAS_avr51_TRUE@ eewr_byte.S \ @HAS_avr51_TRUE@ eewr_dword.S \ @HAS_avr51_TRUE@ eewr_word.S @HAS_avr51_TRUE@misc_a_asm_sources = \ @HAS_avr51_TRUE@ itoa.S \ @HAS_avr51_TRUE@ ltoa.S \ @HAS_avr51_TRUE@ mulsi10.S \ @HAS_avr51_TRUE@ mul10.S \ @HAS_avr51_TRUE@ ultoa.S \ @HAS_avr51_TRUE@ utoa.S @HAS_avr51_TRUE@misc_a_extra_dist = \ @HAS_avr51_TRUE@ eedef.h \ @HAS_avr51_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avr51_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avr51_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avr51_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avr51_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avr51_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avr51_TRUE@misc_a_libadd = \ @HAS_avr51_TRUE@ $(eeprom_asm_objlist) @HAS_avr51_TRUE@stdio_a_c_sources = \ @HAS_avr51_TRUE@ clearerr.c \ @HAS_avr51_TRUE@ fclose.c \ @HAS_avr51_TRUE@ fdevopen.c \ @HAS_avr51_TRUE@ feof.c \ @HAS_avr51_TRUE@ ferror.c \ @HAS_avr51_TRUE@ fgetc.c \ @HAS_avr51_TRUE@ fgets.c \ @HAS_avr51_TRUE@ fprintf.c \ @HAS_avr51_TRUE@ fprintf_p.c \ @HAS_avr51_TRUE@ fputc.c \ @HAS_avr51_TRUE@ fputs.c \ @HAS_avr51_TRUE@ fputs_p.c \ @HAS_avr51_TRUE@ fread.c \ @HAS_avr51_TRUE@ fscanf.c \ @HAS_avr51_TRUE@ fscanf_p.c \ @HAS_avr51_TRUE@ fwrite.c \ @HAS_avr51_TRUE@ getchar.c \ @HAS_avr51_TRUE@ gets.c \ @HAS_avr51_TRUE@ iob.c \ @HAS_avr51_TRUE@ printf.c \ @HAS_avr51_TRUE@ printf_p.c \ @HAS_avr51_TRUE@ putchar.c \ @HAS_avr51_TRUE@ puts.c \ @HAS_avr51_TRUE@ puts_p.c \ @HAS_avr51_TRUE@ scanf.c \ @HAS_avr51_TRUE@ scanf_p.c \ @HAS_avr51_TRUE@ snprintf.c \ @HAS_avr51_TRUE@ snprintf_p.c \ @HAS_avr51_TRUE@ sprintf.c \ @HAS_avr51_TRUE@ sprintf_p.c \ @HAS_avr51_TRUE@ sscanf.c \ @HAS_avr51_TRUE@ sscanf_p.c \ @HAS_avr51_TRUE@ vfprintf_p.c \ @HAS_avr51_TRUE@ vfscanf_p.c \ @HAS_avr51_TRUE@ vprintf.c \ @HAS_avr51_TRUE@ vscanf.c \ @HAS_avr51_TRUE@ vsnprintf.c \ @HAS_avr51_TRUE@ vsnprintf_p.c \ @HAS_avr51_TRUE@ vsprintf.c \ @HAS_avr51_TRUE@ vsprintf_p.c \ @HAS_avr51_TRUE@ ungetc.c @HAS_avr51_TRUE@stdio_a_asm_sources = \ @HAS_avr51_TRUE@ getc.S \ @HAS_avr51_TRUE@ putc.S \ @HAS_avr51_TRUE@ ultoa_invert.S @HAS_avr51_TRUE@stdio_a_extra_dist = \ @HAS_avr51_TRUE@ vfprintf.c \ @HAS_avr51_TRUE@ vfscanf.c \ @HAS_avr51_TRUE@ stdio_private.h \ @HAS_avr51_TRUE@ xtoa_fast.h @HAS_avr51_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avr51_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avr51_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avr51_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avr51_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avr51_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avr51_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avr51_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avr51_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avr51_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avr51_TRUE@libm_a_c_sources = @HAS_avr51_TRUE@libm_a_asm_sources = \ @HAS_avr51_TRUE@ acos.S \ @HAS_avr51_TRUE@ addsf3.S \ @HAS_avr51_TRUE@ addsf3x.S \ @HAS_avr51_TRUE@ asin.S \ @HAS_avr51_TRUE@ atan2.S \ @HAS_avr51_TRUE@ atan.S \ @HAS_avr51_TRUE@ cbrt.S \ @HAS_avr51_TRUE@ ceil.S \ @HAS_avr51_TRUE@ cmpsf2.S \ @HAS_avr51_TRUE@ copysign.S \ @HAS_avr51_TRUE@ cosh.S \ @HAS_avr51_TRUE@ cos.S \ @HAS_avr51_TRUE@ divsf3.S \ @HAS_avr51_TRUE@ divsf3x.S \ @HAS_avr51_TRUE@ exp.S \ @HAS_avr51_TRUE@ fixsfdi.S \ @HAS_avr51_TRUE@ fixsfsi.S \ @HAS_avr51_TRUE@ fixunssfsi.S \ @HAS_avr51_TRUE@ floatdisf.S \ @HAS_avr51_TRUE@ floatsisf.S \ @HAS_avr51_TRUE@ floatundisf.S \ @HAS_avr51_TRUE@ fdim.S \ @HAS_avr51_TRUE@ floor.S \ @HAS_avr51_TRUE@ fma.S \ @HAS_avr51_TRUE@ fmax.S \ @HAS_avr51_TRUE@ fmin.S \ @HAS_avr51_TRUE@ fmod.S \ @HAS_avr51_TRUE@ fp_arccos.S \ @HAS_avr51_TRUE@ fp_cmp.S \ @HAS_avr51_TRUE@ fp_inf.S \ @HAS_avr51_TRUE@ fp_mintl.S \ @HAS_avr51_TRUE@ fp_mpack.S \ @HAS_avr51_TRUE@ fp_nan.S \ @HAS_avr51_TRUE@ fp_negdi.S \ @HAS_avr51_TRUE@ fp_norm2.S \ @HAS_avr51_TRUE@ fp_powser.S \ @HAS_avr51_TRUE@ fp_powsodd.S \ @HAS_avr51_TRUE@ fp_pscA.S \ @HAS_avr51_TRUE@ fp_pscB.S \ @HAS_avr51_TRUE@ fp_rempio2.S \ @HAS_avr51_TRUE@ fp_round.S \ @HAS_avr51_TRUE@ fp_sinus.S \ @HAS_avr51_TRUE@ fp_split3.S \ @HAS_avr51_TRUE@ fp_trunc.S \ @HAS_avr51_TRUE@ fp_zero.S \ @HAS_avr51_TRUE@ frexp.S \ @HAS_avr51_TRUE@ gesf2.S \ @HAS_avr51_TRUE@ hypot.S \ @HAS_avr51_TRUE@ inverse.S \ @HAS_avr51_TRUE@ isfinite.S \ @HAS_avr51_TRUE@ isinf.S \ @HAS_avr51_TRUE@ isnan.S \ @HAS_avr51_TRUE@ ldexp.S \ @HAS_avr51_TRUE@ log10.S \ @HAS_avr51_TRUE@ log.S \ @HAS_avr51_TRUE@ lrint.S \ @HAS_avr51_TRUE@ lround.S \ @HAS_avr51_TRUE@ modf.S \ @HAS_avr51_TRUE@ mulsf3.S \ @HAS_avr51_TRUE@ mulsf3x.S \ @HAS_avr51_TRUE@ negsf2.S \ @HAS_avr51_TRUE@ pow.S \ @HAS_avr51_TRUE@ round.S \ @HAS_avr51_TRUE@ signbit.S \ @HAS_avr51_TRUE@ sinh.S \ @HAS_avr51_TRUE@ sin.S \ @HAS_avr51_TRUE@ sqrt.S \ @HAS_avr51_TRUE@ square.S \ @HAS_avr51_TRUE@ tanh.S \ @HAS_avr51_TRUE@ tan.S \ @HAS_avr51_TRUE@ trunc.S \ @HAS_avr51_TRUE@ unordsf2.S @HAS_avr51_TRUE@libm_a_extra_dist = \ @HAS_avr51_TRUE@ asmdef.h \ @HAS_avr51_TRUE@ fp32def.h \ @HAS_avr51_TRUE@ ntz.h @HAS_avr51_TRUE@nodist_libc_a_SOURCES = \ @HAS_avr51_TRUE@ $(stdlib_a_c_sources) \ @HAS_avr51_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avr51_TRUE@ $(pmstring_a_c_sources) \ @HAS_avr51_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avr51_TRUE@ $(string_a_c_sources) \ @HAS_avr51_TRUE@ $(string_a_asm_sources) \ @HAS_avr51_TRUE@ $(misc_a_c_sources) \ @HAS_avr51_TRUE@ $(misc_a_asm_sources) \ @HAS_avr51_TRUE@ $(stdio_a_c_sources) \ @HAS_avr51_TRUE@ $(stdio_a_asm_sources) \ @HAS_avr51_TRUE@ $(libm_a_c_sources) \ @HAS_avr51_TRUE@ $(libm_a_asm_sources) @HAS_avr51_TRUE@nodist_libm_a_SOURCES = \ @HAS_avr51_TRUE@ $(libm_a_c_sources) \ @HAS_avr51_TRUE@ $(libm_a_asm_sources) @HAS_avr51_TRUE@libc_a_LIBADD = \ @HAS_avr51_TRUE@ $(stdio_a_libadd) \ @HAS_avr51_TRUE@ $(misc_a_libadd) @HAS_avr51_TRUE@libc_a_DEPENDENCIES = \ @HAS_avr51_TRUE@ $(stdio_a_libadd) \ @HAS_avr51_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am $(top_srcdir)/libc/misc/Rules.am $(top_srcdir)/libc/misc/Files.am $(top_srcdir)/libc/stdio/Rules.am $(top_srcdir)/libc/stdio/Files.am $(top_srcdir)/libm/fplib/Rules.am $(top_srcdir)/libm/fplib/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign avr/lib/avr51/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign avr/lib/avr51/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): install-avrLIBRARIES: $(avr_LIBRARIES) @$(NORMAL_INSTALL) test -z "$(avrdir)" || $(MKDIR_P) "$(DESTDIR)$(avrdir)" @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : 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@mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ SUBDIRS = atxmega16a4 atxmega16d4 atxmega32a4 atxmega32d4 AVR_TARGET = avrxmega2 AVR_TARGET_DEFS = -D__COMPILING_AVR_LIBC__ AVR_TARGET_CFLAGS = -mcall-prologues -Os AVR_TARGET_ASFLAGS = AVR_INSTALL_DIR = avrxmega2 @HAS_avrxmega2_TRUE@AVRLIB_DEVLIST = $(am__append_1) $(am__append_2) \ @HAS_avrxmega2_TRUE@ $(am__append_3) $(am__append_4) @HAS_avrxmega2_TRUE@AM_CPPFLAGS = -I$(top_srcdir)/common -I$(top_srcdir)/include -I$(top_builddir)/include @HAS_avrxmega2_TRUE@AVRLIB_CFLAGS = -g -Wall -W -Wstrict-prototypes -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_CFLAGS) @HAS_avrxmega2_TRUE@AVRLIB_ASFLAGS = -x assembler-with-cpp -Wa,-gstabs -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_ASFLAGS) @HAS_avrxmega2_TRUE@AM_CFLAGS = $(AVRLIB_CFLAGS) @HAS_avrxmega2_TRUE@AM_CCASFLAGS = $(AM_CPPFLAGS) $(AVRLIB_ASFLAGS) @HAS_avrxmega2_TRUE@__install_dir = $(prefix)/avr/lib/$(AVR_INSTALL_DIR) @HAS_avrxmega2_TRUE@avrdir = $(__install_dir) @HAS_avrxmega2_TRUE@avrlibdir = $(__install_dir) @HAS_avrxmega2_TRUE@avr_LIBRARIES = \ @HAS_avrxmega2_TRUE@ libc.a \ @HAS_avrxmega2_TRUE@ libprintf_min.a \ @HAS_avrxmega2_TRUE@ libprintf_flt.a \ @HAS_avrxmega2_TRUE@ libscanf_min.a \ @HAS_avrxmega2_TRUE@ libscanf_flt.a \ @HAS_avrxmega2_TRUE@ libm.a @HAS_avrxmega2_TRUE@stdlib_a_c_sources = \ @HAS_avrxmega2_TRUE@ abs.c \ @HAS_avrxmega2_TRUE@ assert.c \ @HAS_avrxmega2_TRUE@ bsearch.c \ @HAS_avrxmega2_TRUE@ calloc.c \ @HAS_avrxmega2_TRUE@ errno.c \ @HAS_avrxmega2_TRUE@ dtoa_prf.c \ @HAS_avrxmega2_TRUE@ dtostre.c \ @HAS_avrxmega2_TRUE@ dtostrf.c \ @HAS_avrxmega2_TRUE@ labs.c \ @HAS_avrxmega2_TRUE@ malloc.c \ @HAS_avrxmega2_TRUE@ qsort.c \ @HAS_avrxmega2_TRUE@ rand.c \ @HAS_avrxmega2_TRUE@ random.c \ @HAS_avrxmega2_TRUE@ realloc.c \ @HAS_avrxmega2_TRUE@ strtod.c \ @HAS_avrxmega2_TRUE@ strtol.c \ @HAS_avrxmega2_TRUE@ strtoul.c \ @HAS_avrxmega2_TRUE@ dtoa_conv.h \ @HAS_avrxmega2_TRUE@ stdlib_private.h @HAS_avrxmega2_TRUE@stdlib_a_asm_sources = \ @HAS_avrxmega2_TRUE@ abort.S \ @HAS_avrxmega2_TRUE@ atof.S \ @HAS_avrxmega2_TRUE@ atoi.S \ @HAS_avrxmega2_TRUE@ atol.S \ @HAS_avrxmega2_TRUE@ div.S \ @HAS_avrxmega2_TRUE@ exit.S \ @HAS_avrxmega2_TRUE@ ftoa_engine.S \ @HAS_avrxmega2_TRUE@ ldiv.S \ @HAS_avrxmega2_TRUE@ setjmp.S \ @HAS_avrxmega2_TRUE@ isascii.S \ @HAS_avrxmega2_TRUE@ toascii.S \ @HAS_avrxmega2_TRUE@ isalnum.S \ @HAS_avrxmega2_TRUE@ cty_isfalse.S \ @HAS_avrxmega2_TRUE@ isalpha.S \ @HAS_avrxmega2_TRUE@ isdigit.S \ @HAS_avrxmega2_TRUE@ isxdigit.S \ @HAS_avrxmega2_TRUE@ iscntrl.S \ @HAS_avrxmega2_TRUE@ isprint.S \ @HAS_avrxmega2_TRUE@ isspace.S \ @HAS_avrxmega2_TRUE@ isblank.S \ @HAS_avrxmega2_TRUE@ ispunct.S \ @HAS_avrxmega2_TRUE@ tolower.S \ @HAS_avrxmega2_TRUE@ toupper.S @HAS_avrxmega2_TRUE@stdlib_a_extra_dist = \ @HAS_avrxmega2_TRUE@ ctype.S \ @HAS_avrxmega2_TRUE@ abort.c \ @HAS_avrxmega2_TRUE@ atoi.c \ @HAS_avrxmega2_TRUE@ atol.c @HAS_avrxmega2_TRUE@pmstring_a_c_sources = \ @HAS_avrxmega2_TRUE@ strtok_P.c @HAS_avrxmega2_TRUE@pmstring_a_asm_sources = \ @HAS_avrxmega2_TRUE@ memchr_P.S \ @HAS_avrxmega2_TRUE@ memcmp_P.S \ @HAS_avrxmega2_TRUE@ memccpy_P.S \ @HAS_avrxmega2_TRUE@ memcpy_P.S \ @HAS_avrxmega2_TRUE@ memrchr_P.S \ @HAS_avrxmega2_TRUE@ strcasecmp_P.S \ @HAS_avrxmega2_TRUE@ strcat_P.S \ @HAS_avrxmega2_TRUE@ strchr_P.S \ @HAS_avrxmega2_TRUE@ strchrnul_P.S \ @HAS_avrxmega2_TRUE@ strcmp_P.S \ @HAS_avrxmega2_TRUE@ strcpy_P.S \ @HAS_avrxmega2_TRUE@ strcspn_P.S \ @HAS_avrxmega2_TRUE@ strlcat_P.S \ @HAS_avrxmega2_TRUE@ strlcpy_P.S \ @HAS_avrxmega2_TRUE@ strlen_P.S \ @HAS_avrxmega2_TRUE@ strncasecmp_P.S \ @HAS_avrxmega2_TRUE@ strncat_P.S \ @HAS_avrxmega2_TRUE@ strncmp_P.S \ @HAS_avrxmega2_TRUE@ strncpy_P.S \ @HAS_avrxmega2_TRUE@ strnlen_P.S \ @HAS_avrxmega2_TRUE@ strpbrk_P.S \ @HAS_avrxmega2_TRUE@ strrchr_P.S \ @HAS_avrxmega2_TRUE@ strsep_P.S \ @HAS_avrxmega2_TRUE@ strspn_P.S \ @HAS_avrxmega2_TRUE@ strstr_P.S \ @HAS_avrxmega2_TRUE@ strtok_rP.S \ @HAS_avrxmega2_TRUE@ memcpy_PF.S \ @HAS_avrxmega2_TRUE@ strcasecmp_PF.S \ @HAS_avrxmega2_TRUE@ strcat_PF.S \ @HAS_avrxmega2_TRUE@ strcmp_PF.S \ @HAS_avrxmega2_TRUE@ strcpy_PF.S \ @HAS_avrxmega2_TRUE@ strlcat_PF.S \ @HAS_avrxmega2_TRUE@ strlcpy_PF.S \ @HAS_avrxmega2_TRUE@ strlen_PF.S \ @HAS_avrxmega2_TRUE@ strncasecmp_PF.S \ @HAS_avrxmega2_TRUE@ strncat_PF.S \ @HAS_avrxmega2_TRUE@ strncmp_PF.S \ @HAS_avrxmega2_TRUE@ strncpy_PF.S \ @HAS_avrxmega2_TRUE@ strnlen_PF.S \ @HAS_avrxmega2_TRUE@ strstr_PF.S \ @HAS_avrxmega2_TRUE@ memcmp_PF.S @HAS_avrxmega2_TRUE@string_a_c_sources = \ @HAS_avrxmega2_TRUE@ strdup.c \ @HAS_avrxmega2_TRUE@ strtok.c @HAS_avrxmega2_TRUE@string_a_asm_sources = \ @HAS_avrxmega2_TRUE@ ffs.S \ @HAS_avrxmega2_TRUE@ ffsl.S \ @HAS_avrxmega2_TRUE@ ffsll.S \ @HAS_avrxmega2_TRUE@ memccpy.S \ @HAS_avrxmega2_TRUE@ memchr.S \ @HAS_avrxmega2_TRUE@ memcmp.S \ @HAS_avrxmega2_TRUE@ memcpy.S \ @HAS_avrxmega2_TRUE@ memmem.S \ @HAS_avrxmega2_TRUE@ memmem_P.S \ @HAS_avrxmega2_TRUE@ memmove.S \ @HAS_avrxmega2_TRUE@ memrchr.S \ @HAS_avrxmega2_TRUE@ memset.S \ @HAS_avrxmega2_TRUE@ strcasecmp.S \ @HAS_avrxmega2_TRUE@ strcasestr.S \ @HAS_avrxmega2_TRUE@ strcasestr_P.S \ @HAS_avrxmega2_TRUE@ strcat.S \ @HAS_avrxmega2_TRUE@ strchr.S \ @HAS_avrxmega2_TRUE@ strchrnul.S \ @HAS_avrxmega2_TRUE@ strcmp.S \ @HAS_avrxmega2_TRUE@ strcpy.S \ @HAS_avrxmega2_TRUE@ strcspn.S \ @HAS_avrxmega2_TRUE@ strlcat.S \ @HAS_avrxmega2_TRUE@ strlcpy.S \ @HAS_avrxmega2_TRUE@ strlen.S \ @HAS_avrxmega2_TRUE@ strlwr.S \ @HAS_avrxmega2_TRUE@ strncasecmp.S \ @HAS_avrxmega2_TRUE@ strncat.S \ @HAS_avrxmega2_TRUE@ strncmp.S \ @HAS_avrxmega2_TRUE@ strncpy.S \ @HAS_avrxmega2_TRUE@ strnlen.S \ @HAS_avrxmega2_TRUE@ strpbrk.S \ @HAS_avrxmega2_TRUE@ strrchr.S \ @HAS_avrxmega2_TRUE@ strrev.S \ @HAS_avrxmega2_TRUE@ strsep.S \ @HAS_avrxmega2_TRUE@ strspn.S \ @HAS_avrxmega2_TRUE@ strstr.S \ @HAS_avrxmega2_TRUE@ strtok_r.S \ @HAS_avrxmega2_TRUE@ strupr.S @HAS_avrxmega2_TRUE@string_a_extra_dist = \ @HAS_avrxmega2_TRUE@ strlcat.c \ @HAS_avrxmega2_TRUE@ strlcpy.c @HAS_avrxmega2_TRUE@misc_a_c_sources = @HAS_avrxmega2_TRUE@eeprom_asm_sources = \ @HAS_avrxmega2_TRUE@ eerd_block.S \ @HAS_avrxmega2_TRUE@ eerd_byte.S \ @HAS_avrxmega2_TRUE@ eerd_dword.S \ @HAS_avrxmega2_TRUE@ eerd_word.S \ @HAS_avrxmega2_TRUE@ eeupd_block.S \ @HAS_avrxmega2_TRUE@ eeupd_byte.S \ @HAS_avrxmega2_TRUE@ eeupd_dword.S \ @HAS_avrxmega2_TRUE@ eeupd_word.S \ @HAS_avrxmega2_TRUE@ eewr_block.S \ @HAS_avrxmega2_TRUE@ eewr_byte.S \ @HAS_avrxmega2_TRUE@ eewr_dword.S \ @HAS_avrxmega2_TRUE@ eewr_word.S @HAS_avrxmega2_TRUE@misc_a_asm_sources = \ @HAS_avrxmega2_TRUE@ itoa.S \ @HAS_avrxmega2_TRUE@ ltoa.S \ @HAS_avrxmega2_TRUE@ mulsi10.S \ @HAS_avrxmega2_TRUE@ mul10.S \ @HAS_avrxmega2_TRUE@ ultoa.S \ @HAS_avrxmega2_TRUE@ utoa.S @HAS_avrxmega2_TRUE@misc_a_extra_dist = \ @HAS_avrxmega2_TRUE@ eedef.h \ @HAS_avrxmega2_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avrxmega2_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avrxmega2_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avrxmega2_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avrxmega2_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avrxmega2_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avrxmega2_TRUE@misc_a_libadd = \ @HAS_avrxmega2_TRUE@ $(eeprom_asm_objlist) @HAS_avrxmega2_TRUE@stdio_a_c_sources = \ @HAS_avrxmega2_TRUE@ clearerr.c \ @HAS_avrxmega2_TRUE@ fclose.c \ @HAS_avrxmega2_TRUE@ fdevopen.c \ @HAS_avrxmega2_TRUE@ feof.c \ @HAS_avrxmega2_TRUE@ ferror.c \ @HAS_avrxmega2_TRUE@ fgetc.c \ @HAS_avrxmega2_TRUE@ fgets.c \ @HAS_avrxmega2_TRUE@ fprintf.c \ @HAS_avrxmega2_TRUE@ fprintf_p.c \ @HAS_avrxmega2_TRUE@ fputc.c \ @HAS_avrxmega2_TRUE@ fputs.c \ @HAS_avrxmega2_TRUE@ fputs_p.c \ @HAS_avrxmega2_TRUE@ fread.c \ @HAS_avrxmega2_TRUE@ fscanf.c \ @HAS_avrxmega2_TRUE@ fscanf_p.c \ @HAS_avrxmega2_TRUE@ fwrite.c \ @HAS_avrxmega2_TRUE@ getchar.c \ @HAS_avrxmega2_TRUE@ gets.c \ @HAS_avrxmega2_TRUE@ iob.c \ @HAS_avrxmega2_TRUE@ printf.c \ @HAS_avrxmega2_TRUE@ printf_p.c \ @HAS_avrxmega2_TRUE@ putchar.c \ @HAS_avrxmega2_TRUE@ puts.c \ @HAS_avrxmega2_TRUE@ puts_p.c \ @HAS_avrxmega2_TRUE@ scanf.c \ @HAS_avrxmega2_TRUE@ scanf_p.c \ @HAS_avrxmega2_TRUE@ snprintf.c \ @HAS_avrxmega2_TRUE@ snprintf_p.c \ @HAS_avrxmega2_TRUE@ sprintf.c \ @HAS_avrxmega2_TRUE@ sprintf_p.c \ @HAS_avrxmega2_TRUE@ sscanf.c \ @HAS_avrxmega2_TRUE@ sscanf_p.c \ @HAS_avrxmega2_TRUE@ vfprintf_p.c \ @HAS_avrxmega2_TRUE@ vfscanf_p.c \ @HAS_avrxmega2_TRUE@ vprintf.c \ @HAS_avrxmega2_TRUE@ vscanf.c \ @HAS_avrxmega2_TRUE@ vsnprintf.c \ @HAS_avrxmega2_TRUE@ vsnprintf_p.c \ @HAS_avrxmega2_TRUE@ vsprintf.c \ @HAS_avrxmega2_TRUE@ vsprintf_p.c \ @HAS_avrxmega2_TRUE@ ungetc.c @HAS_avrxmega2_TRUE@stdio_a_asm_sources = \ @HAS_avrxmega2_TRUE@ getc.S \ @HAS_avrxmega2_TRUE@ putc.S \ @HAS_avrxmega2_TRUE@ ultoa_invert.S @HAS_avrxmega2_TRUE@stdio_a_extra_dist = \ @HAS_avrxmega2_TRUE@ vfprintf.c \ @HAS_avrxmega2_TRUE@ vfscanf.c \ @HAS_avrxmega2_TRUE@ stdio_private.h \ @HAS_avrxmega2_TRUE@ xtoa_fast.h @HAS_avrxmega2_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avrxmega2_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avrxmega2_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avrxmega2_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avrxmega2_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avrxmega2_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avrxmega2_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avrxmega2_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avrxmega2_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avrxmega2_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avrxmega2_TRUE@libm_a_c_sources = @HAS_avrxmega2_TRUE@libm_a_asm_sources = \ @HAS_avrxmega2_TRUE@ acos.S \ @HAS_avrxmega2_TRUE@ addsf3.S \ @HAS_avrxmega2_TRUE@ addsf3x.S \ @HAS_avrxmega2_TRUE@ asin.S \ @HAS_avrxmega2_TRUE@ atan2.S \ @HAS_avrxmega2_TRUE@ atan.S \ @HAS_avrxmega2_TRUE@ cbrt.S \ @HAS_avrxmega2_TRUE@ ceil.S \ @HAS_avrxmega2_TRUE@ cmpsf2.S \ @HAS_avrxmega2_TRUE@ copysign.S \ @HAS_avrxmega2_TRUE@ cosh.S \ @HAS_avrxmega2_TRUE@ cos.S \ @HAS_avrxmega2_TRUE@ divsf3.S \ @HAS_avrxmega2_TRUE@ divsf3x.S \ @HAS_avrxmega2_TRUE@ exp.S \ @HAS_avrxmega2_TRUE@ fixsfdi.S \ @HAS_avrxmega2_TRUE@ fixsfsi.S \ @HAS_avrxmega2_TRUE@ fixunssfsi.S \ @HAS_avrxmega2_TRUE@ floatdisf.S \ @HAS_avrxmega2_TRUE@ floatsisf.S \ @HAS_avrxmega2_TRUE@ floatundisf.S \ @HAS_avrxmega2_TRUE@ fdim.S \ @HAS_avrxmega2_TRUE@ floor.S \ @HAS_avrxmega2_TRUE@ fma.S \ @HAS_avrxmega2_TRUE@ fmax.S \ @HAS_avrxmega2_TRUE@ fmin.S \ @HAS_avrxmega2_TRUE@ fmod.S \ @HAS_avrxmega2_TRUE@ fp_arccos.S \ @HAS_avrxmega2_TRUE@ fp_cmp.S \ @HAS_avrxmega2_TRUE@ fp_inf.S \ @HAS_avrxmega2_TRUE@ fp_mintl.S \ @HAS_avrxmega2_TRUE@ fp_mpack.S \ @HAS_avrxmega2_TRUE@ fp_nan.S \ @HAS_avrxmega2_TRUE@ fp_negdi.S \ @HAS_avrxmega2_TRUE@ fp_norm2.S \ @HAS_avrxmega2_TRUE@ fp_powser.S \ @HAS_avrxmega2_TRUE@ fp_powsodd.S \ @HAS_avrxmega2_TRUE@ fp_pscA.S \ @HAS_avrxmega2_TRUE@ fp_pscB.S \ @HAS_avrxmega2_TRUE@ fp_rempio2.S \ @HAS_avrxmega2_TRUE@ fp_round.S \ @HAS_avrxmega2_TRUE@ fp_sinus.S \ @HAS_avrxmega2_TRUE@ fp_split3.S \ @HAS_avrxmega2_TRUE@ fp_trunc.S \ @HAS_avrxmega2_TRUE@ fp_zero.S \ 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following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1961 2009-05-24 06:10:27Z dmix $ # pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : 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strlcat_P.S \ @HAS_avr25_TRUE@ strlcpy_P.S \ @HAS_avr25_TRUE@ strlen_P.S \ @HAS_avr25_TRUE@ strncasecmp_P.S \ @HAS_avr25_TRUE@ strncat_P.S \ @HAS_avr25_TRUE@ strncmp_P.S \ @HAS_avr25_TRUE@ strncpy_P.S \ @HAS_avr25_TRUE@ strnlen_P.S \ @HAS_avr25_TRUE@ strpbrk_P.S \ @HAS_avr25_TRUE@ strrchr_P.S \ @HAS_avr25_TRUE@ strsep_P.S \ @HAS_avr25_TRUE@ strspn_P.S \ @HAS_avr25_TRUE@ strstr_P.S \ @HAS_avr25_TRUE@ strtok_rP.S \ @HAS_avr25_TRUE@ memcpy_PF.S \ @HAS_avr25_TRUE@ strcasecmp_PF.S \ @HAS_avr25_TRUE@ strcat_PF.S \ @HAS_avr25_TRUE@ strcmp_PF.S \ @HAS_avr25_TRUE@ strcpy_PF.S \ @HAS_avr25_TRUE@ strlcat_PF.S \ @HAS_avr25_TRUE@ strlcpy_PF.S \ @HAS_avr25_TRUE@ strlen_PF.S \ @HAS_avr25_TRUE@ strncasecmp_PF.S \ @HAS_avr25_TRUE@ strncat_PF.S \ @HAS_avr25_TRUE@ strncmp_PF.S \ @HAS_avr25_TRUE@ strncpy_PF.S \ @HAS_avr25_TRUE@ strnlen_PF.S \ @HAS_avr25_TRUE@ strstr_PF.S \ @HAS_avr25_TRUE@ memcmp_PF.S @HAS_avr25_TRUE@string_a_c_sources = \ @HAS_avr25_TRUE@ strdup.c \ @HAS_avr25_TRUE@ strtok.c @HAS_avr25_TRUE@string_a_asm_sources = \ @HAS_avr25_TRUE@ ffs.S \ @HAS_avr25_TRUE@ ffsl.S \ @HAS_avr25_TRUE@ ffsll.S \ @HAS_avr25_TRUE@ memccpy.S \ @HAS_avr25_TRUE@ memchr.S \ @HAS_avr25_TRUE@ memcmp.S \ @HAS_avr25_TRUE@ memcpy.S \ @HAS_avr25_TRUE@ memmem.S \ @HAS_avr25_TRUE@ memmem_P.S \ @HAS_avr25_TRUE@ memmove.S \ @HAS_avr25_TRUE@ memrchr.S \ @HAS_avr25_TRUE@ memset.S \ @HAS_avr25_TRUE@ strcasecmp.S \ @HAS_avr25_TRUE@ strcasestr.S \ @HAS_avr25_TRUE@ strcasestr_P.S \ @HAS_avr25_TRUE@ strcat.S \ @HAS_avr25_TRUE@ strchr.S \ @HAS_avr25_TRUE@ strchrnul.S \ @HAS_avr25_TRUE@ strcmp.S \ @HAS_avr25_TRUE@ strcpy.S \ @HAS_avr25_TRUE@ strcspn.S \ @HAS_avr25_TRUE@ strlcat.S \ @HAS_avr25_TRUE@ strlcpy.S \ @HAS_avr25_TRUE@ strlen.S \ @HAS_avr25_TRUE@ strlwr.S \ @HAS_avr25_TRUE@ strncasecmp.S \ @HAS_avr25_TRUE@ strncat.S \ @HAS_avr25_TRUE@ strncmp.S \ @HAS_avr25_TRUE@ strncpy.S \ @HAS_avr25_TRUE@ strnlen.S \ @HAS_avr25_TRUE@ strpbrk.S \ @HAS_avr25_TRUE@ strrchr.S \ @HAS_avr25_TRUE@ strrev.S \ @HAS_avr25_TRUE@ strsep.S \ @HAS_avr25_TRUE@ strspn.S \ @HAS_avr25_TRUE@ strstr.S \ @HAS_avr25_TRUE@ strtok_r.S \ @HAS_avr25_TRUE@ strupr.S @HAS_avr25_TRUE@string_a_extra_dist = \ @HAS_avr25_TRUE@ strlcat.c \ @HAS_avr25_TRUE@ strlcpy.c @HAS_avr25_TRUE@misc_a_c_sources = @HAS_avr25_TRUE@eeprom_asm_sources = \ @HAS_avr25_TRUE@ eerd_block.S \ @HAS_avr25_TRUE@ eerd_byte.S \ @HAS_avr25_TRUE@ eerd_dword.S \ @HAS_avr25_TRUE@ eerd_word.S \ @HAS_avr25_TRUE@ eeupd_block.S \ @HAS_avr25_TRUE@ eeupd_byte.S \ @HAS_avr25_TRUE@ eeupd_dword.S \ @HAS_avr25_TRUE@ eeupd_word.S \ @HAS_avr25_TRUE@ eewr_block.S \ @HAS_avr25_TRUE@ eewr_byte.S \ @HAS_avr25_TRUE@ eewr_dword.S \ @HAS_avr25_TRUE@ eewr_word.S @HAS_avr25_TRUE@misc_a_asm_sources = \ @HAS_avr25_TRUE@ itoa.S \ @HAS_avr25_TRUE@ ltoa.S \ @HAS_avr25_TRUE@ mulsi10.S \ @HAS_avr25_TRUE@ mul10.S \ @HAS_avr25_TRUE@ ultoa.S \ @HAS_avr25_TRUE@ utoa.S @HAS_avr25_TRUE@misc_a_extra_dist = \ @HAS_avr25_TRUE@ eedef.h \ @HAS_avr25_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avr25_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avr25_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avr25_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avr25_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avr25_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avr25_TRUE@misc_a_libadd = \ @HAS_avr25_TRUE@ $(eeprom_asm_objlist) @HAS_avr25_TRUE@stdio_a_c_sources = \ @HAS_avr25_TRUE@ clearerr.c \ @HAS_avr25_TRUE@ fclose.c \ @HAS_avr25_TRUE@ fdevopen.c \ @HAS_avr25_TRUE@ feof.c \ @HAS_avr25_TRUE@ ferror.c \ @HAS_avr25_TRUE@ fgetc.c \ @HAS_avr25_TRUE@ fgets.c \ @HAS_avr25_TRUE@ fprintf.c \ @HAS_avr25_TRUE@ fprintf_p.c \ @HAS_avr25_TRUE@ fputc.c \ @HAS_avr25_TRUE@ fputs.c \ @HAS_avr25_TRUE@ fputs_p.c \ @HAS_avr25_TRUE@ fread.c \ @HAS_avr25_TRUE@ fscanf.c \ @HAS_avr25_TRUE@ fscanf_p.c \ @HAS_avr25_TRUE@ fwrite.c \ @HAS_avr25_TRUE@ getchar.c \ @HAS_avr25_TRUE@ gets.c \ @HAS_avr25_TRUE@ iob.c \ @HAS_avr25_TRUE@ printf.c \ @HAS_avr25_TRUE@ printf_p.c \ @HAS_avr25_TRUE@ putchar.c \ @HAS_avr25_TRUE@ puts.c \ @HAS_avr25_TRUE@ puts_p.c \ @HAS_avr25_TRUE@ scanf.c \ @HAS_avr25_TRUE@ scanf_p.c \ @HAS_avr25_TRUE@ snprintf.c \ @HAS_avr25_TRUE@ snprintf_p.c \ @HAS_avr25_TRUE@ sprintf.c \ @HAS_avr25_TRUE@ sprintf_p.c \ @HAS_avr25_TRUE@ sscanf.c \ @HAS_avr25_TRUE@ sscanf_p.c \ @HAS_avr25_TRUE@ vfprintf_p.c \ @HAS_avr25_TRUE@ vfscanf_p.c \ @HAS_avr25_TRUE@ vprintf.c \ @HAS_avr25_TRUE@ vscanf.c \ @HAS_avr25_TRUE@ vsnprintf.c \ @HAS_avr25_TRUE@ vsnprintf_p.c \ @HAS_avr25_TRUE@ vsprintf.c \ @HAS_avr25_TRUE@ vsprintf_p.c \ @HAS_avr25_TRUE@ ungetc.c @HAS_avr25_TRUE@stdio_a_asm_sources = \ @HAS_avr25_TRUE@ getc.S \ @HAS_avr25_TRUE@ putc.S \ @HAS_avr25_TRUE@ ultoa_invert.S @HAS_avr25_TRUE@stdio_a_extra_dist = \ @HAS_avr25_TRUE@ vfprintf.c \ @HAS_avr25_TRUE@ vfscanf.c \ @HAS_avr25_TRUE@ stdio_private.h \ @HAS_avr25_TRUE@ xtoa_fast.h @HAS_avr25_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avr25_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avr25_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avr25_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avr25_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avr25_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avr25_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avr25_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avr25_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avr25_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avr25_TRUE@libm_a_c_sources = @HAS_avr25_TRUE@libm_a_asm_sources = \ @HAS_avr25_TRUE@ acos.S \ @HAS_avr25_TRUE@ addsf3.S \ @HAS_avr25_TRUE@ addsf3x.S \ @HAS_avr25_TRUE@ asin.S \ @HAS_avr25_TRUE@ atan2.S \ @HAS_avr25_TRUE@ atan.S \ @HAS_avr25_TRUE@ cbrt.S \ @HAS_avr25_TRUE@ ceil.S \ @HAS_avr25_TRUE@ cmpsf2.S \ @HAS_avr25_TRUE@ copysign.S \ @HAS_avr25_TRUE@ cosh.S \ @HAS_avr25_TRUE@ cos.S \ @HAS_avr25_TRUE@ divsf3.S \ @HAS_avr25_TRUE@ divsf3x.S \ @HAS_avr25_TRUE@ exp.S \ @HAS_avr25_TRUE@ fixsfdi.S \ @HAS_avr25_TRUE@ fixsfsi.S \ @HAS_avr25_TRUE@ fixunssfsi.S \ @HAS_avr25_TRUE@ floatdisf.S \ @HAS_avr25_TRUE@ floatsisf.S \ @HAS_avr25_TRUE@ floatundisf.S \ @HAS_avr25_TRUE@ fdim.S \ @HAS_avr25_TRUE@ floor.S \ @HAS_avr25_TRUE@ fma.S \ @HAS_avr25_TRUE@ fmax.S \ @HAS_avr25_TRUE@ fmin.S \ @HAS_avr25_TRUE@ fmod.S \ @HAS_avr25_TRUE@ fp_arccos.S \ @HAS_avr25_TRUE@ fp_cmp.S \ @HAS_avr25_TRUE@ fp_inf.S \ @HAS_avr25_TRUE@ fp_mintl.S \ @HAS_avr25_TRUE@ fp_mpack.S \ @HAS_avr25_TRUE@ fp_nan.S \ @HAS_avr25_TRUE@ fp_negdi.S \ @HAS_avr25_TRUE@ fp_norm2.S \ @HAS_avr25_TRUE@ fp_powser.S \ @HAS_avr25_TRUE@ fp_powsodd.S \ @HAS_avr25_TRUE@ fp_pscA.S \ @HAS_avr25_TRUE@ fp_pscB.S \ @HAS_avr25_TRUE@ fp_rempio2.S \ @HAS_avr25_TRUE@ fp_round.S \ @HAS_avr25_TRUE@ fp_sinus.S \ @HAS_avr25_TRUE@ fp_split3.S \ @HAS_avr25_TRUE@ fp_trunc.S \ @HAS_avr25_TRUE@ fp_zero.S \ @HAS_avr25_TRUE@ frexp.S \ @HAS_avr25_TRUE@ gesf2.S \ @HAS_avr25_TRUE@ hypot.S \ @HAS_avr25_TRUE@ inverse.S \ @HAS_avr25_TRUE@ isfinite.S \ @HAS_avr25_TRUE@ isinf.S \ @HAS_avr25_TRUE@ isnan.S \ @HAS_avr25_TRUE@ ldexp.S \ @HAS_avr25_TRUE@ log10.S \ @HAS_avr25_TRUE@ log.S \ @HAS_avr25_TRUE@ lrint.S \ @HAS_avr25_TRUE@ lround.S \ @HAS_avr25_TRUE@ modf.S \ @HAS_avr25_TRUE@ mulsf3.S \ @HAS_avr25_TRUE@ mulsf3x.S \ @HAS_avr25_TRUE@ negsf2.S \ @HAS_avr25_TRUE@ pow.S \ @HAS_avr25_TRUE@ round.S \ @HAS_avr25_TRUE@ signbit.S \ @HAS_avr25_TRUE@ sinh.S \ @HAS_avr25_TRUE@ sin.S \ @HAS_avr25_TRUE@ sqrt.S \ @HAS_avr25_TRUE@ square.S \ @HAS_avr25_TRUE@ tanh.S \ @HAS_avr25_TRUE@ tan.S \ @HAS_avr25_TRUE@ trunc.S \ @HAS_avr25_TRUE@ unordsf2.S @HAS_avr25_TRUE@libm_a_extra_dist = \ @HAS_avr25_TRUE@ asmdef.h \ @HAS_avr25_TRUE@ fp32def.h \ @HAS_avr25_TRUE@ ntz.h @HAS_avr25_TRUE@nodist_libc_a_SOURCES = \ @HAS_avr25_TRUE@ $(stdlib_a_c_sources) \ @HAS_avr25_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avr25_TRUE@ $(pmstring_a_c_sources) \ @HAS_avr25_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avr25_TRUE@ $(string_a_c_sources) \ @HAS_avr25_TRUE@ $(string_a_asm_sources) \ @HAS_avr25_TRUE@ $(misc_a_c_sources) \ @HAS_avr25_TRUE@ $(misc_a_asm_sources) \ @HAS_avr25_TRUE@ $(stdio_a_c_sources) \ @HAS_avr25_TRUE@ $(stdio_a_asm_sources) \ @HAS_avr25_TRUE@ $(libm_a_c_sources) \ @HAS_avr25_TRUE@ $(libm_a_asm_sources) @HAS_avr25_TRUE@nodist_libm_a_SOURCES = \ @HAS_avr25_TRUE@ $(libm_a_c_sources) \ @HAS_avr25_TRUE@ $(libm_a_asm_sources) @HAS_avr25_TRUE@libc_a_LIBADD = \ @HAS_avr25_TRUE@ $(stdio_a_libadd) \ @HAS_avr25_TRUE@ $(misc_a_libadd) @HAS_avr25_TRUE@libc_a_DEPENDENCIES = \ @HAS_avr25_TRUE@ $(stdio_a_libadd) \ @HAS_avr25_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am $(top_srcdir)/libc/misc/Rules.am $(top_srcdir)/libc/misc/Files.am $(top_srcdir)/libc/stdio/Rules.am $(top_srcdir)/libc/stdio/Files.am $(top_srcdir)/libm/fplib/Rules.am $(top_srcdir)/libm/fplib/Files.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign avr/lib/avr25/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign avr/lib/avr25/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): install-avrLIBRARIES: $(avr_LIBRARIES) @$(NORMAL_INSTALL) test -z "$(avrdir)" || $(MKDIR_P) "$(DESTDIR)$(avrdir)" @list='$(avr_LIBRARIES)'; test -n "$(avrdir)" || list=; \ list2=; for p in $$list; do \ if test -f $$p; then \ list2="$$list2 $$p"; \ else :; fi; \ done; \ test -z "$$list2" || { \ echo " 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$(libm_a_LIBADD) $(RANLIB) libm.a libprintf_flt.a: $(libprintf_flt_a_OBJECTS) $(libprintf_flt_a_DEPENDENCIES) -rm -f libprintf_flt.a $(libprintf_flt_a_AR) libprintf_flt.a $(libprintf_flt_a_OBJECTS) $(libprintf_flt_a_LIBADD) $(RANLIB) libprintf_flt.a libprintf_min.a: $(libprintf_min_a_OBJECTS) $(libprintf_min_a_DEPENDENCIES) -rm -f libprintf_min.a $(libprintf_min_a_AR) libprintf_min.a $(libprintf_min_a_OBJECTS) $(libprintf_min_a_LIBADD) $(RANLIB) libprintf_min.a libscanf_flt.a: $(libscanf_flt_a_OBJECTS) $(libscanf_flt_a_DEPENDENCIES) -rm -f libscanf_flt.a $(libscanf_flt_a_AR) libscanf_flt.a $(libscanf_flt_a_OBJECTS) $(libscanf_flt_a_LIBADD) $(RANLIB) libscanf_flt.a libscanf_min.a: $(libscanf_min_a_OBJECTS) $(libscanf_min_a_DEPENDENCIES) -rm -f libscanf_min.a $(libscanf_min_a_AR) libscanf_min.a $(libscanf_min_a_OBJECTS) $(libscanf_min_a_LIBADD) $(RANLIB) libscanf_min.a mostlyclean-compile: -rm -f *.$(OBJEXT) distclean-compile: -rm -f *.tab.c @AMDEP_TRUE@@am__include@ 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provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 2164 2010-06-13 12:34:24Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1743 2008-08-20 15:27:33Z arcanum $ # # Copyright (c) 2002, Reinhard Jessich # Copyright (c) 2009 Dmitry Xmelkov # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 1977 2009-06-05 23:05:35Z dmix $ # Copyright (c) 2004,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1976 2009-06-05 23:04:34Z dmix $ # # Copyright (c) 2002, 2003, 2004, 2009 Joerg Wunsch # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Rules.am 1872 2009-02-08 22:55:13Z aesok $ # # Copyright (c) 2004,2005 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Files.am 1381 2007-05-14 13:52:01Z joerg_wunsch $ # # Copyright (c) 2002, Reinhard Jessich # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # $Id: Rules.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # Copyright (c) 2004,2008,2009 Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # * Neither the name of the copyright holders nor the names of # contributors may be used to endorse or promote products derived # from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. 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@htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ SUBDIRS = atmega103 at43usb320 AVR_TARGET = avr31 AVR_TARGET_DEFS = -D__COMPILING_AVR_LIBC__ AVR_TARGET_CFLAGS = -mcall-prologues -Os AVR_TARGET_ASFLAGS = AVR_INSTALL_DIR = avr31 @HAS_avr31_TRUE@AVRLIB_DEVLIST = $(am__append_1) $(am__append_2) @HAS_avr31_TRUE@AM_CPPFLAGS = -I$(top_srcdir)/common -I$(top_srcdir)/include -I$(top_builddir)/include @HAS_avr31_TRUE@AVRLIB_CFLAGS = -g -Wall -W -Wstrict-prototypes -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_CFLAGS) @HAS_avr31_TRUE@AVRLIB_ASFLAGS = -x assembler-with-cpp -Wa,-gstabs -mmcu=$(AVR_TARGET) $(AVR_TARGET_DEFS) $(AVR_TARGET_ASFLAGS) @HAS_avr31_TRUE@AM_CFLAGS = $(AVRLIB_CFLAGS) @HAS_avr31_TRUE@AM_CCASFLAGS = $(AM_CPPFLAGS) $(AVRLIB_ASFLAGS) @HAS_avr31_TRUE@__install_dir = $(prefix)/avr/lib/$(AVR_INSTALL_DIR) @HAS_avr31_TRUE@avrdir = $(__install_dir) @HAS_avr31_TRUE@avrlibdir = $(__install_dir) @HAS_avr31_TRUE@avr_LIBRARIES = \ @HAS_avr31_TRUE@ libc.a \ @HAS_avr31_TRUE@ libprintf_min.a \ @HAS_avr31_TRUE@ libprintf_flt.a \ @HAS_avr31_TRUE@ libscanf_min.a \ @HAS_avr31_TRUE@ libscanf_flt.a \ @HAS_avr31_TRUE@ libm.a @HAS_avr31_TRUE@stdlib_a_c_sources = \ @HAS_avr31_TRUE@ abs.c \ @HAS_avr31_TRUE@ assert.c \ @HAS_avr31_TRUE@ bsearch.c \ @HAS_avr31_TRUE@ calloc.c \ @HAS_avr31_TRUE@ errno.c \ @HAS_avr31_TRUE@ dtoa_prf.c \ @HAS_avr31_TRUE@ dtostre.c \ @HAS_avr31_TRUE@ dtostrf.c \ @HAS_avr31_TRUE@ labs.c \ @HAS_avr31_TRUE@ malloc.c \ @HAS_avr31_TRUE@ qsort.c \ @HAS_avr31_TRUE@ rand.c \ @HAS_avr31_TRUE@ random.c \ @HAS_avr31_TRUE@ realloc.c \ @HAS_avr31_TRUE@ strtod.c \ @HAS_avr31_TRUE@ strtol.c \ @HAS_avr31_TRUE@ strtoul.c \ @HAS_avr31_TRUE@ dtoa_conv.h \ @HAS_avr31_TRUE@ stdlib_private.h @HAS_avr31_TRUE@stdlib_a_asm_sources = \ @HAS_avr31_TRUE@ abort.S \ @HAS_avr31_TRUE@ atof.S \ @HAS_avr31_TRUE@ atoi.S \ @HAS_avr31_TRUE@ atol.S \ @HAS_avr31_TRUE@ div.S \ @HAS_avr31_TRUE@ exit.S \ @HAS_avr31_TRUE@ ftoa_engine.S \ @HAS_avr31_TRUE@ ldiv.S \ @HAS_avr31_TRUE@ setjmp.S \ @HAS_avr31_TRUE@ isascii.S \ @HAS_avr31_TRUE@ toascii.S \ @HAS_avr31_TRUE@ isalnum.S \ @HAS_avr31_TRUE@ cty_isfalse.S \ @HAS_avr31_TRUE@ isalpha.S \ @HAS_avr31_TRUE@ isdigit.S \ @HAS_avr31_TRUE@ isxdigit.S \ @HAS_avr31_TRUE@ iscntrl.S \ @HAS_avr31_TRUE@ isprint.S \ @HAS_avr31_TRUE@ isspace.S \ @HAS_avr31_TRUE@ isblank.S \ @HAS_avr31_TRUE@ ispunct.S \ @HAS_avr31_TRUE@ tolower.S \ @HAS_avr31_TRUE@ toupper.S @HAS_avr31_TRUE@stdlib_a_extra_dist = \ @HAS_avr31_TRUE@ ctype.S \ @HAS_avr31_TRUE@ abort.c \ @HAS_avr31_TRUE@ atoi.c \ @HAS_avr31_TRUE@ atol.c @HAS_avr31_TRUE@pmstring_a_c_sources = \ @HAS_avr31_TRUE@ strtok_P.c @HAS_avr31_TRUE@pmstring_a_asm_sources = \ @HAS_avr31_TRUE@ memchr_P.S \ @HAS_avr31_TRUE@ memcmp_P.S \ @HAS_avr31_TRUE@ memccpy_P.S \ @HAS_avr31_TRUE@ memcpy_P.S \ @HAS_avr31_TRUE@ memrchr_P.S \ @HAS_avr31_TRUE@ strcasecmp_P.S \ @HAS_avr31_TRUE@ strcat_P.S \ @HAS_avr31_TRUE@ strchr_P.S \ @HAS_avr31_TRUE@ strchrnul_P.S \ @HAS_avr31_TRUE@ strcmp_P.S \ @HAS_avr31_TRUE@ strcpy_P.S \ @HAS_avr31_TRUE@ strcspn_P.S \ @HAS_avr31_TRUE@ strlcat_P.S \ @HAS_avr31_TRUE@ strlcpy_P.S \ @HAS_avr31_TRUE@ strlen_P.S \ @HAS_avr31_TRUE@ strncasecmp_P.S \ @HAS_avr31_TRUE@ strncat_P.S \ @HAS_avr31_TRUE@ strncmp_P.S \ @HAS_avr31_TRUE@ strncpy_P.S \ @HAS_avr31_TRUE@ strnlen_P.S \ @HAS_avr31_TRUE@ strpbrk_P.S \ @HAS_avr31_TRUE@ strrchr_P.S \ @HAS_avr31_TRUE@ strsep_P.S \ @HAS_avr31_TRUE@ strspn_P.S \ @HAS_avr31_TRUE@ strstr_P.S \ @HAS_avr31_TRUE@ strtok_rP.S \ @HAS_avr31_TRUE@ memcpy_PF.S \ @HAS_avr31_TRUE@ strcasecmp_PF.S \ @HAS_avr31_TRUE@ strcat_PF.S \ @HAS_avr31_TRUE@ strcmp_PF.S \ @HAS_avr31_TRUE@ strcpy_PF.S \ @HAS_avr31_TRUE@ strlcat_PF.S \ @HAS_avr31_TRUE@ strlcpy_PF.S \ @HAS_avr31_TRUE@ strlen_PF.S \ @HAS_avr31_TRUE@ strncasecmp_PF.S \ @HAS_avr31_TRUE@ strncat_PF.S \ @HAS_avr31_TRUE@ strncmp_PF.S \ @HAS_avr31_TRUE@ strncpy_PF.S \ @HAS_avr31_TRUE@ strnlen_PF.S \ @HAS_avr31_TRUE@ strstr_PF.S \ @HAS_avr31_TRUE@ memcmp_PF.S @HAS_avr31_TRUE@string_a_c_sources = \ @HAS_avr31_TRUE@ strdup.c \ @HAS_avr31_TRUE@ strtok.c @HAS_avr31_TRUE@string_a_asm_sources = \ @HAS_avr31_TRUE@ ffs.S \ @HAS_avr31_TRUE@ ffsl.S \ @HAS_avr31_TRUE@ ffsll.S \ @HAS_avr31_TRUE@ memccpy.S \ @HAS_avr31_TRUE@ memchr.S \ @HAS_avr31_TRUE@ memcmp.S \ @HAS_avr31_TRUE@ memcpy.S \ @HAS_avr31_TRUE@ memmem.S \ @HAS_avr31_TRUE@ memmem_P.S \ @HAS_avr31_TRUE@ memmove.S \ @HAS_avr31_TRUE@ memrchr.S \ @HAS_avr31_TRUE@ memset.S \ @HAS_avr31_TRUE@ strcasecmp.S \ @HAS_avr31_TRUE@ strcasestr.S \ @HAS_avr31_TRUE@ strcasestr_P.S \ @HAS_avr31_TRUE@ strcat.S \ @HAS_avr31_TRUE@ strchr.S \ @HAS_avr31_TRUE@ strchrnul.S \ @HAS_avr31_TRUE@ strcmp.S \ @HAS_avr31_TRUE@ strcpy.S \ @HAS_avr31_TRUE@ strcspn.S \ @HAS_avr31_TRUE@ strlcat.S \ @HAS_avr31_TRUE@ strlcpy.S \ @HAS_avr31_TRUE@ strlen.S \ @HAS_avr31_TRUE@ strlwr.S \ @HAS_avr31_TRUE@ strncasecmp.S \ @HAS_avr31_TRUE@ strncat.S \ @HAS_avr31_TRUE@ strncmp.S \ @HAS_avr31_TRUE@ strncpy.S \ @HAS_avr31_TRUE@ strnlen.S \ @HAS_avr31_TRUE@ strpbrk.S \ @HAS_avr31_TRUE@ strrchr.S \ @HAS_avr31_TRUE@ strrev.S \ @HAS_avr31_TRUE@ strsep.S \ @HAS_avr31_TRUE@ strspn.S \ @HAS_avr31_TRUE@ strstr.S \ @HAS_avr31_TRUE@ strtok_r.S \ @HAS_avr31_TRUE@ strupr.S @HAS_avr31_TRUE@string_a_extra_dist = \ @HAS_avr31_TRUE@ strlcat.c \ @HAS_avr31_TRUE@ strlcpy.c @HAS_avr31_TRUE@misc_a_c_sources = @HAS_avr31_TRUE@eeprom_asm_sources = \ @HAS_avr31_TRUE@ eerd_block.S \ @HAS_avr31_TRUE@ eerd_byte.S \ @HAS_avr31_TRUE@ eerd_dword.S \ @HAS_avr31_TRUE@ eerd_word.S \ @HAS_avr31_TRUE@ eeupd_block.S \ @HAS_avr31_TRUE@ eeupd_byte.S \ @HAS_avr31_TRUE@ eeupd_dword.S \ @HAS_avr31_TRUE@ eeupd_word.S \ @HAS_avr31_TRUE@ eewr_block.S \ @HAS_avr31_TRUE@ eewr_byte.S \ @HAS_avr31_TRUE@ eewr_dword.S \ @HAS_avr31_TRUE@ eewr_word.S @HAS_avr31_TRUE@misc_a_asm_sources = \ @HAS_avr31_TRUE@ itoa.S \ @HAS_avr31_TRUE@ ltoa.S \ @HAS_avr31_TRUE@ mulsi10.S \ @HAS_avr31_TRUE@ mul10.S \ @HAS_avr31_TRUE@ ultoa.S \ @HAS_avr31_TRUE@ utoa.S @HAS_avr31_TRUE@misc_a_extra_dist = \ @HAS_avr31_TRUE@ eedef.h \ @HAS_avr31_TRUE@ readme_eeprom.txt # Example: # eeprom_asm_sources --> eerd_byte.S eerd_word.S # basename --> eerd_byte eerd_word # addsuffix --> eerd_byte_ eerd_word_ # foreach --> eerd_byte_atmega48 eerd_byte_atmega8 # eerd_word_atmega48 eerd_word_atmega8 # addsuffix --> eerd_byte_atmega48.o eerd_byte_atmega8.o # eerd_word_atmega48.o eerd_word_atmega8.o # @HAS_avr31_TRUE@eeprom_asm_basenames = $(basename $(eeprom_asm_sources)) @HAS_avr31_TRUE@eeprom_asm_basenames2 = $(addsuffix _,$(eeprom_asm_basenames)) @HAS_avr31_TRUE@eeprom_asm_baselist = $(foreach dev,$(AVRLIB_DEVLIST),\ @HAS_avr31_TRUE@ $(addsuffix $(dev),$(eeprom_asm_basenames2))) @HAS_avr31_TRUE@eeprom_asm_objlist = $(addsuffix .o,$(eeprom_asm_baselist)) @HAS_avr31_TRUE@misc_a_libadd = \ @HAS_avr31_TRUE@ $(eeprom_asm_objlist) @HAS_avr31_TRUE@stdio_a_c_sources = \ @HAS_avr31_TRUE@ clearerr.c \ @HAS_avr31_TRUE@ fclose.c \ @HAS_avr31_TRUE@ fdevopen.c \ @HAS_avr31_TRUE@ feof.c \ @HAS_avr31_TRUE@ ferror.c \ @HAS_avr31_TRUE@ fgetc.c \ @HAS_avr31_TRUE@ fgets.c \ @HAS_avr31_TRUE@ fprintf.c \ @HAS_avr31_TRUE@ fprintf_p.c \ @HAS_avr31_TRUE@ fputc.c \ @HAS_avr31_TRUE@ fputs.c \ @HAS_avr31_TRUE@ fputs_p.c \ @HAS_avr31_TRUE@ fread.c \ @HAS_avr31_TRUE@ fscanf.c \ @HAS_avr31_TRUE@ fscanf_p.c \ @HAS_avr31_TRUE@ fwrite.c \ @HAS_avr31_TRUE@ getchar.c \ @HAS_avr31_TRUE@ gets.c \ @HAS_avr31_TRUE@ iob.c \ @HAS_avr31_TRUE@ printf.c \ @HAS_avr31_TRUE@ printf_p.c \ @HAS_avr31_TRUE@ putchar.c \ @HAS_avr31_TRUE@ puts.c \ @HAS_avr31_TRUE@ puts_p.c \ @HAS_avr31_TRUE@ scanf.c \ @HAS_avr31_TRUE@ scanf_p.c \ @HAS_avr31_TRUE@ snprintf.c \ @HAS_avr31_TRUE@ snprintf_p.c \ @HAS_avr31_TRUE@ sprintf.c \ @HAS_avr31_TRUE@ sprintf_p.c \ @HAS_avr31_TRUE@ sscanf.c \ @HAS_avr31_TRUE@ sscanf_p.c \ @HAS_avr31_TRUE@ vfprintf_p.c \ @HAS_avr31_TRUE@ vfscanf_p.c \ @HAS_avr31_TRUE@ vprintf.c \ @HAS_avr31_TRUE@ vscanf.c \ @HAS_avr31_TRUE@ vsnprintf.c \ @HAS_avr31_TRUE@ vsnprintf_p.c \ @HAS_avr31_TRUE@ vsprintf.c \ @HAS_avr31_TRUE@ vsprintf_p.c \ @HAS_avr31_TRUE@ ungetc.c @HAS_avr31_TRUE@stdio_a_asm_sources = \ @HAS_avr31_TRUE@ getc.S \ @HAS_avr31_TRUE@ putc.S \ @HAS_avr31_TRUE@ ultoa_invert.S @HAS_avr31_TRUE@stdio_a_extra_dist = \ @HAS_avr31_TRUE@ vfprintf.c \ @HAS_avr31_TRUE@ vfscanf.c \ @HAS_avr31_TRUE@ stdio_private.h \ @HAS_avr31_TRUE@ xtoa_fast.h @HAS_avr31_TRUE@stdio_a_libadd = vfprintf_std.o vfscanf_std.o @HAS_avr31_TRUE@nodist_libprintf_min_a_SOURCES = @HAS_avr31_TRUE@libprintf_min_a_LIBADD = vfprintf_min.o @HAS_avr31_TRUE@nodist_libprintf_flt_a_SOURCES = @HAS_avr31_TRUE@libprintf_flt_a_LIBADD = vfprintf_flt.o @HAS_avr31_TRUE@nodist_libscanf_min_a_SOURCES = @HAS_avr31_TRUE@libscanf_min_a_LIBADD = vfscanf_min.o @HAS_avr31_TRUE@nodist_libscanf_flt_a_SOURCES = @HAS_avr31_TRUE@libscanf_flt_a_LIBADD = vfscanf_flt.o # vfprintf is compiled best with -Os -fno-jump-tables (-mno-tablejump), # this gives the smallest code. @HAS_avr31_TRUE@PRINTF_CFLAGS = -Os $(FNO_JUMP_TABLES) @HAS_avr31_TRUE@libm_a_c_sources = @HAS_avr31_TRUE@libm_a_asm_sources = \ @HAS_avr31_TRUE@ acos.S \ @HAS_avr31_TRUE@ addsf3.S \ @HAS_avr31_TRUE@ addsf3x.S \ @HAS_avr31_TRUE@ asin.S \ @HAS_avr31_TRUE@ atan2.S \ @HAS_avr31_TRUE@ atan.S \ @HAS_avr31_TRUE@ cbrt.S \ @HAS_avr31_TRUE@ ceil.S \ @HAS_avr31_TRUE@ cmpsf2.S \ @HAS_avr31_TRUE@ copysign.S \ @HAS_avr31_TRUE@ cosh.S \ @HAS_avr31_TRUE@ cos.S \ @HAS_avr31_TRUE@ divsf3.S \ @HAS_avr31_TRUE@ divsf3x.S \ @HAS_avr31_TRUE@ exp.S \ @HAS_avr31_TRUE@ fixsfdi.S \ @HAS_avr31_TRUE@ fixsfsi.S \ @HAS_avr31_TRUE@ fixunssfsi.S \ @HAS_avr31_TRUE@ floatdisf.S \ @HAS_avr31_TRUE@ floatsisf.S \ @HAS_avr31_TRUE@ floatundisf.S \ @HAS_avr31_TRUE@ fdim.S \ @HAS_avr31_TRUE@ floor.S \ @HAS_avr31_TRUE@ fma.S \ @HAS_avr31_TRUE@ fmax.S \ @HAS_avr31_TRUE@ fmin.S \ @HAS_avr31_TRUE@ fmod.S \ @HAS_avr31_TRUE@ fp_arccos.S \ @HAS_avr31_TRUE@ fp_cmp.S \ @HAS_avr31_TRUE@ fp_inf.S \ @HAS_avr31_TRUE@ fp_mintl.S \ @HAS_avr31_TRUE@ fp_mpack.S \ @HAS_avr31_TRUE@ fp_nan.S \ @HAS_avr31_TRUE@ fp_negdi.S \ @HAS_avr31_TRUE@ fp_norm2.S \ @HAS_avr31_TRUE@ fp_powser.S \ @HAS_avr31_TRUE@ fp_powsodd.S \ @HAS_avr31_TRUE@ fp_pscA.S \ @HAS_avr31_TRUE@ fp_pscB.S \ @HAS_avr31_TRUE@ fp_rempio2.S \ @HAS_avr31_TRUE@ fp_round.S \ @HAS_avr31_TRUE@ fp_sinus.S \ @HAS_avr31_TRUE@ fp_split3.S \ @HAS_avr31_TRUE@ fp_trunc.S \ @HAS_avr31_TRUE@ fp_zero.S \ @HAS_avr31_TRUE@ frexp.S \ @HAS_avr31_TRUE@ gesf2.S \ @HAS_avr31_TRUE@ hypot.S \ @HAS_avr31_TRUE@ inverse.S \ @HAS_avr31_TRUE@ isfinite.S \ @HAS_avr31_TRUE@ isinf.S \ @HAS_avr31_TRUE@ isnan.S \ @HAS_avr31_TRUE@ ldexp.S \ @HAS_avr31_TRUE@ log10.S \ @HAS_avr31_TRUE@ log.S \ @HAS_avr31_TRUE@ lrint.S \ @HAS_avr31_TRUE@ lround.S \ @HAS_avr31_TRUE@ modf.S \ @HAS_avr31_TRUE@ mulsf3.S \ @HAS_avr31_TRUE@ mulsf3x.S \ @HAS_avr31_TRUE@ negsf2.S \ @HAS_avr31_TRUE@ pow.S \ @HAS_avr31_TRUE@ round.S \ @HAS_avr31_TRUE@ signbit.S \ @HAS_avr31_TRUE@ sinh.S \ @HAS_avr31_TRUE@ sin.S \ @HAS_avr31_TRUE@ sqrt.S \ @HAS_avr31_TRUE@ square.S \ @HAS_avr31_TRUE@ tanh.S \ @HAS_avr31_TRUE@ tan.S \ @HAS_avr31_TRUE@ trunc.S \ @HAS_avr31_TRUE@ unordsf2.S @HAS_avr31_TRUE@libm_a_extra_dist = \ @HAS_avr31_TRUE@ asmdef.h \ @HAS_avr31_TRUE@ fp32def.h \ @HAS_avr31_TRUE@ ntz.h @HAS_avr31_TRUE@nodist_libc_a_SOURCES = \ @HAS_avr31_TRUE@ $(stdlib_a_c_sources) \ @HAS_avr31_TRUE@ $(stdlib_a_asm_sources) \ @HAS_avr31_TRUE@ $(pmstring_a_c_sources) \ @HAS_avr31_TRUE@ $(pmstring_a_asm_sources) \ @HAS_avr31_TRUE@ $(string_a_c_sources) \ @HAS_avr31_TRUE@ $(string_a_asm_sources) \ @HAS_avr31_TRUE@ $(misc_a_c_sources) \ @HAS_avr31_TRUE@ $(misc_a_asm_sources) \ @HAS_avr31_TRUE@ $(stdio_a_c_sources) \ @HAS_avr31_TRUE@ $(stdio_a_asm_sources) \ @HAS_avr31_TRUE@ $(libm_a_c_sources) \ @HAS_avr31_TRUE@ $(libm_a_asm_sources) @HAS_avr31_TRUE@nodist_libm_a_SOURCES = \ @HAS_avr31_TRUE@ $(libm_a_c_sources) \ @HAS_avr31_TRUE@ $(libm_a_asm_sources) @HAS_avr31_TRUE@libc_a_LIBADD = \ @HAS_avr31_TRUE@ $(stdio_a_libadd) \ @HAS_avr31_TRUE@ $(misc_a_libadd) @HAS_avr31_TRUE@libc_a_DEPENDENCIES = \ @HAS_avr31_TRUE@ $(stdio_a_libadd) \ @HAS_avr31_TRUE@ $(misc_a_libadd) all: all-recursive .SUFFIXES: .SUFFIXES: .S .c .o .obj $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/libc/stdlib/Rules.am $(top_srcdir)/libc/stdlib/Files.am $(top_srcdir)/libc/pmstring/Rules.am $(top_srcdir)/libc/pmstring/Files.am $(top_srcdir)/libc/string/Rules.am $(top_srcdir)/libc/string/Files.am $(top_srcdir)/libc/misc/Rules.am $(top_srcdir)/libc/misc/Files.am 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Weddington All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: gcrt1.S 2114 2010-03-31 05:12:22Z arcanum $ */ #if (__GNUC__ < 3) || (__GNUC__ == 3 && __GNUC_MINOR__ < 3) #error "GCC version >= 3.3 required" #endif #include "macros.inc" .macro vector name .if (. - __vectors < _VECTORS_SIZE) .weak \name .set \name, __bad_interrupt XJMP \name .endif .endm .section .vectors,"ax",@progbits .global __vectors .func __vectors __vectors: XJMP __init vector __vector_1 vector __vector_2 vector __vector_3 vector __vector_4 vector __vector_5 vector __vector_6 vector __vector_7 vector __vector_8 vector __vector_9 vector __vector_10 vector __vector_11 vector __vector_12 vector __vector_13 vector __vector_14 vector __vector_15 vector __vector_16 vector __vector_17 vector __vector_18 vector __vector_19 vector __vector_20 vector __vector_21 vector __vector_22 vector __vector_23 vector __vector_24 vector __vector_25 vector __vector_26 vector __vector_27 vector __vector_28 vector __vector_29 vector __vector_30 vector __vector_31 vector __vector_32 vector __vector_33 vector __vector_34 vector __vector_35 vector __vector_36 vector __vector_37 vector __vector_38 vector __vector_39 vector __vector_40 vector __vector_41 vector __vector_42 vector __vector_43 vector __vector_44 vector __vector_45 vector __vector_46 vector __vector_47 vector __vector_48 vector __vector_49 vector __vector_50 vector __vector_51 vector __vector_52 vector __vector_53 vector __vector_54 vector __vector_55 vector __vector_56 vector __vector_57 vector __vector_58 vector __vector_59 vector __vector_60 vector __vector_61 vector __vector_62 vector __vector_63 vector __vector_64 vector __vector_65 vector __vector_66 vector __vector_67 vector __vector_68 vector __vector_69 vector __vector_70 vector __vector_71 vector __vector_72 vector __vector_73 vector __vector_74 vector __vector_75 vector __vector_76 vector __vector_77 vector __vector_78 vector __vector_79 vector __vector_80 vector __vector_81 vector __vector_82 vector __vector_83 vector __vector_84 vector __vector_85 vector __vector_86 vector __vector_87 vector __vector_88 vector __vector_89 vector __vector_90 vector __vector_91 vector __vector_92 vector __vector_93 vector __vector_94 vector __vector_95 vector __vector_96 vector __vector_97 vector __vector_98 vector __vector_99 vector __vector_100 vector __vector_101 vector __vector_102 vector __vector_103 vector __vector_104 vector __vector_105 vector __vector_106 vector __vector_107 vector __vector_108 vector __vector_109 vector __vector_110 vector __vector_111 vector __vector_112 vector __vector_113 vector __vector_114 vector __vector_115 vector __vector_116 vector __vector_117 vector __vector_118 vector __vector_119 vector __vector_120 vector __vector_121 vector __vector_122 vector __vector_123 vector __vector_124 vector __vector_125 vector __vector_126 vector __vector_127 .endfunc /* Handle unexpected interrupts (enabled and no handler), which usually indicate a bug. Jump to the __vector_default function if defined by the user, otherwise jump to the reset address. This must be in a different section, otherwise the assembler will resolve "rjmp" offsets and there will be no relocs. */ .text .global __bad_interrupt .func __bad_interrupt __bad_interrupt: .weak __vector_default .set __vector_default, __vectors XJMP __vector_default .endfunc .section .init0,"ax",@progbits .weak __init ; .func __init __init: #ifndef __AVR_ASM_ONLY__ .weak __stack /* By default, malloc() uses the current value of the stack pointer minus __malloc_margin as the highest available address. In some applications with external SRAM, the stack can be below the data section (in the internal SRAM - faster), and __heap_end should be set to the highest address available for malloc(). */ .weak __heap_end .set __heap_end, 0 .section .init2,"ax",@progbits clr __zero_reg__ out AVR_STATUS_ADDR, __zero_reg__ ldi r28,lo8(__stack) #ifdef _HAVE_AVR_STACK_POINTER_HI ldi r29,hi8(__stack) out AVR_STACK_POINTER_HI_ADDR, r29 #endif /* _HAVE_AVR_STACK_POINTER_HI */ out AVR_STACK_POINTER_LO_ADDR, r28 #ifdef __AVR_3_BYTE_PC__ ldi r16, hh8(pm(__vectors)) out _SFR_IO_ADDR(EIND), r16 #endif /* __AVR_3_BYTE_PC__ */ #ifdef __AVR_HAVE_RAMPD__ out AVR_RAMPD_ADDR, __zero_reg__ out AVR_RAMPX_ADDR, __zero_reg__ out AVR_RAMPY_ADDR, __zero_reg__ out AVR_RAMPZ_ADDR, __zero_reg__ #endif #if defined(__GNUC__) && ((__GNUC__ <= 3) || (__GNUC__ == 4 && __GNUC_MINOR__ <= 3)) #if BIG_CODE /* Only for >64K devices with RAMPZ, replaces the default code provided by libgcc.S which is only linked in if necessary. */ .section .init4,"ax",@progbits .global __do_copy_data __do_copy_data: ldi r17, hi8(__data_end) ldi r26, lo8(__data_start) ldi r27, hi8(__data_start) ldi r30, lo8(__data_load_start) ldi r31, hi8(__data_load_start) /* On the enhanced core, "elpm" with post-increment updates RAMPZ automatically. Otherwise we have to handle it ourselves. */ #ifdef __AVR_ENHANCED__ ldi r16, hh8(__data_load_start) #else ldi r16, hh8(__data_load_start - 0x10000) .L__do_copy_data_carry: inc r16 #endif out AVR_RAMPZ_ADDR, r16 rjmp .L__do_copy_data_start .L__do_copy_data_loop: #ifdef __AVR_ENHANCED__ elpm r0, Z+ #else elpm #endif st X+, r0 #ifndef __AVR_ENHANCED__ adiw r30, 1 brcs .L__do_copy_data_carry #endif .L__do_copy_data_start: cpi r26, lo8(__data_end) cpc r27, r17 brne .L__do_copy_data_loop #ifdef __AVR_HAVE_RAMPD__ out AVR_RAMPZ_ADDR, __zero_reg__ #endif /* __AVR_HAVE_RAMPD__*/ #endif /* BIG_CODE */ #endif /* defined(__GNUC__) && ((__GNUC__ <= 3) || (__GNUC__ == 4 && __GNUC_MINOR__ <= 3)) */ .set __stack, RAMEND #endif /* !__AVR_ASM_ONLY__ */ .section .init9,"ax",@progbits #ifdef __AVR_ASM_ONLY__ XJMP main #else /* !__AVR_ASM_ONLY__ */ XCALL main XJMP exit #endif /* __AVR_ASM_ONLY__ */ ; .endfunc avr-libc-1.8.0.orig/crt1/Makefile.am0000644000000000000000000000262711732702554013766 0ustar # Copyright (c) 2004, Theodore A. Roth # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in # the documentation and/or other materials provided with the # distribution. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # $Id: Makefile.am 802 2005-08-11 20:55:26Z joerg_wunsch $ # EXTRA_DIST = gcrt1.S