debian/0000755000000000000000000000000012213511030007152 5ustar debian/avra.install0000644000000000000000000000003312176632343011512 0ustar includes/* usr/share/avra/ debian/avra.docs0000644000000000000000000000001712205735277011001 0ustar doc/README.txt debian/source/0000755000000000000000000000000012172652264010475 5ustar debian/source/format0000644000000000000000000000001412172652264011703 0ustar 3.0 (quilt) debian/patches/0000755000000000000000000000000012213433723010615 5ustar debian/patches/tn4-5-9-10def.inc.patch0000644000000000000000000006302212212231413014312 0ustar Description: Add header files for ATtiny4, ATtiny5, ATtiny9 and ATtiny10 Author: Milan Kupcevic Bug: http://sourceforge.net/p/avra/bugs/73/ --- This patch header follows DEP-3: http://dep.debian.net/deps/dep3/ --- /dev/null +++ b/includes/tn10def.inc @@ -0,0 +1,358 @@ +; +; Copyright (C) 2013 Milan Kupcevic +; +; You can redistribute and/or modify this file under the +; terms of the GNU General Public License version 2, or +; (at your option) any later version, as published by +; the Free Software Foundation. +; +; This file is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see . +; +; +; Based on ATtiny4/5/9/10 Datasheet 8127F-AVR-02/2013. +; + +.device ATtiny10 + +.equ SIGNATURE_000 = 0x1e +.equ SIGNATURE_001 = 0x90 +.equ SIGNATURE_002 = 0x03 + +; Port B Input Pins +.equ PINB = 0x00 +.equ PINB0 = 0 +.equ PINB1 = 1 +.equ PINB2 = 2 +.equ PINB3 = 3 + +; Port B Data Direction Register +.equ DDRB = 0x01 +.equ DDRB0 = 0 +.equ DDB0 = 0 +.equ DDRB1 = 1 +.equ DDB1 = 1 +.equ DDRB2 = 2 +.equ DDB2 = 2 +.equ DDRB3 = 3 +.equ DDB3 = 3 + +; Port B Data Register +.equ PORTB = 0x02 +.equ PORTB0 = 0 +.equ PB0 = 0 +.equ PORTB1 = 1 +.equ PB1 = 1 +.equ PORTB2 = 2 +.equ PB2 = 2 +.equ PORTB3 = 3 +.equ PB3 = 3 + +; Port B Pull-up Enable Control Register +.equ PUEB = 0x03 +.equ PUEB0 = 0 +.equ PUEB1 = 1 +.equ PUEB2 = 2 +.equ PUEB3 = 3 + +; Port Control Register +.equ PORTCR = 0x0c +.equ BBMB = 1 + +; Pin Change Mask Register +.equ PCMSK = 0x10 +.equ PCINT0 = 0 +.equ PCINT1 = 1 +.equ PCINT2 = 2 +.equ PCINT3 = 3 + +; Pin Change Interrupt Flag Register +.equ PCIFR = 0x11 +.equ PCIF0 = 0 + +; Pin Change Interrupt Control Register +.equ PCICR = 0x12 +.equ PCIE0 = 0 + +; External Interrupt Mask Register +.equ EIMSK = 0x13 +.equ INT0 = 0 + +; External Interrupt Flag Register +.equ EIFR = 0x14 +.equ INTF0 = 0 + +; External Interrupt Control Register A +.equ EICRA = 0x15 +.equ ISC00 = 0 +.equ ISC01 = 1 + +; Digital Input Disable Register 0 +.equ DIDR0 = 0x17 +.equ ADC0D = 0 +.equ AIN0D = 0 +.equ ADC1D = 1 +.equ AIN1D = 1 +.equ ADC2D = 2 +.equ ADC3D = 3 + +; ADC Data Register +.equ ADCL = 0x19 +.equ ADC0 = 0 +.equ ADC1 = 1 +.equ ADC2 = 2 +.equ ADC3 = 3 +.equ ADC4 = 4 +.equ ADC5 = 5 +.equ ADC6 = 6 +.equ ADC7 = 7 + +; ADC Multiplexer Selection Register +.equ ADMUX = 0x1b +.equ MUX0 = 0 +.equ MUX1 = 1 + +; ADC Control and Status Register B +.equ ADCSRB = 0x1c +.equ ADTS0 = 0 +.equ ADTS1 = 1 +.equ ADTS2 = 2 + +; ADC Control and Status Register A +.equ ADCSRA = 0x1d +.equ ADPS0 = 0 +.equ ADPS1 = 1 +.equ ADPS2 = 2 +.equ ADIE = 3 +.equ ADIF = 4 +.equ ADATE = 5 +.equ ADSC = 6 +.equ ADEN = 7 + +; Analog Comparator Control and Status Register +.equ ACSR = 0x1f +.equ ACIS0 = 0 +.equ ACIS1 = 1 +.equ ACIC = 2 +.equ ACIE = 3 +.equ ACI = 4 +.equ ACO = 5 +.equ ACD = 7 + +; Input Capture Register 0 +.equ ICR0L = 0x22 +.equ ICR0H = 0x23 + +; Output Compare Register 0 B +.equ OCR0BL = 0x24 +.equ OCR0BH = 0x25 + +; Output Compare Register 0 A +.equ OCR0AL = 0x26 +.equ OCR0AH = 0x27 + +; Timer/Counter0 +.equ TCNT0L = 0x28 +.equ TCNT0H = 0x29 + +; Timer/Counter Interrupt Flag Register 0 +.equ TIFR0 = 0x2a +.equ TOV0 = 0 +.equ OCF0A = 1 +.equ OCF0B = 2 +.equ ICF0 = 5 + +; Timer/Counter Interrupt Mask Register 0 +.equ TIMSK0 = 0x2b +.equ TOIE0 = 0 +.equ OCIE0A = 1 +.equ OCIE0B = 2 +.equ ICIE0 = 5 + +; Timer/Counter0 Control Register C +.equ TCCR0C = 0x2c +.equ FOC0B = 6 +.equ FOC0A = 7 + +; Timer/Counter0 Control Register B +.equ TCCR0B = 0x2d +.equ CS00 = 0 +.equ CS01 = 1 +.equ CS02 = 2 +.equ WGM02 = 3 +.equ WGM03 = 4 +.equ ICES0 = 6 +.equ ICNC0 = 7 + +; Timer/Counter0 Control Register A +.equ TCCR0A = 0x2e +.equ WGM00 = 0 +.equ WGM01 = 1 +.equ COM0B0 = 4 +.equ COM0B1 = 5 +.equ COM0A0 = 6 +.equ COM0A1 = 7 + +; General Timer/Counter Control Register +.equ GTCCR = 0x2f +.equ PSR = 0 +.equ TSM = 7 + +; Watchdog Timer Control and Status Register +.equ WDTCSR = 0x31 +.equ WDP0 = 0 +.equ WDP1 = 1 +.equ WDP2 = 2 +.equ WDE = 3 +.equ WDP3 = 5 +.equ WDIE = 6 +.equ WDIF = 7 + +; Non-Volatile Memory Control and Status Register +.equ NVMCSR = 0x32 +.equ NVMBSY = 7 + +; Non-Volatile Memory Command Register +.equ NVMCMD = 0x33 +.equ NVMCMD0 = 0 +.equ NVMCMD1 = 1 +.equ NVMCMD2 = 2 +.equ NVMCMD3 = 3 +.equ NVMCMD4 = 4 +.equ NVMCMD5 = 5 + +; Vcc Level Monitoring Control and Status Register +.equ VLMCSR = 0x34 +.equ VLM0 = 0 +.equ VLM1 = 1 +.equ VLM2 = 2 +.equ VLMIE = 6 +.equ VLMF = 7 + +; Power Reduction Register +.equ PRR = 0x35 +.equ PRTIM0 = 0 +.equ PRADC = 1 + +; Clock Prescale Register +.equ CLKPSR = 0x36 +.equ CLKPS0 = 0 +.equ CLKPS1 = 1 +.equ CLKPS2 = 2 +.equ CLKPS3 = 3 + +; Clock Main Settings Register +.equ CLKMSR = 0x37 +.equ CLKMS0 = 0 +.equ CLKMS1 = 1 + +; Oscillator Calibration Register +.equ OSCCAL = 0x39 +.equ CAL0 = 0 +.equ CAL1 = 1 +.equ CAL2 = 2 +.equ CAL3 = 3 +.equ CAL4 = 4 +.equ CAL5 = 5 +.equ CAL6 = 6 +.equ CAL7 = 7 + +; Sleep Mode Control Register +.equ SMCR = 0x3a +.equ SE = 0 +.equ SM0 = 1 +.equ SM1 = 2 +.equ SM2 = 3 + +; Reset Flag Register +.equ RSTFLR = 0x3b +.equ PORF = 0 +.equ EXTRF = 1 +.equ WDRF = 3 + +; Configuration Change Protection Register +.equ CCP = 0x3c +.equ CCP0 = 0 +.equ CCP1 = 1 +.equ CCP2 = 2 +.equ CCP3 = 3 +.equ CCP4 = 4 +.equ CCP5 = 5 +.equ CCP6 = 6 +.equ CCP7 = 7 + +; Stack Pointer Register +.equ SPL = 0x3d +.equ SPH = 0x3e + +; Status Register +.equ SREG = 0x3f +.equ SREG_C = 0 +.equ SREG_Z = 1 +.equ SREG_N = 2 +.equ SREG_V = 3 +.equ SREG_S = 4 +.equ SREG_H = 5 +.equ SREG_T = 6 +.equ SREG_I = 7 + +; Indirect address registers +.def XL = r26 +.def XH = r27 +.def YL = r28 +.def YH = r29 +.def ZL = r30 +.def ZH = r31 + +; Non-Volatile Memory Lock Bits +.equ MAPPED_LOCKBITS_0 = 0x3f00 +.equ NVLB1 = 0 +.equ LB1 = 0 +.equ NVLB2 = 1 +.equ LB2 = 1 + +; Flash Memory +.equ PAGESIZE = 16 +.equ FLASHEND = 0x01ff +.equ MAPPED_FLASH_START = 0x4000 +.equ MAPPED_FLASH_SIZE = 0x0400 +.equ MAPPED_FLASH_END = 0x43ff + +; RAM Memory +.equ IOEND = 0x003f +.equ RAMEND = 0x005f +.equ SRAM_START = 0x0040 +.equ SRAM_SIZE = 32 + +; Configuration +.equ MAPPED_CONFIG_0 = 0x3f40 +.equ RSTDISBL = 0 +.equ WDTON = 1 +.equ CKOUT = 2 + +; Calibration +.equ MAPPED_CALIB_0 = 0x3f80 + +; Signature +.equ MAPPED_SIGN_0 = 0x3fc0 +.equ MAPPED_SIGN_1 = 0x3fc1 +.equ MAPPED_SIGN_2 = 0x3fc2 + +; Interrupt Vectors +.equ INT_VECTORS_SIZE = 11 +.equ INT0addr = 0x0001 +.equ PCI0addr = 0x0002 +.equ ICP0addr = 0x0003 +.equ OVF0addr = 0x0004 +.equ OC0Aaddr = 0x0005 +.equ OC0Baddr = 0x0006 +.equ ACIaddr = 0x0007 +.equ WDTaddr = 0x0008 +.equ VLMaddr = 0x0009 +.equ ADCCaddr = 0x000a + --- /dev/null +++ b/includes/tn4def.inc @@ -0,0 +1,320 @@ +; +; Copyright (C) 2013 Milan Kupcevic +; +; You can redistribute and/or modify this file under the +; terms of the GNU General Public License version 2, or +; (at your option) any later version, as published by +; the Free Software Foundation. +; +; This file is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see . +; +; +; Based on ATtiny4/5/9/10 Datasheet 8127F-AVR-02/2013. +; + +.device ATtiny4 + +.equ SIGNATURE_000 = 0x1e +.equ SIGNATURE_001 = 0x8f +.equ SIGNATURE_002 = 0x0a + +; Port B Input Pins +.equ PINB = 0x00 +.equ PINB0 = 0 +.equ PINB1 = 1 +.equ PINB2 = 2 +.equ PINB3 = 3 + +; Port B Data Direction Register +.equ DDRB = 0x01 +.equ DDRB0 = 0 +.equ DDB0 = 0 +.equ DDRB1 = 1 +.equ DDB1 = 1 +.equ DDRB2 = 2 +.equ DDB2 = 2 +.equ DDRB3 = 3 +.equ DDB3 = 3 + +; Port B Data Register +.equ PORTB = 0x02 +.equ PORTB0 = 0 +.equ PB0 = 0 +.equ PORTB1 = 1 +.equ PB1 = 1 +.equ PORTB2 = 2 +.equ PB2 = 2 +.equ PORTB3 = 3 +.equ PB3 = 3 + +; Port B Pull-up Enable Control Register +.equ PUEB = 0x03 +.equ PUEB0 = 0 +.equ PUEB1 = 1 +.equ PUEB2 = 2 +.equ PUEB3 = 3 + +; Port Control Register +.equ PORTCR = 0x0c +.equ BBMB = 1 + +; Pin Change Mask Register +.equ PCMSK = 0x10 +.equ PCINT0 = 0 +.equ PCINT1 = 1 +.equ PCINT2 = 2 +.equ PCINT3 = 3 + +; Pin Change Interrupt Flag Register +.equ PCIFR = 0x11 +.equ PCIF0 = 0 + +; Pin Change Interrupt Control Register +.equ PCICR = 0x12 +.equ PCIE0 = 0 + +; External Interrupt Mask Register +.equ EIMSK = 0x13 +.equ INT0 = 0 + +; External Interrupt Flag Register +.equ EIFR = 0x14 +.equ INTF0 = 0 + +; External Interrupt Control Register A +.equ EICRA = 0x15 +.equ ISC00 = 0 +.equ ISC01 = 1 + +; Digital Input Disable Register 0 +.equ DIDR0 = 0x17 +.equ AIN0D = 0 +.equ AIN1D = 1 + +; Analog Comparator Control and Status Register +.equ ACSR = 0x1f +.equ ACIS0 = 0 +.equ ACIS1 = 1 +.equ ACIC = 2 +.equ ACIE = 3 +.equ ACI = 4 +.equ ACO = 5 +.equ ACD = 7 + +; Input Capture Register 0 +.equ ICR0L = 0x22 +.equ ICR0H = 0x23 + +; Output Compare Register 0 B +.equ OCR0BL = 0x24 +.equ OCR0BH = 0x25 + +; Output Compare Register 0 A +.equ OCR0AL = 0x26 +.equ OCR0AH = 0x27 + +; Timer/Counter0 +.equ TCNT0L = 0x28 +.equ TCNT0H = 0x29 + +; Timer/Counter Interrupt Flag Register 0 +.equ TIFR0 = 0x2a +.equ TOV0 = 0 +.equ OCF0A = 1 +.equ OCF0B = 2 +.equ ICF0 = 5 + +; Timer/Counter Interrupt Mask Register 0 +.equ TIMSK0 = 0x2b +.equ TOIE0 = 0 +.equ OCIE0A = 1 +.equ OCIE0B = 2 +.equ ICIE0 = 5 + +; Timer/Counter0 Control Register C +.equ TCCR0C = 0x2c +.equ FOC0B = 6 +.equ FOC0A = 7 + +; Timer/Counter0 Control Register B +.equ TCCR0B = 0x2d +.equ CS00 = 0 +.equ CS01 = 1 +.equ CS02 = 2 +.equ WGM02 = 3 +.equ WGM03 = 4 +.equ ICES0 = 6 +.equ ICNC0 = 7 + +; Timer/Counter0 Control Register A +.equ TCCR0A = 0x2e +.equ WGM00 = 0 +.equ WGM01 = 1 +.equ COM0B0 = 4 +.equ COM0B1 = 5 +.equ COM0A0 = 6 +.equ COM0A1 = 7 + +; General Timer/Counter Control Register +.equ GTCCR = 0x2f +.equ PSR = 0 +.equ TSM = 7 + +; Watchdog Timer Control and Status Register +.equ WDTCSR = 0x31 +.equ WDP0 = 0 +.equ WDP1 = 1 +.equ WDP2 = 2 +.equ WDE = 3 +.equ WDP3 = 5 +.equ WDIE = 6 +.equ WDIF = 7 + +; Non-Volatile Memory Control and Status Register +.equ NVMCSR = 0x32 +.equ NVMBSY = 7 + +; Non-Volatile Memory Command Register +.equ NVMCMD = 0x33 +.equ NVMCMD0 = 0 +.equ NVMCMD1 = 1 +.equ NVMCMD2 = 2 +.equ NVMCMD3 = 3 +.equ NVMCMD4 = 4 +.equ NVMCMD5 = 5 + +; Vcc Level Monitoring Control and Status Register +.equ VLMCSR = 0x34 +.equ VLM0 = 0 +.equ VLM1 = 1 +.equ VLM2 = 2 +.equ VLMIE = 6 +.equ VLMF = 7 + +; Power Reduction Register +.equ PRR = 0x35 +.equ PRTIM0 = 0 +.equ PRADC = 1 + +; Clock Prescale Register +.equ CLKPSR = 0x36 +.equ CLKPS0 = 0 +.equ CLKPS1 = 1 +.equ CLKPS2 = 2 +.equ CLKPS3 = 3 + +; Clock Main Settings Register +.equ CLKMSR = 0x37 +.equ CLKMS0 = 0 +.equ CLKMS1 = 1 + +; Oscillator Calibration Register +.equ OSCCAL = 0x39 +.equ CAL0 = 0 +.equ CAL1 = 1 +.equ CAL2 = 2 +.equ CAL3 = 3 +.equ CAL4 = 4 +.equ CAL5 = 5 +.equ CAL6 = 6 +.equ CAL7 = 7 + +; Sleep Mode Control Register +.equ SMCR = 0x3a +.equ SE = 0 +.equ SM0 = 1 +.equ SM1 = 2 +.equ SM2 = 3 + +; Reset Flag Register +.equ RSTFLR = 0x3b +.equ PORF = 0 +.equ EXTRF = 1 +.equ WDRF = 3 + +; Configuration Change Protection Register +.equ CCP = 0x3c +.equ CCP0 = 0 +.equ CCP1 = 1 +.equ CCP2 = 2 +.equ CCP3 = 3 +.equ CCP4 = 4 +.equ CCP5 = 5 +.equ CCP6 = 6 +.equ CCP7 = 7 + +; Stack Pointer Register +.equ SPL = 0x3d +.equ SPH = 0x3e + +; Status Register +.equ SREG = 0x3f +.equ SREG_C = 0 +.equ SREG_Z = 1 +.equ SREG_N = 2 +.equ SREG_V = 3 +.equ SREG_S = 4 +.equ SREG_H = 5 +.equ SREG_T = 6 +.equ SREG_I = 7 + +; Indirect address registers +.def XL = r26 +.def XH = r27 +.def YL = r28 +.def YH = r29 +.def ZL = r30 +.def ZH = r31 + +; Non-Volatile Memory Lock Bits +.equ MAPPED_LOCKBITS_0 = 0x3f00 +.equ NVLB1 = 0 +.equ LB1 = 0 +.equ NVLB2 = 1 +.equ LB2 = 1 + +; Flash Memory +.equ PAGESIZE = 16 +.equ FLASHEND = 0x00ff +.equ MAPPED_FLASH_START = 0x4000 +.equ MAPPED_FLASH_SIZE = 0x0200 +.equ MAPPED_FLASH_END = 0x41ff + +; RAM Memory +.equ IOEND = 0x003f +.equ RAMEND = 0x005f +.equ SRAM_START = 0x0040 +.equ SRAM_SIZE = 32 + +; Configuration +.equ MAPPED_CONFIG_0 = 0x3f40 +.equ RSTDISBL = 0 +.equ WDTON = 1 +.equ CKOUT = 2 + +; Calibration +.equ MAPPED_CALIB_0 = 0x3f80 + +; Signature +.equ MAPPED_SIGN_0 = 0x3fc0 +.equ MAPPED_SIGN_1 = 0x3fc1 +.equ MAPPED_SIGN_2 = 0x3fc2 + +; Interrupt Vectors +.equ INT_VECTORS_SIZE = 10 +.equ INT0addr = 0x0001 +.equ PCI0addr = 0x0002 +.equ ICP0addr = 0x0003 +.equ OVF0addr = 0x0004 +.equ OC0Aaddr = 0x0005 +.equ OC0Baddr = 0x0006 +.equ ACIaddr = 0x0007 +.equ WDTaddr = 0x0008 +.equ VLMaddr = 0x0009 + --- /dev/null +++ b/includes/tn5def.inc @@ -0,0 +1,358 @@ +; +; Copyright (C) 2013 Milan Kupcevic +; +; You can redistribute and/or modify this file under the +; terms of the GNU General Public License version 2, or +; (at your option) any later version, as published by +; the Free Software Foundation. +; +; This file is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see . +; +; +; Based on ATtiny4/5/9/10 Datasheet 8127F-AVR-02/2013. +; + +.device ATtiny5 + +.equ SIGNATURE_000 = 0x1e +.equ SIGNATURE_001 = 0x8f +.equ SIGNATURE_002 = 0x09 + +; Port B Input Pins +.equ PINB = 0x00 +.equ PINB0 = 0 +.equ PINB1 = 1 +.equ PINB2 = 2 +.equ PINB3 = 3 + +; Port B Data Direction Register +.equ DDRB = 0x01 +.equ DDRB0 = 0 +.equ DDB0 = 0 +.equ DDRB1 = 1 +.equ DDB1 = 1 +.equ DDRB2 = 2 +.equ DDB2 = 2 +.equ DDRB3 = 3 +.equ DDB3 = 3 + +; Port B Data Register +.equ PORTB = 0x02 +.equ PORTB0 = 0 +.equ PB0 = 0 +.equ PORTB1 = 1 +.equ PB1 = 1 +.equ PORTB2 = 2 +.equ PB2 = 2 +.equ PORTB3 = 3 +.equ PB3 = 3 + +; Port B Pull-up Enable Control Register +.equ PUEB = 0x03 +.equ PUEB0 = 0 +.equ PUEB1 = 1 +.equ PUEB2 = 2 +.equ PUEB3 = 3 + +; Port Control Register +.equ PORTCR = 0x0c +.equ BBMB = 1 + +; Pin Change Mask Register +.equ PCMSK = 0x10 +.equ PCINT0 = 0 +.equ PCINT1 = 1 +.equ PCINT2 = 2 +.equ PCINT3 = 3 + +; Pin Change Interrupt Flag Register +.equ PCIFR = 0x11 +.equ PCIF0 = 0 + +; Pin Change Interrupt Control Register +.equ PCICR = 0x12 +.equ PCIE0 = 0 + +; External Interrupt Mask Register +.equ EIMSK = 0x13 +.equ INT0 = 0 + +; External Interrupt Flag Register +.equ EIFR = 0x14 +.equ INTF0 = 0 + +; External Interrupt Control Register A +.equ EICRA = 0x15 +.equ ISC00 = 0 +.equ ISC01 = 1 + +; Digital Input Disable Register 0 +.equ DIDR0 = 0x17 +.equ ADC0D = 0 +.equ AIN0D = 0 +.equ ADC1D = 1 +.equ AIN1D = 1 +.equ ADC2D = 2 +.equ ADC3D = 3 + +; ADC Data Register +.equ ADCL = 0x19 +.equ ADC0 = 0 +.equ ADC1 = 1 +.equ ADC2 = 2 +.equ ADC3 = 3 +.equ ADC4 = 4 +.equ ADC5 = 5 +.equ ADC6 = 6 +.equ ADC7 = 7 + +; ADC Multiplexer Selection Register +.equ ADMUX = 0x1b +.equ MUX0 = 0 +.equ MUX1 = 1 + +; ADC Control and Status Register B +.equ ADCSRB = 0x1c +.equ ADTS0 = 0 +.equ ADTS1 = 1 +.equ ADTS2 = 2 + +; ADC Control and Status Register A +.equ ADCSRA = 0x1d +.equ ADPS0 = 0 +.equ ADPS1 = 1 +.equ ADPS2 = 2 +.equ ADIE = 3 +.equ ADIF = 4 +.equ ADATE = 5 +.equ ADSC = 6 +.equ ADEN = 7 + +; Analog Comparator Control and Status Register +.equ ACSR = 0x1f +.equ ACIS0 = 0 +.equ ACIS1 = 1 +.equ ACIC = 2 +.equ ACIE = 3 +.equ ACI = 4 +.equ ACO = 5 +.equ ACD = 7 + +; Input Capture Register 0 +.equ ICR0L = 0x22 +.equ ICR0H = 0x23 + +; Output Compare Register 0 B +.equ OCR0BL = 0x24 +.equ OCR0BH = 0x25 + +; Output Compare Register 0 A +.equ OCR0AL = 0x26 +.equ OCR0AH = 0x27 + +; Timer/Counter0 +.equ TCNT0L = 0x28 +.equ TCNT0H = 0x29 + +; Timer/Counter Interrupt Flag Register 0 +.equ TIFR0 = 0x2a +.equ TOV0 = 0 +.equ OCF0A = 1 +.equ OCF0B = 2 +.equ ICF0 = 5 + +; Timer/Counter Interrupt Mask Register 0 +.equ TIMSK0 = 0x2b +.equ TOIE0 = 0 +.equ OCIE0A = 1 +.equ OCIE0B = 2 +.equ ICIE0 = 5 + +; Timer/Counter0 Control Register C +.equ TCCR0C = 0x2c +.equ FOC0B = 6 +.equ FOC0A = 7 + +; Timer/Counter0 Control Register B +.equ TCCR0B = 0x2d +.equ CS00 = 0 +.equ CS01 = 1 +.equ CS02 = 2 +.equ WGM02 = 3 +.equ WGM03 = 4 +.equ ICES0 = 6 +.equ ICNC0 = 7 + +; Timer/Counter0 Control Register A +.equ TCCR0A = 0x2e +.equ WGM00 = 0 +.equ WGM01 = 1 +.equ COM0B0 = 4 +.equ COM0B1 = 5 +.equ COM0A0 = 6 +.equ COM0A1 = 7 + +; General Timer/Counter Control Register +.equ GTCCR = 0x2f +.equ PSR = 0 +.equ TSM = 7 + +; Watchdog Timer Control and Status Register +.equ WDTCSR = 0x31 +.equ WDP0 = 0 +.equ WDP1 = 1 +.equ WDP2 = 2 +.equ WDE = 3 +.equ WDP3 = 5 +.equ WDIE = 6 +.equ WDIF = 7 + +; Non-Volatile Memory Control and Status Register +.equ NVMCSR = 0x32 +.equ NVMBSY = 7 + +; Non-Volatile Memory Command Register +.equ NVMCMD = 0x33 +.equ NVMCMD0 = 0 +.equ NVMCMD1 = 1 +.equ NVMCMD2 = 2 +.equ NVMCMD3 = 3 +.equ NVMCMD4 = 4 +.equ NVMCMD5 = 5 + +; Vcc Level Monitoring Control and Status Register +.equ VLMCSR = 0x34 +.equ VLM0 = 0 +.equ VLM1 = 1 +.equ VLM2 = 2 +.equ VLMIE = 6 +.equ VLMF = 7 + +; Power Reduction Register +.equ PRR = 0x35 +.equ PRTIM0 = 0 +.equ PRADC = 1 + +; Clock Prescale Register +.equ CLKPSR = 0x36 +.equ CLKPS0 = 0 +.equ CLKPS1 = 1 +.equ CLKPS2 = 2 +.equ CLKPS3 = 3 + +; Clock Main Settings Register +.equ CLKMSR = 0x37 +.equ CLKMS0 = 0 +.equ CLKMS1 = 1 + +; Oscillator Calibration Register +.equ OSCCAL = 0x39 +.equ CAL0 = 0 +.equ CAL1 = 1 +.equ CAL2 = 2 +.equ CAL3 = 3 +.equ CAL4 = 4 +.equ CAL5 = 5 +.equ CAL6 = 6 +.equ CAL7 = 7 + +; Sleep Mode Control Register +.equ SMCR = 0x3a +.equ SE = 0 +.equ SM0 = 1 +.equ SM1 = 2 +.equ SM2 = 3 + +; Reset Flag Register +.equ RSTFLR = 0x3b +.equ PORF = 0 +.equ EXTRF = 1 +.equ WDRF = 3 + +; Configuration Change Protection Register +.equ CCP = 0x3c +.equ CCP0 = 0 +.equ CCP1 = 1 +.equ CCP2 = 2 +.equ CCP3 = 3 +.equ CCP4 = 4 +.equ CCP5 = 5 +.equ CCP6 = 6 +.equ CCP7 = 7 + +; Stack Pointer Register +.equ SPL = 0x3d +.equ SPH = 0x3e + +; Status Register +.equ SREG = 0x3f +.equ SREG_C = 0 +.equ SREG_Z = 1 +.equ SREG_N = 2 +.equ SREG_V = 3 +.equ SREG_S = 4 +.equ SREG_H = 5 +.equ SREG_T = 6 +.equ SREG_I = 7 + +; Indirect address registers +.def XL = r26 +.def XH = r27 +.def YL = r28 +.def YH = r29 +.def ZL = r30 +.def ZH = r31 + +; Non-Volatile Memory Lock Bits +.equ MAPPED_LOCKBITS_0 = 0x3f00 +.equ NVLB1 = 0 +.equ LB1 = 0 +.equ NVLB2 = 1 +.equ LB2 = 1 + +; Flash Memory +.equ PAGESIZE = 16 +.equ FLASHEND = 0x00ff +.equ MAPPED_FLASH_START = 0x4000 +.equ MAPPED_FLASH_SIZE = 0x0200 +.equ MAPPED_FLASH_END = 0x41ff + +; RAM Memory +.equ IOEND = 0x003f +.equ RAMEND = 0x005f +.equ SRAM_START = 0x0040 +.equ SRAM_SIZE = 32 + +; Configuration +.equ MAPPED_CONFIG_0 = 0x3f40 +.equ RSTDISBL = 0 +.equ WDTON = 1 +.equ CKOUT = 2 + +; Calibration +.equ MAPPED_CALIB_0 = 0x3f80 + +; Signature +.equ MAPPED_SIGN_0 = 0x3fc0 +.equ MAPPED_SIGN_1 = 0x3fc1 +.equ MAPPED_SIGN_2 = 0x3fc2 + +; Interrupt Vectors +.equ INT_VECTORS_SIZE = 11 +.equ INT0addr = 0x0001 +.equ PCI0addr = 0x0002 +.equ ICP0addr = 0x0003 +.equ OVF0addr = 0x0004 +.equ OC0Aaddr = 0x0005 +.equ OC0Baddr = 0x0006 +.equ ACIaddr = 0x0007 +.equ WDTaddr = 0x0008 +.equ VLMaddr = 0x0009 +.equ ADCCaddr = 0x000a + --- /dev/null +++ b/includes/tn9def.inc @@ -0,0 +1,320 @@ +; +; Copyright (C) 2013 Milan Kupcevic +; +; You can redistribute and/or modify this file under the +; terms of the GNU General Public License version 2, or +; (at your option) any later version, as published by +; the Free Software Foundation. +; +; This file is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see . +; +; +; Based on ATtiny4/5/9/10 Datasheet 8127F-AVR-02/2013. +; + +.device ATtiny9 + +.equ SIGNATURE_000 = 0x1e +.equ SIGNATURE_001 = 0x90 +.equ SIGNATURE_002 = 0x08 + +; Port B Input Pins +.equ PINB = 0x00 +.equ PINB0 = 0 +.equ PINB1 = 1 +.equ PINB2 = 2 +.equ PINB3 = 3 + +; Port B Data Direction Register +.equ DDRB = 0x01 +.equ DDRB0 = 0 +.equ DDB0 = 0 +.equ DDRB1 = 1 +.equ DDB1 = 1 +.equ DDRB2 = 2 +.equ DDB2 = 2 +.equ DDRB3 = 3 +.equ DDB3 = 3 + +; Port B Data Register +.equ PORTB = 0x02 +.equ PORTB0 = 0 +.equ PB0 = 0 +.equ PORTB1 = 1 +.equ PB1 = 1 +.equ PORTB2 = 2 +.equ PB2 = 2 +.equ PORTB3 = 3 +.equ PB3 = 3 + +; Port B Pull-up Enable Control Register +.equ PUEB = 0x03 +.equ PUEB0 = 0 +.equ PUEB1 = 1 +.equ PUEB2 = 2 +.equ PUEB3 = 3 + +; Port Control Register +.equ PORTCR = 0x0c +.equ BBMB = 1 + +; Pin Change Mask Register +.equ PCMSK = 0x10 +.equ PCINT0 = 0 +.equ PCINT1 = 1 +.equ PCINT2 = 2 +.equ PCINT3 = 3 + +; Pin Change Interrupt Flag Register +.equ PCIFR = 0x11 +.equ PCIF0 = 0 + +; Pin Change Interrupt Control Register +.equ PCICR = 0x12 +.equ PCIE0 = 0 + +; External Interrupt Mask Register +.equ EIMSK = 0x13 +.equ INT0 = 0 + +; External Interrupt Flag Register +.equ EIFR = 0x14 +.equ INTF0 = 0 + +; External Interrupt Control Register A +.equ EICRA = 0x15 +.equ ISC00 = 0 +.equ ISC01 = 1 + +; Digital Input Disable Register 0 +.equ DIDR0 = 0x17 +.equ AIN0D = 0 +.equ AIN1D = 1 + +; Analog Comparator Control and Status Register +.equ ACSR = 0x1f +.equ ACIS0 = 0 +.equ ACIS1 = 1 +.equ ACIC = 2 +.equ ACIE = 3 +.equ ACI = 4 +.equ ACO = 5 +.equ ACD = 7 + +; Input Capture Register 0 +.equ ICR0L = 0x22 +.equ ICR0H = 0x23 + +; Output Compare Register 0 B +.equ OCR0BL = 0x24 +.equ OCR0BH = 0x25 + +; Output Compare Register 0 A +.equ OCR0AL = 0x26 +.equ OCR0AH = 0x27 + +; Timer/Counter0 +.equ TCNT0L = 0x28 +.equ TCNT0H = 0x29 + +; Timer/Counter Interrupt Flag Register 0 +.equ TIFR0 = 0x2a +.equ TOV0 = 0 +.equ OCF0A = 1 +.equ OCF0B = 2 +.equ ICF0 = 5 + +; Timer/Counter Interrupt Mask Register 0 +.equ TIMSK0 = 0x2b +.equ TOIE0 = 0 +.equ OCIE0A = 1 +.equ OCIE0B = 2 +.equ ICIE0 = 5 + +; Timer/Counter0 Control Register C +.equ TCCR0C = 0x2c +.equ FOC0B = 6 +.equ FOC0A = 7 + +; Timer/Counter0 Control Register B +.equ TCCR0B = 0x2d +.equ CS00 = 0 +.equ CS01 = 1 +.equ CS02 = 2 +.equ WGM02 = 3 +.equ WGM03 = 4 +.equ ICES0 = 6 +.equ ICNC0 = 7 + +; Timer/Counter0 Control Register A +.equ TCCR0A = 0x2e +.equ WGM00 = 0 +.equ WGM01 = 1 +.equ COM0B0 = 4 +.equ COM0B1 = 5 +.equ COM0A0 = 6 +.equ COM0A1 = 7 + +; General Timer/Counter Control Register +.equ GTCCR = 0x2f +.equ PSR = 0 +.equ TSM = 7 + +; Watchdog Timer Control and Status Register +.equ WDTCSR = 0x31 +.equ WDP0 = 0 +.equ WDP1 = 1 +.equ WDP2 = 2 +.equ WDE = 3 +.equ WDP3 = 5 +.equ WDIE = 6 +.equ WDIF = 7 + +; Non-Volatile Memory Control and Status Register +.equ NVMCSR = 0x32 +.equ NVMBSY = 7 + +; Non-Volatile Memory Command Register +.equ NVMCMD = 0x33 +.equ NVMCMD0 = 0 +.equ NVMCMD1 = 1 +.equ NVMCMD2 = 2 +.equ NVMCMD3 = 3 +.equ NVMCMD4 = 4 +.equ NVMCMD5 = 5 + +; Vcc Level Monitoring Control and Status Register +.equ VLMCSR = 0x34 +.equ VLM0 = 0 +.equ VLM1 = 1 +.equ VLM2 = 2 +.equ VLMIE = 6 +.equ VLMF = 7 + +; Power Reduction Register +.equ PRR = 0x35 +.equ PRTIM0 = 0 +.equ PRADC = 1 + +; Clock Prescale Register +.equ CLKPSR = 0x36 +.equ CLKPS0 = 0 +.equ CLKPS1 = 1 +.equ CLKPS2 = 2 +.equ CLKPS3 = 3 + +; Clock Main Settings Register +.equ CLKMSR = 0x37 +.equ CLKMS0 = 0 +.equ CLKMS1 = 1 + +; Oscillator Calibration Register +.equ OSCCAL = 0x39 +.equ CAL0 = 0 +.equ CAL1 = 1 +.equ CAL2 = 2 +.equ CAL3 = 3 +.equ CAL4 = 4 +.equ CAL5 = 5 +.equ CAL6 = 6 +.equ CAL7 = 7 + +; Sleep Mode Control Register +.equ SMCR = 0x3a +.equ SE = 0 +.equ SM0 = 1 +.equ SM1 = 2 +.equ SM2 = 3 + +; Reset Flag Register +.equ RSTFLR = 0x3b +.equ PORF = 0 +.equ EXTRF = 1 +.equ WDRF = 3 + +; Configuration Change Protection Register +.equ CCP = 0x3c +.equ CCP0 = 0 +.equ CCP1 = 1 +.equ CCP2 = 2 +.equ CCP3 = 3 +.equ CCP4 = 4 +.equ CCP5 = 5 +.equ CCP6 = 6 +.equ CCP7 = 7 + +; Stack Pointer Register +.equ SPL = 0x3d +.equ SPH = 0x3e + +; Status Register +.equ SREG = 0x3f +.equ SREG_C = 0 +.equ SREG_Z = 1 +.equ SREG_N = 2 +.equ SREG_V = 3 +.equ SREG_S = 4 +.equ SREG_H = 5 +.equ SREG_T = 6 +.equ SREG_I = 7 + +; Indirect address registers +.def XL = r26 +.def XH = r27 +.def YL = r28 +.def YH = r29 +.def ZL = r30 +.def ZH = r31 + +; Non-Volatile Memory Lock Bits +.equ MAPPED_LOCKBITS_0 = 0x3f00 +.equ NVLB1 = 0 +.equ LB1 = 0 +.equ NVLB2 = 1 +.equ LB2 = 1 + +; Flash Memory +.equ PAGESIZE = 16 +.equ FLASHEND = 0x01ff +.equ MAPPED_FLASH_START = 0x4000 +.equ MAPPED_FLASH_SIZE = 0x0400 +.equ MAPPED_FLASH_END = 0x43ff + +; RAM Memory +.equ IOEND = 0x003f +.equ RAMEND = 0x005f +.equ SRAM_START = 0x0040 +.equ SRAM_SIZE = 32 + +; Configuration +.equ MAPPED_CONFIG_0 = 0x3f40 +.equ RSTDISBL = 0 +.equ WDTON = 1 +.equ CKOUT = 2 + +; Calibration +.equ MAPPED_CALIB_0 = 0x3f80 + +; Signature +.equ MAPPED_SIGN_0 = 0x3fc0 +.equ MAPPED_SIGN_1 = 0x3fc1 +.equ MAPPED_SIGN_2 = 0x3fc2 + +; Interrupt Vectors +.equ INT_VECTORS_SIZE = 10 +.equ INT0addr = 0x0001 +.equ PCI0addr = 0x0002 +.equ ICP0addr = 0x0003 +.equ OVF0addr = 0x0004 +.equ OC0Aaddr = 0x0005 +.equ OC0Baddr = 0x0006 +.equ ACIaddr = 0x0007 +.equ WDTaddr = 0x0008 +.equ VLMaddr = 0x0009 + debian/patches/series0000644000000000000000000000012512212231413012017 0ustar AVR8L-plus-attiny20-git-b13b7c.patch attiny4-5-9-10src.patch tn4-5-9-10def.inc.patch debian/patches/AVR8L-plus-attiny20-git-b13b7c.patch0000644000000000000000000001632112212234616016665 0ustar Description: Add support for ATtiny20 with AVR8L instructions Origin: backport, http://sf.net/p/avra/code/ci/b13b7c --- This patch header follows DEP-3: http://dep.debian.net/deps/dep3/ --- a/src/avra.h +++ b/src/avra.h @@ -305,7 +305,7 @@ /* mnemonic.c */ int parse_mnemonic(struct prog_info *pi); -int get_mnemonic_type(char *mnemonic); +int get_mnemonic_type(struct prog_info *pi); int get_register(struct prog_info *pi, char *data); int get_bitnum(struct prog_info *pi, char *data, int *ret); int get_indirect(struct prog_info *pi, char *operand); --- a/src/device.c +++ b/src/device.c @@ -58,7 +58,7 @@ { "ATtiny13", 512, 0x60, 64, 64, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, { "ATtiny13A", 512, 0x60, 64, 64, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, { "ATtiny15", 512, 0x00, 0, 64, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, - // ATtiny20 + { "ATtiny20", 2048, 0x40, 128, 0, DF_AVR8L|DF_NO_JMP|DF_NO_MUL|DF_NO_EIJMP|DF_NO_EICALL|DF_NO_MOVW|DF_NO_LPM|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_BREAK}, { "ATtiny22", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, { "ATtiny24", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, { "ATtiny24A", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, --- a/src/device.h +++ b/src/device.h @@ -16,6 +16,7 @@ #define DF_NO_BREAK 0x00001000 // No BREAK instruction #define DF_NO_EICALL 0x00002000 // No EICALL instruction #define DF_NO_EIJMP 0x00004000 // No EIJMP instruction +#define DF_AVR8L 0x00008000 /* ATtiny10, 20, 40 set No ADIW, SBIW, one word LDS/STS */ struct device { --- a/src/mnemonic.c +++ b/src/mnemonic.c @@ -179,6 +179,8 @@ MNEMONIC_LDD_Z, // Rd, Z+q 10q0 qq0d dddd 0qqq MNEMONIC_STD_Y, // Y+q, Rr 10q0 qq1r rrrr 1qqq MNEMONIC_STD_Z, // Z+q, Rr 10q0 qq1r rrrr 0qqq + MNEMONIC_LDS_AVR8L,// Rd, k 1010 0kkk dddd kkkk + MNEMONIC_STS_AVR8L,// Rd, k 1010 1kkk dddd kkkk MNEMONIC_END }; @@ -279,8 +281,8 @@ {"fmul", 0x0308, DF_NO_MUL}, {"fmuls", 0x0380, DF_NO_MUL}, {"fmulsu",0x0388, DF_NO_MUL}, - {"adiw", 0x9600, DF_TINY1X}, - {"sbiw", 0x9700, DF_TINY1X}, + {"adiw", 0x9600, DF_TINY1X | DF_AVR8L}, + {"sbiw", 0x9700, DF_TINY1X | DF_AVR8L}, {"subi", 0x5000, 0}, {"sbci", 0x4000, 0}, {"andi", 0x7000, 0}, @@ -299,8 +301,8 @@ {"sbis", 0x9b00, 0}, {"sbi", 0x9a00, 0}, {"cbi", 0x9800, 0}, - {"lds", 0x9000, DF_TINY1X}, - {"sts", 0x9200, DF_TINY1X}, + {"lds", 0x9000, DF_TINY1X | DF_AVR8L}, + {"sts", 0x9200, DF_TINY1X | DF_AVR8L}, {"ld", 0, 0}, {"st", 0, 0}, {"ldd", 0, DF_TINY1X}, @@ -332,6 +334,8 @@ {"ldd", 0x8000, DF_TINY1X}, {"std", 0x8208, DF_TINY1X}, {"std", 0x8200, DF_TINY1X}, + {"lds", 0xa000, DF_TINY1X}, + {"sts", 0xa800, DF_TINY1X}, {"end", 0, 0} }; @@ -353,7 +357,7 @@ char temp[MAX_MNEMONIC_LEN + 1]; operand1 = get_next_token(pi->fi->scratch, TERM_SPACE); // we get the first word on line - mnemonic = get_mnemonic_type(my_strlwr(pi->fi->scratch)); + mnemonic = get_mnemonic_type(pi); if(mnemonic == -1) { // if -1 this must be a macro name macro = get_macro(pi, pi->fi->scratch); // and so, we try to get the corresponding macro struct. if(macro) { @@ -539,21 +543,44 @@ } else if(mnemonic == MNEMONIC_LDS) { i = get_register(pi, operand1); opcode = i << 4; + /* AVR8L has one word LDS. High nibble of k in funny order */ + if (pi->device->flag & DF_AVR8L) { + mnemonic = MNEMONIC_LDS_AVR8L; + opcode &= 0x00f0; + } if(!get_expr(pi, operand2, &i)) return(False); - if((i < 0) || (i > 65535)) - print_msg(pi, MSGTYPE_ERROR, "SRAM out of range (0 <= k <= 65535)"); - opcode2 = i; - instruction_long = True; + if (pi->device->flag & DF_AVR8L) { + if((i < 0x40) || (i > 0xbf)) + print_msg(pi, MSGTYPE_ERROR, "SRAM out of range (0x40 <= k <= 0xbf)"); + opcode |= ((i & 0x40) << 2) | ((i & 0x30) << 5) | (i & 0x0f); + } else { + if((i < 0) || (i > 65535)) + print_msg(pi, MSGTYPE_ERROR, "SRAM out of range (0 <= k <= 65535)"); + opcode2 = i; + instruction_long = True; + } } else if(mnemonic == MNEMONIC_STS) { if(!get_expr(pi, operand1, &i)) return(False); - if((i < 0) || (i > 65535)) - print_msg(pi, MSGTYPE_ERROR, "SRAM out of range (0 <= k <= 65535)"); - opcode2 = i; + /* AVR8L has one word STS. High nibble of k in funny order */ + if (pi->device->flag & DF_AVR8L) { + mnemonic = MNEMONIC_STS_AVR8L; + if((i < 0x40) || (i > 0xbf)) + print_msg(pi, MSGTYPE_ERROR, "SRAM out of range (0x40 <= k <= 0xbf)"); + opcode |= ((i & 0x40) << 2) | ((i & 0x30) << 5) | (i & 0x0f); + } else { + if((i < 0) || (i > 65535)) + print_msg(pi, MSGTYPE_ERROR, "SRAM out of range (0 <= k <= 65535)"); + opcode2 = i; + instruction_long = True; + } i = get_register(pi, operand2); - opcode = i << 4; - instruction_long = True; + if (pi->device->flag & DF_AVR8L) + opcode |= ((i << 4) & 0x00f0); + else + opcode = i << 4; + //print_msg(pi, MSGTYPE_MESSAGE, "operand2 0x%04x opcode 0x%04x", i, opcode); } else if(mnemonic == MNEMONIC_LD) { i = get_register(pi, operand1); opcode = i << 4; @@ -628,6 +655,8 @@ else pi->cseg_addr++; } else { // Pass 1 + if (pi->device->flag & DF_AVR8L) + mnemonic = MNEMONIC_LDS_AVR8L; if((mnemonic == MNEMONIC_JMP) || (mnemonic == MNEMONIC_CALL) || (mnemonic == MNEMONIC_LDS) || (mnemonic == MNEMONIC_STS)) { pi->cseg_addr += 2; @@ -640,10 +669,12 @@ return(True); } - -int get_mnemonic_type(char *mnemonic) +int get_mnemonic_type(struct prog_info *pi) { int i; + char *mnemonic; + + mnemonic = my_strlwr(pi->fi->scratch); for(i = 0; i < MNEMONIC_COUNT; i++) { if(!strcmp(mnemonic, instruction_list[i].mnemonic)) { @@ -675,6 +706,8 @@ reg = atoi(&data[1]); if(reg > 31) print_msg(pi, MSGTYPE_ERROR, "R%d is not a valid register", reg); + if ((reg < 16) && (pi->device->flag & DF_AVR8L)) + print_msg(pi, MSGTYPE_ERROR, "%s can only use a high registers (r16 - r31)", pi->device->name); } else print_msg(pi, MSGTYPE_ERROR, "No register associated with %s", data); @@ -767,11 +800,10 @@ /* Return 1 if instruction name is supported by the current device, 0 if unsupported, -1 if it is invalid */ int is_supported(struct prog_info *pi, char *name) { - char temp[MAX_MNEMONIC_LEN+1]; int mnemonic; - strncpy(temp,name,MAX_MNEMONIC_LEN); - mnemonic = get_mnemonic_type(my_strlwr(temp)); + strncpy(pi->fi->scratch,name,MAX_MNEMONIC_LEN); + mnemonic = get_mnemonic_type(pi); if (mnemonic == -1) return -1; if (pi->device->flag & instruction_list[mnemonic].flag) return 0; return 1; debian/patches/attiny4-5-9-10src.patch0000644000000000000000000000662412212231413014467 0ustar Description: Add support for ATtiny4, ATtiny5, ATtiny9 and ATtiny10 Support for ATtiny4, ATtiny5, ATtiny9 and ATtiny10 microcontrollers based on ATtiny4/5/9/10 Datasheet 8127F-AVR-02/2013. Author: Milan Kupcevic Bug: http://sourceforge.net/p/avra/bugs/73/ --- This patch header follows DEP-3: http://dep.debian.net/deps/dep3/ --- a/src/device.c +++ b/src/device.c @@ -49,10 +49,10 @@ /* Name, Flash(words),RAM start, RAM size, EEPROM, flags */ { NULL, 4194304, 0x60, 8388608, 65536, 0}, // Total instructions: 137 /* ATtiny Series */ - // ATtiny4 - // ATtiny5 - // ATtiny9 - { "ATtiny10", 512, 0x00, 0, 0, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, + { "ATtiny4", 256, 0x40, 32, 0, DF_AVR8L|DF_NO_MUL|DF_NO_JMP|DF_NO_LPM|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_EICALL|DF_NO_EIJMP|DF_NO_LDD|DF_NO_STD}, + { "ATtiny5", 256, 0x40, 32, 0, DF_AVR8L|DF_NO_MUL|DF_NO_JMP|DF_NO_LPM|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_EICALL|DF_NO_EIJMP|DF_NO_LDD|DF_NO_STD}, + { "ATtiny9", 512, 0x40, 32, 0, DF_AVR8L|DF_NO_MUL|DF_NO_JMP|DF_NO_LPM|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_EICALL|DF_NO_EIJMP|DF_NO_LDD|DF_NO_STD}, + { "ATtiny10", 512, 0x40, 32, 0, DF_AVR8L|DF_NO_MUL|DF_NO_JMP|DF_NO_LPM|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_EICALL|DF_NO_EIJMP|DF_NO_LDD|DF_NO_STD}, { "ATtiny11", 512, 0x00, 0, 0, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, { "ATtiny12", 512, 0x00, 0, 64, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, { "ATtiny13", 512, 0x60, 64, 64, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, --- a/src/device.h +++ b/src/device.h @@ -17,6 +17,8 @@ #define DF_NO_EICALL 0x00002000 // No EICALL instruction #define DF_NO_EIJMP 0x00004000 // No EIJMP instruction #define DF_AVR8L 0x00008000 /* ATtiny10, 20, 40 set No ADIW, SBIW, one word LDS/STS */ +#define DF_NO_LDD 0x00010000 // No LDD instruction +#define DF_NO_STD 0x00020000 // No STD instruction struct device { --- a/src/mnemonic.c +++ b/src/mnemonic.c @@ -305,8 +305,8 @@ {"sts", 0x9200, DF_TINY1X | DF_AVR8L}, {"ld", 0, 0}, {"st", 0, 0}, - {"ldd", 0, DF_TINY1X}, - {"std", 0, DF_TINY1X}, + {"ldd", 0, DF_TINY1X|DF_NO_LDD}, + {"std", 0, DF_TINY1X|DF_NO_STD}, {"count", 0, 0}, {"lpm", 0x9004, DF_NO_LPM|DF_NO_LPM_X}, {"lpm", 0x9005, DF_NO_LPM|DF_NO_LPM_X}, @@ -330,10 +330,10 @@ {"st", 0x8200, 0}, {"st", 0x9201, DF_TINY1X}, {"st", 0x9202, DF_TINY1X}, - {"ldd", 0x8008, DF_TINY1X}, - {"ldd", 0x8000, DF_TINY1X}, - {"std", 0x8208, DF_TINY1X}, - {"std", 0x8200, DF_TINY1X}, + {"ldd", 0x8008, DF_TINY1X|DF_NO_LDD}, + {"ldd", 0x8000, DF_TINY1X|DF_NO_LDD}, + {"std", 0x8208, DF_TINY1X|DF_NO_STD}, + {"std", 0x8200, DF_TINY1X|DF_NO_STD}, {"lds", 0xa000, DF_TINY1X}, {"sts", 0xa800, DF_TINY1X}, {"end", 0, 0} debian/copyright0000644000000000000000000000560312213511030011111 0ustar Format: http://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: AVRA Source: http://avra.sf.net License: GPL-2+ Files: * Copyright: 1998-2003, 2004, 2006, 2010 Jon Anders Haugum, Tobias Weber License: GPL-2+ Files: src/device.c Copyright: 1998-2010 Jon Anders Haugum, Tobias Weber, Jerry Jacobs License: GPL-2+ Files: src/configure Copyright: 2003 Free Software Foundation, Inc. License: unlimited This configure script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. Files: src/Makefile.in Copyright: 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. License: permissive This Makefile.in is free software; the Free Software Foundation gives unlimited permission to copy and/or distribute it, with or without modifications, as long as this notice is preserved. . This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY, to the extent permitted by law; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Files: src/stab.h Copyright: 1990 by Sun Microsystems, Inc Comment: Contains interface definitions. Copyright on interface definitions is widely regarded as not enforceable. License: unknown Files: includes/* Copyright: 2005 by Atmel Comment: Contains interface definitions. Copyright on interface definitions is widely regarded as not enforceable. License: unknown License: unknown License terms not specified. Files: examples/* Copyright: 2003 Philip DeVries License: GPL-2+ Files: debian/* Copyright: 1999, 2000, 2003 Jefferson E. Noxon 2005 Torsten Landschoff 2007, 2010 Tobias Klauser 2013 Milan Kupcevic License: GPL-2+ Files: debian/patches/* Copyright: 2013 Milan Kupcevic License: GPL-2+ Files: debian/avra.1 Copyright: 2006 Robert Lemmen Comment: This file was contributed to this package by its author as a fix to bug #360577. We can assume the authors intention was to distribute the file under the same licensing terms as the software package itself. License: GPL-2+ License: GPL-2+ This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. . This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. . On Debian systems, the full text of the GNU General Public License version 2 can be found in the file /usr/share/common-licenses/GPL-2 debian/rules0000755000000000000000000000041512205735403010247 0ustar #!/usr/bin/make -f export DH_VERBOSE=1 %: dh $@ --sourcedirectory=src override_dh_auto_configure: cd src; AUTOMAKE="automake --foreign" autoreconf -i dh_auto_configure --sourcedirectory=src override_dh_installchangelogs: dh_installchangelogs doc/ChangeLog.html debian/avra.examples0000644000000000000000000000001312172654373011663 0ustar examples/* debian/compat0000644000000000000000000000000212205730737010372 0ustar 9 debian/avra.10000644000000000000000000000546712205736057010224 0ustar .TH avra 1 "May 8, 2010" "Atmel AVR Assembler" "Atmel AVR Assembler" .SH NAME avra - Assembler for the Atmel AVR microcontroller family .SH SYNOPSIS .B avra [\fB\-f\fR] [\fBO\fR|\fBM\fR|\fBI\fR|\fBG\fR\fR] output file type [\fB\-o\fR \fIoutfile\fR] output file name [\fB\-l\fR \fIlistfile\fR] generate list file [\fB\-m\fR \fImapfile\fR] generate map file [\fB\-\-define\fR \fIsymbol[=value]\fR] [\fB\-\-includepath\fR \fIpath\fR] [\fB\-listmac\fR] [\fB\-\-max_errors\fR \fInumber\fR] [\fB\-\-devices\fR] [\fB\-\-version\fR] [\fB\-h\fR] [\fB\-\-help\fR] general help \fIinfile\fR .SH DESCRIPTION \fBAVRA\fR is an assembler for Atmel AVR microcontrollers, and it is almost compatible with Atmel's own assembler AVRASM32. The differences between the two are: .IP "Support for some extra preprocessor directives." includes: .define, .undef, .ifdef, .ifndef, .if, .else, .endif, .elif, .elseif, .warning .IP "Not all command line options are supported." Specifying an eeprom file (\-e) is not supported. All eeprom data is put out into a file called program.eep.hex and always Intel hex format. Other hex file formats than Intel are currently not supported. .IP "Forward references are not supported." Like in C, you have to define everything before you are using it, excepting labels. This makes sure, that directives like .ifdef and .undef are working properly. If you are familiar with the C programming language, you should get easily into \fBAVRA\fR. See chapter "Programming techniques" for more information about how to write proper code. .IP "Enhanced macro support." \fBAVRA\fR has some new features for writing flexible macros. This should increase the ability to reuse code e.g. build your own library. .IP "Debugging support." \fBAVRA\fR creates a coff file everytime the assembly was sucessful. This file allows AVR Studio or any coff compatible debugger to simulate or emulate the program. .IP "Meta tags for assembly time." This helps you tracking versions of your software and can also be used to generate customer specific serial numbers. .SH OPTIONS Several option can be given after one '\-', but if an option requires an argument; the argument must be given after that option. .TP .B \-\-listfile, \-l Create list file .TP .B \-\-mapfile, \-m Create map file .TP .B \-\-define, \-D Define symbol. .TP .B \-\-includepath, \-I Additional include paths. .TP .B \-\-listmac List macro expansion in listfile. .TP .B \-\-max_errors Maximum number of errors before exit (default: 10) .TP .B \-\-devices List out supported devices. .TP .B \-\-version Version information. .TP .B \-\-help, \-h Show summary of options. .SH "SEE ALSO" .BR avrp (1) .SH AUTHOR The initial version of AVRA was written by John Anders Haugum. He released all versions until v0.7. Later versions were released by Tobias Weber. Version 1.3.0 was released by Jerry Jacobs. debian/watch0000644000000000000000000000012112212673556010222 0ustar version=3 http://sf.net/avra/ avra-([[:alnum:]\.]*)(?:-src|)\.tar\.(?:gz|bz2|xz) debian/avra.manpages0000644000000000000000000000001612176614270011637 0ustar debian/avra.1 debian/changelog0000644000000000000000000000636212213507331011044 0ustar avra (1.3.0-1) unstable; urgency=low * New upstream release (closes: #588507) - fixes invalid comment characters (closes: #668631) * New maintainer (closes: #691906) * Transform source format to 3.0 (quilt) * Update standards version to 3.9.4 * Bump debhelper compatibility to 9 * Remove Vcs-Git and Vcs-Browser control fields. * debian/rules, debian/copyright, debian/watch, debian/avra.examples: Rewrite. * debian/avra.1, debian/control: Update. * debian/avra.manpages, debian/avra.install, debian/avra.docs: New files. * Backport support for ATtiny20 with AVR8L. * Add support and header files for ATtiny4, ATtiny5, ATtiny9 and ATtiny10. -- Milan Kupcevic Mon, 09 Sep 2013 23:15:14 -0400 avra (1.2.3a-1) unstable; urgency=low * New upstream release (closes: #507443). - Fixes address range error (closes: #527978). * Install register and bit-name definitions from AVR000.zip. * Update standards version to 3.8.3. * Use new Homepage control field. * Add Vcs-Git and Vcs-Browser control fields. * Change maintainer's email address. -- Tobias Klauser Wed, 20 Jan 2010 15:24:49 +0100 avra (1.2.2-1) unstable; urgency=low * New upstream release * Depends on automake1.9 now, regenerated autotools files (01-autotools.dpatch) * Update debhelper compatibility level from 4 to 5 * Do not ignore error messages in the clean target of debian/rules -- Tobias Klauser Sat, 18 Aug 2007 14:19:48 +0200 avra (1.2.1-1) unstable; urgency=low * New upstream release (Closes: #314784) * Add watch file -- Tobias Klauser Sun, 14 Jan 2007 16:48:00 +0100 avra (1.0.1-1) unstable; urgency=low * New maintainer (Closes: #404467) * Add manpage for avra (Closes: #360577). Thanks to Robert Lemmen * Update standards version -- Tobias Klauser Mon, 1 Jan 2007 15:14:40 +0100 avra (1.0.1-0.1) unstable; urgency=low * NMU. * New upstream release including new device types that I need... * SOURCE/Makefile: Fix upstream version to 1.0.1. * debian/rules (build,clean,install): Adjust for new Makefile and sources location. -- Torsten Landschoff Wed, 29 Jun 2005 11:04:43 +0200 avra (0.7-1) unstable; urgency=low * New upstream version (closes: Bug#181858) * Updated author's website address & copyright details -- Jefferson E. Noxon Tue, 25 Feb 2003 14:10:40 -0600 avra (0.5-1) unstable; urgency=low * New upstream version * Added Build-Depends (closes: Bug#70139). -- Jefferson E. Noxon Sun, 5 Nov 2000 15:19:57 -0600 avra (0.4-2) unstable; urgency=low * Updated author's web, e-mail, and postal addresses * Updated to comply with debian-policy 3.0.1.1 * Upload now contains pristine upstream source & patches (Fixes #44219) -- Jefferson E. Noxon Tue, 14 Sep 1999 23:14:48 -0500 avra (0.4-1) unstable; urgency=low * Upgraded to new upstream version. * Compiled with glibc 2.1 -- Jefferson E. Noxon Sun, 4 Apr 1999 11:03:50 -0500 avra (0.2-1) unstable; urgency=low * Initial Release. -- Jefferson E. Noxon Mon, 28 Sep 1998 14:01:38 -0500 debian/control0000644000000000000000000000115012213417572010572 0ustar Source: avra Section: electronics Priority: extra Maintainer: Milan Kupcevic Build-Depends: debhelper (>= 9.0.0), autoconf, automake Standards-Version: 3.9.4 Homepage: http://avra.sourceforge.net Package: avra Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends} Suggests: avrdude, avrprog, avrp Description: assembler for Atmel AVR microcontrollers Avra is an assembler for the Atmel's family of AVR 8-bit RISC microcontrollers. It is mostly compatible with Atmel's own assembler, but adds new features such as better macro support and additional preprocessor directives.